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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.49 96.18 85.48 89.91 72.50 88.33 97.90 54.13


Total test records in report: 467
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T125 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1556727108 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:40 PM PDT 24 240203840 ps
T316 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1241262642 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:39 PM PDT 24 2171332044 ps
T77 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1668206957 Aug 02 04:45:55 PM PDT 24 Aug 02 04:46:23 PM PDT 24 1301188470 ps
T88 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1751858142 Aug 02 04:45:46 PM PDT 24 Aug 02 04:45:48 PM PDT 24 3120650991 ps
T317 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4259406361 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:39 PM PDT 24 1621016121 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3706162670 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:03 PM PDT 24 187699229 ps
T319 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3649043435 Aug 02 04:46:32 PM PDT 24 Aug 02 04:46:43 PM PDT 24 8084746713 ps
T119 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2253753434 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:45 PM PDT 24 3177633219 ps
T126 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.963453770 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:45 PM PDT 24 1128140685 ps
T78 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3374379428 Aug 02 04:45:48 PM PDT 24 Aug 02 04:45:49 PM PDT 24 48460352 ps
T63 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1665986864 Aug 02 04:45:48 PM PDT 24 Aug 02 04:45:50 PM PDT 24 207453488 ps
T320 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1052116661 Aug 02 04:46:17 PM PDT 24 Aug 02 04:46:22 PM PDT 24 776517803 ps
T116 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1343275548 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:32 PM PDT 24 7891716740 ps
T64 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3866168168 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:06 PM PDT 24 755559290 ps
T321 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1014182721 Aug 02 04:46:15 PM PDT 24 Aug 02 04:46:20 PM PDT 24 413386707 ps
T79 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1063548196 Aug 02 04:46:22 PM PDT 24 Aug 02 04:46:27 PM PDT 24 538952172 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4288933651 Aug 02 04:45:59 PM PDT 24 Aug 02 04:46:02 PM PDT 24 1220050424 ps
T80 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.445520592 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:41 PM PDT 24 245738951 ps
T81 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1499207037 Aug 02 04:45:46 PM PDT 24 Aug 02 04:45:48 PM PDT 24 619071211 ps
T323 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.36846641 Aug 02 04:46:31 PM PDT 24 Aug 02 04:46:48 PM PDT 24 11833209342 ps
T324 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2093765790 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:38 PM PDT 24 185273430 ps
T325 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.727400389 Aug 02 04:46:12 PM PDT 24 Aug 02 04:46:13 PM PDT 24 169254348 ps
T82 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1213116233 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:26 PM PDT 24 688889970 ps
T120 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1566279020 Aug 02 04:46:01 PM PDT 24 Aug 02 04:46:22 PM PDT 24 12039647275 ps
T83 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.721892099 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:21 PM PDT 24 178590315 ps
T326 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3965773638 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:06 PM PDT 24 352392642 ps
T327 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1345487797 Aug 02 04:46:21 PM PDT 24 Aug 02 04:46:26 PM PDT 24 373409308 ps
T328 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3363694889 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:21 PM PDT 24 935956100 ps
T84 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1603850761 Aug 02 04:45:57 PM PDT 24 Aug 02 04:46:25 PM PDT 24 2982563704 ps
T329 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1161921164 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:40 PM PDT 24 1076889049 ps
T121 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1917679454 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:40 PM PDT 24 146070694 ps
T162 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1478849982 Aug 02 04:46:38 PM PDT 24 Aug 02 04:46:49 PM PDT 24 1037867908 ps
T330 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.982688121 Aug 02 04:46:16 PM PDT 24 Aug 02 04:46:18 PM PDT 24 106667824 ps
T331 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3369683198 Aug 02 04:46:33 PM PDT 24 Aug 02 04:46:38 PM PDT 24 176803242 ps
T85 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2899370255 Aug 02 04:45:59 PM PDT 24 Aug 02 04:46:01 PM PDT 24 180499652 ps
T332 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3922585483 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:20 PM PDT 24 160727863 ps
T333 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2656265087 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:55 PM PDT 24 26250941674 ps
T334 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1705994477 Aug 02 04:46:19 PM PDT 24 Aug 02 04:47:32 PM PDT 24 52895078746 ps
T89 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.163922763 Aug 02 04:45:54 PM PDT 24 Aug 02 04:45:59 PM PDT 24 6001991537 ps
T86 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3581874250 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:22 PM PDT 24 196407459 ps
T91 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.591713930 Aug 02 04:46:15 PM PDT 24 Aug 02 04:46:17 PM PDT 24 160988005 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.422289370 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:05 PM PDT 24 491027392 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2086220803 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:06 PM PDT 24 131050210 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3662326323 Aug 02 04:46:01 PM PDT 24 Aug 02 04:46:02 PM PDT 24 56554474 ps
T164 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1142370212 Aug 02 04:46:15 PM PDT 24 Aug 02 04:46:37 PM PDT 24 6082919248 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3883023321 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:08 PM PDT 24 261190244 ps
T339 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.95151860 Aug 02 04:46:32 PM PDT 24 Aug 02 04:46:35 PM PDT 24 68688770 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.949998988 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:08 PM PDT 24 1152341021 ps
T340 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2477155150 Aug 02 04:46:17 PM PDT 24 Aug 02 04:46:23 PM PDT 24 1686608773 ps
T341 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2801588735 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:37 PM PDT 24 257053527 ps
T342 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.161838471 Aug 02 04:46:04 PM PDT 24 Aug 02 04:46:11 PM PDT 24 4459155499 ps
T92 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2229104110 Aug 02 04:46:16 PM PDT 24 Aug 02 04:46:19 PM PDT 24 110319408 ps
T343 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3541587973 Aug 02 04:45:45 PM PDT 24 Aug 02 04:45:46 PM PDT 24 358590136 ps
T122 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1688545131 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:08 PM PDT 24 210266312 ps
T344 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4114054599 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:19 PM PDT 24 315942619 ps
T60 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.658783689 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:15 PM PDT 24 37470463959 ps
T61 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3848072372 Aug 02 04:46:01 PM PDT 24 Aug 02 04:47:01 PM PDT 24 19640825081 ps
T345 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1047349174 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:39 PM PDT 24 306990457 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3833100067 Aug 02 04:46:00 PM PDT 24 Aug 02 04:46:01 PM PDT 24 543476724 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1414495477 Aug 02 04:46:00 PM PDT 24 Aug 02 04:46:03 PM PDT 24 237958826 ps
T123 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.975300513 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:22 PM PDT 24 325978124 ps
T110 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3336304628 Aug 02 04:45:56 PM PDT 24 Aug 02 04:46:03 PM PDT 24 272838861 ps
T124 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1555022710 Aug 02 04:46:31 PM PDT 24 Aug 02 04:46:34 PM PDT 24 147833070 ps
T347 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3155731409 Aug 02 04:46:22 PM PDT 24 Aug 02 04:47:05 PM PDT 24 17707356608 ps
T348 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4226647606 Aug 02 04:46:22 PM PDT 24 Aug 02 04:46:29 PM PDT 24 4437210500 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3685007875 Aug 02 04:45:59 PM PDT 24 Aug 02 04:46:00 PM PDT 24 118375043 ps
T93 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.398498017 Aug 02 04:46:32 PM PDT 24 Aug 02 04:46:34 PM PDT 24 382698171 ps
T350 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1855002002 Aug 02 04:45:55 PM PDT 24 Aug 02 04:45:56 PM PDT 24 500553947 ps
T351 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2836325566 Aug 02 04:45:45 PM PDT 24 Aug 02 04:45:47 PM PDT 24 700753185 ps
T170 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1544881703 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:23 PM PDT 24 3641896150 ps
T168 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2507731777 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:35 PM PDT 24 2721871085 ps
T352 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3399863969 Aug 02 04:46:32 PM PDT 24 Aug 02 04:46:33 PM PDT 24 243685685 ps
T353 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1932896196 Aug 02 04:45:57 PM PDT 24 Aug 02 04:46:14 PM PDT 24 12235558728 ps
T165 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2338512904 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:28 PM PDT 24 2602765577 ps
T111 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2259303943 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:46 PM PDT 24 3397120015 ps
T354 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.655579915 Aug 02 04:46:30 PM PDT 24 Aug 02 04:46:33 PM PDT 24 209163018 ps
T355 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1539085803 Aug 02 04:46:12 PM PDT 24 Aug 02 04:46:15 PM PDT 24 155269974 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.833762499 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:05 PM PDT 24 2694279066 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.450275259 Aug 02 04:45:46 PM PDT 24 Aug 02 04:45:48 PM PDT 24 281378183 ps
T358 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4085330389 Aug 02 04:45:48 PM PDT 24 Aug 02 04:45:49 PM PDT 24 85808646 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.975601213 Aug 02 04:45:58 PM PDT 24 Aug 02 04:46:02 PM PDT 24 144575970 ps
T94 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.388375186 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:38 PM PDT 24 238722411 ps
T360 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.212374741 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:39 PM PDT 24 894695385 ps
T163 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1909174903 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:16 PM PDT 24 1296314140 ps
T361 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.856445111 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:36 PM PDT 24 299330937 ps
T362 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.454068188 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:21 PM PDT 24 600624176 ps
T363 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2114173687 Aug 02 04:45:57 PM PDT 24 Aug 02 04:46:03 PM PDT 24 10678718339 ps
T112 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1836316328 Aug 02 04:46:22 PM PDT 24 Aug 02 04:46:30 PM PDT 24 1814449101 ps
T364 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3346103163 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:38 PM PDT 24 105595734 ps
T365 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2333555516 Aug 02 04:46:30 PM PDT 24 Aug 02 04:46:33 PM PDT 24 95211114 ps
T366 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3678642537 Aug 02 04:46:36 PM PDT 24 Aug 02 04:49:20 PM PDT 24 61001248015 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1972870996 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:07 PM PDT 24 2546159086 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2953849690 Aug 02 04:46:21 PM PDT 24 Aug 02 04:46:36 PM PDT 24 5738690763 ps
T369 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.320220947 Aug 02 04:46:17 PM PDT 24 Aug 02 04:46:19 PM PDT 24 85428703 ps
T370 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2442824877 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:20 PM PDT 24 367183518 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1960023709 Aug 02 04:46:06 PM PDT 24 Aug 02 04:46:07 PM PDT 24 29968221 ps
T372 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2322378259 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:40 PM PDT 24 3246727596 ps
T174 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4086125296 Aug 02 04:46:18 PM PDT 24 Aug 02 04:47:09 PM PDT 24 32345500019 ps
T169 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.983145584 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:38 PM PDT 24 5994982993 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2336158949 Aug 02 04:45:57 PM PDT 24 Aug 02 04:46:00 PM PDT 24 1103013289 ps
T175 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.970309925 Aug 02 04:46:04 PM PDT 24 Aug 02 04:46:27 PM PDT 24 59019886140 ps
T114 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1751377090 Aug 02 04:46:14 PM PDT 24 Aug 02 04:46:22 PM PDT 24 606325465 ps
T373 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.120598902 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:09 PM PDT 24 576464217 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4118703185 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:22 PM PDT 24 458874965 ps
T375 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3079284722 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:37 PM PDT 24 110504669 ps
T376 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.761149567 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:37 PM PDT 24 361266683 ps
T377 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3984855922 Aug 02 04:46:01 PM PDT 24 Aug 02 04:46:05 PM PDT 24 2051377925 ps
T115 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2360989671 Aug 02 04:46:43 PM PDT 24 Aug 02 04:46:50 PM PDT 24 265898459 ps
T95 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3430523008 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:43 PM PDT 24 201808734 ps
T96 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4064277592 Aug 02 04:45:55 PM PDT 24 Aug 02 04:45:58 PM PDT 24 320888297 ps
T378 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1559685270 Aug 02 04:45:55 PM PDT 24 Aug 02 04:46:01 PM PDT 24 1923402170 ps
T379 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3911420961 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:38 PM PDT 24 144954386 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.955967859 Aug 02 04:46:12 PM PDT 24 Aug 02 04:46:13 PM PDT 24 1295365872 ps
T381 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4162777091 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:35 PM PDT 24 226965018 ps
T166 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3444937104 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:45 PM PDT 24 2437790848 ps
T101 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3565045598 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:38 PM PDT 24 165707213 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.613942320 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:06 PM PDT 24 354249884 ps
T382 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.234239767 Aug 02 04:46:04 PM PDT 24 Aug 02 04:46:06 PM PDT 24 198107035 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2137678817 Aug 02 04:45:54 PM PDT 24 Aug 02 04:46:22 PM PDT 24 1008720027 ps
T102 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2889998267 Aug 02 04:46:31 PM PDT 24 Aug 02 04:46:33 PM PDT 24 152010512 ps
T384 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3963858965 Aug 02 04:46:18 PM PDT 24 Aug 02 04:51:13 PM PDT 24 63522932865 ps
T385 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2511323679 Aug 02 04:46:01 PM PDT 24 Aug 02 04:47:23 PM PDT 24 31722375316 ps
T386 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.875749711 Aug 02 04:45:59 PM PDT 24 Aug 02 04:46:19 PM PDT 24 36356095873 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1395774130 Aug 02 04:45:53 PM PDT 24 Aug 02 04:45:58 PM PDT 24 1784083045 ps
T388 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2209587356 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:04 PM PDT 24 291276773 ps
T171 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.594400991 Aug 02 04:46:38 PM PDT 24 Aug 02 04:46:58 PM PDT 24 2703111395 ps
T389 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.505128910 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:50 PM PDT 24 35394483574 ps
T390 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1461091712 Aug 02 04:45:55 PM PDT 24 Aug 02 04:46:26 PM PDT 24 8415188910 ps
T391 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2506645586 Aug 02 04:46:17 PM PDT 24 Aug 02 04:46:19 PM PDT 24 223337722 ps
T392 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.748828442 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:09 PM PDT 24 4144480841 ps
T104 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1875621460 Aug 02 04:45:49 PM PDT 24 Aug 02 04:46:22 PM PDT 24 8669601529 ps
T393 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.18705484 Aug 02 04:46:33 PM PDT 24 Aug 02 04:46:43 PM PDT 24 8277323419 ps
T394 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2360853349 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:52 PM PDT 24 5507373822 ps
T395 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2786802135 Aug 02 04:45:57 PM PDT 24 Aug 02 04:45:58 PM PDT 24 97544700 ps
T97 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2413400993 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:40 PM PDT 24 365684366 ps
T396 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3380409837 Aug 02 04:46:01 PM PDT 24 Aug 02 04:46:13 PM PDT 24 14543451147 ps
T397 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3490232349 Aug 02 04:46:14 PM PDT 24 Aug 02 04:46:26 PM PDT 24 7575574616 ps
T398 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1294854810 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:21 PM PDT 24 93613247 ps
T399 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2819423012 Aug 02 04:46:36 PM PDT 24 Aug 02 04:46:39 PM PDT 24 473207590 ps
T400 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3189586253 Aug 02 04:45:52 PM PDT 24 Aug 02 04:46:53 PM PDT 24 66849882105 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1055140722 Aug 02 04:45:54 PM PDT 24 Aug 02 04:46:00 PM PDT 24 3600061294 ps
T105 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3381609788 Aug 02 04:46:33 PM PDT 24 Aug 02 04:46:35 PM PDT 24 154476330 ps
T402 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.40788897 Aug 02 04:45:51 PM PDT 24 Aug 02 04:46:46 PM PDT 24 5862199390 ps
T90 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2641184426 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:11 PM PDT 24 2584347556 ps
T403 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4239487126 Aug 02 04:46:00 PM PDT 24 Aug 02 04:46:02 PM PDT 24 274032112 ps
T404 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4014653794 Aug 02 04:46:16 PM PDT 24 Aug 02 04:48:08 PM PDT 24 42236011382 ps
T405 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.427938276 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:38 PM PDT 24 149907388 ps
T172 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3116481987 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:55 PM PDT 24 1773171478 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2294544160 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:08 PM PDT 24 122046662 ps
T407 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.864011995 Aug 02 04:45:59 PM PDT 24 Aug 02 04:46:00 PM PDT 24 504645714 ps
T408 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.141803197 Aug 02 04:46:00 PM PDT 24 Aug 02 04:46:02 PM PDT 24 154240289 ps
T409 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3081806804 Aug 02 04:45:54 PM PDT 24 Aug 02 04:46:16 PM PDT 24 23908631962 ps
T167 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3752584744 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:38 PM PDT 24 5895570464 ps
T410 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2552839064 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:40 PM PDT 24 7729935567 ps
T411 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2649842453 Aug 02 04:46:31 PM PDT 24 Aug 02 04:46:43 PM PDT 24 7538855342 ps
T412 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.361863715 Aug 02 04:46:05 PM PDT 24 Aug 02 04:50:06 PM PDT 24 92411470272 ps
T413 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1172255447 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:06 PM PDT 24 164303305 ps
T106 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4273963379 Aug 02 04:46:29 PM PDT 24 Aug 02 04:46:31 PM PDT 24 189594478 ps
T414 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2270071034 Aug 02 04:45:58 PM PDT 24 Aug 02 04:46:01 PM PDT 24 654650217 ps
T415 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3913892454 Aug 02 04:46:31 PM PDT 24 Aug 02 04:46:54 PM PDT 24 12516199723 ps
T416 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2650485262 Aug 02 04:45:57 PM PDT 24 Aug 02 04:46:00 PM PDT 24 131047994 ps
T417 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2696834118 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:30 PM PDT 24 34015530869 ps
T418 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1962289262 Aug 02 04:46:21 PM PDT 24 Aug 02 04:46:24 PM PDT 24 149614735 ps
T419 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1896977256 Aug 02 04:45:54 PM PDT 24 Aug 02 04:45:56 PM PDT 24 122184363 ps
T420 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1896420890 Aug 02 04:46:01 PM PDT 24 Aug 02 04:46:27 PM PDT 24 22836218011 ps
T421 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2382370479 Aug 02 04:45:46 PM PDT 24 Aug 02 04:45:47 PM PDT 24 68652205 ps
T422 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.375201909 Aug 02 04:45:47 PM PDT 24 Aug 02 04:46:04 PM PDT 24 8508971853 ps
T423 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3969384403 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:03 PM PDT 24 58357734 ps
T424 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.55149854 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:25 PM PDT 24 866090646 ps
T425 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2661863179 Aug 02 04:46:02 PM PDT 24 Aug 02 04:47:05 PM PDT 24 45596649865 ps
T426 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2111022786 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:41 PM PDT 24 2968094804 ps
T427 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3101947427 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:21 PM PDT 24 201544534 ps
T428 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2399633631 Aug 02 04:46:19 PM PDT 24 Aug 02 04:47:01 PM PDT 24 51003949452 ps
T429 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.206690305 Aug 02 04:46:23 PM PDT 24 Aug 02 04:46:25 PM PDT 24 482718515 ps
T430 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.603477294 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:45 PM PDT 24 5019919728 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2972953160 Aug 02 04:45:55 PM PDT 24 Aug 02 04:47:52 PM PDT 24 32785305763 ps
T173 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1343468220 Aug 02 04:45:54 PM PDT 24 Aug 02 04:46:14 PM PDT 24 1401065228 ps
T432 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2399550119 Aug 02 04:46:19 PM PDT 24 Aug 02 04:46:22 PM PDT 24 7476962068 ps
T433 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2807792094 Aug 02 04:45:47 PM PDT 24 Aug 02 04:46:28 PM PDT 24 19811629865 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1855414832 Aug 02 04:46:03 PM PDT 24 Aug 02 04:46:32 PM PDT 24 763321303 ps
T434 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.930071058 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:03 PM PDT 24 28075498 ps
T435 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3084097016 Aug 02 04:46:37 PM PDT 24 Aug 02 04:46:48 PM PDT 24 4029809734 ps
T436 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.822025104 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:09 PM PDT 24 876268030 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1106063258 Aug 02 04:45:48 PM PDT 24 Aug 02 04:45:51 PM PDT 24 726049972 ps
T438 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.131659798 Aug 02 04:46:33 PM PDT 24 Aug 02 04:46:35 PM PDT 24 498005430 ps
T439 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3608530018 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:22 PM PDT 24 301948025 ps
T440 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.407111631 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:05 PM PDT 24 1805431898 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.546357678 Aug 02 04:46:12 PM PDT 24 Aug 02 04:46:45 PM PDT 24 2467540263 ps
T441 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2007810106 Aug 02 04:46:17 PM PDT 24 Aug 02 04:46:18 PM PDT 24 268708749 ps
T442 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1626938581 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:37 PM PDT 24 234179945 ps
T443 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4238503229 Aug 02 04:45:58 PM PDT 24 Aug 02 04:46:02 PM PDT 24 4698718486 ps
T98 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.71976863 Aug 02 04:46:38 PM PDT 24 Aug 02 04:46:42 PM PDT 24 244941307 ps
T444 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3443799932 Aug 02 04:45:52 PM PDT 24 Aug 02 04:46:51 PM PDT 24 65295923685 ps
T445 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3677937203 Aug 02 04:46:12 PM PDT 24 Aug 02 04:46:13 PM PDT 24 221996050 ps
T446 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3688469782 Aug 02 04:46:14 PM PDT 24 Aug 02 04:47:05 PM PDT 24 21743804426 ps
T447 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2384282197 Aug 02 04:46:01 PM PDT 24 Aug 02 04:46:03 PM PDT 24 563415802 ps
T448 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.142964155 Aug 02 04:46:22 PM PDT 24 Aug 02 04:46:26 PM PDT 24 97943700 ps
T449 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3188467339 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:22 PM PDT 24 2090442880 ps
T450 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1467967134 Aug 02 04:46:05 PM PDT 24 Aug 02 04:46:07 PM PDT 24 1154554097 ps
T451 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2776978166 Aug 02 04:45:55 PM PDT 24 Aug 02 04:47:02 PM PDT 24 5027209889 ps
T99 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2858290952 Aug 02 04:46:28 PM PDT 24 Aug 02 04:46:36 PM PDT 24 907689837 ps
T452 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2830459813 Aug 02 04:46:24 PM PDT 24 Aug 02 04:46:29 PM PDT 24 269786039 ps
T453 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3561707140 Aug 02 04:46:20 PM PDT 24 Aug 02 04:46:25 PM PDT 24 3077879215 ps
T454 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2856465639 Aug 02 04:46:34 PM PDT 24 Aug 02 04:46:36 PM PDT 24 124899310 ps
T455 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2805565764 Aug 02 04:45:58 PM PDT 24 Aug 02 04:46:05 PM PDT 24 913490056 ps
T456 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1683555042 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:52 PM PDT 24 14941525189 ps
T457 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3870096318 Aug 02 04:46:02 PM PDT 24 Aug 02 04:46:13 PM PDT 24 9617511852 ps
T458 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2203316155 Aug 02 04:45:58 PM PDT 24 Aug 02 04:46:01 PM PDT 24 106873754 ps
T459 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4003237492 Aug 02 04:46:18 PM PDT 24 Aug 02 04:46:25 PM PDT 24 7329304913 ps
T460 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2814820179 Aug 02 04:46:38 PM PDT 24 Aug 02 04:46:43 PM PDT 24 971378931 ps
T461 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.351566255 Aug 02 04:45:46 PM PDT 24 Aug 02 04:46:08 PM PDT 24 2676224764 ps
T462 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1979408388 Aug 02 04:46:13 PM PDT 24 Aug 02 04:46:15 PM PDT 24 275375806 ps
T463 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1231808445 Aug 02 04:46:12 PM PDT 24 Aug 02 04:46:19 PM PDT 24 2869946603 ps
T464 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3302494100 Aug 02 04:46:21 PM PDT 24 Aug 02 04:46:26 PM PDT 24 289350922 ps
T465 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.437501110 Aug 02 04:46:35 PM PDT 24 Aug 02 04:46:36 PM PDT 24 44395886 ps
T466 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2978293472 Aug 02 04:45:54 PM PDT 24 Aug 02 04:45:55 PM PDT 24 469907126 ps
T467 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2377492833 Aug 02 04:45:55 PM PDT 24 Aug 02 04:46:02 PM PDT 24 847259707 ps

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.2169362269
Short name T7
Test name
Test status
Simulation time 687781836 ps
CPU time 0.95 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205120 kb
Host smart-966e53bd-526f-4bc3-a52c-73453f76abc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169362269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2169362269
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1673319601
Short name T22
Test name
Test status
Simulation time 30008341000 ps
CPU time 498.27 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:55:04 PM PDT 24
Peak memory 232452 kb
Host smart-44dcd667-5d48-4d6c-916b-ec935a74a69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673319601 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1673319601
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3140019871
Short name T23
Test name
Test status
Simulation time 3036431032 ps
CPU time 10.74 seconds
Started Aug 02 04:46:59 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 213836 kb
Host smart-d25f2f3c-ecb8-4570-83f7-415ac9505f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140019871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3140019871
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3568464114
Short name T54
Test name
Test status
Simulation time 1098766418 ps
CPU time 1.65 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 229780 kb
Host smart-81486b0a-abd2-4789-b4b3-9286c39cf5d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568464114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3568464114
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.963453770
Short name T126
Test name
Test status
Simulation time 1128140685 ps
CPU time 10.05 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 213868 kb
Host smart-6af036c9-5e05-4757-bc21-460ae04c6cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963453770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.963453770
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3761916194
Short name T59
Test name
Test status
Simulation time 6814724363 ps
CPU time 5.99 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205448 kb
Host smart-b20bfa12-eb26-4ffb-aec6-a2f6a85308be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761916194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3761916194
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1950673178
Short name T11
Test name
Test status
Simulation time 47353689506 ps
CPU time 1025.07 seconds
Started Aug 02 04:46:49 PM PDT 24
Finished Aug 02 05:03:55 PM PDT 24
Peak memory 233656 kb
Host smart-d5426d9e-f2fd-4aab-b2c6-ddaf47158a19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950673178 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1950673178
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2819161754
Short name T30
Test name
Test status
Simulation time 22266974691 ps
CPU time 22.16 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:47:00 PM PDT 24
Peak memory 213820 kb
Host smart-572b5a22-7990-4bd3-8c1d-ca03039b5fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819161754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2819161754
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.3252787292
Short name T57
Test name
Test status
Simulation time 440985320 ps
CPU time 1.31 seconds
Started Aug 02 04:46:40 PM PDT 24
Finished Aug 02 04:46:41 PM PDT 24
Peak memory 205156 kb
Host smart-e7156fd2-2e83-432c-813d-65b58ac79e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252787292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3252787292
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1759889084
Short name T147
Test name
Test status
Simulation time 19918562574 ps
CPU time 55.79 seconds
Started Aug 02 04:47:08 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 213852 kb
Host smart-78c5b3d5-5a55-4502-9988-136ee5424a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759889084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1759889084
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.3005496585
Short name T49
Test name
Test status
Simulation time 121916049250 ps
CPU time 667.58 seconds
Started Aug 02 04:46:52 PM PDT 24
Finished Aug 02 04:58:00 PM PDT 24
Peak memory 230368 kb
Host smart-61471bec-5f11-4f32-84ab-f4e40e0bf656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005496585 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.3005496585
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.711675801
Short name T127
Test name
Test status
Simulation time 1715934611 ps
CPU time 2.62 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 205376 kb
Host smart-a18b2e00-e0a6-4fda-b761-932921048541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711675801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.711675801
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3581874250
Short name T86
Test name
Test status
Simulation time 196407459 ps
CPU time 1.6 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 213604 kb
Host smart-7775c912-5fa3-411e-b14e-e6e6989020bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581874250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3581874250
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4279792231
Short name T8
Test name
Test status
Simulation time 296137096 ps
CPU time 0.95 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 205176 kb
Host smart-f0c84d87-72e2-41ef-9962-2ded5e454349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279792231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4279792231
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2921644822
Short name T117
Test name
Test status
Simulation time 68935326 ps
CPU time 0.77 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 205228 kb
Host smart-7003d7b8-f972-4d7a-9852-00673aac15cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921644822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2921644822
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.983145584
Short name T169
Test name
Test status
Simulation time 5994982993 ps
CPU time 20.11 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 213824 kb
Host smart-a68f76f5-a7e2-4530-acb6-b4c5e7f9641d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983145584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.983145584
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.875374420
Short name T39
Test name
Test status
Simulation time 55264382 ps
CPU time 0.93 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 213436 kb
Host smart-9880e802-2086-40c4-aa09-06d6bf8b4b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875374420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.875374420
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.873979351
Short name T139
Test name
Test status
Simulation time 122061071817 ps
CPU time 56.6 seconds
Started Aug 02 04:47:00 PM PDT 24
Finished Aug 02 04:47:57 PM PDT 24
Peak memory 215176 kb
Host smart-a7a188dc-e9d7-4acd-a9da-0a508ef82686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873979351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.873979351
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1688639743
Short name T21
Test name
Test status
Simulation time 4780275200 ps
CPU time 6.16 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:08 PM PDT 24
Peak memory 213616 kb
Host smart-0aff5970-97e1-421c-ae29-307f36f07c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688639743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1688639743
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1343468220
Short name T173
Test name
Test status
Simulation time 1401065228 ps
CPU time 19.65 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 213764 kb
Host smart-b9525388-92cc-473e-9a81-314860067dab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343468220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1343468220
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.1735971933
Short name T26
Test name
Test status
Simulation time 105534090 ps
CPU time 0.92 seconds
Started Aug 02 04:46:42 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205176 kb
Host smart-71af2368-bde0-47fa-be25-953036eea5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735971933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1735971933
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2479755148
Short name T246
Test name
Test status
Simulation time 14121125029 ps
CPU time 3.89 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 205764 kb
Host smart-2e237c32-a376-461f-9626-3168ad825fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479755148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2479755148
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1063548196
Short name T79
Test name
Test status
Simulation time 538952172 ps
CPU time 4.59 seconds
Started Aug 02 04:46:22 PM PDT 24
Finished Aug 02 04:46:27 PM PDT 24
Peak memory 205604 kb
Host smart-2a9378f1-9972-42b0-b7ac-ab619443c715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063548196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1063548196
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.658783689
Short name T60
Test name
Test status
Simulation time 37470463959 ps
CPU time 12.47 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 222004 kb
Host smart-17ef6e82-a4ed-4f09-8b21-e969d12cf5a5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658783689 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.658783689
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.479460385
Short name T159
Test name
Test status
Simulation time 1136057366 ps
CPU time 4.21 seconds
Started Aug 02 04:46:43 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 205224 kb
Host smart-cbf36a06-cd6f-46ec-b7bb-f854f995c21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479460385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.479460385
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1730798491
Short name T129
Test name
Test status
Simulation time 3811941891 ps
CPU time 2.79 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 205504 kb
Host smart-95f2f79f-b0ee-47ac-a858-a0f163224984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730798491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1730798491
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2509589955
Short name T152
Test name
Test status
Simulation time 3044637055 ps
CPU time 2.7 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:12 PM PDT 24
Peak memory 213668 kb
Host smart-8a96f7a0-8fc1-491f-8639-b480b77f9569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509589955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2509589955
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3541587973
Short name T343
Test name
Test status
Simulation time 358590136 ps
CPU time 1.17 seconds
Started Aug 02 04:45:45 PM PDT 24
Finished Aug 02 04:45:46 PM PDT 24
Peak memory 205176 kb
Host smart-b7abde12-1580-42f6-9068-a95a6b11155c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541587973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
541587973
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.774208001
Short name T51
Test name
Test status
Simulation time 72937554 ps
CPU time 0.91 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 205152 kb
Host smart-4c67b638-5c0d-4186-a90d-400115279824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774208001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.774208001
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1751858142
Short name T88
Test name
Test status
Simulation time 3120650991 ps
CPU time 1.54 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 205464 kb
Host smart-3f35e43b-a1c3-43a0-988e-9f9ca06de4f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751858142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1751858142
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.869744363
Short name T36
Test name
Test status
Simulation time 406267468 ps
CPU time 1.45 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205120 kb
Host smart-52af18e0-d50e-438b-8834-7c32fde29168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869744363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.869744363
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.315675337
Short name T87
Test name
Test status
Simulation time 4997295941 ps
CPU time 18.18 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 213796 kb
Host smart-18544cf8-9f65-499c-8ccd-4687383fb732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315675337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.315675337
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1909174903
Short name T163
Test name
Test status
Simulation time 1296314140 ps
CPU time 10.39 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:16 PM PDT 24
Peak memory 213704 kb
Host smart-8bd4d654-3cd0-4030-86d2-2363b7b07350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909174903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1909174903
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3374379428
Short name T78
Test name
Test status
Simulation time 48460352 ps
CPU time 1.43 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 213632 kb
Host smart-7aaaa2b7-bc11-4d0d-b97c-e4932f7a6c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374379428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3374379428
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2586649377
Short name T3
Test name
Test status
Simulation time 1027751057 ps
CPU time 1.65 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205536 kb
Host smart-dc931f31-3648-41a2-b9ad-eb470943430c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586649377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2586649377
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1461091712
Short name T390
Test name
Test status
Simulation time 8415188910 ps
CPU time 30.65 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 213668 kb
Host smart-21b2a1eb-027e-4bd1-bf7b-624b969ea2a9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461091712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1461091712
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.40788897
Short name T402
Test name
Test status
Simulation time 5862199390 ps
CPU time 54.41 seconds
Started Aug 02 04:45:51 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 213772 kb
Host smart-b6738b98-af49-4b6a-a144-f93a7fe39680
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40788897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.40788897
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1499207037
Short name T81
Test name
Test status
Simulation time 619071211 ps
CPU time 1.73 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 213756 kb
Host smart-816a3317-82b1-4b5f-8b93-a811d1ad5cf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499207037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1499207037
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1106063258
Short name T437
Test name
Test status
Simulation time 726049972 ps
CPU time 2.61 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:45:51 PM PDT 24
Peak memory 218096 kb
Host smart-a960410b-7a6b-44c6-96db-dd5d7142e31e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106063258 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1106063258
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3443799932
Short name T444
Test name
Test status
Simulation time 65295923685 ps
CPU time 59.16 seconds
Started Aug 02 04:45:52 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 205436 kb
Host smart-469d54e2-1698-43af-adc2-28696421cb85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443799932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3443799932
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1395774130
Short name T387
Test name
Test status
Simulation time 1784083045 ps
CPU time 4.82 seconds
Started Aug 02 04:45:53 PM PDT 24
Finished Aug 02 04:45:58 PM PDT 24
Peak memory 205400 kb
Host smart-df24c7af-f05b-42a9-9d03-5355ad7f7cd8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395774130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1395774130
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1055140722
Short name T401
Test name
Test status
Simulation time 3600061294 ps
CPU time 5.12 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 205520 kb
Host smart-2f7e307e-008e-4ba1-b202-9451744c8a0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055140722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
055140722
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2836325566
Short name T351
Test name
Test status
Simulation time 700753185 ps
CPU time 1.73 seconds
Started Aug 02 04:45:45 PM PDT 24
Finished Aug 02 04:45:47 PM PDT 24
Peak memory 205212 kb
Host smart-ed3a31e8-3ca0-4c60-a7bd-e84301603491
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836325566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2836325566
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.375201909
Short name T422
Test name
Test status
Simulation time 8508971853 ps
CPU time 17.07 seconds
Started Aug 02 04:45:47 PM PDT 24
Finished Aug 02 04:46:04 PM PDT 24
Peak memory 205480 kb
Host smart-8a29ddf8-3661-4334-b172-8750cb5ca036
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375201909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.375201909
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2978293472
Short name T466
Test name
Test status
Simulation time 469907126 ps
CPU time 1.31 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:45:55 PM PDT 24
Peak memory 205312 kb
Host smart-814c2748-85d3-4417-a219-84a628f08658
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978293472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2978293472
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4085330389
Short name T358
Test name
Test status
Simulation time 85808646 ps
CPU time 0.75 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 205252 kb
Host smart-3873edfe-1449-47c3-ae52-b59d4d9a438b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085330389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4085330389
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2382370479
Short name T421
Test name
Test status
Simulation time 68652205 ps
CPU time 0.8 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:45:47 PM PDT 24
Peak memory 205184 kb
Host smart-12414976-ebd0-4e6b-a9ab-8a838c2da3a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382370479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2382370479
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2805565764
Short name T455
Test name
Test status
Simulation time 913490056 ps
CPU time 7.11 seconds
Started Aug 02 04:45:58 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 205512 kb
Host smart-b09c8b53-f887-4b44-8362-ce1068ff8ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805565764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2805565764
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3189586253
Short name T400
Test name
Test status
Simulation time 66849882105 ps
CPU time 61.21 seconds
Started Aug 02 04:45:52 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 226732 kb
Host smart-c3c5ed8f-e707-4596-bc85-cacccb217c21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189586253 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3189586253
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.450275259
Short name T357
Test name
Test status
Simulation time 281378183 ps
CPU time 2.39 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:45:48 PM PDT 24
Peak memory 213836 kb
Host smart-9b92277c-8629-4696-a347-40322f7f83e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450275259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.450275259
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.351566255
Short name T461
Test name
Test status
Simulation time 2676224764 ps
CPU time 22.48 seconds
Started Aug 02 04:45:46 PM PDT 24
Finished Aug 02 04:46:08 PM PDT 24
Peak memory 213680 kb
Host smart-6b2dff46-4688-4ed7-b89f-9a16296f437f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351566255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.351566255
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1875621460
Short name T104
Test name
Test status
Simulation time 8669601529 ps
CPU time 33.23 seconds
Started Aug 02 04:45:49 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 205600 kb
Host smart-46fa62bb-c559-4dcd-bd8e-f046eadf8511
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875621460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1875621460
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1603850761
Short name T84
Test name
Test status
Simulation time 2982563704 ps
CPU time 27.87 seconds
Started Aug 02 04:45:57 PM PDT 24
Finished Aug 02 04:46:25 PM PDT 24
Peak memory 213664 kb
Host smart-fd5c1513-c61d-4d1c-9ca3-ab0733ea74d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603850761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1603850761
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2899370255
Short name T85
Test name
Test status
Simulation time 180499652 ps
CPU time 1.83 seconds
Started Aug 02 04:45:59 PM PDT 24
Finished Aug 02 04:46:01 PM PDT 24
Peak memory 213664 kb
Host smart-231592d1-3fce-4e55-bb4d-42976edb20c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899370255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2899370255
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2203316155
Short name T458
Test name
Test status
Simulation time 106873754 ps
CPU time 2.8 seconds
Started Aug 02 04:45:58 PM PDT 24
Finished Aug 02 04:46:01 PM PDT 24
Peak memory 219164 kb
Host smart-9097624b-c37f-4e00-ace2-6efa93d5bae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203316155 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2203316155
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4239487126
Short name T403
Test name
Test status
Simulation time 274032112 ps
CPU time 1.57 seconds
Started Aug 02 04:46:00 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 213676 kb
Host smart-2f8767ad-b431-4a57-8d7d-9f6cf705de26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239487126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4239487126
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3081806804
Short name T409
Test name
Test status
Simulation time 23908631962 ps
CPU time 21.48 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:46:16 PM PDT 24
Peak memory 205500 kb
Host smart-1385a43f-bc09-4cb5-99f5-09929235865d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081806804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3081806804
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1932896196
Short name T353
Test name
Test status
Simulation time 12235558728 ps
CPU time 16.62 seconds
Started Aug 02 04:45:57 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 205452 kb
Host smart-54606d9b-5917-46e5-8b2b-474f27e9ecd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932896196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1932896196
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1972870996
Short name T367
Test name
Test status
Simulation time 2546159086 ps
CPU time 4.43 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:07 PM PDT 24
Peak memory 205544 kb
Host smart-bd3dbdfa-1b9d-4ef9-b150-93f2093864c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972870996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1972870996
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.833762499
Short name T356
Test name
Test status
Simulation time 2694279066 ps
CPU time 3.07 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 205496 kb
Host smart-3568f94b-e5c7-4af3-8747-a2bfa68de6f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833762499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.833762499
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.407111631
Short name T440
Test name
Test status
Simulation time 1805431898 ps
CPU time 3.03 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 205152 kb
Host smart-eabd7dac-19ef-49be-a2e7-d953518b5de1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407111631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.407111631
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2807792094
Short name T433
Test name
Test status
Simulation time 19811629865 ps
CPU time 41.44 seconds
Started Aug 02 04:45:47 PM PDT 24
Finished Aug 02 04:46:28 PM PDT 24
Peak memory 205564 kb
Host smart-8ebcdcfd-ee2c-4331-be96-f3389889a9cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807792094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2807792094
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1855002002
Short name T350
Test name
Test status
Simulation time 500553947 ps
CPU time 1.17 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:45:56 PM PDT 24
Peak memory 205188 kb
Host smart-6b587def-177e-43e2-aa73-7a338c2f57ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855002002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1855002002
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1665986864
Short name T63
Test name
Test status
Simulation time 207453488 ps
CPU time 1.19 seconds
Started Aug 02 04:45:48 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 205184 kb
Host smart-be7796b0-45b5-4e42-8bd8-ab821a583064
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665986864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
665986864
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2786802135
Short name T395
Test name
Test status
Simulation time 97544700 ps
CPU time 0.91 seconds
Started Aug 02 04:45:57 PM PDT 24
Finished Aug 02 04:45:58 PM PDT 24
Peak memory 205312 kb
Host smart-d37bc377-0bb6-4ced-b329-4243aaa69bf4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786802135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2786802135
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3969384403
Short name T423
Test name
Test status
Simulation time 58357734 ps
CPU time 0.81 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 205224 kb
Host smart-4ef1cf5f-87b2-4c94-852f-df48339b7092
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969384403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3969384403
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2336158949
Short name T113
Test name
Test status
Simulation time 1103013289 ps
CPU time 3.69 seconds
Started Aug 02 04:45:57 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 205592 kb
Host smart-8337b247-aba3-434e-8e1f-e2b7064fae4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336158949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2336158949
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2972953160
Short name T431
Test name
Test status
Simulation time 32785305763 ps
CPU time 116.89 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:47:52 PM PDT 24
Peak memory 221420 kb
Host smart-2e830cd4-c473-4cfe-b44b-16f695422905
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972953160 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2972953160
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2377492833
Short name T467
Test name
Test status
Simulation time 847259707 ps
CPU time 6.14 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 213824 kb
Host smart-0cdc2304-adb0-4ed2-b9d7-4a2cc2e62e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377492833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2377492833
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.142964155
Short name T448
Test name
Test status
Simulation time 97943700 ps
CPU time 3.58 seconds
Started Aug 02 04:46:22 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 219668 kb
Host smart-e58725cf-bf30-43db-8f59-94811cd3c08f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142964155 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.142964155
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1294854810
Short name T398
Test name
Test status
Simulation time 93613247 ps
CPU time 2.31 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:21 PM PDT 24
Peak memory 213664 kb
Host smart-c6d5411a-7108-4bb8-8174-c947ffe166c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294854810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1294854810
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3688469782
Short name T446
Test name
Test status
Simulation time 21743804426 ps
CPU time 50.61 seconds
Started Aug 02 04:46:14 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205452 kb
Host smart-6cebd49a-4f37-4114-80ef-64275214918c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688469782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3688469782
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2477155150
Short name T340
Test name
Test status
Simulation time 1686608773 ps
CPU time 5.73 seconds
Started Aug 02 04:46:17 PM PDT 24
Finished Aug 02 04:46:23 PM PDT 24
Peak memory 205340 kb
Host smart-621de277-886e-4e80-8539-8eae9f10fa39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477155150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2477155150
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3363694889
Short name T328
Test name
Test status
Simulation time 935956100 ps
CPU time 1.79 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:21 PM PDT 24
Peak memory 205280 kb
Host smart-6211f836-d907-492e-a1d5-5ade0376f4f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363694889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3363694889
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1836316328
Short name T112
Test name
Test status
Simulation time 1814449101 ps
CPU time 7.21 seconds
Started Aug 02 04:46:22 PM PDT 24
Finished Aug 02 04:46:30 PM PDT 24
Peak memory 205504 kb
Host smart-e841be4f-fa4e-469f-899a-53e9887363ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836316328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1836316328
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3302494100
Short name T464
Test name
Test status
Simulation time 289350922 ps
CPU time 4.96 seconds
Started Aug 02 04:46:21 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 213868 kb
Host smart-c4538514-465b-4347-a7c7-fe9e26e9fcf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302494100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3302494100
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3752584744
Short name T167
Test name
Test status
Simulation time 5895570464 ps
CPU time 19.87 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 213872 kb
Host smart-5a019e28-e136-433d-a87e-41a21a72f471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752584744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
752584744
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.975300513
Short name T123
Test name
Test status
Simulation time 325978124 ps
CPU time 2.26 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 216052 kb
Host smart-95e92e0d-67a8-45f9-9c73-be37c9d5bbba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975300513 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.975300513
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2229104110
Short name T92
Test name
Test status
Simulation time 110319408 ps
CPU time 2.38 seconds
Started Aug 02 04:46:16 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 213616 kb
Host smart-3a254cf9-4f21-4476-af47-eb3c439e557a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229104110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2229104110
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3155731409
Short name T347
Test name
Test status
Simulation time 17707356608 ps
CPU time 42.71 seconds
Started Aug 02 04:46:22 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205512 kb
Host smart-2beaa215-a71c-45fa-b1ba-9685f7dcd06f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155731409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3155731409
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2399550119
Short name T432
Test name
Test status
Simulation time 7476962068 ps
CPU time 3.32 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 205444 kb
Host smart-d6f7e81c-c0c5-457b-8320-7dd9445a059c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399550119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2399550119
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3922585483
Short name T332
Test name
Test status
Simulation time 160727863 ps
CPU time 1.15 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:20 PM PDT 24
Peak memory 205276 kb
Host smart-c5262c0a-e9d1-4011-9d03-09571c3e5d5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922585483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3922585483
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1962289262
Short name T418
Test name
Test status
Simulation time 149614735 ps
CPU time 2.49 seconds
Started Aug 02 04:46:21 PM PDT 24
Finished Aug 02 04:46:24 PM PDT 24
Peak memory 213828 kb
Host smart-d64fa2f1-3826-45d8-a8da-fdbc62459910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962289262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1962289262
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1555022710
Short name T124
Test name
Test status
Simulation time 147833070 ps
CPU time 2.29 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:46:34 PM PDT 24
Peak memory 215496 kb
Host smart-c0aa04fe-1090-4a85-ba38-e1d07c7b55c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555022710 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1555022710
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.721892099
Short name T83
Test name
Test status
Simulation time 178590315 ps
CPU time 2.36 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:21 PM PDT 24
Peak memory 213596 kb
Host smart-276ac203-0a59-4b6c-8d18-57926e5fab01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721892099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.721892099
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2696834118
Short name T417
Test name
Test status
Simulation time 34015530869 ps
CPU time 10.18 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:30 PM PDT 24
Peak memory 205532 kb
Host smart-763cb931-5877-49be-821a-745013b5fc74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696834118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2696834118
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2953849690
Short name T368
Test name
Test status
Simulation time 5738690763 ps
CPU time 15.28 seconds
Started Aug 02 04:46:21 PM PDT 24
Finished Aug 02 04:46:36 PM PDT 24
Peak memory 205520 kb
Host smart-2816f3d1-b10a-43db-9f7d-f875292cb063
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953849690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2953849690
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.454068188
Short name T362
Test name
Test status
Simulation time 600624176 ps
CPU time 1.16 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:21 PM PDT 24
Peak memory 205200 kb
Host smart-a38af31b-6ca0-42f0-aef4-f80732274a48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454068188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.454068188
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.445520592
Short name T80
Test name
Test status
Simulation time 245738951 ps
CPU time 3.67 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:41 PM PDT 24
Peak memory 205508 kb
Host smart-ec5d1503-a61e-42ac-b05e-b6bb980c09d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445520592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.445520592
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1052116661
Short name T320
Test name
Test status
Simulation time 776517803 ps
CPU time 4.49 seconds
Started Aug 02 04:46:17 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 216148 kb
Host smart-24dd3303-2885-4b98-a520-878c1e405142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052116661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1052116661
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2338512904
Short name T165
Test name
Test status
Simulation time 2602765577 ps
CPU time 8.8 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:28 PM PDT 24
Peak memory 213956 kb
Host smart-1998e7bd-89af-479c-a72b-854fe4ae67f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338512904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
338512904
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3346103163
Short name T364
Test name
Test status
Simulation time 105595734 ps
CPU time 2.28 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 217256 kb
Host smart-39727d83-ff6c-4e8b-822b-ddcda7381bd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346103163 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3346103163
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2889998267
Short name T102
Test name
Test status
Simulation time 152010512 ps
CPU time 1.64 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:46:33 PM PDT 24
Peak memory 213676 kb
Host smart-910971b0-3e4b-4f4b-8816-ea75624b411d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889998267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2889998267
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1241262642
Short name T316
Test name
Test status
Simulation time 2171332044 ps
CPU time 3.98 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 205524 kb
Host smart-f3dbadd1-ed21-4900-a93a-12bfa8413eb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241262642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1241262642
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2649842453
Short name T411
Test name
Test status
Simulation time 7538855342 ps
CPU time 12.32 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205600 kb
Host smart-d17cfcb6-62ae-4975-94ec-f5fb9ba41e7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649842453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2649842453
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3399863969
Short name T352
Test name
Test status
Simulation time 243685685 ps
CPU time 1.1 seconds
Started Aug 02 04:46:32 PM PDT 24
Finished Aug 02 04:46:33 PM PDT 24
Peak memory 205280 kb
Host smart-c1376294-378f-49bf-8930-6c5f7cc8646c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399863969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3399863969
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2360989671
Short name T115
Test name
Test status
Simulation time 265898459 ps
CPU time 7.12 seconds
Started Aug 02 04:46:43 PM PDT 24
Finished Aug 02 04:46:50 PM PDT 24
Peak memory 205564 kb
Host smart-26bff161-b6d2-40b1-818a-c47be5b32f94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360989671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2360989671
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.212374741
Short name T360
Test name
Test status
Simulation time 894695385 ps
CPU time 5.48 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 213768 kb
Host smart-2b0af0a1-d73f-4b5c-8de4-ada4a0f06c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212374741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.212374741
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3116481987
Short name T172
Test name
Test status
Simulation time 1773171478 ps
CPU time 21.25 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 213684 kb
Host smart-6c191450-b928-492c-8e97-f4d4d031d903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116481987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
116481987
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2093765790
Short name T324
Test name
Test status
Simulation time 185273430 ps
CPU time 4.09 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 222040 kb
Host smart-730e48e8-afd2-4c30-a084-2d1213c4db30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093765790 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2093765790
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4273963379
Short name T106
Test name
Test status
Simulation time 189594478 ps
CPU time 1.53 seconds
Started Aug 02 04:46:29 PM PDT 24
Finished Aug 02 04:46:31 PM PDT 24
Peak memory 213656 kb
Host smart-f1e79726-3c86-48f0-9908-16a4e6195a53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273963379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4273963379
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3913892454
Short name T415
Test name
Test status
Simulation time 12516199723 ps
CPU time 22.15 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:46:54 PM PDT 24
Peak memory 205492 kb
Host smart-c6c698c3-2cd0-4c5f-9fc6-29e76ae023f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913892454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3913892454
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4259406361
Short name T317
Test name
Test status
Simulation time 1621016121 ps
CPU time 2.14 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 205352 kb
Host smart-a717b93a-c0cb-4aff-885b-49edf0fd78be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259406361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
4259406361
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4162777091
Short name T381
Test name
Test status
Simulation time 226965018 ps
CPU time 0.96 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:35 PM PDT 24
Peak memory 205128 kb
Host smart-f20a7f2d-988f-45c7-8cad-e14be4628f5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162777091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4162777091
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.71976863
Short name T98
Test name
Test status
Simulation time 244941307 ps
CPU time 3.74 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 205528 kb
Host smart-2f06d768-b530-4a1d-948e-0b481e3c69ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71976863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_c
sr_outstanding.71976863
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3911420961
Short name T379
Test name
Test status
Simulation time 144954386 ps
CPU time 2.54 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 213808 kb
Host smart-99fa97df-91aa-47df-b171-6e4fd3f1efca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911420961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3911420961
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2801588735
Short name T341
Test name
Test status
Simulation time 257053527 ps
CPU time 2.33 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 217948 kb
Host smart-0c852ea6-3156-4194-8afd-75c966b1c524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801588735 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2801588735
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.388375186
Short name T94
Test name
Test status
Simulation time 238722411 ps
CPU time 2.32 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 213664 kb
Host smart-51156463-7f08-4b43-a788-24fda4d25fb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388375186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.388375186
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.427938276
Short name T405
Test name
Test status
Simulation time 149907388 ps
CPU time 0.68 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 205204 kb
Host smart-8d6598c0-c383-48f5-93bc-a6b52f834797
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427938276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.427938276
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3649043435
Short name T319
Test name
Test status
Simulation time 8084746713 ps
CPU time 10.76 seconds
Started Aug 02 04:46:32 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205456 kb
Host smart-2f43a0dc-6fd0-4182-9d82-090ac9549ccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649043435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3649043435
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.761149567
Short name T376
Test name
Test status
Simulation time 361266683 ps
CPU time 1.23 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205160 kb
Host smart-280356d4-06ac-4305-9e73-7f0e5fc61534
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761149567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.761149567
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2858290952
Short name T99
Test name
Test status
Simulation time 907689837 ps
CPU time 7.58 seconds
Started Aug 02 04:46:28 PM PDT 24
Finished Aug 02 04:46:36 PM PDT 24
Peak memory 205536 kb
Host smart-f777a6dd-e6f1-4040-8bf5-706a341c0ad7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858290952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2858290952
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1047349174
Short name T345
Test name
Test status
Simulation time 306990457 ps
CPU time 3 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 213856 kb
Host smart-694fd3c2-7e75-4641-810f-ef76a797b836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047349174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1047349174
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1478849982
Short name T162
Test name
Test status
Simulation time 1037867908 ps
CPU time 10.59 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:49 PM PDT 24
Peak memory 213720 kb
Host smart-f0ff4759-d0b0-4ae3-84c8-122c6ca30a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478849982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
478849982
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2856465639
Short name T454
Test name
Test status
Simulation time 124899310 ps
CPU time 2.25 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:36 PM PDT 24
Peak memory 213732 kb
Host smart-dce01cb6-1993-439b-ac4d-68ba8b45e48a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856465639 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2856465639
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3381609788
Short name T105
Test name
Test status
Simulation time 154476330 ps
CPU time 1.58 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:35 PM PDT 24
Peak memory 213628 kb
Host smart-0ce59e8a-eb55-4f79-be6c-a1a0408e89e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381609788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3381609788
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.18705484
Short name T393
Test name
Test status
Simulation time 8277323419 ps
CPU time 9.61 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205472 kb
Host smart-114560e7-82ca-4c33-84ec-5e717da24aa5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18705484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r
v_dm_jtag_dmi_csr_bit_bash.18705484
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2322378259
Short name T372
Test name
Test status
Simulation time 3246727596 ps
CPU time 5.53 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205508 kb
Host smart-d9550822-e5a2-417a-8542-f1e60a257054
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322378259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2322378259
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.507066201
Short name T62
Test name
Test status
Simulation time 330787178 ps
CPU time 0.89 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205152 kb
Host smart-ad4a33ac-52bf-4b87-be85-c43213d56373
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507066201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.507066201
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2259303943
Short name T111
Test name
Test status
Simulation time 3397120015 ps
CPU time 8.72 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205668 kb
Host smart-f57334d9-e79e-497b-a84f-7a7b8cf7e7d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259303943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2259303943
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.655579915
Short name T354
Test name
Test status
Simulation time 209163018 ps
CPU time 2.9 seconds
Started Aug 02 04:46:30 PM PDT 24
Finished Aug 02 04:46:33 PM PDT 24
Peak memory 213784 kb
Host smart-eff891b2-b4ef-4c1d-ac15-9d68c58f1577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655579915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.655579915
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3444937104
Short name T166
Test name
Test status
Simulation time 2437790848 ps
CPU time 10.36 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 213956 kb
Host smart-c3d9f796-d04a-477d-9fa0-efdfbdab77d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444937104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
444937104
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1917679454
Short name T121
Test name
Test status
Simulation time 146070694 ps
CPU time 2.39 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 215304 kb
Host smart-c05dd49f-0c93-48b2-835e-6d586e6dbf9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917679454 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1917679454
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1626938581
Short name T442
Test name
Test status
Simulation time 234179945 ps
CPU time 2.34 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 213632 kb
Host smart-0dca4b45-e6d2-4315-a0d0-bae477bbb748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626938581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1626938581
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3678642537
Short name T366
Test name
Test status
Simulation time 61001248015 ps
CPU time 163.85 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:49:20 PM PDT 24
Peak memory 205556 kb
Host smart-f92dc19c-0c4e-420a-9fd7-c1717befa52b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678642537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3678642537
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.36846641
Short name T323
Test name
Test status
Simulation time 11833209342 ps
CPU time 16.87 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205508 kb
Host smart-138c1871-90cc-46cf-b1ea-f92b5aa2a085
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.36846641
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.131659798
Short name T438
Test name
Test status
Simulation time 498005430 ps
CPU time 1.96 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:35 PM PDT 24
Peak memory 205256 kb
Host smart-7f7e25d9-a922-40e3-9c61-b1f7fbb34a8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131659798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.131659798
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2413400993
Short name T97
Test name
Test status
Simulation time 365684366 ps
CPU time 3.88 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205572 kb
Host smart-3770d330-c418-4ecf-9b4a-717645501108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413400993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2413400993
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2333555516
Short name T365
Test name
Test status
Simulation time 95211114 ps
CPU time 2.49 seconds
Started Aug 02 04:46:30 PM PDT 24
Finished Aug 02 04:46:33 PM PDT 24
Peak memory 213676 kb
Host smart-093f20c2-b79c-42dd-929a-8a445621cb0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333555516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2333555516
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3084097016
Short name T435
Test name
Test status
Simulation time 4029809734 ps
CPU time 10.68 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 213908 kb
Host smart-b125150d-e768-481c-a2da-b9843b556310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084097016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
084097016
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2819423012
Short name T399
Test name
Test status
Simulation time 473207590 ps
CPU time 2.51 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 213784 kb
Host smart-0bed2c04-338e-4531-8aed-969e565c0fb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819423012 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2819423012
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.398498017
Short name T93
Test name
Test status
Simulation time 382698171 ps
CPU time 2.43 seconds
Started Aug 02 04:46:32 PM PDT 24
Finished Aug 02 04:46:34 PM PDT 24
Peak memory 213640 kb
Host smart-3f3987b3-736e-44a9-8f26-21821b340cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398498017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.398498017
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.437501110
Short name T465
Test name
Test status
Simulation time 44395886 ps
CPU time 0.72 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:36 PM PDT 24
Peak memory 205172 kb
Host smart-451d5a9f-0318-4b00-ab25-37296f52d1dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437501110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.437501110
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2360853349
Short name T394
Test name
Test status
Simulation time 5507373822 ps
CPU time 15.98 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 205564 kb
Host smart-5f522667-5e61-4fe8-b5b0-4dfcad9aa9e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360853349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2360853349
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.856445111
Short name T361
Test name
Test status
Simulation time 299330937 ps
CPU time 0.89 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:36 PM PDT 24
Peak memory 205192 kb
Host smart-2212f218-70f1-44be-998d-080643eb4bb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856445111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.856445111
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2814820179
Short name T460
Test name
Test status
Simulation time 971378931 ps
CPU time 4.26 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205520 kb
Host smart-a6f2000e-0e98-4bc9-87a1-291cc8cc87f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814820179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2814820179
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.95151860
Short name T339
Test name
Test status
Simulation time 68688770 ps
CPU time 3.07 seconds
Started Aug 02 04:46:32 PM PDT 24
Finished Aug 02 04:46:35 PM PDT 24
Peak memory 213760 kb
Host smart-35b783da-60bd-4784-b32a-9cc2ab0cdb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95151860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.95151860
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2253753434
Short name T119
Test name
Test status
Simulation time 3177633219 ps
CPU time 10.45 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 213808 kb
Host smart-5907eea5-4aa3-4947-92ed-8ec74052a8f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253753434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
253753434
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1556727108
Short name T125
Test name
Test status
Simulation time 240203840 ps
CPU time 3.89 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 222020 kb
Host smart-5da7cb3d-cfd1-434b-93bd-e838162f15f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556727108 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1556727108
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3565045598
Short name T101
Test name
Test status
Simulation time 165707213 ps
CPU time 1.96 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 213664 kb
Host smart-9a1c65eb-ad41-4ad3-a4f1-e8e0bdc31d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565045598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3565045598
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.603477294
Short name T430
Test name
Test status
Simulation time 5019919728 ps
CPU time 8.41 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205444 kb
Host smart-cad5fc16-26e8-45a8-ba46-a01cea75ded9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603477294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.603477294
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1161921164
Short name T329
Test name
Test status
Simulation time 1076889049 ps
CPU time 2.34 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205372 kb
Host smart-eb2118de-bae5-4a93-93b1-00181cd7d0c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161921164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1161921164
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3079284722
Short name T375
Test name
Test status
Simulation time 110504669 ps
CPU time 0.79 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205168 kb
Host smart-1e82b95f-defb-4721-8d66-c50911544de0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079284722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3079284722
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3430523008
Short name T95
Test name
Test status
Simulation time 201808734 ps
CPU time 6.65 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205572 kb
Host smart-0e3d7c84-1de9-4f3e-bc86-0e538ae0da76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430523008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3430523008
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3369683198
Short name T331
Test name
Test status
Simulation time 176803242 ps
CPU time 4.77 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 213792 kb
Host smart-f2a538a4-4f5e-4927-b655-965c5881381e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369683198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3369683198
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.594400991
Short name T171
Test name
Test status
Simulation time 2703111395 ps
CPU time 20.25 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:58 PM PDT 24
Peak memory 213856 kb
Host smart-e30f95a4-cd25-4bf4-9ba2-000057996fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594400991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.594400991
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1668206957
Short name T77
Test name
Test status
Simulation time 1301188470 ps
CPU time 28.09 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:46:23 PM PDT 24
Peak memory 205464 kb
Host smart-5db60de6-8b9b-43cb-b95c-b5c5ab76d55f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668206957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1668206957
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2776978166
Short name T451
Test name
Test status
Simulation time 5027209889 ps
CPU time 67.01 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 205600 kb
Host smart-666aff25-51da-48e7-b65a-a6172b4e44b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776978166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2776978166
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4064277592
Short name T96
Test name
Test status
Simulation time 320888297 ps
CPU time 2.74 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:45:58 PM PDT 24
Peak memory 213668 kb
Host smart-5a5ec03d-b158-42b4-844e-9a311a200200
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064277592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4064277592
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.120598902
Short name T373
Test name
Test status
Simulation time 576464217 ps
CPU time 3.7 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:09 PM PDT 24
Peak memory 219056 kb
Host smart-8366d063-71ec-4963-bc90-f412071efa6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120598902 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.120598902
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2650485262
Short name T416
Test name
Test status
Simulation time 131047994 ps
CPU time 2.3 seconds
Started Aug 02 04:45:57 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 213660 kb
Host smart-9fca5c4c-4cd1-4b1b-b8fe-1147a2d79ca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650485262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2650485262
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.875749711
Short name T386
Test name
Test status
Simulation time 36356095873 ps
CPU time 19.54 seconds
Started Aug 02 04:45:59 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 205572 kb
Host smart-f1598a07-d3dc-4d5b-80e4-0b180a1ab05c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875749711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.875749711
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3685007875
Short name T349
Test name
Test status
Simulation time 118375043 ps
CPU time 0.97 seconds
Started Aug 02 04:45:59 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 205200 kb
Host smart-ccd3cf90-63e4-4340-9523-a49a840c0527
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685007875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3685007875
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1559685270
Short name T378
Test name
Test status
Simulation time 1923402170 ps
CPU time 5.78 seconds
Started Aug 02 04:45:55 PM PDT 24
Finished Aug 02 04:46:01 PM PDT 24
Peak memory 205476 kb
Host smart-dfb6ed02-b236-4dcf-88b3-6ad7d34c5408
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559685270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1559685270
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4238503229
Short name T443
Test name
Test status
Simulation time 4698718486 ps
CPU time 4.56 seconds
Started Aug 02 04:45:58 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 205412 kb
Host smart-1fbf9e25-6457-4706-8109-7798b0e4ffb1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238503229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4
238503229
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2270071034
Short name T414
Test name
Test status
Simulation time 654650217 ps
CPU time 2.13 seconds
Started Aug 02 04:45:58 PM PDT 24
Finished Aug 02 04:46:01 PM PDT 24
Peak memory 205256 kb
Host smart-4c01dfde-339f-4c08-8e92-25204f25af86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270071034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2270071034
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3380409837
Short name T396
Test name
Test status
Simulation time 14543451147 ps
CPU time 12.78 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 205456 kb
Host smart-9db77a26-3044-4163-9897-424db12f628f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380409837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3380409837
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3866168168
Short name T64
Test name
Test status
Simulation time 755559290 ps
CPU time 1.26 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 205228 kb
Host smart-4b977524-5257-43b5-9b56-0e7acecf994d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866168168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3866168168
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.864011995
Short name T407
Test name
Test status
Simulation time 504645714 ps
CPU time 1.06 seconds
Started Aug 02 04:45:59 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 205152 kb
Host smart-7dec1038-abc9-4290-9401-dba3e0d154b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864011995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.864011995
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1896977256
Short name T419
Test name
Test status
Simulation time 122184363 ps
CPU time 0.95 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:45:56 PM PDT 24
Peak memory 205216 kb
Host smart-115413a1-e7d4-4bd1-bf68-5f9eb920feb5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896977256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1896977256
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2086220803
Short name T336
Test name
Test status
Simulation time 131050210 ps
CPU time 0.76 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 205156 kb
Host smart-d1f21942-80c7-406b-9e23-9fc7b616b289
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086220803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2086220803
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3336304628
Short name T110
Test name
Test status
Simulation time 272838861 ps
CPU time 6.92 seconds
Started Aug 02 04:45:56 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 205476 kb
Host smart-4cd324a6-d79f-4a40-afa4-2bade56bc0f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336304628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3336304628
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.975601213
Short name T359
Test name
Test status
Simulation time 144575970 ps
CPU time 4.26 seconds
Started Aug 02 04:45:58 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 213676 kb
Host smart-90ad5901-13d7-4bb9-a00f-d6a74279d0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975601213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.975601213
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2137678817
Short name T383
Test name
Test status
Simulation time 1008720027 ps
CPU time 27.61 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 214668 kb
Host smart-f09a5da3-ea64-4c6d-a255-79eb70651158
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137678817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2137678817
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1855414832
Short name T107
Test name
Test status
Simulation time 763321303 ps
CPU time 28.76 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:32 PM PDT 24
Peak memory 205488 kb
Host smart-8e04b2f7-d997-4304-a395-75ba00d1727b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855414832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1855414832
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.613942320
Short name T103
Test name
Test status
Simulation time 354249884 ps
CPU time 3.13 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 213632 kb
Host smart-ff021ca8-7aff-43e6-b9fa-92681c77223f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613942320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.613942320
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3883023321
Short name T338
Test name
Test status
Simulation time 261190244 ps
CPU time 4.29 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:08 PM PDT 24
Peak memory 220004 kb
Host smart-0229e6af-f695-4f5c-9f8a-bc0b8b9275e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883023321 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3883023321
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.141803197
Short name T408
Test name
Test status
Simulation time 154240289 ps
CPU time 2.03 seconds
Started Aug 02 04:46:00 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 213728 kb
Host smart-a267dffe-8ecc-4706-9527-44ab5faa5e38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141803197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.141803197
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.361863715
Short name T412
Test name
Test status
Simulation time 92411470272 ps
CPU time 240.67 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:50:06 PM PDT 24
Peak memory 205452 kb
Host smart-7b25825f-0468-4912-a6be-473e6e91a5ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361863715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.361863715
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1896420890
Short name T420
Test name
Test status
Simulation time 22836218011 ps
CPU time 26.18 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:46:27 PM PDT 24
Peak memory 205500 kb
Host smart-33ac5b07-65ba-4c5c-ba38-af36d3b4759a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896420890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1896420890
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.163922763
Short name T89
Test name
Test status
Simulation time 6001991537 ps
CPU time 5.41 seconds
Started Aug 02 04:45:54 PM PDT 24
Finished Aug 02 04:45:59 PM PDT 24
Peak memory 205556 kb
Host smart-80cd4e6e-8086-4bd2-a633-72a6323f63d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163922763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.163922763
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4288933651
Short name T322
Test name
Test status
Simulation time 1220050424 ps
CPU time 2.75 seconds
Started Aug 02 04:45:59 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 205464 kb
Host smart-c1b2b73a-6081-4e4a-8fe5-2c1747f7a6d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288933651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4
288933651
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1172255447
Short name T413
Test name
Test status
Simulation time 164303305 ps
CPU time 1.19 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 205172 kb
Host smart-49b79a58-8ee6-49f7-a728-4cfb3cd887af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172255447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1172255447
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2114173687
Short name T363
Test name
Test status
Simulation time 10678718339 ps
CPU time 5.82 seconds
Started Aug 02 04:45:57 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 205488 kb
Host smart-324b68a9-1da4-4272-be39-8b6dfee58287
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114173687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2114173687
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3833100067
Short name T346
Test name
Test status
Simulation time 543476724 ps
CPU time 0.98 seconds
Started Aug 02 04:46:00 PM PDT 24
Finished Aug 02 04:46:01 PM PDT 24
Peak memory 205188 kb
Host smart-27cc8252-873a-4363-a59d-46bb04b02c4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833100067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3833100067
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.234239767
Short name T382
Test name
Test status
Simulation time 198107035 ps
CPU time 1.13 seconds
Started Aug 02 04:46:04 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 205144 kb
Host smart-0ec96af1-92a9-4a4c-8682-74763123431a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234239767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.234239767
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3662326323
Short name T337
Test name
Test status
Simulation time 56554474 ps
CPU time 0.8 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:46:02 PM PDT 24
Peak memory 205304 kb
Host smart-79fc8ba4-b558-40b9-8778-b8a63ec182fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662326323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3662326323
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.930071058
Short name T434
Test name
Test status
Simulation time 28075498 ps
CPU time 0.77 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 205156 kb
Host smart-3611eb17-8e2a-4b99-b404-87a6e3f0c914
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930071058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.930071058
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.949998988
Short name T109
Test name
Test status
Simulation time 1152341021 ps
CPU time 4.41 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:08 PM PDT 24
Peak memory 205560 kb
Host smart-93ae44c1-a45b-49e5-aad8-fc455fa69201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949998988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.949998988
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1683555042
Short name T456
Test name
Test status
Simulation time 14941525189 ps
CPU time 49.37 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 220376 kb
Host smart-254b9122-674a-4e2e-9ef4-9d871ac7304d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683555042 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1683555042
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2294544160
Short name T406
Test name
Test status
Simulation time 122046662 ps
CPU time 5.02 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:08 PM PDT 24
Peak memory 213836 kb
Host smart-c0f31044-da84-4644-b340-fbf03efb2cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294544160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2294544160
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1343275548
Short name T116
Test name
Test status
Simulation time 7891716740 ps
CPU time 30.65 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:32 PM PDT 24
Peak memory 205528 kb
Host smart-619faec6-dac1-4760-a584-b51a8c7f84c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343275548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1343275548
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.546357678
Short name T108
Test name
Test status
Simulation time 2467540263 ps
CPU time 32.8 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205624 kb
Host smart-dc855fff-9589-472e-a728-7957d20b4104
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546357678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.546357678
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1414495477
Short name T100
Test name
Test status
Simulation time 237958826 ps
CPU time 2.72 seconds
Started Aug 02 04:46:00 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 213788 kb
Host smart-f518a57c-9382-4052-a027-217cd292909b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414495477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1414495477
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1539085803
Short name T355
Test name
Test status
Simulation time 155269974 ps
CPU time 2.83 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 222004 kb
Host smart-282a3b25-7bdd-4ea1-82e1-98ea72b115ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539085803 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1539085803
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2384282197
Short name T447
Test name
Test status
Simulation time 563415802 ps
CPU time 1.65 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 213776 kb
Host smart-79153460-f6cf-47ec-b3c8-bad6602dde80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384282197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2384282197
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2661863179
Short name T425
Test name
Test status
Simulation time 45596649865 ps
CPU time 62.93 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205444 kb
Host smart-0121889f-d924-46ac-a259-b85d27a9ede9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661863179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2661863179
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2511323679
Short name T385
Test name
Test status
Simulation time 31722375316 ps
CPU time 82.14 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 205520 kb
Host smart-5410a3b7-3531-4864-8d4d-83822ab95b90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511323679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2511323679
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2641184426
Short name T90
Test name
Test status
Simulation time 2584347556 ps
CPU time 5.65 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:11 PM PDT 24
Peak memory 205552 kb
Host smart-74b0f4df-98ff-4cc8-a8a6-ba9291b056be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641184426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2641184426
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1467967134
Short name T450
Test name
Test status
Simulation time 1154554097 ps
CPU time 1.62 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:07 PM PDT 24
Peak memory 205372 kb
Host smart-fc55cd52-3b63-47b0-93a1-92f5a5183341
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467967134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
467967134
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.955967859
Short name T380
Test name
Test status
Simulation time 1295365872 ps
CPU time 1.47 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 205240 kb
Host smart-88c463fc-ec9d-42a8-b5f4-4154516a65c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955967859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.955967859
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1231808445
Short name T463
Test name
Test status
Simulation time 2869946603 ps
CPU time 7.38 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 205504 kb
Host smart-1510157d-feee-46b7-a796-8c57ca98fd0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231808445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1231808445
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3965773638
Short name T326
Test name
Test status
Simulation time 352392642 ps
CPU time 0.98 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:06 PM PDT 24
Peak memory 205240 kb
Host smart-b5ea9cef-35d3-4a1e-ad8d-852c3803cef8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965773638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3965773638
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.422289370
Short name T335
Test name
Test status
Simulation time 491027392 ps
CPU time 1.89 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 205164 kb
Host smart-d02f4dec-be75-4a7f-9328-8d202ac9862a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422289370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.422289370
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1960023709
Short name T371
Test name
Test status
Simulation time 29968221 ps
CPU time 0.74 seconds
Started Aug 02 04:46:06 PM PDT 24
Finished Aug 02 04:46:07 PM PDT 24
Peak memory 205220 kb
Host smart-e610c4fd-d4da-482e-bee8-bad12addce7b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960023709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1960023709
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3706162670
Short name T318
Test name
Test status
Simulation time 187699229 ps
CPU time 0.73 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:03 PM PDT 24
Peak memory 205164 kb
Host smart-423ebf7f-5f45-4e6d-b078-b391c7fb8e21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706162670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3706162670
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.822025104
Short name T436
Test name
Test status
Simulation time 876268030 ps
CPU time 4.27 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:09 PM PDT 24
Peak memory 205556 kb
Host smart-1f0dbbc7-62ee-48ec-bacf-d425c52f503c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822025104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.822025104
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3848072372
Short name T61
Test name
Test status
Simulation time 19640825081 ps
CPU time 59.72 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:47:01 PM PDT 24
Peak memory 222004 kb
Host smart-8a243acc-d2e1-4949-b392-6f05c8ba75d1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848072372 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3848072372
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1688545131
Short name T122
Test name
Test status
Simulation time 210266312 ps
CPU time 2.73 seconds
Started Aug 02 04:46:05 PM PDT 24
Finished Aug 02 04:46:08 PM PDT 24
Peak memory 213824 kb
Host smart-a6178bfd-4511-4170-8029-19cc403f1550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688545131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1688545131
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1566279020
Short name T120
Test name
Test status
Simulation time 12039647275 ps
CPU time 20.52 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 213816 kb
Host smart-603e979e-753e-484c-8f52-09894d3d3473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566279020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1566279020
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1979408388
Short name T462
Test name
Test status
Simulation time 275375806 ps
CPU time 2.74 seconds
Started Aug 02 04:46:13 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 217812 kb
Host smart-8460f3d5-0499-493c-9e11-78b5614112b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979408388 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1979408388
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2209587356
Short name T388
Test name
Test status
Simulation time 291276773 ps
CPU time 1.71 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:04 PM PDT 24
Peak memory 213776 kb
Host smart-d1c396fd-2d6e-489b-a6f3-894a2a733e3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209587356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2209587356
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3984855922
Short name T377
Test name
Test status
Simulation time 2051377925 ps
CPU time 4.05 seconds
Started Aug 02 04:46:01 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 205368 kb
Host smart-eb7f47d0-fc12-4f22-a61f-7f607175402f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984855922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3984855922
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.161838471
Short name T342
Test name
Test status
Simulation time 4459155499 ps
CPU time 7.37 seconds
Started Aug 02 04:46:04 PM PDT 24
Finished Aug 02 04:46:11 PM PDT 24
Peak memory 205504 kb
Host smart-6c570251-ce11-4ad5-a653-8beccd5b9427
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161838471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.161838471
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3677937203
Short name T445
Test name
Test status
Simulation time 221996050 ps
CPU time 0.83 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 205200 kb
Host smart-4b219ea2-aaf8-4f68-ae4a-859de38e90dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677937203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
677937203
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3870096318
Short name T457
Test name
Test status
Simulation time 9617511852 ps
CPU time 10.88 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 205668 kb
Host smart-1d412ccd-9bee-4b33-8baa-367c63cb8d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870096318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3870096318
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.970309925
Short name T175
Test name
Test status
Simulation time 59019886140 ps
CPU time 22.56 seconds
Started Aug 02 04:46:04 PM PDT 24
Finished Aug 02 04:46:27 PM PDT 24
Peak memory 230272 kb
Host smart-2dc3a418-adfd-4bc0-8bb8-7defdd8ac41d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970309925 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.970309925
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.616005718
Short name T70
Test name
Test status
Simulation time 377897161 ps
CPU time 4.63 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:16 PM PDT 24
Peak memory 213820 kb
Host smart-8175e878-6a3c-433b-8c07-4300493ab3d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616005718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.616005718
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1544881703
Short name T170
Test name
Test status
Simulation time 3641896150 ps
CPU time 20.73 seconds
Started Aug 02 04:46:03 PM PDT 24
Finished Aug 02 04:46:23 PM PDT 24
Peak memory 213796 kb
Host smart-139d7849-7d1c-4d6b-9195-5255b20b6bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544881703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1544881703
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1014182721
Short name T321
Test name
Test status
Simulation time 413386707 ps
CPU time 5.21 seconds
Started Aug 02 04:46:15 PM PDT 24
Finished Aug 02 04:46:20 PM PDT 24
Peak memory 220600 kb
Host smart-9e79dc9f-6619-45f6-89ed-f3e034b57ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014182721 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1014182721
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2506645586
Short name T391
Test name
Test status
Simulation time 223337722 ps
CPU time 1.58 seconds
Started Aug 02 04:46:17 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 213556 kb
Host smart-87bc856e-ee6a-423a-88d9-801e1d0e7721
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506645586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2506645586
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2399633631
Short name T428
Test name
Test status
Simulation time 51003949452 ps
CPU time 41.89 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:47:01 PM PDT 24
Peak memory 205520 kb
Host smart-623b5823-7c48-4bca-8083-5284abe1d998
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399633631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2399633631
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.748828442
Short name T392
Test name
Test status
Simulation time 4144480841 ps
CPU time 7.19 seconds
Started Aug 02 04:46:02 PM PDT 24
Finished Aug 02 04:46:09 PM PDT 24
Peak memory 205508 kb
Host smart-a492ac50-c5f1-462b-a7d4-bb5113f536f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748828442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.748828442
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.727400389
Short name T325
Test name
Test status
Simulation time 169254348 ps
CPU time 0.86 seconds
Started Aug 02 04:46:12 PM PDT 24
Finished Aug 02 04:46:13 PM PDT 24
Peak memory 205200 kb
Host smart-f689382d-d0ad-458f-bad1-3ac18bca546e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727400389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.727400389
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.55149854
Short name T424
Test name
Test status
Simulation time 866090646 ps
CPU time 4.17 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:25 PM PDT 24
Peak memory 205628 kb
Host smart-a0dbfc35-616d-4fc6-a7ef-7fb75719eb8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55149854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_cs
r_outstanding.55149854
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3963858965
Short name T384
Test name
Test status
Simulation time 63522932865 ps
CPU time 294.78 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:51:13 PM PDT 24
Peak memory 221976 kb
Host smart-46189d69-354a-4ca1-9342-7bd3798d97dd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963858965 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3963858965
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2830459813
Short name T452
Test name
Test status
Simulation time 269786039 ps
CPU time 4.08 seconds
Started Aug 02 04:46:24 PM PDT 24
Finished Aug 02 04:46:29 PM PDT 24
Peak memory 213952 kb
Host smart-f0ec6eac-7a15-49c7-90fb-5abdcd3a344a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830459813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2830459813
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1142370212
Short name T164
Test name
Test status
Simulation time 6082919248 ps
CPU time 21.75 seconds
Started Aug 02 04:46:15 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 213816 kb
Host smart-7db59681-f675-4186-852e-67843bb44a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142370212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1142370212
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3608530018
Short name T439
Test name
Test status
Simulation time 301948025 ps
CPU time 2.33 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 213872 kb
Host smart-872d82f6-24cf-4de5-8636-bb1f08e6aab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608530018 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3608530018
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4118703185
Short name T374
Test name
Test status
Simulation time 458874965 ps
CPU time 2.45 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 213648 kb
Host smart-16fc6199-cd8e-4e7a-a4f4-f5f1d869dfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118703185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4118703185
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1705994477
Short name T334
Test name
Test status
Simulation time 52895078746 ps
CPU time 72.43 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 205512 kb
Host smart-69460cca-53a1-4c4e-8e1e-7363207e2cd9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705994477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1705994477
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3490232349
Short name T397
Test name
Test status
Simulation time 7575574616 ps
CPU time 12.21 seconds
Started Aug 02 04:46:14 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 205412 kb
Host smart-8760d206-8362-4af9-b923-4713b0732bd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490232349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
490232349
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.982688121
Short name T330
Test name
Test status
Simulation time 106667824 ps
CPU time 1.03 seconds
Started Aug 02 04:46:16 PM PDT 24
Finished Aug 02 04:46:18 PM PDT 24
Peak memory 205052 kb
Host smart-563385a9-f9a0-4e5f-907b-fc4cbdba9bdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982688121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.982688121
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1213116233
Short name T82
Test name
Test status
Simulation time 688889970 ps
CPU time 6.62 seconds
Started Aug 02 04:46:19 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 205528 kb
Host smart-78588c35-4976-4c20-bef9-64853b1bdd97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213116233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1213116233
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4014653794
Short name T404
Test name
Test status
Simulation time 42236011382 ps
CPU time 112.23 seconds
Started Aug 02 04:46:16 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 222104 kb
Host smart-83a5cbc1-7141-4ff5-a975-e7e20a8ba307
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014653794 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4014653794
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2442824877
Short name T370
Test name
Test status
Simulation time 367183518 ps
CPU time 2.64 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:20 PM PDT 24
Peak memory 213672 kb
Host smart-af5c88cd-495f-4b4c-be56-815a0ba1e895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442824877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2442824877
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2552839064
Short name T410
Test name
Test status
Simulation time 7729935567 ps
CPU time 21.27 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 213844 kb
Host smart-95a07e55-372a-4e76-916a-7dfaa2f92dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552839064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2552839064
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3101947427
Short name T427
Test name
Test status
Simulation time 201544534 ps
CPU time 3.7 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:21 PM PDT 24
Peak memory 213804 kb
Host smart-08e99fc3-8dd5-47db-982f-537f68754b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101947427 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3101947427
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.591713930
Short name T91
Test name
Test status
Simulation time 160988005 ps
CPU time 2.25 seconds
Started Aug 02 04:46:15 PM PDT 24
Finished Aug 02 04:46:17 PM PDT 24
Peak memory 213676 kb
Host smart-352a6dad-4588-46c0-8069-8ff905af46e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591713930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.591713930
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2656265087
Short name T333
Test name
Test status
Simulation time 26250941674 ps
CPU time 34.85 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 205508 kb
Host smart-99229f8a-b516-4a80-8353-b23020735640
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656265087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2656265087
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4226647606
Short name T348
Test name
Test status
Simulation time 4437210500 ps
CPU time 6.69 seconds
Started Aug 02 04:46:22 PM PDT 24
Finished Aug 02 04:46:29 PM PDT 24
Peak memory 205580 kb
Host smart-6e4466e3-cd90-45d0-9bed-04b0f80c0ed5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226647606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
226647606
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2007810106
Short name T441
Test name
Test status
Simulation time 268708749 ps
CPU time 0.85 seconds
Started Aug 02 04:46:17 PM PDT 24
Finished Aug 02 04:46:18 PM PDT 24
Peak memory 205312 kb
Host smart-dcc163cc-6c93-4274-a5e7-2b72fcd47fd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007810106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
007810106
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3561707140
Short name T453
Test name
Test status
Simulation time 3077879215 ps
CPU time 4.79 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:25 PM PDT 24
Peak memory 205640 kb
Host smart-ddb21c9a-8834-450f-940e-b4e19744e071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561707140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3561707140
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.505128910
Short name T389
Test name
Test status
Simulation time 35394483574 ps
CPU time 32.34 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:50 PM PDT 24
Peak memory 222012 kb
Host smart-4b1413a7-724e-49dc-bb07-c8890a670cc8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505128910 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.505128910
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.320220947
Short name T369
Test name
Test status
Simulation time 85428703 ps
CPU time 2.08 seconds
Started Aug 02 04:46:17 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 213752 kb
Host smart-6ec48422-3dea-46ce-9de2-763cf9c39e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320220947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.320220947
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2507731777
Short name T168
Test name
Test status
Simulation time 2721871085 ps
CPU time 14.69 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:35 PM PDT 24
Peak memory 213984 kb
Host smart-4151e568-2c1a-4849-947a-359c308a02d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507731777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2507731777
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.206690305
Short name T429
Test name
Test status
Simulation time 482718515 ps
CPU time 2.48 seconds
Started Aug 02 04:46:23 PM PDT 24
Finished Aug 02 04:46:25 PM PDT 24
Peak memory 218664 kb
Host smart-8ce08bf7-e4dc-4bfe-8b34-32f762790070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206690305 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.206690305
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3188467339
Short name T449
Test name
Test status
Simulation time 2090442880 ps
CPU time 3.89 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 205384 kb
Host smart-d386030b-5d11-4c69-aa0b-0e12026e7810
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188467339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3188467339
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4003237492
Short name T459
Test name
Test status
Simulation time 7329304913 ps
CPU time 6.98 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:25 PM PDT 24
Peak memory 205540 kb
Host smart-7162738a-8beb-4e91-8562-9922b5a7ba39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003237492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
003237492
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4114054599
Short name T344
Test name
Test status
Simulation time 315942619 ps
CPU time 1.24 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:46:19 PM PDT 24
Peak memory 205220 kb
Host smart-d63a5b1e-8fc7-40f5-85a6-f11a6543d81d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114054599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
114054599
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1751377090
Short name T114
Test name
Test status
Simulation time 606325465 ps
CPU time 7.89 seconds
Started Aug 02 04:46:14 PM PDT 24
Finished Aug 02 04:46:22 PM PDT 24
Peak memory 205492 kb
Host smart-b4504fac-d821-4428-ac02-471f991521f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751377090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1751377090
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4086125296
Short name T174
Test name
Test status
Simulation time 32345500019 ps
CPU time 51.08 seconds
Started Aug 02 04:46:18 PM PDT 24
Finished Aug 02 04:47:09 PM PDT 24
Peak memory 213872 kb
Host smart-1c097ca5-5875-4f4b-9e3e-854803b95c2c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086125296 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.4086125296
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1345487797
Short name T327
Test name
Test status
Simulation time 373409308 ps
CPU time 4.7 seconds
Started Aug 02 04:46:21 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 213724 kb
Host smart-a5fea09c-c960-4abc-96c6-67a3632ac1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345487797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1345487797
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2111022786
Short name T426
Test name
Test status
Simulation time 2968094804 ps
CPU time 20.63 seconds
Started Aug 02 04:46:20 PM PDT 24
Finished Aug 02 04:46:41 PM PDT 24
Peak memory 213848 kb
Host smart-fe9b41e7-2773-44ed-b38e-293296736c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111022786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2111022786
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.804661157
Short name T269
Test name
Test status
Simulation time 40845261 ps
CPU time 0.79 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:36 PM PDT 24
Peak memory 205160 kb
Host smart-4782b2b2-fd1e-4dd0-bd1b-47a4d401e848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804661157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.804661157
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1204497022
Short name T150
Test name
Test status
Simulation time 8798498618 ps
CPU time 6.85 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 213848 kb
Host smart-99a10c13-b9dc-4f1b-a97c-dc7cbf1881c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204497022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1204497022
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1257997017
Short name T253
Test name
Test status
Simulation time 250212417 ps
CPU time 1.44 seconds
Started Aug 02 04:46:32 PM PDT 24
Finished Aug 02 04:46:34 PM PDT 24
Peak memory 205168 kb
Host smart-a5e0816b-ac93-44a1-b548-5df1d9c45701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257997017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1257997017
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3066418470
Short name T193
Test name
Test status
Simulation time 187986101 ps
CPU time 0.84 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205200 kb
Host smart-47bd1303-f83e-460b-8dca-5236773f0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066418470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3066418470
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3527842561
Short name T75
Test name
Test status
Simulation time 223177712 ps
CPU time 1.31 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205132 kb
Host smart-3b75c1de-0d1e-4756-baba-1371d4f45eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527842561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3527842561
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1020581150
Short name T291
Test name
Test status
Simulation time 134252983 ps
CPU time 0.9 seconds
Started Aug 02 04:46:40 PM PDT 24
Finished Aug 02 04:46:41 PM PDT 24
Peak memory 215400 kb
Host smart-d3839105-7f11-4bbf-9a17-7c59a1231f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020581150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1020581150
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3851514064
Short name T290
Test name
Test status
Simulation time 649929878 ps
CPU time 1.01 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205204 kb
Host smart-80806ca3-99b2-4404-8979-dac74ecf098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851514064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3851514064
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2622829353
Short name T149
Test name
Test status
Simulation time 903521110 ps
CPU time 3.02 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205200 kb
Host smart-1f11d92b-fad3-4a62-9053-765a9586d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622829353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2622829353
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1811043845
Short name T27
Test name
Test status
Simulation time 408633413 ps
CPU time 1.01 seconds
Started Aug 02 04:46:42 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205172 kb
Host smart-452dc480-f3c5-4c7b-92cb-5dda4d267775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811043845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1811043845
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1272461518
Short name T309
Test name
Test status
Simulation time 433950164 ps
CPU time 1.34 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 204948 kb
Host smart-51d5e53d-692b-4a4b-8b4e-65bfd1656dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272461518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1272461518
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2330310378
Short name T181
Test name
Test status
Simulation time 340602800 ps
CPU time 1.66 seconds
Started Aug 02 04:46:38 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205252 kb
Host smart-2a8a3b53-4774-4a66-8b51-de02ea634594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330310378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2330310378
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2004129498
Short name T148
Test name
Test status
Simulation time 112976642 ps
CPU time 0.86 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205284 kb
Host smart-d845485f-4144-4f45-bcb1-7e95fe12c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004129498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2004129498
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.760772598
Short name T202
Test name
Test status
Simulation time 187663066 ps
CPU time 0.76 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:37 PM PDT 24
Peak memory 205116 kb
Host smart-253393dd-d120-4009-a17e-dd8c186cd9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760772598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.760772598
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2049698122
Short name T235
Test name
Test status
Simulation time 802786948 ps
CPU time 0.89 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:35 PM PDT 24
Peak memory 205016 kb
Host smart-d780d1f9-6a8c-45b1-ac2b-489d1807545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049698122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2049698122
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1058271114
Short name T201
Test name
Test status
Simulation time 192825003 ps
CPU time 0.8 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 213412 kb
Host smart-78f0f039-7160-42e8-ac59-a2c4c05764ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058271114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1058271114
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1709756916
Short name T305
Test name
Test status
Simulation time 331623272 ps
CPU time 0.96 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 205144 kb
Host smart-1485e092-97d0-4aca-bd6f-faa0fd38a8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709756916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1709756916
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.704020942
Short name T143
Test name
Test status
Simulation time 6204481657 ps
CPU time 3.46 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205652 kb
Host smart-f2af6658-5cd4-42a1-b2d5-8a9595004f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704020942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.704020942
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.322039817
Short name T68
Test name
Test status
Simulation time 727154164 ps
CPU time 1.37 seconds
Started Aug 02 04:46:37 PM PDT 24
Finished Aug 02 04:46:38 PM PDT 24
Peak memory 229812 kb
Host smart-40e572db-f173-4ae7-88d0-8ea978f54590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322039817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.322039817
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2169544669
Short name T278
Test name
Test status
Simulation time 3006994605 ps
CPU time 8.62 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 205284 kb
Host smart-3ed5223d-ee9c-4f84-9380-2fc7813b293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169544669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2169544669
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2014152948
Short name T273
Test name
Test status
Simulation time 4004963602 ps
CPU time 6.87 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 213756 kb
Host smart-e07d1338-141d-4efd-9327-6550425f8dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014152948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2014152948
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.4165618892
Short name T14
Test name
Test status
Simulation time 220938213579 ps
CPU time 485.3 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 237228 kb
Host smart-17b12341-c26e-42cc-bf45-841bd817be38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165618892 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.4165618892
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.530476247
Short name T52
Test name
Test status
Simulation time 550251526 ps
CPU time 2.08 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205144 kb
Host smart-9e89a585-e319-483e-8f46-d571d001693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530476247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.530476247
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.537195952
Short name T179
Test name
Test status
Simulation time 83524337 ps
CPU time 0.78 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205216 kb
Host smart-3fc8c281-bc81-4d00-b0ab-00ca19ce352a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537195952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.537195952
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3022039822
Short name T264
Test name
Test status
Simulation time 8283150463 ps
CPU time 23.02 seconds
Started Aug 02 04:46:35 PM PDT 24
Finished Aug 02 04:46:58 PM PDT 24
Peak memory 215468 kb
Host smart-8c70b196-6fc5-45fe-9a7d-42696a78183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022039822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3022039822
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.789283245
Short name T234
Test name
Test status
Simulation time 7125119843 ps
CPU time 20.12 seconds
Started Aug 02 04:46:33 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 221940 kb
Host smart-e228e204-4083-450d-9503-fd102d5f4ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789283245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.789283245
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2452435811
Short name T187
Test name
Test status
Simulation time 437704676 ps
CPU time 1.04 seconds
Started Aug 02 04:46:30 PM PDT 24
Finished Aug 02 04:46:31 PM PDT 24
Peak memory 205284 kb
Host smart-bba8685f-aa88-4c1f-9a09-a56daba0f27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452435811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2452435811
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4113923566
Short name T16
Test name
Test status
Simulation time 459088275 ps
CPU time 0.99 seconds
Started Aug 02 04:46:41 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 205164 kb
Host smart-d5945c7c-72f5-4790-a016-c399c63cb6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113923566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4113923566
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2719208888
Short name T37
Test name
Test status
Simulation time 460609328 ps
CPU time 2.09 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:49 PM PDT 24
Peak memory 205140 kb
Host smart-2213f302-d538-4dcc-96de-ebace183d1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719208888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2719208888
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1470105440
Short name T210
Test name
Test status
Simulation time 430883875 ps
CPU time 0.93 seconds
Started Aug 02 04:46:31 PM PDT 24
Finished Aug 02 04:46:32 PM PDT 24
Peak memory 205164 kb
Host smart-2ffa94f7-1d39-4959-83b6-046839a21aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470105440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1470105440
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1088974061
Short name T243
Test name
Test status
Simulation time 328762752 ps
CPU time 1.36 seconds
Started Aug 02 04:46:41 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 205164 kb
Host smart-9779ceab-fee3-407a-abe6-2e64a48bd94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088974061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1088974061
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1559898576
Short name T267
Test name
Test status
Simulation time 62307331 ps
CPU time 0.89 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 215764 kb
Host smart-88038376-9919-41ff-a985-8e234cd078d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559898576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1559898576
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2777113870
Short name T67
Test name
Test status
Simulation time 2640335124 ps
CPU time 4.7 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:39 PM PDT 24
Peak memory 205620 kb
Host smart-fc127b73-fb25-4b13-927e-04acbac97df9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777113870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2777113870
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3407245999
Short name T56
Test name
Test status
Simulation time 531197813 ps
CPU time 1.36 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205152 kb
Host smart-adf2a1d6-9477-48d6-856b-136415bc5118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407245999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3407245999
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.175984246
Short name T260
Test name
Test status
Simulation time 358244761 ps
CPU time 1.59 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205196 kb
Host smart-935126be-cfbf-492c-9348-3dab4fffd5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175984246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.175984246
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1472881489
Short name T9
Test name
Test status
Simulation time 409960731 ps
CPU time 1.44 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205204 kb
Host smart-c2315f8f-49fb-4bd6-b8d2-625d69ea1304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472881489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1472881489
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1891452890
Short name T186
Test name
Test status
Simulation time 247292693 ps
CPU time 0.86 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205184 kb
Host smart-d7be2fb6-8313-4b00-be40-6c80b309de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891452890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1891452890
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.790834453
Short name T28
Test name
Test status
Simulation time 330351002 ps
CPU time 1.06 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205052 kb
Host smart-a325a213-7f9e-454c-9244-302591030b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790834453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.790834453
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.285827715
Short name T287
Test name
Test status
Simulation time 204228273 ps
CPU time 0.83 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205156 kb
Host smart-736a9c52-9e52-4a34-9a91-c40b13e81c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285827715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.285827715
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1009093206
Short name T284
Test name
Test status
Simulation time 174617835 ps
CPU time 0.73 seconds
Started Aug 02 04:46:42 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 205164 kb
Host smart-17cabb5b-1304-41d8-85e7-471b3ae0be4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009093206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1009093206
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2583798355
Short name T207
Test name
Test status
Simulation time 135800271 ps
CPU time 0.87 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 205208 kb
Host smart-a49baf12-d866-45cb-8fbe-04ebfd64c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583798355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2583798355
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2363444867
Short name T205
Test name
Test status
Simulation time 749178038 ps
CPU time 1.71 seconds
Started Aug 02 04:46:41 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 205204 kb
Host smart-44094f21-cfea-4115-b456-96f1b8ed03ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363444867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2363444867
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2195946815
Short name T268
Test name
Test status
Simulation time 287172254 ps
CPU time 0.94 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 213364 kb
Host smart-ed1d0313-476b-4845-8efb-f0be8861cc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195946815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2195946815
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1475356572
Short name T283
Test name
Test status
Simulation time 957295589 ps
CPU time 1.39 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205176 kb
Host smart-9afdb256-38fd-401b-8700-04d995f025cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475356572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1475356572
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.68861834
Short name T40
Test name
Test status
Simulation time 99067528 ps
CPU time 0.89 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 213396 kb
Host smart-0faa0c26-6582-48b9-87d0-9634cf2b6a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68861834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.68861834
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.256726426
Short name T128
Test name
Test status
Simulation time 4395072578 ps
CPU time 11.71 seconds
Started Aug 02 04:46:43 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 205348 kb
Host smart-338d50c9-ab28-491d-9789-08570e0e4222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256726426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.256726426
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2553092178
Short name T154
Test name
Test status
Simulation time 4571934418 ps
CPU time 6.6 seconds
Started Aug 02 04:46:34 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205708 kb
Host smart-a07fa7bd-648f-44b1-aa43-61210fdb00ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553092178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2553092178
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.375545752
Short name T304
Test name
Test status
Simulation time 3711940299 ps
CPU time 9.86 seconds
Started Aug 02 04:46:36 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205196 kb
Host smart-ef90e78f-65fc-4e33-8a1d-9d4528932afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375545752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.375545752
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.1944536721
Short name T10
Test name
Test status
Simulation time 111827457800 ps
CPU time 805.78 seconds
Started Aug 02 04:46:41 PM PDT 24
Finished Aug 02 05:00:07 PM PDT 24
Peak memory 246580 kb
Host smart-62e22fab-bb46-4785-a809-616831e55d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944536721 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.1944536721
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.590622562
Short name T233
Test name
Test status
Simulation time 71720347 ps
CPU time 0.82 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 205228 kb
Host smart-6d6fd0ff-3d3d-4f7a-94cf-dcdfbb18ea83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590622562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.590622562
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.75375052
Short name T132
Test name
Test status
Simulation time 14235768371 ps
CPU time 41.87 seconds
Started Aug 02 04:46:55 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 213864 kb
Host smart-f2d79eb3-3abc-4bed-9472-f2dd27662c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75375052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.75375052
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.671668525
Short name T151
Test name
Test status
Simulation time 2457695648 ps
CPU time 4.33 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:54 PM PDT 24
Peak memory 213924 kb
Host smart-07caf4ba-6c17-415e-a89a-b5dff46a5ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671668525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.671668525
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1068561664
Short name T315
Test name
Test status
Simulation time 2175357015 ps
CPU time 2.8 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 213768 kb
Host smart-62509cec-0d1b-4de7-90ca-7a56a4e38281
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068561664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1068561664
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.4042949217
Short name T74
Test name
Test status
Simulation time 6266867330 ps
CPU time 6.63 seconds
Started Aug 02 04:46:51 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 213808 kb
Host smart-c00a36bc-9fd1-4e85-ace1-a4eaa4c10dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042949217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4042949217
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1337579471
Short name T229
Test name
Test status
Simulation time 42201751 ps
CPU time 0.74 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 205156 kb
Host smart-0f9fedbd-9f6d-4777-8f29-0ca98e0a69c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337579471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1337579471
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3502086029
Short name T270
Test name
Test status
Simulation time 28392696041 ps
CPU time 65.26 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 218832 kb
Host smart-c52f9a10-5067-4cbd-9aa4-053bfb98c3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502086029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3502086029
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1519479343
Short name T182
Test name
Test status
Simulation time 5937970124 ps
CPU time 2.61 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 213796 kb
Host smart-93d1c84e-6869-498b-a78b-b23838f739e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519479343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1519479343
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1313188158
Short name T189
Test name
Test status
Simulation time 7032468211 ps
CPU time 3.19 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 213880 kb
Host smart-e7f91eea-8223-4e04-89e7-0dc101a5d92f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313188158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1313188158
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2496319062
Short name T160
Test name
Test status
Simulation time 1730230942 ps
CPU time 2.28 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 213800 kb
Host smart-1694c818-3018-43ad-a0db-5b29dfded582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496319062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2496319062
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2425702561
Short name T76
Test name
Test status
Simulation time 8417118132 ps
CPU time 19.08 seconds
Started Aug 02 04:46:59 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 213652 kb
Host smart-84d67d17-d7ec-472f-8781-7b54379e4595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425702561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2425702561
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3691869988
Short name T197
Test name
Test status
Simulation time 59049646 ps
CPU time 0.79 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 205156 kb
Host smart-895a755f-0064-4833-b09c-a3a534e767fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691869988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3691869988
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3060229556
Short name T144
Test name
Test status
Simulation time 16845805694 ps
CPU time 48.48 seconds
Started Aug 02 04:46:58 PM PDT 24
Finished Aug 02 04:47:47 PM PDT 24
Peak memory 213892 kb
Host smart-b6bacee3-0223-4518-b0d8-b27c9099320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060229556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3060229556
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.176251641
Short name T203
Test name
Test status
Simulation time 2685850564 ps
CPU time 3.73 seconds
Started Aug 02 04:46:57 PM PDT 24
Finished Aug 02 04:47:01 PM PDT 24
Peak memory 214984 kb
Host smart-b6c295e9-46c1-4dc4-9625-2d5315461031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176251641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.176251641
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1313351122
Short name T293
Test name
Test status
Simulation time 3738365300 ps
CPU time 4.61 seconds
Started Aug 02 04:46:59 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 213944 kb
Host smart-e3bbb341-d7ce-4153-8de7-e05b07f9a3ab
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313351122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1313351122
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2860098398
Short name T237
Test name
Test status
Simulation time 6526526751 ps
CPU time 9.38 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:12 PM PDT 24
Peak memory 213840 kb
Host smart-d8182c65-1659-4d8b-8994-a4f1d473b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860098398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2860098398
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.623167049
Short name T251
Test name
Test status
Simulation time 2438770932 ps
CPU time 3.12 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 213736 kb
Host smart-95f51945-0bee-4f8e-bc32-1d0a6f1fcf9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623167049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.623167049
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2570021794
Short name T314
Test name
Test status
Simulation time 38837325 ps
CPU time 0.75 seconds
Started Aug 02 04:46:59 PM PDT 24
Finished Aug 02 04:47:00 PM PDT 24
Peak memory 205144 kb
Host smart-49c53262-6bd4-4589-af5d-172ea375ff6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570021794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2570021794
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.744094673
Short name T214
Test name
Test status
Simulation time 2684347059 ps
CPU time 4.76 seconds
Started Aug 02 04:47:00 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 215608 kb
Host smart-4d788e33-4128-42ed-b0c9-3e89e396a80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744094673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.744094673
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2698141209
Short name T298
Test name
Test status
Simulation time 2517849280 ps
CPU time 2.35 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 213892 kb
Host smart-57e49ec3-ea42-49ea-8696-8c4061a639fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698141209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2698141209
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.813755880
Short name T195
Test name
Test status
Simulation time 9569436051 ps
CPU time 8.14 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 205768 kb
Host smart-3c64e9f0-4a5c-40f6-aa86-5e67dba5eaa5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813755880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.813755880
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.226825479
Short name T276
Test name
Test status
Simulation time 9133320308 ps
CPU time 12.63 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 205748 kb
Host smart-71decb7e-d80c-4468-8ed9-9842b80ce3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226825479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.226825479
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1397679975
Short name T140
Test name
Test status
Simulation time 12498752065 ps
CPU time 34.58 seconds
Started Aug 02 04:46:58 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 213788 kb
Host smart-deda75ae-cfe7-4e20-b6b5-19d90c55e4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397679975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1397679975
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3097558281
Short name T199
Test name
Test status
Simulation time 211875061 ps
CPU time 0.94 seconds
Started Aug 02 04:46:57 PM PDT 24
Finished Aug 02 04:46:58 PM PDT 24
Peak memory 205156 kb
Host smart-b8268df5-110e-4563-acd7-4233c7c0bea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097558281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3097558281
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3957465011
Short name T310
Test name
Test status
Simulation time 999495907 ps
CPU time 1.67 seconds
Started Aug 02 04:47:04 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205512 kb
Host smart-aeb395cd-1065-4d17-8c13-592dd86ffb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957465011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3957465011
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1890797392
Short name T257
Test name
Test status
Simulation time 6526318241 ps
CPU time 10.75 seconds
Started Aug 02 04:46:57 PM PDT 24
Finished Aug 02 04:47:08 PM PDT 24
Peak memory 213880 kb
Host smart-acab1f6b-6510-4c51-902a-6b569880337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890797392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1890797392
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1414019938
Short name T32
Test name
Test status
Simulation time 3096706785 ps
CPU time 3.46 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:06 PM PDT 24
Peak memory 205660 kb
Host smart-195c500b-d859-4f84-a687-6c0b6fb1cc84
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414019938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1414019938
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.205725035
Short name T282
Test name
Test status
Simulation time 3302256610 ps
CPU time 9.93 seconds
Started Aug 02 04:47:00 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 213740 kb
Host smart-15cfdbb5-aae7-4bb6-9de9-211bc1e7bac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205725035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.205725035
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3875980835
Short name T48
Test name
Test status
Simulation time 2416782222 ps
CPU time 7.49 seconds
Started Aug 02 04:46:57 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 213600 kb
Host smart-9b0795aa-a946-40d2-a41d-46be0d68c9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875980835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3875980835
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3258883446
Short name T217
Test name
Test status
Simulation time 45744530 ps
CPU time 0.75 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 205152 kb
Host smart-a359148f-894f-4f6f-b341-dd058a4be3c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258883446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3258883446
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.817473085
Short name T297
Test name
Test status
Simulation time 4943938985 ps
CPU time 12.9 seconds
Started Aug 02 04:46:58 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 213804 kb
Host smart-ab4870d8-3811-4391-b8d1-9a90d71298db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817473085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.817473085
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4252244695
Short name T271
Test name
Test status
Simulation time 4107995609 ps
CPU time 5.95 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 04:47:07 PM PDT 24
Peak memory 213800 kb
Host smart-f894d8dd-eb91-4e70-a3cf-141480a98ad4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252244695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.4252244695
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.557905733
Short name T2
Test name
Test status
Simulation time 6311994417 ps
CPU time 18.92 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 213888 kb
Host smart-0517852c-2bcb-4860-a798-da8909404564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557905733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.557905733
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2663341077
Short name T42
Test name
Test status
Simulation time 1346991166 ps
CPU time 2 seconds
Started Aug 02 04:47:00 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 213448 kb
Host smart-6df09832-179f-454b-91c5-1faa1732d2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663341077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2663341077
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1838094012
Short name T295
Test name
Test status
Simulation time 140307943 ps
CPU time 0.78 seconds
Started Aug 02 04:46:57 PM PDT 24
Finished Aug 02 04:46:58 PM PDT 24
Peak memory 205184 kb
Host smart-03a13272-d849-44de-a0fe-433565dffb51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838094012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1838094012
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2054764171
Short name T220
Test name
Test status
Simulation time 3832721817 ps
CPU time 6.7 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 214780 kb
Host smart-65779750-eb13-4bc6-a607-40412b934718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054764171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2054764171
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.437688734
Short name T224
Test name
Test status
Simulation time 12261379106 ps
CPU time 18.55 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 213832 kb
Host smart-1e74a1e9-764c-47ed-8108-ddb064ae277b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437688734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.437688734
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.140297866
Short name T72
Test name
Test status
Simulation time 4392761164 ps
CPU time 8.39 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 213884 kb
Host smart-76c8d911-37a6-471a-a90c-29671826592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140297866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.140297866
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1073839868
Short name T285
Test name
Test status
Simulation time 9366204846 ps
CPU time 23.39 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 213580 kb
Host smart-c91c9c61-d873-42ef-8ce7-241d39fbb320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073839868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1073839868
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1735259225
Short name T239
Test name
Test status
Simulation time 840208340 ps
CPU time 1.69 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 205468 kb
Host smart-83e62b19-1722-4072-afde-007962b6fd48
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735259225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1735259225
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3650399086
Short name T73
Test name
Test status
Simulation time 2687320220 ps
CPU time 4.84 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:06 PM PDT 24
Peak memory 213812 kb
Host smart-3a5cd8dc-f42e-42e6-8399-c762c7749af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650399086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3650399086
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2322605963
Short name T6
Test name
Test status
Simulation time 3626432221 ps
CPU time 5.49 seconds
Started Aug 02 04:46:58 PM PDT 24
Finished Aug 02 04:47:03 PM PDT 24
Peak memory 205608 kb
Host smart-e9eb6e07-d46d-4d01-9cf3-41fdccef7069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322605963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2322605963
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2677850717
Short name T245
Test name
Test status
Simulation time 96414785 ps
CPU time 0.78 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:03 PM PDT 24
Peak memory 205224 kb
Host smart-2c0327e4-29e1-4698-bc95-fd3bc1c1a0f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677850717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2677850717
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.276228525
Short name T311
Test name
Test status
Simulation time 4568235254 ps
CPU time 4.59 seconds
Started Aug 02 04:47:00 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 213796 kb
Host smart-2741d531-dcc6-48b6-b1e9-63851b91d018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276228525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.276228525
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1599549990
Short name T279
Test name
Test status
Simulation time 2207932744 ps
CPU time 2.7 seconds
Started Aug 02 04:47:04 PM PDT 24
Finished Aug 02 04:47:07 PM PDT 24
Peak memory 213788 kb
Host smart-306e5e6f-0bc2-47e7-b65b-5a3cf5cd61a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599549990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1599549990
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.787580348
Short name T155
Test name
Test status
Simulation time 5042605431 ps
CPU time 6.87 seconds
Started Aug 02 04:47:00 PM PDT 24
Finished Aug 02 04:47:07 PM PDT 24
Peak memory 205596 kb
Host smart-1e1d2d7b-d6a6-4d48-98a9-67640a54cbae
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787580348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.787580348
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1336339245
Short name T188
Test name
Test status
Simulation time 2701951353 ps
CPU time 5.85 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:08 PM PDT 24
Peak memory 205692 kb
Host smart-530e1887-3943-4b7d-bd0e-392929a5c6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336339245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1336339245
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1123747969
Short name T20
Test name
Test status
Simulation time 2514679067 ps
CPU time 3.66 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:13 PM PDT 24
Peak memory 213732 kb
Host smart-720225c5-1d58-45eb-97e8-d106ec2351ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123747969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1123747969
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1154074972
Short name T53
Test name
Test status
Simulation time 40267093 ps
CPU time 0.76 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:12 PM PDT 24
Peak memory 205180 kb
Host smart-825e4bab-cbd0-40f0-94ce-2132a6b55189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154074972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1154074972
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.784541149
Short name T263
Test name
Test status
Simulation time 6247532173 ps
CPU time 9.68 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 213832 kb
Host smart-1804604b-0ead-4606-8d75-82e0491b5acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784541149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.784541149
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.142613679
Short name T196
Test name
Test status
Simulation time 7894685791 ps
CPU time 11.71 seconds
Started Aug 02 04:47:12 PM PDT 24
Finished Aug 02 04:47:24 PM PDT 24
Peak memory 222000 kb
Host smart-e1fb75a0-6299-4c96-bb3d-2c5307da5e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142613679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.142613679
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3614962023
Short name T254
Test name
Test status
Simulation time 1526504364 ps
CPU time 2.67 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:06 PM PDT 24
Peak memory 205444 kb
Host smart-7d1e6f67-0187-4b36-b60a-c11fb327e3bb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614962023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3614962023
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.56013349
Short name T312
Test name
Test status
Simulation time 6239797938 ps
CPU time 4.75 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:16 PM PDT 24
Peak memory 213788 kb
Host smart-cec195e3-a7e4-4499-8203-9031cadcc8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56013349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.56013349
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1452441942
Short name T303
Test name
Test status
Simulation time 5834054521 ps
CPU time 4.01 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:06 PM PDT 24
Peak memory 205476 kb
Host smart-9db8c19e-59c2-4c3a-a1ac-ba40c807bbf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452441942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1452441942
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1466472944
Short name T231
Test name
Test status
Simulation time 89389318 ps
CPU time 0.85 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205216 kb
Host smart-ede68085-a92d-46df-80d4-ed3ee4362e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466472944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1466472944
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.913781670
Short name T286
Test name
Test status
Simulation time 38951066499 ps
CPU time 45.55 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 213984 kb
Host smart-2da5eef4-69f9-4cb7-9fae-c6bd18468a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913781670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.913781670
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2362787638
Short name T222
Test name
Test status
Simulation time 1033416702 ps
CPU time 3.54 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205572 kb
Host smart-486c618c-b456-4ed8-a7b3-38891caff569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362787638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2362787638
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1538167348
Short name T184
Test name
Test status
Simulation time 1739060735 ps
CPU time 2.08 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 205644 kb
Host smart-14da4a3b-b04b-4610-84a6-76c6a13e089a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538167348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1538167348
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.2713442180
Short name T308
Test name
Test status
Simulation time 321908553 ps
CPU time 1.31 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:46 PM PDT 24
Peak memory 205172 kb
Host smart-9f6d3117-c7b0-4d80-952f-bd358e17c22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713442180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2713442180
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.507422314
Short name T191
Test name
Test status
Simulation time 1185217989 ps
CPU time 3.91 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205080 kb
Host smart-9db23664-5241-4d28-8637-4953d51f6086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507422314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.507422314
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1963475685
Short name T153
Test name
Test status
Simulation time 725642846 ps
CPU time 2.6 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:49 PM PDT 24
Peak memory 205472 kb
Host smart-6f85af35-36f6-460a-9c9d-e98ee055a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963475685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1963475685
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2437478304
Short name T69
Test name
Test status
Simulation time 1124595375 ps
CPU time 2.65 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:49 PM PDT 24
Peak memory 229864 kb
Host smart-10dc29cc-6ad4-4da1-8860-314f5836a0db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437478304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2437478304
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1361894034
Short name T255
Test name
Test status
Simulation time 6634699370 ps
CPU time 17.6 seconds
Started Aug 02 04:46:47 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 213712 kb
Host smart-13deeb49-27e9-48b7-99d0-b8e48d20e342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361894034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1361894034
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1950709812
Short name T17
Test name
Test status
Simulation time 37439339870 ps
CPU time 800.27 seconds
Started Aug 02 04:46:43 PM PDT 24
Finished Aug 02 05:00:04 PM PDT 24
Peak memory 230588 kb
Host smart-ce3e7527-e42d-4371-bd17-eab6ad75dc48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950709812 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1950709812
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1525600352
Short name T66
Test name
Test status
Simulation time 164123762 ps
CPU time 0.93 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:03 PM PDT 24
Peak memory 205164 kb
Host smart-1efef66a-7e0c-42d5-8700-b909a3a9f424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525600352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1525600352
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3492957821
Short name T38
Test name
Test status
Simulation time 2743007323 ps
CPU time 2.82 seconds
Started Aug 02 04:47:02 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 213688 kb
Host smart-633426d4-5a8a-4ae1-ab4a-c973d4575867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492957821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3492957821
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1629503010
Short name T299
Test name
Test status
Simulation time 133866258 ps
CPU time 0.73 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:18 PM PDT 24
Peak memory 205236 kb
Host smart-c51ce0db-af3d-4cd8-8863-b72fd3f41b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629503010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1629503010
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3972921564
Short name T5
Test name
Test status
Simulation time 7428509582 ps
CPU time 21.42 seconds
Started Aug 02 04:47:04 PM PDT 24
Finished Aug 02 04:47:26 PM PDT 24
Peak memory 213640 kb
Host smart-8290ec12-a42f-4bfd-aabd-d4a6121b2243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972921564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3972921564
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3051932741
Short name T180
Test name
Test status
Simulation time 69537074 ps
CPU time 0.76 seconds
Started Aug 02 04:47:04 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205172 kb
Host smart-c20b1d13-fc52-4c6f-9f03-c573f4c1d7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051932741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3051932741
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3777216501
Short name T274
Test name
Test status
Simulation time 1214144319 ps
CPU time 4.33 seconds
Started Aug 02 04:47:01 PM PDT 24
Finished Aug 02 04:47:06 PM PDT 24
Peak memory 213500 kb
Host smart-075ca144-0c6c-4506-8e0a-6e7283addfec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777216501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3777216501
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3413365006
Short name T280
Test name
Test status
Simulation time 95592217 ps
CPU time 0.77 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 205160 kb
Host smart-31be336f-aca8-4fb3-a687-33e622d20f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413365006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3413365006
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.4140265260
Short name T15
Test name
Test status
Simulation time 6711880453 ps
CPU time 17.47 seconds
Started Aug 02 04:47:15 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 213768 kb
Host smart-3e1c3b2f-f086-416b-a7b0-ab5ea8339b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140265260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.4140265260
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1141103243
Short name T289
Test name
Test status
Simulation time 170596180 ps
CPU time 0.82 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 205180 kb
Host smart-9a693218-2519-4552-b74a-0cb88da9c0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141103243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1141103243
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1014138774
Short name T46
Test name
Test status
Simulation time 2420885665 ps
CPU time 2.47 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205448 kb
Host smart-2584baf4-9ff9-45b4-8da4-383e7877f7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014138774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1014138774
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2966725271
Short name T247
Test name
Test status
Simulation time 174693876 ps
CPU time 0.96 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 205180 kb
Host smart-0118a22c-3c39-4ea5-bf85-47cb1e3fd713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966725271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2966725271
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2593222564
Short name T142
Test name
Test status
Simulation time 5420128271 ps
CPU time 8.98 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 213676 kb
Host smart-3e0da313-e362-4788-8518-341c9c284f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593222564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2593222564
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3965502049
Short name T200
Test name
Test status
Simulation time 151289070 ps
CPU time 0.81 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 205164 kb
Host smart-b56ad506-267d-41d4-b4e7-29fcc03585f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965502049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3965502049
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2769062083
Short name T50
Test name
Test status
Simulation time 5291374659 ps
CPU time 15.22 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 205448 kb
Host smart-09309256-96f6-4eef-bba3-bcf51d4cb452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769062083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2769062083
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3268063459
Short name T288
Test name
Test status
Simulation time 90093959 ps
CPU time 0.85 seconds
Started Aug 02 04:47:04 PM PDT 24
Finished Aug 02 04:47:05 PM PDT 24
Peak memory 205172 kb
Host smart-40ce5c4a-b89e-4f4d-8175-f43c6f1e0064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268063459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3268063459
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.550353956
Short name T134
Test name
Test status
Simulation time 7066527880 ps
CPU time 20.88 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 213692 kb
Host smart-b0a94e4b-1778-48e3-88a5-a711ef985f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550353956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.550353956
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.405642133
Short name T261
Test name
Test status
Simulation time 32220069 ps
CPU time 0.77 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 205124 kb
Host smart-a83311ce-0d19-46e5-a482-308b7f8ec78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405642133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.405642133
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2415166762
Short name T212
Test name
Test status
Simulation time 150840714 ps
CPU time 1.05 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 205184 kb
Host smart-9cb2b569-01d3-434f-af60-e160a414f3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415166762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2415166762
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.646384477
Short name T141
Test name
Test status
Simulation time 2811223055 ps
CPU time 6.96 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 205592 kb
Host smart-90127d4a-d08f-42ca-a85c-20ca2987dd0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646384477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.646384477
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2503170309
Short name T71
Test name
Test status
Simulation time 60062753 ps
CPU time 0.78 seconds
Started Aug 02 04:46:39 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 205172 kb
Host smart-2f66851f-f139-468e-afe7-311821b4a4fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503170309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2503170309
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.167510809
Short name T135
Test name
Test status
Simulation time 9155116441 ps
CPU time 7.92 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 213976 kb
Host smart-ee6482d8-bc7b-4d4d-938b-019a0cd167a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167510809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.167510809
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.411159523
Short name T242
Test name
Test status
Simulation time 12832048813 ps
CPU time 8.14 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 213796 kb
Host smart-f7291005-d3f3-4351-b5bd-67920168792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411159523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.411159523
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3834164378
Short name T256
Test name
Test status
Simulation time 13014591199 ps
CPU time 27.18 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 213896 kb
Host smart-1db592c4-485e-462e-bc4b-b864a97122b4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834164378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3834164378
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.366822354
Short name T4
Test name
Test status
Simulation time 512063822 ps
CPU time 2.01 seconds
Started Aug 02 04:46:43 PM PDT 24
Finished Aug 02 04:46:45 PM PDT 24
Peak memory 205080 kb
Host smart-861ac687-4d0d-4631-8fa5-a74c3def742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366822354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.366822354
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1819817159
Short name T292
Test name
Test status
Simulation time 221231758 ps
CPU time 0.95 seconds
Started Aug 02 04:46:47 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205208 kb
Host smart-38d4b831-d126-4ba8-b500-a50c7186b3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819817159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1819817159
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1871930240
Short name T206
Test name
Test status
Simulation time 1865047050 ps
CPU time 4.9 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:50 PM PDT 24
Peak memory 205580 kb
Host smart-acf10ce7-e794-42ef-bb51-1c20ede62951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871930240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1871930240
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3290651743
Short name T55
Test name
Test status
Simulation time 429250993 ps
CPU time 2.05 seconds
Started Aug 02 04:46:39 PM PDT 24
Finished Aug 02 04:46:41 PM PDT 24
Peak memory 229736 kb
Host smart-b3b687aa-0ae1-4447-a548-64eebd4a4d52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290651743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3290651743
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3962452428
Short name T43
Test name
Test status
Simulation time 9239711559 ps
CPU time 23.39 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 213772 kb
Host smart-e8b905e6-fd72-433c-a2e2-b5cadca2223b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962452428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3962452428
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3948109158
Short name T18
Test name
Test status
Simulation time 418494626607 ps
CPU time 2325.99 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 05:25:30 PM PDT 24
Peak memory 260480 kb
Host smart-3bae0258-bf7f-4ae3-acc2-598f8b33785f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948109158 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3948109158
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3068321117
Short name T190
Test name
Test status
Simulation time 111158679 ps
CPU time 0.74 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 205184 kb
Host smart-648c60ea-4804-45fe-8b38-90634579d683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068321117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3068321117
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3770594953
Short name T133
Test name
Test status
Simulation time 3988442885 ps
CPU time 1.81 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 213684 kb
Host smart-6ec24aa9-5cb7-4c6c-93b1-82cbad0ae181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770594953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3770594953
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2160591009
Short name T34
Test name
Test status
Simulation time 167039862 ps
CPU time 0.84 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:12 PM PDT 24
Peak memory 205096 kb
Host smart-95aa03d7-788d-4e44-9666-fd02429782d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160591009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2160591009
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1861069289
Short name T130
Test name
Test status
Simulation time 7129329410 ps
CPU time 3.45 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 213612 kb
Host smart-3dd6a10f-ce54-4851-976b-43711597c01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861069289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1861069289
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2257664956
Short name T262
Test name
Test status
Simulation time 131582943 ps
CPU time 0.7 seconds
Started Aug 02 04:46:59 PM PDT 24
Finished Aug 02 04:47:00 PM PDT 24
Peak memory 205192 kb
Host smart-f06fd242-6cd5-4208-920e-b9a3afa910db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257664956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2257664956
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.4021791134
Short name T156
Test name
Test status
Simulation time 6300154099 ps
CPU time 5.3 seconds
Started Aug 02 04:47:24 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 213688 kb
Host smart-ccd62e29-e72a-44e8-a8e9-cf2739500aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021791134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.4021791134
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.4035872525
Short name T218
Test name
Test status
Simulation time 57165123 ps
CPU time 0.71 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:10 PM PDT 24
Peak memory 205184 kb
Host smart-7cb5e2f0-8c26-4974-9fea-bdbb4d258402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035872525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4035872525
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2073457328
Short name T183
Test name
Test status
Simulation time 38067991 ps
CPU time 0.75 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 205092 kb
Host smart-32a0a6e4-cb1b-4ac5-ba8f-d357fcb44420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073457328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2073457328
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3865079912
Short name T209
Test name
Test status
Simulation time 1615721326 ps
CPU time 2.22 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:15 PM PDT 24
Peak memory 213480 kb
Host smart-bcdfe9f0-ceaa-46a1-a707-23634b58f449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865079912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3865079912
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3239628021
Short name T33
Test name
Test status
Simulation time 95107422 ps
CPU time 0.81 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 205220 kb
Host smart-105154b7-30b7-44e5-abfe-c9b76a73ebd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239628021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3239628021
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1123049311
Short name T137
Test name
Test status
Simulation time 4346387617 ps
CPU time 13.26 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:26 PM PDT 24
Peak memory 204752 kb
Host smart-1a2e6e52-9721-4652-bdfe-2ed3bd2fd65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123049311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1123049311
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.854677462
Short name T194
Test name
Test status
Simulation time 51795342 ps
CPU time 0.75 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 205068 kb
Host smart-c5a5a445-c85d-4bf2-a4e0-3b7564f83ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854677462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.854677462
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.4656012
Short name T226
Test name
Test status
Simulation time 2789215707 ps
CPU time 3.89 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:13 PM PDT 24
Peak memory 213664 kb
Host smart-2bb1d8a2-fa5c-4388-b9e4-411340e3155a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4656012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.4656012
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3017361892
Short name T208
Test name
Test status
Simulation time 72720684 ps
CPU time 0.84 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 204516 kb
Host smart-4154b499-bbc6-4577-9fe1-464be032cfbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017361892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3017361892
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.4105876059
Short name T138
Test name
Test status
Simulation time 1826793149 ps
CPU time 6.09 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:16 PM PDT 24
Peak memory 213488 kb
Host smart-8bca1752-bc01-4e31-a74d-a3d30f5b61d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105876059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4105876059
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2699559373
Short name T294
Test name
Test status
Simulation time 101529291 ps
CPU time 0.92 seconds
Started Aug 02 04:47:03 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 205180 kb
Host smart-ef4d7238-a38d-4fb5-bffc-d6e98911dfb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699559373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2699559373
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2029666122
Short name T277
Test name
Test status
Simulation time 4968959236 ps
CPU time 4.91 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:15 PM PDT 24
Peak memory 213604 kb
Host smart-a664c8f5-9ba6-4907-b84c-ac12882c2dab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029666122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2029666122
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1992144507
Short name T265
Test name
Test status
Simulation time 91004233 ps
CPU time 0.74 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 205128 kb
Host smart-445b5ddb-6748-4e07-a06f-55ff0d79ef09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992144507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1992144507
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.4042981953
Short name T136
Test name
Test status
Simulation time 2102714598 ps
CPU time 2.09 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:15 PM PDT 24
Peak memory 213552 kb
Host smart-c12dc4c4-02ab-4354-b7c9-d14db6455100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042981953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.4042981953
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3598758624
Short name T258
Test name
Test status
Simulation time 232248698 ps
CPU time 0.72 seconds
Started Aug 02 04:46:52 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 205164 kb
Host smart-8b2f042c-2096-4b70-9cc3-4acc18ac60ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598758624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3598758624
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3599154290
Short name T29
Test name
Test status
Simulation time 16497743838 ps
CPU time 11.78 seconds
Started Aug 02 04:46:39 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 216528 kb
Host smart-6888a2ef-daba-4a6a-a3c6-d50822d668b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599154290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3599154290
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1794507731
Short name T24
Test name
Test status
Simulation time 1893379438 ps
CPU time 2.56 seconds
Started Aug 02 04:46:45 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205520 kb
Host smart-871167ad-e837-43ba-89e0-91598e975dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794507731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1794507731
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2667635290
Short name T232
Test name
Test status
Simulation time 1310148136 ps
CPU time 2.14 seconds
Started Aug 02 04:46:41 PM PDT 24
Finished Aug 02 04:46:43 PM PDT 24
Peak memory 213784 kb
Host smart-da1c61f3-52b6-4630-9e0a-1708e3c4151f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667635290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2667635290
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.4133955693
Short name T266
Test name
Test status
Simulation time 138389523 ps
CPU time 1.08 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 205204 kb
Host smart-60bbb736-7c3a-403e-8459-606a21b5c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133955693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.4133955693
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.791387431
Short name T192
Test name
Test status
Simulation time 2020053737 ps
CPU time 6.76 seconds
Started Aug 02 04:46:43 PM PDT 24
Finished Aug 02 04:46:50 PM PDT 24
Peak memory 205440 kb
Host smart-fed00821-8323-4d28-9fbe-161f43d6b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791387431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.791387431
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2897837190
Short name T35
Test name
Test status
Simulation time 1134996374 ps
CPU time 2.32 seconds
Started Aug 02 04:46:40 PM PDT 24
Finished Aug 02 04:46:42 PM PDT 24
Peak memory 228832 kb
Host smart-afd888f3-5ccd-4519-96fa-53689be7f38e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897837190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2897837190
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.4025044099
Short name T250
Test name
Test status
Simulation time 2645761372 ps
CPU time 8.51 seconds
Started Aug 02 04:46:44 PM PDT 24
Finished Aug 02 04:46:53 PM PDT 24
Peak memory 213676 kb
Host smart-ef7f0ac9-e65a-4ccc-b22e-5d916abbe19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025044099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.4025044099
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3656085148
Short name T58
Test name
Test status
Simulation time 235145935835 ps
CPU time 1813.41 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 05:17:00 PM PDT 24
Peak memory 248764 kb
Host smart-25e4f0f7-ba92-423d-9389-04069222062a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656085148 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.3656085148
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.752467411
Short name T215
Test name
Test status
Simulation time 92259100 ps
CPU time 0.74 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 205044 kb
Host smart-7e69d261-fb9a-42d3-9669-5ff1e751403d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752467411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.752467411
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.4207125214
Short name T131
Test name
Test status
Simulation time 3407615379 ps
CPU time 6.13 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 213620 kb
Host smart-056ceed0-e25b-4cc8-aa9f-050ae3192e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207125214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.4207125214
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3790307036
Short name T300
Test name
Test status
Simulation time 76220638 ps
CPU time 0.78 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 205168 kb
Host smart-84ccabf2-88c5-41ea-83a1-f25460ea031f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790307036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3790307036
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1293781570
Short name T47
Test name
Test status
Simulation time 8853755929 ps
CPU time 23.3 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:42 PM PDT 24
Peak memory 205448 kb
Host smart-2cc3c6ef-caf2-41a7-9371-e9d01233cb2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293781570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1293781570
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.888636836
Short name T198
Test name
Test status
Simulation time 99061040 ps
CPU time 0.76 seconds
Started Aug 02 04:47:07 PM PDT 24
Finished Aug 02 04:47:08 PM PDT 24
Peak memory 205172 kb
Host smart-053b0ccb-786d-4a47-8dce-6f895f3ecaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888636836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.888636836
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1482502942
Short name T45
Test name
Test status
Simulation time 3075304675 ps
CPU time 5.18 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 205384 kb
Host smart-d4b7dc3d-ff93-4a12-80c5-f501e34aacfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482502942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1482502942
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2953534700
Short name T65
Test name
Test status
Simulation time 72038689 ps
CPU time 0.85 seconds
Started Aug 02 04:47:24 PM PDT 24
Finished Aug 02 04:47:25 PM PDT 24
Peak memory 205156 kb
Host smart-68fe4633-306e-4ecc-8e9e-42152e00cabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953534700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2953534700
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3432692431
Short name T161
Test name
Test status
Simulation time 12740092876 ps
CPU time 9.32 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 205560 kb
Host smart-ba9c374f-3695-4f86-b4d9-423e711b6054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432692431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3432692431
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2022652814
Short name T313
Test name
Test status
Simulation time 80269502 ps
CPU time 0.73 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 205236 kb
Host smart-f3de2c7b-6a02-44be-8828-72edaed83375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022652814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2022652814
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3373104364
Short name T19
Test name
Test status
Simulation time 3891785224 ps
CPU time 3.74 seconds
Started Aug 02 04:47:26 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 213628 kb
Host smart-09d6c3a3-690c-4f57-8ed3-a22e6086c19d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373104364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3373104364
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1179016173
Short name T178
Test name
Test status
Simulation time 75789033 ps
CPU time 0.96 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 205208 kb
Host smart-73901923-4b14-4c73-83b8-3d3e0a95a87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179016173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1179016173
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3570401094
Short name T281
Test name
Test status
Simulation time 9396859551 ps
CPU time 23.62 seconds
Started Aug 02 04:47:09 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 213624 kb
Host smart-f6db0f9a-f4d2-49fd-8f07-212d67f95844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570401094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3570401094
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2804889769
Short name T177
Test name
Test status
Simulation time 48857652 ps
CPU time 0.77 seconds
Started Aug 02 04:47:16 PM PDT 24
Finished Aug 02 04:47:17 PM PDT 24
Peak memory 205076 kb
Host smart-a3e5edc1-2736-4a63-b288-7414d53d6e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804889769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2804889769
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1601175558
Short name T176
Test name
Test status
Simulation time 5159027322 ps
CPU time 4.95 seconds
Started Aug 02 04:47:08 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 205512 kb
Host smart-7004c328-f9cf-4211-b34b-e9d2d08f8708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601175558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1601175558
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1599076256
Short name T252
Test name
Test status
Simulation time 151648742 ps
CPU time 0.87 seconds
Started Aug 02 04:47:08 PM PDT 24
Finished Aug 02 04:47:09 PM PDT 24
Peak memory 205300 kb
Host smart-170515d8-b99b-481f-8a8f-76e61a2ae69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599076256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1599076256
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.911164191
Short name T272
Test name
Test status
Simulation time 4369309459 ps
CPU time 11.61 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 205500 kb
Host smart-189a37e1-943f-4438-9fb7-0c751fbf9e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911164191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.911164191
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.54127000
Short name T118
Test name
Test status
Simulation time 61658403 ps
CPU time 0.77 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 205164 kb
Host smart-2494e66d-6786-4e95-8a12-5776ff51f0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54127000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.54127000
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.281458239
Short name T244
Test name
Test status
Simulation time 9671004276 ps
CPU time 14.84 seconds
Started Aug 02 04:47:26 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 213712 kb
Host smart-e072be99-7122-4022-a92a-f52e16647760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281458239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.281458239
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2531296086
Short name T248
Test name
Test status
Simulation time 41126788 ps
CPU time 0.8 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 205004 kb
Host smart-553fb86e-91c7-463e-969a-c32054c451f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531296086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2531296086
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3556619178
Short name T145
Test name
Test status
Simulation time 2582300099 ps
CPU time 8.41 seconds
Started Aug 02 04:47:22 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 205576 kb
Host smart-d508a2bb-574a-488e-a67c-a0f0258697d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556619178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3556619178
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.448557676
Short name T241
Test name
Test status
Simulation time 155947901 ps
CPU time 0.78 seconds
Started Aug 02 04:46:49 PM PDT 24
Finished Aug 02 04:46:50 PM PDT 24
Peak memory 205252 kb
Host smart-920cdf15-7fbe-4008-aa95-726ceda53bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448557676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.448557676
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.4121550072
Short name T307
Test name
Test status
Simulation time 7744541652 ps
CPU time 19.3 seconds
Started Aug 02 04:46:54 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 213784 kb
Host smart-c6a554f0-5ec2-45ae-a1f6-9b4699f63653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121550072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.4121550072
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.444559114
Short name T25
Test name
Test status
Simulation time 3529489692 ps
CPU time 8.35 seconds
Started Aug 02 04:46:49 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 213800 kb
Host smart-49a65f20-82fc-49e5-926e-2f8c37f34798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444559114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.444559114
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.915175698
Short name T306
Test name
Test status
Simulation time 14228940270 ps
CPU time 12.21 seconds
Started Aug 02 04:46:48 PM PDT 24
Finished Aug 02 04:47:01 PM PDT 24
Peak memory 213812 kb
Host smart-5354aea3-0c24-46ad-ab72-ddc32def5225
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915175698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.915175698
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3155261053
Short name T44
Test name
Test status
Simulation time 449729028 ps
CPU time 1.08 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 205140 kb
Host smart-428e94ab-4730-4293-b0c3-87bde3773c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155261053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3155261053
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3889632633
Short name T236
Test name
Test status
Simulation time 3486921778 ps
CPU time 9.12 seconds
Started Aug 02 04:46:47 PM PDT 24
Finished Aug 02 04:46:56 PM PDT 24
Peak memory 213832 kb
Host smart-4937c406-f1df-44ca-837a-d19cc9df1d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889632633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3889632633
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1920462694
Short name T228
Test name
Test status
Simulation time 7293551642 ps
CPU time 11.04 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:47:01 PM PDT 24
Peak memory 205384 kb
Host smart-16a92d7e-77ed-4017-ae84-91e7d5ca3338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920462694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1920462694
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1092834476
Short name T223
Test name
Test status
Simulation time 115002571 ps
CPU time 0.79 seconds
Started Aug 02 04:46:47 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205144 kb
Host smart-75ec62fc-dbc7-4925-ad96-9cf7dc4294fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092834476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1092834476
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1556306570
Short name T157
Test name
Test status
Simulation time 4707290882 ps
CPU time 8.81 seconds
Started Aug 02 04:46:51 PM PDT 24
Finished Aug 02 04:47:00 PM PDT 24
Peak memory 213788 kb
Host smart-3b811edb-7f0c-4d5e-9a13-46a425263718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556306570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1556306570
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.32656504
Short name T225
Test name
Test status
Simulation time 1254805316 ps
CPU time 1.4 seconds
Started Aug 02 04:46:46 PM PDT 24
Finished Aug 02 04:46:48 PM PDT 24
Peak memory 205440 kb
Host smart-4a46e930-c22c-4d5c-9b03-48956cd93d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32656504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.32656504
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2255622110
Short name T185
Test name
Test status
Simulation time 2518103429 ps
CPU time 8.21 seconds
Started Aug 02 04:46:48 PM PDT 24
Finished Aug 02 04:46:56 PM PDT 24
Peak memory 213776 kb
Host smart-4de46d92-474a-4c96-bb6d-35e189e324f3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255622110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2255622110
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3124367138
Short name T296
Test name
Test status
Simulation time 1031563607 ps
CPU time 1.45 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 205088 kb
Host smart-12b4e6bc-1b6b-4737-bd42-d345f43f11df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124367138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3124367138
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3481378407
Short name T204
Test name
Test status
Simulation time 7298552782 ps
CPU time 6.74 seconds
Started Aug 02 04:46:48 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 205712 kb
Host smart-21a8ee3c-7f90-44b9-91cb-898d667ddb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481378407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3481378407
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1514206998
Short name T275
Test name
Test status
Simulation time 7501000370 ps
CPU time 21.14 seconds
Started Aug 02 04:46:48 PM PDT 24
Finished Aug 02 04:47:09 PM PDT 24
Peak memory 213704 kb
Host smart-9238acbe-85d1-4b10-8934-d4018cd0f99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514206998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1514206998
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.2941633834
Short name T12
Test name
Test status
Simulation time 382645696583 ps
CPU time 2208.91 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 05:23:45 PM PDT 24
Peak memory 254764 kb
Host smart-c61a0021-e36b-4086-b401-86df8afd7eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941633834 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.2941633834
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2626774826
Short name T213
Test name
Test status
Simulation time 276632872 ps
CPU time 0.76 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 205164 kb
Host smart-9d7b4862-8f76-40d6-8a48-384efeb7d880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626774826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2626774826
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.275446012
Short name T31
Test name
Test status
Simulation time 9578594570 ps
CPU time 14.06 seconds
Started Aug 02 04:46:47 PM PDT 24
Finished Aug 02 04:47:01 PM PDT 24
Peak memory 213868 kb
Host smart-198e72eb-d8fc-496e-adbb-8b7853ccb80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275446012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.275446012
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.68283392
Short name T230
Test name
Test status
Simulation time 5409610543 ps
CPU time 3.6 seconds
Started Aug 02 04:46:48 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 213872 kb
Host smart-75a9c0fb-ed21-47ce-bd9d-557c301b8668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68283392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.68283392
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.283278438
Short name T1
Test name
Test status
Simulation time 1903972880 ps
CPU time 6.02 seconds
Started Aug 02 04:46:49 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 213740 kb
Host smart-b9a7e854-5a63-4aca-9ec0-6d32f7a81cd8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283278438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.283278438
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.1730182162
Short name T158
Test name
Test status
Simulation time 283472094 ps
CPU time 1.47 seconds
Started Aug 02 04:46:53 PM PDT 24
Finished Aug 02 04:46:54 PM PDT 24
Peak memory 205152 kb
Host smart-288a47a8-2e6d-49ff-8ebb-1f9d5fe9e7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730182162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1730182162
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.4009736438
Short name T259
Test name
Test status
Simulation time 3349994251 ps
CPU time 9.84 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:47:00 PM PDT 24
Peak memory 213836 kb
Host smart-d968a14f-27c5-474a-9399-5bdf847fa684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009736438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4009736438
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2846039595
Short name T13
Test name
Test status
Simulation time 3352277755 ps
CPU time 5.58 seconds
Started Aug 02 04:46:51 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 213636 kb
Host smart-268238ea-37c2-43bb-bebd-261100d62a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846039595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2846039595
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.712812855
Short name T221
Test name
Test status
Simulation time 56649548 ps
CPU time 0.72 seconds
Started Aug 02 04:46:56 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 205184 kb
Host smart-bf448e1c-efee-43fc-9909-c4586c573649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712812855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.712812855
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4238448827
Short name T216
Test name
Test status
Simulation time 7200162126 ps
CPU time 23.22 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:47:13 PM PDT 24
Peak memory 213808 kb
Host smart-0b84e44a-ad39-475f-ac9d-2dcfc5772dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238448827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4238448827
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1393690774
Short name T219
Test name
Test status
Simulation time 818459848 ps
CPU time 1.73 seconds
Started Aug 02 04:46:49 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 205580 kb
Host smart-0cd8aabc-ad71-4993-934e-63e084d8f208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393690774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1393690774
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2809230924
Short name T41
Test name
Test status
Simulation time 2695042873 ps
CPU time 7.87 seconds
Started Aug 02 04:46:51 PM PDT 24
Finished Aug 02 04:46:59 PM PDT 24
Peak memory 205608 kb
Host smart-5a9731d4-af87-4a20-a830-5dba2bce15bf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809230924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2809230924
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.4212638536
Short name T238
Test name
Test status
Simulation time 1434669551 ps
CPU time 1.83 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 213644 kb
Host smart-193678d2-01b3-424b-a0cb-6b20cda89d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212638536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4212638536
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2350073667
Short name T146
Test name
Test status
Simulation time 1598291237 ps
CPU time 5.32 seconds
Started Aug 02 04:46:47 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 213524 kb
Host smart-d7cb955f-6717-4511-85de-b8cf5e308f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350073667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2350073667
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1090220227
Short name T302
Test name
Test status
Simulation time 41169872 ps
CPU time 0.75 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 205196 kb
Host smart-76fc17a3-ea2d-42e4-99b2-1508fd74e464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090220227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1090220227
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1093939614
Short name T227
Test name
Test status
Simulation time 24566963382 ps
CPU time 17.3 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:47:07 PM PDT 24
Peak memory 218728 kb
Host smart-eb00da0e-c395-40b8-a01c-8f32374fc67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093939614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1093939614
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.4207125818
Short name T301
Test name
Test status
Simulation time 2481756269 ps
CPU time 5.17 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:55 PM PDT 24
Peak memory 213904 kb
Host smart-250ca449-a3a5-440d-a012-8cf9eca7c387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207125818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.4207125818
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2573116209
Short name T240
Test name
Test status
Simulation time 942021577 ps
CPU time 1.65 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:52 PM PDT 24
Peak memory 205684 kb
Host smart-cec309fb-647d-4c10-b40d-4658dc2b8702
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573116209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2573116209
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3686571181
Short name T249
Test name
Test status
Simulation time 492808661 ps
CPU time 2.13 seconds
Started Aug 02 04:46:49 PM PDT 24
Finished Aug 02 04:46:51 PM PDT 24
Peak memory 205496 kb
Host smart-e0c20fc0-7095-4289-a24a-c233edb55ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686571181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3686571181
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1978969551
Short name T211
Test name
Test status
Simulation time 2432785299 ps
CPU time 4.49 seconds
Started Aug 02 04:46:50 PM PDT 24
Finished Aug 02 04:46:54 PM PDT 24
Peak memory 213640 kb
Host smart-e58e28bf-d9a7-4905-ac3e-e774da41822f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978969551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1978969551
Directory /workspace/9.rv_dm_stress_all/latest
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