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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
84.07 96.18 85.48 89.91 73.75 88.33 98.53 56.31


Total test records in report: 463
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T310 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2996212970 Aug 03 04:32:43 PM PDT 24 Aug 03 04:33:25 PM PDT 24 15427464503 ps
T91 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2719594561 Aug 03 04:32:26 PM PDT 24 Aug 03 04:32:28 PM PDT 24 703294041 ps
T63 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3624490330 Aug 03 04:32:20 PM PDT 24 Aug 03 04:32:42 PM PDT 24 15257202223 ps
T87 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3501054675 Aug 03 04:32:18 PM PDT 24 Aug 03 04:32:34 PM PDT 24 3453840437 ps
T88 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.17551873 Aug 03 04:32:39 PM PDT 24 Aug 03 04:33:08 PM PDT 24 5877150764 ps
T311 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3602133461 Aug 03 04:33:05 PM PDT 24 Aug 03 04:33:11 PM PDT 24 1733118640 ps
T64 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.401835232 Aug 03 04:32:19 PM PDT 24 Aug 03 04:32:21 PM PDT 24 589940764 ps
T100 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2586968414 Aug 03 04:32:48 PM PDT 24 Aug 03 04:32:53 PM PDT 24 473699268 ps
T92 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4224891848 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:49 PM PDT 24 2393477026 ps
T312 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4051424566 Aug 03 04:32:49 PM PDT 24 Aug 03 04:34:03 PM PDT 24 43312683245 ps
T154 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2148479583 Aug 03 04:32:53 PM PDT 24 Aug 03 04:33:14 PM PDT 24 4078571739 ps
T93 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1593068579 Aug 03 04:32:43 PM PDT 24 Aug 03 04:32:44 PM PDT 24 227702827 ps
T313 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3546219653 Aug 03 04:32:39 PM PDT 24 Aug 03 04:32:42 PM PDT 24 179509552 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2758529583 Aug 03 04:32:20 PM PDT 24 Aug 03 04:33:28 PM PDT 24 69863999979 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3330021143 Aug 03 04:32:20 PM PDT 24 Aug 03 04:32:21 PM PDT 24 724655059 ps
T315 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4087528658 Aug 03 04:32:15 PM PDT 24 Aug 03 04:32:28 PM PDT 24 4234773653 ps
T316 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.186867911 Aug 03 04:33:00 PM PDT 24 Aug 03 04:33:06 PM PDT 24 526858487 ps
T159 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3521411213 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:56 PM PDT 24 3410765339 ps
T128 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.397376239 Aug 03 04:32:39 PM PDT 24 Aug 03 04:32:43 PM PDT 24 188731649 ps
T95 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.237283170 Aug 03 04:32:49 PM PDT 24 Aug 03 04:32:51 PM PDT 24 122806197 ps
T96 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1859366274 Aug 03 04:32:26 PM PDT 24 Aug 03 04:32:56 PM PDT 24 1720623308 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3134383545 Aug 03 04:32:13 PM PDT 24 Aug 03 04:32:15 PM PDT 24 334011934 ps
T318 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4289628527 Aug 03 04:32:52 PM PDT 24 Aug 03 04:33:32 PM PDT 24 14271794388 ps
T129 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2076967820 Aug 03 04:32:35 PM PDT 24 Aug 03 04:32:40 PM PDT 24 352638431 ps
T319 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2847193283 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:45 PM PDT 24 2531717681 ps
T320 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1960422323 Aug 03 04:32:26 PM PDT 24 Aug 03 04:32:30 PM PDT 24 2813659865 ps
T97 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3862600827 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:44 PM PDT 24 265095182 ps
T321 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4138260621 Aug 03 04:32:41 PM PDT 24 Aug 03 04:32:43 PM PDT 24 259007926 ps
T130 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4225222752 Aug 03 04:32:36 PM PDT 24 Aug 03 04:32:41 PM PDT 24 293675087 ps
T61 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3562328360 Aug 03 04:32:31 PM PDT 24 Aug 03 04:33:44 PM PDT 24 22550544228 ps
T322 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3612559267 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:33 PM PDT 24 93609411 ps
T98 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2248386730 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:38 PM PDT 24 468823528 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3693901508 Aug 03 04:32:29 PM PDT 24 Aug 03 04:33:10 PM PDT 24 14539419382 ps
T324 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.573301010 Aug 03 04:32:23 PM PDT 24 Aug 03 04:32:25 PM PDT 24 174196765 ps
T325 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2839688863 Aug 03 04:32:14 PM PDT 24 Aug 03 04:32:24 PM PDT 24 10906782487 ps
T99 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2364997220 Aug 03 04:33:01 PM PDT 24 Aug 03 04:33:03 PM PDT 24 310002518 ps
T326 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3615309330 Aug 03 04:33:09 PM PDT 24 Aug 03 04:33:12 PM PDT 24 115159812 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.436657002 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:51 PM PDT 24 36070868867 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4181733808 Aug 03 04:32:14 PM PDT 24 Aug 03 04:32:19 PM PDT 24 336474602 ps
T131 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.312786452 Aug 03 04:32:44 PM PDT 24 Aug 03 04:32:50 PM PDT 24 1043697819 ps
T329 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1347249284 Aug 03 04:32:51 PM PDT 24 Aug 03 04:32:56 PM PDT 24 260812207 ps
T106 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1287365770 Aug 03 04:32:40 PM PDT 24 Aug 03 04:32:48 PM PDT 24 610695828 ps
T330 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4187582935 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:29 PM PDT 24 59886905 ps
T331 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2068649185 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:42 PM PDT 24 534719728 ps
T332 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2537161902 Aug 03 04:32:43 PM PDT 24 Aug 03 04:32:59 PM PDT 24 11377571613 ps
T333 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2141604260 Aug 03 04:32:53 PM PDT 24 Aug 03 04:33:05 PM PDT 24 12908949506 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1469779340 Aug 03 04:32:13 PM PDT 24 Aug 03 04:32:15 PM PDT 24 811835375 ps
T335 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1680189441 Aug 03 04:32:41 PM PDT 24 Aug 03 04:32:58 PM PDT 24 3367784974 ps
T123 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3120281754 Aug 03 04:32:18 PM PDT 24 Aug 03 04:32:25 PM PDT 24 182979559 ps
T155 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1350151630 Aug 03 04:32:50 PM PDT 24 Aug 03 04:33:12 PM PDT 24 5925077528 ps
T166 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2635025473 Aug 03 04:32:36 PM PDT 24 Aug 03 04:34:44 PM PDT 24 42164277952 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3182598673 Aug 03 04:32:31 PM PDT 24 Aug 03 04:32:36 PM PDT 24 1515710169 ps
T337 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3024357103 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:50 PM PDT 24 27162144737 ps
T124 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2011104748 Aug 03 04:32:25 PM PDT 24 Aug 03 04:32:29 PM PDT 24 320383427 ps
T338 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2815313632 Aug 03 04:32:39 PM PDT 24 Aug 03 04:32:40 PM PDT 24 136677976 ps
T339 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.378305002 Aug 03 04:32:24 PM PDT 24 Aug 03 04:32:25 PM PDT 24 763516474 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3590858635 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:22 PM PDT 24 94268840 ps
T108 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1681184817 Aug 03 04:32:38 PM PDT 24 Aug 03 04:32:40 PM PDT 24 170029152 ps
T109 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.854478260 Aug 03 04:32:53 PM PDT 24 Aug 03 04:33:00 PM PDT 24 1365259449 ps
T340 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3855532877 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:36 PM PDT 24 356553849 ps
T341 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1803972323 Aug 03 04:32:35 PM PDT 24 Aug 03 04:32:46 PM PDT 24 12096685522 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3027558418 Aug 03 04:32:25 PM PDT 24 Aug 03 04:32:27 PM PDT 24 350076585 ps
T343 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2632400868 Aug 03 04:32:45 PM PDT 24 Aug 03 04:32:47 PM PDT 24 139625202 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.234545292 Aug 03 04:32:15 PM PDT 24 Aug 03 04:32:53 PM PDT 24 21053868804 ps
T345 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1019889052 Aug 03 04:32:28 PM PDT 24 Aug 03 04:32:29 PM PDT 24 192040998 ps
T346 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2991001706 Aug 03 04:32:43 PM PDT 24 Aug 03 04:32:47 PM PDT 24 1104494578 ps
T110 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3537559256 Aug 03 04:32:41 PM PDT 24 Aug 03 04:32:45 PM PDT 24 116145164 ps
T347 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2694961035 Aug 03 04:32:28 PM PDT 24 Aug 03 04:32:29 PM PDT 24 74009866 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1994115996 Aug 03 04:32:28 PM PDT 24 Aug 03 04:33:20 PM PDT 24 2033968921 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3934455230 Aug 03 04:32:22 PM PDT 24 Aug 03 04:37:50 PM PDT 24 207464701724 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.415480943 Aug 03 04:32:43 PM PDT 24 Aug 03 04:32:48 PM PDT 24 398380850 ps
T160 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4106086621 Aug 03 04:32:31 PM PDT 24 Aug 03 04:32:51 PM PDT 24 6231445074 ps
T350 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3275554922 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:46 PM PDT 24 1123402257 ps
T351 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2403644428 Aug 03 04:32:36 PM PDT 24 Aug 03 04:32:38 PM PDT 24 264696999 ps
T352 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3038837404 Aug 03 04:32:20 PM PDT 24 Aug 03 04:32:22 PM PDT 24 220288148 ps
T165 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.732131663 Aug 03 04:32:39 PM PDT 24 Aug 03 04:32:49 PM PDT 24 1717903828 ps
T353 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.446464471 Aug 03 04:32:28 PM PDT 24 Aug 03 04:32:56 PM PDT 24 47162157615 ps
T354 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2700399998 Aug 03 04:32:48 PM PDT 24 Aug 03 04:33:25 PM PDT 24 22461179498 ps
T355 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2699151027 Aug 03 04:32:26 PM PDT 24 Aug 03 04:34:33 PM PDT 24 32228507541 ps
T167 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1451710398 Aug 03 04:32:21 PM PDT 24 Aug 03 04:33:17 PM PDT 24 50310116089 ps
T161 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3561821784 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:50 PM PDT 24 2812716751 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3423814605 Aug 03 04:32:38 PM PDT 24 Aug 03 04:32:41 PM PDT 24 130196830 ps
T357 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2920238056 Aug 03 04:32:28 PM PDT 24 Aug 03 04:32:46 PM PDT 24 6713654547 ps
T358 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2403355740 Aug 03 04:32:22 PM PDT 24 Aug 03 04:32:23 PM PDT 24 306839688 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3721938309 Aug 03 04:32:29 PM PDT 24 Aug 03 04:32:30 PM PDT 24 42867857 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.371709445 Aug 03 04:32:19 PM PDT 24 Aug 03 04:32:21 PM PDT 24 142557458 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4055559149 Aug 03 04:32:22 PM PDT 24 Aug 03 04:32:23 PM PDT 24 117046659 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2491516303 Aug 03 04:32:44 PM PDT 24 Aug 03 04:32:58 PM PDT 24 10839752306 ps
T362 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3789433146 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:22 PM PDT 24 41483304 ps
T111 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4277275216 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:42 PM PDT 24 439899344 ps
T363 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3521762637 Aug 03 04:32:47 PM PDT 24 Aug 03 04:32:54 PM PDT 24 13658955626 ps
T364 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.603376229 Aug 03 04:32:43 PM PDT 24 Aug 03 04:33:03 PM PDT 24 7793099701 ps
T365 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1559266399 Aug 03 04:32:54 PM PDT 24 Aug 03 04:32:58 PM PDT 24 729677193 ps
T156 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4201395762 Aug 03 04:32:26 PM PDT 24 Aug 03 04:32:58 PM PDT 24 6542523789 ps
T366 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4264381120 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:49 PM PDT 24 6615112724 ps
T125 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3266899184 Aug 03 04:32:26 PM PDT 24 Aug 03 04:32:34 PM PDT 24 1662149597 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.477767162 Aug 03 04:32:22 PM PDT 24 Aug 03 04:33:49 PM PDT 24 32105025413 ps
T368 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1679980855 Aug 03 04:32:37 PM PDT 24 Aug 03 04:33:07 PM PDT 24 5985154463 ps
T369 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2486185712 Aug 03 04:32:26 PM PDT 24 Aug 03 04:32:29 PM PDT 24 50147867 ps
T370 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.47451439 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:46 PM PDT 24 2275889404 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1332284467 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:29 PM PDT 24 781238268 ps
T372 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.490261421 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:35 PM PDT 24 165602854 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.738981232 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:25 PM PDT 24 1970250955 ps
T116 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.753794352 Aug 03 04:32:12 PM PDT 24 Aug 03 04:32:50 PM PDT 24 7178112532 ps
T112 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.263316629 Aug 03 04:32:32 PM PDT 24 Aug 03 04:32:34 PM PDT 24 174199998 ps
T373 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.905092922 Aug 03 04:32:54 PM PDT 24 Aug 03 04:32:55 PM PDT 24 631200233 ps
T374 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1866006323 Aug 03 04:32:38 PM PDT 24 Aug 03 04:32:41 PM PDT 24 837139937 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.387533520 Aug 03 04:32:19 PM PDT 24 Aug 03 04:32:45 PM PDT 24 609151183 ps
T376 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1820873470 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:25 PM PDT 24 568206569 ps
T377 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3745477237 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:43 PM PDT 24 74494524 ps
T378 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2743422394 Aug 03 04:32:16 PM PDT 24 Aug 03 04:32:17 PM PDT 24 60642116 ps
T379 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1464497135 Aug 03 04:32:30 PM PDT 24 Aug 03 04:32:41 PM PDT 24 9537075789 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2094898935 Aug 03 04:32:18 PM PDT 24 Aug 03 04:32:28 PM PDT 24 11335864024 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1791383414 Aug 03 04:32:20 PM PDT 24 Aug 03 04:32:21 PM PDT 24 151308364 ps
T117 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.522597420 Aug 03 04:32:28 PM PDT 24 Aug 03 04:32:30 PM PDT 24 512432197 ps
T382 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1463602740 Aug 03 04:32:18 PM PDT 24 Aug 03 04:32:20 PM PDT 24 365723945 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1732235612 Aug 03 04:32:14 PM PDT 24 Aug 03 04:32:15 PM PDT 24 49152926 ps
T384 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3688467648 Aug 03 04:32:43 PM PDT 24 Aug 03 04:32:44 PM PDT 24 145955154 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1836863243 Aug 03 04:32:17 PM PDT 24 Aug 03 04:33:37 PM PDT 24 4699179722 ps
T385 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1813360843 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:51 PM PDT 24 19027076892 ps
T121 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1033435486 Aug 03 04:32:40 PM PDT 24 Aug 03 04:32:43 PM PDT 24 533511328 ps
T386 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3312728332 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:29 PM PDT 24 540432829 ps
T387 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.961384857 Aug 03 04:32:29 PM PDT 24 Aug 03 04:32:29 PM PDT 24 69771860 ps
T126 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3777149871 Aug 03 04:32:32 PM PDT 24 Aug 03 04:32:37 PM PDT 24 801147142 ps
T388 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2923815188 Aug 03 04:32:40 PM PDT 24 Aug 03 04:32:41 PM PDT 24 183903225 ps
T389 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3220633054 Aug 03 04:32:29 PM PDT 24 Aug 03 04:33:48 PM PDT 24 80467018354 ps
T390 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3061414490 Aug 03 04:33:06 PM PDT 24 Aug 03 04:33:08 PM PDT 24 231559185 ps
T391 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2539096948 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:41 PM PDT 24 181472879 ps
T392 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.368630477 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:35 PM PDT 24 877846428 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3612568000 Aug 03 04:32:20 PM PDT 24 Aug 03 04:32:22 PM PDT 24 222585950 ps
T393 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.438959201 Aug 03 04:32:36 PM PDT 24 Aug 03 04:32:38 PM PDT 24 238587443 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3554732928 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:38 PM PDT 24 10719891681 ps
T394 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4284580565 Aug 03 04:32:31 PM PDT 24 Aug 03 04:33:11 PM PDT 24 74139034685 ps
T164 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4082475781 Aug 03 04:32:48 PM PDT 24 Aug 03 04:33:00 PM PDT 24 2643743511 ps
T395 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3051964733 Aug 03 04:32:28 PM PDT 24 Aug 03 04:32:29 PM PDT 24 50239536 ps
T162 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1248045618 Aug 03 04:32:17 PM PDT 24 Aug 03 04:32:31 PM PDT 24 3375203012 ps
T396 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.199789772 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:46 PM PDT 24 301062634 ps
T397 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2140931934 Aug 03 04:32:15 PM PDT 24 Aug 03 04:32:16 PM PDT 24 135892137 ps
T113 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1296539205 Aug 03 04:32:22 PM PDT 24 Aug 03 04:32:26 PM PDT 24 866826424 ps
T398 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2491056694 Aug 03 04:32:40 PM PDT 24 Aug 03 04:32:41 PM PDT 24 608640346 ps
T399 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1285040835 Aug 03 04:32:41 PM PDT 24 Aug 03 04:33:31 PM PDT 24 65388960580 ps
T400 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.131557631 Aug 03 04:32:27 PM PDT 24 Aug 03 04:34:46 PM PDT 24 48644080918 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.682642247 Aug 03 04:32:16 PM PDT 24 Aug 03 04:32:22 PM PDT 24 354948576 ps
T402 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2331379406 Aug 03 04:33:04 PM PDT 24 Aug 03 04:33:06 PM PDT 24 159074179 ps
T403 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2363252664 Aug 03 04:32:31 PM PDT 24 Aug 03 04:32:33 PM PDT 24 60827520 ps
T404 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2293158995 Aug 03 04:32:38 PM PDT 24 Aug 03 04:32:48 PM PDT 24 732813691 ps
T405 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2834807027 Aug 03 04:32:34 PM PDT 24 Aug 03 04:32:36 PM PDT 24 232578327 ps
T104 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2541460596 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:32 PM PDT 24 1616664593 ps
T105 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2028482196 Aug 03 04:32:14 PM PDT 24 Aug 03 04:32:41 PM PDT 24 10819933777 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2607803211 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:23 PM PDT 24 560805279 ps
T407 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.366432738 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:43 PM PDT 24 227695118 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2649895012 Aug 03 04:32:16 PM PDT 24 Aug 03 04:32:17 PM PDT 24 154616611 ps
T409 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2374763916 Aug 03 04:32:41 PM PDT 24 Aug 03 04:32:44 PM PDT 24 757637533 ps
T410 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4037001504 Aug 03 04:32:44 PM PDT 24 Aug 03 04:33:03 PM PDT 24 21009532681 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3959435844 Aug 03 04:32:17 PM PDT 24 Aug 03 04:32:18 PM PDT 24 153692704 ps
T412 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1762784370 Aug 03 04:32:20 PM PDT 24 Aug 03 04:32:22 PM PDT 24 3126296465 ps
T413 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3865481715 Aug 03 04:32:14 PM PDT 24 Aug 03 04:32:21 PM PDT 24 3790262223 ps
T168 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2702121989 Aug 03 04:32:30 PM PDT 24 Aug 03 04:33:09 PM PDT 24 63813567384 ps
T163 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1218467776 Aug 03 04:32:50 PM PDT 24 Aug 03 04:33:08 PM PDT 24 1585620158 ps
T414 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.885819802 Aug 03 04:32:15 PM PDT 24 Aug 03 04:33:47 PM PDT 24 66806491832 ps
T415 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2639498547 Aug 03 04:32:44 PM PDT 24 Aug 03 04:32:45 PM PDT 24 626786458 ps
T416 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.349533977 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:31 PM PDT 24 218073339 ps
T417 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2631107734 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:56 PM PDT 24 26075862689 ps
T418 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.135312606 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:49 PM PDT 24 4754577451 ps
T419 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2880767242 Aug 03 04:33:09 PM PDT 24 Aug 03 04:33:10 PM PDT 24 120321537 ps
T114 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3795709008 Aug 03 04:32:12 PM PDT 24 Aug 03 04:32:43 PM PDT 24 7938732077 ps
T119 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3658239567 Aug 03 04:32:54 PM PDT 24 Aug 03 04:32:56 PM PDT 24 347695544 ps
T420 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2102447738 Aug 03 04:32:13 PM PDT 24 Aug 03 04:32:14 PM PDT 24 288180225 ps
T421 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2678517796 Aug 03 04:32:18 PM PDT 24 Aug 03 04:32:20 PM PDT 24 220807477 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1547722544 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:31 PM PDT 24 1374212373 ps
T423 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1408528315 Aug 03 04:32:35 PM PDT 24 Aug 03 04:32:38 PM PDT 24 119450554 ps
T424 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4223941968 Aug 03 04:32:24 PM PDT 24 Aug 03 04:32:29 PM PDT 24 5227660935 ps
T425 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1436189663 Aug 03 04:32:40 PM PDT 24 Aug 03 04:32:44 PM PDT 24 110493698 ps
T426 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.818665661 Aug 03 04:32:33 PM PDT 24 Aug 03 04:32:42 PM PDT 24 15511971976 ps
T157 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3762163718 Aug 03 04:32:52 PM PDT 24 Aug 03 04:33:13 PM PDT 24 2671122589 ps
T427 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2906282085 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:28 PM PDT 24 42000885 ps
T428 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1183258955 Aug 03 04:32:41 PM PDT 24 Aug 03 04:32:44 PM PDT 24 230512196 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4088852333 Aug 03 04:32:18 PM PDT 24 Aug 03 04:32:23 PM PDT 24 287576785 ps
T430 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3327187069 Aug 03 04:32:18 PM PDT 24 Aug 03 04:33:23 PM PDT 24 1163692486 ps
T431 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.90317659 Aug 03 04:32:32 PM PDT 24 Aug 03 04:32:35 PM PDT 24 365797687 ps
T432 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.248237150 Aug 03 04:32:15 PM PDT 24 Aug 03 04:33:00 PM PDT 24 15575122342 ps
T433 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4034575306 Aug 03 04:32:16 PM PDT 24 Aug 03 04:32:42 PM PDT 24 9163086241 ps
T434 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.261757075 Aug 03 04:32:45 PM PDT 24 Aug 03 04:32:52 PM PDT 24 6908352594 ps
T435 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.208431913 Aug 03 04:32:40 PM PDT 24 Aug 03 04:32:45 PM PDT 24 3605551091 ps
T436 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2337986994 Aug 03 04:32:31 PM PDT 24 Aug 03 04:32:35 PM PDT 24 179376864 ps
T437 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3258051473 Aug 03 04:32:19 PM PDT 24 Aug 03 04:32:22 PM PDT 24 427264261 ps
T438 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4210615273 Aug 03 04:32:32 PM PDT 24 Aug 03 04:32:36 PM PDT 24 623321418 ps
T439 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2971374588 Aug 03 04:32:36 PM PDT 24 Aug 03 04:33:01 PM PDT 24 16963898988 ps
T440 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2052794577 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:46 PM PDT 24 759409204 ps
T441 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1973840290 Aug 03 04:32:13 PM PDT 24 Aug 03 04:33:39 PM PDT 24 25890536632 ps
T442 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1079988914 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:29 PM PDT 24 569140665 ps
T443 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3311783659 Aug 03 04:32:29 PM PDT 24 Aug 03 04:32:33 PM PDT 24 350506711 ps
T444 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1610378179 Aug 03 04:32:14 PM PDT 24 Aug 03 04:32:16 PM PDT 24 73491860 ps
T445 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.704674239 Aug 03 04:32:26 PM PDT 24 Aug 03 04:33:34 PM PDT 24 5127112672 ps
T446 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1541642463 Aug 03 04:32:27 PM PDT 24 Aug 03 04:32:28 PM PDT 24 156759554 ps
T447 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.554997000 Aug 03 04:32:51 PM PDT 24 Aug 03 04:32:56 PM PDT 24 295811390 ps
T448 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.245217154 Aug 03 04:32:37 PM PDT 24 Aug 03 04:32:39 PM PDT 24 155005678 ps
T449 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2362309056 Aug 03 04:32:23 PM PDT 24 Aug 03 04:32:26 PM PDT 24 278413024 ps
T450 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2044381132 Aug 03 04:32:30 PM PDT 24 Aug 03 04:32:31 PM PDT 24 439963873 ps
T451 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1071500054 Aug 03 04:32:41 PM PDT 24 Aug 03 04:32:47 PM PDT 24 130292397 ps
T452 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1367414557 Aug 03 04:32:37 PM PDT 24 Aug 03 04:32:41 PM PDT 24 2219207470 ps
T453 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1551700021 Aug 03 04:32:39 PM PDT 24 Aug 03 04:32:41 PM PDT 24 190862602 ps
T454 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3269043860 Aug 03 04:32:29 PM PDT 24 Aug 03 04:32:33 PM PDT 24 443532086 ps
T455 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3264585231 Aug 03 04:32:35 PM PDT 24 Aug 03 04:32:36 PM PDT 24 454114931 ps
T456 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.113787759 Aug 03 04:32:19 PM PDT 24 Aug 03 04:32:47 PM PDT 24 876910880 ps
T457 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3599919559 Aug 03 04:32:35 PM PDT 24 Aug 03 04:32:41 PM PDT 24 240171975 ps
T458 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1486512076 Aug 03 04:32:31 PM PDT 24 Aug 03 04:32:32 PM PDT 24 76753505 ps
T459 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2711551854 Aug 03 04:33:04 PM PDT 24 Aug 03 04:33:10 PM PDT 24 947968308 ps
T460 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1658183107 Aug 03 04:32:42 PM PDT 24 Aug 03 04:32:55 PM PDT 24 17684563999 ps
T461 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2330057328 Aug 03 04:32:21 PM PDT 24 Aug 03 04:32:22 PM PDT 24 49094595 ps
T158 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2503413095 Aug 03 04:32:19 PM PDT 24 Aug 03 04:32:40 PM PDT 24 1794784393 ps
T462 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.266298409 Aug 03 04:33:04 PM PDT 24 Aug 03 04:33:05 PM PDT 24 86808787 ps
T463 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.65181883 Aug 03 04:32:39 PM PDT 24 Aug 03 04:32:43 PM PDT 24 91524926 ps

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.1213103724
Short name T1
Test name
Test status
Simulation time 145349489914 ps
CPU time 824.9 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:48:33 PM PDT 24
Peak memory 238528 kb
Host smart-7e933ff3-edeb-4853-8d6f-61dafb0d8706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213103724 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.1213103724
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1034828638
Short name T23
Test name
Test status
Simulation time 1957832360 ps
CPU time 6.18 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:56 PM PDT 24
Peak memory 205564 kb
Host smart-328f77f8-d49f-4d5d-a046-28ac153d2bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034828638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1034828638
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3681423743
Short name T85
Test name
Test status
Simulation time 2226970962 ps
CPU time 21.08 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:48 PM PDT 24
Peak memory 213840 kb
Host smart-039f82b8-8720-4cf0-957c-5976990f80c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681423743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3681423743
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1451710398
Short name T167
Test name
Test status
Simulation time 50310116089 ps
CPU time 56.48 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:33:17 PM PDT 24
Peak memory 221912 kb
Host smart-c95b8c94-9464-4a2d-b176-ba4f802fd840
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451710398 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1451710398
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.629577340
Short name T31
Test name
Test status
Simulation time 13253284907 ps
CPU time 37.01 seconds
Started Aug 03 04:34:56 PM PDT 24
Finished Aug 03 04:35:33 PM PDT 24
Peak memory 217084 kb
Host smart-18ea085b-5fb2-4220-a7d5-fbdd28fc4849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629577340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.629577340
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.550736390
Short name T33
Test name
Test status
Simulation time 113963705 ps
CPU time 0.77 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 205152 kb
Host smart-58ccd271-0572-4b77-ae92-55f33f1c7f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550736390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.550736390
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.1135195045
Short name T8
Test name
Test status
Simulation time 149096479637 ps
CPU time 568.78 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:44:12 PM PDT 24
Peak memory 238004 kb
Host smart-11eb1a49-2e41-4288-98cc-fd80298f9f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135195045 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.1135195045
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2265755056
Short name T53
Test name
Test status
Simulation time 266886141 ps
CPU time 1.38 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:50 PM PDT 24
Peak memory 205276 kb
Host smart-db02f5cd-462f-46f9-83fa-0c5425bbd9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265755056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2265755056
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3847239275
Short name T132
Test name
Test status
Simulation time 3647511260 ps
CPU time 10.23 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205636 kb
Host smart-5fa914a6-bf7b-412b-a93e-0443b848a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847239275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3847239275
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1681184817
Short name T108
Test name
Test status
Simulation time 170029152 ps
CPU time 1.81 seconds
Started Aug 03 04:32:38 PM PDT 24
Finished Aug 03 04:32:40 PM PDT 24
Peak memory 213696 kb
Host smart-c0cf085c-028f-4c3c-a4aa-be44df495878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681184817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1681184817
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.321013495
Short name T18
Test name
Test status
Simulation time 2913715224 ps
CPU time 8.7 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 205464 kb
Host smart-68eb6628-29f8-43df-9ab7-c71290490233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321013495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.321013495
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.787708709
Short name T57
Test name
Test status
Simulation time 74900396 ps
CPU time 0.96 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:34:44 PM PDT 24
Peak memory 215480 kb
Host smart-ac8a9271-89ed-4dda-86d3-49c9e4f91b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787708709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.787708709
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.496694071
Short name T51
Test name
Test status
Simulation time 1593763831 ps
CPU time 2.85 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:34:46 PM PDT 24
Peak memory 230112 kb
Host smart-4286066c-403f-4430-9e59-54e14f4357ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496694071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.496694071
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.944733945
Short name T272
Test name
Test status
Simulation time 65208977852 ps
CPU time 74.24 seconds
Started Aug 03 04:34:48 PM PDT 24
Finished Aug 03 04:36:02 PM PDT 24
Peak memory 215312 kb
Host smart-8972d3e3-7e99-43a2-acd3-d60bc506f191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944733945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.944733945
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2736695091
Short name T15
Test name
Test status
Simulation time 977425678 ps
CPU time 2.65 seconds
Started Aug 03 04:34:33 PM PDT 24
Finished Aug 03 04:34:36 PM PDT 24
Peak memory 205108 kb
Host smart-a29d815e-8b9b-400e-8960-44dabcb685a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736695091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2736695091
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4129585480
Short name T37
Test name
Test status
Simulation time 52011502 ps
CPU time 0.91 seconds
Started Aug 03 04:34:35 PM PDT 24
Finished Aug 03 04:34:36 PM PDT 24
Peak memory 213444 kb
Host smart-15162529-124a-47ba-abfe-78330d11ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129585480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4129585480
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1350151630
Short name T155
Test name
Test status
Simulation time 5925077528 ps
CPU time 22.36 seconds
Started Aug 03 04:32:50 PM PDT 24
Finished Aug 03 04:33:12 PM PDT 24
Peak memory 213888 kb
Host smart-507f75d8-49f6-4754-b8d0-594d7c26358b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350151630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
350151630
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1216135697
Short name T9
Test name
Test status
Simulation time 3227420951 ps
CPU time 5.15 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 213648 kb
Host smart-374783ff-d49c-4e30-9505-a099450ae462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216135697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1216135697
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4224891848
Short name T92
Test name
Test status
Simulation time 2393477026 ps
CPU time 7.82 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:49 PM PDT 24
Peak memory 205744 kb
Host smart-62ab460c-80b0-4c34-94d5-9aee9bf2b6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224891848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.4224891848
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2803248643
Short name T140
Test name
Test status
Simulation time 1443023411 ps
CPU time 4.32 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 205604 kb
Host smart-3f870284-26f0-47c7-8a5f-b1f36e944f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803248643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2803248643
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2779997621
Short name T10
Test name
Test status
Simulation time 2158189215 ps
CPU time 7.3 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 213660 kb
Host smart-f14c00ef-c48d-4272-bbc2-0b458b5c7ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779997621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2779997621
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.782078562
Short name T2
Test name
Test status
Simulation time 7190748663 ps
CPU time 10.94 seconds
Started Aug 03 04:35:06 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 213860 kb
Host smart-44df8f38-8b2e-4214-937f-a984f44ff995
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782078562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.782078562
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3134383545
Short name T317
Test name
Test status
Simulation time 334011934 ps
CPU time 1.54 seconds
Started Aug 03 04:32:13 PM PDT 24
Finished Aug 03 04:32:15 PM PDT 24
Peak memory 205244 kb
Host smart-44c7cf1c-1489-46ea-b7cf-dac303294252
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134383545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3134383545
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3438807423
Short name T27
Test name
Test status
Simulation time 54966023 ps
CPU time 0.84 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:34:44 PM PDT 24
Peak memory 205140 kb
Host smart-ef7fa2a7-741d-4906-86d5-e03e92c12a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438807423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3438807423
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1918096211
Short name T19
Test name
Test status
Simulation time 800619388140 ps
CPU time 2068.09 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 05:09:14 PM PDT 24
Peak memory 250000 kb
Host smart-6a19e76c-fc26-48dc-ace4-665df423a246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918096211 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1918096211
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2503413095
Short name T158
Test name
Test status
Simulation time 1794784393 ps
CPU time 20.68 seconds
Started Aug 03 04:32:19 PM PDT 24
Finished Aug 03 04:32:40 PM PDT 24
Peak memory 213808 kb
Host smart-cce6af60-0782-4271-bfe6-b0db8c1442b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503413095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2503413095
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1998508496
Short name T79
Test name
Test status
Simulation time 5944036137 ps
CPU time 19.04 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 213808 kb
Host smart-6a13338d-78cb-4347-bc08-7cf92c2fa625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998508496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1998508496
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.277344619
Short name T147
Test name
Test status
Simulation time 13657511425 ps
CPU time 6.96 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 213684 kb
Host smart-abb087eb-8eaf-477a-9fa6-0297bd4f1234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277344619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.277344619
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.71317609
Short name T45
Test name
Test status
Simulation time 529760149 ps
CPU time 1.45 seconds
Started Aug 03 04:34:38 PM PDT 24
Finished Aug 03 04:34:39 PM PDT 24
Peak memory 205148 kb
Host smart-56294c04-3231-4d3a-8d65-ca96de3c3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71317609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.71317609
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2028482196
Short name T105
Test name
Test status
Simulation time 10819933777 ps
CPU time 27.26 seconds
Started Aug 03 04:32:14 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 205588 kb
Host smart-37111d4d-ed0b-4bdf-aff8-1313ada66ca5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028482196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2028482196
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.66682562
Short name T36
Test name
Test status
Simulation time 772277506 ps
CPU time 1.21 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205280 kb
Host smart-884e1795-6f7e-4403-9096-d9105c3e7649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66682562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.66682562
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1218467776
Short name T163
Test name
Test status
Simulation time 1585620158 ps
CPU time 18.32 seconds
Started Aug 03 04:32:50 PM PDT 24
Finished Aug 03 04:33:08 PM PDT 24
Peak memory 213788 kb
Host smart-f5daa7af-1b21-4ebd-9eeb-fce695026226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218467776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
218467776
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2148479583
Short name T154
Test name
Test status
Simulation time 4078571739 ps
CPU time 20.77 seconds
Started Aug 03 04:32:53 PM PDT 24
Finished Aug 03 04:33:14 PM PDT 24
Peak memory 213844 kb
Host smart-7ec04b32-da83-4670-beb4-95f02eb34689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148479583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
148479583
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2312412411
Short name T30
Test name
Test status
Simulation time 2805589238 ps
CPU time 2.41 seconds
Started Aug 03 04:34:33 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 213800 kb
Host smart-6154ec0a-b7bb-4975-b894-b6001583ce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312412411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2312412411
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.640712323
Short name T59
Test name
Test status
Simulation time 10625005441 ps
CPU time 30.82 seconds
Started Aug 03 04:34:32 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 205580 kb
Host smart-d370e34b-e544-4d28-a669-afc9afd7d414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640712323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.640712323
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3948788384
Short name T134
Test name
Test status
Simulation time 4236471050 ps
CPU time 4.45 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 213636 kb
Host smart-8d85041b-9f46-4bec-8031-1b9d475ad19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948788384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3948788384
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2896373603
Short name T139
Test name
Test status
Simulation time 4963289332 ps
CPU time 14.33 seconds
Started Aug 03 04:34:57 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 213908 kb
Host smart-38264a21-3e4d-48aa-ab63-c58ea1bf7d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896373603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2896373603
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3795709008
Short name T114
Test name
Test status
Simulation time 7938732077 ps
CPU time 31.12 seconds
Started Aug 03 04:32:12 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 205632 kb
Host smart-ac4d87aa-be55-4a7e-98df-09cde9ecef70
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795709008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3795709008
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.753794352
Short name T116
Test name
Test status
Simulation time 7178112532 ps
CPU time 38.55 seconds
Started Aug 03 04:32:12 PM PDT 24
Finished Aug 03 04:32:50 PM PDT 24
Peak memory 205732 kb
Host smart-d20ebcdd-49cf-4bc2-8f56-22e2339bc4c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753794352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.753794352
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.973695766
Short name T90
Test name
Test status
Simulation time 279649166 ps
CPU time 1.57 seconds
Started Aug 03 04:32:22 PM PDT 24
Finished Aug 03 04:32:23 PM PDT 24
Peak memory 213668 kb
Host smart-7377fa04-c74b-4c44-8174-9f50c33564cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973695766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.973695766
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1463602740
Short name T382
Test name
Test status
Simulation time 365723945 ps
CPU time 2.15 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:32:20 PM PDT 24
Peak memory 215804 kb
Host smart-5d632c18-5e4d-41f6-a969-b112190fb07f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463602740 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1463602740
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1610378179
Short name T444
Test name
Test status
Simulation time 73491860 ps
CPU time 1.57 seconds
Started Aug 03 04:32:14 PM PDT 24
Finished Aug 03 04:32:16 PM PDT 24
Peak memory 213712 kb
Host smart-7cebeabe-5d2e-4fd9-aad5-46158243660d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610378179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1610378179
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.234545292
Short name T344
Test name
Test status
Simulation time 21053868804 ps
CPU time 38.22 seconds
Started Aug 03 04:32:15 PM PDT 24
Finished Aug 03 04:32:53 PM PDT 24
Peak memory 205540 kb
Host smart-d35fa06c-cedb-40c7-9307-8a3ba11c91ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234545292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.234545292
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4087528658
Short name T315
Test name
Test status
Simulation time 4234773653 ps
CPU time 12.65 seconds
Started Aug 03 04:32:15 PM PDT 24
Finished Aug 03 04:32:28 PM PDT 24
Peak memory 205560 kb
Host smart-f974e411-90b7-489d-a2e8-af38bfa9dd6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087528658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.4087528658
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4034575306
Short name T433
Test name
Test status
Simulation time 9163086241 ps
CPU time 25.76 seconds
Started Aug 03 04:32:16 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 205512 kb
Host smart-e2f02730-dac7-46f7-900d-50aa7bae8d6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034575306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.4
034575306
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2403355740
Short name T358
Test name
Test status
Simulation time 306839688 ps
CPU time 0.86 seconds
Started Aug 03 04:32:22 PM PDT 24
Finished Aug 03 04:32:23 PM PDT 24
Peak memory 205144 kb
Host smart-244600f0-964e-4888-a849-6dcf8b87146c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403355740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2403355740
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.248237150
Short name T432
Test name
Test status
Simulation time 15575122342 ps
CPU time 44.72 seconds
Started Aug 03 04:32:15 PM PDT 24
Finished Aug 03 04:33:00 PM PDT 24
Peak memory 205520 kb
Host smart-5b2f0e1c-ebdc-409e-a3e7-bd74bf2837d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248237150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.248237150
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2102447738
Short name T420
Test name
Test status
Simulation time 288180225 ps
CPU time 0.85 seconds
Started Aug 03 04:32:13 PM PDT 24
Finished Aug 03 04:32:14 PM PDT 24
Peak memory 205264 kb
Host smart-fcefb66d-e7cc-4613-9547-60c34fa46bb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102447738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2102447738
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2140931934
Short name T397
Test name
Test status
Simulation time 135892137 ps
CPU time 0.78 seconds
Started Aug 03 04:32:15 PM PDT 24
Finished Aug 03 04:32:16 PM PDT 24
Peak memory 205164 kb
Host smart-f9c97aab-d244-4563-a7d3-44c7829d1763
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140931934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
140931934
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2743422394
Short name T378
Test name
Test status
Simulation time 60642116 ps
CPU time 0.71 seconds
Started Aug 03 04:32:16 PM PDT 24
Finished Aug 03 04:32:17 PM PDT 24
Peak memory 205308 kb
Host smart-6f23715b-0369-460b-8467-08d73ce1a8d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743422394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2743422394
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1732235612
Short name T383
Test name
Test status
Simulation time 49152926 ps
CPU time 0.84 seconds
Started Aug 03 04:32:14 PM PDT 24
Finished Aug 03 04:32:15 PM PDT 24
Peak memory 205464 kb
Host smart-854281de-89b0-4d5c-a1ec-e1111241689f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732235612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1732235612
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1296539205
Short name T113
Test name
Test status
Simulation time 866826424 ps
CPU time 4.25 seconds
Started Aug 03 04:32:22 PM PDT 24
Finished Aug 03 04:32:26 PM PDT 24
Peak memory 205464 kb
Host smart-3c3f2c79-6fd0-478b-a2ee-d15a582abdd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296539205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1296539205
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.477767162
Short name T367
Test name
Test status
Simulation time 32105025413 ps
CPU time 86.46 seconds
Started Aug 03 04:32:22 PM PDT 24
Finished Aug 03 04:33:49 PM PDT 24
Peak memory 222000 kb
Host smart-c04ae7ae-1cc2-4bbd-9912-d6c75134f2d7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477767162 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.477767162
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.682642247
Short name T401
Test name
Test status
Simulation time 354948576 ps
CPU time 5.91 seconds
Started Aug 03 04:32:16 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 221944 kb
Host smart-9778fe83-e3ad-43a6-a0f4-087272e5f314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682642247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.682642247
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3501054675
Short name T87
Test name
Test status
Simulation time 3453840437 ps
CPU time 15.53 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:32:34 PM PDT 24
Peak memory 213968 kb
Host smart-c7ed02be-9dfc-4dbc-b8b9-65ff999574a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501054675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3501054675
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3327187069
Short name T430
Test name
Test status
Simulation time 1163692486 ps
CPU time 64.47 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:33:23 PM PDT 24
Peak memory 217792 kb
Host smart-c08866ec-85c9-416f-b968-0630d703d95a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327187069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3327187069
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.113787759
Short name T456
Test name
Test status
Simulation time 876910880 ps
CPU time 27.37 seconds
Started Aug 03 04:32:19 PM PDT 24
Finished Aug 03 04:32:47 PM PDT 24
Peak memory 205584 kb
Host smart-979d9e21-979b-47e4-891a-ea5ce2bbf521
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113787759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.113787759
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.371709445
Short name T115
Test name
Test status
Simulation time 142557458 ps
CPU time 1.91 seconds
Started Aug 03 04:32:19 PM PDT 24
Finished Aug 03 04:32:21 PM PDT 24
Peak memory 213736 kb
Host smart-f81d971e-5153-4290-9ecb-b8af2620ff89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371709445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.371709445
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.573301010
Short name T324
Test name
Test status
Simulation time 174196765 ps
CPU time 2.4 seconds
Started Aug 03 04:32:23 PM PDT 24
Finished Aug 03 04:32:25 PM PDT 24
Peak memory 215444 kb
Host smart-391a9eea-98ef-4462-a350-e1205d60d803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573301010 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.573301010
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3258051473
Short name T437
Test name
Test status
Simulation time 427264261 ps
CPU time 2.43 seconds
Started Aug 03 04:32:19 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 213596 kb
Host smart-e6de1e77-3c70-4e1d-96cf-4794d763c6cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258051473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3258051473
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.885819802
Short name T414
Test name
Test status
Simulation time 66806491832 ps
CPU time 91.89 seconds
Started Aug 03 04:32:15 PM PDT 24
Finished Aug 03 04:33:47 PM PDT 24
Peak memory 205464 kb
Host smart-7d5e17bf-e164-4557-b0a9-0d9dfb0c4186
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885819802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.885819802
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3165082821
Short name T309
Test name
Test status
Simulation time 62044539 ps
CPU time 0.69 seconds
Started Aug 03 04:32:12 PM PDT 24
Finished Aug 03 04:32:12 PM PDT 24
Peak memory 205192 kb
Host smart-e289adfc-376f-465a-a96b-ea0071b45e04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165082821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3165082821
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2839688863
Short name T325
Test name
Test status
Simulation time 10906782487 ps
CPU time 10.03 seconds
Started Aug 03 04:32:14 PM PDT 24
Finished Aug 03 04:32:24 PM PDT 24
Peak memory 205528 kb
Host smart-e0c041fe-4120-4e38-b97d-4361886ace97
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839688863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2839688863
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3865481715
Short name T413
Test name
Test status
Simulation time 3790262223 ps
CPU time 6.65 seconds
Started Aug 03 04:32:14 PM PDT 24
Finished Aug 03 04:32:21 PM PDT 24
Peak memory 205568 kb
Host smart-b459a497-7518-4a49-8cfc-c05e7de3bc05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865481715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
865481715
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1469779340
Short name T334
Test name
Test status
Simulation time 811835375 ps
CPU time 1.87 seconds
Started Aug 03 04:32:13 PM PDT 24
Finished Aug 03 04:32:15 PM PDT 24
Peak memory 205164 kb
Host smart-61c41796-9b30-43b7-ae74-62a6d508a135
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469779340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1469779340
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2094898935
Short name T380
Test name
Test status
Simulation time 11335864024 ps
CPU time 9.44 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:32:28 PM PDT 24
Peak memory 205568 kb
Host smart-a0582749-5210-46fa-9b8c-da4979b2fbd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094898935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2094898935
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2649895012
Short name T408
Test name
Test status
Simulation time 154616611 ps
CPU time 0.75 seconds
Started Aug 03 04:32:16 PM PDT 24
Finished Aug 03 04:32:17 PM PDT 24
Peak memory 205236 kb
Host smart-f78ce4df-eb50-4d91-ab40-b0a6b4bdcd9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649895012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
649895012
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3959435844
Short name T411
Test name
Test status
Simulation time 153692704 ps
CPU time 0.8 seconds
Started Aug 03 04:32:17 PM PDT 24
Finished Aug 03 04:32:18 PM PDT 24
Peak memory 205240 kb
Host smart-e52b41bf-03ab-482d-9e10-398ab092a9a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959435844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3959435844
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4055559149
Short name T360
Test name
Test status
Simulation time 117046659 ps
CPU time 0.7 seconds
Started Aug 03 04:32:22 PM PDT 24
Finished Aug 03 04:32:23 PM PDT 24
Peak memory 205144 kb
Host smart-f8980589-a041-4a25-9e1f-0b65b5e4e692
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055559149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4055559149
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4088852333
Short name T429
Test name
Test status
Simulation time 287576785 ps
CPU time 4.2 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:32:23 PM PDT 24
Peak memory 205576 kb
Host smart-a46b99cf-137c-414c-af83-3dddbb5e5937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088852333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4088852333
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1973840290
Short name T441
Test name
Test status
Simulation time 25890536632 ps
CPU time 85.39 seconds
Started Aug 03 04:32:13 PM PDT 24
Finished Aug 03 04:33:39 PM PDT 24
Peak memory 222200 kb
Host smart-45b3cdc8-12c2-420b-964b-f11ce0fd160a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973840290 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1973840290
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4181733808
Short name T328
Test name
Test status
Simulation time 336474602 ps
CPU time 4.85 seconds
Started Aug 03 04:32:14 PM PDT 24
Finished Aug 03 04:32:19 PM PDT 24
Peak memory 213784 kb
Host smart-b370a216-8ed6-4f37-b133-e37a821c6021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181733808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4181733808
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1248045618
Short name T162
Test name
Test status
Simulation time 3375203012 ps
CPU time 13.07 seconds
Started Aug 03 04:32:17 PM PDT 24
Finished Aug 03 04:32:31 PM PDT 24
Peak memory 213868 kb
Host smart-e961cb0e-b2ce-4caa-bff0-e58109284dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248045618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1248045618
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2632400868
Short name T343
Test name
Test status
Simulation time 139625202 ps
CPU time 2.22 seconds
Started Aug 03 04:32:45 PM PDT 24
Finished Aug 03 04:32:47 PM PDT 24
Peak memory 218980 kb
Host smart-fcf5f8b2-69ad-4dbe-a946-434976b456ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632400868 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2632400868
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.245217154
Short name T448
Test name
Test status
Simulation time 155005678 ps
CPU time 2.21 seconds
Started Aug 03 04:32:37 PM PDT 24
Finished Aug 03 04:32:39 PM PDT 24
Peak memory 213628 kb
Host smart-979b3542-8c9e-4ec4-9168-14a3b37c9462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245217154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.245217154
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.818665661
Short name T426
Test name
Test status
Simulation time 15511971976 ps
CPU time 8.4 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 205516 kb
Host smart-5d48c0a1-c50f-405a-ae83-13e080fb90a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818665661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.818665661
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3275554922
Short name T350
Test name
Test status
Simulation time 1123402257 ps
CPU time 3.72 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 205420 kb
Host smart-c42def0b-e77f-4bdb-83a4-239b2c5153ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275554922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3275554922
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.366432738
Short name T407
Test name
Test status
Simulation time 227695118 ps
CPU time 0.72 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 205224 kb
Host smart-cc432308-be74-4bf0-92cc-0e113c9af941
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366432738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.366432738
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3777149871
Short name T126
Test name
Test status
Simulation time 801147142 ps
CPU time 4.1 seconds
Started Aug 03 04:32:32 PM PDT 24
Finished Aug 03 04:32:37 PM PDT 24
Peak memory 205628 kb
Host smart-5ae3051e-3bfd-41b7-86a4-26bd2df42135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777149871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3777149871
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.90317659
Short name T431
Test name
Test status
Simulation time 365797687 ps
CPU time 2.74 seconds
Started Aug 03 04:32:32 PM PDT 24
Finished Aug 03 04:32:35 PM PDT 24
Peak memory 213780 kb
Host smart-e6067e58-50ea-4480-8ebb-783d1d343ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90317659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.90317659
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2068649185
Short name T331
Test name
Test status
Simulation time 534719728 ps
CPU time 8.56 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 213796 kb
Host smart-75aeaceb-5008-4e04-a39b-0a9bf0c83077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068649185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
068649185
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3423814605
Short name T356
Test name
Test status
Simulation time 130196830 ps
CPU time 2.81 seconds
Started Aug 03 04:32:38 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 218988 kb
Host smart-1ee348dd-cbf0-43fd-ade4-ee514daf0898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423814605 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3423814605
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2364997220
Short name T99
Test name
Test status
Simulation time 310002518 ps
CPU time 1.78 seconds
Started Aug 03 04:33:01 PM PDT 24
Finished Aug 03 04:33:03 PM PDT 24
Peak memory 213652 kb
Host smart-47f2f88a-0cbd-42d3-b5c3-76bd759f0617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364997220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2364997220
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4264381120
Short name T366
Test name
Test status
Simulation time 6615112724 ps
CPU time 16.51 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:49 PM PDT 24
Peak memory 205508 kb
Host smart-2c873a27-6fc3-4ec5-8af0-1e2b92ec1294
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264381120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.4264381120
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1803972323
Short name T341
Test name
Test status
Simulation time 12096685522 ps
CPU time 10.53 seconds
Started Aug 03 04:32:35 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 205492 kb
Host smart-09b1cded-9820-4700-a65b-c10ff891fef3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803972323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1803972323
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.368630477
Short name T392
Test name
Test status
Simulation time 877846428 ps
CPU time 1.01 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:35 PM PDT 24
Peak memory 205228 kb
Host smart-1d458681-a6c4-40aa-83c5-52c0e27fb214
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368630477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.368630477
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1436189663
Short name T425
Test name
Test status
Simulation time 110493698 ps
CPU time 3.52 seconds
Started Aug 03 04:32:40 PM PDT 24
Finished Aug 03 04:32:44 PM PDT 24
Peak memory 205512 kb
Host smart-247cd607-be2a-4979-8ff2-5fd5280d55d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436189663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1436189663
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2403644428
Short name T351
Test name
Test status
Simulation time 264696999 ps
CPU time 2.26 seconds
Started Aug 03 04:32:36 PM PDT 24
Finished Aug 03 04:32:38 PM PDT 24
Peak memory 213916 kb
Host smart-966d859d-1514-4620-9f72-0c591143beb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403644428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2403644428
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.732131663
Short name T165
Test name
Test status
Simulation time 1717903828 ps
CPU time 9.32 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:32:49 PM PDT 24
Peak memory 213796 kb
Host smart-1d53edaf-2fa8-40f2-abe2-3acef7d17b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732131663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.732131663
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3546219653
Short name T313
Test name
Test status
Simulation time 179509552 ps
CPU time 2.49 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 221924 kb
Host smart-2623e220-384a-4807-8ad6-78ec08c15b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546219653 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3546219653
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4051424566
Short name T312
Test name
Test status
Simulation time 43312683245 ps
CPU time 69.19 seconds
Started Aug 03 04:32:49 PM PDT 24
Finished Aug 03 04:34:03 PM PDT 24
Peak memory 205540 kb
Host smart-60eff358-7076-4143-87aa-1d9c758941b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051424566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.4051424566
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.261757075
Short name T434
Test name
Test status
Simulation time 6908352594 ps
CPU time 6.37 seconds
Started Aug 03 04:32:45 PM PDT 24
Finished Aug 03 04:32:52 PM PDT 24
Peak memory 205496 kb
Host smart-cded4f85-74cb-40d7-8a6a-a24985be0b8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261757075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.261757075
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2639498547
Short name T415
Test name
Test status
Simulation time 626786458 ps
CPU time 0.8 seconds
Started Aug 03 04:32:44 PM PDT 24
Finished Aug 03 04:32:45 PM PDT 24
Peak memory 205184 kb
Host smart-88dd04b0-254b-40e2-8aa7-766bf156e91f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639498547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2639498547
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1287365770
Short name T106
Test name
Test status
Simulation time 610695828 ps
CPU time 8.15 seconds
Started Aug 03 04:32:40 PM PDT 24
Finished Aug 03 04:32:48 PM PDT 24
Peak memory 205548 kb
Host smart-7b32782e-1ad0-4eb4-ab67-e70ac1206e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287365770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1287365770
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4138260621
Short name T321
Test name
Test status
Simulation time 259007926 ps
CPU time 2.3 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 213812 kb
Host smart-ae0ae480-f8f5-409f-af84-d464ca8ac7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138260621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4138260621
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3762163718
Short name T157
Test name
Test status
Simulation time 2671122589 ps
CPU time 20.63 seconds
Started Aug 03 04:32:52 PM PDT 24
Finished Aug 03 04:33:13 PM PDT 24
Peak memory 213932 kb
Host smart-58e4ae3c-b890-4413-b352-bda9c59d5c78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762163718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
762163718
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1551700021
Short name T453
Test name
Test status
Simulation time 190862602 ps
CPU time 2.71 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 218168 kb
Host smart-a8462029-fb10-4e47-be40-39f6f17ca43a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551700021 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1551700021
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3862600827
Short name T97
Test name
Test status
Simulation time 265095182 ps
CPU time 1.58 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:44 PM PDT 24
Peak memory 213960 kb
Host smart-db086928-68ca-4bb4-8b8b-039f908e1fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862600827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3862600827
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2491516303
Short name T361
Test name
Test status
Simulation time 10839752306 ps
CPU time 13.79 seconds
Started Aug 03 04:32:44 PM PDT 24
Finished Aug 03 04:32:58 PM PDT 24
Peak memory 205428 kb
Host smart-f447f1a5-d745-40ff-a9fb-bbf9e98047c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491516303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2491516303
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2537161902
Short name T332
Test name
Test status
Simulation time 11377571613 ps
CPU time 15.56 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:32:59 PM PDT 24
Peak memory 205492 kb
Host smart-4aa27ba9-1cc5-408a-b7c0-a86ced57c157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537161902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2537161902
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2923815188
Short name T388
Test name
Test status
Simulation time 183903225 ps
CPU time 1.01 seconds
Started Aug 03 04:32:40 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 205192 kb
Host smart-d18e3a76-ae4c-41c1-872b-50b8b03e3968
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923815188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2923815188
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3537559256
Short name T110
Test name
Test status
Simulation time 116145164 ps
CPU time 3.64 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:32:45 PM PDT 24
Peak memory 205520 kb
Host smart-735d214e-ba09-4d3f-a001-d5970582f79b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537559256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3537559256
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.186867911
Short name T316
Test name
Test status
Simulation time 526858487 ps
CPU time 6.1 seconds
Started Aug 03 04:33:00 PM PDT 24
Finished Aug 03 04:33:06 PM PDT 24
Peak memory 213768 kb
Host smart-0d76f6b1-e010-488a-ac06-4bdd5afbe0ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186867911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.186867911
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.17551873
Short name T88
Test name
Test status
Simulation time 5877150764 ps
CPU time 28.49 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:33:08 PM PDT 24
Peak memory 222056 kb
Host smart-406a01ee-2c5f-4474-8bc9-863a84057e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.17551873
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3061414490
Short name T390
Test name
Test status
Simulation time 231559185 ps
CPU time 2.49 seconds
Started Aug 03 04:33:06 PM PDT 24
Finished Aug 03 04:33:08 PM PDT 24
Peak memory 218716 kb
Host smart-bcc3be55-5734-45b1-9e58-dcd11b96ef81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061414490 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3061414490
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1033435486
Short name T121
Test name
Test status
Simulation time 533511328 ps
CPU time 2.46 seconds
Started Aug 03 04:32:40 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 213716 kb
Host smart-ed62543d-6c81-4c52-b72c-e9c27d6b7974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033435486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1033435486
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1658183107
Short name T460
Test name
Test status
Simulation time 17684563999 ps
CPU time 12.92 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:55 PM PDT 24
Peak memory 205536 kb
Host smart-d3de360b-4d4c-4494-89c3-5fc4c742aaeb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658183107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1658183107
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2991001706
Short name T346
Test name
Test status
Simulation time 1104494578 ps
CPU time 3.93 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:32:47 PM PDT 24
Peak memory 205260 kb
Host smart-e36c893a-aa00-463e-b30b-42e3c7ae2add
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991001706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2991001706
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.266298409
Short name T462
Test name
Test status
Simulation time 86808787 ps
CPU time 0.89 seconds
Started Aug 03 04:33:04 PM PDT 24
Finished Aug 03 04:33:05 PM PDT 24
Peak memory 205200 kb
Host smart-79f8837a-1326-462d-9100-63c361e9a351
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266298409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.266298409
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2052794577
Short name T440
Test name
Test status
Simulation time 759409204 ps
CPU time 4.29 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 205556 kb
Host smart-1edf259d-a41b-43ef-883c-7d9e9a134563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052794577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2052794577
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2711551854
Short name T459
Test name
Test status
Simulation time 947968308 ps
CPU time 5.83 seconds
Started Aug 03 04:33:04 PM PDT 24
Finished Aug 03 04:33:10 PM PDT 24
Peak memory 213820 kb
Host smart-1ca3547d-05bc-438b-bfbb-60dd819daac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711551854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2711551854
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3521411213
Short name T159
Test name
Test status
Simulation time 3410765339 ps
CPU time 14.48 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 214148 kb
Host smart-81587a8d-a84b-4b6f-8044-a2aa9e361905
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521411213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
521411213
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.415480943
Short name T349
Test name
Test status
Simulation time 398380850 ps
CPU time 3.97 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:32:48 PM PDT 24
Peak memory 221916 kb
Host smart-70e9db8c-9421-455a-966f-c1d0cc94d003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415480943 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.415480943
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1183258955
Short name T428
Test name
Test status
Simulation time 230512196 ps
CPU time 2.71 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:32:44 PM PDT 24
Peak memory 213820 kb
Host smart-1bfa0f60-4b88-4bea-8ac6-2e80732a7c40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183258955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1183258955
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1285040835
Short name T399
Test name
Test status
Simulation time 65388960580 ps
CPU time 50.31 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:33:31 PM PDT 24
Peak memory 205504 kb
Host smart-6cbed1de-5822-4e72-aef7-dcf5934d9133
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285040835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1285040835
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2996212970
Short name T310
Test name
Test status
Simulation time 15427464503 ps
CPU time 41.78 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:33:25 PM PDT 24
Peak memory 205508 kb
Host smart-fae92f4a-15e9-4493-8e29-21362822ae63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996212970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2996212970
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2491056694
Short name T398
Test name
Test status
Simulation time 608640346 ps
CPU time 0.89 seconds
Started Aug 03 04:32:40 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 205184 kb
Host smart-942ad736-e0a3-4cbe-b496-1881a1f0f01b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491056694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2491056694
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.65181883
Short name T463
Test name
Test status
Simulation time 91524926 ps
CPU time 3.48 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 205584 kb
Host smart-3af4f97e-8efe-4cdb-aefe-ed31561a7271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65181883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_c
sr_outstanding.65181883
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.312786452
Short name T131
Test name
Test status
Simulation time 1043697819 ps
CPU time 5.88 seconds
Started Aug 03 04:32:44 PM PDT 24
Finished Aug 03 04:32:50 PM PDT 24
Peak memory 213708 kb
Host smart-70c9c5f6-b95c-49fa-9cb7-432a75b1c144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312786452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.312786452
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2586968414
Short name T100
Test name
Test status
Simulation time 473699268 ps
CPU time 4.53 seconds
Started Aug 03 04:32:48 PM PDT 24
Finished Aug 03 04:32:53 PM PDT 24
Peak memory 221936 kb
Host smart-699eb0af-8d1d-4089-81c8-4231e71f5327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586968414 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2586968414
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1593068579
Short name T93
Test name
Test status
Simulation time 227702827 ps
CPU time 1.58 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:32:44 PM PDT 24
Peak memory 213520 kb
Host smart-6e715632-c37c-4061-a228-2b81ccf67cc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593068579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1593068579
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4037001504
Short name T410
Test name
Test status
Simulation time 21009532681 ps
CPU time 19.39 seconds
Started Aug 03 04:32:44 PM PDT 24
Finished Aug 03 04:33:03 PM PDT 24
Peak memory 205488 kb
Host smart-4194f991-5bc9-4eb4-ba93-cee13f3af0d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037001504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.4037001504
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.603376229
Short name T364
Test name
Test status
Simulation time 7793099701 ps
CPU time 19.71 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:33:03 PM PDT 24
Peak memory 205512 kb
Host smart-6a1bdcb7-cf51-42f3-9869-112de474b2d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603376229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.603376229
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2815313632
Short name T338
Test name
Test status
Simulation time 136677976 ps
CPU time 1.03 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:32:40 PM PDT 24
Peak memory 205188 kb
Host smart-171cb7b6-9adb-44ee-aba9-2efde8dba829
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815313632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2815313632
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.208431913
Short name T435
Test name
Test status
Simulation time 3605551091 ps
CPU time 4.56 seconds
Started Aug 03 04:32:40 PM PDT 24
Finished Aug 03 04:32:45 PM PDT 24
Peak memory 205636 kb
Host smart-0739e5df-51d7-4b8a-91f7-b315ad1eb83e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208431913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.208431913
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1071500054
Short name T451
Test name
Test status
Simulation time 130292397 ps
CPU time 5.66 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:32:47 PM PDT 24
Peak memory 213784 kb
Host smart-8af7095a-d808-4913-bab5-90376b5caed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071500054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1071500054
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.199789772
Short name T396
Test name
Test status
Simulation time 301062634 ps
CPU time 3.75 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 220452 kb
Host smart-59ed165f-88c1-4b36-bd20-d6fadae0809c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199789772 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.199789772
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2331379406
Short name T402
Test name
Test status
Simulation time 159074179 ps
CPU time 1.61 seconds
Started Aug 03 04:33:04 PM PDT 24
Finished Aug 03 04:33:06 PM PDT 24
Peak memory 213648 kb
Host smart-e7d7b727-3289-436d-a18d-0830ec1e499d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331379406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2331379406
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2700399998
Short name T354
Test name
Test status
Simulation time 22461179498 ps
CPU time 36.88 seconds
Started Aug 03 04:32:48 PM PDT 24
Finished Aug 03 04:33:25 PM PDT 24
Peak memory 205596 kb
Host smart-5231ba6f-8abf-4de9-9c2c-57962d451291
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700399998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2700399998
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3521762637
Short name T363
Test name
Test status
Simulation time 13658955626 ps
CPU time 7.4 seconds
Started Aug 03 04:32:47 PM PDT 24
Finished Aug 03 04:32:54 PM PDT 24
Peak memory 205572 kb
Host smart-ff2fbc51-ad70-4c8a-8519-d4708b0d46f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521762637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3521762637
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2374763916
Short name T409
Test name
Test status
Simulation time 757637533 ps
CPU time 2.68 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:32:44 PM PDT 24
Peak memory 205204 kb
Host smart-69103db2-c604-45ad-bfb5-13324532d3ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374763916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2374763916
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.397376239
Short name T128
Test name
Test status
Simulation time 188731649 ps
CPU time 3.27 seconds
Started Aug 03 04:32:39 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 213852 kb
Host smart-beb379e5-7e5c-4d71-8418-14f8f72c17c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397376239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.397376239
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1680189441
Short name T335
Test name
Test status
Simulation time 3367784974 ps
CPU time 17.16 seconds
Started Aug 03 04:32:41 PM PDT 24
Finished Aug 03 04:32:58 PM PDT 24
Peak memory 213916 kb
Host smart-92fe23ec-0e53-4d54-90eb-1872daebe3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680189441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
680189441
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3615309330
Short name T326
Test name
Test status
Simulation time 115159812 ps
CPU time 2.46 seconds
Started Aug 03 04:33:09 PM PDT 24
Finished Aug 03 04:33:12 PM PDT 24
Peak memory 213796 kb
Host smart-8dc84cc2-8cf8-4f95-a766-2b054324ac31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615309330 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3615309330
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.237283170
Short name T95
Test name
Test status
Simulation time 122806197 ps
CPU time 1.55 seconds
Started Aug 03 04:32:49 PM PDT 24
Finished Aug 03 04:32:51 PM PDT 24
Peak memory 213768 kb
Host smart-6e05163b-e2f6-4a6b-8d97-2bc10c52756b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237283170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.237283170
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2880767242
Short name T419
Test name
Test status
Simulation time 120321537 ps
CPU time 0.68 seconds
Started Aug 03 04:33:09 PM PDT 24
Finished Aug 03 04:33:10 PM PDT 24
Peak memory 205240 kb
Host smart-4a14cedb-cf45-4262-88ec-7daed5b18025
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880767242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2880767242
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3602133461
Short name T311
Test name
Test status
Simulation time 1733118640 ps
CPU time 6.24 seconds
Started Aug 03 04:33:05 PM PDT 24
Finished Aug 03 04:33:11 PM PDT 24
Peak memory 205400 kb
Host smart-6ada0218-1e87-48d7-929c-580f772169c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602133461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3602133461
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3688467648
Short name T384
Test name
Test status
Simulation time 145955154 ps
CPU time 0.98 seconds
Started Aug 03 04:32:43 PM PDT 24
Finished Aug 03 04:32:44 PM PDT 24
Peak memory 205216 kb
Host smart-4f76f2c9-b8b3-4bf5-8f41-e503571f5842
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688467648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3688467648
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.854478260
Short name T109
Test name
Test status
Simulation time 1365259449 ps
CPU time 7.07 seconds
Started Aug 03 04:32:53 PM PDT 24
Finished Aug 03 04:33:00 PM PDT 24
Peak memory 205560 kb
Host smart-ebfcdfab-24cf-4551-87b4-f38ba92edfcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854478260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.854478260
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1347249284
Short name T329
Test name
Test status
Simulation time 260812207 ps
CPU time 4.75 seconds
Started Aug 03 04:32:51 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 213828 kb
Host smart-36c31d4f-7066-4bc2-8699-61393f42088e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347249284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1347249284
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1559266399
Short name T365
Test name
Test status
Simulation time 729677193 ps
CPU time 4 seconds
Started Aug 03 04:32:54 PM PDT 24
Finished Aug 03 04:32:58 PM PDT 24
Peak memory 219852 kb
Host smart-937e138c-9589-4b22-be85-23133b572399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559266399 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1559266399
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3658239567
Short name T119
Test name
Test status
Simulation time 347695544 ps
CPU time 2.34 seconds
Started Aug 03 04:32:54 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 213744 kb
Host smart-d3a314fa-220e-4a43-9a7f-3e821a032882
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658239567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3658239567
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2141604260
Short name T333
Test name
Test status
Simulation time 12908949506 ps
CPU time 11.86 seconds
Started Aug 03 04:32:53 PM PDT 24
Finished Aug 03 04:33:05 PM PDT 24
Peak memory 205424 kb
Host smart-3348e505-8eeb-4f3a-8972-df9aee6de3a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141604260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2141604260
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4289628527
Short name T318
Test name
Test status
Simulation time 14271794388 ps
CPU time 39.35 seconds
Started Aug 03 04:32:52 PM PDT 24
Finished Aug 03 04:33:32 PM PDT 24
Peak memory 205484 kb
Host smart-917c88b0-d119-4a42-9c14-dad115516b53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289628527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4289628527
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.905092922
Short name T373
Test name
Test status
Simulation time 631200233 ps
CPU time 1.04 seconds
Started Aug 03 04:32:54 PM PDT 24
Finished Aug 03 04:32:55 PM PDT 24
Peak memory 205196 kb
Host smart-c057e4ac-0827-44ce-95c9-c80eb89cf4c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905092922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.905092922
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.554997000
Short name T447
Test name
Test status
Simulation time 295811390 ps
CPU time 4.26 seconds
Started Aug 03 04:32:51 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 205476 kb
Host smart-b9ffac52-8945-4d36-874e-2947f4f7f57c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554997000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.554997000
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.764106948
Short name T86
Test name
Test status
Simulation time 170597505 ps
CPU time 2.87 seconds
Started Aug 03 04:32:55 PM PDT 24
Finished Aug 03 04:32:58 PM PDT 24
Peak memory 213800 kb
Host smart-652642f9-ae60-4f7d-aa47-134e97af873e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764106948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.764106948
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4082475781
Short name T164
Test name
Test status
Simulation time 2643743511 ps
CPU time 11.36 seconds
Started Aug 03 04:32:48 PM PDT 24
Finished Aug 03 04:33:00 PM PDT 24
Peak memory 222036 kb
Host smart-c4539358-8031-4855-919a-96cab362a41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082475781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
082475781
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1836863243
Short name T120
Test name
Test status
Simulation time 4699179722 ps
CPU time 79.04 seconds
Started Aug 03 04:32:17 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 213792 kb
Host smart-5d53f6df-ce1b-4424-8b8b-a076d70b1231
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836863243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1836863243
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2758529583
Short name T94
Test name
Test status
Simulation time 69863999979 ps
CPU time 67.65 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:33:28 PM PDT 24
Peak memory 205632 kb
Host smart-7915e5b3-f153-484b-8293-8eeb469630f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758529583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2758529583
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3612568000
Short name T122
Test name
Test status
Simulation time 222585950 ps
CPU time 1.67 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 213680 kb
Host smart-884880db-aec9-45c0-9a6f-213c6f1d2b57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612568000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3612568000
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1820873470
Short name T376
Test name
Test status
Simulation time 568206569 ps
CPU time 3.74 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:25 PM PDT 24
Peak memory 221924 kb
Host smart-dab3cef3-c812-4fc3-93ff-8ffcd59fcdc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820873470 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1820873470
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3590858635
Short name T107
Test name
Test status
Simulation time 94268840 ps
CPU time 1.41 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 213720 kb
Host smart-fd508379-456b-4353-897a-30b32324af07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590858635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3590858635
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3934455230
Short name T348
Test name
Test status
Simulation time 207464701724 ps
CPU time 327.93 seconds
Started Aug 03 04:32:22 PM PDT 24
Finished Aug 03 04:37:50 PM PDT 24
Peak memory 210340 kb
Host smart-ab396d97-6234-452d-8c13-c3a31f2b3053
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934455230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3934455230
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.436657002
Short name T327
Test name
Test status
Simulation time 36070868867 ps
CPU time 29.21 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:51 PM PDT 24
Peak memory 205484 kb
Host smart-3f5410e3-c15d-4731-9b53-7096fcf1bb60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436657002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.436657002
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.738981232
Short name T102
Test name
Test status
Simulation time 1970250955 ps
CPU time 4.08 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:25 PM PDT 24
Peak memory 205516 kb
Host smart-16f7172c-162c-4f0a-9cf6-a6230eb9485a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738981232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.738981232
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1762784370
Short name T412
Test name
Test status
Simulation time 3126296465 ps
CPU time 2.05 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 205536 kb
Host smart-0d719be4-d8f1-4e60-821b-33610be507dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762784370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
762784370
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.401835232
Short name T64
Test name
Test status
Simulation time 589940764 ps
CPU time 1.18 seconds
Started Aug 03 04:32:19 PM PDT 24
Finished Aug 03 04:32:21 PM PDT 24
Peak memory 205292 kb
Host smart-d76e9e75-048e-40ee-9a8d-abea30a81efb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401835232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.401835232
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4223941968
Short name T424
Test name
Test status
Simulation time 5227660935 ps
CPU time 4.88 seconds
Started Aug 03 04:32:24 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205492 kb
Host smart-9b3b0ffc-3e54-4012-9559-f25c6b3e087d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223941968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4223941968
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3330021143
Short name T314
Test name
Test status
Simulation time 724655059 ps
CPU time 1.26 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:21 PM PDT 24
Peak memory 204728 kb
Host smart-6d152dc0-f610-4b36-95a3-53d02756cb35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330021143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3330021143
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3096696320
Short name T62
Test name
Test status
Simulation time 551214325 ps
CPU time 1.51 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:21 PM PDT 24
Peak memory 205228 kb
Host smart-b29fd627-019a-4d89-902e-eb20d055ba2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096696320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
096696320
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2330057328
Short name T461
Test name
Test status
Simulation time 49094595 ps
CPU time 0.74 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 204732 kb
Host smart-584f5ef1-a468-4f6a-b779-6e0c8d5814d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330057328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2330057328
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3789433146
Short name T362
Test name
Test status
Simulation time 41483304 ps
CPU time 0.76 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 205248 kb
Host smart-7ed57952-76ef-4ce8-a5e9-daf4fcc85feb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789433146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3789433146
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3120281754
Short name T123
Test name
Test status
Simulation time 182979559 ps
CPU time 6.31 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:32:25 PM PDT 24
Peak memory 205520 kb
Host smart-d6f4e85f-dd63-4c42-91bf-1e4c8929d5cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120281754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3120281754
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3038837404
Short name T352
Test name
Test status
Simulation time 220288148 ps
CPU time 2.24 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:22 PM PDT 24
Peak memory 213732 kb
Host smart-625a08c6-09b0-4c3d-a9ea-682c9766cd78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038837404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3038837404
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.387533520
Short name T375
Test name
Test status
Simulation time 609151183 ps
CPU time 25.97 seconds
Started Aug 03 04:32:19 PM PDT 24
Finished Aug 03 04:32:45 PM PDT 24
Peak memory 205628 kb
Host smart-c1ccbda1-b780-4daa-8b82-a12d1ee54820
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387533520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.387533520
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1994115996
Short name T118
Test name
Test status
Simulation time 2033968921 ps
CPU time 51.79 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:33:20 PM PDT 24
Peak memory 213692 kb
Host smart-a8a66b3c-87ae-4901-8afb-48e4294a6a96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994115996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1994115996
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2719594561
Short name T91
Test name
Test status
Simulation time 703294041 ps
CPU time 2.61 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:28 PM PDT 24
Peak memory 214744 kb
Host smart-ea09d55a-e0cd-4569-8522-f39176548f6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719594561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2719594561
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3312728332
Short name T386
Test name
Test status
Simulation time 540432829 ps
CPU time 2.5 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 221824 kb
Host smart-6c9636ec-cc8d-44e4-a329-8f347fce008a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312728332 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3312728332
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1486512076
Short name T458
Test name
Test status
Simulation time 76753505 ps
CPU time 1.63 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:32:32 PM PDT 24
Peak memory 213604 kb
Host smart-ea00c6a5-5e7b-439a-96ef-0e81fe860666
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486512076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1486512076
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3220633054
Short name T389
Test name
Test status
Simulation time 80467018354 ps
CPU time 79.04 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 205556 kb
Host smart-2b437ae9-d4f7-4064-a0a9-0f68f4dc6403
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220633054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3220633054
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1960422323
Short name T320
Test name
Test status
Simulation time 2813659865 ps
CPU time 3.26 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:30 PM PDT 24
Peak memory 205592 kb
Host smart-4be346bf-568e-42ee-828f-6b4dda94785f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960422323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1960422323
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3554732928
Short name T103
Test name
Test status
Simulation time 10719891681 ps
CPU time 17.47 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:38 PM PDT 24
Peak memory 205584 kb
Host smart-ff9298fe-7056-4f41-99c7-236edae4516d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554732928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3554732928
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3182598673
Short name T336
Test name
Test status
Simulation time 1515710169 ps
CPU time 4.88 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:32:36 PM PDT 24
Peak memory 205408 kb
Host smart-51e85972-1249-4fdf-b9d6-166306b076e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182598673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
182598673
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2607803211
Short name T406
Test name
Test status
Simulation time 560805279 ps
CPU time 2.16 seconds
Started Aug 03 04:32:21 PM PDT 24
Finished Aug 03 04:32:23 PM PDT 24
Peak memory 204672 kb
Host smart-0a94b699-1eb9-4fbd-b542-14e164ff5fa0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607803211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2607803211
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3624490330
Short name T63
Test name
Test status
Simulation time 15257202223 ps
CPU time 21.89 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 205460 kb
Host smart-d2a80924-90ff-417c-8c52-097248628627
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624490330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3624490330
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1791383414
Short name T381
Test name
Test status
Simulation time 151308364 ps
CPU time 1.03 seconds
Started Aug 03 04:32:20 PM PDT 24
Finished Aug 03 04:32:21 PM PDT 24
Peak memory 205292 kb
Host smart-fd7d317a-7c7b-4da9-8e12-acabe67de9ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791383414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1791383414
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2678517796
Short name T421
Test name
Test status
Simulation time 220807477 ps
CPU time 1.24 seconds
Started Aug 03 04:32:18 PM PDT 24
Finished Aug 03 04:32:20 PM PDT 24
Peak memory 205200 kb
Host smart-de3aa94d-d73f-420f-a137-061974d22b71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678517796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
678517796
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2694961035
Short name T347
Test name
Test status
Simulation time 74009866 ps
CPU time 0.71 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205280 kb
Host smart-f3fc594b-ca50-4f33-ab63-4c86e48fa6b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694961035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2694961035
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3721938309
Short name T359
Test name
Test status
Simulation time 42867857 ps
CPU time 0.69 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:32:30 PM PDT 24
Peak memory 205168 kb
Host smart-e24a671e-86e8-4285-9727-4b51f99e4255
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721938309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3721938309
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3266899184
Short name T125
Test name
Test status
Simulation time 1662149597 ps
CPU time 7.81 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:34 PM PDT 24
Peak memory 205504 kb
Host smart-1785c42b-453f-4127-838b-47e71950f7bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266899184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3266899184
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.246544191
Short name T60
Test name
Test status
Simulation time 18069057936 ps
CPU time 27.86 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:32:57 PM PDT 24
Peak memory 219620 kb
Host smart-52069e8b-862b-4a76-9f33-708fc822da0b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246544191 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.246544191
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3027558418
Short name T342
Test name
Test status
Simulation time 350076585 ps
CPU time 1.82 seconds
Started Aug 03 04:32:25 PM PDT 24
Finished Aug 03 04:32:27 PM PDT 24
Peak memory 213748 kb
Host smart-609722a2-a51a-4425-b80a-47dffa85f184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027558418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3027558418
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3561821784
Short name T161
Test name
Test status
Simulation time 2812716751 ps
CPU time 22.83 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:50 PM PDT 24
Peak memory 213852 kb
Host smart-4942b082-ac07-411e-a690-6cb474d99c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561821784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3561821784
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1859366274
Short name T96
Test name
Test status
Simulation time 1720623308 ps
CPU time 30.53 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 214868 kb
Host smart-08ddf404-fcb5-44ab-8675-37dbbf3e7652
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859366274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1859366274
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.704674239
Short name T445
Test name
Test status
Simulation time 5127112672 ps
CPU time 67.73 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:33:34 PM PDT 24
Peak memory 214076 kb
Host smart-869ecbd8-c341-46d8-8c99-4a87f8426111
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704674239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.704674239
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.522597420
Short name T117
Test name
Test status
Simulation time 512432197 ps
CPU time 2.44 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:32:30 PM PDT 24
Peak memory 213824 kb
Host smart-328257bb-8a97-42d2-bcfb-fe8a3ca27b2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522597420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.522597420
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2362309056
Short name T449
Test name
Test status
Simulation time 278413024 ps
CPU time 2.35 seconds
Started Aug 03 04:32:23 PM PDT 24
Finished Aug 03 04:32:26 PM PDT 24
Peak memory 217568 kb
Host smart-dd4d970f-fc09-4afe-87e4-926c530fa33b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362309056 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2362309056
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1079988914
Short name T442
Test name
Test status
Simulation time 569140665 ps
CPU time 2.35 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 213652 kb
Host smart-b617927f-897a-4730-aa7b-21edecc47b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079988914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1079988914
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.131557631
Short name T400
Test name
Test status
Simulation time 48644080918 ps
CPU time 138.26 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:34:46 PM PDT 24
Peak memory 205556 kb
Host smart-8a6047cb-1b5f-451e-8dfa-0d80b4138a4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131557631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.131557631
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.446464471
Short name T353
Test name
Test status
Simulation time 47162157615 ps
CPU time 27.29 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 205512 kb
Host smart-10631416-1e6e-429b-9c34-0d2666d85098
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446464471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.446464471
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2541460596
Short name T104
Test name
Test status
Simulation time 1616664593 ps
CPU time 5.2 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:32 PM PDT 24
Peak memory 205452 kb
Host smart-55aeb1f1-b053-4436-81ea-9f95eb5e0b82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541460596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2541460596
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1547722544
Short name T422
Test name
Test status
Simulation time 1374212373 ps
CPU time 3.62 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:31 PM PDT 24
Peak memory 205420 kb
Host smart-d427181e-6e85-44a1-a5d7-1828a8b5a019
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547722544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
547722544
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1332284467
Short name T371
Test name
Test status
Simulation time 781238268 ps
CPU time 1.42 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205204 kb
Host smart-df5f688e-20ae-4792-8aaa-b50b475b9bf0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332284467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1332284467
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3693901508
Short name T323
Test name
Test status
Simulation time 14539419382 ps
CPU time 40.9 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:33:10 PM PDT 24
Peak memory 205492 kb
Host smart-98c0be1e-6f0c-4a6a-b7cc-fec7c674ce71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693901508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3693901508
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2044381132
Short name T450
Test name
Test status
Simulation time 439963873 ps
CPU time 1.18 seconds
Started Aug 03 04:32:30 PM PDT 24
Finished Aug 03 04:32:31 PM PDT 24
Peak memory 205236 kb
Host smart-1e58d2cf-2fc5-4a70-9cb8-dcfdb093b048
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044381132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2044381132
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1541642463
Short name T446
Test name
Test status
Simulation time 156759554 ps
CPU time 0.87 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:28 PM PDT 24
Peak memory 205228 kb
Host smart-9c8c15e6-b826-442a-a9d9-da8fa7dd0173
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541642463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
541642463
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2906282085
Short name T427
Test name
Test status
Simulation time 42000885 ps
CPU time 0.75 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:28 PM PDT 24
Peak memory 205264 kb
Host smart-27db2572-9480-4372-a4c3-7894de5839d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906282085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2906282085
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.961384857
Short name T387
Test name
Test status
Simulation time 69771860 ps
CPU time 0.84 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205220 kb
Host smart-78fab4b6-b43a-4b86-980e-0f5bc9a40e1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961384857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.961384857
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3311783659
Short name T443
Test name
Test status
Simulation time 350506711 ps
CPU time 4.31 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:32:33 PM PDT 24
Peak memory 205504 kb
Host smart-789f94fc-cc43-44de-9300-34fca0e820f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311783659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3311783659
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2702121989
Short name T168
Test name
Test status
Simulation time 63813567384 ps
CPU time 38.33 seconds
Started Aug 03 04:32:30 PM PDT 24
Finished Aug 03 04:33:09 PM PDT 24
Peak memory 230408 kb
Host smart-50f4fe8d-91a7-43e7-9996-11ca139a27f5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702121989 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2702121989
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4187582935
Short name T330
Test name
Test status
Simulation time 59886905 ps
CPU time 2.63 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 213884 kb
Host smart-1462668a-b282-402b-b6c9-e340ab43e004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187582935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4187582935
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4106086621
Short name T160
Test name
Test status
Simulation time 6231445074 ps
CPU time 20.73 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:32:51 PM PDT 24
Peak memory 221956 kb
Host smart-070513f3-2b01-4abb-81d8-35f0ffdc81c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106086621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4106086621
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3269043860
Short name T454
Test name
Test status
Simulation time 443532086 ps
CPU time 4.5 seconds
Started Aug 03 04:32:29 PM PDT 24
Finished Aug 03 04:32:33 PM PDT 24
Peak memory 221928 kb
Host smart-90df03c7-2f93-42d4-a88e-1924aa4418d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269043860 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3269043860
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2363252664
Short name T403
Test name
Test status
Simulation time 60827520 ps
CPU time 1.39 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:32:33 PM PDT 24
Peak memory 213684 kb
Host smart-cffaed99-9120-42ee-8147-906ab7313f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363252664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2363252664
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4284580565
Short name T394
Test name
Test status
Simulation time 74139034685 ps
CPU time 39.33 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:33:11 PM PDT 24
Peak memory 205420 kb
Host smart-38d8537d-e561-485c-87e0-85779a794541
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284580565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.4284580565
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2920238056
Short name T357
Test name
Test status
Simulation time 6713654547 ps
CPU time 18.37 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 205508 kb
Host smart-c48a5925-e7b3-440b-a935-f3b3b1726e06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920238056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
920238056
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1019889052
Short name T345
Test name
Test status
Simulation time 192040998 ps
CPU time 1.11 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205244 kb
Host smart-29978d45-7aa2-4b82-b489-0184a7ac1976
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019889052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
019889052
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2011104748
Short name T124
Test name
Test status
Simulation time 320383427 ps
CPU time 4.05 seconds
Started Aug 03 04:32:25 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205536 kb
Host smart-8ce65a60-2e1a-4474-b68f-cf209f5b9910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011104748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2011104748
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2699151027
Short name T355
Test name
Test status
Simulation time 32228507541 ps
CPU time 127.19 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:34:33 PM PDT 24
Peak memory 221524 kb
Host smart-80419691-d318-4d42-9e66-5dabdcd921de
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699151027 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2699151027
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2486185712
Short name T369
Test name
Test status
Simulation time 50147867 ps
CPU time 2.35 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 213768 kb
Host smart-06790c76-da6c-40d9-aa8a-382359b5aad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486185712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2486185712
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4201395762
Short name T156
Test name
Test status
Simulation time 6542523789 ps
CPU time 32.05 seconds
Started Aug 03 04:32:26 PM PDT 24
Finished Aug 03 04:32:58 PM PDT 24
Peak memory 213904 kb
Host smart-a7662c6d-28ac-4c4b-b3ff-3f17bee723cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201395762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4201395762
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1408528315
Short name T423
Test name
Test status
Simulation time 119450554 ps
CPU time 2.78 seconds
Started Aug 03 04:32:35 PM PDT 24
Finished Aug 03 04:32:38 PM PDT 24
Peak memory 213776 kb
Host smart-e4f462a2-0a70-4939-a24c-da83ab2684d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408528315 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1408528315
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3745477237
Short name T377
Test name
Test status
Simulation time 74494524 ps
CPU time 1.5 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:43 PM PDT 24
Peak memory 213740 kb
Host smart-28f5e7de-ac28-46b7-82ae-934a2b03fb5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745477237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3745477237
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3051964733
Short name T395
Test name
Test status
Simulation time 50239536 ps
CPU time 0.65 seconds
Started Aug 03 04:32:28 PM PDT 24
Finished Aug 03 04:32:29 PM PDT 24
Peak memory 205252 kb
Host smart-0a0358fc-3994-47cf-a461-6a1a89e02cfc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051964733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3051964733
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1464497135
Short name T379
Test name
Test status
Simulation time 9537075789 ps
CPU time 10.7 seconds
Started Aug 03 04:32:30 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 205492 kb
Host smart-5af3da66-f73f-4508-a21a-1c68139fab58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464497135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
464497135
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.378305002
Short name T339
Test name
Test status
Simulation time 763516474 ps
CPU time 1.11 seconds
Started Aug 03 04:32:24 PM PDT 24
Finished Aug 03 04:32:25 PM PDT 24
Peak memory 205308 kb
Host smart-6b117476-f0ed-4b78-8e53-b59e4c7306f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378305002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.378305002
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4277275216
Short name T111
Test name
Test status
Simulation time 439899344 ps
CPU time 7.6 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 205444 kb
Host smart-05135134-c278-4643-873e-24ad604ec71b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277275216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.4277275216
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3562328360
Short name T61
Test name
Test status
Simulation time 22550544228 ps
CPU time 72.86 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 222100 kb
Host smart-ec5bfb28-0b79-406b-aea9-375ae9e85f76
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562328360 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3562328360
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.349533977
Short name T416
Test name
Test status
Simulation time 218073339 ps
CPU time 3.18 seconds
Started Aug 03 04:32:27 PM PDT 24
Finished Aug 03 04:32:31 PM PDT 24
Peak memory 213784 kb
Host smart-0b92c0be-5e2b-4314-a659-793dfea4d869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349533977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.349533977
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4210615273
Short name T438
Test name
Test status
Simulation time 623321418 ps
CPU time 3.88 seconds
Started Aug 03 04:32:32 PM PDT 24
Finished Aug 03 04:32:36 PM PDT 24
Peak memory 221692 kb
Host smart-abcffbba-9c6f-4508-8c81-9ee1e3dcca6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210615273 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.4210615273
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.438959201
Short name T393
Test name
Test status
Simulation time 238587443 ps
CPU time 1.62 seconds
Started Aug 03 04:32:36 PM PDT 24
Finished Aug 03 04:32:38 PM PDT 24
Peak memory 213700 kb
Host smart-d226c2a6-447e-47c1-a51f-ac6e515e3497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438959201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.438959201
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3024357103
Short name T337
Test name
Test status
Simulation time 27162144737 ps
CPU time 16.62 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:50 PM PDT 24
Peak memory 205480 kb
Host smart-3422ef89-f9ce-4c95-8b19-61588388ece9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024357103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3024357103
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2847193283
Short name T319
Test name
Test status
Simulation time 2531717681 ps
CPU time 2.88 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:45 PM PDT 24
Peak memory 205536 kb
Host smart-8e5d77cc-dd27-4d16-9b23-285be51506d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847193283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
847193283
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.490261421
Short name T372
Test name
Test status
Simulation time 165602854 ps
CPU time 0.84 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:35 PM PDT 24
Peak memory 205168 kb
Host smart-7e2ac4aa-49ef-4d57-92f0-8e791af0b091
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490261421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.490261421
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2248386730
Short name T98
Test name
Test status
Simulation time 468823528 ps
CPU time 4.15 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:38 PM PDT 24
Peak memory 205524 kb
Host smart-527221d5-b6b7-4712-b204-1eb187db1c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248386730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2248386730
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1813360843
Short name T385
Test name
Test status
Simulation time 19027076892 ps
CPU time 17.94 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:51 PM PDT 24
Peak memory 221724 kb
Host smart-210e28fe-3e93-42a0-addf-793e27d96604
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813360843 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1813360843
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4225222752
Short name T130
Test name
Test status
Simulation time 293675087 ps
CPU time 5.55 seconds
Started Aug 03 04:32:36 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 213784 kb
Host smart-dbec6307-d158-4aa6-8e76-a062f05dcdf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225222752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4225222752
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.47451439
Short name T370
Test name
Test status
Simulation time 2275889404 ps
CPU time 11.08 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 213808 kb
Host smart-eb151cdb-4d7d-41c8-8afa-dc6840e2c709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47451439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.47451439
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1866006323
Short name T374
Test name
Test status
Simulation time 837139937 ps
CPU time 2.29 seconds
Started Aug 03 04:32:38 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 219244 kb
Host smart-d4b707c8-bce9-471d-b9dc-d538983f3ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866006323 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1866006323
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.263316629
Short name T112
Test name
Test status
Simulation time 174199998 ps
CPU time 2.03 seconds
Started Aug 03 04:32:32 PM PDT 24
Finished Aug 03 04:32:34 PM PDT 24
Peak memory 213596 kb
Host smart-8c8ac8c1-5c5f-41ed-bb7a-de28e8e776be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263316629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.263316629
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2631107734
Short name T417
Test name
Test status
Simulation time 26075862689 ps
CPU time 23.75 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:56 PM PDT 24
Peak memory 205488 kb
Host smart-e0e16010-ada2-4305-a8aa-5c0228fd84f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631107734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2631107734
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1367414557
Short name T452
Test name
Test status
Simulation time 2219207470 ps
CPU time 4.57 seconds
Started Aug 03 04:32:37 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 205532 kb
Host smart-13199ab7-b9ec-4427-89a6-c86afa9181ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367414557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
367414557
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3264585231
Short name T455
Test name
Test status
Simulation time 454114931 ps
CPU time 1.26 seconds
Started Aug 03 04:32:35 PM PDT 24
Finished Aug 03 04:32:36 PM PDT 24
Peak memory 205192 kb
Host smart-0315b095-a661-4827-8819-825d0de4fdc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264585231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
264585231
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2539096948
Short name T391
Test name
Test status
Simulation time 181472879 ps
CPU time 6.65 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 205500 kb
Host smart-25da2df7-77d8-4d5e-90ff-cd13eb892dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539096948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2539096948
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2635025473
Short name T166
Test name
Test status
Simulation time 42164277952 ps
CPU time 127.94 seconds
Started Aug 03 04:32:36 PM PDT 24
Finished Aug 03 04:34:44 PM PDT 24
Peak memory 223280 kb
Host smart-0ed62e19-815a-4845-bf6d-da14664d44d1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635025473 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2635025473
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2076967820
Short name T129
Test name
Test status
Simulation time 352638431 ps
CPU time 4.74 seconds
Started Aug 03 04:32:35 PM PDT 24
Finished Aug 03 04:32:40 PM PDT 24
Peak memory 213764 kb
Host smart-243ef02e-7371-4f80-afcc-139b4b70569d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076967820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2076967820
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2293158995
Short name T404
Test name
Test status
Simulation time 732813691 ps
CPU time 9.47 seconds
Started Aug 03 04:32:38 PM PDT 24
Finished Aug 03 04:32:48 PM PDT 24
Peak memory 213752 kb
Host smart-22d5db56-5b05-44ce-b555-f61472371768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293158995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2293158995
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3855532877
Short name T340
Test name
Test status
Simulation time 356553849 ps
CPU time 2.87 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:36 PM PDT 24
Peak memory 219888 kb
Host smart-57975ca4-4bd6-4abc-9775-623776a34d80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855532877 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3855532877
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2834807027
Short name T405
Test name
Test status
Simulation time 232578327 ps
CPU time 1.82 seconds
Started Aug 03 04:32:34 PM PDT 24
Finished Aug 03 04:32:36 PM PDT 24
Peak memory 213716 kb
Host smart-faf0ede0-887d-4561-82ae-52bc81df9d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834807027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2834807027
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2971374588
Short name T439
Test name
Test status
Simulation time 16963898988 ps
CPU time 24.77 seconds
Started Aug 03 04:32:36 PM PDT 24
Finished Aug 03 04:33:01 PM PDT 24
Peak memory 205508 kb
Host smart-786c03f6-d8c5-453a-83ba-1f4719801628
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971374588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2971374588
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.135312606
Short name T418
Test name
Test status
Simulation time 4754577451 ps
CPU time 7.46 seconds
Started Aug 03 04:32:42 PM PDT 24
Finished Aug 03 04:32:49 PM PDT 24
Peak memory 205536 kb
Host smart-83816155-b222-4ad7-b06b-b2f2d8719eb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135312606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.135312606
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3612559267
Short name T322
Test name
Test status
Simulation time 93609411 ps
CPU time 0.82 seconds
Started Aug 03 04:32:33 PM PDT 24
Finished Aug 03 04:32:33 PM PDT 24
Peak memory 205304 kb
Host smart-8999ca35-5a8c-49c9-b9ff-864a7e181364
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612559267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
612559267
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2337986994
Short name T436
Test name
Test status
Simulation time 179376864 ps
CPU time 3.49 seconds
Started Aug 03 04:32:31 PM PDT 24
Finished Aug 03 04:32:35 PM PDT 24
Peak memory 205392 kb
Host smart-b1d10b5a-b6f5-4908-845f-32c327785f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337986994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2337986994
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3599919559
Short name T457
Test name
Test status
Simulation time 240171975 ps
CPU time 5.87 seconds
Started Aug 03 04:32:35 PM PDT 24
Finished Aug 03 04:32:41 PM PDT 24
Peak memory 213800 kb
Host smart-f6429d1c-79eb-45c7-9d42-17e5c8709d36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599919559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3599919559
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1679980855
Short name T368
Test name
Test status
Simulation time 5985154463 ps
CPU time 29.99 seconds
Started Aug 03 04:32:37 PM PDT 24
Finished Aug 03 04:33:07 PM PDT 24
Peak memory 213868 kb
Host smart-5e546067-e37b-403f-bbf2-c0ce2ce1ed0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679980855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1679980855
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2896527891
Short name T186
Test name
Test status
Simulation time 196221450 ps
CPU time 0.79 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:46 PM PDT 24
Peak memory 205264 kb
Host smart-463420b8-8327-48f3-af21-6c494bc7ed07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896527891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2896527891
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1661112871
Short name T77
Test name
Test status
Simulation time 3441889496 ps
CPU time 5.24 seconds
Started Aug 03 04:34:35 PM PDT 24
Finished Aug 03 04:34:41 PM PDT 24
Peak memory 213988 kb
Host smart-a009cc2d-7006-40d4-888a-cb1fae24a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661112871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1661112871
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1609243097
Short name T21
Test name
Test status
Simulation time 641886365 ps
CPU time 1.11 seconds
Started Aug 03 04:34:35 PM PDT 24
Finished Aug 03 04:34:36 PM PDT 24
Peak memory 205180 kb
Host smart-b9359d00-93ae-4e12-b649-83ea20aaaeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609243097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1609243097
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1547749835
Short name T241
Test name
Test status
Simulation time 921064786 ps
CPU time 0.99 seconds
Started Aug 03 04:34:38 PM PDT 24
Finished Aug 03 04:34:39 PM PDT 24
Peak memory 205268 kb
Host smart-d820c3f3-a2b8-4297-8dc9-4300d760e803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547749835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1547749835
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.4087323601
Short name T81
Test name
Test status
Simulation time 158825992 ps
CPU time 0.78 seconds
Started Aug 03 04:34:32 PM PDT 24
Finished Aug 03 04:34:34 PM PDT 24
Peak memory 205232 kb
Host smart-13d3803e-bd26-4087-ae2d-763b0ecd705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087323601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.4087323601
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2254593854
Short name T255
Test name
Test status
Simulation time 3361505374 ps
CPU time 6.04 seconds
Started Aug 03 04:34:38 PM PDT 24
Finished Aug 03 04:34:44 PM PDT 24
Peak memory 213912 kb
Host smart-eba5a657-0891-4205-a24c-0e21c6124c8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254593854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2254593854
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.364330328
Short name T198
Test name
Test status
Simulation time 1282353298 ps
CPU time 1.48 seconds
Started Aug 03 04:34:33 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205220 kb
Host smart-af444d1f-7607-4d33-a18e-1b17402899ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364330328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.364330328
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1313439044
Short name T253
Test name
Test status
Simulation time 513668596 ps
CPU time 1.08 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205172 kb
Host smart-73b9c87e-a814-41f7-809f-0540a9f2de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313439044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1313439044
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3310127971
Short name T227
Test name
Test status
Simulation time 136254328 ps
CPU time 0.78 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205284 kb
Host smart-b8854120-5b4c-4398-aa1f-bc103a04071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310127971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3310127971
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.336717492
Short name T84
Test name
Test status
Simulation time 374123730 ps
CPU time 0.9 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205064 kb
Host smart-94e4dc96-c069-46bd-9453-4771e291f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336717492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.336717492
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3963983207
Short name T208
Test name
Test status
Simulation time 216683596 ps
CPU time 0.92 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205180 kb
Host smart-9c5a81ed-ba73-4650-a5d4-6b3091289c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963983207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3963983207
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.753486452
Short name T249
Test name
Test status
Simulation time 183860202 ps
CPU time 1.11 seconds
Started Aug 03 04:34:32 PM PDT 24
Finished Aug 03 04:34:33 PM PDT 24
Peak memory 205196 kb
Host smart-43f60d90-720f-47c8-9310-2b28ff165932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753486452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.753486452
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1906365285
Short name T308
Test name
Test status
Simulation time 531148737 ps
CPU time 0.93 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 205252 kb
Host smart-ed56078a-70fd-4c13-8df6-6f6ae7af079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906365285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1906365285
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3507476550
Short name T291
Test name
Test status
Simulation time 2903311100 ps
CPU time 7.46 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:41 PM PDT 24
Peak memory 205316 kb
Host smart-796b0dc5-cde8-4e6d-a214-6f827c74f4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507476550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3507476550
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3709549467
Short name T89
Test name
Test status
Simulation time 237024295 ps
CPU time 0.93 seconds
Started Aug 03 04:34:38 PM PDT 24
Finished Aug 03 04:34:39 PM PDT 24
Peak memory 213352 kb
Host smart-eccf14d6-6693-4223-ac2d-2046accfd044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709549467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3709549467
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.605713375
Short name T238
Test name
Test status
Simulation time 313487968 ps
CPU time 1.01 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:51 PM PDT 24
Peak memory 205188 kb
Host smart-70ef22a1-d4c5-4283-916d-3e1efb738953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605713375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.605713375
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1277971016
Short name T24
Test name
Test status
Simulation time 2287195994 ps
CPU time 2.68 seconds
Started Aug 03 04:34:33 PM PDT 24
Finished Aug 03 04:34:36 PM PDT 24
Peak memory 205528 kb
Host smart-6dcf16d0-1369-4163-b2be-9d1e829414b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277971016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1277971016
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1343027006
Short name T231
Test name
Test status
Simulation time 5321293852 ps
CPU time 12.33 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:47 PM PDT 24
Peak memory 213876 kb
Host smart-c1b1681a-82c6-4179-8344-1f4d4e411506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343027006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1343027006
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.4068304093
Short name T151
Test name
Test status
Simulation time 934052845 ps
CPU time 3.58 seconds
Started Aug 03 04:34:34 PM PDT 24
Finished Aug 03 04:34:37 PM PDT 24
Peak memory 205416 kb
Host smart-7781c0a3-598a-4bd4-818a-ba09b7173aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068304093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4068304093
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.845244174
Short name T143
Test name
Test status
Simulation time 1163634530 ps
CPU time 1.6 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 205396 kb
Host smart-4b262cb0-119c-483a-919c-d5bfdbd70ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845244174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.845244174
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2878940928
Short name T46
Test name
Test status
Simulation time 459375999 ps
CPU time 2 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205140 kb
Host smart-4826d31e-442d-46ab-b8e5-fc0d22f4bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878940928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2878940928
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4071688747
Short name T268
Test name
Test status
Simulation time 126847802 ps
CPU time 0.99 seconds
Started Aug 03 04:34:44 PM PDT 24
Finished Aug 03 04:34:45 PM PDT 24
Peak memory 205304 kb
Host smart-457baa91-f144-4cab-915c-18b76b24fdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071688747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4071688747
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1115362911
Short name T202
Test name
Test status
Simulation time 299800915 ps
CPU time 0.93 seconds
Started Aug 03 04:34:48 PM PDT 24
Finished Aug 03 04:34:49 PM PDT 24
Peak memory 205188 kb
Host smart-46299a06-116a-4c0d-aab4-ba7e0a31f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115362911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1115362911
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2080175294
Short name T16
Test name
Test status
Simulation time 268368245 ps
CPU time 0.95 seconds
Started Aug 03 04:34:44 PM PDT 24
Finished Aug 03 04:34:45 PM PDT 24
Peak memory 205256 kb
Host smart-732a73d4-b0e6-439d-9294-4601f3aa1113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080175294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2080175294
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3650499366
Short name T35
Test name
Test status
Simulation time 1372558891 ps
CPU time 2.3 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:47 PM PDT 24
Peak memory 205264 kb
Host smart-73103a18-4a1b-4fb1-a34d-8a7736028e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650499366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3650499366
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1668879875
Short name T32
Test name
Test status
Simulation time 231336694 ps
CPU time 0.81 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:45 PM PDT 24
Peak memory 205244 kb
Host smart-7c5d88a5-878e-4d43-b347-162f01cb16bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668879875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1668879875
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3567836753
Short name T127
Test name
Test status
Simulation time 83007630 ps
CPU time 0.79 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:01 PM PDT 24
Peak memory 205232 kb
Host smart-3555ee93-0307-46b3-8771-db5973545d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567836753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3567836753
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2838620501
Short name T283
Test name
Test status
Simulation time 71166827 ps
CPU time 0.97 seconds
Started Aug 03 04:34:42 PM PDT 24
Finished Aug 03 04:34:43 PM PDT 24
Peak memory 215404 kb
Host smart-f69fcbc0-3812-42a5-829d-0a28700a9b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838620501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2838620501
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2833308744
Short name T207
Test name
Test status
Simulation time 1490426498 ps
CPU time 1.53 seconds
Started Aug 03 04:34:42 PM PDT 24
Finished Aug 03 04:34:44 PM PDT 24
Peak memory 205620 kb
Host smart-14f6b924-10a6-41b0-b6c5-58ba132edf93
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833308744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2833308744
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2309950271
Short name T54
Test name
Test status
Simulation time 198340106 ps
CPU time 0.93 seconds
Started Aug 03 04:34:51 PM PDT 24
Finished Aug 03 04:34:52 PM PDT 24
Peak memory 205276 kb
Host smart-012752db-df46-4b16-bf58-5e3e0c2f333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309950271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2309950271
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4253719285
Short name T41
Test name
Test status
Simulation time 1388889582 ps
CPU time 2 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:47 PM PDT 24
Peak memory 205128 kb
Host smart-01c5b0f3-08a4-474c-9ae8-58e1e7b91556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253719285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4253719285
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2108550963
Short name T254
Test name
Test status
Simulation time 226401837 ps
CPU time 1.29 seconds
Started Aug 03 04:34:40 PM PDT 24
Finished Aug 03 04:34:41 PM PDT 24
Peak memory 205248 kb
Host smart-ad1e97af-5eea-47a6-8d6d-0554eaa0108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108550963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2108550963
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3935639982
Short name T237
Test name
Test status
Simulation time 384026280 ps
CPU time 1.02 seconds
Started Aug 03 04:34:54 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205180 kb
Host smart-f0eee007-9f12-4366-ab8f-d50cb39949fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935639982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3935639982
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1362162267
Short name T246
Test name
Test status
Simulation time 315324098 ps
CPU time 1.54 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:51 PM PDT 24
Peak memory 205044 kb
Host smart-33523b10-7936-439a-9638-99a74b7a79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362162267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1362162267
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1310476504
Short name T262
Test name
Test status
Simulation time 316627657 ps
CPU time 1.47 seconds
Started Aug 03 04:34:44 PM PDT 24
Finished Aug 03 04:34:45 PM PDT 24
Peak memory 205296 kb
Host smart-b2978c48-5472-4f17-aef7-e42176655485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310476504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1310476504
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1519029184
Short name T233
Test name
Test status
Simulation time 374690908 ps
CPU time 1.24 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:34:44 PM PDT 24
Peak memory 205280 kb
Host smart-4a869212-cc35-466c-be44-466b9bd9d740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519029184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1519029184
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2920113570
Short name T204
Test name
Test status
Simulation time 96151605 ps
CPU time 0.78 seconds
Started Aug 03 04:34:46 PM PDT 24
Finished Aug 03 04:34:46 PM PDT 24
Peak memory 205156 kb
Host smart-d1c083ae-b896-42ad-835d-849ca861acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920113570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2920113570
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.519275093
Short name T278
Test name
Test status
Simulation time 2495857359 ps
CPU time 3.99 seconds
Started Aug 03 04:34:46 PM PDT 24
Finished Aug 03 04:34:50 PM PDT 24
Peak memory 205244 kb
Host smart-2251db3b-6a2d-447c-a05e-9a3640b1f847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519275093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.519275093
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2051954752
Short name T307
Test name
Test status
Simulation time 355911210 ps
CPU time 1.72 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:34:53 PM PDT 24
Peak memory 213384 kb
Host smart-d635abe2-1986-4082-8068-608a6ef64002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051954752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2051954752
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4128418320
Short name T232
Test name
Test status
Simulation time 525840637 ps
CPU time 1.1 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:50 PM PDT 24
Peak memory 205136 kb
Host smart-76f8b7f7-8622-4e91-a9e5-f5e4e38a1a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128418320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4128418320
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.4117856291
Short name T38
Test name
Test status
Simulation time 74801876 ps
CPU time 0.79 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:51 PM PDT 24
Peak memory 213396 kb
Host smart-5c2bc70e-0b2d-4bfc-b71f-ab5a87609aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117856291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.4117856291
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.4060833962
Short name T73
Test name
Test status
Simulation time 5053801072 ps
CPU time 6.88 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:56 PM PDT 24
Peak memory 213800 kb
Host smart-d4b53575-90c0-4c2f-be10-5e874cb78e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060833962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4060833962
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3519190185
Short name T49
Test name
Test status
Simulation time 1073742587 ps
CPU time 1.36 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:50 PM PDT 24
Peak memory 229868 kb
Host smart-3204576b-49f0-4756-b733-f7654338ead2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519190185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3519190185
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.202339197
Short name T297
Test name
Test status
Simulation time 548523224 ps
CPU time 1.12 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:34:48 PM PDT 24
Peak memory 205136 kb
Host smart-dfabe49f-10e9-4a89-98b4-a976298be70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202339197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.202339197
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3209338553
Short name T266
Test name
Test status
Simulation time 36014638 ps
CPU time 0.7 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:34:54 PM PDT 24
Peak memory 205256 kb
Host smart-4aa81d66-d0ed-4f97-a19e-5e41e9a9ceaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209338553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3209338553
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2373675603
Short name T70
Test name
Test status
Simulation time 2091805281 ps
CPU time 2.64 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:07 PM PDT 24
Peak memory 214792 kb
Host smart-76a3ee0f-7552-496d-8ab5-430f9a2bd0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373675603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2373675603
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1723017950
Short name T224
Test name
Test status
Simulation time 5260965917 ps
CPU time 5.35 seconds
Started Aug 03 04:34:57 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 215392 kb
Host smart-77123757-544c-4889-afb7-f60fb617079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723017950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1723017950
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.4025936052
Short name T305
Test name
Test status
Simulation time 12172309044 ps
CPU time 10.43 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 213816 kb
Host smart-dbd8dbc0-66e3-49c1-bdd1-379463bd565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025936052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4025936052
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3941089038
Short name T277
Test name
Test status
Simulation time 3635716395 ps
CPU time 9.43 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:18 PM PDT 24
Peak memory 205600 kb
Host smart-14b9db17-d962-4765-981b-12c402b12540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941089038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3941089038
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.37775639
Short name T184
Test name
Test status
Simulation time 75178365 ps
CPU time 0.76 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 205164 kb
Host smart-c590b9aa-6505-490c-94a9-48dad7535f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37775639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.37775639
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.837670744
Short name T196
Test name
Test status
Simulation time 18157928514 ps
CPU time 49.08 seconds
Started Aug 03 04:35:01 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 213804 kb
Host smart-a700d8f5-baa2-4374-9cc5-fdd0abe81840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837670744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.837670744
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1631989224
Short name T181
Test name
Test status
Simulation time 4448129954 ps
CPU time 7.04 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 213812 kb
Host smart-9f875dad-c40c-41d4-9965-a3071f71e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631989224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1631989224
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3671091471
Short name T267
Test name
Test status
Simulation time 2918219496 ps
CPU time 3.88 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:34:57 PM PDT 24
Peak memory 213788 kb
Host smart-32428741-afac-4fd2-8ea4-9d4e21d7d943
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671091471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3671091471
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.726657518
Short name T288
Test name
Test status
Simulation time 6309398419 ps
CPU time 7.23 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 213920 kb
Host smart-92463646-4afb-4d80-b739-636d45eacc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726657518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.726657518
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2801654543
Short name T220
Test name
Test status
Simulation time 3566544643 ps
CPU time 1.87 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 205452 kb
Host smart-4e51a60d-602b-4498-a68e-f6247bdd16e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801654543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2801654543
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1257919535
Short name T177
Test name
Test status
Simulation time 39901219 ps
CPU time 0.81 seconds
Started Aug 03 04:35:10 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 205428 kb
Host smart-4e22e8a9-54ec-4698-aca1-ea0c73fc9067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257919535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1257919535
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2307868104
Short name T29
Test name
Test status
Simulation time 1333819951 ps
CPU time 1.66 seconds
Started Aug 03 04:35:02 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 213632 kb
Host smart-67987380-95e0-41e3-8c9c-4c2d82777981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307868104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2307868104
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.230717624
Short name T261
Test name
Test status
Simulation time 1470825304 ps
CPU time 4.4 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 205500 kb
Host smart-787526cf-6572-4f88-ae98-c2996072c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230717624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.230717624
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.182440183
Short name T235
Test name
Test status
Simulation time 3736920941 ps
CPU time 7.23 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:07 PM PDT 24
Peak memory 213868 kb
Host smart-0feec935-6e6f-4485-b06e-50951178cad9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182440183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.182440183
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3134469259
Short name T218
Test name
Test status
Simulation time 4452426884 ps
CPU time 4.86 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 213844 kb
Host smart-4ff1e5b1-96ab-4527-9a79-15e0f97e1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134469259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3134469259
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.190153382
Short name T17
Test name
Test status
Simulation time 2030194800 ps
CPU time 5.74 seconds
Started Aug 03 04:34:57 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 205428 kb
Host smart-af8f432b-e738-4bec-99a1-d28894a0ca24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190153382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.190153382
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3989682010
Short name T244
Test name
Test status
Simulation time 70694449 ps
CPU time 0.82 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:34:56 PM PDT 24
Peak memory 205304 kb
Host smart-b0626eb4-e7a9-4b42-8b99-7380febb011e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989682010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3989682010
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2222729013
Short name T148
Test name
Test status
Simulation time 10230456002 ps
CPU time 17.42 seconds
Started Aug 03 04:34:56 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213888 kb
Host smart-a1bfd568-f4cc-4faf-8eb3-15757eb84e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222729013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2222729013
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.4125536799
Short name T199
Test name
Test status
Simulation time 4474056460 ps
CPU time 4.44 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 205720 kb
Host smart-77036b25-b38a-4623-bec3-ed53870345b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125536799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.4125536799
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.150273275
Short name T71
Test name
Test status
Simulation time 2140253290 ps
CPU time 2.28 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 213696 kb
Host smart-908302a5-82a1-4f87-b761-57ff2b35d74b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150273275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.150273275
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.412147350
Short name T303
Test name
Test status
Simulation time 6617776022 ps
CPU time 3.75 seconds
Started Aug 03 04:34:56 PM PDT 24
Finished Aug 03 04:35:00 PM PDT 24
Peak memory 213984 kb
Host smart-276494ca-b9c1-425c-a463-16a5d1c22387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412147350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.412147350
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.617809054
Short name T263
Test name
Test status
Simulation time 155815323 ps
CPU time 0.72 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:01 PM PDT 24
Peak memory 205200 kb
Host smart-3cdd5072-95df-49df-aa73-750457da3e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617809054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.617809054
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.167469811
Short name T230
Test name
Test status
Simulation time 29111701398 ps
CPU time 20.86 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 213920 kb
Host smart-c8ee369d-1cd0-40ba-83d4-295f3125c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167469811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.167469811
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2587595374
Short name T260
Test name
Test status
Simulation time 1115263893 ps
CPU time 2.53 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 213720 kb
Host smart-b5632aca-99cb-47e2-a586-e9cde6565bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587595374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2587595374
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1738817862
Short name T141
Test name
Test status
Simulation time 12476307773 ps
CPU time 19.11 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:18 PM PDT 24
Peak memory 213804 kb
Host smart-68ee81a9-0690-4b75-86d0-513873aed01d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738817862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1738817862
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3399119229
Short name T287
Test name
Test status
Simulation time 5977399459 ps
CPU time 9.91 seconds
Started Aug 03 04:34:56 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 205636 kb
Host smart-80a53c36-227a-42cc-b365-25304d4ba2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399119229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3399119229
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3082499786
Short name T137
Test name
Test status
Simulation time 6896072855 ps
CPU time 4.69 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 213748 kb
Host smart-4b72de3e-a9b7-4cb5-bf02-4bfabd661636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082499786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3082499786
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3298140210
Short name T65
Test name
Test status
Simulation time 45976435 ps
CPU time 0.74 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 205168 kb
Host smart-7adba878-ee1e-4483-940c-3893fb686988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298140210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3298140210
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3504574212
Short name T271
Test name
Test status
Simulation time 7955370115 ps
CPU time 8.44 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 205668 kb
Host smart-4c96b9bb-750b-4735-986d-601307136578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504574212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3504574212
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.4023830678
Short name T295
Test name
Test status
Simulation time 6448795175 ps
CPU time 4.87 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 205584 kb
Host smart-72c08541-9a5b-4eca-b10a-15c15ce74f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023830678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4023830678
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3334311219
Short name T34
Test name
Test status
Simulation time 959224773 ps
CPU time 2.35 seconds
Started Aug 03 04:34:57 PM PDT 24
Finished Aug 03 04:34:59 PM PDT 24
Peak memory 205592 kb
Host smart-a7114a3a-c127-4b8b-a797-9841c08a4b3a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334311219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3334311219
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.4106425776
Short name T206
Test name
Test status
Simulation time 2451056136 ps
CPU time 3.34 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 205596 kb
Host smart-5626a959-aebd-4699-a80f-138af58a9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106425776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4106425776
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3705357825
Short name T75
Test name
Test status
Simulation time 8001343320 ps
CPU time 24.28 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 213652 kb
Host smart-94c0d6e7-d452-493a-9246-727031e48a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705357825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3705357825
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1747499720
Short name T286
Test name
Test status
Simulation time 96658034 ps
CPU time 0.69 seconds
Started Aug 03 04:34:57 PM PDT 24
Finished Aug 03 04:34:57 PM PDT 24
Peak memory 205280 kb
Host smart-773a1242-6fb5-4739-87f4-edff4ed3e57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747499720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1747499720
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2427967033
Short name T222
Test name
Test status
Simulation time 5222743358 ps
CPU time 12.76 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213856 kb
Host smart-53803392-fe6c-43fc-a849-4ba6109ddbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427967033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2427967033
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2934092570
Short name T285
Test name
Test status
Simulation time 10559477705 ps
CPU time 17.33 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 213780 kb
Host smart-62038456-bf11-4f18-9edf-00eba1689820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934092570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2934092570
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.673170203
Short name T179
Test name
Test status
Simulation time 8492250541 ps
CPU time 8.09 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213980 kb
Host smart-6276b08f-ff10-439f-bc7f-89a328371cf6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673170203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.673170203
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2695460039
Short name T101
Test name
Test status
Simulation time 4824148121 ps
CPU time 4.85 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213900 kb
Host smart-fa066854-f276-4523-9471-78a46f5ac78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695460039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2695460039
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4166556285
Short name T279
Test name
Test status
Simulation time 62131025 ps
CPU time 0.74 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:00 PM PDT 24
Peak memory 205284 kb
Host smart-92952026-d16f-49aa-9adb-c80e6daf5702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166556285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4166556285
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2667713481
Short name T133
Test name
Test status
Simulation time 15809483334 ps
CPU time 31.62 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:36 PM PDT 24
Peak memory 213444 kb
Host smart-6c64147a-33d2-40e6-a5f9-39b4f4b801cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667713481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2667713481
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.820001564
Short name T136
Test name
Test status
Simulation time 1080876317 ps
CPU time 2.38 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 205556 kb
Host smart-e89d04de-92fc-4675-9027-dadc4569636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820001564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.820001564
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4005665124
Short name T83
Test name
Test status
Simulation time 7438293900 ps
CPU time 11.52 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 205684 kb
Host smart-4bf595e5-f0f9-49d1-a45f-5cbd09024d46
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005665124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.4005665124
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1935859484
Short name T187
Test name
Test status
Simulation time 2451356115 ps
CPU time 4.98 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 205680 kb
Host smart-9142c836-a578-4dc5-9bc9-ba6629d8fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935859484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1935859484
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1676734029
Short name T242
Test name
Test status
Simulation time 5791640864 ps
CPU time 4.92 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 205656 kb
Host smart-c70fbea1-adad-4f96-a5c2-51c7fd8f8733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676734029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1676734029
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.15748408
Short name T301
Test name
Test status
Simulation time 67997052 ps
CPU time 0.81 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 205172 kb
Host smart-d7f5daa8-c12c-40ca-a3c4-8c810e13ed05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.15748408
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1752886911
Short name T214
Test name
Test status
Simulation time 3772445335 ps
CPU time 7.6 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 213784 kb
Host smart-33c24057-abcf-4087-8362-6c78a314b303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752886911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1752886911
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2752784640
Short name T213
Test name
Test status
Simulation time 909234400 ps
CPU time 1.52 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 205660 kb
Host smart-eda77a50-f8c4-4de9-adf8-b2f41fd68f18
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752784640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2752784640
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3172548608
Short name T58
Test name
Test status
Simulation time 9632882300 ps
CPU time 25.54 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 205564 kb
Host smart-c9307819-fa1c-4fac-989c-561026b56c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172548608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3172548608
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.924610308
Short name T174
Test name
Test status
Simulation time 69241455 ps
CPU time 0.81 seconds
Started Aug 03 04:35:11 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 205240 kb
Host smart-1fd408ed-139e-4cbc-9940-95bbc1ec0dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924610308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.924610308
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1051270403
Short name T270
Test name
Test status
Simulation time 3238469489 ps
CPU time 4.57 seconds
Started Aug 03 04:35:06 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 221904 kb
Host smart-86b0b6e6-3cf1-4ab4-8ca4-779a9494895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051270403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1051270403
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3508718566
Short name T149
Test name
Test status
Simulation time 1887953259 ps
CPU time 4.2 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:35:00 PM PDT 24
Peak memory 213720 kb
Host smart-80768075-cf63-45f0-8476-cfc0710c8394
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508718566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3508718566
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.4033864597
Short name T175
Test name
Test status
Simulation time 3789146957 ps
CPU time 6.5 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 214008 kb
Host smart-d5f3cc99-73a3-4f46-ac27-973cce5f0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033864597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4033864597
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4241787723
Short name T226
Test name
Test status
Simulation time 4527025918 ps
CPU time 11.61 seconds
Started Aug 03 04:34:56 PM PDT 24
Finished Aug 03 04:35:07 PM PDT 24
Peak memory 213756 kb
Host smart-93f03252-4730-46d4-b496-b4a2347c7685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241787723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4241787723
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3422010221
Short name T292
Test name
Test status
Simulation time 44296095 ps
CPU time 0.77 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:46 PM PDT 24
Peak memory 205252 kb
Host smart-219c9c12-9f9d-4f8d-a8e9-688d9adf36f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422010221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3422010221
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3885929473
Short name T274
Test name
Test status
Simulation time 4709834376 ps
CPU time 2.93 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 213976 kb
Host smart-06f3cfde-f76c-4e3f-b9d3-7463fb95f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885929473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3885929473
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2102291180
Short name T205
Test name
Test status
Simulation time 4799968417 ps
CPU time 7.14 seconds
Started Aug 03 04:34:57 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 205576 kb
Host smart-94fa565a-b375-40f6-b87c-668bac0ff9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102291180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2102291180
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1093062761
Short name T190
Test name
Test status
Simulation time 2740985095 ps
CPU time 8.96 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:54 PM PDT 24
Peak memory 205788 kb
Host smart-00c86d42-57b5-4cc7-a5d0-1de8245d3b46
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093062761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1093062761
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.2086017791
Short name T284
Test name
Test status
Simulation time 393868440 ps
CPU time 1.38 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:46 PM PDT 24
Peak memory 205128 kb
Host smart-1132f3c6-8ed1-430f-9277-4ffaa4b41f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086017791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2086017791
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3584700157
Short name T221
Test name
Test status
Simulation time 165898406 ps
CPU time 0.98 seconds
Started Aug 03 04:34:44 PM PDT 24
Finished Aug 03 04:34:45 PM PDT 24
Peak memory 205156 kb
Host smart-913e592f-04ec-468a-aaea-6de34b2c1866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584700157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3584700157
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3588085073
Short name T67
Test name
Test status
Simulation time 11286678865 ps
CPU time 15.94 seconds
Started Aug 03 04:34:54 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 213936 kb
Host smart-c76122cc-3fb0-469f-9af4-653a5fbd7700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588085073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3588085073
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.616309940
Short name T69
Test name
Test status
Simulation time 1104131698 ps
CPU time 2.48 seconds
Started Aug 03 04:34:46 PM PDT 24
Finished Aug 03 04:34:49 PM PDT 24
Peak memory 229448 kb
Host smart-c37af3d3-5554-4d36-a05d-896281c7e4aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616309940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.616309940
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2183680427
Short name T228
Test name
Test status
Simulation time 2870987273 ps
CPU time 8.34 seconds
Started Aug 03 04:34:43 PM PDT 24
Finished Aug 03 04:34:51 PM PDT 24
Peak memory 213788 kb
Host smart-99c1033f-fedf-4986-aaf2-a60c1ebc357c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183680427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2183680427
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2016418331
Short name T192
Test name
Test status
Simulation time 71936007 ps
CPU time 0.7 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:05 PM PDT 24
Peak memory 204776 kb
Host smart-218c1410-6d6b-46bc-8061-836ba8ac003e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016418331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2016418331
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.465878024
Short name T145
Test name
Test status
Simulation time 3714075838 ps
CPU time 7.98 seconds
Started Aug 03 04:34:58 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 213892 kb
Host smart-657fd6a3-ab9d-4f22-9151-684be0d677e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465878024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.465878024
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1274967018
Short name T302
Test name
Test status
Simulation time 124538293 ps
CPU time 0.71 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:34:56 PM PDT 24
Peak memory 205248 kb
Host smart-1d73d125-0ea9-4ff8-a27e-b6a01fa9d23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274967018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1274967018
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.702357838
Short name T150
Test name
Test status
Simulation time 3848116459 ps
CPU time 10.82 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 213668 kb
Host smart-2ca7d7a4-1d4e-4cc4-ae27-2adc64cdc154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702357838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.702357838
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3403139534
Short name T289
Test name
Test status
Simulation time 40978667 ps
CPU time 0.77 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 205152 kb
Host smart-eaf575f5-f8a8-4b4f-92bc-ae7248103ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403139534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3403139534
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3253568909
Short name T169
Test name
Test status
Simulation time 2397945115 ps
CPU time 2.62 seconds
Started Aug 03 04:35:02 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 205552 kb
Host smart-7bce4733-2bb7-49bd-8d60-63cdf2adc3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253568909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3253568909
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3670694899
Short name T193
Test name
Test status
Simulation time 65479013 ps
CPU time 0.79 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 205156 kb
Host smart-e96af2fd-8137-45dc-b0da-4aef027d7e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670694899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3670694899
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.3760090256
Short name T26
Test name
Test status
Simulation time 15813886092 ps
CPU time 49.51 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 213804 kb
Host smart-53a8fdef-76cd-47cb-9b88-abb990ed44d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760090256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3760090256
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2437506013
Short name T191
Test name
Test status
Simulation time 164339843 ps
CPU time 0.73 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:01 PM PDT 24
Peak memory 205196 kb
Host smart-08f1de85-38e8-4307-b9c9-a7d2dfe32f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437506013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2437506013
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.422865238
Short name T144
Test name
Test status
Simulation time 4484388289 ps
CPU time 3.98 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 205440 kb
Host smart-ab5b66bc-b2ab-4c22-a528-9003b2dceb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422865238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.422865238
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1798166431
Short name T197
Test name
Test status
Simulation time 95166062 ps
CPU time 0.9 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 205144 kb
Host smart-c4da31d2-94fe-4de2-9f35-8b9673c8037d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798166431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1798166431
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.409284816
Short name T243
Test name
Test status
Simulation time 3903859993 ps
CPU time 4.45 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 205460 kb
Host smart-475365e9-439a-44b8-ab8b-387a76eaf9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409284816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.409284816
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2177399750
Short name T223
Test name
Test status
Simulation time 43110546 ps
CPU time 0.75 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 205248 kb
Host smart-caba0312-bf6c-400e-a53a-b112bcc9c15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177399750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2177399750
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.125141772
Short name T153
Test name
Test status
Simulation time 10091742796 ps
CPU time 26.37 seconds
Started Aug 03 04:35:01 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 213764 kb
Host smart-19a0d898-da28-4544-8989-3a110c72b49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125141772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.125141772
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.4146555493
Short name T293
Test name
Test status
Simulation time 50414269 ps
CPU time 0.75 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 205080 kb
Host smart-102d6e3d-f5fa-448d-ad8b-1ecccef934d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146555493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4146555493
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1261150083
Short name T40
Test name
Test status
Simulation time 7965899205 ps
CPU time 14.69 seconds
Started Aug 03 04:35:12 PM PDT 24
Finished Aug 03 04:35:27 PM PDT 24
Peak memory 213728 kb
Host smart-4c61fec3-31dc-47b7-bd8d-a8ae4fa4e8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261150083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1261150083
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2283870219
Short name T257
Test name
Test status
Simulation time 8831639509 ps
CPU time 9.56 seconds
Started Aug 03 04:35:04 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213764 kb
Host smart-70552a1e-a18b-4329-8fe0-b5611cb6ed6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283870219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2283870219
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3416114698
Short name T294
Test name
Test status
Simulation time 60921016 ps
CPU time 0.84 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 205088 kb
Host smart-4a8228b9-feed-4863-bacc-3d5aa9750b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416114698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3416114698
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2823778054
Short name T282
Test name
Test status
Simulation time 3356170162 ps
CPU time 10.16 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213688 kb
Host smart-7afeca7e-1d2b-49d1-901c-c617b796b2ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823778054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2823778054
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1759430345
Short name T203
Test name
Test status
Simulation time 29842604 ps
CPU time 0.71 seconds
Started Aug 03 04:35:01 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 205168 kb
Host smart-c8c78ac7-bac6-49bd-8a60-49832065f43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759430345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1759430345
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3142165106
Short name T209
Test name
Test status
Simulation time 131058341019 ps
CPU time 314.1 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:40:04 PM PDT 24
Peak memory 218492 kb
Host smart-79098f1c-386e-4f4d-9b49-f63f86c8a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142165106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3142165106
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3453892074
Short name T251
Test name
Test status
Simulation time 1079397409 ps
CPU time 1.75 seconds
Started Aug 03 04:34:54 PM PDT 24
Finished Aug 03 04:34:56 PM PDT 24
Peak memory 205504 kb
Host smart-8cc185d2-6e20-4094-894a-e0bbd00e4e98
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453892074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3453892074
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.1565391675
Short name T39
Test name
Test status
Simulation time 416086090 ps
CPU time 1.51 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:34:54 PM PDT 24
Peak memory 205108 kb
Host smart-d8e838d3-19e7-43d3-b1f4-f3125d43e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565391675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1565391675
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3605799269
Short name T72
Test name
Test status
Simulation time 370575182 ps
CPU time 1.03 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:34:48 PM PDT 24
Peak memory 205240 kb
Host smart-31b93a85-de77-4a40-a3cb-f2fbf3a863ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605799269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3605799269
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1927777545
Short name T239
Test name
Test status
Simulation time 11436628803 ps
CPU time 10.31 seconds
Started Aug 03 04:34:44 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 222036 kb
Host smart-ab039c06-57a2-4062-a043-621101875184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927777545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1927777545
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2697250013
Short name T50
Test name
Test status
Simulation time 1160609811 ps
CPU time 1.54 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:34:54 PM PDT 24
Peak memory 229332 kb
Host smart-0c5d99c7-5b86-4c65-80eb-f12dccbd378f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697250013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2697250013
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2595725026
Short name T6
Test name
Test status
Simulation time 5979457952 ps
CPU time 5.2 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 213756 kb
Host smart-2a409dd2-0da5-46de-a83f-aa4052c62dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595725026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2595725026
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.1961407387
Short name T56
Test name
Test status
Simulation time 100485379266 ps
CPU time 731.4 seconds
Started Aug 03 04:34:48 PM PDT 24
Finished Aug 03 04:47:00 PM PDT 24
Peak memory 234560 kb
Host smart-8cffeff5-a6c8-4a5d-9e31-a7374f68189b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961407387 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.1961407387
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1348865024
Short name T201
Test name
Test status
Simulation time 108128842 ps
CPU time 0.72 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 205156 kb
Host smart-ac397072-ff37-47ad-bec3-721984598807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348865024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1348865024
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.911106513
Short name T20
Test name
Test status
Simulation time 3388145984 ps
CPU time 5.97 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 213628 kb
Host smart-90247fb0-72dd-4c02-b5ec-d851df34d70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911106513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.911106513
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1122238751
Short name T240
Test name
Test status
Simulation time 79152486 ps
CPU time 0.68 seconds
Started Aug 03 04:35:07 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 205252 kb
Host smart-a5927878-6a83-40a0-89b8-cf4336a4bfcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122238751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1122238751
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2674243309
Short name T135
Test name
Test status
Simulation time 4767404363 ps
CPU time 4.3 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:07 PM PDT 24
Peak memory 213768 kb
Host smart-582e9733-dc6d-4901-97f5-f1f0593914f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674243309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2674243309
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2600911663
Short name T180
Test name
Test status
Simulation time 109066041 ps
CPU time 0.81 seconds
Started Aug 03 04:35:07 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 205268 kb
Host smart-5859566e-db98-4322-82fb-a1d1e4c313ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600911663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2600911663
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1977965647
Short name T28
Test name
Test status
Simulation time 2922989668 ps
CPU time 8.95 seconds
Started Aug 03 04:35:10 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 213652 kb
Host smart-6d82ac79-bd53-4e6d-8f9c-3f46ec2effe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977965647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1977965647
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3446960491
Short name T173
Test name
Test status
Simulation time 37381110 ps
CPU time 0.75 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 205244 kb
Host smart-29400719-0c49-48a7-81f8-f4c916e7c129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446960491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3446960491
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1462131939
Short name T13
Test name
Test status
Simulation time 5336541199 ps
CPU time 5.95 seconds
Started Aug 03 04:35:11 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 213912 kb
Host smart-fe477489-6d99-452c-877f-6b568bc26d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462131939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1462131939
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2285182132
Short name T248
Test name
Test status
Simulation time 83859382 ps
CPU time 0.7 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 205288 kb
Host smart-8e80d6b5-eb91-4926-b44c-3be5ea795827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285182132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2285182132
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1596265064
Short name T234
Test name
Test status
Simulation time 2433849431 ps
CPU time 3.25 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 213716 kb
Host smart-fe6b63f2-ce34-4eed-ad52-ef58fada7969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596265064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1596265064
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3718520439
Short name T185
Test name
Test status
Simulation time 154762373 ps
CPU time 0.78 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 204612 kb
Host smart-cb57121c-6de9-482f-af31-fce3cc1cc3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718520439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3718520439
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.884780652
Short name T22
Test name
Test status
Simulation time 4775103519 ps
CPU time 13.71 seconds
Started Aug 03 04:35:07 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 213816 kb
Host smart-bfa65a71-67ce-494f-8509-f362e59bbd4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884780652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.884780652
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.581714814
Short name T47
Test name
Test status
Simulation time 80417339 ps
CPU time 0.77 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 205152 kb
Host smart-26ebea76-91a8-4cbc-ba0d-49ff587d5482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581714814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.581714814
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.4238360814
Short name T76
Test name
Test status
Simulation time 6242146375 ps
CPU time 3.45 seconds
Started Aug 03 04:35:11 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 213680 kb
Host smart-ad9169f5-f39b-40c3-b4ca-e7ba28516921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238360814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.4238360814
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2504977222
Short name T265
Test name
Test status
Simulation time 46675603 ps
CPU time 0.72 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 205148 kb
Host smart-494c4d5c-ffe0-4943-8712-27fa2f2a6819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504977222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2504977222
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2430230271
Short name T48
Test name
Test status
Simulation time 94779007 ps
CPU time 0.81 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 205184 kb
Host smart-2fcdf871-6341-46b1-b4ce-05d3175042ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430230271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2430230271
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1401864665
Short name T276
Test name
Test status
Simulation time 3224250048 ps
CPU time 9.48 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 213760 kb
Host smart-f2d847f7-21a0-48cc-a88c-1459b55fd18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401864665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1401864665
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1615347368
Short name T178
Test name
Test status
Simulation time 34641611 ps
CPU time 0.77 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 204740 kb
Host smart-68ad8739-6f75-403b-be9b-84932c6e0f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615347368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1615347368
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1023529794
Short name T210
Test name
Test status
Simulation time 9001111939 ps
CPU time 12.57 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 205504 kb
Host smart-b5094797-a00a-4abe-9a60-6289db70ffed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023529794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1023529794
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3065534053
Short name T182
Test name
Test status
Simulation time 32222046 ps
CPU time 0.84 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:50 PM PDT 24
Peak memory 205284 kb
Host smart-c2fcad2d-10b6-4bac-9f6b-00858f3323ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065534053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3065534053
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2589294169
Short name T273
Test name
Test status
Simulation time 5128129411 ps
CPU time 11.87 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 213888 kb
Host smart-a7234d19-cee8-418f-9dd7-4ffcba769687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589294169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2589294169
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1786192921
Short name T300
Test name
Test status
Simulation time 2376723745 ps
CPU time 2.2 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:52 PM PDT 24
Peak memory 214000 kb
Host smart-a6de3bd1-3963-4230-8b66-f36f40dca8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786192921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1786192921
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2368348760
Short name T3
Test name
Test status
Simulation time 3421558073 ps
CPU time 3.66 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 213816 kb
Host smart-5c0a540c-b394-4adb-aadc-840ed2d64fe1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368348760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2368348760
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.4015513790
Short name T256
Test name
Test status
Simulation time 246396600 ps
CPU time 0.95 seconds
Started Aug 03 04:34:54 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205276 kb
Host smart-1a07064a-3b12-42b9-b9df-8258e1c1c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015513790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.4015513790
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2671340312
Short name T7
Test name
Test status
Simulation time 275728023 ps
CPU time 0.84 seconds
Started Aug 03 04:34:58 PM PDT 24
Finished Aug 03 04:34:59 PM PDT 24
Peak memory 205164 kb
Host smart-7c3d8b3d-bf80-4c54-82d5-90432aa6c1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671340312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2671340312
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1956584846
Short name T12
Test name
Test status
Simulation time 2012002651 ps
CPU time 2.91 seconds
Started Aug 03 04:34:49 PM PDT 24
Finished Aug 03 04:34:52 PM PDT 24
Peak memory 205564 kb
Host smart-73566353-e094-4fd7-9dee-12072cb31cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956584846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1956584846
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.669259630
Short name T68
Test name
Test status
Simulation time 516979974 ps
CPU time 1.44 seconds
Started Aug 03 04:34:48 PM PDT 24
Finished Aug 03 04:34:50 PM PDT 24
Peak memory 229276 kb
Host smart-d7eb47ac-2108-4b19-ae67-1f09798fd978
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669259630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.669259630
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3337761870
Short name T44
Test name
Test status
Simulation time 3360976094 ps
CPU time 3.9 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:49 PM PDT 24
Peak memory 213736 kb
Host smart-1ec52ea2-b887-4648-acc3-7ea4c081e4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337761870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3337761870
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2059519281
Short name T171
Test name
Test status
Simulation time 103996726 ps
CPU time 0.96 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:09 PM PDT 24
Peak memory 205244 kb
Host smart-27aab6ed-4620-4865-b4c8-2ccc92a27250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059519281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2059519281
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.4179665076
Short name T306
Test name
Test status
Simulation time 7454569397 ps
CPU time 7.92 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 213744 kb
Host smart-f531b4bc-c2ef-40fc-95d8-1f313af6f954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179665076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.4179665076
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2487149857
Short name T211
Test name
Test status
Simulation time 128047278 ps
CPU time 1.02 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:09 PM PDT 24
Peak memory 205272 kb
Host smart-71936b04-abf1-4b36-bfe9-32faf16f010b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487149857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2487149857
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1806747792
Short name T245
Test name
Test status
Simulation time 2892513661 ps
CPU time 5.1 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 213768 kb
Host smart-de4630b7-966b-47e3-abde-e6447f8233f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806747792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1806747792
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2405221749
Short name T212
Test name
Test status
Simulation time 57839195 ps
CPU time 0.78 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 205160 kb
Host smart-2c448953-ee57-40f7-9dfa-94b0aab8238b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405221749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2405221749
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3513111096
Short name T4
Test name
Test status
Simulation time 1810523465 ps
CPU time 5.53 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 213584 kb
Host smart-7fe5fa95-1496-48c0-9646-95e0b84a3273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513111096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3513111096
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1899571803
Short name T219
Test name
Test status
Simulation time 39682190 ps
CPU time 0.78 seconds
Started Aug 03 04:35:10 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 205172 kb
Host smart-d8d7b6c8-e89a-4ccf-bdf4-ee76156cd4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899571803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1899571803
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3936647603
Short name T138
Test name
Test status
Simulation time 11843075387 ps
CPU time 13.37 seconds
Started Aug 03 04:35:10 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 213644 kb
Host smart-5c7ace96-8600-4906-ab01-cb9b65dbdfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936647603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3936647603
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2416017426
Short name T299
Test name
Test status
Simulation time 54056210 ps
CPU time 0.86 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 205172 kb
Host smart-67546373-1467-4062-8c0f-b98389b56b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416017426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2416017426
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2178814802
Short name T275
Test name
Test status
Simulation time 8710466392 ps
CPU time 7.52 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 205540 kb
Host smart-eda817b4-4c2a-44f5-b3f1-433412361e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178814802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2178814802
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.694101038
Short name T170
Test name
Test status
Simulation time 47618784 ps
CPU time 0.79 seconds
Started Aug 03 04:35:01 PM PDT 24
Finished Aug 03 04:35:01 PM PDT 24
Peak memory 205288 kb
Host smart-385c68b7-ce9c-45e7-9772-a9440aa4be30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694101038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.694101038
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.4233558949
Short name T11
Test name
Test status
Simulation time 15239062817 ps
CPU time 14.59 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:29 PM PDT 24
Peak memory 219144 kb
Host smart-1c2791e8-ee53-4eea-9917-44983c009a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233558949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.4233558949
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.150397491
Short name T269
Test name
Test status
Simulation time 89308067 ps
CPU time 0.74 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:09 PM PDT 24
Peak memory 205232 kb
Host smart-ad3471b4-bc4d-475a-a43e-6ffd0dfe8b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150397491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.150397491
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.4026543559
Short name T5
Test name
Test status
Simulation time 6804973003 ps
CPU time 10.73 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 213712 kb
Host smart-3cc497b5-9c4b-41db-a96e-a3947fd982d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026543559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.4026543559
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.294989694
Short name T259
Test name
Test status
Simulation time 138550791 ps
CPU time 0.86 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 205172 kb
Host smart-d499ee6b-6c90-4aa9-afb4-0159463fb63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294989694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.294989694
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3254774213
Short name T296
Test name
Test status
Simulation time 2382170879 ps
CPU time 6.53 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:09 PM PDT 24
Peak memory 205488 kb
Host smart-6a1b60b4-f547-4ef4-814f-3ebf65ecabe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254774213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3254774213
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.570829678
Short name T225
Test name
Test status
Simulation time 103949793 ps
CPU time 0.94 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 205156 kb
Host smart-7569e71f-c236-45d6-9182-d324677414a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570829678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.570829678
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1351614151
Short name T52
Test name
Test status
Simulation time 3426609241 ps
CPU time 2.78 seconds
Started Aug 03 04:35:10 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 213912 kb
Host smart-9297887d-7503-4974-b632-7edd22afe723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351614151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1351614151
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3997965875
Short name T216
Test name
Test status
Simulation time 53237979 ps
CPU time 0.82 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 205216 kb
Host smart-f7855672-2972-4b6d-bb7b-1e51d55e2699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997965875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3997965875
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2728702059
Short name T74
Test name
Test status
Simulation time 7727289444 ps
CPU time 22.19 seconds
Started Aug 03 04:35:12 PM PDT 24
Finished Aug 03 04:35:34 PM PDT 24
Peak memory 213644 kb
Host smart-be5d25f3-9019-443d-ac74-d33ecd989493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728702059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2728702059
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.4148420398
Short name T189
Test name
Test status
Simulation time 59620828 ps
CPU time 0.81 seconds
Started Aug 03 04:34:54 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205148 kb
Host smart-312bf5d9-bc2e-4535-82c8-f79471a55d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148420398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.4148420398
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1845269112
Short name T264
Test name
Test status
Simulation time 3538075207 ps
CPU time 4.17 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:49 PM PDT 24
Peak memory 205720 kb
Host smart-c2cd0d48-57af-4416-bab8-7ad4df04852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845269112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1845269112
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1550649642
Short name T25
Test name
Test status
Simulation time 3738281133 ps
CPU time 3.24 seconds
Started Aug 03 04:35:03 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 213816 kb
Host smart-193e86a3-2350-4bdb-b453-c021d69b5b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550649642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1550649642
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2478608356
Short name T82
Test name
Test status
Simulation time 4217662943 ps
CPU time 8.11 seconds
Started Aug 03 04:34:56 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 213840 kb
Host smart-4b2db3cf-0aaf-46bd-a2a2-d591a1b80d52
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478608356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2478608356
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.622787992
Short name T43
Test name
Test status
Simulation time 476722354 ps
CPU time 1.02 seconds
Started Aug 03 04:35:01 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 205184 kb
Host smart-f4f8c485-7ceb-4a9c-8523-5442eca3e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622787992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.622787992
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1519725318
Short name T172
Test name
Test status
Simulation time 2688994130 ps
CPU time 3.91 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:34:51 PM PDT 24
Peak memory 205628 kb
Host smart-3613cc95-cd73-4a27-b603-642c9e448413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519725318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1519725318
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1406887566
Short name T152
Test name
Test status
Simulation time 7298923538 ps
CPU time 4.06 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:34:58 PM PDT 24
Peak memory 213824 kb
Host smart-cf827891-daa8-4246-93d6-4cc8c6a0f928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406887566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1406887566
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.497507597
Short name T217
Test name
Test status
Simulation time 47803894 ps
CPU time 0.87 seconds
Started Aug 03 04:35:05 PM PDT 24
Finished Aug 03 04:35:06 PM PDT 24
Peak memory 205192 kb
Host smart-d9391357-867a-4ce7-9557-b8c5d13ca34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497507597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.497507597
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2865485070
Short name T281
Test name
Test status
Simulation time 14693115344 ps
CPU time 15.13 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 205720 kb
Host smart-0d8eaded-10eb-4c51-842b-da706fc14a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865485070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2865485070
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3743496529
Short name T250
Test name
Test status
Simulation time 1316673385 ps
CPU time 5.02 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205596 kb
Host smart-1dc6e52f-9fd6-4e82-9037-e3b436b19def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743496529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3743496529
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3921392674
Short name T188
Test name
Test status
Simulation time 2317457178 ps
CPU time 4.58 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:34:58 PM PDT 24
Peak memory 205620 kb
Host smart-d6d9786f-646d-439b-8110-06a4942303cc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921392674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3921392674
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.2766747217
Short name T42
Test name
Test status
Simulation time 510857288 ps
CPU time 1.9 seconds
Started Aug 03 04:34:45 PM PDT 24
Finished Aug 03 04:34:47 PM PDT 24
Peak memory 205276 kb
Host smart-e4cef2b4-6b84-4fd8-bdce-b3de136a5f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766747217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2766747217
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.771159521
Short name T194
Test name
Test status
Simulation time 2072508066 ps
CPU time 4.14 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:54 PM PDT 24
Peak memory 205600 kb
Host smart-aec89143-3ecc-463a-b04b-3646717dca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771159521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.771159521
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1811329391
Short name T66
Test name
Test status
Simulation time 1604788164 ps
CPU time 4.55 seconds
Started Aug 03 04:34:51 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 213540 kb
Host smart-16a8cc04-1bee-450f-bdb8-75306bd314a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811329391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1811329391
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.200085184
Short name T55
Test name
Test status
Simulation time 54879530419 ps
CPU time 240.14 seconds
Started Aug 03 04:34:51 PM PDT 24
Finished Aug 03 04:38:51 PM PDT 24
Peak memory 230268 kb
Host smart-ef08a119-08dd-43b8-8fe3-6370907e8061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200085184 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.200085184
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2320135894
Short name T247
Test name
Test status
Simulation time 51250462 ps
CPU time 0.71 seconds
Started Aug 03 04:34:58 PM PDT 24
Finished Aug 03 04:34:59 PM PDT 24
Peak memory 205180 kb
Host smart-92e58f0e-af98-4919-a06d-04228c477b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320135894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2320135894
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.13806353
Short name T236
Test name
Test status
Simulation time 6923129187 ps
CPU time 7.78 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:58 PM PDT 24
Peak memory 213956 kb
Host smart-f939d292-a633-4740-83a1-00fee06db09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13806353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.13806353
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1332600609
Short name T80
Test name
Test status
Simulation time 9306571908 ps
CPU time 7.68 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:35:01 PM PDT 24
Peak memory 215144 kb
Host smart-382ba751-0936-447d-84ec-63d884933fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332600609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1332600609
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3443131004
Short name T290
Test name
Test status
Simulation time 4064601084 ps
CPU time 10.47 seconds
Started Aug 03 04:34:53 PM PDT 24
Finished Aug 03 04:35:03 PM PDT 24
Peak memory 205648 kb
Host smart-e11c846b-a4c5-41c5-8b4a-3a913e02bee6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443131004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3443131004
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.70564676
Short name T298
Test name
Test status
Simulation time 427492876 ps
CPU time 0.76 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:09 PM PDT 24
Peak memory 205228 kb
Host smart-a52f1629-8469-4a4a-9694-703b7384bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70564676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.70564676
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.613580828
Short name T183
Test name
Test status
Simulation time 1767356649 ps
CPU time 3.51 seconds
Started Aug 03 04:34:59 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 205628 kb
Host smart-92d5428c-9ad2-4998-bb43-30e9f7519b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613580828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.613580828
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.4178009321
Short name T146
Test name
Test status
Simulation time 5000150849 ps
CPU time 4.59 seconds
Started Aug 03 04:34:48 PM PDT 24
Finished Aug 03 04:34:53 PM PDT 24
Peak memory 213700 kb
Host smart-a46f6952-300a-4ec5-8a26-1b14fbed608b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178009321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.4178009321
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.725637460
Short name T14
Test name
Test status
Simulation time 100206735192 ps
CPU time 405.78 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:41:36 PM PDT 24
Peak memory 230328 kb
Host smart-f3920a50-5f2d-457e-8068-e80040d18d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725637460 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.725637460
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.4011662509
Short name T252
Test name
Test status
Simulation time 95536873 ps
CPU time 0.76 seconds
Started Aug 03 04:34:46 PM PDT 24
Finished Aug 03 04:34:47 PM PDT 24
Peak memory 205224 kb
Host smart-0bf4e54e-f1b1-40bc-b687-870d092444ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011662509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4011662509
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.407396143
Short name T78
Test name
Test status
Simulation time 3874604048 ps
CPU time 4.39 seconds
Started Aug 03 04:34:55 PM PDT 24
Finished Aug 03 04:34:59 PM PDT 24
Peak memory 213824 kb
Host smart-cf273ab3-14e1-414c-b58a-a3ed11a1c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407396143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.407396143
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2126895679
Short name T200
Test name
Test status
Simulation time 5292236626 ps
CPU time 9.66 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:35:02 PM PDT 24
Peak memory 213860 kb
Host smart-7d84c95e-9d94-45d0-8ab1-71f61339f3e4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126895679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2126895679
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3427034009
Short name T176
Test name
Test status
Simulation time 3702125625 ps
CPU time 4.79 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:34:52 PM PDT 24
Peak memory 205716 kb
Host smart-33cd959c-ffb4-4d73-9a5e-b93e40dc7ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427034009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3427034009
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2849146424
Short name T304
Test name
Test status
Simulation time 3133036479 ps
CPU time 8.94 seconds
Started Aug 03 04:34:50 PM PDT 24
Finished Aug 03 04:34:59 PM PDT 24
Peak memory 213624 kb
Host smart-ed07377d-cd6b-46b5-aa5f-b8aeda914ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849146424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2849146424
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1238642988
Short name T195
Test name
Test status
Simulation time 122276640 ps
CPU time 0.88 seconds
Started Aug 03 04:34:47 PM PDT 24
Finished Aug 03 04:34:48 PM PDT 24
Peak memory 205284 kb
Host smart-c68bddd1-b617-4a73-bb7b-e518f1ba5164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238642988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1238642988
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.845615154
Short name T280
Test name
Test status
Simulation time 44356013250 ps
CPU time 62.68 seconds
Started Aug 03 04:35:00 PM PDT 24
Finished Aug 03 04:36:03 PM PDT 24
Peak memory 205704 kb
Host smart-a9d42a84-c47c-440a-af6c-feac55a55f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845615154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.845615154
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3653540911
Short name T229
Test name
Test status
Simulation time 1488978853 ps
CPU time 2.23 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 205544 kb
Host smart-f5087dc4-4b2f-4ec1-85d0-1154b774ff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653540911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3653540911
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1396295460
Short name T258
Test name
Test status
Simulation time 3373026389 ps
CPU time 6.1 seconds
Started Aug 03 04:34:58 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 205648 kb
Host smart-63f54605-f557-485f-9a45-6c45edeb065b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396295460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1396295460
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.654508516
Short name T215
Test name
Test status
Simulation time 1943135495 ps
CPU time 2.35 seconds
Started Aug 03 04:34:52 PM PDT 24
Finished Aug 03 04:34:54 PM PDT 24
Peak memory 205540 kb
Host smart-254b9a09-5199-47d7-9228-eceda72f6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654508516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.654508516
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.347533578
Short name T142
Test name
Test status
Simulation time 2286662338 ps
CPU time 3.97 seconds
Started Aug 03 04:34:54 PM PDT 24
Finished Aug 03 04:34:58 PM PDT 24
Peak memory 213736 kb
Host smart-86ece785-949b-4d20-8e5b-8dd74d1e6c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347533578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.347533578
Directory /workspace/9.rv_dm_stress_all/latest
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