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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.86 96.18 85.48 89.91 72.50 88.33 98.32 56.31


Total test records in report: 465
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T66 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4024928220 Aug 04 04:29:53 PM PDT 24 Aug 04 04:29:56 PM PDT 24 106546570 ps
T67 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2239435813 Aug 04 04:30:07 PM PDT 24 Aug 04 04:30:17 PM PDT 24 1772786875 ps
T77 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2855354883 Aug 04 04:29:45 PM PDT 24 Aug 04 04:29:50 PM PDT 24 594906859 ps
T68 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.110448382 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:49 PM PDT 24 1238402770 ps
T69 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.459719228 Aug 04 04:29:18 PM PDT 24 Aug 04 04:29:20 PM PDT 24 166893049 ps
T70 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1887305311 Aug 04 04:29:49 PM PDT 24 Aug 04 04:29:52 PM PDT 24 333994530 ps
T111 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1311898092 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:48 PM PDT 24 1168215624 ps
T309 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1137249881 Aug 04 04:29:11 PM PDT 24 Aug 04 04:29:12 PM PDT 24 112728389 ps
T78 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.39385564 Aug 04 04:29:44 PM PDT 24 Aug 04 04:29:49 PM PDT 24 1076786711 ps
T79 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3783132718 Aug 04 04:29:31 PM PDT 24 Aug 04 04:29:33 PM PDT 24 325064914 ps
T55 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3394445639 Aug 04 04:30:07 PM PDT 24 Aug 04 04:30:09 PM PDT 24 115815466 ps
T310 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1965974892 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:54 PM PDT 24 4890605868 ps
T311 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2353387784 Aug 04 04:29:17 PM PDT 24 Aug 04 04:31:25 PM PDT 24 48232768696 ps
T80 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2600108464 Aug 04 04:29:29 PM PDT 24 Aug 04 04:29:32 PM PDT 24 176364569 ps
T312 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2969274507 Aug 04 04:30:01 PM PDT 24 Aug 04 04:30:05 PM PDT 24 365452397 ps
T151 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3446470783 Aug 04 04:29:33 PM PDT 24 Aug 04 04:29:53 PM PDT 24 2761747839 ps
T81 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.706760133 Aug 04 04:29:47 PM PDT 24 Aug 04 04:30:00 PM PDT 24 243916972 ps
T82 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1389636499 Aug 04 04:29:33 PM PDT 24 Aug 04 04:30:41 PM PDT 24 19686677481 ps
T56 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1358330899 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:40 PM PDT 24 196363424 ps
T86 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3233353808 Aug 04 04:29:17 PM PDT 24 Aug 04 04:29:34 PM PDT 24 3984832595 ps
T83 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.543834635 Aug 04 04:29:45 PM PDT 24 Aug 04 04:30:21 PM PDT 24 7085627775 ps
T51 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3672432064 Aug 04 04:29:29 PM PDT 24 Aug 04 04:30:12 PM PDT 24 17141750809 ps
T313 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3538546313 Aug 04 04:29:57 PM PDT 24 Aug 04 04:30:34 PM PDT 24 16351184268 ps
T314 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.712072836 Aug 04 04:29:51 PM PDT 24 Aug 04 04:30:16 PM PDT 24 8923922921 ps
T152 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2887120901 Aug 04 04:29:17 PM PDT 24 Aug 04 04:29:26 PM PDT 24 647266018 ps
T315 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1455749036 Aug 04 04:29:15 PM PDT 24 Aug 04 04:29:18 PM PDT 24 424774440 ps
T316 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3601316666 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:36 PM PDT 24 204381610 ps
T52 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2001847114 Aug 04 04:29:13 PM PDT 24 Aug 04 04:30:00 PM PDT 24 51465684288 ps
T317 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.43211919 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:55 PM PDT 24 4423184102 ps
T318 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2009145800 Aug 04 04:29:40 PM PDT 24 Aug 04 04:29:50 PM PDT 24 14521629249 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1433390462 Aug 04 04:29:16 PM PDT 24 Aug 04 04:29:27 PM PDT 24 3677148780 ps
T154 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.594463567 Aug 04 04:29:43 PM PDT 24 Aug 04 04:30:04 PM PDT 24 2219090490 ps
T84 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.492687829 Aug 04 04:29:29 PM PDT 24 Aug 04 04:30:50 PM PDT 24 18030190678 ps
T163 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2441955157 Aug 04 04:29:22 PM PDT 24 Aug 04 04:29:53 PM PDT 24 30790698359 ps
T89 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1033425459 Aug 04 04:29:38 PM PDT 24 Aug 04 04:30:11 PM PDT 24 8596757200 ps
T164 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1348206364 Aug 04 04:29:40 PM PDT 24 Aug 04 04:32:22 PM PDT 24 53329849485 ps
T320 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1267182921 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:37 PM PDT 24 291528667 ps
T321 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4177084393 Aug 04 04:29:20 PM PDT 24 Aug 04 04:29:21 PM PDT 24 101037802 ps
T87 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3342456732 Aug 04 04:29:33 PM PDT 24 Aug 04 04:29:45 PM PDT 24 3797092598 ps
T322 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1081525329 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:39 PM PDT 24 739469107 ps
T323 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1365381115 Aug 04 04:29:28 PM PDT 24 Aug 04 04:29:30 PM PDT 24 1615513186 ps
T90 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3729801146 Aug 04 04:29:43 PM PDT 24 Aug 04 04:29:50 PM PDT 24 372475347 ps
T324 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3779994374 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:42 PM PDT 24 164272039 ps
T159 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4080871236 Aug 04 04:30:00 PM PDT 24 Aug 04 04:30:28 PM PDT 24 5108193123 ps
T155 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3353372957 Aug 04 04:29:46 PM PDT 24 Aug 04 04:30:03 PM PDT 24 5599268918 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.52415396 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:50 PM PDT 24 6277431754 ps
T99 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2025089309 Aug 04 04:29:52 PM PDT 24 Aug 04 04:29:55 PM PDT 24 213559708 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.926449186 Aug 04 04:29:17 PM PDT 24 Aug 04 04:29:20 PM PDT 24 130408046 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3249747672 Aug 04 04:29:13 PM PDT 24 Aug 04 04:29:17 PM PDT 24 2779821549 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3222947986 Aug 04 04:30:02 PM PDT 24 Aug 04 04:31:36 PM PDT 24 28944211820 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2412485101 Aug 04 04:29:47 PM PDT 24 Aug 04 04:29:53 PM PDT 24 587749223 ps
T328 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.494436832 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:40 PM PDT 24 141876332 ps
T112 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3052273349 Aug 04 04:30:01 PM PDT 24 Aug 04 04:30:04 PM PDT 24 159843726 ps
T329 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2934128947 Aug 04 04:29:54 PM PDT 24 Aug 04 04:29:56 PM PDT 24 103474550 ps
T102 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1041081768 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:39 PM PDT 24 268565221 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3207164761 Aug 04 04:29:55 PM PDT 24 Aug 04 04:29:56 PM PDT 24 124396105 ps
T331 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2711316035 Aug 04 04:29:55 PM PDT 24 Aug 04 04:30:00 PM PDT 24 657036473 ps
T106 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2429877718 Aug 04 04:29:58 PM PDT 24 Aug 04 04:30:06 PM PDT 24 506896236 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4201886273 Aug 04 04:29:19 PM PDT 24 Aug 04 04:29:21 PM PDT 24 346486093 ps
T333 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.290429114 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:41 PM PDT 24 178986465 ps
T334 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3921958801 Aug 04 04:29:58 PM PDT 24 Aug 04 04:29:59 PM PDT 24 96693331 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1843601661 Aug 04 04:29:57 PM PDT 24 Aug 04 04:30:55 PM PDT 24 24512453601 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2352437414 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:37 PM PDT 24 305870492 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1060737144 Aug 04 04:29:49 PM PDT 24 Aug 04 04:29:58 PM PDT 24 11724724251 ps
T157 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2302725492 Aug 04 04:29:46 PM PDT 24 Aug 04 04:30:15 PM PDT 24 13972790760 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.755515196 Aug 04 04:29:48 PM PDT 24 Aug 04 04:29:49 PM PDT 24 69431124 ps
T339 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4171116448 Aug 04 04:29:40 PM PDT 24 Aug 04 04:29:41 PM PDT 24 269008330 ps
T340 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3001429256 Aug 04 04:30:04 PM PDT 24 Aug 04 04:30:05 PM PDT 24 228943085 ps
T341 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1541875134 Aug 04 04:29:54 PM PDT 24 Aug 04 04:29:55 PM PDT 24 648064338 ps
T165 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2182078227 Aug 04 04:29:40 PM PDT 24 Aug 04 04:30:31 PM PDT 24 53643416106 ps
T342 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3065928259 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:51 PM PDT 24 19093976486 ps
T343 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3228042874 Aug 04 04:29:49 PM PDT 24 Aug 04 04:29:51 PM PDT 24 80764248 ps
T344 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3060364797 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:40 PM PDT 24 203739921 ps
T345 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3942443161 Aug 04 04:30:05 PM PDT 24 Aug 04 04:30:09 PM PDT 24 232345773 ps
T158 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1318196406 Aug 04 04:29:42 PM PDT 24 Aug 04 04:29:52 PM PDT 24 1232928063 ps
T346 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2556556376 Aug 04 04:29:42 PM PDT 24 Aug 04 04:29:45 PM PDT 24 115953772 ps
T347 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.614226449 Aug 04 04:29:55 PM PDT 24 Aug 04 04:29:58 PM PDT 24 2259631534 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3795520955 Aug 04 04:29:16 PM PDT 24 Aug 04 04:29:43 PM PDT 24 72961288163 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2349548878 Aug 04 04:29:31 PM PDT 24 Aug 04 04:29:35 PM PDT 24 4575922281 ps
T350 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4167136236 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:39 PM PDT 24 206824494 ps
T351 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3875327768 Aug 04 04:29:13 PM PDT 24 Aug 04 04:29:14 PM PDT 24 85749339 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4220833705 Aug 04 04:29:30 PM PDT 24 Aug 04 04:29:32 PM PDT 24 125459549 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3841962886 Aug 04 04:29:18 PM PDT 24 Aug 04 04:29:27 PM PDT 24 3514323946 ps
T103 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.314970653 Aug 04 04:30:07 PM PDT 24 Aug 04 04:30:09 PM PDT 24 182284506 ps
T91 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3487196894 Aug 04 04:30:08 PM PDT 24 Aug 04 04:30:12 PM PDT 24 529943108 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.773913119 Aug 04 04:29:38 PM PDT 24 Aug 04 04:30:20 PM PDT 24 24375136434 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4034148980 Aug 04 04:29:31 PM PDT 24 Aug 04 04:29:34 PM PDT 24 381850673 ps
T156 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1821230022 Aug 04 04:30:03 PM PDT 24 Aug 04 04:30:20 PM PDT 24 1389044020 ps
T354 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2301108314 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:41 PM PDT 24 439848344 ps
T355 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2631640150 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:37 PM PDT 24 351348848 ps
T356 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2710711124 Aug 04 04:30:01 PM PDT 24 Aug 04 04:30:03 PM PDT 24 408102715 ps
T357 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2114039395 Aug 04 04:29:17 PM PDT 24 Aug 04 04:29:18 PM PDT 24 259746271 ps
T105 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3635355365 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:38 PM PDT 24 158016782 ps
T358 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2973467525 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:41 PM PDT 24 722760863 ps
T359 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1628904751 Aug 04 04:29:33 PM PDT 24 Aug 04 04:29:38 PM PDT 24 343080896 ps
T360 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3427293863 Aug 04 04:29:36 PM PDT 24 Aug 04 04:30:07 PM PDT 24 38013420007 ps
T361 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3274225006 Aug 04 04:29:09 PM PDT 24 Aug 04 04:29:41 PM PDT 24 42051116474 ps
T107 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3811543476 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:42 PM PDT 24 293662299 ps
T362 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.907493185 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:44 PM PDT 24 4613769751 ps
T363 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1219609684 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:41 PM PDT 24 562798529 ps
T364 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1176646386 Aug 04 04:29:49 PM PDT 24 Aug 04 04:29:50 PM PDT 24 66075504 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4007070990 Aug 04 04:29:33 PM PDT 24 Aug 04 04:29:34 PM PDT 24 47762853 ps
T93 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2301447050 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:42 PM PDT 24 1455923964 ps
T366 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2172969981 Aug 04 04:29:14 PM PDT 24 Aug 04 04:29:17 PM PDT 24 617174012 ps
T367 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1186774705 Aug 04 04:30:02 PM PDT 24 Aug 04 04:30:06 PM PDT 24 285572626 ps
T368 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1706195495 Aug 04 04:29:55 PM PDT 24 Aug 04 04:30:01 PM PDT 24 5567756603 ps
T369 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3610615298 Aug 04 04:29:47 PM PDT 24 Aug 04 04:29:50 PM PDT 24 2969400195 ps
T370 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1318542455 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:36 PM PDT 24 96993168 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.926186731 Aug 04 04:29:48 PM PDT 24 Aug 04 04:29:52 PM PDT 24 2033525930 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1913751940 Aug 04 04:29:41 PM PDT 24 Aug 04 04:29:50 PM PDT 24 1269371319 ps
T372 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2188638753 Aug 04 04:30:00 PM PDT 24 Aug 04 04:30:07 PM PDT 24 61019097 ps
T161 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.439696306 Aug 04 04:29:41 PM PDT 24 Aug 04 04:29:50 PM PDT 24 2080975296 ps
T373 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1233477352 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:45 PM PDT 24 4880207113 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3817451950 Aug 04 04:29:50 PM PDT 24 Aug 04 04:29:53 PM PDT 24 156163952 ps
T375 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2567337529 Aug 04 04:29:57 PM PDT 24 Aug 04 04:30:09 PM PDT 24 4216977652 ps
T376 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3706013626 Aug 04 04:29:58 PM PDT 24 Aug 04 04:30:02 PM PDT 24 2998123456 ps
T377 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1506657473 Aug 04 04:30:13 PM PDT 24 Aug 04 04:30:35 PM PDT 24 17064393148 ps
T378 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.561673656 Aug 04 04:30:05 PM PDT 24 Aug 04 04:30:07 PM PDT 24 1198862225 ps
T379 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.303623583 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:36 PM PDT 24 102983712 ps
T380 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.534707493 Aug 04 04:29:46 PM PDT 24 Aug 04 04:29:49 PM PDT 24 381416145 ps
T381 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1996310336 Aug 04 04:29:42 PM PDT 24 Aug 04 04:31:10 PM PDT 24 60556200332 ps
T109 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.599045951 Aug 04 04:30:17 PM PDT 24 Aug 04 04:30:20 PM PDT 24 174362027 ps
T382 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3621953441 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:41 PM PDT 24 5795791810 ps
T383 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.976987753 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:40 PM PDT 24 271880810 ps
T384 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.407466669 Aug 04 04:29:47 PM PDT 24 Aug 04 04:29:53 PM PDT 24 1032645691 ps
T385 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2232510874 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:36 PM PDT 24 843592429 ps
T386 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3334581643 Aug 04 04:29:48 PM PDT 24 Aug 04 04:33:31 PM PDT 24 83048145074 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1696210375 Aug 04 04:29:12 PM PDT 24 Aug 04 04:29:13 PM PDT 24 153786532 ps
T388 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3530022028 Aug 04 04:29:33 PM PDT 24 Aug 04 04:29:34 PM PDT 24 138421645 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2618750764 Aug 04 04:29:13 PM PDT 24 Aug 04 04:29:22 PM PDT 24 14928793688 ps
T390 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2237315775 Aug 04 04:30:10 PM PDT 24 Aug 04 04:30:14 PM PDT 24 269171988 ps
T391 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.89692307 Aug 04 04:29:46 PM PDT 24 Aug 04 04:29:53 PM PDT 24 443227115 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.220551475 Aug 04 04:29:27 PM PDT 24 Aug 04 04:29:28 PM PDT 24 412491789 ps
T393 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3135130129 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:36 PM PDT 24 86914944 ps
T394 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.149193591 Aug 04 04:29:18 PM PDT 24 Aug 04 04:29:19 PM PDT 24 79714574 ps
T395 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3178997739 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:47 PM PDT 24 8761747626 ps
T396 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2730493596 Aug 04 04:30:00 PM PDT 24 Aug 04 04:31:08 PM PDT 24 40898689567 ps
T397 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1753411258 Aug 04 04:29:53 PM PDT 24 Aug 04 04:30:00 PM PDT 24 379964665 ps
T398 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3596957040 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:49 PM PDT 24 8710530754 ps
T399 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1993385568 Aug 04 04:29:46 PM PDT 24 Aug 04 04:29:51 PM PDT 24 4279424025 ps
T94 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2083188793 Aug 04 04:29:49 PM PDT 24 Aug 04 04:29:51 PM PDT 24 220972717 ps
T400 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1063051649 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:33 PM PDT 24 71376957 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2717185724 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:33 PM PDT 24 1047478446 ps
T402 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3121573196 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:43 PM PDT 24 85967226 ps
T403 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4177143416 Aug 04 04:30:03 PM PDT 24 Aug 04 04:30:12 PM PDT 24 8080159449 ps
T404 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2388981251 Aug 04 04:30:06 PM PDT 24 Aug 04 04:30:10 PM PDT 24 4439613803 ps
T405 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.526678934 Aug 04 04:29:45 PM PDT 24 Aug 04 04:31:04 PM PDT 24 27675903914 ps
T406 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.608732175 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:44 PM PDT 24 3674493092 ps
T407 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3774406804 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:38 PM PDT 24 1992407554 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3994466807 Aug 04 04:29:11 PM PDT 24 Aug 04 04:29:12 PM PDT 24 235682450 ps
T409 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4040145789 Aug 04 04:29:35 PM PDT 24 Aug 04 04:30:46 PM PDT 24 51551377440 ps
T410 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.402830596 Aug 04 04:29:30 PM PDT 24 Aug 04 04:31:24 PM PDT 24 79230996458 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3734365448 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:39 PM PDT 24 375763206 ps
T412 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.355806118 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:37 PM PDT 24 488689408 ps
T413 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.164116869 Aug 04 04:29:52 PM PDT 24 Aug 04 04:29:57 PM PDT 24 151798078 ps
T414 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4136005848 Aug 04 04:29:42 PM PDT 24 Aug 04 04:30:15 PM PDT 24 2449747522 ps
T95 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1627444710 Aug 04 04:29:42 PM PDT 24 Aug 04 04:29:49 PM PDT 24 635345886 ps
T415 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1274722325 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:41 PM PDT 24 7849067623 ps
T416 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1770079428 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:35 PM PDT 24 866566671 ps
T96 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1099722991 Aug 04 04:29:35 PM PDT 24 Aug 04 04:29:43 PM PDT 24 457465598 ps
T417 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2501348071 Aug 04 04:29:55 PM PDT 24 Aug 04 04:29:59 PM PDT 24 230846807 ps
T97 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1298272169 Aug 04 04:29:44 PM PDT 24 Aug 04 04:29:47 PM PDT 24 79051749 ps
T418 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1724125347 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:36 PM PDT 24 111178858 ps
T419 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1464173644 Aug 04 04:29:29 PM PDT 24 Aug 04 04:30:22 PM PDT 24 1487657154 ps
T98 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1853434531 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:42 PM PDT 24 530497203 ps
T420 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1753447177 Aug 04 04:29:43 PM PDT 24 Aug 04 04:29:47 PM PDT 24 733005236 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1135495989 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:46 PM PDT 24 8421901374 ps
T422 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3915990978 Aug 04 04:29:50 PM PDT 24 Aug 04 04:30:00 PM PDT 24 1437110437 ps
T423 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2094746938 Aug 04 04:29:38 PM PDT 24 Aug 04 04:30:04 PM PDT 24 7685992272 ps
T160 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.499048750 Aug 04 04:29:17 PM PDT 24 Aug 04 04:29:34 PM PDT 24 1092501652 ps
T424 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.913610050 Aug 04 04:29:38 PM PDT 24 Aug 04 04:30:12 PM PDT 24 29216219367 ps
T425 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4216350589 Aug 04 04:29:48 PM PDT 24 Aug 04 04:29:49 PM PDT 24 53180461 ps
T426 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4246588381 Aug 04 04:30:01 PM PDT 24 Aug 04 04:30:03 PM PDT 24 69842510 ps
T427 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2794504254 Aug 04 04:29:55 PM PDT 24 Aug 04 04:30:06 PM PDT 24 7140140879 ps
T428 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.525820810 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:36 PM PDT 24 240113587 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2388868060 Aug 04 04:29:16 PM PDT 24 Aug 04 04:29:18 PM PDT 24 127050402 ps
T430 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1409937333 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:38 PM PDT 24 946304259 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4104503153 Aug 04 04:29:31 PM PDT 24 Aug 04 04:29:34 PM PDT 24 97809275 ps
T432 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4123924314 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:39 PM PDT 24 102481680 ps
T433 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2477565766 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:48 PM PDT 24 34649556522 ps
T434 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2780261287 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:35 PM PDT 24 181023775 ps
T88 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.170218437 Aug 04 04:29:32 PM PDT 24 Aug 04 04:29:34 PM PDT 24 2014950422 ps
T435 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1605740665 Aug 04 04:29:57 PM PDT 24 Aug 04 04:30:02 PM PDT 24 2394934873 ps
T436 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3050022536 Aug 04 04:29:30 PM PDT 24 Aug 04 04:29:32 PM PDT 24 137098938 ps
T437 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1289265097 Aug 04 04:29:24 PM PDT 24 Aug 04 04:29:27 PM PDT 24 797878322 ps
T438 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.16659887 Aug 04 04:29:30 PM PDT 24 Aug 04 04:29:33 PM PDT 24 228505361 ps
T162 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3456571632 Aug 04 04:29:40 PM PDT 24 Aug 04 04:29:51 PM PDT 24 1529059934 ps
T439 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.290893803 Aug 04 04:29:16 PM PDT 24 Aug 04 04:29:34 PM PDT 24 1235079503 ps
T440 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1523336641 Aug 04 04:29:40 PM PDT 24 Aug 04 04:29:43 PM PDT 24 491832736 ps
T441 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1337264018 Aug 04 04:29:28 PM PDT 24 Aug 04 04:29:29 PM PDT 24 569456961 ps
T442 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2541949846 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:48 PM PDT 24 15941285581 ps
T443 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1107668012 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:38 PM PDT 24 307943929 ps
T444 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.480537803 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:47 PM PDT 24 2297778952 ps
T445 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1692251196 Aug 04 04:29:59 PM PDT 24 Aug 04 04:30:21 PM PDT 24 14681103260 ps
T446 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3737546852 Aug 04 04:29:42 PM PDT 24 Aug 04 04:29:43 PM PDT 24 321333887 ps
T447 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4134769524 Aug 04 04:29:57 PM PDT 24 Aug 04 04:30:00 PM PDT 24 154450425 ps
T448 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2770252279 Aug 04 04:29:36 PM PDT 24 Aug 04 04:35:32 PM PDT 24 62844728792 ps
T449 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3774097726 Aug 04 04:29:28 PM PDT 24 Aug 04 04:29:28 PM PDT 24 43443410 ps
T450 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1189751041 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:38 PM PDT 24 601911395 ps
T451 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3444213064 Aug 04 04:29:38 PM PDT 24 Aug 04 04:29:46 PM PDT 24 1128398675 ps
T452 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1699970556 Aug 04 04:29:31 PM PDT 24 Aug 04 04:29:37 PM PDT 24 3586275565 ps
T453 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3251764554 Aug 04 04:29:34 PM PDT 24 Aug 04 04:29:35 PM PDT 24 44364013 ps
T454 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1675921977 Aug 04 04:30:17 PM PDT 24 Aug 04 04:30:24 PM PDT 24 7386834024 ps
T455 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1645892415 Aug 04 04:29:40 PM PDT 24 Aug 04 04:30:58 PM PDT 24 25539345566 ps
T456 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3546296077 Aug 04 04:29:36 PM PDT 24 Aug 04 04:30:02 PM PDT 24 2483492151 ps
T457 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.767359776 Aug 04 04:29:39 PM PDT 24 Aug 04 04:29:40 PM PDT 24 1112925080 ps
T458 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.120606816 Aug 04 04:29:14 PM PDT 24 Aug 04 04:31:26 PM PDT 24 48403177777 ps
T459 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1890315324 Aug 04 04:29:29 PM PDT 24 Aug 04 04:29:31 PM PDT 24 296142665 ps
T153 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1965218076 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:54 PM PDT 24 4309265729 ps
T460 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3929074226 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:37 PM PDT 24 357424210 ps
T461 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1488040328 Aug 04 04:29:36 PM PDT 24 Aug 04 04:29:41 PM PDT 24 578114857 ps
T462 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1024540121 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:41 PM PDT 24 642760473 ps
T463 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2647346237 Aug 04 04:29:37 PM PDT 24 Aug 04 04:29:43 PM PDT 24 2256513520 ps
T464 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1285623597 Aug 04 04:29:54 PM PDT 24 Aug 04 04:29:57 PM PDT 24 389962411 ps
T465 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1874071054 Aug 04 04:29:54 PM PDT 24 Aug 04 04:29:58 PM PDT 24 2995301789 ps

Test location /workspace/coverage/default/1.rv_dm_stress_all.3009991934
Short name T2
Test name
Test status
Simulation time 3433035363 ps
CPU time 5.97 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 213620 kb
Host smart-77897b26-e37e-425f-b238-5338b9d4b7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009991934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3009991934
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.1097901655
Short name T17
Test name
Test status
Simulation time 213394616409 ps
CPU time 1041.62 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:47:29 PM PDT 24
Peak memory 238456 kb
Host smart-fdc33ac5-be42-4201-9aa0-bacd2594f3ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097901655 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.1097901655
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.538210065
Short name T22
Test name
Test status
Simulation time 4624429597 ps
CPU time 12.95 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:20 PM PDT 24
Peak memory 205620 kb
Host smart-339dba7e-5058-4217-9c1b-d7737ff7872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538210065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.538210065
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1563193856
Short name T31
Test name
Test status
Simulation time 834088534 ps
CPU time 1.4 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:26 PM PDT 24
Peak memory 230112 kb
Host smart-f5a6c69a-1e22-4b3f-ae2a-a57eb91468fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563193856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1563193856
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.110448382
Short name T68
Test name
Test status
Simulation time 1238402770 ps
CPU time 17.47 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 213708 kb
Host smart-a8d87142-e3b7-4ea2-94df-7cadee78192e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110448382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.110448382
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1348206364
Short name T164
Test name
Test status
Simulation time 53329849485 ps
CPU time 162.19 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 222100 kb
Host smart-ac94db0d-fdc1-4465-8b68-667389d43d4c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348206364 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1348206364
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.653346783
Short name T9
Test name
Test status
Simulation time 99425207272 ps
CPU time 690.54 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:41:53 PM PDT 24
Peak memory 238284 kb
Host smart-74bb61d5-d15d-42b2-824c-d9c4b0ce2be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653346783 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.653346783
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.4170154337
Short name T116
Test name
Test status
Simulation time 22009498614 ps
CPU time 40.73 seconds
Started Aug 04 04:30:15 PM PDT 24
Finished Aug 04 04:30:56 PM PDT 24
Peak memory 213868 kb
Host smart-0352268f-2bfe-452d-8fad-fb18837b0bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170154337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4170154337
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.4077741070
Short name T46
Test name
Test status
Simulation time 112593250 ps
CPU time 0.86 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 205044 kb
Host smart-311504cb-30a7-4f35-8cf1-543996e93a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077741070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.4077741070
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.111077210
Short name T128
Test name
Test status
Simulation time 17478858103 ps
CPU time 13.53 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:34 PM PDT 24
Peak memory 213744 kb
Host smart-a762f8ae-6611-45cf-9342-082b13e92f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111077210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.111077210
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.543834635
Short name T83
Test name
Test status
Simulation time 7085627775 ps
CPU time 35.26 seconds
Started Aug 04 04:29:45 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 213812 kb
Host smart-bfef2ca0-967d-41d4-9cf6-644bdea2aba2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543834635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.543834635
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3920540550
Short name T123
Test name
Test status
Simulation time 2021174891 ps
CPU time 5.71 seconds
Started Aug 04 04:30:05 PM PDT 24
Finished Aug 04 04:30:10 PM PDT 24
Peak memory 205244 kb
Host smart-4834501a-bf11-4848-9146-b267e025d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920540550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3920540550
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3985903973
Short name T15
Test name
Test status
Simulation time 228357771 ps
CPU time 1.28 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:30:08 PM PDT 24
Peak memory 205092 kb
Host smart-2ff49595-ef5d-4c83-8296-e19ec1eb832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985903973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3985903973
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2607046434
Short name T6
Test name
Test status
Simulation time 63133217064 ps
CPU time 1309.53 seconds
Started Aug 04 04:29:51 PM PDT 24
Finished Aug 04 04:51:41 PM PDT 24
Peak memory 239928 kb
Host smart-c8d0aa75-031a-4c89-a2e3-04e7c7a6aa63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607046434 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2607046434
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1717456835
Short name T26
Test name
Test status
Simulation time 4127071634 ps
CPU time 4.1 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 215404 kb
Host smart-34e0218a-28cf-46a1-98aa-dcca6f031716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717456835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1717456835
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.594463567
Short name T154
Test name
Test status
Simulation time 2219090490 ps
CPU time 21.22 seconds
Started Aug 04 04:29:43 PM PDT 24
Finished Aug 04 04:30:04 PM PDT 24
Peak memory 213924 kb
Host smart-e1352b1f-d458-4b11-b954-c964763ef2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594463567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.594463567
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1407112325
Short name T28
Test name
Test status
Simulation time 85015633 ps
CPU time 0.96 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 205248 kb
Host smart-7af5c839-da99-4a6a-b92d-3efcf771fd49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407112325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1407112325
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3282575861
Short name T148
Test name
Test status
Simulation time 3506190936 ps
CPU time 5.12 seconds
Started Aug 04 04:30:18 PM PDT 24
Finished Aug 04 04:30:23 PM PDT 24
Peak memory 213788 kb
Host smart-ccb0e5c6-4b39-457b-939d-e69fc7a4efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282575861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3282575861
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2696351122
Short name T139
Test name
Test status
Simulation time 2751225393 ps
CPU time 6.42 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205980 kb
Host smart-f75d9548-9ea8-46ad-846a-0f1a865c234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696351122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2696351122
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3580835562
Short name T1
Test name
Test status
Simulation time 707593799 ps
CPU time 1.87 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 205392 kb
Host smart-6d0ba56b-1602-4cc0-86a9-aa66bad90b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580835562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3580835562
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1298272169
Short name T97
Test name
Test status
Simulation time 79051749 ps
CPU time 2.13 seconds
Started Aug 04 04:29:44 PM PDT 24
Finished Aug 04 04:29:47 PM PDT 24
Peak memory 213632 kb
Host smart-51515ddf-c478-4b56-86e4-0d859e04de4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298272169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1298272169
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.500133774
Short name T35
Test name
Test status
Simulation time 103266373 ps
CPU time 0.83 seconds
Started Aug 04 04:30:21 PM PDT 24
Finished Aug 04 04:30:22 PM PDT 24
Peak memory 213296 kb
Host smart-a99f51b1-88d4-4b2a-8d87-5419490f0bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500133774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.500133774
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.1857722765
Short name T25
Test name
Test status
Simulation time 116759677 ps
CPU time 0.77 seconds
Started Aug 04 04:29:53 PM PDT 24
Finished Aug 04 04:29:54 PM PDT 24
Peak memory 205164 kb
Host smart-d9a52c0a-1584-461c-896e-000145bda559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857722765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1857722765
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3487196894
Short name T91
Test name
Test status
Simulation time 529943108 ps
CPU time 3.58 seconds
Started Aug 04 04:30:08 PM PDT 24
Finished Aug 04 04:30:12 PM PDT 24
Peak memory 205480 kb
Host smart-0ef50f58-6ef2-4fb6-b9db-1dfa144dc1a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487196894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3487196894
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.875810515
Short name T33
Test name
Test status
Simulation time 651715364 ps
CPU time 2.01 seconds
Started Aug 04 04:30:14 PM PDT 24
Finished Aug 04 04:30:16 PM PDT 24
Peak memory 205104 kb
Host smart-b356fed3-7e87-4f8a-872c-7baa543db6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875810515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.875810515
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2302725492
Short name T157
Test name
Test status
Simulation time 13972790760 ps
CPU time 24.41 seconds
Started Aug 04 04:29:46 PM PDT 24
Finished Aug 04 04:30:15 PM PDT 24
Peak memory 214236 kb
Host smart-81437b88-cb59-4db1-bf38-cdae92e5550b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302725492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
302725492
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3508940140
Short name T129
Test name
Test status
Simulation time 2929211451 ps
CPU time 10.19 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:27 PM PDT 24
Peak memory 215572 kb
Host smart-93e21d0f-4840-4c87-8238-d032b26bbfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508940140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3508940140
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1358330899
Short name T56
Test name
Test status
Simulation time 196363424 ps
CPU time 0.73 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:40 PM PDT 24
Peak memory 205212 kb
Host smart-194727e9-f14b-4f66-be03-386ae82db4a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358330899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
358330899
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2141719219
Short name T41
Test name
Test status
Simulation time 250472272 ps
CPU time 1.47 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205260 kb
Host smart-8defae45-688c-4020-ac0a-b51f611afe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141719219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2141719219
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.170218437
Short name T88
Test name
Test status
Simulation time 2014950422 ps
CPU time 2.39 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 205508 kb
Host smart-61f9b2ed-8eff-449d-ade2-1b7b51e926ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170218437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.170218437
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1318196406
Short name T158
Test name
Test status
Simulation time 1232928063 ps
CPU time 10.28 seconds
Started Aug 04 04:29:42 PM PDT 24
Finished Aug 04 04:29:52 PM PDT 24
Peak memory 221280 kb
Host smart-26afad6f-3312-44d7-a1a2-0e9dd007b719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318196406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
318196406
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1047646373
Short name T203
Test name
Test status
Simulation time 2413313142 ps
CPU time 2.54 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205616 kb
Host smart-e218c058-a9fb-4ba4-ab32-6a92087648d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047646373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1047646373
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1987640626
Short name T147
Test name
Test status
Simulation time 8843960091 ps
CPU time 7.5 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 213716 kb
Host smart-8b2ddbd7-9d26-4924-b6fb-21bddd447a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987640626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1987640626
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3222947986
Short name T101
Test name
Test status
Simulation time 28944211820 ps
CPU time 88.75 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:31:36 PM PDT 24
Peak memory 213812 kb
Host smart-d714855d-4cd5-4738-8602-bdadb6cc40b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222947986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3222947986
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4034148980
Short name T92
Test name
Test status
Simulation time 381850673 ps
CPU time 3.04 seconds
Started Aug 04 04:29:31 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 213800 kb
Host smart-4c6e2502-85b9-4cd0-8be3-30c2eafc8b68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034148980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4034148980
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1455749036
Short name T315
Test name
Test status
Simulation time 424774440 ps
CPU time 2.44 seconds
Started Aug 04 04:29:15 PM PDT 24
Finished Aug 04 04:29:18 PM PDT 24
Peak memory 213800 kb
Host smart-6e3acc69-cba1-4003-bae1-34bcba06a80d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455749036 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1455749036
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3875327768
Short name T351
Test name
Test status
Simulation time 85749339 ps
CPU time 1.47 seconds
Started Aug 04 04:29:13 PM PDT 24
Finished Aug 04 04:29:14 PM PDT 24
Peak memory 213684 kb
Host smart-04e7cb53-24d5-42e8-811b-f6cd0cd72f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875327768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3875327768
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3274225006
Short name T361
Test name
Test status
Simulation time 42051116474 ps
CPU time 31.59 seconds
Started Aug 04 04:29:09 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 205004 kb
Host smart-f0d35dcb-84cd-42d8-b021-55c5a102c0d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274225006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3274225006
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1137249881
Short name T309
Test name
Test status
Simulation time 112728389 ps
CPU time 0.69 seconds
Started Aug 04 04:29:11 PM PDT 24
Finished Aug 04 04:29:12 PM PDT 24
Peak memory 205176 kb
Host smart-07404b0c-7395-474e-9e06-8a1741bcd2e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137249881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1137249881
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2941408709
Short name T308
Test name
Test status
Simulation time 4323182240 ps
CPU time 12.73 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:29:30 PM PDT 24
Peak memory 205556 kb
Host smart-8d96f200-a982-4d7b-a944-ae9e2c6ee83f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941408709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2941408709
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1675921977
Short name T454
Test name
Test status
Simulation time 7386834024 ps
CPU time 7.09 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205468 kb
Host smart-8a505fd9-12a9-40c0-84cd-3bcb262f6cdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675921977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
675921977
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3994466807
Short name T408
Test name
Test status
Simulation time 235682450 ps
CPU time 0.91 seconds
Started Aug 04 04:29:11 PM PDT 24
Finished Aug 04 04:29:12 PM PDT 24
Peak memory 205180 kb
Host smart-c16be3c7-f169-4a6b-b87e-f429d5441280
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994466807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3994466807
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2618750764
Short name T389
Test name
Test status
Simulation time 14928793688 ps
CPU time 8.44 seconds
Started Aug 04 04:29:13 PM PDT 24
Finished Aug 04 04:29:22 PM PDT 24
Peak memory 205500 kb
Host smart-37648b27-16de-48bd-ac52-3e688e7a23b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618750764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2618750764
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1696210375
Short name T387
Test name
Test status
Simulation time 153786532 ps
CPU time 0.88 seconds
Started Aug 04 04:29:12 PM PDT 24
Finished Aug 04 04:29:13 PM PDT 24
Peak memory 205236 kb
Host smart-75b65864-d14c-4166-80f2-f19e716bc604
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696210375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1696210375
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.149193591
Short name T394
Test name
Test status
Simulation time 79714574 ps
CPU time 0.83 seconds
Started Aug 04 04:29:18 PM PDT 24
Finished Aug 04 04:29:19 PM PDT 24
Peak memory 205256 kb
Host smart-d7dd4a0f-b490-446a-b6dd-f1ccdcb8a5d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149193591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.149193591
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3207164761
Short name T330
Test name
Test status
Simulation time 124396105 ps
CPU time 0.68 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:29:56 PM PDT 24
Peak memory 205220 kb
Host smart-040264b3-1f25-4d9c-a585-c1e6b2bb74d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207164761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3207164761
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1099722991
Short name T96
Test name
Test status
Simulation time 457465598 ps
CPU time 7.39 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:43 PM PDT 24
Peak memory 205532 kb
Host smart-9450a77e-ef11-4c2e-9369-7f52cbc7b1e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099722991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1099722991
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3427293863
Short name T360
Test name
Test status
Simulation time 38013420007 ps
CPU time 31.64 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 221972 kb
Host smart-0e7972db-2cfc-4047-92ba-82d9da6f2002
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427293863 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3427293863
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2172969981
Short name T366
Test name
Test status
Simulation time 617174012 ps
CPU time 2.8 seconds
Started Aug 04 04:29:14 PM PDT 24
Finished Aug 04 04:29:17 PM PDT 24
Peak memory 213776 kb
Host smart-f7126910-f68c-4487-8522-ffc19517f238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172969981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2172969981
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1965218076
Short name T153
Test name
Test status
Simulation time 4309265729 ps
CPU time 18.07 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:54 PM PDT 24
Peak memory 213776 kb
Host smart-2509f609-2ed5-4f35-a39f-5db3e61b07ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965218076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1965218076
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.492687829
Short name T84
Test name
Test status
Simulation time 18030190678 ps
CPU time 80.35 seconds
Started Aug 04 04:29:29 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 213800 kb
Host smart-cc6edd44-9b86-4b7b-a8a4-c692c2ed6858
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492687829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.492687829
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1464173644
Short name T419
Test name
Test status
Simulation time 1487657154 ps
CPU time 53.43 seconds
Started Aug 04 04:29:29 PM PDT 24
Finished Aug 04 04:30:22 PM PDT 24
Peak memory 205444 kb
Host smart-82f59ca0-4ccc-45a8-be1e-822e2d8849b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464173644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1464173644
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1289265097
Short name T437
Test name
Test status
Simulation time 797878322 ps
CPU time 2.77 seconds
Started Aug 04 04:29:24 PM PDT 24
Finished Aug 04 04:29:27 PM PDT 24
Peak memory 213772 kb
Host smart-6bd786d3-d78c-41e8-a24b-2cdc140762ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289265097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1289265097
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2388868060
Short name T429
Test name
Test status
Simulation time 127050402 ps
CPU time 2.76 seconds
Started Aug 04 04:29:16 PM PDT 24
Finished Aug 04 04:29:18 PM PDT 24
Peak memory 218912 kb
Host smart-2346a8f8-0b25-4264-9e67-bc01c794b109
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388868060 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2388868060
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4201886273
Short name T332
Test name
Test status
Simulation time 346486093 ps
CPU time 2.27 seconds
Started Aug 04 04:29:19 PM PDT 24
Finished Aug 04 04:29:21 PM PDT 24
Peak memory 213636 kb
Host smart-f115a29d-5c50-4ce4-a1f6-5b798b295acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201886273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4201886273
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3795520955
Short name T348
Test name
Test status
Simulation time 72961288163 ps
CPU time 27.15 seconds
Started Aug 04 04:29:16 PM PDT 24
Finished Aug 04 04:29:43 PM PDT 24
Peak memory 205520 kb
Host smart-4bd5f9eb-b7e3-417c-8fe6-f6b56a5cf72b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795520955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3795520955
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.120606816
Short name T458
Test name
Test status
Simulation time 48403177777 ps
CPU time 131.61 seconds
Started Aug 04 04:29:14 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 205516 kb
Host smart-5abbbc03-726f-47cc-9a33-3c06ca27b45e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120606816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.120606816
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3249747672
Short name T326
Test name
Test status
Simulation time 2779821549 ps
CPU time 3.62 seconds
Started Aug 04 04:29:13 PM PDT 24
Finished Aug 04 04:29:17 PM PDT 24
Peak memory 205540 kb
Host smart-18489c4f-abf9-4d0c-b954-6400600b6046
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249747672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
249747672
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1337264018
Short name T441
Test name
Test status
Simulation time 569456961 ps
CPU time 0.99 seconds
Started Aug 04 04:29:28 PM PDT 24
Finished Aug 04 04:29:29 PM PDT 24
Peak memory 205196 kb
Host smart-b5c07e97-abc8-4641-8424-b25c766b242b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337264018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1337264018
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3621953441
Short name T382
Test name
Test status
Simulation time 5795791810 ps
CPU time 9.29 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 204968 kb
Host smart-0b85dabc-cde4-47bb-be38-2c454ede1c94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621953441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3621953441
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2352437414
Short name T336
Test name
Test status
Simulation time 305870492 ps
CPU time 0.87 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:37 PM PDT 24
Peak memory 205236 kb
Host smart-17135dd0-1249-4ab2-afb6-544a87ee3c6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352437414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2352437414
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4177084393
Short name T321
Test name
Test status
Simulation time 101037802 ps
CPU time 0.83 seconds
Started Aug 04 04:29:20 PM PDT 24
Finished Aug 04 04:29:21 PM PDT 24
Peak memory 205180 kb
Host smart-cf3f20f8-4384-4186-9731-4f20b10f73ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177084393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
177084393
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3774097726
Short name T449
Test name
Test status
Simulation time 43443410 ps
CPU time 0.72 seconds
Started Aug 04 04:29:28 PM PDT 24
Finished Aug 04 04:29:28 PM PDT 24
Peak memory 205260 kb
Host smart-a4db7dfb-d2f9-47f2-b820-31b86037ebb5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774097726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3774097726
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3135130129
Short name T393
Test name
Test status
Simulation time 86914944 ps
CPU time 0.67 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 205220 kb
Host smart-0c75cb55-0dd7-4fb4-91d7-0959e20adbc5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135130129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3135130129
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3734365448
Short name T411
Test name
Test status
Simulation time 375763206 ps
CPU time 4.52 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:39 PM PDT 24
Peak memory 205464 kb
Host smart-e12b3749-fc61-46d0-9606-cf00890233d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734365448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3734365448
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2001847114
Short name T52
Test name
Test status
Simulation time 51465684288 ps
CPU time 46.24 seconds
Started Aug 04 04:29:13 PM PDT 24
Finished Aug 04 04:30:00 PM PDT 24
Peak memory 222456 kb
Host smart-b11a57ca-ee82-4086-a88d-45103f248922
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001847114 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2001847114
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4104503153
Short name T431
Test name
Test status
Simulation time 97809275 ps
CPU time 2.62 seconds
Started Aug 04 04:29:31 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 213784 kb
Host smart-e0296e27-2b44-4fa2-918a-bf7e41d99661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104503153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4104503153
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.499048750
Short name T160
Test name
Test status
Simulation time 1092501652 ps
CPU time 16.9 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 213784 kb
Host smart-f3b286cf-a30c-4990-b5b6-0f0dcd9e290f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499048750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.499048750
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3942443161
Short name T345
Test name
Test status
Simulation time 232345773 ps
CPU time 3.79 seconds
Started Aug 04 04:30:05 PM PDT 24
Finished Aug 04 04:30:09 PM PDT 24
Peak memory 216616 kb
Host smart-c717677c-e4c1-4c09-8445-ebedb7eb004b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942443161 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3942443161
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4246588381
Short name T426
Test name
Test status
Simulation time 69842510 ps
CPU time 1.52 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:03 PM PDT 24
Peak memory 213620 kb
Host smart-ab60ecc6-b4e4-44c7-88d7-0873dfccaf58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246588381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4246588381
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.526678934
Short name T405
Test name
Test status
Simulation time 27675903914 ps
CPU time 79.58 seconds
Started Aug 04 04:29:45 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 205492 kb
Host smart-d476bd59-84cb-4352-b6a8-7a2fb2230935
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526678934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.526678934
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3774406804
Short name T407
Test name
Test status
Simulation time 1992407554 ps
CPU time 2.6 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:38 PM PDT 24
Peak memory 205412 kb
Host smart-df45ce10-c22d-4c8d-b5fa-c6663d0934f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774406804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3774406804
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4171116448
Short name T339
Test name
Test status
Simulation time 269008330 ps
CPU time 0.77 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 205164 kb
Host smart-9b7f179d-411d-4b65-b0ab-d47d24176137
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171116448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4171116448
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3811543476
Short name T107
Test name
Test status
Simulation time 293662299 ps
CPU time 6.9 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:42 PM PDT 24
Peak memory 205524 kb
Host smart-969c7d1f-a64a-4ab4-8070-27a46d4ff3a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811543476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3811543476
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3121573196
Short name T402
Test name
Test status
Simulation time 85967226 ps
CPU time 4.12 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:43 PM PDT 24
Peak memory 213784 kb
Host smart-18f59007-edc1-478c-b8c0-2a93f94bd781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121573196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3121573196
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.439696306
Short name T161
Test name
Test status
Simulation time 2080975296 ps
CPU time 9.64 seconds
Started Aug 04 04:29:41 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 213668 kb
Host smart-94edbcc9-c677-461d-960c-55fe31914196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439696306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.439696306
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1107668012
Short name T443
Test name
Test status
Simulation time 307943929 ps
CPU time 2.5 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:38 PM PDT 24
Peak memory 214128 kb
Host smart-6d8349d2-a1f0-454a-a036-344930449085
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107668012 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1107668012
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1041081768
Short name T102
Test name
Test status
Simulation time 268565221 ps
CPU time 1.71 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:39 PM PDT 24
Peak memory 213612 kb
Host smart-c21814dc-ea17-4330-8b8a-aa4b5d857772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041081768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1041081768
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3065928259
Short name T342
Test name
Test status
Simulation time 19093976486 ps
CPU time 16.31 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:51 PM PDT 24
Peak memory 205508 kb
Host smart-5476ced2-69c6-4b3b-a78d-8c90cddf81c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065928259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3065928259
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.43211919
Short name T317
Test name
Test status
Simulation time 4423184102 ps
CPU time 12.63 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:55 PM PDT 24
Peak memory 205540 kb
Host smart-2db6e21b-a303-4129-8cdd-af4268c7323b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43211919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.43211919
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1770079428
Short name T416
Test name
Test status
Simulation time 866566671 ps
CPU time 1.21 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:35 PM PDT 24
Peak memory 205204 kb
Host smart-3a33fded-4252-4c84-be25-2a5347c45022
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770079428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1770079428
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1627444710
Short name T95
Test name
Test status
Simulation time 635345886 ps
CPU time 6.67 seconds
Started Aug 04 04:29:42 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 205832 kb
Host smart-db58644f-202d-4bd9-9986-42f324ae307e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627444710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1627444710
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1628904751
Short name T359
Test name
Test status
Simulation time 343080896 ps
CPU time 4.63 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:29:38 PM PDT 24
Peak memory 213852 kb
Host smart-f9e072be-16dd-450c-9a12-dced6f11f514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628904751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1628904751
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2094746938
Short name T423
Test name
Test status
Simulation time 7685992272 ps
CPU time 26.36 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:30:04 PM PDT 24
Peak memory 213920 kb
Host smart-66beddec-d955-4c5d-8faf-99f3489575bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094746938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
094746938
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3052273349
Short name T112
Test name
Test status
Simulation time 159843726 ps
CPU time 2.57 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:04 PM PDT 24
Peak memory 217888 kb
Host smart-357d5056-addf-450c-be0e-13b8505add87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052273349 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3052273349
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2567337529
Short name T375
Test name
Test status
Simulation time 4216977652 ps
CPU time 12.49 seconds
Started Aug 04 04:29:57 PM PDT 24
Finished Aug 04 04:30:09 PM PDT 24
Peak memory 205468 kb
Host smart-b3817117-2600-4b5a-8684-07c65b89a84b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567337529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2567337529
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1233477352
Short name T373
Test name
Test status
Simulation time 4880207113 ps
CPU time 8.53 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:45 PM PDT 24
Peak memory 205496 kb
Host smart-ffacb0f1-7824-4936-8f93-aa2336bfc75d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233477352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1233477352
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1189751041
Short name T450
Test name
Test status
Simulation time 601911395 ps
CPU time 1.1 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:38 PM PDT 24
Peak memory 205188 kb
Host smart-297868d9-68c0-431e-8a57-ec7ff0c5cdd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189751041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1189751041
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1488040328
Short name T461
Test name
Test status
Simulation time 578114857 ps
CPU time 4.24 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 205556 kb
Host smart-1e74269d-1135-4739-96a8-161bf7dfefd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488040328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1488040328
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.164116869
Short name T413
Test name
Test status
Simulation time 151798078 ps
CPU time 4.56 seconds
Started Aug 04 04:29:52 PM PDT 24
Finished Aug 04 04:29:57 PM PDT 24
Peak memory 213836 kb
Host smart-99cdd8ad-fd9c-4651-b152-41a91ddb5358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164116869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.164116869
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1821230022
Short name T156
Test name
Test status
Simulation time 1389044020 ps
CPU time 16.39 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:20 PM PDT 24
Peak memory 213684 kb
Host smart-d3957902-1d79-44e5-a350-8a6d13fe32a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821230022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
821230022
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1285623597
Short name T464
Test name
Test status
Simulation time 389962411 ps
CPU time 3.79 seconds
Started Aug 04 04:29:54 PM PDT 24
Finished Aug 04 04:29:57 PM PDT 24
Peak memory 221824 kb
Host smart-e28c6dda-304f-49a0-bc0f-51fbac733c3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285623597 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1285623597
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2083188793
Short name T94
Test name
Test status
Simulation time 220972717 ps
CPU time 1.55 seconds
Started Aug 04 04:29:49 PM PDT 24
Finished Aug 04 04:29:51 PM PDT 24
Peak memory 213652 kb
Host smart-a03fbf17-a91e-4e9d-96fa-0db9ae1ba91d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083188793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2083188793
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1176646386
Short name T364
Test name
Test status
Simulation time 66075504 ps
CPU time 0.8 seconds
Started Aug 04 04:29:49 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 205212 kb
Host smart-882e3b23-960b-49e6-85ae-4119a761abc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176646386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1176646386
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1692251196
Short name T445
Test name
Test status
Simulation time 14681103260 ps
CPU time 21.07 seconds
Started Aug 04 04:29:59 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 205520 kb
Host smart-6372d19e-04a8-419e-8a80-821aecdd92a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692251196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1692251196
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3001429256
Short name T340
Test name
Test status
Simulation time 228943085 ps
CPU time 1.27 seconds
Started Aug 04 04:30:04 PM PDT 24
Finished Aug 04 04:30:05 PM PDT 24
Peak memory 205172 kb
Host smart-1467c18e-78be-4507-be8c-b2d7eadfe870
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001429256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3001429256
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1523336641
Short name T440
Test name
Test status
Simulation time 491832736 ps
CPU time 3.42 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:29:43 PM PDT 24
Peak memory 205544 kb
Host smart-f2fd5c7a-da5e-4126-87c5-af2f011d0765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523336641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1523336641
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2556556376
Short name T346
Test name
Test status
Simulation time 115953772 ps
CPU time 2.26 seconds
Started Aug 04 04:29:42 PM PDT 24
Finished Aug 04 04:29:45 PM PDT 24
Peak memory 213836 kb
Host smart-3e2da9df-d4d0-4503-a8c6-da8ad2b18ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556556376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2556556376
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4024928220
Short name T66
Test name
Test status
Simulation time 106546570 ps
CPU time 2.93 seconds
Started Aug 04 04:29:53 PM PDT 24
Finished Aug 04 04:29:56 PM PDT 24
Peak memory 219980 kb
Host smart-94999933-6a52-4999-9909-9a4a45476a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024928220 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4024928220
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.314970653
Short name T103
Test name
Test status
Simulation time 182284506 ps
CPU time 2.38 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:30:09 PM PDT 24
Peak memory 213712 kb
Host smart-28562640-efb0-47c1-92d2-25db8273f8e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314970653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.314970653
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1706195495
Short name T368
Test name
Test status
Simulation time 5567756603 ps
CPU time 5.08 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:30:01 PM PDT 24
Peak memory 205532 kb
Host smart-5a93dec8-f4b7-4df9-9932-ede8092337d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706195495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1706195495
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1605740665
Short name T435
Test name
Test status
Simulation time 2394934873 ps
CPU time 4.8 seconds
Started Aug 04 04:29:57 PM PDT 24
Finished Aug 04 04:30:02 PM PDT 24
Peak memory 205552 kb
Host smart-9c68433d-dc2c-4a83-abd9-5f82c11401d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605740665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1605740665
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3601316666
Short name T316
Test name
Test status
Simulation time 204381610 ps
CPU time 1.38 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 205220 kb
Host smart-197673a5-1265-4f84-8a36-5c846e1412cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601316666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3601316666
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1186774705
Short name T367
Test name
Test status
Simulation time 285572626 ps
CPU time 4.1 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 213812 kb
Host smart-dde66b6e-5245-4f6c-805e-9c10f9b29bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186774705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1186774705
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3915990978
Short name T422
Test name
Test status
Simulation time 1437110437 ps
CPU time 10.47 seconds
Started Aug 04 04:29:50 PM PDT 24
Finished Aug 04 04:30:00 PM PDT 24
Peak memory 213764 kb
Host smart-441ed7fd-a495-47df-8b3a-2058ce3fc1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915990978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
915990978
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1887305311
Short name T70
Test name
Test status
Simulation time 333994530 ps
CPU time 2.31 seconds
Started Aug 04 04:29:49 PM PDT 24
Finished Aug 04 04:29:52 PM PDT 24
Peak memory 218164 kb
Host smart-f7242533-1f4a-4d34-bc7b-40c9df91a170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887305311 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1887305311
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1724125347
Short name T418
Test name
Test status
Simulation time 111178858 ps
CPU time 1.68 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 213680 kb
Host smart-5e367565-e328-4d96-9265-0b1ed15872c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724125347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1724125347
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3538546313
Short name T313
Test name
Test status
Simulation time 16351184268 ps
CPU time 37.5 seconds
Started Aug 04 04:29:57 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 205436 kb
Host smart-a57d1440-1ceb-4872-a1cf-41fc29663cb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538546313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3538546313
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3596957040
Short name T398
Test name
Test status
Simulation time 8710530754 ps
CPU time 7.39 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 205536 kb
Host smart-9b93788d-ee5c-420d-9f18-6670f502a533
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596957040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3596957040
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3921958801
Short name T334
Test name
Test status
Simulation time 96693331 ps
CPU time 0.79 seconds
Started Aug 04 04:29:58 PM PDT 24
Finished Aug 04 04:29:59 PM PDT 24
Peak memory 205192 kb
Host smart-4766e611-bf1f-47c1-b47d-bc5d86de4100
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921958801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3921958801
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3729801146
Short name T90
Test name
Test status
Simulation time 372475347 ps
CPU time 6.65 seconds
Started Aug 04 04:29:43 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 205528 kb
Host smart-894a322f-7244-405b-ae25-ebc0989ffe84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729801146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3729801146
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.407466669
Short name T384
Test name
Test status
Simulation time 1032645691 ps
CPU time 6.34 seconds
Started Aug 04 04:29:47 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 213776 kb
Host smart-835c00a8-ee95-4d61-852d-e0aff6815396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407466669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.407466669
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.534707493
Short name T380
Test name
Test status
Simulation time 381416145 ps
CPU time 2.51 seconds
Started Aug 04 04:29:46 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 213836 kb
Host smart-9fafa221-868d-48eb-ad03-502bc9428c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534707493 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.534707493
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3635355365
Short name T105
Test name
Test status
Simulation time 158016782 ps
CPU time 2.17 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:38 PM PDT 24
Peak memory 213688 kb
Host smart-3f83bbfb-07ee-4298-9499-5c16618790b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635355365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3635355365
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1965974892
Short name T310
Test name
Test status
Simulation time 4890605868 ps
CPU time 15.19 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:54 PM PDT 24
Peak memory 204624 kb
Host smart-4d1f7488-daaf-4064-9e9a-064a3ce20153
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965974892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1965974892
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1993385568
Short name T399
Test name
Test status
Simulation time 4279424025 ps
CPU time 4.47 seconds
Started Aug 04 04:29:46 PM PDT 24
Finished Aug 04 04:29:51 PM PDT 24
Peak memory 205468 kb
Host smart-3cf496cd-0bc4-4c98-a0c2-f9c8da70b39c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993385568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1993385568
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1219609684
Short name T363
Test name
Test status
Simulation time 562798529 ps
CPU time 2.07 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 205192 kb
Host smart-d10950f7-f5f7-4b50-97f0-1e5308f24295
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219609684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1219609684
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.89692307
Short name T391
Test name
Test status
Simulation time 443227115 ps
CPU time 7.04 seconds
Started Aug 04 04:29:46 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 205508 kb
Host smart-357b41c8-f1d1-4512-984a-594e02860837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89692307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_c
sr_outstanding.89692307
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4134769524
Short name T447
Test name
Test status
Simulation time 154450425 ps
CPU time 2.88 seconds
Started Aug 04 04:29:57 PM PDT 24
Finished Aug 04 04:30:00 PM PDT 24
Peak memory 213820 kb
Host smart-013e99d5-4867-47e3-86cb-40b65a37ec71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134769524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.4134769524
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1506657473
Short name T377
Test name
Test status
Simulation time 17064393148 ps
CPU time 21.51 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 213880 kb
Host smart-3b3f238f-f514-4e29-9c03-7b9f2d8156c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506657473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
506657473
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2710711124
Short name T356
Test name
Test status
Simulation time 408102715 ps
CPU time 2.25 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:03 PM PDT 24
Peak memory 217600 kb
Host smart-f95ea405-9506-4b32-9709-592161dfb11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710711124 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2710711124
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1753411258
Short name T397
Test name
Test status
Simulation time 379964665 ps
CPU time 2.37 seconds
Started Aug 04 04:29:53 PM PDT 24
Finished Aug 04 04:30:00 PM PDT 24
Peak memory 213708 kb
Host smart-b15cc3ed-fe9c-47ef-bf83-251f6cb57561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753411258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1753411258
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.712072836
Short name T314
Test name
Test status
Simulation time 8923922921 ps
CPU time 24.59 seconds
Started Aug 04 04:29:51 PM PDT 24
Finished Aug 04 04:30:16 PM PDT 24
Peak memory 205448 kb
Host smart-6b17d3a3-be2c-4bc8-b7db-f8e4afbd8021
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712072836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.712072836
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2647346237
Short name T463
Test name
Test status
Simulation time 2256513520 ps
CPU time 6.61 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:43 PM PDT 24
Peak memory 205552 kb
Host smart-56df9e18-1af9-4bbb-ad13-f86ca06d52e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647346237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2647346237
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3929074226
Short name T460
Test name
Test status
Simulation time 357424210 ps
CPU time 1.03 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:37 PM PDT 24
Peak memory 205200 kb
Host smart-8257cac1-20c6-4e9e-8899-442fd64d0d66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929074226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3929074226
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1149796777
Short name T75
Test name
Test status
Simulation time 317465184 ps
CPU time 3.7 seconds
Started Aug 04 04:29:50 PM PDT 24
Finished Aug 04 04:29:54 PM PDT 24
Peak memory 205504 kb
Host smart-70d2238f-b02f-4008-99af-26e0059efb5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149796777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1149796777
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1874071054
Short name T465
Test name
Test status
Simulation time 2995301789 ps
CPU time 3.95 seconds
Started Aug 04 04:29:54 PM PDT 24
Finished Aug 04 04:29:58 PM PDT 24
Peak memory 213888 kb
Host smart-3e539467-3b02-46bb-9bb1-cc37d622cfb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874071054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1874071054
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4080871236
Short name T159
Test name
Test status
Simulation time 5108193123 ps
CPU time 28.5 seconds
Started Aug 04 04:30:00 PM PDT 24
Finished Aug 04 04:30:28 PM PDT 24
Peak memory 213884 kb
Host smart-de0c968a-6c66-4c8e-85a2-bd08aa251d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080871236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
080871236
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1753447177
Short name T420
Test name
Test status
Simulation time 733005236 ps
CPU time 3.53 seconds
Started Aug 04 04:29:43 PM PDT 24
Finished Aug 04 04:29:47 PM PDT 24
Peak memory 221900 kb
Host smart-af01282b-ff41-4a9a-affa-c6d26f22d42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753447177 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1753447177
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.706760133
Short name T81
Test name
Test status
Simulation time 243916972 ps
CPU time 2.67 seconds
Started Aug 04 04:29:47 PM PDT 24
Finished Aug 04 04:30:00 PM PDT 24
Peak memory 213712 kb
Host smart-992e3e94-213f-457f-9f3b-f6cd6dcd722e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706760133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.706760133
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4177143416
Short name T403
Test name
Test status
Simulation time 8080159449 ps
CPU time 8.44 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:12 PM PDT 24
Peak memory 205532 kb
Host smart-bec5ac2b-ccb3-47b5-9a13-4c66918d1586
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177143416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.4177143416
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.614226449
Short name T347
Test name
Test status
Simulation time 2259631534 ps
CPU time 2.91 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:29:58 PM PDT 24
Peak memory 205548 kb
Host smart-48655b10-206f-4e63-b61d-dfa8b143759f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614226449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.614226449
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.494436832
Short name T328
Test name
Test status
Simulation time 141876332 ps
CPU time 0.85 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:40 PM PDT 24
Peak memory 204264 kb
Host smart-924ecb63-143d-4c77-b37f-aafceb1e5bd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494436832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.494436832
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.39385564
Short name T78
Test name
Test status
Simulation time 1076786711 ps
CPU time 4.35 seconds
Started Aug 04 04:29:44 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 205472 kb
Host smart-9b7b7d7f-29b2-4677-ae71-4df22eba4be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39385564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_c
sr_outstanding.39385564
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3706013626
Short name T376
Test name
Test status
Simulation time 2998123456 ps
CPU time 4.27 seconds
Started Aug 04 04:29:58 PM PDT 24
Finished Aug 04 04:30:02 PM PDT 24
Peak memory 213912 kb
Host smart-e5b9556e-6c50-47d4-af19-c4da66f50c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706013626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3706013626
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2239435813
Short name T67
Test name
Test status
Simulation time 1772786875 ps
CPU time 9.5 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 213780 kb
Host smart-5120d21a-1fa4-4ef9-9930-d1d03a1ceb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239435813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
239435813
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2969274507
Short name T312
Test name
Test status
Simulation time 365452397 ps
CPU time 4.1 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:05 PM PDT 24
Peak memory 220468 kb
Host smart-cf93d361-5831-4758-b557-0488936d77a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969274507 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2969274507
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3228042874
Short name T343
Test name
Test status
Simulation time 80764248 ps
CPU time 1.54 seconds
Started Aug 04 04:29:49 PM PDT 24
Finished Aug 04 04:29:51 PM PDT 24
Peak memory 213624 kb
Host smart-12e802a4-ade4-4ebf-81f2-15538fd9c727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228042874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3228042874
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2388981251
Short name T404
Test name
Test status
Simulation time 4439613803 ps
CPU time 3.78 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:10 PM PDT 24
Peak memory 205436 kb
Host smart-622ecc33-0359-4f8c-a1c0-f7337d0c6a8e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388981251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2388981251
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2794504254
Short name T427
Test name
Test status
Simulation time 7140140879 ps
CPU time 10.63 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 205456 kb
Host smart-6a535102-d4de-4dfc-a70b-c55dce3b8497
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794504254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2794504254
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2631640150
Short name T355
Test name
Test status
Simulation time 351348848 ps
CPU time 0.92 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:37 PM PDT 24
Peak memory 205188 kb
Host smart-c87abf6f-c5bd-490b-b5d7-bd20829230a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631640150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2631640150
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.480537803
Short name T444
Test name
Test status
Simulation time 2297778952 ps
CPU time 4.2 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:47 PM PDT 24
Peak memory 205612 kb
Host smart-34e35fd8-031a-4f77-b5fe-98f5b0e5d052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480537803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.480537803
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2237315775
Short name T390
Test name
Test status
Simulation time 269171988 ps
CPU time 4.13 seconds
Started Aug 04 04:30:10 PM PDT 24
Finished Aug 04 04:30:14 PM PDT 24
Peak memory 213768 kb
Host smart-17a0e6d6-2e85-4823-9e92-fb5443d3b03f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237315775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2237315775
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1033425459
Short name T89
Test name
Test status
Simulation time 8596757200 ps
CPU time 33.37 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:30:11 PM PDT 24
Peak memory 205576 kb
Host smart-03ba1c4a-384c-40f5-9903-35b2274d9545
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033425459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1033425459
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1389636499
Short name T82
Test name
Test status
Simulation time 19686677481 ps
CPU time 67.3 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 213832 kb
Host smart-1c735465-48bd-4d9c-8fa5-e140ea120582
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389636499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1389636499
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2600108464
Short name T80
Test name
Test status
Simulation time 176364569 ps
CPU time 2.63 seconds
Started Aug 04 04:29:29 PM PDT 24
Finished Aug 04 04:29:32 PM PDT 24
Peak memory 213744 kb
Host smart-582ed8d0-a71b-417c-96c6-4c40a7ebd9ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600108464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2600108464
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2780261287
Short name T434
Test name
Test status
Simulation time 181023775 ps
CPU time 2.39 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:35 PM PDT 24
Peak memory 217448 kb
Host smart-3efda4e6-76d1-4960-bccd-3614ae334fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780261287 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2780261287
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3050022536
Short name T436
Test name
Test status
Simulation time 137098938 ps
CPU time 1.48 seconds
Started Aug 04 04:29:30 PM PDT 24
Finished Aug 04 04:29:32 PM PDT 24
Peak memory 213668 kb
Host smart-8a299255-ea02-49e0-bad1-d96df251205d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050022536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3050022536
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1996310336
Short name T381
Test name
Test status
Simulation time 60556200332 ps
CPU time 87.54 seconds
Started Aug 04 04:29:42 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 205508 kb
Host smart-59ff12df-1dbc-413f-95c5-6647b052bcfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996310336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1996310336
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1365381115
Short name T323
Test name
Test status
Simulation time 1615513186 ps
CPU time 2.17 seconds
Started Aug 04 04:29:28 PM PDT 24
Finished Aug 04 04:29:30 PM PDT 24
Peak memory 205336 kb
Host smart-0c9ee0d9-0921-4ecf-96c3-166add64b589
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365381115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1365381115
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2349548878
Short name T349
Test name
Test status
Simulation time 4575922281 ps
CPU time 4.1 seconds
Started Aug 04 04:29:31 PM PDT 24
Finished Aug 04 04:29:35 PM PDT 24
Peak memory 205560 kb
Host smart-b8255ab0-f8f3-4e5e-9e7d-e0d75d1d0756
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349548878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2349548878
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3841962886
Short name T353
Test name
Test status
Simulation time 3514323946 ps
CPU time 9.5 seconds
Started Aug 04 04:29:18 PM PDT 24
Finished Aug 04 04:29:27 PM PDT 24
Peak memory 205564 kb
Host smart-340105ca-733b-44e3-8eac-4d1047ee2e51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841962886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
841962886
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2717185724
Short name T401
Test name
Test status
Simulation time 1047478446 ps
CPU time 0.89 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:33 PM PDT 24
Peak memory 205180 kb
Host smart-6f6daec4-f28d-49bd-a25b-db3a4fcc8039
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717185724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2717185724
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1433390462
Short name T319
Test name
Test status
Simulation time 3677148780 ps
CPU time 6.55 seconds
Started Aug 04 04:29:16 PM PDT 24
Finished Aug 04 04:29:27 PM PDT 24
Peak memory 205504 kb
Host smart-3d0d4168-26af-4879-a544-541d228bd08f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433390462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1433390462
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.220551475
Short name T392
Test name
Test status
Simulation time 412491789 ps
CPU time 1.37 seconds
Started Aug 04 04:29:27 PM PDT 24
Finished Aug 04 04:29:28 PM PDT 24
Peak memory 205268 kb
Host smart-ff6983db-96ab-44f4-b013-dc2564922b24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220551475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.220551475
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1081525329
Short name T322
Test name
Test status
Simulation time 739469107 ps
CPU time 2.4 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:39 PM PDT 24
Peak memory 205220 kb
Host smart-3a1618df-66d6-4fc2-98d1-9be3cc9d9ede
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081525329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
081525329
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4007070990
Short name T365
Test name
Test status
Simulation time 47762853 ps
CPU time 0.82 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 205256 kb
Host smart-f91852e8-4261-48db-b6d3-e60b59a2361e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007070990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.4007070990
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1318542455
Short name T370
Test name
Test status
Simulation time 96993168 ps
CPU time 0.86 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 205128 kb
Host smart-be02ca1f-b97a-436e-8427-f05418c716f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318542455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1318542455
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.926186731
Short name T108
Test name
Test status
Simulation time 2033525930 ps
CPU time 4.04 seconds
Started Aug 04 04:29:48 PM PDT 24
Finished Aug 04 04:29:52 PM PDT 24
Peak memory 204876 kb
Host smart-87acb84d-70e9-4327-bca4-9db6d7dbf38c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926186731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.926186731
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2770252279
Short name T448
Test name
Test status
Simulation time 62844728792 ps
CPU time 355.62 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:35:32 PM PDT 24
Peak memory 221860 kb
Host smart-4a2f200c-8396-479a-a93d-9ac02a7f1493
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770252279 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2770252279
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.459719228
Short name T69
Test name
Test status
Simulation time 166893049 ps
CPU time 2.58 seconds
Started Aug 04 04:29:18 PM PDT 24
Finished Aug 04 04:29:20 PM PDT 24
Peak memory 213764 kb
Host smart-abd3ae70-6586-433a-b44b-31f3e01d0f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459719228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.459719228
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2887120901
Short name T152
Test name
Test status
Simulation time 647266018 ps
CPU time 9.19 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:29:26 PM PDT 24
Peak memory 213764 kb
Host smart-c10356d5-9a88-41f1-a19d-930302071471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887120901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2887120901
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3546296077
Short name T456
Test name
Test status
Simulation time 2483492151 ps
CPU time 25.8 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:30:02 PM PDT 24
Peak memory 205736 kb
Host smart-1980d404-890b-4de9-8c5b-5f927f1cccb9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546296077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3546296077
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.773913119
Short name T104
Test name
Test status
Simulation time 24375136434 ps
CPU time 41.6 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:30:20 PM PDT 24
Peak memory 205620 kb
Host smart-cecbf9d8-f3a2-4c83-844b-4547c6e71f0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773913119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.773913119
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2973467525
Short name T358
Test name
Test status
Simulation time 722760863 ps
CPU time 2.89 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 213692 kb
Host smart-7723149f-fc46-40ae-9fb9-495b8c7665ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973467525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2973467525
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2501348071
Short name T417
Test name
Test status
Simulation time 230846807 ps
CPU time 4.08 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:29:59 PM PDT 24
Peak memory 221948 kb
Host smart-59257dc2-ac6f-4c6e-a3b2-71653ea27605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501348071 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2501348071
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.926449186
Short name T100
Test name
Test status
Simulation time 130408046 ps
CPU time 2.36 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:29:20 PM PDT 24
Peak memory 213656 kb
Host smart-38fd5ad4-5ca4-4d20-97b0-c9e84289a4eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926449186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.926449186
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2353387784
Short name T311
Test name
Test status
Simulation time 48232768696 ps
CPU time 126.97 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:31:25 PM PDT 24
Peak memory 205544 kb
Host smart-da4f83ea-7e8b-49f6-94b1-af58b5a11406
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353387784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2353387784
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1699970556
Short name T452
Test name
Test status
Simulation time 3586275565 ps
CPU time 6.85 seconds
Started Aug 04 04:29:31 PM PDT 24
Finished Aug 04 04:29:37 PM PDT 24
Peak memory 205476 kb
Host smart-6b0934e8-0a9d-4df9-a73f-7f455e2b35f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699970556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1699970556
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3233353808
Short name T86
Test name
Test status
Simulation time 3984832595 ps
CPU time 11.19 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 205564 kb
Host smart-59b1fa8c-f1a3-4320-be52-7d758a6e63d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233353808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3233353808
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1060737144
Short name T337
Test name
Test status
Simulation time 11724724251 ps
CPU time 9.18 seconds
Started Aug 04 04:29:49 PM PDT 24
Finished Aug 04 04:29:58 PM PDT 24
Peak memory 205488 kb
Host smart-31c1e37d-de91-40b5-a1fa-a847fdaf4860
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060737144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
060737144
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.767359776
Short name T457
Test name
Test status
Simulation time 1112925080 ps
CPU time 0.97 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:40 PM PDT 24
Peak memory 205172 kb
Host smart-acbedd06-8028-4b0a-a8e9-4c15e4709dd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767359776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.767359776
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1274722325
Short name T415
Test name
Test status
Simulation time 7849067623 ps
CPU time 8.93 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 205428 kb
Host smart-569d737a-b3bf-4925-8aae-b64ea7d89dc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274722325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1274722325
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2934128947
Short name T329
Test name
Test status
Simulation time 103474550 ps
CPU time 0.9 seconds
Started Aug 04 04:29:54 PM PDT 24
Finished Aug 04 04:29:56 PM PDT 24
Peak memory 205268 kb
Host smart-56eaabcf-98b5-4b17-9538-ee7a8ea23d19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934128947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2934128947
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2114039395
Short name T357
Test name
Test status
Simulation time 259746271 ps
CPU time 0.86 seconds
Started Aug 04 04:29:17 PM PDT 24
Finished Aug 04 04:29:18 PM PDT 24
Peak memory 205208 kb
Host smart-b0d2d81d-fe4b-41e0-ac69-fa337b0c61cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114039395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
114039395
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.755515196
Short name T338
Test name
Test status
Simulation time 69431124 ps
CPU time 0.73 seconds
Started Aug 04 04:29:48 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 205272 kb
Host smart-0273b378-7e8a-4007-92e3-436960820eeb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755515196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.755515196
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4216350589
Short name T425
Test name
Test status
Simulation time 53180461 ps
CPU time 0.71 seconds
Started Aug 04 04:29:48 PM PDT 24
Finished Aug 04 04:29:49 PM PDT 24
Peak memory 205204 kb
Host smart-8df9bcab-16c7-4f32-8ab7-45f0f4a3fa46
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216350589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4216350589
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.525820810
Short name T428
Test name
Test status
Simulation time 240113587 ps
CPU time 4.13 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 205484 kb
Host smart-7077e521-041a-406b-a356-888d1599a678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525820810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.525820810
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1645892415
Short name T455
Test name
Test status
Simulation time 25539345566 ps
CPU time 74.56 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:30:58 PM PDT 24
Peak memory 221472 kb
Host smart-55c3ff26-38ff-4940-89cf-cf8a46ccc447
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645892415 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1645892415
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.16659887
Short name T438
Test name
Test status
Simulation time 228505361 ps
CPU time 2.81 seconds
Started Aug 04 04:29:30 PM PDT 24
Finished Aug 04 04:29:33 PM PDT 24
Peak memory 213824 kb
Host smart-f439d6d8-2c32-4fcd-a69e-0d47236eab39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.16659887
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.290893803
Short name T439
Test name
Test status
Simulation time 1235079503 ps
CPU time 17.46 seconds
Started Aug 04 04:29:16 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 213804 kb
Host smart-24c91c4d-e593-48f0-8902-66e62d884ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290893803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.290893803
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4136005848
Short name T414
Test name
Test status
Simulation time 2449747522 ps
CPU time 32.59 seconds
Started Aug 04 04:29:42 PM PDT 24
Finished Aug 04 04:30:15 PM PDT 24
Peak memory 214844 kb
Host smart-699ab236-ef95-4d6b-94e8-14c91e18dbb5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136005848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4136005848
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2730493596
Short name T396
Test name
Test status
Simulation time 40898689567 ps
CPU time 67.73 seconds
Started Aug 04 04:30:00 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 205636 kb
Host smart-136d8745-410d-4912-b4e1-4679fb20a6fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730493596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2730493596
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3451698602
Short name T76
Test name
Test status
Simulation time 441373512 ps
CPU time 3.22 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:39 PM PDT 24
Peak memory 213628 kb
Host smart-5192cc74-179a-4e37-98d7-191ae051758a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451698602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3451698602
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4220833705
Short name T352
Test name
Test status
Simulation time 125459549 ps
CPU time 2.75 seconds
Started Aug 04 04:29:30 PM PDT 24
Finished Aug 04 04:29:32 PM PDT 24
Peak memory 218420 kb
Host smart-ab963945-784a-4046-97a8-0184b4a81d1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220833705 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.4220833705
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1890315324
Short name T459
Test name
Test status
Simulation time 296142665 ps
CPU time 1.62 seconds
Started Aug 04 04:29:29 PM PDT 24
Finished Aug 04 04:29:31 PM PDT 24
Peak memory 213688 kb
Host smart-8941bd74-fb8e-46e3-bfea-401e18f00ccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890315324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1890315324
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1843601661
Short name T335
Test name
Test status
Simulation time 24512453601 ps
CPU time 58.02 seconds
Started Aug 04 04:29:57 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 205572 kb
Host smart-6a5c76f2-fec6-4064-aaf2-041a8c37a0d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843601661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1843601661
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2477565766
Short name T433
Test name
Test status
Simulation time 34649556522 ps
CPU time 13.55 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:48 PM PDT 24
Peak memory 205500 kb
Host smart-0fa36e8d-4155-4188-b06b-c8d7d6961569
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477565766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2477565766
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3342456732
Short name T87
Test name
Test status
Simulation time 3797092598 ps
CPU time 11.8 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:29:45 PM PDT 24
Peak memory 205568 kb
Host smart-01555423-7283-401d-bfe4-fc88cf5cb655
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342456732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3342456732
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.52415396
Short name T325
Test name
Test status
Simulation time 6277431754 ps
CPU time 17.78 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 205532 kb
Host smart-bf054b3e-99cb-4780-998e-2ae2867783cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52415396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.52415396
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1541875134
Short name T341
Test name
Test status
Simulation time 648064338 ps
CPU time 1.09 seconds
Started Aug 04 04:29:54 PM PDT 24
Finished Aug 04 04:29:55 PM PDT 24
Peak memory 205204 kb
Host smart-ca21d196-2051-430a-9039-bbc20f228f05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541875134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1541875134
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2541949846
Short name T442
Test name
Test status
Simulation time 15941285581 ps
CPU time 11.44 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:48 PM PDT 24
Peak memory 205484 kb
Host smart-2eb0deda-d6c4-4d04-9f62-efd6b1c06e47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541949846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2541949846
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3394445639
Short name T55
Test name
Test status
Simulation time 115815466 ps
CPU time 0.94 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:30:09 PM PDT 24
Peak memory 205292 kb
Host smart-08215104-869d-4310-9fdd-ade03f38cb53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394445639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3394445639
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2232510874
Short name T385
Test name
Test status
Simulation time 843592429 ps
CPU time 2.05 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 205148 kb
Host smart-b1288b9e-3860-40ae-9cda-1af528653193
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232510874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
232510874
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3251764554
Short name T453
Test name
Test status
Simulation time 44364013 ps
CPU time 0.7 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:35 PM PDT 24
Peak memory 205216 kb
Host smart-7f58cd65-0848-407c-92ab-24533183a8d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251764554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3251764554
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1063051649
Short name T400
Test name
Test status
Simulation time 71376957 ps
CPU time 0.68 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:33 PM PDT 24
Peak memory 205168 kb
Host smart-05da5c14-8e8d-42bc-b038-2a6e342eacb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063051649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1063051649
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2429877718
Short name T106
Test name
Test status
Simulation time 506896236 ps
CPU time 7.39 seconds
Started Aug 04 04:29:58 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 205476 kb
Host smart-e333bc02-3354-4fe5-9f39-38d82dd758c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429877718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2429877718
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3672432064
Short name T51
Test name
Test status
Simulation time 17141750809 ps
CPU time 43 seconds
Started Aug 04 04:29:29 PM PDT 24
Finished Aug 04 04:30:12 PM PDT 24
Peak memory 213880 kb
Host smart-6ad2fd4a-938d-4cad-991c-5e282eb5ee49
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672432064 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3672432064
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2412485101
Short name T327
Test name
Test status
Simulation time 587749223 ps
CPU time 5.73 seconds
Started Aug 04 04:29:47 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 221992 kb
Host smart-a4860ab0-7060-4f56-a9f5-dbabdde0010a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412485101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2412485101
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1913751940
Short name T371
Test name
Test status
Simulation time 1269371319 ps
CPU time 9.78 seconds
Started Aug 04 04:29:41 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 221344 kb
Host smart-fef601e2-711c-457b-b046-75a352a00e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913751940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1913751940
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3060364797
Short name T344
Test name
Test status
Simulation time 203739921 ps
CPU time 3.59 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:40 PM PDT 24
Peak memory 216504 kb
Host smart-e3bf01d4-855d-437d-9371-5296c9fa07e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060364797 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3060364797
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3783132718
Short name T79
Test name
Test status
Simulation time 325064914 ps
CPU time 1.52 seconds
Started Aug 04 04:29:31 PM PDT 24
Finished Aug 04 04:29:33 PM PDT 24
Peak memory 213624 kb
Host smart-114a7cfb-7bb2-4d81-8ffe-890b3fc4c0a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783132718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3783132718
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3334581643
Short name T386
Test name
Test status
Simulation time 83048145074 ps
CPU time 222.36 seconds
Started Aug 04 04:29:48 PM PDT 24
Finished Aug 04 04:33:31 PM PDT 24
Peak memory 204940 kb
Host smart-d35d7aad-e252-49a2-a987-0cd48f6bfb53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334581643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3334581643
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3610615298
Short name T369
Test name
Test status
Simulation time 2969400195 ps
CPU time 2.86 seconds
Started Aug 04 04:29:47 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 205548 kb
Host smart-023fb40d-2ede-4f2e-9ae9-9001638bc238
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610615298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
610615298
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3530022028
Short name T388
Test name
Test status
Simulation time 138421645 ps
CPU time 0.97 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:29:34 PM PDT 24
Peak memory 205152 kb
Host smart-16d3b178-e19d-4810-912f-adb0f5235272
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530022028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
530022028
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.599045951
Short name T109
Test name
Test status
Simulation time 174362027 ps
CPU time 3.69 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:20 PM PDT 24
Peak memory 205568 kb
Host smart-755d0f4c-df7c-4ff6-bcaa-1bdb64d52443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599045951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.599045951
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.402830596
Short name T410
Test name
Test status
Simulation time 79230996458 ps
CPU time 114.07 seconds
Started Aug 04 04:29:30 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 222096 kb
Host smart-95dabe88-4420-442d-b261-08391e0390e5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402830596 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.402830596
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1267182921
Short name T320
Test name
Test status
Simulation time 291528667 ps
CPU time 2.81 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:37 PM PDT 24
Peak memory 213828 kb
Host smart-c4de44db-0e85-4c15-84c4-b67d254d8e70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267182921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1267182921
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3446470783
Short name T151
Test name
Test status
Simulation time 2761747839 ps
CPU time 20.39 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 213832 kb
Host smart-28a1ba86-f1a8-4637-8de4-2692dc1ff5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446470783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3446470783
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.355806118
Short name T412
Test name
Test status
Simulation time 488689408 ps
CPU time 2.59 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:37 PM PDT 24
Peak memory 219644 kb
Host smart-c2f72e57-aca0-4f1e-ab36-99e51eff7d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355806118 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.355806118
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4123924314
Short name T432
Test name
Test status
Simulation time 102481680 ps
CPU time 2.12 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:39 PM PDT 24
Peak memory 213620 kb
Host smart-5e60f353-133a-4824-a538-928cd765711b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123924314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4123924314
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4040145789
Short name T409
Test name
Test status
Simulation time 51551377440 ps
CPU time 70.9 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 205512 kb
Host smart-474b4b7e-df05-46d8-aea4-f6788fa865b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040145789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.4040145789
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.561673656
Short name T378
Test name
Test status
Simulation time 1198862225 ps
CPU time 2.41 seconds
Started Aug 04 04:30:05 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 205416 kb
Host smart-c86a3d3b-14d5-4190-a98f-da0b9b2f30d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561673656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.561673656
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.303623583
Short name T379
Test name
Test status
Simulation time 102983712 ps
CPU time 0.8 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:36 PM PDT 24
Peak memory 205124 kb
Host smart-d3d897c8-b1f6-42ed-876e-f8987c8deb65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303623583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.303623583
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3444213064
Short name T451
Test name
Test status
Simulation time 1128398675 ps
CPU time 7.69 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:46 PM PDT 24
Peak memory 205464 kb
Host smart-71d89ab5-891a-4719-91e8-eb4401549482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444213064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3444213064
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2441955157
Short name T163
Test name
Test status
Simulation time 30790698359 ps
CPU time 31.47 seconds
Started Aug 04 04:29:22 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 222008 kb
Host smart-70ca66a0-687f-4855-8a66-8b73587ec52f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441955157 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2441955157
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4167136236
Short name T350
Test name
Test status
Simulation time 206824494 ps
CPU time 3.67 seconds
Started Aug 04 04:29:35 PM PDT 24
Finished Aug 04 04:29:39 PM PDT 24
Peak memory 213764 kb
Host smart-c676ff0d-653f-4cc3-a19c-debde146dab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167136236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4167136236
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3353372957
Short name T155
Test name
Test status
Simulation time 5599268918 ps
CPU time 17.45 seconds
Started Aug 04 04:29:46 PM PDT 24
Finished Aug 04 04:30:03 PM PDT 24
Peak memory 213800 kb
Host smart-67c72033-6a17-48a3-9d8c-86192991d319
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353372957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3353372957
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3779994374
Short name T324
Test name
Test status
Simulation time 164272039 ps
CPU time 2.6 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:42 PM PDT 24
Peak memory 221916 kb
Host smart-fdc870f8-42ac-4e0a-9a3d-434adab1e56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779994374 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3779994374
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.976987753
Short name T383
Test name
Test status
Simulation time 271880810 ps
CPU time 2.06 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:40 PM PDT 24
Peak memory 213736 kb
Host smart-b20d7649-e850-4f36-b14c-b2bd8adb5acb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976987753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.976987753
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1135495989
Short name T421
Test name
Test status
Simulation time 8421901374 ps
CPU time 14.24 seconds
Started Aug 04 04:29:32 PM PDT 24
Finished Aug 04 04:29:46 PM PDT 24
Peak memory 205500 kb
Host smart-5b025409-b186-42c3-8886-9b091bec8b5d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135495989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1135495989
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2009145800
Short name T318
Test name
Test status
Simulation time 14521629249 ps
CPU time 8.61 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 205512 kb
Host smart-4b176989-0f43-4932-9f0a-4999063c1793
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009145800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
009145800
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3619647040
Short name T54
Test name
Test status
Simulation time 397740204 ps
CPU time 1.61 seconds
Started Aug 04 04:29:57 PM PDT 24
Finished Aug 04 04:29:59 PM PDT 24
Peak memory 205172 kb
Host smart-b7c50a3f-f81f-4508-94be-8f953df7486a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619647040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
619647040
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2301447050
Short name T93
Test name
Test status
Simulation time 1455923964 ps
CPU time 4.76 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:42 PM PDT 24
Peak memory 205584 kb
Host smart-bafece3d-ae62-4b3d-bd77-c99ec36db3cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301447050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2301447050
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2182078227
Short name T165
Test name
Test status
Simulation time 53643416106 ps
CPU time 51.07 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 222500 kb
Host smart-67f81c40-af5a-4a86-b8c6-e68d9e3c8a70
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182078227 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2182078227
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3817451950
Short name T374
Test name
Test status
Simulation time 156163952 ps
CPU time 3.22 seconds
Started Aug 04 04:29:50 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 213808 kb
Host smart-47787d55-5587-4dc7-86c0-e4e3f93b1363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817451950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3817451950
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1024540121
Short name T462
Test name
Test status
Simulation time 642760473 ps
CPU time 3.62 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 219316 kb
Host smart-62fb6e63-8ac0-4661-b230-2e8a2a6e3308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024540121 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1024540121
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2025089309
Short name T99
Test name
Test status
Simulation time 213559708 ps
CPU time 2.43 seconds
Started Aug 04 04:29:52 PM PDT 24
Finished Aug 04 04:29:55 PM PDT 24
Peak memory 213632 kb
Host smart-729962d3-5e5d-4c9f-980a-da203d3018f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025089309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2025089309
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.907493185
Short name T362
Test name
Test status
Simulation time 4613769751 ps
CPU time 8.66 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:44 PM PDT 24
Peak memory 205532 kb
Host smart-722951cf-aa7d-4f9b-b7a3-58a0801bf5ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907493185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.907493185
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3178997739
Short name T395
Test name
Test status
Simulation time 8761747626 ps
CPU time 7.48 seconds
Started Aug 04 04:29:39 PM PDT 24
Finished Aug 04 04:29:47 PM PDT 24
Peak memory 205508 kb
Host smart-94bdd488-6550-4bc6-b4fc-e0253092891e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178997739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
178997739
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3737546852
Short name T446
Test name
Test status
Simulation time 321333887 ps
CPU time 1.42 seconds
Started Aug 04 04:29:42 PM PDT 24
Finished Aug 04 04:29:43 PM PDT 24
Peak memory 205200 kb
Host smart-ba8559e8-4e78-40fd-ae67-f322855289b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737546852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
737546852
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1853434531
Short name T98
Test name
Test status
Simulation time 530497203 ps
CPU time 4.44 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:42 PM PDT 24
Peak memory 205572 kb
Host smart-a2bf26d6-88f0-4d05-b83f-86b295181653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853434531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1853434531
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.290429114
Short name T333
Test name
Test status
Simulation time 178986465 ps
CPU time 4.28 seconds
Started Aug 04 04:29:37 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 213808 kb
Host smart-03ebe20f-fd01-4799-87f0-c1f21ed4bd8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290429114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.290429114
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3456571632
Short name T162
Test name
Test status
Simulation time 1529059934 ps
CPU time 10.35 seconds
Started Aug 04 04:29:40 PM PDT 24
Finished Aug 04 04:29:51 PM PDT 24
Peak memory 213784 kb
Host smart-f4769b39-47a9-495c-be91-11aa6da2cc49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456571632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3456571632
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2301108314
Short name T354
Test name
Test status
Simulation time 439848344 ps
CPU time 2.42 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:41 PM PDT 24
Peak memory 213792 kb
Host smart-6dfa9220-c4ec-4578-bccf-a9c780802045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301108314 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2301108314
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2188638753
Short name T372
Test name
Test status
Simulation time 61019097 ps
CPU time 1.52 seconds
Started Aug 04 04:30:00 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 213640 kb
Host smart-230d2be2-2c15-492e-a92f-06ef6c0a619d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188638753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2188638753
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2433841379
Short name T307
Test name
Test status
Simulation time 55817713393 ps
CPU time 97.7 seconds
Started Aug 04 04:29:33 PM PDT 24
Finished Aug 04 04:31:11 PM PDT 24
Peak memory 205480 kb
Host smart-7781c8f3-31b4-4dd2-abe4-d107aa5715e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433841379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2433841379
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.608732175
Short name T406
Test name
Test status
Simulation time 3674493092 ps
CPU time 10.66 seconds
Started Aug 04 04:29:34 PM PDT 24
Finished Aug 04 04:29:44 PM PDT 24
Peak memory 205508 kb
Host smart-ac523893-5be3-44f5-becf-5f8d6ad858de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608732175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.608732175
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1409937333
Short name T430
Test name
Test status
Simulation time 946304259 ps
CPU time 1.35 seconds
Started Aug 04 04:29:36 PM PDT 24
Finished Aug 04 04:29:38 PM PDT 24
Peak memory 205196 kb
Host smart-5412b7cc-f16a-4d31-af32-e0e1c852cc22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409937333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
409937333
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2855354883
Short name T77
Test name
Test status
Simulation time 594906859 ps
CPU time 4.26 seconds
Started Aug 04 04:29:45 PM PDT 24
Finished Aug 04 04:29:50 PM PDT 24
Peak memory 205472 kb
Host smart-00eb4b10-3116-4f58-bc08-c73265604dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855354883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2855354883
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.913610050
Short name T424
Test name
Test status
Simulation time 29216219367 ps
CPU time 34.05 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:30:12 PM PDT 24
Peak memory 222028 kb
Host smart-2388f142-d7bd-4a3d-b7e0-51a941f5a132
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913610050 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.913610050
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2711316035
Short name T331
Test name
Test status
Simulation time 657036473 ps
CPU time 4.59 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:30:00 PM PDT 24
Peak memory 213836 kb
Host smart-ddff629c-f5aa-4c38-ad17-aa3c0384fa59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711316035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2711316035
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1311898092
Short name T111
Test name
Test status
Simulation time 1168215624 ps
CPU time 10.38 seconds
Started Aug 04 04:29:38 PM PDT 24
Finished Aug 04 04:29:48 PM PDT 24
Peak memory 213672 kb
Host smart-89757816-1573-4b75-9b41-e328e5bb6f98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311898092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1311898092
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2101934785
Short name T169
Test name
Test status
Simulation time 63381318 ps
CPU time 0.71 seconds
Started Aug 04 04:29:55 PM PDT 24
Finished Aug 04 04:30:01 PM PDT 24
Peak memory 205112 kb
Host smart-08762464-3070-4a24-8687-57ec6f474952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101934785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2101934785
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.997430367
Short name T23
Test name
Test status
Simulation time 3174609171 ps
CPU time 4.02 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:10 PM PDT 24
Peak memory 213764 kb
Host smart-e317d93f-462f-4099-b932-6af00a03f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997430367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.997430367
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1102551822
Short name T257
Test name
Test status
Simulation time 1444707872 ps
CPU time 4.49 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:10 PM PDT 24
Peak memory 205136 kb
Host smart-94821d29-5d9a-4538-8f52-4fb1e529e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102551822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1102551822
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1725374802
Short name T5
Test name
Test status
Simulation time 193564406 ps
CPU time 1.24 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:02 PM PDT 24
Peak memory 205180 kb
Host smart-594a6333-7f48-4241-a1ec-0105b760bc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725374802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1725374802
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2883825406
Short name T32
Test name
Test status
Simulation time 751495257 ps
CPU time 1.29 seconds
Started Aug 04 04:30:04 PM PDT 24
Finished Aug 04 04:30:05 PM PDT 24
Peak memory 205104 kb
Host smart-f98f75c9-beea-45a4-a71d-aa7675ee15ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883825406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2883825406
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1703796125
Short name T137
Test name
Test status
Simulation time 373287728 ps
CPU time 0.8 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:03 PM PDT 24
Peak memory 205132 kb
Host smart-9f79f268-1277-4f8d-9a55-6f99b0001ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703796125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1703796125
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3157859919
Short name T231
Test name
Test status
Simulation time 260439242 ps
CPU time 0.92 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205168 kb
Host smart-957f682f-27b9-40de-b62d-73a36d9a5b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157859919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3157859919
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2194380959
Short name T209
Test name
Test status
Simulation time 32426090 ps
CPU time 0.86 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:05 PM PDT 24
Peak memory 215384 kb
Host smart-c00a0e5c-e705-4d03-b9c7-2c54dd848cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194380959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2194380959
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2104569644
Short name T149
Test name
Test status
Simulation time 4447653162 ps
CPU time 7.47 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:20 PM PDT 24
Peak memory 213840 kb
Host smart-a5515321-a715-4df3-b440-7f648af51122
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104569644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2104569644
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2243292880
Short name T189
Test name
Test status
Simulation time 1112575844 ps
CPU time 3.46 seconds
Started Aug 04 04:30:11 PM PDT 24
Finished Aug 04 04:30:15 PM PDT 24
Peak memory 205124 kb
Host smart-5c28e72d-4320-4fe5-b981-5031bd2e6c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243292880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2243292880
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.148473263
Short name T174
Test name
Test status
Simulation time 222217729 ps
CPU time 0.77 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 205048 kb
Host smart-bbcae71d-e3bd-4da5-ba94-4c808d4e29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148473263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.148473263
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1140342904
Short name T120
Test name
Test status
Simulation time 116913283 ps
CPU time 0.8 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 205172 kb
Host smart-7eaf2ab9-83d7-4d14-90a2-8da5f680c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140342904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1140342904
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1276272341
Short name T175
Test name
Test status
Simulation time 1316371057 ps
CPU time 1.93 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 203368 kb
Host smart-6253b0fd-ce20-4d7e-bbb9-f9c829d6766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276272341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1276272341
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1765269356
Short name T286
Test name
Test status
Simulation time 163016044 ps
CPU time 1.12 seconds
Started Aug 04 04:30:14 PM PDT 24
Finished Aug 04 04:30:15 PM PDT 24
Peak memory 205124 kb
Host smart-6d8ba1c5-2cb8-46ad-a04e-276a052928f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765269356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1765269356
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2676956049
Short name T242
Test name
Test status
Simulation time 124277830 ps
CPU time 1.01 seconds
Started Aug 04 04:30:11 PM PDT 24
Finished Aug 04 04:30:12 PM PDT 24
Peak memory 205076 kb
Host smart-2a2c9d8a-3e8d-4f6f-98c6-37e7bf089854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676956049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2676956049
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1525912702
Short name T191
Test name
Test status
Simulation time 143972814 ps
CPU time 0.81 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 205112 kb
Host smart-8290ce84-af72-4479-bd32-ddfa27cb7960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525912702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1525912702
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2862293896
Short name T274
Test name
Test status
Simulation time 2371452633 ps
CPU time 3.71 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 205224 kb
Host smart-8a6b8817-e6b0-4458-bf73-2cb82bb2798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862293896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2862293896
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.226627279
Short name T127
Test name
Test status
Simulation time 485999821 ps
CPU time 1.1 seconds
Started Aug 04 04:30:04 PM PDT 24
Finished Aug 04 04:30:05 PM PDT 24
Peak memory 213332 kb
Host smart-6f93d7c0-887a-451d-afbc-deeb60a085a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226627279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.226627279
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.652908612
Short name T303
Test name
Test status
Simulation time 306045500 ps
CPU time 0.93 seconds
Started Aug 04 04:30:15 PM PDT 24
Finished Aug 04 04:30:16 PM PDT 24
Peak memory 205148 kb
Host smart-2d3de80f-0666-46fc-acf7-938fad8ef424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652908612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.652908612
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1364855913
Short name T122
Test name
Test status
Simulation time 2081524645 ps
CPU time 5.94 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:09 PM PDT 24
Peak memory 205328 kb
Host smart-933ee256-71cf-4a25-b26d-4bfe7105c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364855913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1364855913
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1087023950
Short name T305
Test name
Test status
Simulation time 7992194830 ps
CPU time 23.22 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 205584 kb
Host smart-f2a6068f-e0e1-40d5-b9d5-f04bfb98c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087023950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1087023950
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1999940749
Short name T43
Test name
Test status
Simulation time 1478661624 ps
CPU time 2.72 seconds
Started Aug 04 04:30:04 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 228812 kb
Host smart-fc1470ed-67e5-42cb-9a89-061c6783f7ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999940749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1999940749
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.4130228955
Short name T192
Test name
Test status
Simulation time 1653848154 ps
CPU time 1.69 seconds
Started Aug 04 04:29:52 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 205136 kb
Host smart-bb2195cf-d413-4336-a19d-a6b425160b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130228955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4130228955
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3961162454
Short name T295
Test name
Test status
Simulation time 3843796626 ps
CPU time 2.71 seconds
Started Aug 04 04:29:58 PM PDT 24
Finished Aug 04 04:30:01 PM PDT 24
Peak memory 213664 kb
Host smart-894da416-9907-4854-bdc2-9eeeaef6f734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961162454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3961162454
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2594659440
Short name T50
Test name
Test status
Simulation time 8535031635 ps
CPU time 22.22 seconds
Started Aug 04 04:30:19 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 205456 kb
Host smart-22327156-c208-48bd-86e5-ea4bf377d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594659440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2594659440
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2608073161
Short name T42
Test name
Test status
Simulation time 460628323 ps
CPU time 0.82 seconds
Started Aug 04 04:30:00 PM PDT 24
Finished Aug 04 04:30:01 PM PDT 24
Peak memory 205196 kb
Host smart-20001128-4dc9-4707-87bf-350c43c5af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608073161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2608073161
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.177226528
Short name T183
Test name
Test status
Simulation time 77797520 ps
CPU time 0.82 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:03 PM PDT 24
Peak memory 205168 kb
Host smart-04b0d8b7-07e5-456e-8676-03d896e7292a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177226528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.177226528
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2685084886
Short name T171
Test name
Test status
Simulation time 7055313164 ps
CPU time 4.85 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 213876 kb
Host smart-8522a130-0b01-454e-b188-1c4630ed0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685084886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2685084886
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.235740187
Short name T11
Test name
Test status
Simulation time 2229849111 ps
CPU time 6.21 seconds
Started Aug 04 04:30:08 PM PDT 24
Finished Aug 04 04:30:14 PM PDT 24
Peak memory 205640 kb
Host smart-bd2ef973-86b4-41cb-8205-ef82436ebd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235740187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.235740187
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3625129714
Short name T253
Test name
Test status
Simulation time 295002177 ps
CPU time 0.97 seconds
Started Aug 04 04:30:16 PM PDT 24
Finished Aug 04 04:30:18 PM PDT 24
Peak memory 205136 kb
Host smart-b3a23b17-67c2-4cc4-9d30-652e4aea10ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625129714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3625129714
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1273706181
Short name T285
Test name
Test status
Simulation time 397334190 ps
CPU time 1.32 seconds
Started Aug 04 04:31:17 PM PDT 24
Finished Aug 04 04:31:19 PM PDT 24
Peak memory 205048 kb
Host smart-2495f761-b033-480e-9197-8ddb543c42a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273706181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1273706181
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.112322090
Short name T187
Test name
Test status
Simulation time 215572501 ps
CPU time 0.85 seconds
Started Aug 04 04:30:05 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 205152 kb
Host smart-a74018c8-d26b-4c55-aeb7-0f3eb0b642c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112322090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.112322090
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2470129818
Short name T117
Test name
Test status
Simulation time 43745755 ps
CPU time 0.97 seconds
Started Aug 04 04:30:19 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 215496 kb
Host smart-4f482c66-ee1f-404c-a904-ff299ef87328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470129818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2470129818
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1565789573
Short name T250
Test name
Test status
Simulation time 5600802371 ps
CPU time 3.17 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 205644 kb
Host smart-ad31e197-3385-4512-adfc-4d5b8fdc51a7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565789573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1565789573
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.1034508923
Short name T47
Test name
Test status
Simulation time 485383478 ps
CPU time 1.93 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:14 PM PDT 24
Peak memory 205132 kb
Host smart-9c5c67b3-24e4-4538-84a9-20a666385b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034508923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1034508923
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3865318728
Short name T194
Test name
Test status
Simulation time 237309953 ps
CPU time 1.27 seconds
Started Aug 04 04:30:15 PM PDT 24
Finished Aug 04 04:30:16 PM PDT 24
Peak memory 205100 kb
Host smart-ee35f2c2-e324-41cc-9483-3be7bc0d38bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865318728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3865318728
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2184487019
Short name T236
Test name
Test status
Simulation time 394718857 ps
CPU time 0.95 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 205192 kb
Host smart-8e010f9a-a3cb-4c84-97d4-79f9d7c3284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184487019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2184487019
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2346302461
Short name T293
Test name
Test status
Simulation time 553977177 ps
CPU time 1.1 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 205264 kb
Host smart-56305449-31bb-493f-92c8-fb68b520472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346302461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2346302461
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1338641621
Short name T188
Test name
Test status
Simulation time 2019361432 ps
CPU time 2.26 seconds
Started Aug 04 04:30:05 PM PDT 24
Finished Aug 04 04:30:08 PM PDT 24
Peak memory 205028 kb
Host smart-6053f0a6-2e20-4aa5-918b-7c9f54a2b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338641621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1338641621
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2663270403
Short name T258
Test name
Test status
Simulation time 460352570 ps
CPU time 1.01 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:30:08 PM PDT 24
Peak memory 205188 kb
Host smart-6b87d5ce-a805-4d27-b18f-4c4d07edab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663270403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2663270403
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3363661151
Short name T143
Test name
Test status
Simulation time 95229051 ps
CPU time 0.93 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 205160 kb
Host smart-7134590c-a693-40ce-85a9-8621f0066557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363661151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3363661151
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3013411737
Short name T276
Test name
Test status
Simulation time 122160090 ps
CPU time 0.97 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 205236 kb
Host smart-320114d2-1d6f-4190-907f-0fdeb9ca6c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013411737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3013411737
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3025328826
Short name T166
Test name
Test status
Simulation time 3378567023 ps
CPU time 1.69 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:08 PM PDT 24
Peak memory 205496 kb
Host smart-219a2cd9-1d90-4c5d-b387-b24d249fb734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025328826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3025328826
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2921899761
Short name T205
Test name
Test status
Simulation time 175890209 ps
CPU time 1.23 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:13 PM PDT 24
Peak memory 213376 kb
Host smart-cb6a88ba-42af-4fb3-b02b-4bdfb1b1c8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921899761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2921899761
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.833827591
Short name T227
Test name
Test status
Simulation time 265328304 ps
CPU time 0.86 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205172 kb
Host smart-c6997d9a-4552-4656-b6e7-317c5b21ccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833827591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.833827591
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3098942035
Short name T34
Test name
Test status
Simulation time 60669142 ps
CPU time 0.82 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:13 PM PDT 24
Peak memory 213380 kb
Host smart-dce8e1c4-0ce2-4dac-ac79-e69dcc1a94fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098942035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3098942035
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2060512127
Short name T193
Test name
Test status
Simulation time 3814266859 ps
CPU time 3.44 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 213820 kb
Host smart-f5c02ee8-cf2f-4c10-beb7-ed5440a41c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060512127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2060512127
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.323163481
Short name T44
Test name
Test status
Simulation time 870733468 ps
CPU time 1.7 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:22 PM PDT 24
Peak memory 229544 kb
Host smart-86d74a02-950a-4e30-9723-2f738e9c7639
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323163481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.323163481
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1656085329
Short name T228
Test name
Test status
Simulation time 580051888 ps
CPU time 1.64 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:26 PM PDT 24
Peak memory 205248 kb
Host smart-38901b61-f65b-424d-9020-027912751052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656085329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1656085329
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2436575018
Short name T64
Test name
Test status
Simulation time 311220465052 ps
CPU time 633.68 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:41:09 PM PDT 24
Peak memory 238372 kb
Host smart-9b94f322-1c6d-4b3b-9c91-1f9683b07e6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436575018 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2436575018
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2601785949
Short name T240
Test name
Test status
Simulation time 86447601 ps
CPU time 0.9 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 205100 kb
Host smart-57d2d545-d29e-44cc-9d07-64e48c03e235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601785949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2601785949
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2932066275
Short name T150
Test name
Test status
Simulation time 1935869271 ps
CPU time 6.27 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 205448 kb
Host smart-8e2fc012-82ec-4339-b062-41edfd5aa1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932066275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2932066275
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2572182733
Short name T172
Test name
Test status
Simulation time 1991634874 ps
CPU time 3.63 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 205520 kb
Host smart-acdc1302-58dd-487d-8282-510ccf08858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572182733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2572182733
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2898016713
Short name T247
Test name
Test status
Simulation time 6305049820 ps
CPU time 16.38 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:40 PM PDT 24
Peak memory 213812 kb
Host smart-e061d63d-298b-4a78-94dd-d9ab9ad365f2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898016713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2898016713
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1699078365
Short name T200
Test name
Test status
Simulation time 1805429726 ps
CPU time 3.81 seconds
Started Aug 04 04:30:15 PM PDT 24
Finished Aug 04 04:30:19 PM PDT 24
Peak memory 205520 kb
Host smart-f6e546ad-a5ba-4516-95bd-a17cebc01af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699078365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1699078365
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.928705463
Short name T185
Test name
Test status
Simulation time 7972679067 ps
CPU time 8.43 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 213672 kb
Host smart-b386b0ff-143b-430d-814d-171019d23ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928705463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.928705463
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3707612133
Short name T186
Test name
Test status
Simulation time 135242133 ps
CPU time 0.88 seconds
Started Aug 04 04:31:00 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 203152 kb
Host smart-7de753a7-9744-43cd-95f2-1756f1c5b7d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707612133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3707612133
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.345429358
Short name T62
Test name
Test status
Simulation time 7873973504 ps
CPU time 21.51 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:40 PM PDT 24
Peak memory 213740 kb
Host smart-3c240791-44d7-41d5-8030-1c89996106f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345429358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.345429358
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1623961504
Short name T223
Test name
Test status
Simulation time 3742068000 ps
CPU time 10.96 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 214936 kb
Host smart-1ae62cfe-a578-4438-bbc7-17e915bea57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623961504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1623961504
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1243170474
Short name T71
Test name
Test status
Simulation time 2249559471 ps
CPU time 2.81 seconds
Started Aug 04 04:31:29 PM PDT 24
Finished Aug 04 04:31:32 PM PDT 24
Peak memory 205640 kb
Host smart-744050c5-7109-4ef3-a718-717b374d6755
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243170474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1243170474
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.104866410
Short name T222
Test name
Test status
Simulation time 3458711915 ps
CPU time 2.22 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:25 PM PDT 24
Peak memory 213736 kb
Host smart-4f9ef203-a80a-43f9-8194-4a29e72fbc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104866410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.104866410
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.534126909
Short name T298
Test name
Test status
Simulation time 4155069894 ps
CPU time 3.66 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:20 PM PDT 24
Peak memory 213712 kb
Host smart-ab3d63ec-a4c4-4e0d-bb51-6d4161e1eb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534126909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.534126909
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2014185575
Short name T202
Test name
Test status
Simulation time 197423345 ps
CPU time 0.74 seconds
Started Aug 04 04:30:16 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 205180 kb
Host smart-cda2665f-7a9d-4b44-ad7a-e5420626bec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014185575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2014185575
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4101988843
Short name T294
Test name
Test status
Simulation time 22183437357 ps
CPU time 39.31 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 221956 kb
Host smart-1254e5e1-6f15-41ac-8ac4-e7830291db42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101988843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4101988843
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3384673928
Short name T280
Test name
Test status
Simulation time 2811785285 ps
CPU time 5.07 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 214512 kb
Host smart-72429dfd-be22-4f12-bc0a-0e84aa167053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384673928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3384673928
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.106004701
Short name T226
Test name
Test status
Simulation time 1066669850 ps
CPU time 2.02 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:27 PM PDT 24
Peak memory 205572 kb
Host smart-581a51fd-67e7-4d75-805b-a1752c31f716
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106004701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.106004701
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4182585301
Short name T246
Test name
Test status
Simulation time 2924607241 ps
CPU time 7.68 seconds
Started Aug 04 04:31:23 PM PDT 24
Finished Aug 04 04:31:31 PM PDT 24
Peak memory 205536 kb
Host smart-83f7d1fc-411d-4b1e-b042-0156498f691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182585301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4182585301
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3710963810
Short name T142
Test name
Test status
Simulation time 4401440667 ps
CPU time 12.68 seconds
Started Aug 04 04:30:19 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 213684 kb
Host smart-d7370f19-a241-4653-bf05-f05e5f93f8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710963810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3710963810
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3164534028
Short name T121
Test name
Test status
Simulation time 128804092 ps
CPU time 0.72 seconds
Started Aug 04 04:31:29 PM PDT 24
Finished Aug 04 04:31:30 PM PDT 24
Peak memory 205100 kb
Host smart-068a98d3-6cc8-4147-8986-11fd6bb8bd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164534028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3164534028
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.4272565287
Short name T234
Test name
Test status
Simulation time 26136314612 ps
CPU time 77.23 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:31:30 PM PDT 24
Peak memory 205640 kb
Host smart-f2464df5-9452-4a1a-846d-2a8684d23aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272565287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4272565287
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2367367688
Short name T224
Test name
Test status
Simulation time 4447632678 ps
CPU time 4.32 seconds
Started Aug 04 04:30:19 PM PDT 24
Finished Aug 04 04:30:23 PM PDT 24
Peak memory 214540 kb
Host smart-511ad26d-6a11-4651-b090-b8e306d62a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367367688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2367367688
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2266029518
Short name T168
Test name
Test status
Simulation time 2428358839 ps
CPU time 7.68 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 213892 kb
Host smart-693f8e45-7df2-42e4-9a3d-006f72e1e639
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266029518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2266029518
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.866721903
Short name T16
Test name
Test status
Simulation time 5394962880 ps
CPU time 9.1 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 203892 kb
Host smart-b702768f-c41b-49b0-b11c-baa163dc9a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866721903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.866721903
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3691356341
Short name T176
Test name
Test status
Simulation time 92622968 ps
CPU time 0.77 seconds
Started Aug 04 04:31:26 PM PDT 24
Finished Aug 04 04:31:27 PM PDT 24
Peak memory 205100 kb
Host smart-0f9e1599-aed3-4461-a59e-1093936e3530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691356341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3691356341
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2708957276
Short name T221
Test name
Test status
Simulation time 20284840973 ps
CPU time 35.47 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 213780 kb
Host smart-781feefb-6f83-4afb-8dea-0d9f79bed3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708957276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2708957276
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4031716151
Short name T262
Test name
Test status
Simulation time 4420762450 ps
CPU time 2.24 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:19 PM PDT 24
Peak memory 214916 kb
Host smart-e5833ff2-fbcd-4b1e-84ff-e28444a21e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031716151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4031716151
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3038634020
Short name T230
Test name
Test status
Simulation time 3680241740 ps
CPU time 6.22 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 213816 kb
Host smart-76b83f39-347a-44f2-acca-d43d0e881ab8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038634020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3038634020
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3594836017
Short name T213
Test name
Test status
Simulation time 2917555733 ps
CPU time 9.15 seconds
Started Aug 04 04:30:18 PM PDT 24
Finished Aug 04 04:30:28 PM PDT 24
Peak memory 213800 kb
Host smart-cf559f0d-e099-4e33-afc8-0b2b0753adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594836017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3594836017
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3671401865
Short name T131
Test name
Test status
Simulation time 1802772077 ps
CPU time 5.94 seconds
Started Aug 04 04:31:29 PM PDT 24
Finished Aug 04 04:31:35 PM PDT 24
Peak memory 213536 kb
Host smart-ee63bb79-d72e-436f-a994-2fc3ae7fa13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671401865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3671401865
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.136112295
Short name T167
Test name
Test status
Simulation time 48925223 ps
CPU time 0.75 seconds
Started Aug 04 04:30:16 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 205164 kb
Host smart-20fb9963-5432-40dc-836c-f3c7a2798e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136112295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.136112295
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.758868198
Short name T268
Test name
Test status
Simulation time 1008068945 ps
CPU time 1.15 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 213664 kb
Host smart-2444b767-e3c9-4142-957e-03012742f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758868198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.758868198
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.918738676
Short name T182
Test name
Test status
Simulation time 2861132262 ps
CPU time 5.32 seconds
Started Aug 04 04:31:32 PM PDT 24
Finished Aug 04 04:31:37 PM PDT 24
Peak memory 213804 kb
Host smart-73a34f0c-2f3e-4a60-bc29-d70e8c17e8be
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918738676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.918738676
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2537015002
Short name T249
Test name
Test status
Simulation time 8732799432 ps
CPU time 24.35 seconds
Started Aug 04 04:30:15 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 205596 kb
Host smart-80d551e7-b88b-4a9b-82f0-b235f463038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537015002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2537015002
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3438023841
Short name T135
Test name
Test status
Simulation time 4366055601 ps
CPU time 4.67 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 213584 kb
Host smart-d30a23d7-11c5-4e99-bedb-f1e34443bcab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438023841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3438023841
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1346142538
Short name T279
Test name
Test status
Simulation time 61733491 ps
CPU time 0.73 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:22 PM PDT 24
Peak memory 205200 kb
Host smart-fcf4bba2-78c0-48c8-8a9c-898699a3ee47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346142538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1346142538
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3557712535
Short name T141
Test name
Test status
Simulation time 4758938493 ps
CPU time 2.79 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 214780 kb
Host smart-bc9b955d-3b11-4f01-bac4-0de4b178c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557712535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3557712535
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3240896280
Short name T196
Test name
Test status
Simulation time 4637460235 ps
CPU time 13.07 seconds
Started Aug 04 04:30:10 PM PDT 24
Finished Aug 04 04:30:23 PM PDT 24
Peak memory 205628 kb
Host smart-cae20af3-3f04-40f8-9477-4d8b2fa419e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240896280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3240896280
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3377387686
Short name T300
Test name
Test status
Simulation time 2218029022 ps
CPU time 3.58 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 205632 kb
Host smart-fa691a8b-4b64-4a1d-8222-a5777ca972d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377387686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3377387686
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.3955402719
Short name T13
Test name
Test status
Simulation time 3194082755 ps
CPU time 6.06 seconds
Started Aug 04 04:30:17 PM PDT 24
Finished Aug 04 04:30:23 PM PDT 24
Peak memory 205464 kb
Host smart-44fd1c8e-6b60-4a02-9c46-785e1fd1be3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955402719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3955402719
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3866571440
Short name T179
Test name
Test status
Simulation time 69984390 ps
CPU time 0.74 seconds
Started Aug 04 04:30:36 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 205124 kb
Host smart-b17e75a2-14e9-4edb-8262-0c2d7c17e5f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866571440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3866571440
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2480154623
Short name T199
Test name
Test status
Simulation time 29622747394 ps
CPU time 34.33 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 213796 kb
Host smart-f3e6d014-38cf-4846-8661-54c0ed3192d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480154623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2480154623
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1766409492
Short name T273
Test name
Test status
Simulation time 5965656452 ps
CPU time 16.55 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 205608 kb
Host smart-3653f592-3f71-4907-9b09-a3ed7feb9df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766409492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1766409492
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2214264980
Short name T220
Test name
Test status
Simulation time 15461054168 ps
CPU time 42.25 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:31:13 PM PDT 24
Peak memory 222008 kb
Host smart-21d47a4d-d493-491d-8443-cb009775a134
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214264980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2214264980
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3848533511
Short name T178
Test name
Test status
Simulation time 4804043911 ps
CPU time 14.61 seconds
Started Aug 04 04:30:47 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 205708 kb
Host smart-dd178234-3f05-4d03-9218-4e4b152f2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848533511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3848533511
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.4022683575
Short name T21
Test name
Test status
Simulation time 3263955936 ps
CPU time 3.11 seconds
Started Aug 04 04:30:26 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 205444 kb
Host smart-41ea44e9-74f9-4b9a-a8a3-8eb9fe0da30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022683575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.4022683575
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2079348020
Short name T212
Test name
Test status
Simulation time 63429712 ps
CPU time 0.85 seconds
Started Aug 04 04:30:19 PM PDT 24
Finished Aug 04 04:30:19 PM PDT 24
Peak memory 205280 kb
Host smart-63388930-4fb8-4680-9c4c-5088a989817b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079348020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2079348020
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1733262400
Short name T197
Test name
Test status
Simulation time 9036978933 ps
CPU time 9.68 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 213828 kb
Host smart-46d17c49-1025-4753-9eee-45473a2f578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733262400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1733262400
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1345085653
Short name T204
Test name
Test status
Simulation time 3597261326 ps
CPU time 8 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 213888 kb
Host smart-dfba910c-ab13-44c2-bf4b-177d70556ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345085653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1345085653
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1878551942
Short name T275
Test name
Test status
Simulation time 728621542 ps
CPU time 2.85 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 205624 kb
Host smart-9b270e6d-3699-4780-a60d-df66bf927250
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878551942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1878551942
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2338066769
Short name T49
Test name
Test status
Simulation time 13987369683 ps
CPU time 17.77 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:51 PM PDT 24
Peak memory 205716 kb
Host smart-df19bea9-346b-482a-b7e5-4a30684234ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338066769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2338066769
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1203758351
Short name T251
Test name
Test status
Simulation time 45492542 ps
CPU time 0.79 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205168 kb
Host smart-cfe03fc1-b671-4440-9492-49780f48f84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203758351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1203758351
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3970628101
Short name T140
Test name
Test status
Simulation time 4762751791 ps
CPU time 6.13 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 205680 kb
Host smart-7bfb59c1-33f3-4498-b930-a20aea08f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970628101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3970628101
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3102471487
Short name T241
Test name
Test status
Simulation time 2564433062 ps
CPU time 5.45 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 205940 kb
Host smart-ff036c8b-8384-4a0c-bc45-dd549f87c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102471487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3102471487
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4154756186
Short name T216
Test name
Test status
Simulation time 2347905021 ps
CPU time 2.9 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 205580 kb
Host smart-4a082dce-427c-4645-a582-59a856c18c33
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4154756186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.4154756186
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.614914116
Short name T245
Test name
Test status
Simulation time 1246184422 ps
CPU time 4.25 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 205524 kb
Host smart-3e9cdaef-6378-4347-b89f-83d26e5d6e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614914116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.614914116
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3050475654
Short name T198
Test name
Test status
Simulation time 4955112454 ps
CPU time 3.95 seconds
Started Aug 04 04:30:26 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205472 kb
Host smart-3316d7cb-b2f4-444a-8ccf-ca5cd924a851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050475654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3050475654
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3818005797
Short name T270
Test name
Test status
Simulation time 244862626 ps
CPU time 0.68 seconds
Started Aug 04 04:30:04 PM PDT 24
Finished Aug 04 04:30:05 PM PDT 24
Peak memory 205104 kb
Host smart-2c031b5e-8940-4b25-b2fc-7207021aaefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818005797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3818005797
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3597449685
Short name T283
Test name
Test status
Simulation time 8434728711 ps
CPU time 20.53 seconds
Started Aug 04 04:30:20 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 205596 kb
Host smart-452b4e07-99ce-4854-abaf-b04090863c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597449685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3597449685
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3587341903
Short name T59
Test name
Test status
Simulation time 881515048 ps
CPU time 1.56 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:27 PM PDT 24
Peak memory 205496 kb
Host smart-a77f75b5-18d4-4edf-88a9-dac3063ea143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587341903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3587341903
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4250096153
Short name T232
Test name
Test status
Simulation time 5607919305 ps
CPU time 5.36 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 213904 kb
Host smart-bbbd2d63-a29d-4525-960d-18f64ca55f01
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250096153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.4250096153
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.4208927437
Short name T214
Test name
Test status
Simulation time 221347571 ps
CPU time 0.96 seconds
Started Aug 04 04:30:11 PM PDT 24
Finished Aug 04 04:30:12 PM PDT 24
Peak memory 205188 kb
Host smart-e8ba9ac6-474f-4a43-820c-0318ee6dc5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208927437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.4208927437
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3235222645
Short name T254
Test name
Test status
Simulation time 248100573 ps
CPU time 1.37 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205144 kb
Host smart-bbeb46be-aa62-4ef9-bb6d-9f6057755ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235222645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3235222645
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3303895740
Short name T180
Test name
Test status
Simulation time 1709173304 ps
CPU time 6.19 seconds
Started Aug 04 04:30:11 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 205484 kb
Host smart-73b9de1d-1981-47be-ad9d-114b8c0a761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303895740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3303895740
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2237901486
Short name T61
Test name
Test status
Simulation time 620424647 ps
CPU time 2.5 seconds
Started Aug 04 04:30:21 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 228864 kb
Host smart-56cded62-0730-4d2b-b826-79aaee20c914
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237901486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2237901486
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2793010632
Short name T136
Test name
Test status
Simulation time 4057754311 ps
CPU time 4.32 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:28 PM PDT 24
Peak memory 213700 kb
Host smart-a12f1a39-8405-4cbd-93b4-6da0f79315f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793010632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2793010632
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1269156097
Short name T40
Test name
Test status
Simulation time 35039153816 ps
CPU time 792.37 seconds
Started Aug 04 04:30:10 PM PDT 24
Finished Aug 04 04:43:23 PM PDT 24
Peak memory 238084 kb
Host smart-d054fac2-4025-4e2c-8343-4980eaa7a182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269156097 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1269156097
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1880285274
Short name T184
Test name
Test status
Simulation time 134136522 ps
CPU time 0.76 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 205100 kb
Host smart-9eb04bcb-98f5-4439-bcca-3e346c2c9805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880285274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1880285274
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2560645023
Short name T38
Test name
Test status
Simulation time 6037933207 ps
CPU time 11.68 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:43 PM PDT 24
Peak memory 213656 kb
Host smart-e73dea9b-713f-447d-9031-a8c0c8137a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560645023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2560645023
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.172451345
Short name T18
Test name
Test status
Simulation time 5908495292 ps
CPU time 10.03 seconds
Started Aug 04 04:31:26 PM PDT 24
Finished Aug 04 04:31:36 PM PDT 24
Peak memory 213552 kb
Host smart-279e93f4-3adc-4aa4-a843-8b08c54f1c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172451345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.172451345
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3625284681
Short name T260
Test name
Test status
Simulation time 52078913 ps
CPU time 0.75 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 205176 kb
Host smart-7283a7d9-28df-4204-b9a1-7fe767cec5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625284681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3625284681
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.244457050
Short name T133
Test name
Test status
Simulation time 2152226267 ps
CPU time 2.4 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205496 kb
Host smart-f39bbea5-b32a-4d59-803f-607987e3bf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244457050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.244457050
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2555119932
Short name T219
Test name
Test status
Simulation time 122300882 ps
CPU time 0.97 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 205172 kb
Host smart-dc86207e-206e-4a0d-86d2-caba0533ff55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555119932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2555119932
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3246471802
Short name T264
Test name
Test status
Simulation time 62920328 ps
CPU time 0.76 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205172 kb
Host smart-4351f4f2-6458-4255-8df5-972b48cbf308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246471802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3246471802
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.753482682
Short name T14
Test name
Test status
Simulation time 2555252730 ps
CPU time 7.74 seconds
Started Aug 04 04:31:25 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 205376 kb
Host smart-6e355e67-d9eb-4c5e-87d1-29b3b59ea113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753482682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.753482682
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2615252862
Short name T30
Test name
Test status
Simulation time 82046946 ps
CPU time 0.8 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 205164 kb
Host smart-73aa9093-5160-49c4-92f2-b0285c63e901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615252862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2615252862
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3895508933
Short name T248
Test name
Test status
Simulation time 8490925864 ps
CPU time 4.19 seconds
Started Aug 04 04:31:27 PM PDT 24
Finished Aug 04 04:31:32 PM PDT 24
Peak memory 213592 kb
Host smart-25200696-3dd8-4165-9c0d-4d02f2d2025d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895508933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3895508933
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1887680093
Short name T114
Test name
Test status
Simulation time 78378013 ps
CPU time 0.73 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 205172 kb
Host smart-f4275f42-fe90-42a7-b803-a43ec1e59b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887680093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1887680093
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2684392140
Short name T233
Test name
Test status
Simulation time 1198275764 ps
CPU time 2.59 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 205328 kb
Host smart-e3481c71-a0bb-4a3e-8827-4be085b7cf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684392140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2684392140
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2031592377
Short name T29
Test name
Test status
Simulation time 46238411 ps
CPU time 0.72 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 205156 kb
Host smart-0f5d252a-24ac-45f6-9def-5bd5bc4d5930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031592377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2031592377
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.632108105
Short name T146
Test name
Test status
Simulation time 4130878814 ps
CPU time 3.09 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 213456 kb
Host smart-db34635d-b22a-48f6-9841-7b268e278007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632108105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.632108105
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.147875205
Short name T119
Test name
Test status
Simulation time 58818677 ps
CPU time 0.8 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 205128 kb
Host smart-5d7a81fd-cadc-4f95-9f3f-9f445c814d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147875205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.147875205
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1523617999
Short name T19
Test name
Test status
Simulation time 3175832129 ps
CPU time 6.74 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 213336 kb
Host smart-20527ad9-22dd-4dab-949a-488610834900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523617999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1523617999
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2416251119
Short name T239
Test name
Test status
Simulation time 165402420 ps
CPU time 0.78 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 205188 kb
Host smart-7211a7c9-d30f-44dc-b5f4-8901bfbdf2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416251119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2416251119
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1799144821
Short name T4
Test name
Test status
Simulation time 5007854074 ps
CPU time 3.49 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 213716 kb
Host smart-9972ac74-cfeb-4003-a7db-6ee5eb3544a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799144821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1799144821
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3756410682
Short name T266
Test name
Test status
Simulation time 113801609 ps
CPU time 0.76 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:04 PM PDT 24
Peak memory 205140 kb
Host smart-3aa90c4d-0153-47ee-ad73-1fd0fec49a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756410682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3756410682
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1947396259
Short name T304
Test name
Test status
Simulation time 3433468250 ps
CPU time 2.9 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 214600 kb
Host smart-59a5ac77-df17-49b6-8ee8-20be1b5b615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947396259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1947396259
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.153957811
Short name T302
Test name
Test status
Simulation time 2181038448 ps
CPU time 6.68 seconds
Started Aug 04 04:30:01 PM PDT 24
Finished Aug 04 04:30:08 PM PDT 24
Peak memory 213852 kb
Host smart-7d20d976-c7d4-4f4e-bab1-c27f86bd0db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153957811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.153957811
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.150618786
Short name T269
Test name
Test status
Simulation time 3291832266 ps
CPU time 9.99 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:22 PM PDT 24
Peak memory 205512 kb
Host smart-f501e46d-aec3-4c38-a988-3dee2e902a88
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150618786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.150618786
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.15561922
Short name T145
Test name
Test status
Simulation time 555565892 ps
CPU time 1.84 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 205148 kb
Host smart-5d8c178b-ecf5-40de-b35c-f57ab188450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15561922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.15561922
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2018941190
Short name T181
Test name
Test status
Simulation time 246154569 ps
CPU time 1.1 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:03 PM PDT 24
Peak memory 205076 kb
Host smart-af9d17c8-a4fe-4bab-b49e-92a633dc751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018941190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2018941190
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1702439499
Short name T85
Test name
Test status
Simulation time 3981378352 ps
CPU time 5.63 seconds
Started Aug 04 04:30:10 PM PDT 24
Finished Aug 04 04:30:15 PM PDT 24
Peak memory 213864 kb
Host smart-ee6f42e7-5035-4751-ac44-3f42a2769e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702439499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1702439499
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1287486415
Short name T8
Test name
Test status
Simulation time 4065384057 ps
CPU time 6.46 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 213692 kb
Host smart-303343b5-0288-4f55-ac96-8d0a62a00daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287486415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1287486415
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.73136078
Short name T48
Test name
Test status
Simulation time 24347110945 ps
CPU time 334.54 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 229500 kb
Host smart-e7540522-d09a-43e2-82d8-08c0ea48176c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73136078 -assert nopostpr
oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.73136078
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3027250100
Short name T291
Test name
Test status
Simulation time 57275505 ps
CPU time 0.79 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 205200 kb
Host smart-46677df9-5a91-44d7-8c5f-bf2e37800997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027250100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3027250100
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1596488538
Short name T252
Test name
Test status
Simulation time 6653176851 ps
CPU time 5.97 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 213648 kb
Host smart-be148563-9de2-4e14-b99b-5a65a1cfb186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596488538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1596488538
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1699409539
Short name T170
Test name
Test status
Simulation time 174553047 ps
CPU time 0.79 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 205180 kb
Host smart-30c4b08d-7212-4211-9a76-2f2a9760adb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699409539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1699409539
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1637202391
Short name T130
Test name
Test status
Simulation time 2720113765 ps
CPU time 2.27 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 213724 kb
Host smart-d383dc10-09f8-4432-b849-eac5bd8483dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637202391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1637202391
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3835946427
Short name T118
Test name
Test status
Simulation time 98264092 ps
CPU time 0.87 seconds
Started Aug 04 04:30:48 PM PDT 24
Finished Aug 04 04:30:49 PM PDT 24
Peak memory 205196 kb
Host smart-73ae517d-9651-4317-8ab1-a8255f47bb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835946427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3835946427
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2881871148
Short name T125
Test name
Test status
Simulation time 2575056141 ps
CPU time 2.29 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 213640 kb
Host smart-88f952c4-96e6-44d4-ae31-aeac88c1f036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881871148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2881871148
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2633678447
Short name T73
Test name
Test status
Simulation time 152433895 ps
CPU time 0.8 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 205136 kb
Host smart-603d2d01-16d6-451e-b7af-66b1c58c8c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633678447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2633678447
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1882346218
Short name T3
Test name
Test status
Simulation time 8037021286 ps
CPU time 4.04 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 205596 kb
Host smart-cf97a464-8ce0-4618-af34-b3c12cee1b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882346218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1882346218
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3944324925
Short name T243
Test name
Test status
Simulation time 93548805 ps
CPU time 0.74 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 205160 kb
Host smart-30b1ad1c-2e45-4d6c-99df-6f61fa027151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944324925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3944324925
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3531309848
Short name T237
Test name
Test status
Simulation time 3702987429 ps
CPU time 1.89 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:30:26 PM PDT 24
Peak memory 213668 kb
Host smart-93c1f0c4-a800-4d67-96d5-c5cae344a2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531309848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3531309848
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2280694898
Short name T173
Test name
Test status
Simulation time 178766419 ps
CPU time 0.73 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 205188 kb
Host smart-650cabda-671d-4a16-ad3c-964e2b8eb436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280694898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2280694898
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.605053248
Short name T132
Test name
Test status
Simulation time 2723624116 ps
CPU time 2.82 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:28 PM PDT 24
Peak memory 213720 kb
Host smart-c3e7138a-7c61-46d5-93a1-fad32310cfc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605053248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.605053248
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2706982608
Short name T299
Test name
Test status
Simulation time 37550146 ps
CPU time 0.74 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 205152 kb
Host smart-e38f1141-71be-4deb-81bf-ea456490ed85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706982608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2706982608
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2214430976
Short name T207
Test name
Test status
Simulation time 5778592769 ps
CPU time 6.47 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:52 PM PDT 24
Peak memory 213608 kb
Host smart-429d347e-ec31-41f1-9094-25db336d4db8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214430976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2214430976
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2994159622
Short name T272
Test name
Test status
Simulation time 54937199 ps
CPU time 0.73 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 205200 kb
Host smart-e5170a86-e09e-443e-944a-2c1232495e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994159622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2994159622
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.4264769178
Short name T218
Test name
Test status
Simulation time 2659136592 ps
CPU time 4.23 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 213716 kb
Host smart-07b8f787-7062-43e6-b644-fe5e1011e936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264769178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4264769178
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.45750500
Short name T238
Test name
Test status
Simulation time 60388347 ps
CPU time 0.84 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 205172 kb
Host smart-bbd415a6-86fd-4995-9af3-5aa9228a6a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45750500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.45750500
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1497868310
Short name T296
Test name
Test status
Simulation time 4701133534 ps
CPU time 12.41 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 213692 kb
Host smart-bf4fafc2-c284-4442-bb3e-fdd39294d754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497868310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1497868310
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3619301262
Short name T210
Test name
Test status
Simulation time 38532170 ps
CPU time 0.77 seconds
Started Aug 04 04:30:40 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 205484 kb
Host smart-5511648b-50d5-489d-a0cc-bab459e5b9fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619301262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3619301262
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3641227662
Short name T271
Test name
Test status
Simulation time 3482145588 ps
CPU time 3.33 seconds
Started Aug 04 04:30:36 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 205460 kb
Host smart-80ef328b-b78c-479c-9955-cc2967f3246a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641227662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3641227662
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1608297904
Short name T110
Test name
Test status
Simulation time 112783720 ps
CPU time 0.83 seconds
Started Aug 04 04:30:23 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205172 kb
Host smart-4298f3bb-802a-4ff9-80a9-119245b5abd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608297904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1608297904
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3662061395
Short name T195
Test name
Test status
Simulation time 44556909743 ps
CPU time 62.37 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:31:44 PM PDT 24
Peak memory 218956 kb
Host smart-5eb35479-be3d-4510-8f3a-50a190449d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662061395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3662061395
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1348721071
Short name T215
Test name
Test status
Simulation time 1197783662 ps
CPU time 1.81 seconds
Started Aug 04 04:29:52 PM PDT 24
Finished Aug 04 04:29:53 PM PDT 24
Peak memory 205572 kb
Host smart-7522c210-f3ed-41da-b7a9-f3b151012b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348721071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1348721071
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3194646630
Short name T12
Test name
Test status
Simulation time 5459922734 ps
CPU time 4.94 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:17 PM PDT 24
Peak memory 213732 kb
Host smart-2c878acc-b6b9-44b6-9214-4fcaadb39fca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194646630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3194646630
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.53880384
Short name T287
Test name
Test status
Simulation time 363417419 ps
CPU time 1.54 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 205184 kb
Host smart-e096dd9b-6e81-413b-82f9-bcedc4247851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53880384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.53880384
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1099432653
Short name T115
Test name
Test status
Simulation time 182111702 ps
CPU time 1.18 seconds
Started Aug 04 04:30:22 PM PDT 24
Finished Aug 04 04:30:24 PM PDT 24
Peak memory 205144 kb
Host smart-6935b7ca-f3a3-4dcf-8484-eafb8e90d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099432653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1099432653
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2938728597
Short name T263
Test name
Test status
Simulation time 11374959625 ps
CPU time 14.44 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 205688 kb
Host smart-535c3bf3-b58f-4387-8d47-c72047bce558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938728597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2938728597
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1137608156
Short name T60
Test name
Test status
Simulation time 2258904919 ps
CPU time 6.48 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 229520 kb
Host smart-57ece18d-f441-4ac1-8d07-dda13d49ea43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137608156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1137608156
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2823466317
Short name T7
Test name
Test status
Simulation time 6065823016 ps
CPU time 9.74 seconds
Started Aug 04 04:30:00 PM PDT 24
Finished Aug 04 04:30:10 PM PDT 24
Peak memory 205472 kb
Host smart-f9668e64-6b7b-4912-b0ab-d0e12c75b269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823466317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2823466317
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3086108438
Short name T277
Test name
Test status
Simulation time 43214216 ps
CPU time 0.77 seconds
Started Aug 04 04:30:44 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 205172 kb
Host smart-a52927f6-d0dc-4e14-9d37-7e1991479cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086108438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3086108438
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2499180105
Short name T217
Test name
Test status
Simulation time 5311824375 ps
CPU time 16.74 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 213728 kb
Host smart-0cd19c29-0ec3-43f9-ac2b-5c31e8bf2baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499180105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2499180105
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.435566720
Short name T267
Test name
Test status
Simulation time 131375984 ps
CPU time 0.99 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 205204 kb
Host smart-534a0093-003f-4026-8504-dae372ba44d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435566720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.435566720
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.4030660240
Short name T256
Test name
Test status
Simulation time 4737624816 ps
CPU time 12.15 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:57 PM PDT 24
Peak memory 205496 kb
Host smart-193e1db1-5317-43ff-80e2-5035a78f1e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030660240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.4030660240
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.861007089
Short name T53
Test name
Test status
Simulation time 29599963 ps
CPU time 0.76 seconds
Started Aug 04 04:30:30 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 205188 kb
Host smart-d69bd003-ae47-43fa-bfa3-fbe9f10e3e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861007089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.861007089
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3726048516
Short name T138
Test name
Test status
Simulation time 4940146811 ps
CPU time 14.34 seconds
Started Aug 04 04:30:51 PM PDT 24
Finished Aug 04 04:31:05 PM PDT 24
Peak memory 219352 kb
Host smart-809707e8-b0f8-45b3-b6bc-e00adf8ceaf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726048516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3726048516
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3457832978
Short name T259
Test name
Test status
Simulation time 127725635 ps
CPU time 0.69 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 205276 kb
Host smart-59fd58d9-f6c5-4951-a8e0-b3a3f27a2822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457832978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3457832978
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1700867207
Short name T20
Test name
Test status
Simulation time 3773130182 ps
CPU time 11.06 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 213420 kb
Host smart-b5ebcdb2-1eaa-4ad0-b15a-db6db2353ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700867207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1700867207
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.489635110
Short name T288
Test name
Test status
Simulation time 88946310 ps
CPU time 0.73 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 205160 kb
Host smart-119fde1a-842c-4133-abed-25c88ce59658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489635110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.489635110
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.145694918
Short name T297
Test name
Test status
Simulation time 3835100055 ps
CPU time 4.46 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 213660 kb
Host smart-3237605b-78be-4bee-977e-70916cf4b629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145694918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.145694918
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.740417440
Short name T281
Test name
Test status
Simulation time 152687836 ps
CPU time 0.78 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:27 PM PDT 24
Peak memory 205216 kb
Host smart-6b02f890-02bd-4a70-95f7-8011ae3b1104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740417440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.740417440
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.938899545
Short name T39
Test name
Test status
Simulation time 6395493155 ps
CPU time 5.65 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 213696 kb
Host smart-fbb82521-d49f-4083-b9c0-0defda5ea760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938899545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.938899545
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.650123064
Short name T289
Test name
Test status
Simulation time 100175194 ps
CPU time 0.8 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 205484 kb
Host smart-15cad266-d008-4455-9d18-3cbe2eff0565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650123064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.650123064
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1047472810
Short name T292
Test name
Test status
Simulation time 3085706312 ps
CPU time 9.32 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 214008 kb
Host smart-2dac47ff-ee63-4308-b99f-98f9e7a12068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047472810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1047472810
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1725130571
Short name T261
Test name
Test status
Simulation time 119530629 ps
CPU time 0.87 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 205184 kb
Host smart-8cd40efd-bf23-4cdd-a6f1-8fffbb53ded4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725130571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1725130571
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1370444950
Short name T284
Test name
Test status
Simulation time 2418862815 ps
CPU time 6.16 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 213720 kb
Host smart-e69598e1-5fff-4417-83d3-67ccd6b29a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370444950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1370444950
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1206721482
Short name T301
Test name
Test status
Simulation time 113767559 ps
CPU time 0.99 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 205216 kb
Host smart-5d8f803f-fefb-4dec-b45e-cba70416ca67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206721482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1206721482
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.445155578
Short name T24
Test name
Test status
Simulation time 5076243286 ps
CPU time 7.97 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 213668 kb
Host smart-a6cbbfef-716a-4a3d-8e5f-bbd8c084872d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445155578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.445155578
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1441286866
Short name T208
Test name
Test status
Simulation time 33617650 ps
CPU time 0.72 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 205200 kb
Host smart-2846a1e6-fdcb-49f5-bdf7-2ac0cf72a375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441286866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1441286866
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1920601972
Short name T58
Test name
Test status
Simulation time 1094946780 ps
CPU time 3.85 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 205352 kb
Host smart-7ba3b5a2-933e-4ff7-9685-8ab3dbf20774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920601972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1920601972
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2628833314
Short name T72
Test name
Test status
Simulation time 102400341 ps
CPU time 0.69 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:04 PM PDT 24
Peak memory 205160 kb
Host smart-81225974-2ca9-4d22-842a-d82c88b1a5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628833314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2628833314
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3827517109
Short name T229
Test name
Test status
Simulation time 37382129193 ps
CPU time 63.97 seconds
Started Aug 04 04:30:24 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 219676 kb
Host smart-4510de7c-7b88-4947-a663-a7279040b94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827517109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3827517109
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2305081509
Short name T113
Test name
Test status
Simulation time 688234005 ps
CPU time 2.58 seconds
Started Aug 04 04:31:23 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 205552 kb
Host smart-bab0fcae-e027-4bad-a2d3-b4925e63b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305081509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2305081509
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.712963267
Short name T134
Test name
Test status
Simulation time 5382102721 ps
CPU time 3.88 seconds
Started Aug 04 04:30:03 PM PDT 24
Finished Aug 04 04:30:07 PM PDT 24
Peak memory 205680 kb
Host smart-ac5cb05c-d7c4-4130-a3cc-c1034b0fade9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712963267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.712963267
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.720771503
Short name T36
Test name
Test status
Simulation time 412736454 ps
CPU time 1.25 seconds
Started Aug 04 04:30:02 PM PDT 24
Finished Aug 04 04:30:04 PM PDT 24
Peak memory 205080 kb
Host smart-10c35a73-b368-4513-977e-a6c2e8b426e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720771503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.720771503
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.582004318
Short name T63
Test name
Test status
Simulation time 946408933 ps
CPU time 2.17 seconds
Started Aug 04 04:30:11 PM PDT 24
Finished Aug 04 04:30:13 PM PDT 24
Peak memory 205536 kb
Host smart-18f125d3-70cc-4e33-b15a-0ec404478209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582004318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.582004318
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1447203159
Short name T74
Test name
Test status
Simulation time 4330863083 ps
CPU time 2.54 seconds
Started Aug 04 04:31:25 PM PDT 24
Finished Aug 04 04:31:28 PM PDT 24
Peak memory 213592 kb
Host smart-52fa49dc-aa88-40e3-a0ab-d623f4db9e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447203159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1447203159
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3445968303
Short name T282
Test name
Test status
Simulation time 48632865 ps
CPU time 0.8 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 203240 kb
Host smart-7e704daf-d452-4270-82ed-487bcc670c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445968303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3445968303
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2899631094
Short name T27
Test name
Test status
Simulation time 23337341664 ps
CPU time 68.09 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 213860 kb
Host smart-fbe14d5c-4d06-4205-8851-ea46881e2a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899631094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2899631094
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1232420924
Short name T124
Test name
Test status
Simulation time 10030424551 ps
CPU time 3.55 seconds
Started Aug 04 04:30:10 PM PDT 24
Finished Aug 04 04:30:14 PM PDT 24
Peak memory 213852 kb
Host smart-f2a1b62c-d02b-4441-a792-aec502405f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232420924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1232420924
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2515540512
Short name T255
Test name
Test status
Simulation time 10268277918 ps
CPU time 14.95 seconds
Started Aug 04 04:31:28 PM PDT 24
Finished Aug 04 04:31:43 PM PDT 24
Peak memory 213812 kb
Host smart-dfd38342-959c-4379-a1e0-ec02ae2240ab
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515540512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2515540512
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.2155353317
Short name T265
Test name
Test status
Simulation time 421109099 ps
CPU time 1.82 seconds
Started Aug 04 04:30:04 PM PDT 24
Finished Aug 04 04:30:06 PM PDT 24
Peak memory 205172 kb
Host smart-e54d1ab0-8882-4d33-84ac-adc1c9c54177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155353317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2155353317
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3460604711
Short name T206
Test name
Test status
Simulation time 2708745638 ps
CPU time 9.07 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:14 PM PDT 24
Peak memory 212052 kb
Host smart-1d2a8533-10ad-4d4a-a72b-cb8b16edf272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460604711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3460604711
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3232346396
Short name T144
Test name
Test status
Simulation time 4424179782 ps
CPU time 10.99 seconds
Started Aug 04 04:30:19 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 205772 kb
Host smart-dce854ce-2ae8-4276-bcbd-8a4863e4eb4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232346396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3232346396
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1326272077
Short name T211
Test name
Test status
Simulation time 166519543 ps
CPU time 0.98 seconds
Started Aug 04 04:31:24 PM PDT 24
Finished Aug 04 04:31:26 PM PDT 24
Peak memory 205180 kb
Host smart-886fc005-0f45-4645-b2ed-108954cc79b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326272077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1326272077
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3788372810
Short name T45
Test name
Test status
Simulation time 5174471046 ps
CPU time 13.2 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:33 PM PDT 24
Peak memory 213704 kb
Host smart-2072003c-d28c-43eb-9a49-6bfa1e4ea41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788372810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3788372810
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2673452987
Short name T10
Test name
Test status
Simulation time 4065654661 ps
CPU time 4.47 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 204044 kb
Host smart-3b22724e-60f9-4f4f-afb9-2a58eff688aa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673452987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2673452987
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.1861808996
Short name T201
Test name
Test status
Simulation time 166183186 ps
CPU time 1.12 seconds
Started Aug 04 04:30:12 PM PDT 24
Finished Aug 04 04:30:14 PM PDT 24
Peak memory 205188 kb
Host smart-22251cb4-164e-43b4-abdc-dc6cbc211891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861808996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1861808996
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2339977480
Short name T177
Test name
Test status
Simulation time 6058191889 ps
CPU time 8.1 seconds
Started Aug 04 04:30:06 PM PDT 24
Finished Aug 04 04:30:14 PM PDT 24
Peak memory 205596 kb
Host smart-ce669498-2f8d-4b81-8056-c3170fd890b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339977480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2339977480
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1227036629
Short name T37
Test name
Test status
Simulation time 1813111316 ps
CPU time 6.12 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:19 PM PDT 24
Peak memory 213596 kb
Host smart-36b40a50-64e1-490d-9040-126bf7169330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227036629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1227036629
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3185177199
Short name T225
Test name
Test status
Simulation time 188400059 ps
CPU time 0.94 seconds
Started Aug 04 04:31:00 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 203280 kb
Host smart-b3487ec6-6732-4bbe-bf0f-0b5271159c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185177199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3185177199
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3963303877
Short name T244
Test name
Test status
Simulation time 2801317364 ps
CPU time 9.26 seconds
Started Aug 04 04:30:11 PM PDT 24
Finished Aug 04 04:30:25 PM PDT 24
Peak memory 205612 kb
Host smart-17624924-53de-40d9-a762-ec234f2e2548
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963303877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3963303877
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.4164547370
Short name T126
Test name
Test status
Simulation time 13424869242 ps
CPU time 19.38 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 213820 kb
Host smart-c6b78278-22da-45f3-a034-8e322466f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164547370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4164547370
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.833568932
Short name T190
Test name
Test status
Simulation time 5117010214 ps
CPU time 14.82 seconds
Started Aug 04 04:30:07 PM PDT 24
Finished Aug 04 04:30:22 PM PDT 24
Peak memory 205516 kb
Host smart-aab4e348-8727-469f-96b0-fdcb744c9507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833568932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.833568932
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1430507300
Short name T65
Test name
Test status
Simulation time 219757347281 ps
CPU time 876.18 seconds
Started Aug 04 04:30:18 PM PDT 24
Finished Aug 04 04:44:54 PM PDT 24
Peak memory 239624 kb
Host smart-c26f0def-b954-4644-b624-fdf535574ba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430507300 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1430507300
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2338431191
Short name T57
Test name
Test status
Simulation time 65783327 ps
CPU time 0.71 seconds
Started Aug 04 04:31:23 PM PDT 24
Finished Aug 04 04:31:24 PM PDT 24
Peak memory 205100 kb
Host smart-8eb7898b-9f13-480e-8c9a-14b07791a9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338431191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2338431191
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.530888215
Short name T235
Test name
Test status
Simulation time 4171297683 ps
CPU time 10.45 seconds
Started Aug 04 04:30:10 PM PDT 24
Finished Aug 04 04:30:21 PM PDT 24
Peak memory 215208 kb
Host smart-7a232ed1-c3f2-4aac-84fc-171dd76fd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530888215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.530888215
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3786922922
Short name T278
Test name
Test status
Simulation time 1616945039 ps
CPU time 1.95 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:15 PM PDT 24
Peak memory 205500 kb
Host smart-098b961d-6b2e-4206-a335-9ffd363f7726
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786922922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3786922922
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1004144803
Short name T290
Test name
Test status
Simulation time 946635372 ps
CPU time 2.51 seconds
Started Aug 04 04:30:13 PM PDT 24
Finished Aug 04 04:30:16 PM PDT 24
Peak memory 205496 kb
Host smart-eaf18972-aaec-45c3-8ce6-b1f572d61cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004144803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1004144803
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.156388844
Short name T306
Test name
Test status
Simulation time 8875799569 ps
CPU time 10.39 seconds
Started Aug 04 04:30:18 PM PDT 24
Finished Aug 04 04:30:28 PM PDT 24
Peak memory 213696 kb
Host smart-3b6f3b7d-1eaa-4b5f-8814-3ab950746446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156388844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.156388844
Directory /workspace/9.rv_dm_stress_all/latest
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