Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.68 96.18 84.92 89.91 73.75 88.33 98.53 54.13


Total test records in report: 464
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T84 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1664831258 Aug 05 04:55:48 PM PDT 24 Aug 05 04:55:51 PM PDT 24 164171981 ps
T65 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2180513181 Aug 05 04:55:21 PM PDT 24 Aug 05 04:55:36 PM PDT 24 9533400708 ps
T85 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.601170057 Aug 05 04:55:56 PM PDT 24 Aug 05 04:55:59 PM PDT 24 438495891 ps
T66 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3289436385 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:34 PM PDT 24 735660832 ps
T90 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2076143564 Aug 05 04:55:47 PM PDT 24 Aug 05 04:55:51 PM PDT 24 249671078 ps
T308 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3132612143 Aug 05 04:55:32 PM PDT 24 Aug 05 04:55:57 PM PDT 24 29602251940 ps
T309 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2862456534 Aug 05 04:55:32 PM PDT 24 Aug 05 04:56:03 PM PDT 24 9889781074 ps
T310 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.773412875 Aug 05 04:55:21 PM PDT 24 Aug 05 04:55:23 PM PDT 24 438165946 ps
T130 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1024365032 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:53 PM PDT 24 3761773807 ps
T91 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1061950686 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:29 PM PDT 24 1388095357 ps
T311 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4269751254 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:52 PM PDT 24 8448543630 ps
T62 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3308428536 Aug 05 04:55:41 PM PDT 24 Aug 05 04:58:57 PM PDT 24 60272095338 ps
T312 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1033904945 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:46 PM PDT 24 1697488572 ps
T131 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1163269623 Aug 05 04:55:53 PM PDT 24 Aug 05 04:56:13 PM PDT 24 1962896003 ps
T132 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3350872375 Aug 05 04:55:40 PM PDT 24 Aug 05 04:56:01 PM PDT 24 3869952604 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1569170850 Aug 05 04:55:13 PM PDT 24 Aug 05 04:55:14 PM PDT 24 49586737 ps
T314 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.379824033 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:31 PM PDT 24 4176478621 ps
T315 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1875324745 Aug 05 04:55:30 PM PDT 24 Aug 05 04:55:31 PM PDT 24 248400904 ps
T92 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2420693863 Aug 05 04:55:47 PM PDT 24 Aug 05 04:55:54 PM PDT 24 214657127 ps
T93 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.9542928 Aug 05 04:55:20 PM PDT 24 Aug 05 04:55:24 PM PDT 24 914203521 ps
T166 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.4250499429 Aug 05 04:55:26 PM PDT 24 Aug 05 04:58:12 PM PDT 24 17241751324 ps
T126 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1149814964 Aug 05 04:55:19 PM PDT 24 Aug 05 04:55:24 PM PDT 24 252672798 ps
T94 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4053616168 Aug 05 04:55:52 PM PDT 24 Aug 05 04:55:55 PM PDT 24 346056548 ps
T127 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2630270173 Aug 05 04:55:40 PM PDT 24 Aug 05 04:55:50 PM PDT 24 6629845836 ps
T95 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.182184820 Aug 05 04:55:49 PM PDT 24 Aug 05 04:55:57 PM PDT 24 1565765096 ps
T128 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3866479042 Aug 05 04:55:37 PM PDT 24 Aug 05 04:55:58 PM PDT 24 5113105657 ps
T316 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.547889084 Aug 05 04:55:39 PM PDT 24 Aug 05 04:55:41 PM PDT 24 339525482 ps
T317 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4040642971 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:50 PM PDT 24 247322533 ps
T318 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2471689607 Aug 05 04:55:31 PM PDT 24 Aug 05 04:55:32 PM PDT 24 124689002 ps
T129 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3546962367 Aug 05 04:55:47 PM PDT 24 Aug 05 04:55:51 PM PDT 24 171907233 ps
T96 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.842431304 Aug 05 04:55:40 PM PDT 24 Aug 05 04:56:18 PM PDT 24 3707909439 ps
T319 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3046757960 Aug 05 04:55:39 PM PDT 24 Aug 05 04:55:41 PM PDT 24 2510346377 ps
T97 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2494227596 Aug 05 04:55:37 PM PDT 24 Aug 05 04:55:40 PM PDT 24 196575576 ps
T320 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4204029911 Aug 05 04:55:59 PM PDT 24 Aug 05 04:56:05 PM PDT 24 7060292224 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2026451480 Aug 05 04:55:20 PM PDT 24 Aug 05 04:55:23 PM PDT 24 206863100 ps
T99 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.193170581 Aug 05 04:55:29 PM PDT 24 Aug 05 04:55:31 PM PDT 24 948117561 ps
T123 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.903759800 Aug 05 04:55:41 PM PDT 24 Aug 05 04:55:48 PM PDT 24 751559555 ps
T321 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3515175724 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:30 PM PDT 24 162698629 ps
T322 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2375685496 Aug 05 04:55:45 PM PDT 24 Aug 05 04:56:00 PM PDT 24 5314631637 ps
T323 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2738408043 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:48 PM PDT 24 212756812 ps
T324 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1566236497 Aug 05 04:55:35 PM PDT 24 Aug 05 04:55:39 PM PDT 24 165995970 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1576924347 Aug 05 04:55:34 PM PDT 24 Aug 05 04:56:08 PM PDT 24 36261331528 ps
T326 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3810423498 Aug 05 04:55:29 PM PDT 24 Aug 05 04:55:32 PM PDT 24 389936818 ps
T104 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.23281309 Aug 05 04:55:08 PM PDT 24 Aug 05 04:55:10 PM PDT 24 250846605 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3783366983 Aug 05 04:55:18 PM PDT 24 Aug 05 04:55:19 PM PDT 24 124280919 ps
T328 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2140117566 Aug 05 04:55:48 PM PDT 24 Aug 05 04:55:52 PM PDT 24 1487776863 ps
T329 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2172997054 Aug 05 04:55:28 PM PDT 24 Aug 05 04:55:29 PM PDT 24 1104459753 ps
T330 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2304008104 Aug 05 04:55:38 PM PDT 24 Aug 05 04:55:55 PM PDT 24 11947232301 ps
T331 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3727455023 Aug 05 04:55:20 PM PDT 24 Aug 05 04:59:21 PM PDT 24 96108381829 ps
T332 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3954591633 Aug 05 04:55:34 PM PDT 24 Aug 05 04:55:36 PM PDT 24 168092316 ps
T333 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3333251813 Aug 05 04:55:58 PM PDT 24 Aug 05 04:56:02 PM PDT 24 7131682489 ps
T334 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2640216480 Aug 05 04:55:54 PM PDT 24 Aug 05 04:56:01 PM PDT 24 2538045424 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2659993852 Aug 05 04:55:16 PM PDT 24 Aug 05 04:55:23 PM PDT 24 10612006756 ps
T336 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.767656322 Aug 05 04:55:53 PM PDT 24 Aug 05 04:56:06 PM PDT 24 5135507923 ps
T337 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4227619396 Aug 05 04:55:51 PM PDT 24 Aug 05 04:55:53 PM PDT 24 1145614511 ps
T338 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3777236036 Aug 05 04:55:40 PM PDT 24 Aug 05 04:55:41 PM PDT 24 187812425 ps
T105 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4289342933 Aug 05 04:55:13 PM PDT 24 Aug 05 04:55:40 PM PDT 24 749889722 ps
T106 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.123322189 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:34 PM PDT 24 674473129 ps
T159 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1300349787 Aug 05 04:55:34 PM PDT 24 Aug 05 04:55:53 PM PDT 24 3971956100 ps
T339 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.324603630 Aug 05 04:55:47 PM PDT 24 Aug 05 04:55:48 PM PDT 24 296976054 ps
T340 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3759893033 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:47 PM PDT 24 626817562 ps
T341 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3369577375 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:48 PM PDT 24 170607256 ps
T107 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2515106 Aug 05 04:55:26 PM PDT 24 Aug 05 04:55:34 PM PDT 24 1101594709 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2356717358 Aug 05 04:55:27 PM PDT 24 Aug 05 04:56:36 PM PDT 24 44138063588 ps
T108 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3216116300 Aug 05 04:55:17 PM PDT 24 Aug 05 04:56:22 PM PDT 24 3616051630 ps
T343 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1450648987 Aug 05 04:55:34 PM PDT 24 Aug 05 04:55:35 PM PDT 24 128304931 ps
T344 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.200442539 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:47 PM PDT 24 122706004 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1998484588 Aug 05 04:55:32 PM PDT 24 Aug 05 04:55:33 PM PDT 24 124623356 ps
T346 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1141460567 Aug 05 04:55:28 PM PDT 24 Aug 05 04:55:31 PM PDT 24 235665078 ps
T347 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3419286102 Aug 05 04:55:56 PM PDT 24 Aug 05 04:55:58 PM PDT 24 630976821 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3593929390 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:54 PM PDT 24 14038899602 ps
T349 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4205641101 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:46 PM PDT 24 1018924950 ps
T350 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.379355523 Aug 05 04:55:32 PM PDT 24 Aug 05 04:55:33 PM PDT 24 42379898 ps
T109 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2234880215 Aug 05 04:55:22 PM PDT 24 Aug 05 04:57:48 PM PDT 24 45528447893 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.821535645 Aug 05 04:55:35 PM PDT 24 Aug 05 04:55:49 PM PDT 24 5338062970 ps
T352 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3037155645 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:56 PM PDT 24 293866266 ps
T353 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.334222951 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:47 PM PDT 24 87669360 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2255662209 Aug 05 04:55:30 PM PDT 24 Aug 05 04:55:49 PM PDT 24 21182955641 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2253650537 Aug 05 04:55:24 PM PDT 24 Aug 05 04:55:28 PM PDT 24 998641077 ps
T356 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.857776975 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:31 PM PDT 24 5726656301 ps
T115 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3803705703 Aug 05 04:55:50 PM PDT 24 Aug 05 04:55:52 PM PDT 24 393436304 ps
T357 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3426528549 Aug 05 04:55:34 PM PDT 24 Aug 05 04:55:54 PM PDT 24 11851396806 ps
T156 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1440192883 Aug 05 04:55:48 PM PDT 24 Aug 05 04:56:10 PM PDT 24 2125128588 ps
T358 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2870954250 Aug 05 04:55:22 PM PDT 24 Aug 05 04:57:53 PM PDT 24 27801527921 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4142396347 Aug 05 04:55:38 PM PDT 24 Aug 05 04:55:39 PM PDT 24 949658915 ps
T360 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1771688581 Aug 05 04:55:24 PM PDT 24 Aug 05 04:55:25 PM PDT 24 384114977 ps
T361 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3116840429 Aug 05 04:55:15 PM PDT 24 Aug 05 04:56:14 PM PDT 24 40647249153 ps
T362 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2327972694 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:52 PM PDT 24 3363748323 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2455426775 Aug 05 04:55:20 PM PDT 24 Aug 05 04:55:25 PM PDT 24 4751816979 ps
T364 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2251106701 Aug 05 04:55:54 PM PDT 24 Aug 05 04:56:10 PM PDT 24 21876147293 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3803493339 Aug 05 04:55:30 PM PDT 24 Aug 05 04:55:34 PM PDT 24 1100713349 ps
T110 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2523635415 Aug 05 04:55:39 PM PDT 24 Aug 05 04:55:41 PM PDT 24 149631060 ps
T366 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1875062647 Aug 05 04:55:39 PM PDT 24 Aug 05 04:55:42 PM PDT 24 1533037530 ps
T124 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.406469680 Aug 05 04:55:39 PM PDT 24 Aug 05 04:55:46 PM PDT 24 288313611 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2537435887 Aug 05 04:55:35 PM PDT 24 Aug 05 04:55:37 PM PDT 24 683545923 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1506192338 Aug 05 04:55:26 PM PDT 24 Aug 05 04:56:00 PM PDT 24 4949115951 ps
T111 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1920985369 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:48 PM PDT 24 337456970 ps
T369 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.678139185 Aug 05 04:55:40 PM PDT 24 Aug 05 04:55:42 PM PDT 24 335749803 ps
T370 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4286757116 Aug 05 04:55:58 PM PDT 24 Aug 05 04:56:02 PM PDT 24 246414165 ps
T371 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3244417595 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:46 PM PDT 24 577391905 ps
T112 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3759728927 Aug 05 04:55:25 PM PDT 24 Aug 05 04:56:41 PM PDT 24 20714460872 ps
T157 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1628838022 Aug 05 04:55:15 PM PDT 24 Aug 05 04:55:37 PM PDT 24 2607966978 ps
T372 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.377804543 Aug 05 04:55:58 PM PDT 24 Aug 05 04:56:01 PM PDT 24 143776336 ps
T373 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1449723563 Aug 05 04:55:17 PM PDT 24 Aug 05 04:55:25 PM PDT 24 2710023680 ps
T113 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1634635098 Aug 05 04:55:26 PM PDT 24 Aug 05 04:56:41 PM PDT 24 3520946184 ps
T374 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2660353893 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:50 PM PDT 24 289542124 ps
T162 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4067569206 Aug 05 04:55:37 PM PDT 24 Aug 05 04:56:01 PM PDT 24 5767619365 ps
T375 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2297361479 Aug 05 04:55:56 PM PDT 24 Aug 05 04:56:00 PM PDT 24 1344305063 ps
T376 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.278910139 Aug 05 04:55:33 PM PDT 24 Aug 05 04:55:34 PM PDT 24 171917598 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1882132023 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:37 PM PDT 24 104675972 ps
T378 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3567000560 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:32 PM PDT 24 105956957 ps
T379 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2680725603 Aug 05 04:55:26 PM PDT 24 Aug 05 04:58:04 PM PDT 24 219950149197 ps
T114 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3058088320 Aug 05 04:55:24 PM PDT 24 Aug 05 04:56:46 PM PDT 24 4708676949 ps
T380 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3140821634 Aug 05 04:55:58 PM PDT 24 Aug 05 04:56:00 PM PDT 24 54449988 ps
T381 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3241481126 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:44 PM PDT 24 126535674 ps
T382 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3627065859 Aug 05 04:55:51 PM PDT 24 Aug 05 04:55:55 PM PDT 24 672982142 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2375715335 Aug 05 04:55:32 PM PDT 24 Aug 05 04:55:41 PM PDT 24 2373041352 ps
T384 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.548990513 Aug 05 04:55:30 PM PDT 24 Aug 05 04:55:31 PM PDT 24 295027522 ps
T385 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.954311088 Aug 05 04:55:55 PM PDT 24 Aug 05 04:55:57 PM PDT 24 296630048 ps
T116 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3366507002 Aug 05 04:55:32 PM PDT 24 Aug 05 04:55:35 PM PDT 24 193072158 ps
T386 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3299420990 Aug 05 04:55:42 PM PDT 24 Aug 05 04:57:56 PM PDT 24 40546035212 ps
T387 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3018544014 Aug 05 04:55:45 PM PDT 24 Aug 05 04:56:05 PM PDT 24 14313275021 ps
T388 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4257568352 Aug 05 04:55:39 PM PDT 24 Aug 05 04:55:42 PM PDT 24 731956400 ps
T389 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1384906107 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:26 PM PDT 24 219421048 ps
T390 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2883707226 Aug 05 04:55:19 PM PDT 24 Aug 05 04:55:22 PM PDT 24 1026882531 ps
T391 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2860370414 Aug 05 04:55:49 PM PDT 24 Aug 05 04:56:04 PM PDT 24 20722824321 ps
T161 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3056361173 Aug 05 04:55:47 PM PDT 24 Aug 05 04:56:09 PM PDT 24 5860056284 ps
T392 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2555250060 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:44 PM PDT 24 128746319 ps
T117 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3577355809 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:37 PM PDT 24 141657002 ps
T393 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.967187586 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:30 PM PDT 24 67360182 ps
T394 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.831771969 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:45 PM PDT 24 378855416 ps
T395 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2271435920 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:50 PM PDT 24 467200821 ps
T396 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2681832917 Aug 05 04:55:47 PM PDT 24 Aug 05 04:56:06 PM PDT 24 20491062636 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.396809448 Aug 05 04:55:19 PM PDT 24 Aug 05 04:55:27 PM PDT 24 5055949078 ps
T398 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2219642020 Aug 05 04:55:22 PM PDT 24 Aug 05 04:55:27 PM PDT 24 6209820154 ps
T119 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2924889941 Aug 05 04:55:21 PM PDT 24 Aug 05 04:55:23 PM PDT 24 298572129 ps
T399 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2065246380 Aug 05 04:55:32 PM PDT 24 Aug 05 04:55:38 PM PDT 24 416376848 ps
T120 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.699214507 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:48 PM PDT 24 77124377 ps
T400 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.562297585 Aug 05 04:55:16 PM PDT 24 Aug 05 04:55:20 PM PDT 24 2470307711 ps
T401 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4016721161 Aug 05 04:55:58 PM PDT 24 Aug 05 04:57:09 PM PDT 24 78121801889 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.168391722 Aug 05 04:55:22 PM PDT 24 Aug 05 04:55:26 PM PDT 24 3819989470 ps
T158 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3510197033 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:45 PM PDT 24 1430937917 ps
T402 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1162857054 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:30 PM PDT 24 301165941 ps
T403 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1791918423 Aug 05 04:55:24 PM PDT 24 Aug 05 04:55:25 PM PDT 24 119222140 ps
T404 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3470030381 Aug 05 04:55:29 PM PDT 24 Aug 05 04:55:30 PM PDT 24 744294450 ps
T405 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2373712766 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:46 PM PDT 24 1876976418 ps
T406 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2432915507 Aug 05 04:55:37 PM PDT 24 Aug 05 04:55:39 PM PDT 24 1250080847 ps
T407 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2307966638 Aug 05 04:56:19 PM PDT 24 Aug 05 04:56:22 PM PDT 24 333674954 ps
T408 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1543992816 Aug 05 04:55:50 PM PDT 24 Aug 05 04:55:54 PM PDT 24 442040333 ps
T160 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3816556925 Aug 05 04:55:26 PM PDT 24 Aug 05 04:55:58 PM PDT 24 6610069776 ps
T409 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2115480794 Aug 05 04:55:58 PM PDT 24 Aug 05 04:56:00 PM PDT 24 436619713 ps
T410 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.511308329 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:29 PM PDT 24 215981923 ps
T411 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4147902272 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:38 PM PDT 24 75753106 ps
T412 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.560654125 Aug 05 04:55:49 PM PDT 24 Aug 05 05:09:29 PM PDT 24 76902420471 ps
T413 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3611866619 Aug 05 04:55:30 PM PDT 24 Aug 05 04:55:35 PM PDT 24 2045742563 ps
T414 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1370237254 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:45 PM PDT 24 1127344385 ps
T415 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3529004822 Aug 05 04:55:23 PM PDT 24 Aug 05 04:55:32 PM PDT 24 1666691251 ps
T416 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.917149841 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:51 PM PDT 24 746824786 ps
T121 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3022690128 Aug 05 04:55:50 PM PDT 24 Aug 05 04:55:53 PM PDT 24 339698428 ps
T122 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2545790926 Aug 05 04:55:20 PM PDT 24 Aug 05 04:55:24 PM PDT 24 452608114 ps
T417 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3541869694 Aug 05 04:55:26 PM PDT 24 Aug 05 04:56:03 PM PDT 24 47628138231 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3011111512 Aug 05 04:55:20 PM PDT 24 Aug 05 04:55:50 PM PDT 24 1797666309 ps
T418 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1962967334 Aug 05 04:55:31 PM PDT 24 Aug 05 04:55:33 PM PDT 24 743913573 ps
T419 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2079760258 Aug 05 04:55:23 PM PDT 24 Aug 05 04:55:31 PM PDT 24 2735349452 ps
T420 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.754251332 Aug 05 04:55:22 PM PDT 24 Aug 05 04:55:24 PM PDT 24 961608866 ps
T421 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.430388701 Aug 05 04:55:53 PM PDT 24 Aug 05 04:56:01 PM PDT 24 451001654 ps
T422 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.289148032 Aug 05 04:55:43 PM PDT 24 Aug 05 04:55:49 PM PDT 24 1831866814 ps
T423 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.816589296 Aug 05 04:55:33 PM PDT 24 Aug 05 04:55:36 PM PDT 24 454524867 ps
T424 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1779927877 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:42 PM PDT 24 8049522114 ps
T425 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.297829031 Aug 05 04:55:40 PM PDT 24 Aug 05 04:55:45 PM PDT 24 236035509 ps
T426 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.630208508 Aug 05 04:55:28 PM PDT 24 Aug 05 04:55:29 PM PDT 24 405326176 ps
T427 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3479889066 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:44 PM PDT 24 214515134 ps
T165 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.146717707 Aug 05 04:55:37 PM PDT 24 Aug 05 04:55:49 PM PDT 24 3406327562 ps
T428 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2958615847 Aug 05 04:55:34 PM PDT 24 Aug 05 04:55:38 PM PDT 24 686144984 ps
T163 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1710048762 Aug 05 04:55:53 PM PDT 24 Aug 05 04:56:15 PM PDT 24 2378517720 ps
T429 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4012880438 Aug 05 04:55:40 PM PDT 24 Aug 05 04:55:42 PM PDT 24 117845148 ps
T430 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2387952697 Aug 05 04:55:44 PM PDT 24 Aug 05 04:56:46 PM PDT 24 19980781146 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1827387644 Aug 05 04:55:31 PM PDT 24 Aug 05 04:55:38 PM PDT 24 4758302250 ps
T431 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1596514478 Aug 05 04:55:50 PM PDT 24 Aug 05 04:56:44 PM PDT 24 21106016647 ps
T432 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1621748217 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:46 PM PDT 24 146257033 ps
T433 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.12591739 Aug 05 04:55:22 PM PDT 24 Aug 05 04:55:23 PM PDT 24 53134607 ps
T434 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1300056905 Aug 05 04:55:26 PM PDT 24 Aug 05 04:55:33 PM PDT 24 426696890 ps
T435 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3868610038 Aug 05 04:55:18 PM PDT 24 Aug 05 04:55:52 PM PDT 24 22803669587 ps
T436 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1385648101 Aug 05 04:55:45 PM PDT 24 Aug 05 04:55:46 PM PDT 24 620141694 ps
T437 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3399416840 Aug 05 04:55:31 PM PDT 24 Aug 05 04:55:34 PM PDT 24 226413853 ps
T438 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1236616489 Aug 05 04:55:51 PM PDT 24 Aug 05 04:56:38 PM PDT 24 66444277353 ps
T439 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4142294839 Aug 05 04:55:37 PM PDT 24 Aug 05 04:59:22 PM PDT 24 170544858704 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1750222856 Aug 05 04:55:17 PM PDT 24 Aug 05 04:55:31 PM PDT 24 5753517848 ps
T440 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1088934364 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:43 PM PDT 24 81384755 ps
T441 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1353565339 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:42 PM PDT 24 401462285 ps
T442 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3985242723 Aug 05 04:55:53 PM PDT 24 Aug 05 04:55:56 PM PDT 24 172348314 ps
T443 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2910961682 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:28 PM PDT 24 817985843 ps
T444 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3559899443 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:26 PM PDT 24 436629489 ps
T445 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1113523946 Aug 05 04:55:31 PM PDT 24 Aug 05 04:55:33 PM PDT 24 190007380 ps
T446 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1464053170 Aug 05 04:55:18 PM PDT 24 Aug 05 04:55:19 PM PDT 24 141537895 ps
T447 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1441640526 Aug 05 04:55:25 PM PDT 24 Aug 05 04:55:27 PM PDT 24 250805257 ps
T448 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3568558981 Aug 05 04:55:26 PM PDT 24 Aug 05 04:56:00 PM PDT 24 9872763329 ps
T449 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3879857101 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:38 PM PDT 24 5710600239 ps
T450 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2388274112 Aug 05 04:55:19 PM PDT 24 Aug 05 04:55:58 PM PDT 24 41267439254 ps
T451 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1987487155 Aug 05 04:55:46 PM PDT 24 Aug 05 04:55:47 PM PDT 24 114907505 ps
T452 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3315890106 Aug 05 04:55:42 PM PDT 24 Aug 05 04:55:45 PM PDT 24 380423928 ps
T453 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4067371038 Aug 05 04:55:38 PM PDT 24 Aug 05 04:55:41 PM PDT 24 219249903 ps
T454 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.540675658 Aug 05 04:55:36 PM PDT 24 Aug 05 04:55:44 PM PDT 24 468305268 ps
T455 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3649290772 Aug 05 04:55:36 PM PDT 24 Aug 05 04:56:16 PM PDT 24 33541024573 ps
T456 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.462801144 Aug 05 04:55:27 PM PDT 24 Aug 05 04:55:32 PM PDT 24 273465868 ps
T457 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1990854893 Aug 05 04:55:39 PM PDT 24 Aug 05 04:56:28 PM PDT 24 72375180071 ps
T458 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2404778421 Aug 05 04:55:35 PM PDT 24 Aug 05 04:55:43 PM PDT 24 1571444943 ps
T459 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1990140397 Aug 05 04:55:28 PM PDT 24 Aug 05 04:55:29 PM PDT 24 122767641 ps
T164 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3569783484 Aug 05 04:55:34 PM PDT 24 Aug 05 04:55:50 PM PDT 24 3936440744 ps
T460 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3683097255 Aug 05 04:55:24 PM PDT 24 Aug 05 04:55:28 PM PDT 24 238441263 ps
T461 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.504061794 Aug 05 04:55:37 PM PDT 24 Aug 05 04:55:40 PM PDT 24 266000174 ps
T462 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2530287469 Aug 05 04:55:38 PM PDT 24 Aug 05 04:55:39 PM PDT 24 111640854 ps
T463 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.795829170 Aug 05 04:55:20 PM PDT 24 Aug 05 04:55:40 PM PDT 24 2368775137 ps
T464 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2509470342 Aug 05 04:55:40 PM PDT 24 Aug 05 04:55:41 PM PDT 24 251191114 ps

Test location /workspace/coverage/default/33.rv_dm_stress_all.1964425435
Short name T6
Test name
Test status
Simulation time 9238516383 ps
CPU time 23.16 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:28 PM PDT 24
Peak memory 213816 kb
Host smart-71cf76de-b2e2-4f35-9039-58dfc915b365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964425435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1964425435
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3507843072
Short name T8
Test name
Test status
Simulation time 44151358740 ps
CPU time 192.23 seconds
Started Aug 05 06:00:35 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 230240 kb
Host smart-02752a3c-ca30-44f7-b7c7-1fbb0c2c64cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507843072 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.3507843072
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.677455082
Short name T13
Test name
Test status
Simulation time 11551905020 ps
CPU time 32.49 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:01:11 PM PDT 24
Peak memory 222052 kb
Host smart-427f2a09-7f0b-477a-b3bc-3716295d10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677455082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.677455082
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3350872375
Short name T132
Test name
Test status
Simulation time 3869952604 ps
CPU time 21.45 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:56:01 PM PDT 24
Peak memory 213880 kb
Host smart-f3a1cb75-da7e-40f3-ad1b-3b1b66dba18b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350872375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
350872375
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3308428536
Short name T62
Test name
Test status
Simulation time 60272095338 ps
CPU time 195.89 seconds
Started Aug 05 04:55:41 PM PDT 24
Finished Aug 05 04:58:57 PM PDT 24
Peak memory 222100 kb
Host smart-318ce524-3e15-4cbe-a3ed-1c1ae81900f7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308428536 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3308428536
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.1459061885
Short name T23
Test name
Test status
Simulation time 136732696876 ps
CPU time 1478 seconds
Started Aug 05 06:00:36 PM PDT 24
Finished Aug 05 06:25:15 PM PDT 24
Peak memory 245852 kb
Host smart-dbff34ab-dfc1-45ed-b2aa-b558541687da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459061885 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.1459061885
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.3437118469
Short name T59
Test name
Test status
Simulation time 225254813 ps
CPU time 0.88 seconds
Started Aug 05 06:00:17 PM PDT 24
Finished Aug 05 06:00:18 PM PDT 24
Peak memory 205300 kb
Host smart-807e7ebc-590d-4ffb-95e4-d5c0bf63b59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437118469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3437118469
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3998653618
Short name T50
Test name
Test status
Simulation time 68302400 ps
CPU time 0.88 seconds
Started Aug 05 06:00:57 PM PDT 24
Finished Aug 05 06:00:58 PM PDT 24
Peak memory 205304 kb
Host smart-3125b764-3c82-4dcc-b4a6-5e9c577ca35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998653618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3998653618
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3759728927
Short name T112
Test name
Test status
Simulation time 20714460872 ps
CPU time 75.57 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:56:41 PM PDT 24
Peak memory 213772 kb
Host smart-7d380cc2-bb77-4ae7-be16-7399732d30b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759728927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3759728927
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.830762732
Short name T80
Test name
Test status
Simulation time 3277372167 ps
CPU time 4.79 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:50 PM PDT 24
Peak memory 205740 kb
Host smart-e79c2c1f-b5c9-41d6-a55d-c97391e070b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830762732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.830762732
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3466706617
Short name T58
Test name
Test status
Simulation time 183339955 ps
CPU time 0.96 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:30 PM PDT 24
Peak memory 205280 kb
Host smart-4fb5cd40-838d-4253-951a-b044af90292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466706617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3466706617
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1133882263
Short name T77
Test name
Test status
Simulation time 1095330293 ps
CPU time 3.68 seconds
Started Aug 05 06:00:12 PM PDT 24
Finished Aug 05 06:00:15 PM PDT 24
Peak memory 205524 kb
Host smart-2af64285-1594-4f14-b8ed-69472357152d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133882263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1133882263
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2557157648
Short name T54
Test name
Test status
Simulation time 2004641638 ps
CPU time 3.7 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:33 PM PDT 24
Peak memory 229640 kb
Host smart-b7ef3597-fd78-4e61-9d02-464b77439185
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557157648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2557157648
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4034367335
Short name T133
Test name
Test status
Simulation time 2283140618 ps
CPU time 2.8 seconds
Started Aug 05 06:00:39 PM PDT 24
Finished Aug 05 06:00:42 PM PDT 24
Peak memory 205764 kb
Host smart-bd41d4a4-8fdd-4b5b-9861-818d0c2edf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034367335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4034367335
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3433002941
Short name T67
Test name
Test status
Simulation time 6630275390 ps
CPU time 5.13 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:10 PM PDT 24
Peak memory 205716 kb
Host smart-f7835423-8b80-4dee-9fe4-1097c858aa46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433002941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3433002941
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2126006618
Short name T19
Test name
Test status
Simulation time 247792303 ps
CPU time 1.45 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 205324 kb
Host smart-b6dba079-90e6-4a23-9650-cdbec48a2637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126006618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2126006618
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1797127155
Short name T38
Test name
Test status
Simulation time 102739684 ps
CPU time 0.83 seconds
Started Aug 05 06:00:21 PM PDT 24
Finished Aug 05 06:00:22 PM PDT 24
Peak memory 213500 kb
Host smart-466fad99-0c90-4968-bd57-c4b6554e45ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797127155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1797127155
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.9542928
Short name T93
Test name
Test status
Simulation time 914203521 ps
CPU time 4.08 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:24 PM PDT 24
Peak memory 205628 kb
Host smart-ed13bd9a-dd94-4412-ad13-a1e7a8ec4211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9542928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr
_outstanding.9542928
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3816556925
Short name T160
Test name
Test status
Simulation time 6610069776 ps
CPU time 32.41 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:55:58 PM PDT 24
Peak memory 213956 kb
Host smart-b33c8dae-6765-49d5-a919-ebb2ff7ddf24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816556925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3816556925
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3171468497
Short name T137
Test name
Test status
Simulation time 3360320444 ps
CPU time 10.26 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 215396 kb
Host smart-41f8d37d-3547-4bce-a3ed-e450fc0160fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171468497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3171468497
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1005732886
Short name T140
Test name
Test status
Simulation time 9203906117 ps
CPU time 8.33 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:00:57 PM PDT 24
Peak memory 214004 kb
Host smart-6499f464-1fe8-4cae-8990-3d46d3965bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005732886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1005732886
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2383413060
Short name T141
Test name
Test status
Simulation time 1591908854 ps
CPU time 4.71 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:50 PM PDT 24
Peak memory 205508 kb
Host smart-d5a5a280-ef05-4988-9679-dc111c915c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383413060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2383413060
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2715496024
Short name T30
Test name
Test status
Simulation time 415287347 ps
CPU time 0.83 seconds
Started Aug 05 06:00:16 PM PDT 24
Finished Aug 05 06:00:17 PM PDT 24
Peak memory 205272 kb
Host smart-3081c859-a37a-44fd-b22c-6aaec8e47593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715496024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2715496024
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1453593505
Short name T146
Test name
Test status
Simulation time 5163822827 ps
CPU time 12.55 seconds
Started Aug 05 06:00:51 PM PDT 24
Finished Aug 05 06:01:03 PM PDT 24
Peak memory 205692 kb
Host smart-ae0e7ec4-d3b6-4b28-8af3-0c8c0ea4af9f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1453593505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1453593505
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1628838022
Short name T157
Test name
Test status
Simulation time 2607966978 ps
CPU time 21.56 seconds
Started Aug 05 04:55:15 PM PDT 24
Finished Aug 05 04:55:37 PM PDT 24
Peak memory 214040 kb
Host smart-8209adbf-5678-4809-bf8f-35f42a15f187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628838022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1628838022
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1806103259
Short name T154
Test name
Test status
Simulation time 3844806921 ps
CPU time 10.18 seconds
Started Aug 05 06:00:56 PM PDT 24
Finished Aug 05 06:01:07 PM PDT 24
Peak memory 213796 kb
Host smart-0f25244c-9c14-42da-9e25-76885b0950b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806103259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1806103259
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2180513181
Short name T65
Test name
Test status
Simulation time 9533400708 ps
CPU time 15.7 seconds
Started Aug 05 04:55:21 PM PDT 24
Finished Aug 05 04:55:36 PM PDT 24
Peak memory 205560 kb
Host smart-f0620f1c-8238-45f4-b698-640145614c38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180513181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2180513181
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2829142881
Short name T49
Test name
Test status
Simulation time 141319511 ps
CPU time 0.82 seconds
Started Aug 05 06:00:21 PM PDT 24
Finished Aug 05 06:00:22 PM PDT 24
Peak memory 205304 kb
Host smart-6877ec66-5733-4ebc-b19e-b0d5a6c427b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829142881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2829142881
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.168391722
Short name T101
Test name
Test status
Simulation time 3819989470 ps
CPU time 3.73 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:55:26 PM PDT 24
Peak memory 205588 kb
Host smart-2cf0b0c8-e769-47b2-b8c4-53683b9089f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168391722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.168391722
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.302135047
Short name T35
Test name
Test status
Simulation time 700630099 ps
CPU time 1.61 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 205348 kb
Host smart-20a98c9c-ba32-497c-8285-121bb58581c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302135047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.302135047
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1300349787
Short name T159
Test name
Test status
Simulation time 3971956100 ps
CPU time 18.94 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:53 PM PDT 24
Peak memory 213964 kb
Host smart-de2eeabf-1913-4367-ba4c-555b7978088b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300349787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
300349787
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3333470912
Short name T245
Test name
Test status
Simulation time 3793879566 ps
CPU time 2.07 seconds
Started Aug 05 06:00:59 PM PDT 24
Finished Aug 05 06:01:02 PM PDT 24
Peak memory 213780 kb
Host smart-ce1db840-709a-44c3-b0fc-100dba76b6c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333470912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3333470912
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1806941114
Short name T155
Test name
Test status
Simulation time 5346759812 ps
CPU time 11.85 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:17 PM PDT 24
Peak memory 205560 kb
Host smart-cc9b4afa-42c6-40a9-85f8-9f81bad0f940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806941114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1806941114
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3541869694
Short name T417
Test name
Test status
Simulation time 47628138231 ps
CPU time 36.44 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:56:03 PM PDT 24
Peak memory 220132 kb
Host smart-69496a64-2db9-43b4-bf89-12091184fa03
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541869694 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3541869694
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3216116300
Short name T108
Test name
Test status
Simulation time 3616051630 ps
CPU time 64.89 seconds
Started Aug 05 04:55:17 PM PDT 24
Finished Aug 05 04:56:22 PM PDT 24
Peak memory 213944 kb
Host smart-73b9ef83-14d6-4212-b72a-7cc1e46ce207
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216116300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3216116300
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4289342933
Short name T105
Test name
Test status
Simulation time 749889722 ps
CPU time 27.29 seconds
Started Aug 05 04:55:13 PM PDT 24
Finished Aug 05 04:55:40 PM PDT 24
Peak memory 205496 kb
Host smart-e393f13b-fae1-49f0-953e-23f5e7603edc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289342933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4289342933
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2545790926
Short name T122
Test name
Test status
Simulation time 452608114 ps
CPU time 3.43 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:24 PM PDT 24
Peak memory 213860 kb
Host smart-7fcb21a6-8dae-47b7-9a79-3bbab986fcb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545790926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2545790926
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1162857054
Short name T402
Test name
Test status
Simulation time 301165941 ps
CPU time 4.58 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:30 PM PDT 24
Peak memory 222004 kb
Host smart-2e4fcb35-96e6-44a5-9c92-d45bc8b01a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162857054 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1162857054
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1441640526
Short name T447
Test name
Test status
Simulation time 250805257 ps
CPU time 1.73 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:27 PM PDT 24
Peak memory 213676 kb
Host smart-cd331e37-027a-4128-ac53-aee07b91df6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441640526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1441640526
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3727455023
Short name T331
Test name
Test status
Simulation time 96108381829 ps
CPU time 241.52 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:59:21 PM PDT 24
Peak memory 205696 kb
Host smart-01ec1acb-3691-42fc-9238-f123fa68df11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727455023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3727455023
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2659993852
Short name T335
Test name
Test status
Simulation time 10612006756 ps
CPU time 6.93 seconds
Started Aug 05 04:55:16 PM PDT 24
Finished Aug 05 04:55:23 PM PDT 24
Peak memory 205524 kb
Host smart-f2755c7f-a9de-4a1d-81f5-13af25685fbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659993852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2659993852
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2455426775
Short name T363
Test name
Test status
Simulation time 4751816979 ps
CPU time 4.25 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:25 PM PDT 24
Peak memory 205752 kb
Host smart-24e0ed80-7cc5-48a8-acd6-d5c88d58d5b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455426775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2455426775
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2354501000
Short name T307
Test name
Test status
Simulation time 7788441462 ps
CPU time 6.83 seconds
Started Aug 05 04:55:23 PM PDT 24
Finished Aug 05 04:55:30 PM PDT 24
Peak memory 205608 kb
Host smart-c7f2429e-c1f2-4706-ad12-562c793c3dbc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354501000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
354501000
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3559899443
Short name T444
Test name
Test status
Simulation time 436629489 ps
CPU time 1.28 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:26 PM PDT 24
Peak memory 205320 kb
Host smart-2c929d3b-1050-4352-bf7e-9c6830eb9c00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559899443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3559899443
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1449723563
Short name T373
Test name
Test status
Simulation time 2710023680 ps
CPU time 8.2 seconds
Started Aug 05 04:55:17 PM PDT 24
Finished Aug 05 04:55:25 PM PDT 24
Peak memory 205604 kb
Host smart-0c593a78-97db-4fa6-9655-7553aee3d259
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449723563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1449723563
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2883707226
Short name T390
Test name
Test status
Simulation time 1026882531 ps
CPU time 3.02 seconds
Started Aug 05 04:55:19 PM PDT 24
Finished Aug 05 04:55:22 PM PDT 24
Peak memory 205284 kb
Host smart-0cc193da-a283-406a-b326-43c069a8963c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883707226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2883707226
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1771688581
Short name T360
Test name
Test status
Simulation time 384114977 ps
CPU time 0.96 seconds
Started Aug 05 04:55:24 PM PDT 24
Finished Aug 05 04:55:25 PM PDT 24
Peak memory 205308 kb
Host smart-b1af5769-725b-4832-94b5-403ddecdbe28
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771688581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
771688581
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1464053170
Short name T446
Test name
Test status
Simulation time 141537895 ps
CPU time 1 seconds
Started Aug 05 04:55:18 PM PDT 24
Finished Aug 05 04:55:19 PM PDT 24
Peak memory 205332 kb
Host smart-cc7fec79-a929-4bdc-9065-d4711023dd56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464053170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1464053170
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1882132023
Short name T377
Test name
Test status
Simulation time 104675972 ps
CPU time 0.68 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:37 PM PDT 24
Peak memory 205352 kb
Host smart-b85d1d2f-c24b-47e3-a7b0-12fe1e602225
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882132023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1882132023
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2026451480
Short name T98
Test name
Test status
Simulation time 206863100 ps
CPU time 3.68 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:23 PM PDT 24
Peak memory 205584 kb
Host smart-f0396234-5eba-4f8b-9212-6ead181ae8dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026451480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2026451480
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3116840429
Short name T361
Test name
Test status
Simulation time 40647249153 ps
CPU time 59.37 seconds
Started Aug 05 04:55:15 PM PDT 24
Finished Aug 05 04:56:14 PM PDT 24
Peak memory 221404 kb
Host smart-7b22e62d-4016-4213-8b28-144e26eeff6c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116840429 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3116840429
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2302633372
Short name T83
Test name
Test status
Simulation time 500296779 ps
CPU time 5.5 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:25 PM PDT 24
Peak memory 213800 kb
Host smart-f73931a3-367c-4c60-910c-56b47294240d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302633372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2302633372
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.795829170
Short name T463
Test name
Test status
Simulation time 2368775137 ps
CPU time 20.3 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:40 PM PDT 24
Peak memory 214000 kb
Host smart-2ef4e7ad-b5e8-42f7-8ca1-451935e5d069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795829170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.795829170
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3011111512
Short name T118
Test name
Test status
Simulation time 1797666309 ps
CPU time 29.77 seconds
Started Aug 05 04:55:20 PM PDT 24
Finished Aug 05 04:55:50 PM PDT 24
Peak memory 205472 kb
Host smart-8916b744-19d6-439d-a3b2-7f2613febf68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011111512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3011111512
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2388274112
Short name T450
Test name
Test status
Simulation time 41267439254 ps
CPU time 38.65 seconds
Started Aug 05 04:55:19 PM PDT 24
Finished Aug 05 04:55:58 PM PDT 24
Peak memory 205668 kb
Host smart-a6f1dc8e-75da-4a74-b4b6-192074e376e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388274112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2388274112
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.23281309
Short name T104
Test name
Test status
Simulation time 250846605 ps
CPU time 1.78 seconds
Started Aug 05 04:55:08 PM PDT 24
Finished Aug 05 04:55:10 PM PDT 24
Peak memory 213748 kb
Host smart-4a486368-dfaf-434c-b187-23153fcd2b22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23281309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.23281309
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.297829031
Short name T425
Test name
Test status
Simulation time 236035509 ps
CPU time 4.81 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:55:45 PM PDT 24
Peak memory 222008 kb
Host smart-a64c2593-5127-4a86-a797-e7a195895f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297829031 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.297829031
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2924889941
Short name T119
Test name
Test status
Simulation time 298572129 ps
CPU time 1.62 seconds
Started Aug 05 04:55:21 PM PDT 24
Finished Aug 05 04:55:23 PM PDT 24
Peak memory 213756 kb
Host smart-8284e873-5814-4832-94d2-cf9acacccdfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924889941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2924889941
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2680725603
Short name T379
Test name
Test status
Simulation time 219950149197 ps
CPU time 157.92 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 211260 kb
Host smart-070c3a13-f397-4c9e-8684-6a20fa79ea35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680725603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2680725603
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3868610038
Short name T435
Test name
Test status
Simulation time 22803669587 ps
CPU time 33.17 seconds
Started Aug 05 04:55:18 PM PDT 24
Finished Aug 05 04:55:52 PM PDT 24
Peak memory 205660 kb
Host smart-73fa83f1-e385-4dd4-8bba-68f0cef7dacc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868610038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3868610038
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2219642020
Short name T398
Test name
Test status
Simulation time 6209820154 ps
CPU time 5.02 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:55:27 PM PDT 24
Peak memory 205600 kb
Host smart-2faadae9-e406-4995-b968-751f68f776fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219642020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
219642020
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2253650537
Short name T355
Test name
Test status
Simulation time 998641077 ps
CPU time 3.17 seconds
Started Aug 05 04:55:24 PM PDT 24
Finished Aug 05 04:55:28 PM PDT 24
Peak memory 205236 kb
Host smart-be7ed60f-387f-4dea-9915-4e1f622f4502
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253650537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2253650537
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.773412875
Short name T310
Test name
Test status
Simulation time 438165946 ps
CPU time 1.32 seconds
Started Aug 05 04:55:21 PM PDT 24
Finished Aug 05 04:55:23 PM PDT 24
Peak memory 205300 kb
Host smart-5b3141c5-b612-41c8-ad17-bc89a7c9944b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773412875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.773412875
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1770970670
Short name T64
Test name
Test status
Simulation time 411128852 ps
CPU time 0.95 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:55:23 PM PDT 24
Peak memory 205332 kb
Host smart-a6bd7d75-3762-47f6-9c66-3354d48f26a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770970670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
770970670
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1569170850
Short name T313
Test name
Test status
Simulation time 49586737 ps
CPU time 0.79 seconds
Started Aug 05 04:55:13 PM PDT 24
Finished Aug 05 04:55:14 PM PDT 24
Peak memory 205296 kb
Host smart-63fe01ea-5bf8-453b-bb98-83a64a6a4b8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569170850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1569170850
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.12591739
Short name T433
Test name
Test status
Simulation time 53134607 ps
CPU time 0.68 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:55:23 PM PDT 24
Peak memory 205232 kb
Host smart-9f0008c6-23bc-4cfa-905a-ec28ff93026c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12591739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.12591739
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.406469680
Short name T124
Test name
Test status
Simulation time 288313611 ps
CPU time 6.23 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 205668 kb
Host smart-6b296229-6104-4dc3-b69a-5bc335ceefcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406469680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.406469680
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1149814964
Short name T126
Test name
Test status
Simulation time 252672798 ps
CPU time 5.36 seconds
Started Aug 05 04:55:19 PM PDT 24
Finished Aug 05 04:55:24 PM PDT 24
Peak memory 213940 kb
Host smart-33aa10b1-b3a4-43f5-8c1a-4adb79931df4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149814964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1149814964
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1566236497
Short name T324
Test name
Test status
Simulation time 165995970 ps
CPU time 3.76 seconds
Started Aug 05 04:55:35 PM PDT 24
Finished Aug 05 04:55:39 PM PDT 24
Peak memory 213904 kb
Host smart-7be22215-71ce-4af9-86af-44b581e2cb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566236497 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1566236497
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4147902272
Short name T411
Test name
Test status
Simulation time 75753106 ps
CPU time 1.56 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:38 PM PDT 24
Peak memory 213832 kb
Host smart-2e051209-39a2-400d-a0a3-67f410281a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147902272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4147902272
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.857776975
Short name T356
Test name
Test status
Simulation time 5726656301 ps
CPU time 3.98 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 205600 kb
Host smart-fb030f18-1295-4347-baf1-989d7c6eb800
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857776975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.857776975
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1896789917
Short name T306
Test name
Test status
Simulation time 5976241690 ps
CPU time 2.04 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:36 PM PDT 24
Peak memory 205632 kb
Host smart-86af1fa0-d820-4020-826b-325ca5354aae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896789917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1896789917
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1450648987
Short name T343
Test name
Test status
Simulation time 128304931 ps
CPU time 1.04 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:35 PM PDT 24
Peak memory 205256 kb
Host smart-bb14035d-30cb-4408-b49d-53de581f97fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450648987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1450648987
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1061950686
Short name T91
Test name
Test status
Simulation time 1388095357 ps
CPU time 3.48 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 205616 kb
Host smart-45fab246-dce4-4a17-a048-355993c0b6dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061950686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1061950686
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4067371038
Short name T453
Test name
Test status
Simulation time 219249903 ps
CPU time 2.73 seconds
Started Aug 05 04:55:38 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 221912 kb
Host smart-96ab1125-f8e1-4aa3-9b62-d9c722554b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067371038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4067371038
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1370237254
Short name T414
Test name
Test status
Simulation time 1127344385 ps
CPU time 8.78 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:45 PM PDT 24
Peak memory 213772 kb
Host smart-5775b017-0bf9-43e5-bb44-d4184e010ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370237254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
370237254
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3546962367
Short name T129
Test name
Test status
Simulation time 171907233 ps
CPU time 3.73 seconds
Started Aug 05 04:55:47 PM PDT 24
Finished Aug 05 04:55:51 PM PDT 24
Peak memory 221764 kb
Host smart-86718389-1975-4f5d-a14c-6c2a911a344b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546962367 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3546962367
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3479889066
Short name T427
Test name
Test status
Simulation time 214515134 ps
CPU time 1.62 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:44 PM PDT 24
Peak memory 213852 kb
Host smart-11a9f03f-0737-4dd9-9d08-4cf0c0f8b140
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479889066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3479889066
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1596514478
Short name T431
Test name
Test status
Simulation time 21106016647 ps
CPU time 53.96 seconds
Started Aug 05 04:55:50 PM PDT 24
Finished Aug 05 04:56:44 PM PDT 24
Peak memory 205592 kb
Host smart-01883278-e4e6-4c17-8246-92b0e336dda3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596514478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1596514478
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2373712766
Short name T405
Test name
Test status
Simulation time 1876976418 ps
CPU time 3.77 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 205512 kb
Host smart-b0c2b557-ed05-4cc2-852a-348715d45421
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373712766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2373712766
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1875324745
Short name T315
Test name
Test status
Simulation time 248400904 ps
CPU time 0.84 seconds
Started Aug 05 04:55:30 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 205420 kb
Host smart-902ca8ff-c9ab-45b9-9be6-d5f67e1d33f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875324745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1875324745
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.182184820
Short name T95
Test name
Test status
Simulation time 1565765096 ps
CPU time 8.06 seconds
Started Aug 05 04:55:49 PM PDT 24
Finished Aug 05 04:55:57 PM PDT 24
Peak memory 205596 kb
Host smart-e029bdee-e378-4268-bbc5-19dd8abcf814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182184820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.182184820
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3954591633
Short name T332
Test name
Test status
Simulation time 168092316 ps
CPU time 2.38 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:36 PM PDT 24
Peak memory 213864 kb
Host smart-f91608f6-eae0-451a-9f57-a88c902558aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954591633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3954591633
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4067569206
Short name T162
Test name
Test status
Simulation time 5767619365 ps
CPU time 23.78 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:56:01 PM PDT 24
Peak memory 213856 kb
Host smart-3557ce12-45bd-48c4-89ca-2013477cf3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067569206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4
067569206
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4286757116
Short name T370
Test name
Test status
Simulation time 246414165 ps
CPU time 3.9 seconds
Started Aug 05 04:55:58 PM PDT 24
Finished Aug 05 04:56:02 PM PDT 24
Peak memory 219320 kb
Host smart-80ed3edc-94fc-40f9-bf76-e4c586831363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286757116 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4286757116
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4012880438
Short name T429
Test name
Test status
Simulation time 117845148 ps
CPU time 2.21 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 213772 kb
Host smart-cbc472d9-1dcc-4b05-9ee0-271ca4592e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012880438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4012880438
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1236616489
Short name T438
Test name
Test status
Simulation time 66444277353 ps
CPU time 47.26 seconds
Started Aug 05 04:55:51 PM PDT 24
Finished Aug 05 04:56:38 PM PDT 24
Peak memory 205568 kb
Host smart-493eb515-e6d9-4d55-8954-a671e4d999bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236616489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1236616489
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1779927877
Short name T424
Test name
Test status
Simulation time 8049522114 ps
CPU time 6.38 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 205560 kb
Host smart-9216dea7-f343-40db-82fc-c0dcde1bf10c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779927877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1779927877
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.678139185
Short name T369
Test name
Test status
Simulation time 335749803 ps
CPU time 1.41 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 205344 kb
Host smart-95628159-691f-4b74-9fea-93474e3aff09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678139185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.678139185
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.540675658
Short name T454
Test name
Test status
Simulation time 468305268 ps
CPU time 7.72 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:44 PM PDT 24
Peak memory 205588 kb
Host smart-5123d577-86fc-4187-9f66-9d45b2420bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540675658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.540675658
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3244417595
Short name T371
Test name
Test status
Simulation time 577391905 ps
CPU time 2.76 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 213808 kb
Host smart-8208b7b5-ee33-4693-b534-ae58a72e075e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244417595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3244417595
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3056361173
Short name T161
Test name
Test status
Simulation time 5860056284 ps
CPU time 21.62 seconds
Started Aug 05 04:55:47 PM PDT 24
Finished Aug 05 04:56:09 PM PDT 24
Peak memory 213712 kb
Host smart-778b55bc-fcef-4e77-9dbd-ab450558abe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056361173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
056361173
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.377804543
Short name T372
Test name
Test status
Simulation time 143776336 ps
CPU time 2.6 seconds
Started Aug 05 04:55:58 PM PDT 24
Finished Aug 05 04:56:01 PM PDT 24
Peak memory 219512 kb
Host smart-da861268-380a-43ae-8aef-6462ce8a9adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377804543 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.377804543
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3022690128
Short name T121
Test name
Test status
Simulation time 339698428 ps
CPU time 2.41 seconds
Started Aug 05 04:55:50 PM PDT 24
Finished Aug 05 04:55:53 PM PDT 24
Peak memory 213656 kb
Host smart-e641ad7e-9b61-45bf-9620-7d0d1f3b2243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022690128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3022690128
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3241481126
Short name T381
Test name
Test status
Simulation time 126535674 ps
CPU time 0.79 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:44 PM PDT 24
Peak memory 205336 kb
Host smart-df02e208-dab9-4eca-8388-682fc41c9a73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241481126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3241481126
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4204029911
Short name T320
Test name
Test status
Simulation time 7060292224 ps
CPU time 6.41 seconds
Started Aug 05 04:55:59 PM PDT 24
Finished Aug 05 04:56:05 PM PDT 24
Peak memory 205624 kb
Host smart-68d097ba-d443-4438-8bdc-5bcd258eeca8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204029911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4204029911
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2509470342
Short name T464
Test name
Test status
Simulation time 251191114 ps
CPU time 1.35 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 205348 kb
Host smart-5144dcae-bb7f-4d28-bd45-30adae8c64de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509470342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2509470342
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.903759800
Short name T123
Test name
Test status
Simulation time 751559555 ps
CPU time 6.71 seconds
Started Aug 05 04:55:41 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 205532 kb
Host smart-acfddf11-765e-4afb-a3b7-d6e8b3f77136
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903759800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.903759800
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1353565339
Short name T441
Test name
Test status
Simulation time 401462285 ps
CPU time 5.91 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 216456 kb
Host smart-70954c2e-2feb-45cb-8d5f-cf261ef51ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353565339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1353565339
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.954311088
Short name T385
Test name
Test status
Simulation time 296630048 ps
CPU time 2.27 seconds
Started Aug 05 04:55:55 PM PDT 24
Finished Aug 05 04:55:57 PM PDT 24
Peak memory 218328 kb
Host smart-af56847c-3f2a-4209-b278-ff3696f5cb15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954311088 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.954311088
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.699214507
Short name T120
Test name
Test status
Simulation time 77124377 ps
CPU time 1.47 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 213820 kb
Host smart-e4457d45-6106-4a20-b498-2d9cfd45541d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699214507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.699214507
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2681832917
Short name T396
Test name
Test status
Simulation time 20491062636 ps
CPU time 19.04 seconds
Started Aug 05 04:55:47 PM PDT 24
Finished Aug 05 04:56:06 PM PDT 24
Peak memory 205504 kb
Host smart-ba075cfd-003e-4a2c-8dde-f903763481d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681832917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2681832917
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3018544014
Short name T387
Test name
Test status
Simulation time 14313275021 ps
CPU time 19.97 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:56:05 PM PDT 24
Peak memory 205632 kb
Host smart-6f12e210-4ba6-40c6-a8d1-1d3cb37f848c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018544014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3018544014
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2432915507
Short name T406
Test name
Test status
Simulation time 1250080847 ps
CPU time 1.49 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:55:39 PM PDT 24
Peak memory 205348 kb
Host smart-86a2dda0-63ab-48e6-8063-4249e714a580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432915507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2432915507
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2660353893
Short name T374
Test name
Test status
Simulation time 289542124 ps
CPU time 4.09 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:50 PM PDT 24
Peak memory 205648 kb
Host smart-3520f7a3-a0b1-4347-9a93-cfbe4f9df3e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660353893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2660353893
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3369577375
Short name T341
Test name
Test status
Simulation time 170607256 ps
CPU time 2.24 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 213816 kb
Host smart-21d0e352-189e-4499-a81d-e56e1e863141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369577375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3369577375
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1440192883
Short name T156
Test name
Test status
Simulation time 2125128588 ps
CPU time 21.81 seconds
Started Aug 05 04:55:48 PM PDT 24
Finished Aug 05 04:56:10 PM PDT 24
Peak memory 213748 kb
Host smart-70d8e563-55da-4633-aa53-700d283bad3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440192883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
440192883
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1543992816
Short name T408
Test name
Test status
Simulation time 442040333 ps
CPU time 4.43 seconds
Started Aug 05 04:55:50 PM PDT 24
Finished Aug 05 04:55:54 PM PDT 24
Peak memory 219648 kb
Host smart-d4b98078-f3ce-4f9b-b7ef-7c5bd7064753
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543992816 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1543992816
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2523635415
Short name T110
Test name
Test status
Simulation time 149631060 ps
CPU time 2.34 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 213692 kb
Host smart-ad84aae6-a2d5-4f42-9961-5e4ab007f4fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523635415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2523635415
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2375685496
Short name T322
Test name
Test status
Simulation time 5314631637 ps
CPU time 15.03 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 205556 kb
Host smart-aa458928-ecae-4924-a655-bd20c4349431
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375685496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2375685496
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2304008104
Short name T330
Test name
Test status
Simulation time 11947232301 ps
CPU time 16.66 seconds
Started Aug 05 04:55:38 PM PDT 24
Finished Aug 05 04:55:55 PM PDT 24
Peak memory 205564 kb
Host smart-406fcc7c-0f81-4df4-bd98-5f6eea013e09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304008104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2304008104
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2115480794
Short name T409
Test name
Test status
Simulation time 436619713 ps
CPU time 1.47 seconds
Started Aug 05 04:55:58 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 205256 kb
Host smart-615f33e4-c34d-4189-a6ad-447c47546523
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115480794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2115480794
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1920985369
Short name T111
Test name
Test status
Simulation time 337456970 ps
CPU time 6.16 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 205600 kb
Host smart-50e86668-4726-4404-ba65-2d8c7936da62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920985369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1920985369
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3037155645
Short name T352
Test name
Test status
Simulation time 293866266 ps
CPU time 4.03 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:56 PM PDT 24
Peak memory 213768 kb
Host smart-df971ea1-9358-408b-9bf4-7d205a5b9c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037155645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3037155645
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.146717707
Short name T165
Test name
Test status
Simulation time 3406327562 ps
CPU time 11.26 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:55:49 PM PDT 24
Peak memory 213980 kb
Host smart-4d6bf25e-6b8c-4f32-9725-710f42fb4ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146717707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.146717707
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.547889084
Short name T316
Test name
Test status
Simulation time 339525482 ps
CPU time 2.41 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 218304 kb
Host smart-52c33a90-daba-4872-9f36-eead5ebee932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547889084 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.547889084
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3803705703
Short name T115
Test name
Test status
Simulation time 393436304 ps
CPU time 2.4 seconds
Started Aug 05 04:55:50 PM PDT 24
Finished Aug 05 04:55:52 PM PDT 24
Peak memory 213776 kb
Host smart-b45f4300-5632-4ee8-854e-f752e0a6a9e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803705703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3803705703
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2251106701
Short name T364
Test name
Test status
Simulation time 21876147293 ps
CPU time 15.51 seconds
Started Aug 05 04:55:54 PM PDT 24
Finished Aug 05 04:56:10 PM PDT 24
Peak memory 205584 kb
Host smart-d3f06abf-d124-4a65-b1fe-69d9fd4a79c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251106701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2251106701
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.289148032
Short name T422
Test name
Test status
Simulation time 1831866814 ps
CPU time 5.32 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:49 PM PDT 24
Peak memory 205492 kb
Host smart-848cb230-6925-40c4-a8b0-a98108e16778
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289148032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.289148032
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2555250060
Short name T392
Test name
Test status
Simulation time 128746319 ps
CPU time 0.78 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:44 PM PDT 24
Peak memory 205284 kb
Host smart-25d6d7bc-1e4b-4c6d-bd43-6ca72889ee9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555250060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2555250060
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2271435920
Short name T395
Test name
Test status
Simulation time 467200821 ps
CPU time 7.57 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:50 PM PDT 24
Peak memory 205548 kb
Host smart-240f5fea-3ffe-421b-bb38-0c3ebbd960d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271435920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2271435920
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.601170057
Short name T85
Test name
Test status
Simulation time 438495891 ps
CPU time 2.62 seconds
Started Aug 05 04:55:56 PM PDT 24
Finished Aug 05 04:55:59 PM PDT 24
Peak memory 213816 kb
Host smart-22715062-7971-45e0-9e8b-fd4011f70ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601170057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.601170057
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2630270173
Short name T127
Test name
Test status
Simulation time 6629845836 ps
CPU time 10.51 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:55:50 PM PDT 24
Peak memory 213924 kb
Host smart-1cfcda0d-0239-439c-8671-f77975214f50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630270173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
630270173
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1664831258
Short name T84
Test name
Test status
Simulation time 164171981 ps
CPU time 2.94 seconds
Started Aug 05 04:55:48 PM PDT 24
Finished Aug 05 04:55:51 PM PDT 24
Peak memory 219860 kb
Host smart-80d9f35c-5908-4e2e-9622-c1d7de4d4114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664831258 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1664831258
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2494227596
Short name T97
Test name
Test status
Simulation time 196575576 ps
CPU time 2.64 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:55:40 PM PDT 24
Peak memory 213688 kb
Host smart-e369ffe9-7d77-4d03-8e17-262f1b520b40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494227596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2494227596
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2860370414
Short name T391
Test name
Test status
Simulation time 20722824321 ps
CPU time 14.88 seconds
Started Aug 05 04:55:49 PM PDT 24
Finished Aug 05 04:56:04 PM PDT 24
Peak memory 205528 kb
Host smart-39957403-a057-4a3e-9bba-ed5a2a0afe5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860370414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2860370414
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3333251813
Short name T333
Test name
Test status
Simulation time 7131682489 ps
CPU time 4.17 seconds
Started Aug 05 04:55:58 PM PDT 24
Finished Aug 05 04:56:02 PM PDT 24
Peak memory 205532 kb
Host smart-292a1e80-d11a-4591-99f9-3f805aacd1d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333251813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3333251813
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1385648101
Short name T436
Test name
Test status
Simulation time 620141694 ps
CPU time 1.26 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 205348 kb
Host smart-261d420d-c331-481b-a48d-fd61286d1b9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385648101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1385648101
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2404778421
Short name T458
Test name
Test status
Simulation time 1571444943 ps
CPU time 7.42 seconds
Started Aug 05 04:55:35 PM PDT 24
Finished Aug 05 04:55:43 PM PDT 24
Peak memory 205592 kb
Host smart-2616595a-5373-440f-bb9a-ed5f6dd97c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404778421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2404778421
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.334222951
Short name T353
Test name
Test status
Simulation time 87669360 ps
CPU time 4.32 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:47 PM PDT 24
Peak memory 213884 kb
Host smart-62be80f3-f78b-4b31-aabf-bff3ec6cd96f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334222951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.334222951
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3985242723
Short name T442
Test name
Test status
Simulation time 172348314 ps
CPU time 2.61 seconds
Started Aug 05 04:55:53 PM PDT 24
Finished Aug 05 04:55:56 PM PDT 24
Peak memory 219468 kb
Host smart-2396caa3-4095-47d9-9510-a9df43ce7bd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985242723 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3985242723
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2307966638
Short name T407
Test name
Test status
Simulation time 333674954 ps
CPU time 2.31 seconds
Started Aug 05 04:56:19 PM PDT 24
Finished Aug 05 04:56:22 PM PDT 24
Peak memory 213792 kb
Host smart-be40e19f-44ba-498e-87ee-6bdc10947221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307966638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2307966638
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2387952697
Short name T430
Test name
Test status
Simulation time 19980781146 ps
CPU time 61.87 seconds
Started Aug 05 04:55:44 PM PDT 24
Finished Aug 05 04:56:46 PM PDT 24
Peak memory 205620 kb
Host smart-7650534b-684b-49c0-a498-44a3cbedb513
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387952697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2387952697
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2640216480
Short name T334
Test name
Test status
Simulation time 2538045424 ps
CPU time 6.82 seconds
Started Aug 05 04:55:54 PM PDT 24
Finished Aug 05 04:56:01 PM PDT 24
Peak memory 205604 kb
Host smart-f13c53bf-7373-4e3f-a8f1-9c70dfc88f4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640216480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2640216480
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3759893033
Short name T340
Test name
Test status
Simulation time 626817562 ps
CPU time 1.06 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:47 PM PDT 24
Peak memory 205336 kb
Host smart-e8e4188e-dcda-48cc-9efb-45e3abd9eaad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759893033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3759893033
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2297361479
Short name T375
Test name
Test status
Simulation time 1344305063 ps
CPU time 4.37 seconds
Started Aug 05 04:55:56 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 205664 kb
Host smart-4be74514-acb6-4abf-8498-25c26c7c559f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297361479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2297361479
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3140821634
Short name T380
Test name
Test status
Simulation time 54449988 ps
CPU time 2.36 seconds
Started Aug 05 04:55:58 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 213868 kb
Host smart-c9466ae6-7f39-4939-901e-8b70fefaa571
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140821634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3140821634
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1710048762
Short name T163
Test name
Test status
Simulation time 2378517720 ps
CPU time 22.25 seconds
Started Aug 05 04:55:53 PM PDT 24
Finished Aug 05 04:56:15 PM PDT 24
Peak memory 213952 kb
Host smart-6679202e-f808-4c22-b8cd-3fedca1f8b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710048762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
710048762
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3627065859
Short name T382
Test name
Test status
Simulation time 672982142 ps
CPU time 4.11 seconds
Started Aug 05 04:55:51 PM PDT 24
Finished Aug 05 04:55:55 PM PDT 24
Peak memory 219464 kb
Host smart-f669ae0c-a241-4a1c-9f6c-2beabdbabd0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627065859 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3627065859
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1987487155
Short name T451
Test name
Test status
Simulation time 114907505 ps
CPU time 1.67 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:47 PM PDT 24
Peak memory 213832 kb
Host smart-4a49b648-7e1d-41f1-aa81-26a7f3f5ea2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987487155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1987487155
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1083767287
Short name T305
Test name
Test status
Simulation time 45260501351 ps
CPU time 33.76 seconds
Started Aug 05 04:56:01 PM PDT 24
Finished Aug 05 04:56:34 PM PDT 24
Peak memory 205652 kb
Host smart-035edba1-50a8-47e3-9232-f100fcfd0d05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083767287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1083767287
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3593929390
Short name T348
Test name
Test status
Simulation time 14038899602 ps
CPU time 11.88 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:54 PM PDT 24
Peak memory 205632 kb
Host smart-4835b18a-401d-4eb0-a8a8-5d8499ccb816
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593929390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3593929390
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2530287469
Short name T462
Test name
Test status
Simulation time 111640854 ps
CPU time 0.88 seconds
Started Aug 05 04:55:38 PM PDT 24
Finished Aug 05 04:55:39 PM PDT 24
Peak memory 205292 kb
Host smart-1322cbf6-9b28-48b6-9b73-aabeac5b1742
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530287469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2530287469
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2420693863
Short name T92
Test name
Test status
Simulation time 214657127 ps
CPU time 6.56 seconds
Started Aug 05 04:55:47 PM PDT 24
Finished Aug 05 04:55:54 PM PDT 24
Peak memory 205596 kb
Host smart-7a208f94-d4d6-47fe-832a-46254488524d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420693863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2420693863
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2140117566
Short name T328
Test name
Test status
Simulation time 1487776863 ps
CPU time 4.38 seconds
Started Aug 05 04:55:48 PM PDT 24
Finished Aug 05 04:55:52 PM PDT 24
Peak memory 213948 kb
Host smart-d0b6e48d-9950-473e-9063-34683c4083aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140117566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2140117566
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1163269623
Short name T131
Test name
Test status
Simulation time 1962896003 ps
CPU time 19.83 seconds
Started Aug 05 04:55:53 PM PDT 24
Finished Aug 05 04:56:13 PM PDT 24
Peak memory 213808 kb
Host smart-e8a7098e-3a2b-4f48-9d4d-6ffc28b5382e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163269623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
163269623
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.842431304
Short name T96
Test name
Test status
Simulation time 3707909439 ps
CPU time 37.57 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:56:18 PM PDT 24
Peak memory 213848 kb
Host smart-b04b3567-cdb4-4df0-a816-4620c220c8d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842431304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.842431304
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3315890106
Short name T452
Test name
Test status
Simulation time 380423928 ps
CPU time 2.46 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:45 PM PDT 24
Peak memory 213908 kb
Host smart-d2a52d8b-f799-4920-b68c-aedb447a32aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315890106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3315890106
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3683097255
Short name T460
Test name
Test status
Simulation time 238441263 ps
CPU time 3.68 seconds
Started Aug 05 04:55:24 PM PDT 24
Finished Aug 05 04:55:28 PM PDT 24
Peak memory 221988 kb
Host smart-ed3fe5eb-b623-4841-b374-acb5e6dacef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683097255 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3683097255
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1962967334
Short name T418
Test name
Test status
Simulation time 743913573 ps
CPU time 1.63 seconds
Started Aug 05 04:55:31 PM PDT 24
Finished Aug 05 04:55:33 PM PDT 24
Peak memory 213772 kb
Host smart-65976745-5369-4d4f-8a01-2cb3e35ee415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962967334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1962967334
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1576924347
Short name T325
Test name
Test status
Simulation time 36261331528 ps
CPU time 33.12 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:56:08 PM PDT 24
Peak memory 205560 kb
Host smart-ba2c46f5-e553-483f-b92b-ddbff3a1128d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576924347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1576924347
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2471689607
Short name T318
Test name
Test status
Simulation time 124689002 ps
CPU time 0.89 seconds
Started Aug 05 04:55:31 PM PDT 24
Finished Aug 05 04:55:32 PM PDT 24
Peak memory 205416 kb
Host smart-69913494-0282-4127-95ec-d49cd6147f24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471689607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2471689607
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1827387644
Short name T102
Test name
Test status
Simulation time 4758302250 ps
CPU time 7.18 seconds
Started Aug 05 04:55:31 PM PDT 24
Finished Aug 05 04:55:38 PM PDT 24
Peak memory 205716 kb
Host smart-09effae6-8673-4f6d-8283-cf9aece238b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827387644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1827387644
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2862456534
Short name T309
Test name
Test status
Simulation time 9889781074 ps
CPU time 30.27 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:56:03 PM PDT 24
Peak memory 205648 kb
Host smart-37856c0f-8b62-4ff9-b316-2643f05c9d06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862456534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
862456534
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2910961682
Short name T443
Test name
Test status
Simulation time 817985843 ps
CPU time 2.83 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:28 PM PDT 24
Peak memory 205344 kb
Host smart-a5a8cc73-8735-4980-af25-4e5abc9a1fe1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910961682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2910961682
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2255662209
Short name T354
Test name
Test status
Simulation time 21182955641 ps
CPU time 18.55 seconds
Started Aug 05 04:55:30 PM PDT 24
Finished Aug 05 04:55:49 PM PDT 24
Peak memory 205632 kb
Host smart-6209ecbf-6477-4bd4-9e33-b387b18c492e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255662209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2255662209
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.548990513
Short name T384
Test name
Test status
Simulation time 295027522 ps
CPU time 0.77 seconds
Started Aug 05 04:55:30 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 205272 kb
Host smart-974e40ac-c4bd-4ff1-9763-1620a104e6f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548990513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.548990513
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3470030381
Short name T404
Test name
Test status
Simulation time 744294450 ps
CPU time 1.69 seconds
Started Aug 05 04:55:29 PM PDT 24
Finished Aug 05 04:55:30 PM PDT 24
Peak memory 205344 kb
Host smart-69ad180c-fea7-4722-9a32-991338007b48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470030381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
470030381
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3783366983
Short name T327
Test name
Test status
Simulation time 124280919 ps
CPU time 0.98 seconds
Started Aug 05 04:55:18 PM PDT 24
Finished Aug 05 04:55:19 PM PDT 24
Peak memory 205340 kb
Host smart-612933e8-b249-4317-a67e-82439064a2a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783366983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3783366983
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1998484588
Short name T345
Test name
Test status
Simulation time 124623356 ps
CPU time 0.95 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:55:33 PM PDT 24
Peak memory 205228 kb
Host smart-e9877869-64fb-41f8-8d7d-fd0aef77df45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998484588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1998484588
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2234880215
Short name T109
Test name
Test status
Simulation time 45528447893 ps
CPU time 145.92 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:57:48 PM PDT 24
Peak memory 222144 kb
Host smart-be586d37-64ac-4f96-8051-d6fbb315a19b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234880215 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2234880215
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2537435887
Short name T367
Test name
Test status
Simulation time 683545923 ps
CPU time 2.46 seconds
Started Aug 05 04:55:35 PM PDT 24
Finished Aug 05 04:55:37 PM PDT 24
Peak memory 214048 kb
Host smart-e7cc9eac-4a90-481e-9d5b-513d720eaaaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537435887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2537435887
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3058088320
Short name T114
Test name
Test status
Simulation time 4708676949 ps
CPU time 82.07 seconds
Started Aug 05 04:55:24 PM PDT 24
Finished Aug 05 04:56:46 PM PDT 24
Peak memory 213828 kb
Host smart-fba8de70-84b5-482c-b746-3eef6f955d4b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058088320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3058088320
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3568558981
Short name T448
Test name
Test status
Simulation time 9872763329 ps
CPU time 33.89 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 214036 kb
Host smart-b7ba39ed-07b0-446a-8a59-5abd604741a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568558981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3568558981
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3577355809
Short name T117
Test name
Test status
Simulation time 141657002 ps
CPU time 1.61 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:55:37 PM PDT 24
Peak memory 213736 kb
Host smart-6851c37b-9287-4216-8443-99b7dbe7137d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577355809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3577355809
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.831771969
Short name T394
Test name
Test status
Simulation time 378855416 ps
CPU time 3.66 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:45 PM PDT 24
Peak memory 218908 kb
Host smart-0a461c60-6bb1-4c40-87de-c646c687bb80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831771969 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.831771969
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3399416840
Short name T437
Test name
Test status
Simulation time 226413853 ps
CPU time 2.83 seconds
Started Aug 05 04:55:31 PM PDT 24
Finished Aug 05 04:55:34 PM PDT 24
Peak memory 213740 kb
Host smart-cc7f8f9d-8df4-409a-af6e-0c61ecf9bd4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399416840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3399416840
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4142294839
Short name T439
Test name
Test status
Simulation time 170544858704 ps
CPU time 224.73 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:59:22 PM PDT 24
Peak memory 207916 kb
Host smart-ab6f0568-48c0-4a98-8210-db1eca07fbd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142294839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4142294839
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.396809448
Short name T397
Test name
Test status
Simulation time 5055949078 ps
CPU time 7.95 seconds
Started Aug 05 04:55:19 PM PDT 24
Finished Aug 05 04:55:27 PM PDT 24
Peak memory 205532 kb
Host smart-2bed182b-b57a-4ec9-b8c4-6b183f4bdbc9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396809448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.396809448
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1750222856
Short name T103
Test name
Test status
Simulation time 5753517848 ps
CPU time 14.46 seconds
Started Aug 05 04:55:17 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 205600 kb
Host smart-f0424265-dff1-427a-8440-179e7c5260fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750222856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1750222856
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.754251332
Short name T420
Test name
Test status
Simulation time 961608866 ps
CPU time 2.08 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:55:24 PM PDT 24
Peak memory 205492 kb
Host smart-fd52245b-1fab-4d90-85a3-fadad727ae01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754251332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.754251332
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.630208508
Short name T426
Test name
Test status
Simulation time 405326176 ps
CPU time 1.04 seconds
Started Aug 05 04:55:28 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 205324 kb
Host smart-993f03e9-d529-46f3-ad77-255eb28362b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630208508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.630208508
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.562297585
Short name T400
Test name
Test status
Simulation time 2470307711 ps
CPU time 3.36 seconds
Started Aug 05 04:55:16 PM PDT 24
Finished Aug 05 04:55:20 PM PDT 24
Peak memory 205616 kb
Host smart-af513289-2f4c-40f9-92d7-2f99650fa7f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562297585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.562297585
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4257568352
Short name T388
Test name
Test status
Simulation time 731956400 ps
CPU time 2.79 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 205292 kb
Host smart-16a4364c-5e7e-425f-909c-345e7362e262
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257568352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4257568352
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2172997054
Short name T329
Test name
Test status
Simulation time 1104459753 ps
CPU time 1.18 seconds
Started Aug 05 04:55:28 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 205308 kb
Host smart-db11678b-79f4-415b-997e-c56e8f0834bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172997054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
172997054
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1088934364
Short name T440
Test name
Test status
Simulation time 81384755 ps
CPU time 0.71 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:43 PM PDT 24
Peak memory 205300 kb
Host smart-0cf6f9c1-7b2f-42f9-b544-ce8b5ca45462
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088934364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1088934364
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.278910139
Short name T376
Test name
Test status
Simulation time 171917598 ps
CPU time 0.83 seconds
Started Aug 05 04:55:33 PM PDT 24
Finished Aug 05 04:55:34 PM PDT 24
Peak memory 205328 kb
Host smart-64ea209f-a042-40bc-8105-4c0e9d5d246e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278910139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.278910139
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.462801144
Short name T456
Test name
Test status
Simulation time 273465868 ps
CPU time 4.14 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:32 PM PDT 24
Peak memory 205692 kb
Host smart-88bf83b2-1695-4974-8858-7d092d7a74b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462801144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.462801144
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1164659048
Short name T61
Test name
Test status
Simulation time 56034369710 ps
CPU time 164.57 seconds
Started Aug 05 04:55:21 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 223012 kb
Host smart-da3284ad-533c-4155-b417-ba8ad450feb7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164659048 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1164659048
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.967187586
Short name T393
Test name
Test status
Simulation time 67360182 ps
CPU time 2.63 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:30 PM PDT 24
Peak memory 213936 kb
Host smart-0551fce4-b038-431c-b68d-d712c59912d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967187586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.967187586
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2375715335
Short name T383
Test name
Test status
Simulation time 2373041352 ps
CPU time 9.26 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 214012 kb
Host smart-2ea9de7e-3131-4777-9e7c-a203f5177ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375715335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2375715335
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1634635098
Short name T113
Test name
Test status
Simulation time 3520946184 ps
CPU time 74.63 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:56:41 PM PDT 24
Peak memory 213932 kb
Host smart-c331eda7-82fd-40e8-b919-5274450e8881
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634635098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1634635098
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1506192338
Short name T368
Test name
Test status
Simulation time 4949115951 ps
CPU time 33.92 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:56:00 PM PDT 24
Peak memory 213948 kb
Host smart-2dbd63bc-6dfc-40ea-89b5-410d03337ca6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506192338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1506192338
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4053616168
Short name T94
Test name
Test status
Simulation time 346056548 ps
CPU time 2.64 seconds
Started Aug 05 04:55:52 PM PDT 24
Finished Aug 05 04:55:55 PM PDT 24
Peak memory 213752 kb
Host smart-171ab957-04e7-4924-bdd3-80a70cd6bb87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053616168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4053616168
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.917149841
Short name T416
Test name
Test status
Simulation time 746824786 ps
CPU time 3.64 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:55:51 PM PDT 24
Peak memory 219044 kb
Host smart-5510cbe7-6aaa-40bb-885c-2ba2eb596d78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917149841 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.917149841
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4142396347
Short name T359
Test name
Test status
Simulation time 949658915 ps
CPU time 1.5 seconds
Started Aug 05 04:55:38 PM PDT 24
Finished Aug 05 04:55:39 PM PDT 24
Peak memory 213780 kb
Host smart-5a99d29a-16b5-4632-992d-c9bbef5566f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142396347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4142396347
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2356717358
Short name T342
Test name
Test status
Simulation time 44138063588 ps
CPU time 68.99 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:56:36 PM PDT 24
Peak memory 205624 kb
Host smart-fa986796-4b58-4f71-bf4a-8fa51261b581
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356717358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2356717358
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3649290772
Short name T455
Test name
Test status
Simulation time 33541024573 ps
CPU time 35.2 seconds
Started Aug 05 04:55:36 PM PDT 24
Finished Aug 05 04:56:16 PM PDT 24
Peak memory 205600 kb
Host smart-497e2fe2-3fc0-4d57-b718-293fb4809a26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649290772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3649290772
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4269751254
Short name T311
Test name
Test status
Simulation time 8448543630 ps
CPU time 24.15 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:52 PM PDT 24
Peak memory 205672 kb
Host smart-60058443-4b53-4219-9453-d99b4fffd7f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269751254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4269751254
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3803493339
Short name T365
Test name
Test status
Simulation time 1100713349 ps
CPU time 4.11 seconds
Started Aug 05 04:55:30 PM PDT 24
Finished Aug 05 04:55:34 PM PDT 24
Peak memory 205476 kb
Host smart-9a9e5c69-f0aa-45b9-9b85-b53596bfb2fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803493339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
803493339
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1875062647
Short name T366
Test name
Test status
Simulation time 1533037530 ps
CPU time 2.88 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 205220 kb
Host smart-f2d8234f-7d83-4c27-a68f-1fffdb056a84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875062647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1875062647
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2079760258
Short name T419
Test name
Test status
Simulation time 2735349452 ps
CPU time 8.29 seconds
Started Aug 05 04:55:23 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 205620 kb
Host smart-2f3e125c-1af8-4827-b156-2434ae9bb383
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079760258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2079760258
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3289436385
Short name T66
Test name
Test status
Simulation time 735660832 ps
CPU time 1.52 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:34 PM PDT 24
Peak memory 205336 kb
Host smart-4059fee9-86db-42e3-a29d-e3ba5432d0b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289436385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3289436385
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1621748217
Short name T432
Test name
Test status
Simulation time 146257033 ps
CPU time 1.08 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 205228 kb
Host smart-e0497fbb-474d-44e9-8be4-c293dc75b464
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621748217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
621748217
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1791918423
Short name T403
Test name
Test status
Simulation time 119222140 ps
CPU time 0.94 seconds
Started Aug 05 04:55:24 PM PDT 24
Finished Aug 05 04:55:25 PM PDT 24
Peak memory 205340 kb
Host smart-b6380efa-79b1-4d7f-8aca-adf286bf5c96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791918423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1791918423
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.379355523
Short name T350
Test name
Test status
Simulation time 42379898 ps
CPU time 0.75 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:55:33 PM PDT 24
Peak memory 205336 kb
Host smart-2163278e-397d-4837-9271-8165626f56fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379355523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.379355523
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3611866619
Short name T413
Test name
Test status
Simulation time 2045742563 ps
CPU time 4.1 seconds
Started Aug 05 04:55:30 PM PDT 24
Finished Aug 05 04:55:35 PM PDT 24
Peak memory 205552 kb
Host smart-ea829ceb-161e-4385-a26f-a54eb3060f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611866619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3611866619
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.4250499429
Short name T166
Test name
Test status
Simulation time 17241751324 ps
CPU time 165.89 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:58:12 PM PDT 24
Peak memory 222132 kb
Host smart-915d62fd-b5d7-4079-bfa8-a532363d4c4a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250499429 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.4250499429
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1300056905
Short name T434
Test name
Test status
Simulation time 426696890 ps
CPU time 6.11 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:55:33 PM PDT 24
Peak memory 213920 kb
Host smart-501880af-16af-4722-b1d9-c0da0f9f0144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300056905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1300056905
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3529004822
Short name T415
Test name
Test status
Simulation time 1666691251 ps
CPU time 8.59 seconds
Started Aug 05 04:55:23 PM PDT 24
Finished Aug 05 04:55:32 PM PDT 24
Peak memory 213848 kb
Host smart-d7fe17f9-7457-4501-b9c9-a4e1d43c898a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529004822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3529004822
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.816589296
Short name T423
Test name
Test status
Simulation time 454524867 ps
CPU time 2.31 seconds
Started Aug 05 04:55:33 PM PDT 24
Finished Aug 05 04:55:36 PM PDT 24
Peak memory 218188 kb
Host smart-7a46fe19-7251-4f69-ae1b-64b3faec3b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816589296 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.816589296
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1113523946
Short name T445
Test name
Test status
Simulation time 190007380 ps
CPU time 2.38 seconds
Started Aug 05 04:55:31 PM PDT 24
Finished Aug 05 04:55:33 PM PDT 24
Peak memory 213756 kb
Host smart-1734b15b-a658-4be2-bade-0e214ecb89aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113523946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1113523946
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2327972694
Short name T362
Test name
Test status
Simulation time 3363748323 ps
CPU time 5.59 seconds
Started Aug 05 04:55:46 PM PDT 24
Finished Aug 05 04:55:52 PM PDT 24
Peak memory 205648 kb
Host smart-09168f3c-6b8b-49da-8e28-2aeb56dde636
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327972694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2327972694
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.767656322
Short name T336
Test name
Test status
Simulation time 5135507923 ps
CPU time 13.15 seconds
Started Aug 05 04:55:53 PM PDT 24
Finished Aug 05 04:56:06 PM PDT 24
Peak memory 205628 kb
Host smart-e0c6f7e6-da27-475f-93a5-aeeddb3684f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767656322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.767656322
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1384906107
Short name T389
Test name
Test status
Simulation time 219421048 ps
CPU time 0.75 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:26 PM PDT 24
Peak memory 205328 kb
Host smart-99319a98-9fb9-4161-bc1e-0cd41181cddd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384906107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
384906107
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2958615847
Short name T428
Test name
Test status
Simulation time 686144984 ps
CPU time 3.5 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:38 PM PDT 24
Peak memory 205676 kb
Host smart-745e59a8-727d-4475-b44e-c6ac708199cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958615847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2958615847
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.560654125
Short name T412
Test name
Test status
Simulation time 76902420471 ps
CPU time 819.57 seconds
Started Aug 05 04:55:49 PM PDT 24
Finished Aug 05 05:09:29 PM PDT 24
Peak memory 229100 kb
Host smart-df3c91ed-b09f-476a-a9db-7f04b279baab
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560654125 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.560654125
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1141460567
Short name T346
Test name
Test status
Simulation time 235665078 ps
CPU time 2.91 seconds
Started Aug 05 04:55:28 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 213856 kb
Host smart-6924d189-44d4-4f00-9d78-2c4dc6da3aed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141460567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1141460567
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3879857101
Short name T449
Test name
Test status
Simulation time 5710600239 ps
CPU time 11.38 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:38 PM PDT 24
Peak memory 213948 kb
Host smart-0180243f-49a3-42e0-8da5-7f0dee96246d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879857101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3879857101
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.511308329
Short name T410
Test name
Test status
Simulation time 215981923 ps
CPU time 3.68 seconds
Started Aug 05 04:55:25 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 217396 kb
Host smart-81fe798f-b3bb-4ef5-a659-47a963260dfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511308329 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.511308329
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4227619396
Short name T337
Test name
Test status
Simulation time 1145614511 ps
CPU time 2.45 seconds
Started Aug 05 04:55:51 PM PDT 24
Finished Aug 05 04:55:53 PM PDT 24
Peak memory 213680 kb
Host smart-ce3abd20-f4e2-47f1-8161-86d3b5fb2ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227619396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4227619396
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3132612143
Short name T308
Test name
Test status
Simulation time 29602251940 ps
CPU time 24.19 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:55:57 PM PDT 24
Peak memory 205552 kb
Host smart-cf707583-7e2b-4316-a267-fbeb80b43723
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132612143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3132612143
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.821535645
Short name T351
Test name
Test status
Simulation time 5338062970 ps
CPU time 14.64 seconds
Started Aug 05 04:55:35 PM PDT 24
Finished Aug 05 04:55:49 PM PDT 24
Peak memory 205684 kb
Host smart-478a4b16-2923-46de-89a4-696ae5b423d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821535645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.821535645
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3777236036
Short name T338
Test name
Test status
Simulation time 187812425 ps
CPU time 0.79 seconds
Started Aug 05 04:55:40 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 205228 kb
Host smart-aff8b745-d7a1-451e-bf9b-f7dea94b7666
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777236036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
777236036
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2515106
Short name T107
Test name
Test status
Simulation time 1101594709 ps
CPU time 7.69 seconds
Started Aug 05 04:55:26 PM PDT 24
Finished Aug 05 04:55:34 PM PDT 24
Peak memory 205648 kb
Host smart-070dfabc-d431-4f40-a78d-86a098374146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr
_outstanding.2515106
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2065246380
Short name T399
Test name
Test status
Simulation time 416376848 ps
CPU time 5.91 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:55:38 PM PDT 24
Peak memory 216432 kb
Host smart-7cb7f1bc-0e38-4780-b903-bc1172db66d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065246380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2065246380
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3569783484
Short name T164
Test name
Test status
Simulation time 3936440744 ps
CPU time 15.52 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:50 PM PDT 24
Peak memory 213932 kb
Host smart-8eab3842-67b7-4a89-bbc3-53335bf194c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569783484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3569783484
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3810423498
Short name T326
Test name
Test status
Simulation time 389936818 ps
CPU time 3.14 seconds
Started Aug 05 04:55:29 PM PDT 24
Finished Aug 05 04:55:32 PM PDT 24
Peak memory 218780 kb
Host smart-b5a95c0a-36aa-497a-a831-7fc8381c79a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810423498 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3810423498
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.200442539
Short name T344
Test name
Test status
Simulation time 122706004 ps
CPU time 1.54 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:47 PM PDT 24
Peak memory 213820 kb
Host smart-71634c70-0cb0-47d5-b46e-f38417fd4e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200442539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.200442539
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1990854893
Short name T457
Test name
Test status
Simulation time 72375180071 ps
CPU time 48.86 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:56:28 PM PDT 24
Peak memory 205660 kb
Host smart-23f781ad-18c8-4944-9525-dc36503036e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990854893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1990854893
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4205641101
Short name T349
Test name
Test status
Simulation time 1018924950 ps
CPU time 1.59 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 205528 kb
Host smart-f9e172b9-e220-4b2b-9523-7f56cac4d2a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205641101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4
205641101
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1990140397
Short name T459
Test name
Test status
Simulation time 122767641 ps
CPU time 0.91 seconds
Started Aug 05 04:55:28 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 205228 kb
Host smart-9d566696-391e-41d9-a495-9a1f7449e2ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990140397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
990140397
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2076143564
Short name T90
Test name
Test status
Simulation time 249671078 ps
CPU time 3.6 seconds
Started Aug 05 04:55:47 PM PDT 24
Finished Aug 05 04:55:51 PM PDT 24
Peak memory 205340 kb
Host smart-79631c68-112a-459e-8410-63c08dcafa01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076143564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2076143564
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3299420990
Short name T386
Test name
Test status
Simulation time 40546035212 ps
CPU time 134.65 seconds
Started Aug 05 04:55:42 PM PDT 24
Finished Aug 05 04:57:56 PM PDT 24
Peak memory 222096 kb
Host smart-e6706ad8-ce6d-4ebb-8046-7059ffca578d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299420990 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3299420990
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4040642971
Short name T317
Test name
Test status
Simulation time 247322533 ps
CPU time 5.01 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:50 PM PDT 24
Peak memory 213868 kb
Host smart-ee8ed5b4-c55c-4e25-9ba9-29f218e0cc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040642971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4040642971
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1024365032
Short name T130
Test name
Test status
Simulation time 3761773807 ps
CPU time 10.26 seconds
Started Aug 05 04:55:43 PM PDT 24
Finished Aug 05 04:55:53 PM PDT 24
Peak memory 214040 kb
Host smart-b1790651-45e7-4402-a2a0-e6fe7ede8d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024365032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1024365032
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3567000560
Short name T378
Test name
Test status
Simulation time 105956957 ps
CPU time 4.39 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:32 PM PDT 24
Peak memory 221980 kb
Host smart-486ca0f4-7963-4736-bf28-ad6d0da0dc2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567000560 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3567000560
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3366507002
Short name T116
Test name
Test status
Simulation time 193072158 ps
CPU time 2.65 seconds
Started Aug 05 04:55:32 PM PDT 24
Finished Aug 05 04:55:35 PM PDT 24
Peak memory 213684 kb
Host smart-39f8170a-c113-4cbf-820a-05876974ea0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366507002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3366507002
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3426528549
Short name T357
Test name
Test status
Simulation time 11851396806 ps
CPU time 20.45 seconds
Started Aug 05 04:55:34 PM PDT 24
Finished Aug 05 04:55:54 PM PDT 24
Peak memory 205576 kb
Host smart-0a04c170-ace6-4a43-bab0-c56a92e35992
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426528549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3426528549
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1033904945
Short name T312
Test name
Test status
Simulation time 1697488572 ps
CPU time 1.67 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:46 PM PDT 24
Peak memory 205552 kb
Host smart-5193816d-bea1-45f4-8146-572726618057
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033904945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
033904945
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3419286102
Short name T347
Test name
Test status
Simulation time 630976821 ps
CPU time 1.38 seconds
Started Aug 05 04:55:56 PM PDT 24
Finished Aug 05 04:55:58 PM PDT 24
Peak memory 205268 kb
Host smart-053ce6d1-331d-4ff0-80d9-ef296538e0f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419286102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
419286102
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.123322189
Short name T106
Test name
Test status
Simulation time 674473129 ps
CPU time 7.65 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:34 PM PDT 24
Peak memory 205664 kb
Host smart-38f56b18-0ed3-47d5-9aab-4de131292ef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123322189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.123322189
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4016721161
Short name T401
Test name
Test status
Simulation time 78121801889 ps
CPU time 71.29 seconds
Started Aug 05 04:55:58 PM PDT 24
Finished Aug 05 04:57:09 PM PDT 24
Peak memory 226300 kb
Host smart-093c437b-9339-485a-a8a9-07c76a78945a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016721161 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4016721161
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3515175724
Short name T321
Test name
Test status
Simulation time 162698629 ps
CPU time 3.04 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:30 PM PDT 24
Peak memory 213856 kb
Host smart-ba6529a3-fb31-4362-9b6b-be1cc65375ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515175724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3515175724
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3510197033
Short name T158
Test name
Test status
Simulation time 1430937917 ps
CPU time 17.91 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:45 PM PDT 24
Peak memory 213764 kb
Host smart-1621a3ac-992b-4390-b11e-5de381ae1af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510197033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3510197033
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.504061794
Short name T461
Test name
Test status
Simulation time 266000174 ps
CPU time 2.87 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:55:40 PM PDT 24
Peak memory 218704 kb
Host smart-14658a31-0f20-4db8-afe3-de32e1ab2977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504061794 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.504061794
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.193170581
Short name T99
Test name
Test status
Simulation time 948117561 ps
CPU time 2.55 seconds
Started Aug 05 04:55:29 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 213720 kb
Host smart-14f4c29a-42f1-4f22-92a5-eaf580ac48e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193170581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.193170581
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.379824033
Short name T314
Test name
Test status
Simulation time 4176478621 ps
CPU time 3.88 seconds
Started Aug 05 04:55:27 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 205628 kb
Host smart-df137a72-5341-4317-9ed8-6f655b3564b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379824033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.379824033
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3046757960
Short name T319
Test name
Test status
Simulation time 2510346377 ps
CPU time 2.62 seconds
Started Aug 05 04:55:39 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 205644 kb
Host smart-8a723627-5db1-44e9-ba14-16fe554c45a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046757960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
046757960
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.324603630
Short name T339
Test name
Test status
Simulation time 296976054 ps
CPU time 0.92 seconds
Started Aug 05 04:55:47 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 205348 kb
Host smart-de230a43-1e82-4b1d-9878-9d5d3fd30a39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324603630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.324603630
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.430388701
Short name T421
Test name
Test status
Simulation time 451001654 ps
CPU time 7.82 seconds
Started Aug 05 04:55:53 PM PDT 24
Finished Aug 05 04:56:01 PM PDT 24
Peak memory 205632 kb
Host smart-36b8b43b-2e40-4c2c-9a07-2ccefc50aa44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430388701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.430388701
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2870954250
Short name T358
Test name
Test status
Simulation time 27801527921 ps
CPU time 150.8 seconds
Started Aug 05 04:55:22 PM PDT 24
Finished Aug 05 04:57:53 PM PDT 24
Peak memory 214516 kb
Host smart-33270c11-22d4-46e1-bb45-19fd6c6cce7e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870954250 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2870954250
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2738408043
Short name T323
Test name
Test status
Simulation time 212756812 ps
CPU time 3.47 seconds
Started Aug 05 04:55:45 PM PDT 24
Finished Aug 05 04:55:48 PM PDT 24
Peak memory 213868 kb
Host smart-b4a8009b-fc9f-4262-b946-facac99a8bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738408043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2738408043
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3866479042
Short name T128
Test name
Test status
Simulation time 5113105657 ps
CPU time 19.87 seconds
Started Aug 05 04:55:37 PM PDT 24
Finished Aug 05 04:55:58 PM PDT 24
Peak memory 214008 kb
Host smart-67c86e1c-f324-4062-94b3-67cf2f68073f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866479042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3866479042
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2976234115
Short name T174
Test name
Test status
Simulation time 48589018 ps
CPU time 0.79 seconds
Started Aug 05 06:00:23 PM PDT 24
Finished Aug 05 06:00:24 PM PDT 24
Peak memory 205288 kb
Host smart-b2dd8ff8-7d94-41e7-bc67-89d0ad256ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976234115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2976234115
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2915264906
Short name T254
Test name
Test status
Simulation time 10371580200 ps
CPU time 25.63 seconds
Started Aug 05 06:00:13 PM PDT 24
Finished Aug 05 06:00:38 PM PDT 24
Peak memory 213988 kb
Host smart-a1449754-ef5b-463d-8c54-4c027e0e6613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915264906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2915264906
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2197671204
Short name T198
Test name
Test status
Simulation time 5183423370 ps
CPU time 4.11 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:15 PM PDT 24
Peak memory 215040 kb
Host smart-da1487d2-e2c6-4e91-a8a6-cde997964f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197671204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2197671204
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2903282838
Short name T20
Test name
Test status
Simulation time 457421710 ps
CPU time 1.37 seconds
Started Aug 05 06:00:12 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 205260 kb
Host smart-add4308b-7603-4c51-a964-89f963c90bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903282838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2903282838
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3765103452
Short name T125
Test name
Test status
Simulation time 164779801 ps
CPU time 1.1 seconds
Started Aug 05 06:00:13 PM PDT 24
Finished Aug 05 06:00:14 PM PDT 24
Peak memory 205312 kb
Host smart-cdb581e1-4a06-4ed9-86b0-d4a168d992a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765103452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3765103452
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2290252128
Short name T271
Test name
Test status
Simulation time 63859819 ps
CPU time 0.8 seconds
Started Aug 05 06:00:15 PM PDT 24
Finished Aug 05 06:00:16 PM PDT 24
Peak memory 205296 kb
Host smart-444ac541-0dea-4394-a493-db28f9839867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290252128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2290252128
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1599143024
Short name T7
Test name
Test status
Simulation time 109023861 ps
CPU time 1.05 seconds
Started Aug 05 06:00:17 PM PDT 24
Finished Aug 05 06:00:19 PM PDT 24
Peak memory 215524 kb
Host smart-1ef4f1b2-2450-4d66-a52d-d0ef72d733a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599143024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1599143024
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.75561796
Short name T260
Test name
Test status
Simulation time 953129350 ps
CPU time 3.52 seconds
Started Aug 05 06:00:12 PM PDT 24
Finished Aug 05 06:00:15 PM PDT 24
Peak memory 205612 kb
Host smart-839e39c8-223f-4cbf-adbd-24981730771b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75561796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_
access.75561796
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.4164867450
Short name T41
Test name
Test status
Simulation time 553106279 ps
CPU time 1.43 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 205496 kb
Host smart-18cfcb41-48d8-45fa-b111-aae97c228058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164867450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.4164867450
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4023112395
Short name T239
Test name
Test status
Simulation time 447352377 ps
CPU time 1.23 seconds
Started Aug 05 06:00:12 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 205380 kb
Host smart-66ee6ac7-df71-42d6-a8d2-24c6aee144c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023112395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4023112395
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3188475179
Short name T203
Test name
Test status
Simulation time 141322883 ps
CPU time 0.74 seconds
Started Aug 05 06:00:17 PM PDT 24
Finished Aug 05 06:00:18 PM PDT 24
Peak memory 205300 kb
Host smart-65c5c4ae-bef4-45b2-8ce0-fb7f901735a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188475179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3188475179
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3707036343
Short name T302
Test name
Test status
Simulation time 2247818570 ps
CPU time 2.21 seconds
Started Aug 05 06:00:15 PM PDT 24
Finished Aug 05 06:00:17 PM PDT 24
Peak memory 205268 kb
Host smart-3b290580-3c4e-432b-9c52-c8c0cfe49ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707036343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3707036343
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2833112715
Short name T55
Test name
Test status
Simulation time 456610426 ps
CPU time 1.93 seconds
Started Aug 05 06:00:17 PM PDT 24
Finished Aug 05 06:00:19 PM PDT 24
Peak memory 205276 kb
Host smart-e7ee4b97-fd8b-49aa-b0f6-c721a2b05300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833112715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2833112715
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.668595400
Short name T235
Test name
Test status
Simulation time 225245317 ps
CPU time 0.75 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 205252 kb
Host smart-cc8e004d-a7fa-4686-bfd9-0fa3d4d383eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668595400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.668595400
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3278273929
Short name T287
Test name
Test status
Simulation time 149709152 ps
CPU time 1.12 seconds
Started Aug 05 06:00:13 PM PDT 24
Finished Aug 05 06:00:14 PM PDT 24
Peak memory 205288 kb
Host smart-9a0a2294-0892-40e3-a661-ff1aa69f9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278273929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3278273929
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1985879439
Short name T251
Test name
Test status
Simulation time 430176240 ps
CPU time 1.79 seconds
Started Aug 05 06:00:14 PM PDT 24
Finished Aug 05 06:00:16 PM PDT 24
Peak memory 205280 kb
Host smart-126acb43-cd6b-4423-bc65-1511cde28d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985879439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1985879439
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1580814243
Short name T248
Test name
Test status
Simulation time 649632712 ps
CPU time 1.68 seconds
Started Aug 05 06:00:13 PM PDT 24
Finished Aug 05 06:00:14 PM PDT 24
Peak memory 213520 kb
Host smart-c4796e10-b915-4619-9e82-5af98d001598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580814243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1580814243
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1314926605
Short name T286
Test name
Test status
Simulation time 222499119 ps
CPU time 1.11 seconds
Started Aug 05 06:00:17 PM PDT 24
Finished Aug 05 06:00:19 PM PDT 24
Peak memory 205284 kb
Host smart-ee255489-779a-4d8d-b13a-c2a0a6afc9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314926605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1314926605
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2016677590
Short name T81
Test name
Test status
Simulation time 2200781967 ps
CPU time 7.01 seconds
Started Aug 05 06:00:13 PM PDT 24
Finished Aug 05 06:00:20 PM PDT 24
Peak memory 205752 kb
Host smart-d39e3a17-ed84-428d-8f8d-4ef946a92bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016677590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2016677590
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.634984660
Short name T172
Test name
Test status
Simulation time 5215328045 ps
CPU time 7.92 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:20 PM PDT 24
Peak memory 205628 kb
Host smart-a8bd57f1-db9a-431c-8b30-cd54ce3cb1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634984660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.634984660
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2832626485
Short name T142
Test name
Test status
Simulation time 3307313535 ps
CPU time 5.12 seconds
Started Aug 05 06:00:24 PM PDT 24
Finished Aug 05 06:00:30 PM PDT 24
Peak memory 205568 kb
Host smart-8a128a7f-10fe-45a9-9bcb-6734975c4ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832626485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2832626485
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2925075660
Short name T60
Test name
Test status
Simulation time 8048017905 ps
CPU time 12.17 seconds
Started Aug 05 06:00:14 PM PDT 24
Finished Aug 05 06:00:26 PM PDT 24
Peak memory 205652 kb
Host smart-8899f465-5a46-4805-9a1f-a8e447ac6e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925075660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2925075660
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.4240097421
Short name T48
Test name
Test status
Simulation time 200271452 ps
CPU time 0.76 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:29 PM PDT 24
Peak memory 205328 kb
Host smart-391663cc-5ce3-4398-917f-06b3b9d29fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240097421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4240097421
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4189762200
Short name T193
Test name
Test status
Simulation time 158974146 ps
CPU time 0.8 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:32 PM PDT 24
Peak memory 205244 kb
Host smart-c151e8b0-34f7-4e72-9a56-2d6d1182de9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189762200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4189762200
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2158072130
Short name T212
Test name
Test status
Simulation time 24357693147 ps
CPU time 71.36 seconds
Started Aug 05 06:00:23 PM PDT 24
Finished Aug 05 06:01:34 PM PDT 24
Peak memory 214004 kb
Host smart-9eedb5fd-aded-43e3-8da3-c4858c8003db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158072130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2158072130
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.495121916
Short name T188
Test name
Test status
Simulation time 9915112831 ps
CPU time 9.73 seconds
Started Aug 05 06:00:24 PM PDT 24
Finished Aug 05 06:00:33 PM PDT 24
Peak memory 213996 kb
Host smart-18986658-c9d3-45d9-a213-434fe8a602af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495121916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.495121916
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.829221828
Short name T21
Test name
Test status
Simulation time 291556475 ps
CPU time 0.91 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:29 PM PDT 24
Peak memory 205332 kb
Host smart-b7b0453d-195e-4303-87c0-4d49d8987d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829221828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.829221828
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2366192240
Short name T18
Test name
Test status
Simulation time 148177489 ps
CPU time 0.93 seconds
Started Aug 05 06:00:25 PM PDT 24
Finished Aug 05 06:00:26 PM PDT 24
Peak memory 205292 kb
Host smart-7157350f-549b-4dd7-9dbc-788a70f62f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366192240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2366192240
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.852638858
Short name T34
Test name
Test status
Simulation time 191603412 ps
CPU time 0.85 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:29 PM PDT 24
Peak memory 205300 kb
Host smart-6f28ac2f-35fe-4b3f-80e1-3e584d8e1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852638858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.852638858
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.531470172
Short name T4
Test name
Test status
Simulation time 563745986 ps
CPU time 1.03 seconds
Started Aug 05 06:00:21 PM PDT 24
Finished Aug 05 06:00:22 PM PDT 24
Peak memory 205304 kb
Host smart-a3f9008b-0515-4e80-bf81-236c5df326ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531470172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.531470172
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2307508236
Short name T170
Test name
Test status
Simulation time 131950992 ps
CPU time 0.84 seconds
Started Aug 05 06:00:23 PM PDT 24
Finished Aug 05 06:00:24 PM PDT 24
Peak memory 205308 kb
Host smart-9ff6eaae-3091-40e9-b51e-35abb3eee665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307508236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2307508236
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2459384211
Short name T76
Test name
Test status
Simulation time 43059618 ps
CPU time 0.91 seconds
Started Aug 05 06:00:27 PM PDT 24
Finished Aug 05 06:00:28 PM PDT 24
Peak memory 215828 kb
Host smart-717081de-7e72-4b92-8bd4-f8b26b08a6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459384211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2459384211
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.607955082
Short name T143
Test name
Test status
Simulation time 10884758297 ps
CPU time 30.18 seconds
Started Aug 05 06:00:25 PM PDT 24
Finished Aug 05 06:00:56 PM PDT 24
Peak memory 214004 kb
Host smart-c1785f83-6940-4ffa-b388-0ba30951ac42
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607955082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.607955082
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4199047457
Short name T29
Test name
Test status
Simulation time 277138165 ps
CPU time 1.41 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:30 PM PDT 24
Peak memory 205328 kb
Host smart-edd08c84-6134-41a6-9b14-b4de67095e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199047457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4199047457
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.4091253852
Short name T153
Test name
Test status
Simulation time 598277569 ps
CPU time 1.53 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:30 PM PDT 24
Peak memory 205296 kb
Host smart-1e175a4d-a4bd-4890-b135-eea9d7cb03b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091253852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4091253852
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.9310862
Short name T211
Test name
Test status
Simulation time 717600494 ps
CPU time 2.63 seconds
Started Aug 05 06:00:24 PM PDT 24
Finished Aug 05 06:00:26 PM PDT 24
Peak memory 205288 kb
Host smart-3cb9dff8-b219-4795-8010-18339cc61415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9310862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.9310862
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2701795437
Short name T216
Test name
Test status
Simulation time 736565227 ps
CPU time 1.89 seconds
Started Aug 05 06:00:25 PM PDT 24
Finished Aug 05 06:00:27 PM PDT 24
Peak memory 205148 kb
Host smart-c8e76f25-5587-4eac-bb2b-048e7479aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701795437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2701795437
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2268940303
Short name T3
Test name
Test status
Simulation time 334099643 ps
CPU time 0.93 seconds
Started Aug 05 06:00:22 PM PDT 24
Finished Aug 05 06:00:23 PM PDT 24
Peak memory 205324 kb
Host smart-6765d7fa-9d36-46e6-955b-cadb136bba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268940303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2268940303
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3856768639
Short name T217
Test name
Test status
Simulation time 238372347 ps
CPU time 1.42 seconds
Started Aug 05 06:00:21 PM PDT 24
Finished Aug 05 06:00:23 PM PDT 24
Peak memory 205296 kb
Host smart-18f5caeb-9ac3-46fd-888d-d0d0bdff1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856768639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3856768639
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.778824607
Short name T2
Test name
Test status
Simulation time 547871408 ps
CPU time 1.44 seconds
Started Aug 05 06:00:20 PM PDT 24
Finished Aug 05 06:00:22 PM PDT 24
Peak memory 205300 kb
Host smart-561a9130-ce64-4070-bd2c-3274d3dfce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778824607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.778824607
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.359551942
Short name T301
Test name
Test status
Simulation time 1119733989 ps
CPU time 3.95 seconds
Started Aug 05 06:00:25 PM PDT 24
Finished Aug 05 06:00:29 PM PDT 24
Peak memory 205500 kb
Host smart-2ba0995a-bf9b-4682-8fea-1f3849e5546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359551942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.359551942
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.709428311
Short name T249
Test name
Test status
Simulation time 463170760 ps
CPU time 1.74 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:31 PM PDT 24
Peak memory 213540 kb
Host smart-071fa051-efb8-4079-bf22-862fe9818ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709428311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.709428311
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3772620848
Short name T281
Test name
Test status
Simulation time 321383746 ps
CPU time 1.13 seconds
Started Aug 05 06:00:30 PM PDT 24
Finished Aug 05 06:00:31 PM PDT 24
Peak memory 205272 kb
Host smart-af4f75b6-6c60-41b0-a923-888daa2b7cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772620848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3772620848
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2145554014
Short name T39
Test name
Test status
Simulation time 130622761 ps
CPU time 0.93 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:29 PM PDT 24
Peak memory 213492 kb
Host smart-b01f52a0-bd5d-4ec2-acac-942a755cd7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145554014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2145554014
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2591091984
Short name T78
Test name
Test status
Simulation time 1334535568 ps
CPU time 3.06 seconds
Started Aug 05 06:00:23 PM PDT 24
Finished Aug 05 06:00:26 PM PDT 24
Peak memory 205476 kb
Host smart-bf33bd1d-eccb-4ae5-b616-fa9ebc7be39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591091984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2591091984
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.4224374015
Short name T224
Test name
Test status
Simulation time 1352738140 ps
CPU time 1.82 seconds
Started Aug 05 06:00:23 PM PDT 24
Finished Aug 05 06:00:25 PM PDT 24
Peak memory 205660 kb
Host smart-41e4f69f-d38c-4f1f-879e-1b952e595465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224374015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4224374015
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3545411477
Short name T69
Test name
Test status
Simulation time 738872174 ps
CPU time 2.91 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:34 PM PDT 24
Peak memory 228916 kb
Host smart-0336b75e-4fc0-4a21-929f-cadd52c4a89e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545411477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3545411477
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.545163500
Short name T294
Test name
Test status
Simulation time 1639294026 ps
CPU time 5.35 seconds
Started Aug 05 06:00:24 PM PDT 24
Finished Aug 05 06:00:29 PM PDT 24
Peak memory 205540 kb
Host smart-ec41560f-cfd5-4076-b353-886a6a0fd2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545163500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.545163500
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.462599747
Short name T293
Test name
Test status
Simulation time 4072568111 ps
CPU time 3.21 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:34 PM PDT 24
Peak memory 205640 kb
Host smart-bfdccea1-acbf-4dc2-9c5c-fd19d2d243fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462599747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.462599747
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.809867351
Short name T82
Test name
Test status
Simulation time 49131343550 ps
CPU time 219.26 seconds
Started Aug 05 06:00:30 PM PDT 24
Finished Aug 05 06:04:09 PM PDT 24
Peak memory 222120 kb
Host smart-e85aaf3f-1824-43e3-95f6-69926aff1507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809867351 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.809867351
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.368857845
Short name T86
Test name
Test status
Simulation time 45993450 ps
CPU time 0.76 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 205272 kb
Host smart-5d8fecdf-664b-4380-8fe1-a8800969f671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368857845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.368857845
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1110163859
Short name T183
Test name
Test status
Simulation time 5466853997 ps
CPU time 9.4 seconds
Started Aug 05 06:00:39 PM PDT 24
Finished Aug 05 06:00:49 PM PDT 24
Peak memory 213964 kb
Host smart-538bdb29-363e-4387-98f0-5ab8ef319cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110163859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1110163859
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1626538517
Short name T144
Test name
Test status
Simulation time 5875888032 ps
CPU time 5.51 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:00:44 PM PDT 24
Peak memory 205800 kb
Host smart-7771970d-1885-499a-8506-38eb39690753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626538517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1626538517
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2545126495
Short name T288
Test name
Test status
Simulation time 1919412261 ps
CPU time 3.3 seconds
Started Aug 05 06:00:41 PM PDT 24
Finished Aug 05 06:00:44 PM PDT 24
Peak memory 205656 kb
Host smart-1bc0313e-9694-4934-9d28-a74f48cc570c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545126495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2545126495
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1191824034
Short name T14
Test name
Test status
Simulation time 2615187795 ps
CPU time 2.08 seconds
Started Aug 05 06:00:41 PM PDT 24
Finished Aug 05 06:00:43 PM PDT 24
Peak memory 213952 kb
Host smart-a2f683f6-4786-4563-bcc2-13e39f28a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191824034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1191824034
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1362778003
Short name T268
Test name
Test status
Simulation time 2638934464 ps
CPU time 6.3 seconds
Started Aug 05 06:00:48 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 205580 kb
Host smart-3a05bc03-9554-4232-851b-840f3367a0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362778003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1362778003
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3917880011
Short name T171
Test name
Test status
Simulation time 69041023 ps
CPU time 0.75 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:46 PM PDT 24
Peak memory 205304 kb
Host smart-c5f4c981-9e53-4227-8df4-e753cc47bb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917880011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3917880011
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.384821391
Short name T266
Test name
Test status
Simulation time 6857342319 ps
CPU time 21.54 seconds
Started Aug 05 06:00:39 PM PDT 24
Finished Aug 05 06:01:01 PM PDT 24
Peak memory 213952 kb
Host smart-e46ef50d-7a6a-4bb1-969e-6edda2a973be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384821391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.384821391
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3004216296
Short name T197
Test name
Test status
Simulation time 3849862627 ps
CPU time 11.95 seconds
Started Aug 05 06:00:47 PM PDT 24
Finished Aug 05 06:00:59 PM PDT 24
Peak memory 213996 kb
Host smart-bc521a3f-e8b0-409a-8c36-ce3f7e2867cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004216296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3004216296
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.716702830
Short name T199
Test name
Test status
Simulation time 2083374826 ps
CPU time 2.38 seconds
Started Aug 05 06:00:39 PM PDT 24
Finished Aug 05 06:00:42 PM PDT 24
Peak memory 213816 kb
Host smart-95152e29-85a6-4d77-ac17-0b5481d866fa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716702830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.716702830
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3553132422
Short name T296
Test name
Test status
Simulation time 6957857456 ps
CPU time 8.65 seconds
Started Aug 05 06:00:48 PM PDT 24
Finished Aug 05 06:00:57 PM PDT 24
Peak memory 213984 kb
Host smart-c3f1cd26-a7cb-47a8-96f1-4c08547010ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553132422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3553132422
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1442827349
Short name T138
Test name
Test status
Simulation time 1777674046 ps
CPU time 3.22 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:00:47 PM PDT 24
Peak memory 213664 kb
Host smart-fe15a01a-f061-41f0-8db3-e1a4a11b489c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442827349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1442827349
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2389913364
Short name T180
Test name
Test status
Simulation time 83881199 ps
CPU time 0.72 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:46 PM PDT 24
Peak memory 205308 kb
Host smart-e7b1cb5e-6d75-412b-b899-83e3fc445762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389913364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2389913364
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1110736489
Short name T136
Test name
Test status
Simulation time 36909690101 ps
CPU time 100.97 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:02:25 PM PDT 24
Peak memory 213952 kb
Host smart-f9b87901-ee7d-4448-aabe-7ad1ab4acf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110736489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1110736489
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3576134645
Short name T264
Test name
Test status
Simulation time 4876527226 ps
CPU time 14.5 seconds
Started Aug 05 06:00:50 PM PDT 24
Finished Aug 05 06:01:05 PM PDT 24
Peak memory 213916 kb
Host smart-e5541aa3-3c48-4129-a5b1-c47bb430341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576134645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3576134645
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.145533008
Short name T73
Test name
Test status
Simulation time 9978843666 ps
CPU time 9.55 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 213916 kb
Host smart-e1a0304a-5bb3-4c1a-b2c2-75b8e1b74004
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145533008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.145533008
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2523631154
Short name T276
Test name
Test status
Simulation time 2626779312 ps
CPU time 3.25 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 205748 kb
Host smart-4991f9bd-5e11-48b4-9810-d53ac5e6b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523631154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2523631154
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.637334202
Short name T257
Test name
Test status
Simulation time 4182316550 ps
CPU time 7.2 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:00:51 PM PDT 24
Peak memory 205624 kb
Host smart-d017aed5-fe9c-4fb4-90c7-d9b1508c6fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637334202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.637334202
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4244309548
Short name T244
Test name
Test status
Simulation time 44633417 ps
CPU time 0.81 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:46 PM PDT 24
Peak memory 205280 kb
Host smart-4482d846-fe79-4f4b-a08d-ceb4e2ca58a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244309548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4244309548
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.4050150517
Short name T177
Test name
Test status
Simulation time 10300456011 ps
CPU time 8.68 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 213928 kb
Host smart-4ea65faa-83b6-4490-9d29-519f70aac38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050150517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4050150517
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2661767043
Short name T214
Test name
Test status
Simulation time 1368417883 ps
CPU time 3.01 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:00:47 PM PDT 24
Peak memory 205704 kb
Host smart-7d5973b7-ec72-44da-ae15-13780e209395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661767043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2661767043
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2407384588
Short name T213
Test name
Test status
Simulation time 2867346224 ps
CPU time 4.82 seconds
Started Aug 05 06:00:48 PM PDT 24
Finished Aug 05 06:00:53 PM PDT 24
Peak memory 205760 kb
Host smart-49c3dec2-7e22-4bc3-86fe-9c0f72a11bcd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407384588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2407384588
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3274356538
Short name T270
Test name
Test status
Simulation time 12088205665 ps
CPU time 17.51 seconds
Started Aug 05 06:00:47 PM PDT 24
Finished Aug 05 06:01:04 PM PDT 24
Peak memory 213984 kb
Host smart-f80497ef-f646-469c-99c0-7bd6cd325181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274356538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3274356538
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.502462613
Short name T28
Test name
Test status
Simulation time 4481468206 ps
CPU time 5.99 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:52 PM PDT 24
Peak memory 213684 kb
Host smart-6e28a246-6e66-44af-8872-122df86dd97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502462613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.502462613
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1078404358
Short name T215
Test name
Test status
Simulation time 74767399 ps
CPU time 0.78 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:46 PM PDT 24
Peak memory 205292 kb
Host smart-a16efc2d-8c46-4364-818f-1d86b9ade445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078404358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1078404358
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2707777914
Short name T139
Test name
Test status
Simulation time 6271149926 ps
CPU time 9.65 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 214008 kb
Host smart-0b9429a8-24f6-4622-8848-39609bc95e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707777914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2707777914
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.749062240
Short name T204
Test name
Test status
Simulation time 1473544998 ps
CPU time 1.9 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 205636 kb
Host smart-b1b10da6-3d43-40a5-9472-ba434719257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749062240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.749062240
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1564160021
Short name T256
Test name
Test status
Simulation time 1487829639 ps
CPU time 5.24 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:00:49 PM PDT 24
Peak memory 205708 kb
Host smart-2fd9d555-0d84-4453-bbe1-d42c74e70c87
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564160021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1564160021
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.28667087
Short name T70
Test name
Test status
Simulation time 478969817 ps
CPU time 2.13 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:47 PM PDT 24
Peak memory 205816 kb
Host smart-101ca325-978a-4d94-9a86-b5e56a1ba5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28667087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.28667087
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3547317034
Short name T40
Test name
Test status
Simulation time 2613071730 ps
CPU time 1.65 seconds
Started Aug 05 06:00:46 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 213892 kb
Host smart-e9bb4244-0561-49e3-8918-e43ab1b6877e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547317034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3547317034
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1411455394
Short name T298
Test name
Test status
Simulation time 39989557 ps
CPU time 0.79 seconds
Started Aug 05 06:00:47 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 205312 kb
Host smart-6e922f5d-a901-42a8-8c45-097897522606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411455394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1411455394
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1157510189
Short name T31
Test name
Test status
Simulation time 2170328266 ps
CPU time 3.13 seconds
Started Aug 05 06:00:47 PM PDT 24
Finished Aug 05 06:00:50 PM PDT 24
Peak memory 214020 kb
Host smart-91a0c839-1822-46a1-acda-c64479b1c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157510189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1157510189
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1430557231
Short name T27
Test name
Test status
Simulation time 816564165 ps
CPU time 2.02 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:47 PM PDT 24
Peak memory 205616 kb
Host smart-b180abcd-a616-43bb-a6d3-e782c4cb6432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430557231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1430557231
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3126080432
Short name T57
Test name
Test status
Simulation time 3121081109 ps
CPU time 6.16 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:51 PM PDT 24
Peak memory 205796 kb
Host smart-80b7c4dc-d514-4559-a8e9-51aead4e477c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126080432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3126080432
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2655083155
Short name T145
Test name
Test status
Simulation time 1611343777 ps
CPU time 1.48 seconds
Started Aug 05 06:00:43 PM PDT 24
Finished Aug 05 06:00:45 PM PDT 24
Peak memory 205684 kb
Host smart-ed6366d9-8e2a-4b60-ba51-29b5cae72547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655083155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2655083155
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.4165650999
Short name T285
Test name
Test status
Simulation time 4101207043 ps
CPU time 11.79 seconds
Started Aug 05 06:00:47 PM PDT 24
Finished Aug 05 06:00:59 PM PDT 24
Peak memory 213856 kb
Host smart-08304d09-a488-4f23-85cb-7cb0306a7474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165650999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.4165650999
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3973071853
Short name T184
Test name
Test status
Simulation time 59598132 ps
CPU time 0.69 seconds
Started Aug 05 06:00:50 PM PDT 24
Finished Aug 05 06:00:51 PM PDT 24
Peak memory 205280 kb
Host smart-1d6ab12b-2b22-47fb-876e-55ae9d8077bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973071853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3973071853
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1431328534
Short name T202
Test name
Test status
Simulation time 14467144404 ps
CPU time 13.9 seconds
Started Aug 05 06:00:51 PM PDT 24
Finished Aug 05 06:01:05 PM PDT 24
Peak memory 213932 kb
Host smart-d097f7a2-1d45-4f4e-ac71-59a734237d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431328534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1431328534
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3582601275
Short name T277
Test name
Test status
Simulation time 8069713627 ps
CPU time 17.05 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 205740 kb
Host smart-e420e7f0-9dc0-4711-b9d3-d80d3c5393c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582601275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3582601275
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2157389360
Short name T225
Test name
Test status
Simulation time 1373794704 ps
CPU time 1.91 seconds
Started Aug 05 06:00:47 PM PDT 24
Finished Aug 05 06:00:49 PM PDT 24
Peak memory 205696 kb
Host smart-a3083e02-1e57-40ef-bf5c-7c06221d52c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157389360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2157389360
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.3409881191
Short name T11
Test name
Test status
Simulation time 6947158305 ps
CPU time 12.4 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:01:02 PM PDT 24
Peak memory 213836 kb
Host smart-a63ff2fd-4905-4966-9420-6f48e69d747a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409881191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3409881191
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2233477370
Short name T200
Test name
Test status
Simulation time 40773086 ps
CPU time 0.76 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:00:49 PM PDT 24
Peak memory 205316 kb
Host smart-5da89574-9953-45d0-86d4-739f78ea8240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233477370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2233477370
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3538066228
Short name T195
Test name
Test status
Simulation time 26503328751 ps
CPU time 65.32 seconds
Started Aug 05 06:00:51 PM PDT 24
Finished Aug 05 06:01:56 PM PDT 24
Peak memory 213940 kb
Host smart-7df58c2c-6386-4543-b897-ede113584963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538066228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3538066228
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2639344185
Short name T247
Test name
Test status
Simulation time 12119147241 ps
CPU time 9.88 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:00:59 PM PDT 24
Peak memory 214188 kb
Host smart-7f651a98-6a32-4343-8a66-747f185f411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639344185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2639344185
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3264087301
Short name T209
Test name
Test status
Simulation time 3017205903 ps
CPU time 9.25 seconds
Started Aug 05 06:00:50 PM PDT 24
Finished Aug 05 06:00:59 PM PDT 24
Peak memory 213956 kb
Host smart-5dc2f595-df60-47e2-8fc5-b9e2f795083b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264087301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3264087301
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3166193405
Short name T100
Test name
Test status
Simulation time 3949829753 ps
CPU time 5.86 seconds
Started Aug 05 06:00:51 PM PDT 24
Finished Aug 05 06:00:57 PM PDT 24
Peak memory 205744 kb
Host smart-615a43b0-7bba-432f-b959-74eb267f2f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166193405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3166193405
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1767965273
Short name T135
Test name
Test status
Simulation time 4033723667 ps
CPU time 11.84 seconds
Started Aug 05 06:00:52 PM PDT 24
Finished Aug 05 06:01:04 PM PDT 24
Peak memory 213756 kb
Host smart-d30049d6-d726-4fbb-8a7e-b595b199a1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767965273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1767965273
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.175933216
Short name T186
Test name
Test status
Simulation time 91546396 ps
CPU time 0.93 seconds
Started Aug 05 06:00:51 PM PDT 24
Finished Aug 05 06:00:52 PM PDT 24
Peak memory 205284 kb
Host smart-ba9f05fd-8b13-4f3f-8f7f-3d9da30eeb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175933216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.175933216
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3461886884
Short name T219
Test name
Test status
Simulation time 5547237664 ps
CPU time 4.86 seconds
Started Aug 05 06:00:51 PM PDT 24
Finished Aug 05 06:00:56 PM PDT 24
Peak memory 205760 kb
Host smart-10f1c47e-4db3-4d7b-b946-db5b5994c68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461886884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3461886884
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4293767457
Short name T255
Test name
Test status
Simulation time 3098012753 ps
CPU time 5.4 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 214020 kb
Host smart-2da2c13e-b4e0-4447-bda6-eb9851f7b5b0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293767457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.4293767457
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.918013333
Short name T243
Test name
Test status
Simulation time 7119979793 ps
CPU time 7.12 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:00:56 PM PDT 24
Peak memory 205776 kb
Host smart-b0874d99-582a-411f-978f-91b02915547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918013333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.918013333
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2419118431
Short name T234
Test name
Test status
Simulation time 5816178124 ps
CPU time 6.65 seconds
Started Aug 05 06:00:50 PM PDT 24
Finished Aug 05 06:00:57 PM PDT 24
Peak memory 213876 kb
Host smart-8398fcf6-8b54-4c61-b30f-9d6d16023152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419118431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2419118431
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2113472279
Short name T175
Test name
Test status
Simulation time 81518809 ps
CPU time 0.89 seconds
Started Aug 05 06:01:00 PM PDT 24
Finished Aug 05 06:01:01 PM PDT 24
Peak memory 205276 kb
Host smart-e6f572ee-145e-49dc-9331-053ac3decd8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113472279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2113472279
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2590561162
Short name T182
Test name
Test status
Simulation time 21480193873 ps
CPU time 10.94 seconds
Started Aug 05 06:00:58 PM PDT 24
Finished Aug 05 06:01:09 PM PDT 24
Peak memory 213916 kb
Host smart-7b728fe7-a8b2-4c9c-a738-65713c22244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590561162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2590561162
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.203793519
Short name T63
Test name
Test status
Simulation time 2196935037 ps
CPU time 3.19 seconds
Started Aug 05 06:00:52 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 215064 kb
Host smart-c12a27b7-eec9-4e76-939b-b8e2f6f37917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203793519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.203793519
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4044094613
Short name T292
Test name
Test status
Simulation time 750566143 ps
CPU time 1.72 seconds
Started Aug 05 06:00:50 PM PDT 24
Finished Aug 05 06:00:53 PM PDT 24
Peak memory 213748 kb
Host smart-f1a01c85-3416-40ba-927b-7f7a26b1d13e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044094613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.4044094613
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.413184186
Short name T226
Test name
Test status
Simulation time 4001596362 ps
CPU time 6.33 seconds
Started Aug 05 06:00:52 PM PDT 24
Finished Aug 05 06:00:58 PM PDT 24
Peak memory 213948 kb
Host smart-c8936e2f-1016-4a98-b983-bba381b5bcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413184186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.413184186
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.988002477
Short name T201
Test name
Test status
Simulation time 159345753 ps
CPU time 0.73 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:30 PM PDT 24
Peak memory 205292 kb
Host smart-646d73a0-7288-4db0-b062-2c4ec38b9a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988002477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.988002477
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.4248085943
Short name T291
Test name
Test status
Simulation time 15707979651 ps
CPU time 14.25 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:43 PM PDT 24
Peak memory 213920 kb
Host smart-6e722e2a-66a6-4f70-8222-59f2b018bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248085943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.4248085943
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2183090573
Short name T282
Test name
Test status
Simulation time 7849895618 ps
CPU time 20.71 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 213948 kb
Host smart-164ae56c-2b22-477c-b085-de4cf9798d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183090573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2183090573
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2683592063
Short name T206
Test name
Test status
Simulation time 11120444566 ps
CPU time 31.5 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:01:03 PM PDT 24
Peak memory 213936 kb
Host smart-b411206a-754d-4957-b50e-7df9dd1e0d15
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683592063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2683592063
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1241561305
Short name T263
Test name
Test status
Simulation time 244504004 ps
CPU time 1.03 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:32 PM PDT 24
Peak memory 205300 kb
Host smart-4dbec194-8966-4ac5-aa7f-2dd00b17bc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241561305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1241561305
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1402787192
Short name T207
Test name
Test status
Simulation time 252405412 ps
CPU time 0.77 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:31 PM PDT 24
Peak memory 205272 kb
Host smart-3c661b8b-3400-4378-992c-eccd45c9c48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402787192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1402787192
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2418076053
Short name T273
Test name
Test status
Simulation time 2849690709 ps
CPU time 6.69 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:38 PM PDT 24
Peak memory 205816 kb
Host smart-2e08654c-ee59-4260-83e4-da91aedb9245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418076053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2418076053
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2915841607
Short name T52
Test name
Test status
Simulation time 1275345629 ps
CPU time 4.41 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:32 PM PDT 24
Peak memory 229612 kb
Host smart-230ade3d-5877-4ac8-8e5f-2ae3755ffa04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915841607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2915841607
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1468788492
Short name T89
Test name
Test status
Simulation time 2471475150 ps
CPU time 4.15 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:33 PM PDT 24
Peak memory 213776 kb
Host smart-c86dcb28-7a69-4b57-a0f4-e5da60a50443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468788492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1468788492
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.823234110
Short name T17
Test name
Test status
Simulation time 138192400465 ps
CPU time 2126.67 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:35:55 PM PDT 24
Peak memory 248684 kb
Host smart-66291814-c27e-45f9-9e71-af2a0a22332c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823234110 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.823234110
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.48198601
Short name T208
Test name
Test status
Simulation time 161335052 ps
CPU time 1.1 seconds
Started Aug 05 06:00:56 PM PDT 24
Finished Aug 05 06:00:58 PM PDT 24
Peak memory 205284 kb
Host smart-149c9e5f-904d-456e-87d2-37f361d390c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48198601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.48198601
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1915566425
Short name T210
Test name
Test status
Simulation time 37010313 ps
CPU time 0.75 seconds
Started Aug 05 06:00:57 PM PDT 24
Finished Aug 05 06:00:58 PM PDT 24
Peak memory 205296 kb
Host smart-c3c98143-a8ab-4179-9bef-a94508adbfdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915566425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1915566425
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3310143483
Short name T149
Test name
Test status
Simulation time 6573083093 ps
CPU time 20.57 seconds
Started Aug 05 06:00:58 PM PDT 24
Finished Aug 05 06:01:18 PM PDT 24
Peak memory 213808 kb
Host smart-a722d280-901b-4e9c-98fe-f64354340999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310143483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3310143483
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2763122783
Short name T178
Test name
Test status
Simulation time 7360951964 ps
CPU time 12.8 seconds
Started Aug 05 06:00:59 PM PDT 24
Finished Aug 05 06:01:12 PM PDT 24
Peak memory 213804 kb
Host smart-cc9d3301-8fcc-4b05-9661-3ec04a4fd1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763122783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2763122783
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.32613451
Short name T88
Test name
Test status
Simulation time 119014519 ps
CPU time 0.72 seconds
Started Aug 05 06:00:58 PM PDT 24
Finished Aug 05 06:00:59 PM PDT 24
Peak memory 205280 kb
Host smart-0881513f-1aa5-45e5-b205-85c13468802d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32613451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.32613451
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2980899979
Short name T192
Test name
Test status
Simulation time 3762219861 ps
CPU time 6.45 seconds
Started Aug 05 06:00:54 PM PDT 24
Finished Aug 05 06:01:00 PM PDT 24
Peak memory 205552 kb
Host smart-29029963-a76a-4b7c-91e1-7d5e91abdb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980899979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2980899979
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1497333015
Short name T220
Test name
Test status
Simulation time 50281251 ps
CPU time 0.79 seconds
Started Aug 05 06:00:57 PM PDT 24
Finished Aug 05 06:00:58 PM PDT 24
Peak memory 205292 kb
Host smart-74fe8620-573c-4a21-9cdb-b2e16cbd3f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497333015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1497333015
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.875517289
Short name T233
Test name
Test status
Simulation time 11896589746 ps
CPU time 9.45 seconds
Started Aug 05 06:00:57 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 213740 kb
Host smart-6ad060f6-406f-4ffe-824d-f89e78cfefb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875517289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.875517289
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1013757454
Short name T196
Test name
Test status
Simulation time 41112324 ps
CPU time 0.79 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 205324 kb
Host smart-da13ec3a-fcac-45c0-abe7-e4bbe8c6d7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013757454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1013757454
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3081006078
Short name T45
Test name
Test status
Simulation time 6959453194 ps
CPU time 10.56 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 214680 kb
Host smart-8323d208-d138-492e-9d9c-dd685e04901b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081006078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3081006078
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.300037094
Short name T241
Test name
Test status
Simulation time 79064029 ps
CPU time 0.85 seconds
Started Aug 05 06:01:13 PM PDT 24
Finished Aug 05 06:01:14 PM PDT 24
Peak memory 205300 kb
Host smart-9daf51e1-bfa0-414f-b289-d5adbdf69dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300037094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.300037094
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1605382169
Short name T147
Test name
Test status
Simulation time 7444290443 ps
CPU time 11.97 seconds
Started Aug 05 06:01:04 PM PDT 24
Finished Aug 05 06:01:17 PM PDT 24
Peak memory 213788 kb
Host smart-18e4b68a-6a04-47e8-8613-8c85b883d191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605382169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1605382169
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3202708402
Short name T289
Test name
Test status
Simulation time 56649952 ps
CPU time 0.74 seconds
Started Aug 05 06:01:06 PM PDT 24
Finished Aug 05 06:01:07 PM PDT 24
Peak memory 205284 kb
Host smart-168c3a25-c87a-4d97-af6e-7b8a53ae932c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202708402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3202708402
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1691771857
Short name T15
Test name
Test status
Simulation time 1537474795 ps
CPU time 3.29 seconds
Started Aug 05 06:01:04 PM PDT 24
Finished Aug 05 06:01:08 PM PDT 24
Peak memory 205428 kb
Host smart-22869e4e-fcb9-41c3-85cf-371ae97d6ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691771857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1691771857
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3977858165
Short name T280
Test name
Test status
Simulation time 144667210 ps
CPU time 0.85 seconds
Started Aug 05 06:01:06 PM PDT 24
Finished Aug 05 06:01:07 PM PDT 24
Peak memory 205292 kb
Host smart-fadd6881-6c19-40de-a878-9b0c8b69b4d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977858165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3977858165
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3571916718
Short name T16
Test name
Test status
Simulation time 3562403806 ps
CPU time 6.65 seconds
Started Aug 05 06:01:08 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 213792 kb
Host smart-97180df0-e124-4aaa-afb7-74ee81de631d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571916718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3571916718
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1493791823
Short name T72
Test name
Test status
Simulation time 75773865 ps
CPU time 0.76 seconds
Started Aug 05 06:01:13 PM PDT 24
Finished Aug 05 06:01:14 PM PDT 24
Peak memory 205236 kb
Host smart-0ae2dd94-df87-4c8b-b2ca-94fc4d068fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493791823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1493791823
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2368808930
Short name T10
Test name
Test status
Simulation time 4143354364 ps
CPU time 2.1 seconds
Started Aug 05 06:01:06 PM PDT 24
Finished Aug 05 06:01:08 PM PDT 24
Peak memory 205384 kb
Host smart-424202ab-3fbc-41ab-b877-d68cf662d8ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368808930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2368808930
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2493097900
Short name T205
Test name
Test status
Simulation time 73417092 ps
CPU time 0.74 seconds
Started Aug 05 06:00:33 PM PDT 24
Finished Aug 05 06:00:34 PM PDT 24
Peak memory 205324 kb
Host smart-b1399d5d-99c9-40d3-9b36-61da936457cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493097900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2493097900
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1509445256
Short name T259
Test name
Test status
Simulation time 20743333922 ps
CPU time 63.8 seconds
Started Aug 05 06:00:33 PM PDT 24
Finished Aug 05 06:01:37 PM PDT 24
Peak memory 213980 kb
Host smart-3e1c7c7e-2cd2-48fb-bb83-203e23082c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509445256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1509445256
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3891300552
Short name T228
Test name
Test status
Simulation time 5309947871 ps
CPU time 5.21 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:34 PM PDT 24
Peak memory 213932 kb
Host smart-e9e551f7-e9a2-413d-9c91-169ee196d3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891300552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3891300552
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3146597869
Short name T75
Test name
Test status
Simulation time 1877990319 ps
CPU time 3.88 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:35 PM PDT 24
Peak memory 213856 kb
Host smart-3096752e-a522-43b4-b536-53208fb92c8c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146597869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3146597869
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.2088554956
Short name T269
Test name
Test status
Simulation time 220211157 ps
CPU time 0.94 seconds
Started Aug 05 06:00:32 PM PDT 24
Finished Aug 05 06:00:33 PM PDT 24
Peak memory 205300 kb
Host smart-936dbaa8-d803-4e18-8f6d-ce3d39d5b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088554956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2088554956
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2029307094
Short name T279
Test name
Test status
Simulation time 814658315 ps
CPU time 2.68 seconds
Started Aug 05 06:00:29 PM PDT 24
Finished Aug 05 06:00:32 PM PDT 24
Peak memory 205264 kb
Host smart-64fd8527-4a22-4b6e-b193-fb0ee6cff925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029307094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2029307094
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2644697943
Short name T284
Test name
Test status
Simulation time 6141361229 ps
CPU time 8.52 seconds
Started Aug 05 06:00:30 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 205740 kb
Host smart-74160026-c4bd-4d8f-8409-6116dfbf3931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644697943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2644697943
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2127513624
Short name T53
Test name
Test status
Simulation time 459496106 ps
CPU time 1.12 seconds
Started Aug 05 06:00:30 PM PDT 24
Finished Aug 05 06:00:31 PM PDT 24
Peak memory 229900 kb
Host smart-292019fe-6915-4162-a9b8-3958b5773bea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127513624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2127513624
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.350401186
Short name T36
Test name
Test status
Simulation time 6797656023 ps
CPU time 5.49 seconds
Started Aug 05 06:00:31 PM PDT 24
Finished Aug 05 06:00:37 PM PDT 24
Peak memory 213832 kb
Host smart-5203ad9c-ec8f-49a2-a3e4-e94d5a5df64d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350401186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.350401186
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3354766473
Short name T231
Test name
Test status
Simulation time 189223707 ps
CPU time 1.13 seconds
Started Aug 05 06:01:08 PM PDT 24
Finished Aug 05 06:01:09 PM PDT 24
Peak memory 205300 kb
Host smart-20427716-218f-4d0b-9662-01bde2deb823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354766473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3354766473
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1741962115
Short name T44
Test name
Test status
Simulation time 5165144614 ps
CPU time 15.27 seconds
Started Aug 05 06:01:04 PM PDT 24
Finished Aug 05 06:01:19 PM PDT 24
Peak memory 213752 kb
Host smart-6d59b194-8c47-48cc-9f28-54a7050a41f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741962115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1741962115
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3419736716
Short name T274
Test name
Test status
Simulation time 36098245 ps
CPU time 0.75 seconds
Started Aug 05 06:01:07 PM PDT 24
Finished Aug 05 06:01:07 PM PDT 24
Peak memory 205256 kb
Host smart-f9231ee8-dde1-48c0-8b70-520fb1d234f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419736716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3419736716
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2993365124
Short name T236
Test name
Test status
Simulation time 127792343 ps
CPU time 0.73 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 205264 kb
Host smart-4b540757-cb27-4e34-9640-65521cd17bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993365124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2993365124
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.368632227
Short name T299
Test name
Test status
Simulation time 87433107 ps
CPU time 0.79 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 205324 kb
Host smart-df647daf-253d-42d0-9628-7a656463ec08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368632227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.368632227
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.193565313
Short name T240
Test name
Test status
Simulation time 175065010 ps
CPU time 0.7 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 205292 kb
Host smart-707b0425-db74-4ab5-95d1-2b8a61e4a525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193565313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.193565313
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2452727529
Short name T12
Test name
Test status
Simulation time 1685244856 ps
CPU time 5.7 seconds
Started Aug 05 06:01:05 PM PDT 24
Finished Aug 05 06:01:10 PM PDT 24
Peak memory 205508 kb
Host smart-f8bea14a-fbba-408b-b2bd-4a9102d10513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452727529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2452727529
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2503716691
Short name T227
Test name
Test status
Simulation time 60337246 ps
CPU time 0.75 seconds
Started Aug 05 06:01:06 PM PDT 24
Finished Aug 05 06:01:07 PM PDT 24
Peak memory 205284 kb
Host smart-bb595a69-2a7d-49c8-a57c-434fec4f7c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503716691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2503716691
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2510735918
Short name T148
Test name
Test status
Simulation time 3005371968 ps
CPU time 4.67 seconds
Started Aug 05 06:01:06 PM PDT 24
Finished Aug 05 06:01:11 PM PDT 24
Peak memory 213860 kb
Host smart-fb3a0ee9-ba7f-499b-adbc-b325c2a16435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510735918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2510735918
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2657909967
Short name T176
Test name
Test status
Simulation time 75429102 ps
CPU time 0.77 seconds
Started Aug 05 06:01:07 PM PDT 24
Finished Aug 05 06:01:08 PM PDT 24
Peak memory 205256 kb
Host smart-b0eb636c-76fd-457f-8949-680eed65fb6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657909967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2657909967
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.994121046
Short name T42
Test name
Test status
Simulation time 2202953772 ps
CPU time 4.95 seconds
Started Aug 05 06:01:07 PM PDT 24
Finished Aug 05 06:01:12 PM PDT 24
Peak memory 205516 kb
Host smart-5e7ed814-e2eb-4edc-9824-4a6f2c15ba66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994121046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.994121046
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.247655455
Short name T190
Test name
Test status
Simulation time 39116981 ps
CPU time 0.71 seconds
Started Aug 05 06:01:09 PM PDT 24
Finished Aug 05 06:01:10 PM PDT 24
Peak memory 205300 kb
Host smart-73db7586-2fa2-4303-9aa9-ccb924c9e6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247655455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.247655455
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.456146865
Short name T9
Test name
Test status
Simulation time 13184695545 ps
CPU time 24.02 seconds
Started Aug 05 06:01:14 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 213764 kb
Host smart-185b96dd-bad1-4d19-aa01-c463940bed42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456146865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.456146865
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2345182408
Short name T242
Test name
Test status
Simulation time 57837741 ps
CPU time 0.74 seconds
Started Aug 05 06:01:12 PM PDT 24
Finished Aug 05 06:01:13 PM PDT 24
Peak memory 205288 kb
Host smart-5819b0ae-a0ff-4019-9025-6f5b149ea069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345182408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2345182408
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1810655212
Short name T43
Test name
Test status
Simulation time 3092650733 ps
CPU time 3.23 seconds
Started Aug 05 06:01:15 PM PDT 24
Finished Aug 05 06:01:19 PM PDT 24
Peak memory 205560 kb
Host smart-54c3ae22-ab02-4006-9204-2fc8edb4ffea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810655212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1810655212
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4288175793
Short name T191
Test name
Test status
Simulation time 91926231 ps
CPU time 0.71 seconds
Started Aug 05 06:01:13 PM PDT 24
Finished Aug 05 06:01:14 PM PDT 24
Peak memory 205280 kb
Host smart-b28b6ff9-8816-47b9-9261-427552ae5d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288175793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4288175793
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1985776980
Short name T25
Test name
Test status
Simulation time 4501617719 ps
CPU time 10.29 seconds
Started Aug 05 06:01:11 PM PDT 24
Finished Aug 05 06:01:21 PM PDT 24
Peak memory 205540 kb
Host smart-e64fb919-2248-45b7-b806-e98159334ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985776980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1985776980
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.968038685
Short name T262
Test name
Test status
Simulation time 59476606 ps
CPU time 0.81 seconds
Started Aug 05 06:00:37 PM PDT 24
Finished Aug 05 06:00:38 PM PDT 24
Peak memory 205304 kb
Host smart-c515754f-1690-4f6f-9eb2-79ea3f72867b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968038685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.968038685
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3809285867
Short name T26
Test name
Test status
Simulation time 42346276731 ps
CPU time 123.81 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:02:42 PM PDT 24
Peak memory 213928 kb
Host smart-e86b58e0-ccaa-4595-8e5f-3da93d62917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809285867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3809285867
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.59079420
Short name T56
Test name
Test status
Simulation time 936890096 ps
CPU time 1.28 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 213796 kb
Host smart-0f5f1bfd-3b99-4906-b4d0-4fae1fafe281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59079420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.59079420
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.559833860
Short name T252
Test name
Test status
Simulation time 2024183744 ps
CPU time 4.06 seconds
Started Aug 05 06:00:28 PM PDT 24
Finished Aug 05 06:00:32 PM PDT 24
Peak memory 205644 kb
Host smart-b2b73fc0-91af-4002-8e7d-632079c560e4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559833860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.559833860
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.447466201
Short name T134
Test name
Test status
Simulation time 649225991 ps
CPU time 0.92 seconds
Started Aug 05 06:00:34 PM PDT 24
Finished Aug 05 06:00:35 PM PDT 24
Peak memory 205288 kb
Host smart-b2bb5521-a743-4fdf-83c5-1eaf19ceeb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447466201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.447466201
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2759051463
Short name T272
Test name
Test status
Simulation time 403112274 ps
CPU time 1.18 seconds
Started Aug 05 06:00:37 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 205272 kb
Host smart-230defcb-ef54-4c74-b7df-e85c1a129f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759051463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2759051463
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3648199140
Short name T1
Test name
Test status
Simulation time 1815200520 ps
CPU time 2.1 seconds
Started Aug 05 06:00:30 PM PDT 24
Finished Aug 05 06:00:33 PM PDT 24
Peak memory 205728 kb
Host smart-bbfe9250-a600-40a0-972c-f1a2c3c92fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648199140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3648199140
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.70086440
Short name T68
Test name
Test status
Simulation time 1224330067 ps
CPU time 2.92 seconds
Started Aug 05 06:00:34 PM PDT 24
Finished Aug 05 06:00:38 PM PDT 24
Peak memory 229676 kb
Host smart-9476d070-d2fa-4efa-9bce-ac4cc6c49b4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70086440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.70086440
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1181120413
Short name T232
Test name
Test status
Simulation time 1338013865 ps
CPU time 1.73 seconds
Started Aug 05 06:00:37 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 205508 kb
Host smart-69d6dd0d-dd48-4617-a9e2-ca4803b848d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181120413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1181120413
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1744207349
Short name T258
Test name
Test status
Simulation time 153558596 ps
CPU time 0.91 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:19 PM PDT 24
Peak memory 205232 kb
Host smart-9592b8d9-fa30-42de-bcff-8a9a5a15f032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744207349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1744207349
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1734697651
Short name T152
Test name
Test status
Simulation time 5767999821 ps
CPU time 5.81 seconds
Started Aug 05 06:01:11 PM PDT 24
Finished Aug 05 06:01:17 PM PDT 24
Peak memory 213808 kb
Host smart-5e002750-013f-427d-804e-490e8ac82734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734697651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1734697651
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3730749931
Short name T51
Test name
Test status
Simulation time 58539676 ps
CPU time 0.87 seconds
Started Aug 05 06:01:13 PM PDT 24
Finished Aug 05 06:01:14 PM PDT 24
Peak memory 205280 kb
Host smart-7b581882-7611-4ec9-97d9-1071cb762013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730749931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3730749931
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.20135315
Short name T168
Test name
Test status
Simulation time 2256584805 ps
CPU time 3.9 seconds
Started Aug 05 06:01:12 PM PDT 24
Finished Aug 05 06:01:16 PM PDT 24
Peak memory 205616 kb
Host smart-d9507910-82ad-4c05-9862-35d4cee75235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.20135315
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.54417961
Short name T222
Test name
Test status
Simulation time 33188652 ps
CPU time 0.73 seconds
Started Aug 05 06:01:15 PM PDT 24
Finished Aug 05 06:01:16 PM PDT 24
Peak memory 205300 kb
Host smart-cd0e223d-2a75-4edf-93dd-d832e4f8d1bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54417961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.54417961
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2626598931
Short name T169
Test name
Test status
Simulation time 3215625459 ps
CPU time 3.11 seconds
Started Aug 05 06:01:15 PM PDT 24
Finished Aug 05 06:01:19 PM PDT 24
Peak memory 205652 kb
Host smart-441fb0b1-62d4-4f80-8d27-4438f73a58b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626598931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2626598931
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1800233703
Short name T187
Test name
Test status
Simulation time 64943051 ps
CPU time 0.72 seconds
Started Aug 05 06:01:12 PM PDT 24
Finished Aug 05 06:01:13 PM PDT 24
Peak memory 205320 kb
Host smart-91d782d1-44ef-4ed9-ba0f-1022b66aba9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800233703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1800233703
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3518569766
Short name T47
Test name
Test status
Simulation time 8500965590 ps
CPU time 13.5 seconds
Started Aug 05 06:01:14 PM PDT 24
Finished Aug 05 06:01:27 PM PDT 24
Peak memory 213824 kb
Host smart-b0724572-82c9-48e9-b0de-502409f3fd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518569766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3518569766
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3848246833
Short name T229
Test name
Test status
Simulation time 49261357 ps
CPU time 0.76 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:01:21 PM PDT 24
Peak memory 205304 kb
Host smart-65aa6b1e-19dc-458b-9b1b-0d1ab1c5f868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848246833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3848246833
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2294059712
Short name T267
Test name
Test status
Simulation time 1791192890 ps
CPU time 2.64 seconds
Started Aug 05 06:01:12 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 205440 kb
Host smart-f4566dd5-2681-40f1-82e8-68b4df77dcfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294059712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2294059712
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.4234421831
Short name T189
Test name
Test status
Simulation time 59433872 ps
CPU time 0.75 seconds
Started Aug 05 06:01:15 PM PDT 24
Finished Aug 05 06:01:16 PM PDT 24
Peak memory 205276 kb
Host smart-746abacc-02ef-4da6-8dd1-7aabc9c48242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234421831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4234421831
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3696872256
Short name T167
Test name
Test status
Simulation time 1637273702 ps
CPU time 2.72 seconds
Started Aug 05 06:01:16 PM PDT 24
Finished Aug 05 06:01:19 PM PDT 24
Peak memory 213720 kb
Host smart-458351ef-5da4-4d51-bbc2-13bba90d074c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696872256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3696872256
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3261355042
Short name T33
Test name
Test status
Simulation time 37097780 ps
CPU time 0.76 seconds
Started Aug 05 06:01:13 PM PDT 24
Finished Aug 05 06:01:14 PM PDT 24
Peak memory 205292 kb
Host smart-83f0450d-01e8-46c9-a5ed-cc88fd5131de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261355042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3261355042
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1538901061
Short name T304
Test name
Test status
Simulation time 4195816221 ps
CPU time 3.04 seconds
Started Aug 05 06:01:13 PM PDT 24
Finished Aug 05 06:01:16 PM PDT 24
Peak memory 214400 kb
Host smart-d17f6ecf-15c3-4cc6-97b6-7690860efc96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538901061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1538901061
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2524087315
Short name T173
Test name
Test status
Simulation time 37115722 ps
CPU time 0.78 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:19 PM PDT 24
Peak memory 205304 kb
Host smart-31b11b8c-5ec9-45a1-b002-7064b261179e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524087315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2524087315
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1213141131
Short name T250
Test name
Test status
Simulation time 3151030799 ps
CPU time 2.13 seconds
Started Aug 05 06:01:16 PM PDT 24
Finished Aug 05 06:01:18 PM PDT 24
Peak memory 213888 kb
Host smart-86d682ef-b55b-4d2c-bcbf-0fa7c2f0df01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213141131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1213141131
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.329556332
Short name T185
Test name
Test status
Simulation time 37958344 ps
CPU time 0.84 seconds
Started Aug 05 06:01:11 PM PDT 24
Finished Aug 05 06:01:12 PM PDT 24
Peak memory 205288 kb
Host smart-ab85f08e-0c3d-4c28-a1bc-7a718d85ddf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329556332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.329556332
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2031507471
Short name T32
Test name
Test status
Simulation time 920544082 ps
CPU time 1.5 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:20 PM PDT 24
Peak memory 205340 kb
Host smart-0189d929-558d-4003-80fd-43f886ccd010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031507471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2031507471
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2022675351
Short name T253
Test name
Test status
Simulation time 129838045 ps
CPU time 0.77 seconds
Started Aug 05 06:01:14 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 205288 kb
Host smart-4666c1f6-b046-4c30-bcac-9f37286eec20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022675351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2022675351
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.544979657
Short name T37
Test name
Test status
Simulation time 6170579728 ps
CPU time 18.2 seconds
Started Aug 05 06:01:11 PM PDT 24
Finished Aug 05 06:01:29 PM PDT 24
Peak memory 214020 kb
Host smart-5b3af700-c91b-470b-b5c5-2d12e1fb8899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544979657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.544979657
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2970060212
Short name T179
Test name
Test status
Simulation time 73128107 ps
CPU time 0.88 seconds
Started Aug 05 06:00:37 PM PDT 24
Finished Aug 05 06:00:38 PM PDT 24
Peak memory 205292 kb
Host smart-29540d36-b593-4bc0-9004-baae4ed83635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970060212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2970060212
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2505854509
Short name T238
Test name
Test status
Simulation time 37133280072 ps
CPU time 28.43 seconds
Started Aug 05 06:00:34 PM PDT 24
Finished Aug 05 06:01:02 PM PDT 24
Peak memory 214012 kb
Host smart-1d67d6a9-9de1-41e2-9fc0-0a021a4f397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505854509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2505854509
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.947264729
Short name T265
Test name
Test status
Simulation time 3669754720 ps
CPU time 9.88 seconds
Started Aug 05 06:00:35 PM PDT 24
Finished Aug 05 06:00:45 PM PDT 24
Peak memory 215052 kb
Host smart-892b01bd-376a-46ef-9212-39ba88e69e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947264729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.947264729
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2174417119
Short name T275
Test name
Test status
Simulation time 13385837598 ps
CPU time 6.24 seconds
Started Aug 05 06:00:33 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 222072 kb
Host smart-8939c45b-c3f0-4ed2-ae84-96fd4e809a74
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174417119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2174417119
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3763298139
Short name T290
Test name
Test status
Simulation time 924688254 ps
CPU time 3.12 seconds
Started Aug 05 06:00:37 PM PDT 24
Finished Aug 05 06:00:40 PM PDT 24
Peak memory 205312 kb
Host smart-c5ec4737-50eb-4898-bf4e-4e86e895a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763298139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3763298139
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3029075583
Short name T295
Test name
Test status
Simulation time 1949739840 ps
CPU time 5.16 seconds
Started Aug 05 06:00:34 PM PDT 24
Finished Aug 05 06:00:40 PM PDT 24
Peak memory 205664 kb
Host smart-a9b43a94-1752-4bf0-bbce-f0d64fedc220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029075583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3029075583
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.4197131993
Short name T261
Test name
Test status
Simulation time 4975278227 ps
CPU time 7.8 seconds
Started Aug 05 06:00:32 PM PDT 24
Finished Aug 05 06:00:40 PM PDT 24
Peak memory 213752 kb
Host smart-1606d441-fad9-4171-aeee-2ca252dea98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197131993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.4197131993
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2429832685
Short name T87
Test name
Test status
Simulation time 131270892 ps
CPU time 0.82 seconds
Started Aug 05 06:00:36 PM PDT 24
Finished Aug 05 06:00:36 PM PDT 24
Peak memory 205288 kb
Host smart-a194833a-18ec-4a7d-b115-a770dcc2e7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429832685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2429832685
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2133032001
Short name T79
Test name
Test status
Simulation time 4133953383 ps
CPU time 12.27 seconds
Started Aug 05 06:00:36 PM PDT 24
Finished Aug 05 06:00:48 PM PDT 24
Peak memory 205744 kb
Host smart-80e406a6-408b-4b6b-bb65-0af8cce162c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133032001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2133032001
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2546203344
Short name T150
Test name
Test status
Simulation time 2198231700 ps
CPU time 2.17 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:00:40 PM PDT 24
Peak memory 213932 kb
Host smart-8d2be28d-fffc-433e-bf04-4c2dc8463fe5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546203344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2546203344
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3390398473
Short name T297
Test name
Test status
Simulation time 447564901 ps
CPU time 1.02 seconds
Started Aug 05 06:00:38 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 205312 kb
Host smart-8557f733-52fd-4a50-b386-0c051fcfbdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390398473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3390398473
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3245175092
Short name T283
Test name
Test status
Simulation time 1288536228 ps
CPU time 4.46 seconds
Started Aug 05 06:00:37 PM PDT 24
Finished Aug 05 06:00:42 PM PDT 24
Peak memory 205620 kb
Host smart-b18a627c-2140-4561-a9a0-2998afb01925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245175092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3245175092
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1966757552
Short name T5
Test name
Test status
Simulation time 4915112209 ps
CPU time 10.33 seconds
Started Aug 05 06:00:34 PM PDT 24
Finished Aug 05 06:00:45 PM PDT 24
Peak memory 213816 kb
Host smart-a364d4d7-d5ed-4e97-89c4-2aca2eb16a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966757552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1966757552
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.4247260447
Short name T181
Test name
Test status
Simulation time 129973992 ps
CPU time 0.89 seconds
Started Aug 05 06:00:40 PM PDT 24
Finished Aug 05 06:00:41 PM PDT 24
Peak memory 205280 kb
Host smart-95cf5ec3-bbf9-4882-a6be-e720af46e6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247260447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4247260447
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1709197584
Short name T300
Test name
Test status
Simulation time 2823121948 ps
CPU time 5.34 seconds
Started Aug 05 06:00:39 PM PDT 24
Finished Aug 05 06:00:44 PM PDT 24
Peak memory 214068 kb
Host smart-b79aa3d8-abd3-4c3a-a2d8-728461db85c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709197584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1709197584
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4074457405
Short name T278
Test name
Test status
Simulation time 1035001600 ps
CPU time 3.67 seconds
Started Aug 05 06:00:39 PM PDT 24
Finished Aug 05 06:00:43 PM PDT 24
Peak memory 205604 kb
Host smart-e1e6636a-f3b0-4288-933f-0e5fae6cd86e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074457405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4074457405
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.3923390129
Short name T246
Test name
Test status
Simulation time 1203767508 ps
CPU time 2.32 seconds
Started Aug 05 06:00:40 PM PDT 24
Finished Aug 05 06:00:43 PM PDT 24
Peak memory 205308 kb
Host smart-d1784097-3629-415d-9caf-2b490eb76541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923390129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3923390129
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1050951361
Short name T303
Test name
Test status
Simulation time 3816018685 ps
CPU time 9.56 seconds
Started Aug 05 06:00:35 PM PDT 24
Finished Aug 05 06:00:44 PM PDT 24
Peak memory 213960 kb
Host smart-850c16b1-523b-4348-8768-fa64c1816b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050951361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1050951361
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1352984907
Short name T194
Test name
Test status
Simulation time 89355219 ps
CPU time 0.77 seconds
Started Aug 05 06:00:41 PM PDT 24
Finished Aug 05 06:00:42 PM PDT 24
Peak memory 205292 kb
Host smart-cd93b4c6-da50-4cc9-ae31-9c556f7cb715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352984907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1352984907
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2006873368
Short name T230
Test name
Test status
Simulation time 3117304323 ps
CPU time 5.24 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:00:50 PM PDT 24
Peak memory 214008 kb
Host smart-55d44bcc-02ae-4ef0-9bc8-409ab7e9e020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006873368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2006873368
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1391696560
Short name T71
Test name
Test status
Simulation time 2361186926 ps
CPU time 7.21 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:00:52 PM PDT 24
Peak memory 205736 kb
Host smart-c37de79e-2a32-4cf0-8889-08b96ba18f81
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391696560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1391696560
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1207010142
Short name T221
Test name
Test status
Simulation time 6219713557 ps
CPU time 9.74 seconds
Started Aug 05 06:00:48 PM PDT 24
Finished Aug 05 06:00:58 PM PDT 24
Peak memory 213936 kb
Host smart-dc8064df-1acd-474a-b727-2b51187fb005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207010142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1207010142
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3063739099
Short name T151
Test name
Test status
Simulation time 4757273648 ps
CPU time 1.95 seconds
Started Aug 05 06:00:40 PM PDT 24
Finished Aug 05 06:00:42 PM PDT 24
Peak memory 213776 kb
Host smart-f54b08eb-e8c8-428a-908b-62eb1408c518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063739099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3063739099
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.2842776139
Short name T46
Test name
Test status
Simulation time 90602842453 ps
CPU time 738.46 seconds
Started Aug 05 06:00:41 PM PDT 24
Finished Aug 05 06:12:59 PM PDT 24
Peak memory 231524 kb
Host smart-a0182883-61db-4492-ab1f-c585e568c6bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842776139 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.2842776139
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2241916523
Short name T74
Test name
Test status
Simulation time 180980798 ps
CPU time 1.21 seconds
Started Aug 05 06:00:42 PM PDT 24
Finished Aug 05 06:00:43 PM PDT 24
Peak memory 205328 kb
Host smart-1f441414-6009-47dd-9252-eb5d729d78d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241916523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2241916523
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3473274143
Short name T223
Test name
Test status
Simulation time 814269242 ps
CPU time 1.89 seconds
Started Aug 05 06:00:49 PM PDT 24
Finished Aug 05 06:00:51 PM PDT 24
Peak memory 205624 kb
Host smart-d01a356c-65e4-481a-a4fa-1a77c4a145fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473274143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3473274143
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1179739554
Short name T218
Test name
Test status
Simulation time 11878772500 ps
CPU time 34.4 seconds
Started Aug 05 06:00:45 PM PDT 24
Finished Aug 05 06:01:20 PM PDT 24
Peak memory 213936 kb
Host smart-6f1c79bd-7f6b-449f-a916-d8d4bd610f00
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179739554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1179739554
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3351992382
Short name T237
Test name
Test status
Simulation time 1747309986 ps
CPU time 5.27 seconds
Started Aug 05 06:00:50 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 205644 kb
Host smart-4e1acede-d1a3-47c2-94e3-08c5f8ea77a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351992382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3351992382
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2830352741
Short name T24
Test name
Test status
Simulation time 3745880024 ps
CPU time 11.11 seconds
Started Aug 05 06:00:41 PM PDT 24
Finished Aug 05 06:00:52 PM PDT 24
Peak memory 213700 kb
Host smart-a9ecea61-674a-451f-aa9e-12c0de51a400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830352741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2830352741
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.847413618
Short name T22
Test name
Test status
Simulation time 127675376713 ps
CPU time 527.61 seconds
Started Aug 05 06:00:44 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 229540 kb
Host smart-8afbc67d-90ff-4f47-bb11-b6fe5f4041dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847413618 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.847413618
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%