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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
84.61 96.32 87.13 92.10 73.75 90.44 98.53 54.00


Total test records in report: 465
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T68 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4272843109 Aug 07 04:46:55 PM PDT 24 Aug 07 04:46:56 PM PDT 24 258230526 ps
T94 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1870774121 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:16 PM PDT 24 215190001 ps
T308 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1328231647 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:17 PM PDT 24 8269437260 ps
T83 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2350515367 Aug 07 04:47:03 PM PDT 24 Aug 07 04:47:31 PM PDT 24 4344591764 ps
T309 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.378676469 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:19 PM PDT 24 1626492909 ps
T310 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.546582846 Aug 07 04:47:03 PM PDT 24 Aug 07 04:49:31 PM PDT 24 52795310404 ps
T95 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4234128950 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:16 PM PDT 24 336291032 ps
T96 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3781176290 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:12 PM PDT 24 112304587 ps
T69 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3751598861 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:15 PM PDT 24 213492728 ps
T311 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.668695091 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:32 PM PDT 24 20599846535 ps
T97 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3127011826 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:08 PM PDT 24 142915494 ps
T70 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1734445895 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:17 PM PDT 24 5001793781 ps
T312 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4219453651 Aug 07 04:47:20 PM PDT 24 Aug 07 04:47:24 PM PDT 24 5642347806 ps
T84 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4077539027 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:16 PM PDT 24 182758275 ps
T313 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.717038753 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:02 PM PDT 24 149651724 ps
T102 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.691039783 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:14 PM PDT 24 96693057 ps
T314 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2423856746 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:27 PM PDT 24 52619519973 ps
T103 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.88190799 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:12 PM PDT 24 291844860 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1985612099 Aug 07 04:46:54 PM PDT 24 Aug 07 04:46:55 PM PDT 24 150105836 ps
T132 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3427333812 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:22 PM PDT 24 2064251934 ps
T316 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.70866721 Aug 07 04:47:02 PM PDT 24 Aug 07 04:47:05 PM PDT 24 1158329120 ps
T317 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3013498392 Aug 07 04:47:15 PM PDT 24 Aug 07 04:48:15 PM PDT 24 58198549506 ps
T318 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3229287551 Aug 07 04:47:15 PM PDT 24 Aug 07 04:47:20 PM PDT 24 1756955665 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3983469123 Aug 07 04:46:47 PM PDT 24 Aug 07 04:47:55 PM PDT 24 4900792908 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.162946659 Aug 07 04:46:55 PM PDT 24 Aug 07 04:46:59 PM PDT 24 406903429 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3026856539 Aug 07 04:46:52 PM PDT 24 Aug 07 04:46:55 PM PDT 24 285987174 ps
T100 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1664777719 Aug 07 04:47:24 PM PDT 24 Aug 07 04:47:27 PM PDT 24 110933086 ps
T320 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4135039596 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:19 PM PDT 24 11800687810 ps
T321 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1437395029 Aug 07 04:46:48 PM PDT 24 Aug 07 04:46:53 PM PDT 24 3778448582 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1788512828 Aug 07 04:46:48 PM PDT 24 Aug 07 04:46:51 PM PDT 24 286306881 ps
T323 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1311851302 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:18 PM PDT 24 196650204 ps
T324 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2616632597 Aug 07 04:46:59 PM PDT 24 Aug 07 04:46:59 PM PDT 24 91799784 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.827112958 Aug 07 04:46:58 PM PDT 24 Aug 07 04:47:04 PM PDT 24 593858228 ps
T108 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1443177650 Aug 07 04:47:31 PM PDT 24 Aug 07 04:47:34 PM PDT 24 432887256 ps
T325 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3723761193 Aug 07 04:46:59 PM PDT 24 Aug 07 04:47:19 PM PDT 24 7119878318 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4205040108 Aug 07 04:46:51 PM PDT 24 Aug 07 04:46:58 PM PDT 24 5887114535 ps
T327 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3883713615 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:37 PM PDT 24 11967941411 ps
T133 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.298587308 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:04 PM PDT 24 783270572 ps
T328 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1563614027 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:18 PM PDT 24 242940412 ps
T134 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2980376603 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:37 PM PDT 24 4648381467 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2949522902 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:58 PM PDT 24 6226893314 ps
T330 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1193596144 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:16 PM PDT 24 6397398095 ps
T109 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2124121248 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:02 PM PDT 24 146056133 ps
T65 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.835033823 Aug 07 04:46:49 PM PDT 24 Aug 07 04:48:53 PM PDT 24 74368818834 ps
T331 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1854677102 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:22 PM PDT 24 5639914281 ps
T162 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3657092124 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:29 PM PDT 24 3854401839 ps
T332 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4018000385 Aug 07 04:47:03 PM PDT 24 Aug 07 04:47:04 PM PDT 24 47228970 ps
T110 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2195482585 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:11 PM PDT 24 50215441 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.308750695 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:58 PM PDT 24 262620660 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3606568524 Aug 07 04:46:49 PM PDT 24 Aug 07 04:47:16 PM PDT 24 16417030489 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.674602185 Aug 07 04:46:46 PM PDT 24 Aug 07 04:47:15 PM PDT 24 18218522032 ps
T130 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1176408331 Aug 07 04:46:59 PM PDT 24 Aug 07 04:47:01 PM PDT 24 113972615 ps
T166 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2259389303 Aug 07 04:47:10 PM PDT 24 Aug 07 04:47:30 PM PDT 24 1652352814 ps
T336 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.169953087 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:24 PM PDT 24 3410629231 ps
T337 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2652185943 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:48 PM PDT 24 553562337 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1223696025 Aug 07 04:46:59 PM PDT 24 Aug 07 04:47:00 PM PDT 24 72272094 ps
T339 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1220480225 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:33 PM PDT 24 20511684563 ps
T135 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.643029384 Aug 07 04:46:51 PM PDT 24 Aug 07 04:47:13 PM PDT 24 2439941184 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2083373682 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:19 PM PDT 24 1193575427 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3854389315 Aug 07 04:46:48 PM PDT 24 Aug 07 04:47:28 PM PDT 24 27788569845 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.670194192 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:10 PM PDT 24 149095816 ps
T111 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4277096837 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:10 PM PDT 24 378657785 ps
T125 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2417530138 Aug 07 04:47:05 PM PDT 24 Aug 07 04:47:11 PM PDT 24 436501031 ps
T116 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.810700260 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:03 PM PDT 24 289673701 ps
T343 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.175418264 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:18 PM PDT 24 3042652292 ps
T344 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1807869316 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:08 PM PDT 24 101777690 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.92644709 Aug 07 04:47:02 PM PDT 24 Aug 07 04:47:03 PM PDT 24 144086013 ps
T346 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1380070834 Aug 07 04:47:16 PM PDT 24 Aug 07 04:47:19 PM PDT 24 144081658 ps
T117 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1127945473 Aug 07 04:47:03 PM PDT 24 Aug 07 04:47:55 PM PDT 24 1553397091 ps
T347 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3645344530 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:02 PM PDT 24 52501804 ps
T348 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.892585133 Aug 07 04:47:10 PM PDT 24 Aug 07 04:47:10 PM PDT 24 196987717 ps
T112 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3913216118 Aug 07 04:47:18 PM PDT 24 Aug 07 04:47:27 PM PDT 24 1659685371 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2041690384 Aug 07 04:46:48 PM PDT 24 Aug 07 04:46:49 PM PDT 24 43286763 ps
T350 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.185475344 Aug 07 04:46:58 PM PDT 24 Aug 07 04:47:00 PM PDT 24 429128455 ps
T66 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1520069680 Aug 07 04:47:06 PM PDT 24 Aug 07 04:48:10 PM PDT 24 21477131870 ps
T118 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.458312422 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:09 PM PDT 24 281880685 ps
T126 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.690948012 Aug 07 04:47:19 PM PDT 24 Aug 07 04:47:26 PM PDT 24 289902461 ps
T168 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.193460915 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:39 PM PDT 24 66056780205 ps
T119 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.646052059 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:15 PM PDT 24 166376183 ps
T113 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2172872876 Aug 07 04:46:56 PM PDT 24 Aug 07 04:48:15 PM PDT 24 4359543627 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3846865792 Aug 07 04:46:47 PM PDT 24 Aug 07 04:47:53 PM PDT 24 3300558285 ps
T352 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3187642904 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:14 PM PDT 24 5002138206 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4002934086 Aug 07 04:46:50 PM PDT 24 Aug 07 04:47:07 PM PDT 24 10513889448 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2254897970 Aug 07 04:47:03 PM PDT 24 Aug 07 04:47:14 PM PDT 24 4132197473 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3007077929 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:02 PM PDT 24 143872861 ps
T355 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.411365736 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:10 PM PDT 24 716274856 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2178882678 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:56 PM PDT 24 281460159 ps
T127 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1341057757 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:23 PM PDT 24 892584626 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2615522047 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:59 PM PDT 24 2398872601 ps
T128 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2223874152 Aug 07 04:47:05 PM PDT 24 Aug 07 04:47:12 PM PDT 24 404801251 ps
T129 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.208869135 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:14 PM PDT 24 1446302624 ps
T358 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1576617079 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:48 PM PDT 24 64884801 ps
T359 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2369125601 Aug 07 04:47:25 PM PDT 24 Aug 07 04:47:26 PM PDT 24 194775518 ps
T360 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3153306065 Aug 07 04:46:49 PM PDT 24 Aug 07 04:46:52 PM PDT 24 973288042 ps
T361 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4109410598 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:07 PM PDT 24 143986638 ps
T362 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2510872873 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:15 PM PDT 24 864323175 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3040213617 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:19 PM PDT 24 4439099801 ps
T364 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1507522571 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:11 PM PDT 24 157748521 ps
T365 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4248229424 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:12 PM PDT 24 564470169 ps
T114 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3760633630 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:16 PM PDT 24 351801397 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3061885991 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:05 PM PDT 24 244716355 ps
T367 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2994743977 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:11 PM PDT 24 533014275 ps
T169 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3198227029 Aug 07 04:47:04 PM PDT 24 Aug 07 04:50:38 PM PDT 24 29224158312 ps
T115 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3412292797 Aug 07 04:47:16 PM PDT 24 Aug 07 04:47:21 PM PDT 24 1002033736 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1158535532 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:12 PM PDT 24 233279871 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1393498009 Aug 07 04:46:48 PM PDT 24 Aug 07 04:49:47 PM PDT 24 40134969955 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.843176095 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:06 PM PDT 24 1262975946 ps
T371 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3905831753 Aug 07 04:47:05 PM PDT 24 Aug 07 04:47:07 PM PDT 24 152132933 ps
T372 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1792649372 Aug 07 04:47:16 PM PDT 24 Aug 07 04:47:18 PM PDT 24 358387125 ps
T120 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.713659460 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:55 PM PDT 24 291620681 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2351845663 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:49 PM PDT 24 221974112 ps
T124 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3622204708 Aug 07 04:46:54 PM PDT 24 Aug 07 04:46:56 PM PDT 24 156719628 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3478960827 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:07 PM PDT 24 69521873 ps
T375 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1615263344 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:30 PM PDT 24 12868408903 ps
T123 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3698976322 Aug 07 04:46:59 PM PDT 24 Aug 07 04:47:01 PM PDT 24 270412429 ps
T376 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3031556979 Aug 07 04:47:10 PM PDT 24 Aug 07 04:47:17 PM PDT 24 384326657 ps
T377 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2524891842 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:09 PM PDT 24 541295380 ps
T378 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.731317185 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:22 PM PDT 24 1493177204 ps
T379 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1504388350 Aug 07 04:46:52 PM PDT 24 Aug 07 04:46:54 PM PDT 24 461088206 ps
T170 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2251063186 Aug 07 04:47:05 PM PDT 24 Aug 07 04:48:03 PM PDT 24 62364521305 ps
T380 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2111757393 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:16 PM PDT 24 385900567 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2350944228 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:06 PM PDT 24 1168429089 ps
T381 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2180325372 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:13 PM PDT 24 171712760 ps
T382 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3313799957 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:59 PM PDT 24 59332625791 ps
T383 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2205706412 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:11 PM PDT 24 76797330 ps
T384 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.102036417 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:05 PM PDT 24 1419950062 ps
T385 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3581922382 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:16 PM PDT 24 512637239 ps
T386 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2618872355 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:17 PM PDT 24 1617453464 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3953277718 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:49 PM PDT 24 125282657 ps
T388 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3907430671 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:23 PM PDT 24 23796012525 ps
T389 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.347390045 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:13 PM PDT 24 671201893 ps
T390 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3622403801 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:05 PM PDT 24 1223857813 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3836455632 Aug 07 04:46:51 PM PDT 24 Aug 07 04:46:52 PM PDT 24 498526946 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1086264942 Aug 07 04:46:53 PM PDT 24 Aug 07 04:47:52 PM PDT 24 28191073697 ps
T164 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.715931203 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:20 PM PDT 24 1998055009 ps
T393 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.29552580 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:07 PM PDT 24 389557552 ps
T394 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2236093092 Aug 07 04:46:57 PM PDT 24 Aug 07 04:49:42 PM PDT 24 211879909444 ps
T395 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3794875947 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:11 PM PDT 24 516932829 ps
T396 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2239980915 Aug 07 04:46:54 PM PDT 24 Aug 07 04:46:55 PM PDT 24 284027056 ps
T121 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3504777237 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:31 PM PDT 24 6612575436 ps
T397 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2796757081 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:14 PM PDT 24 124406773 ps
T398 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2925731367 Aug 07 04:47:38 PM PDT 24 Aug 07 04:47:39 PM PDT 24 500179779 ps
T399 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.229957694 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:36 PM PDT 24 3702806852 ps
T400 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3320213977 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:11 PM PDT 24 782486425 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4097236392 Aug 07 04:46:52 PM PDT 24 Aug 07 04:48:11 PM PDT 24 15713996033 ps
T402 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2677144856 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:01 PM PDT 24 141263623 ps
T403 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2645072074 Aug 07 04:47:02 PM PDT 24 Aug 07 04:47:03 PM PDT 24 504108868 ps
T404 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2538607023 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:11 PM PDT 24 420625356 ps
T405 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.962916279 Aug 07 04:47:17 PM PDT 24 Aug 07 04:47:24 PM PDT 24 357668229 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1505746280 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:06 PM PDT 24 588600132 ps
T407 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1444808987 Aug 07 04:47:13 PM PDT 24 Aug 07 04:47:16 PM PDT 24 745882252 ps
T408 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4101986914 Aug 07 04:47:00 PM PDT 24 Aug 07 04:48:39 PM PDT 24 37041633167 ps
T409 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2804405949 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:12 PM PDT 24 190875916 ps
T165 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2215429478 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:36 PM PDT 24 5493944806 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.329826439 Aug 07 04:46:50 PM PDT 24 Aug 07 04:47:03 PM PDT 24 4360401625 ps
T410 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3820749095 Aug 07 04:47:06 PM PDT 24 Aug 07 04:48:19 PM PDT 24 26708641883 ps
T411 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3588616614 Aug 07 04:47:19 PM PDT 24 Aug 07 04:47:39 PM PDT 24 5554381723 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2874128389 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:11 PM PDT 24 927209908 ps
T413 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4231881620 Aug 07 04:47:13 PM PDT 24 Aug 07 04:48:05 PM PDT 24 21789901307 ps
T414 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3318933001 Aug 07 04:47:03 PM PDT 24 Aug 07 04:47:07 PM PDT 24 2113994595 ps
T415 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1378773935 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:07 PM PDT 24 359199273 ps
T416 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4219312939 Aug 07 04:47:33 PM PDT 24 Aug 07 04:47:38 PM PDT 24 2543311477 ps
T417 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3794525083 Aug 07 04:47:16 PM PDT 24 Aug 07 04:47:28 PM PDT 24 1341202665 ps
T418 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3628598437 Aug 07 04:46:51 PM PDT 24 Aug 07 04:46:54 PM PDT 24 3730375909 ps
T163 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.518749959 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:29 PM PDT 24 2024046994 ps
T419 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1636888309 Aug 07 04:47:20 PM PDT 24 Aug 07 04:47:31 PM PDT 24 4252195657 ps
T420 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3381510429 Aug 07 04:47:16 PM PDT 24 Aug 07 04:47:17 PM PDT 24 305546593 ps
T122 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2527996527 Aug 07 04:46:49 PM PDT 24 Aug 07 04:47:22 PM PDT 24 3500251454 ps
T421 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1945855590 Aug 07 04:46:55 PM PDT 24 Aug 07 04:46:56 PM PDT 24 203085953 ps
T422 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1964499885 Aug 07 04:46:47 PM PDT 24 Aug 07 04:47:11 PM PDT 24 15497310533 ps
T423 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1572962607 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:06 PM PDT 24 149435818 ps
T424 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4114417020 Aug 07 04:47:05 PM PDT 24 Aug 07 04:47:50 PM PDT 24 49728899882 ps
T425 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2301016854 Aug 07 04:47:02 PM PDT 24 Aug 07 04:47:20 PM PDT 24 16529564157 ps
T426 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4041864115 Aug 07 04:47:37 PM PDT 24 Aug 07 04:48:11 PM PDT 24 45085414776 ps
T427 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3444236138 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:16 PM PDT 24 7232990570 ps
T428 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2712073504 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:09 PM PDT 24 228121927 ps
T429 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3085007712 Aug 07 04:47:01 PM PDT 24 Aug 07 04:47:09 PM PDT 24 1817534003 ps
T430 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2520539709 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:58 PM PDT 24 2803402369 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2570726228 Aug 07 04:46:48 PM PDT 24 Aug 07 04:46:51 PM PDT 24 182333080 ps
T432 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3237122474 Aug 07 04:47:25 PM PDT 24 Aug 07 04:47:30 PM PDT 24 361834348 ps
T433 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1711664430 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:15 PM PDT 24 2856228463 ps
T434 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1613667474 Aug 07 04:47:37 PM PDT 24 Aug 07 04:47:39 PM PDT 24 87280376 ps
T435 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2466979204 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:13 PM PDT 24 1407843537 ps
T436 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2499686045 Aug 07 04:46:53 PM PDT 24 Aug 07 04:51:21 PM PDT 24 44123442015 ps
T437 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.753155316 Aug 07 04:47:05 PM PDT 24 Aug 07 04:47:12 PM PDT 24 348804256 ps
T438 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3305550754 Aug 07 04:46:52 PM PDT 24 Aug 07 04:46:53 PM PDT 24 123173538 ps
T439 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.740519269 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:10 PM PDT 24 138770478 ps
T440 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3102576712 Aug 07 04:47:09 PM PDT 24 Aug 07 04:47:17 PM PDT 24 1082010118 ps
T441 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3913685131 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:17 PM PDT 24 6459564901 ps
T442 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2674155458 Aug 07 04:46:51 PM PDT 24 Aug 07 04:46:55 PM PDT 24 105287095 ps
T443 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1246885328 Aug 07 04:47:02 PM PDT 24 Aug 07 04:48:16 PM PDT 24 6428649397 ps
T444 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4123582593 Aug 07 04:46:59 PM PDT 24 Aug 07 04:47:02 PM PDT 24 340306401 ps
T445 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1142549823 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:12 PM PDT 24 350141902 ps
T446 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1518258878 Aug 07 04:47:05 PM PDT 24 Aug 07 04:47:09 PM PDT 24 8969679406 ps
T447 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.259466846 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:55 PM PDT 24 296816868 ps
T448 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3154384134 Aug 07 04:47:14 PM PDT 24 Aug 07 04:47:18 PM PDT 24 203379320 ps
T449 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1826632942 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:37 PM PDT 24 4316003575 ps
T450 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2906904889 Aug 07 04:46:54 PM PDT 24 Aug 07 04:46:56 PM PDT 24 164273032 ps
T451 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2892424870 Aug 07 04:46:47 PM PDT 24 Aug 07 04:46:48 PM PDT 24 261073424 ps
T452 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1094808059 Aug 07 04:47:13 PM PDT 24 Aug 07 04:48:26 PM PDT 24 30030234900 ps
T453 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.425309799 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:36 PM PDT 24 11444371488 ps
T454 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.961823720 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:09 PM PDT 24 383413966 ps
T455 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2119129879 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:12 PM PDT 24 827826664 ps
T456 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3767348613 Aug 07 04:47:08 PM PDT 24 Aug 07 04:47:11 PM PDT 24 145690377 ps
T457 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4029590845 Aug 07 04:47:00 PM PDT 24 Aug 07 04:47:04 PM PDT 24 347840388 ps
T458 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1234379496 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:56 PM PDT 24 967862830 ps
T459 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4210808772 Aug 07 04:46:54 PM PDT 24 Aug 07 04:46:55 PM PDT 24 356912554 ps
T460 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3337526617 Aug 07 04:46:53 PM PDT 24 Aug 07 04:46:58 PM PDT 24 416665034 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2789298952 Aug 07 04:46:55 PM PDT 24 Aug 07 04:47:15 PM PDT 24 7187571514 ps
T461 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1339269743 Aug 07 04:47:06 PM PDT 24 Aug 07 04:47:11 PM PDT 24 4097567689 ps
T462 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3002109413 Aug 07 04:46:59 PM PDT 24 Aug 07 04:47:08 PM PDT 24 529436135 ps
T463 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3884762420 Aug 07 04:47:04 PM PDT 24 Aug 07 04:49:39 PM PDT 24 58987028764 ps
T464 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2579490230 Aug 07 04:47:07 PM PDT 24 Aug 07 04:47:08 PM PDT 24 389213760 ps
T167 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.962305599 Aug 07 04:47:04 PM PDT 24 Aug 07 04:47:14 PM PDT 24 1287598438 ps
T465 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1694879188 Aug 07 04:47:12 PM PDT 24 Aug 07 04:47:17 PM PDT 24 321436163 ps

Test location /workspace/coverage/default/27.rv_dm_stress_all.765309409
Short name T1
Test name
Test status
Simulation time 1897112112 ps
CPU time 4.02 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:49 PM PDT 24
Peak memory 213228 kb
Host smart-31fd6de1-7b17-470b-a08e-97f78ba8a074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765309409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.765309409
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.2991063021
Short name T24
Test name
Test status
Simulation time 200917453279 ps
CPU time 881.42 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 234580 kb
Host smart-e8428a06-727b-4d84-8c69-be3bf4cf73d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991063021 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.2991063021
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3246094325
Short name T78
Test name
Test status
Simulation time 1723100289 ps
CPU time 1.97 seconds
Started Aug 07 04:47:33 PM PDT 24
Finished Aug 07 04:47:35 PM PDT 24
Peak memory 205268 kb
Host smart-a4694221-bdd5-412e-9a7b-fd40e0c5fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246094325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3246094325
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.387516955
Short name T42
Test name
Test status
Simulation time 3898014548 ps
CPU time 3.24 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:43 PM PDT 24
Peak memory 213396 kb
Host smart-62946ce2-0f64-420c-845a-39a8412a7dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387516955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.387516955
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3454308485
Short name T75
Test name
Test status
Simulation time 4024321645 ps
CPU time 4.86 seconds
Started Aug 07 04:47:33 PM PDT 24
Finished Aug 07 04:47:38 PM PDT 24
Peak memory 215980 kb
Host smart-c3cb285b-cdfd-45bc-b32e-8b21e3100ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454308485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3454308485
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2350515367
Short name T83
Test name
Test status
Simulation time 4344591764 ps
CPU time 27.67 seconds
Started Aug 07 04:47:03 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 213612 kb
Host smart-f296f86f-e0e0-4fa0-81f2-6d6df690f55a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350515367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2350515367
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.835033823
Short name T65
Test name
Test status
Simulation time 74368818834 ps
CPU time 123.5 seconds
Started Aug 07 04:46:49 PM PDT 24
Finished Aug 07 04:48:53 PM PDT 24
Peak memory 221816 kb
Host smart-f749a8f0-7f05-4dd6-90a9-d51fd706d38c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835033823 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.835033823
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1880711469
Short name T55
Test name
Test status
Simulation time 194300994 ps
CPU time 0.72 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 204832 kb
Host smart-82135649-4a00-4ed9-bf4e-176a5f244e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880711469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1880711469
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1337297968
Short name T49
Test name
Test status
Simulation time 268995940032 ps
CPU time 930.29 seconds
Started Aug 07 04:47:26 PM PDT 24
Finished Aug 07 05:02:56 PM PDT 24
Peak memory 232048 kb
Host smart-5363b100-c060-48b3-bfea-e2570ff8609f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337297968 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1337297968
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.906889822
Short name T152
Test name
Test status
Simulation time 13311766308 ps
CPU time 40.12 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:48:27 PM PDT 24
Peak memory 213576 kb
Host smart-9dfa88e9-2ac4-4528-9c6b-2d2cf4d2212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906889822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.906889822
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.163779101
Short name T62
Test name
Test status
Simulation time 608315825 ps
CPU time 1.53 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:42 PM PDT 24
Peak memory 204844 kb
Host smart-4d6debfc-cc7e-4f8f-8d33-384223dcbad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163779101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.163779101
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.717983003
Short name T26
Test name
Test status
Simulation time 8513780104 ps
CPU time 27.13 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:48:09 PM PDT 24
Peak memory 213556 kb
Host smart-0f3e9270-50ac-44ae-a981-d9b19c5ed5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717983003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.717983003
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2822545146
Short name T61
Test name
Test status
Simulation time 207800736 ps
CPU time 0.73 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:47:43 PM PDT 24
Peak memory 204936 kb
Host smart-3cdf3bff-f7dd-4aa2-bbbf-6b36584d999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822545146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2822545146
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2308744768
Short name T139
Test name
Test status
Simulation time 1913670956 ps
CPU time 5.97 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:30 PM PDT 24
Peak memory 205004 kb
Host smart-38a3cea4-5576-40ab-a867-4c7a0e4940cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308744768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2308744768
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3781176290
Short name T96
Test name
Test status
Simulation time 112304587 ps
CPU time 2.36 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 212992 kb
Host smart-a822fbbd-c43a-423a-9674-484b11ea7e11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781176290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3781176290
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3523690817
Short name T35
Test name
Test status
Simulation time 1803696091 ps
CPU time 1.61 seconds
Started Aug 07 04:47:35 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 229136 kb
Host smart-3ee29764-a322-4b9d-996f-5fbe31cb91f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523690817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3523690817
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4183619819
Short name T15
Test name
Test status
Simulation time 144928056 ps
CPU time 0.99 seconds
Started Aug 07 04:47:17 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 204816 kb
Host smart-7e248175-8feb-4e17-872c-e7f7fc5db516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183619819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4183619819
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.4045224271
Short name T3
Test name
Test status
Simulation time 3265953843 ps
CPU time 4.06 seconds
Started Aug 07 04:47:53 PM PDT 24
Finished Aug 07 04:47:57 PM PDT 24
Peak memory 213392 kb
Host smart-6ecb332d-a648-47eb-914c-b83541443c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045224271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.4045224271
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2172872876
Short name T113
Test name
Test status
Simulation time 4359543627 ps
CPU time 78.61 seconds
Started Aug 07 04:46:56 PM PDT 24
Finished Aug 07 04:48:15 PM PDT 24
Peak memory 205408 kb
Host smart-1f048302-7e58-4cab-adda-64ae86fa9e1d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172872876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2172872876
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.610792758
Short name T38
Test name
Test status
Simulation time 75668733 ps
CPU time 0.99 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 213064 kb
Host smart-bfd08b1a-7961-4264-892a-69ec39d631b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610792758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.610792758
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3657092124
Short name T162
Test name
Test status
Simulation time 3854401839 ps
CPU time 17.14 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:29 PM PDT 24
Peak memory 213584 kb
Host smart-2b33e5c4-2477-40dd-a40c-5072f18fb920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657092124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
657092124
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3503095334
Short name T157
Test name
Test status
Simulation time 27854341844 ps
CPU time 26.62 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:48:14 PM PDT 24
Peak memory 213516 kb
Host smart-3ffee979-4fc2-4862-b2c0-7573fadb5fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503095334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3503095334
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3788203497
Short name T7
Test name
Test status
Simulation time 178743359 ps
CPU time 0.96 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:25 PM PDT 24
Peak memory 204804 kb
Host smart-b9fc4d38-0937-4f41-acde-d90c97d55ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788203497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3788203497
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3024278076
Short name T147
Test name
Test status
Simulation time 6841552905 ps
CPU time 20.68 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:44 PM PDT 24
Peak memory 213532 kb
Host smart-8d33122f-e4a0-4e3f-8aca-952bd52fc5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024278076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3024278076
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.1190711704
Short name T27
Test name
Test status
Simulation time 329963327 ps
CPU time 0.96 seconds
Started Aug 07 04:47:21 PM PDT 24
Finished Aug 07 04:47:22 PM PDT 24
Peak memory 204844 kb
Host smart-11344e8e-f4c3-4d15-98f1-2f4942b26e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190711704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1190711704
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.2021228661
Short name T81
Test name
Test status
Simulation time 273575298301 ps
CPU time 465.28 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:55:09 PM PDT 24
Peak memory 235984 kb
Host smart-81be87fc-1d64-46e7-94f9-80b5efd140c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021228661 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.2021228661
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2652185943
Short name T337
Test name
Test status
Simulation time 553562337 ps
CPU time 1.11 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 204948 kb
Host smart-f10fbc1a-23ba-473d-88fa-64daef58b458
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652185943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2652185943
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.4288542523
Short name T46
Test name
Test status
Simulation time 389424040 ps
CPU time 1.81 seconds
Started Aug 07 04:47:17 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 204820 kb
Host smart-b0aec5dc-776c-4e84-9c8c-d7399dd7715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288542523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4288542523
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.329826439
Short name T106
Test name
Test status
Simulation time 4360401625 ps
CPU time 13.11 seconds
Started Aug 07 04:46:50 PM PDT 24
Finished Aug 07 04:47:03 PM PDT 24
Peak memory 205332 kb
Host smart-7118ab75-15d0-4231-8499-4be44dfe6331
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329826439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.329826439
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.162946659
Short name T99
Test name
Test status
Simulation time 406903429 ps
CPU time 3.92 seconds
Started Aug 07 04:46:55 PM PDT 24
Finished Aug 07 04:46:59 PM PDT 24
Peak memory 205264 kb
Host smart-abd8d099-0b14-4cbf-910f-b92fdcb320bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162946659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.162946659
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2259389303
Short name T166
Test name
Test status
Simulation time 1652352814 ps
CPU time 19.4 seconds
Started Aug 07 04:47:10 PM PDT 24
Finished Aug 07 04:47:30 PM PDT 24
Peak memory 213540 kb
Host smart-23754552-0d2f-4306-9989-953dbeafa25c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259389303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
259389303
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1869812555
Short name T36
Test name
Test status
Simulation time 281123085 ps
CPU time 0.8 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:13 PM PDT 24
Peak memory 204784 kb
Host smart-1ae6fd26-d9db-49b8-a15d-c22bd3adf31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869812555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1869812555
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.962305599
Short name T167
Test name
Test status
Simulation time 1287598438 ps
CPU time 10.27 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 213256 kb
Host smart-7bc5589e-2e8b-4efa-84c8-125ecf1998cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962305599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.962305599
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.908510535
Short name T64
Test name
Test status
Simulation time 5157980944 ps
CPU time 3.86 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 205096 kb
Host smart-cba3b276-1a8e-4611-8179-cf1c6139b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908510535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.908510535
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3736220007
Short name T29
Test name
Test status
Simulation time 32179368656 ps
CPU time 8.71 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 219740 kb
Host smart-0ada673c-2197-4b6d-9c61-31df679e817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736220007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3736220007
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.868423039
Short name T30
Test name
Test status
Simulation time 50439934479 ps
CPU time 24.44 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:48:10 PM PDT 24
Peak memory 213540 kb
Host smart-c0e0a692-3e0b-4577-89e9-73680b5d8471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868423039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.868423039
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.4126171167
Short name T262
Test name
Test status
Simulation time 3059729551 ps
CPU time 4.38 seconds
Started Aug 07 04:47:30 PM PDT 24
Finished Aug 07 04:47:34 PM PDT 24
Peak memory 205296 kb
Host smart-4b34b285-33af-4646-9d87-ef18cf17d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126171167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4126171167
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3203674927
Short name T159
Test name
Test status
Simulation time 2495041910 ps
CPU time 3.05 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 205168 kb
Host smart-083ebf8b-7149-44d1-bafb-ae1b783887ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203674927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3203674927
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2875571148
Short name T188
Test name
Test status
Simulation time 4621994383 ps
CPU time 8.25 seconds
Started Aug 07 04:47:35 PM PDT 24
Finished Aug 07 04:47:44 PM PDT 24
Peak memory 213568 kb
Host smart-7ef27d16-73e6-45ed-b4ea-1bc18cdf0921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875571148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2875571148
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2527996527
Short name T122
Test name
Test status
Simulation time 3500251454 ps
CPU time 32.7 seconds
Started Aug 07 04:46:49 PM PDT 24
Finished Aug 07 04:47:22 PM PDT 24
Peak memory 205340 kb
Host smart-eed57841-3dde-4513-a522-25ef19810b22
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527996527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2527996527
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3983469123
Short name T98
Test name
Test status
Simulation time 4900792908 ps
CPU time 67.89 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 213580 kb
Host smart-06a79e92-2891-47a8-b74c-dfc26fdaab16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983469123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3983469123
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.713659460
Short name T120
Test name
Test status
Simulation time 291620681 ps
CPU time 2.3 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 213600 kb
Host smart-352db444-89cd-4273-bf0a-c5b33153fbd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713659460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.713659460
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.308750695
Short name T333
Test name
Test status
Simulation time 262620660 ps
CPU time 4.11 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:58 PM PDT 24
Peak memory 221768 kb
Host smart-87d06d39-9147-4820-8471-9dcfed2a9762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308750695 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.308750695
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1576617079
Short name T358
Test name
Test status
Simulation time 64884801 ps
CPU time 1.48 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 213344 kb
Host smart-c15daa12-6dea-4508-835d-16b7a0ace811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576617079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1576617079
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.674602185
Short name T335
Test name
Test status
Simulation time 18218522032 ps
CPU time 28.9 seconds
Started Aug 07 04:46:46 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 205224 kb
Host smart-6007158c-c043-4736-82ec-f4754b29c33e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674602185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.674602185
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4002934086
Short name T353
Test name
Test status
Simulation time 10513889448 ps
CPU time 16.8 seconds
Started Aug 07 04:46:50 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 205280 kb
Host smart-d8f2cb7a-d722-4ae5-9f36-0a9c24047e44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002934086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.4002934086
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3628598437
Short name T418
Test name
Test status
Simulation time 3730375909 ps
CPU time 3.4 seconds
Started Aug 07 04:46:51 PM PDT 24
Finished Aug 07 04:46:54 PM PDT 24
Peak memory 205228 kb
Host smart-cde965c4-a01f-4963-88d6-a284f365175d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628598437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
628598437
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3153306065
Short name T360
Test name
Test status
Simulation time 973288042 ps
CPU time 3.34 seconds
Started Aug 07 04:46:49 PM PDT 24
Finished Aug 07 04:46:52 PM PDT 24
Peak memory 204964 kb
Host smart-706d31af-fc93-432a-bcde-da02533cb420
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153306065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3153306065
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2949522902
Short name T329
Test name
Test status
Simulation time 6226893314 ps
CPU time 11.27 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:58 PM PDT 24
Peak memory 205280 kb
Host smart-31ba6e6c-cdbe-41d2-9322-5c7617f81acc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949522902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2949522902
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2892424870
Short name T451
Test name
Test status
Simulation time 261073424 ps
CPU time 1.4 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:48 PM PDT 24
Peak memory 205020 kb
Host smart-e4afa305-9675-48dc-8ca4-9dc105ce747d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892424870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2892424870
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4210808772
Short name T459
Test name
Test status
Simulation time 356912554 ps
CPU time 1.08 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 204988 kb
Host smart-edb8baf3-d92f-4cf3-8681-1a0ffd7a614e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210808772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
210808772
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3953277718
Short name T387
Test name
Test status
Simulation time 125282657 ps
CPU time 1.01 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:49 PM PDT 24
Peak memory 205048 kb
Host smart-5b9f17c9-c35f-47e3-96b4-5a96f4408c49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953277718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3953277718
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2041690384
Short name T349
Test name
Test status
Simulation time 43286763 ps
CPU time 0.75 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:46:49 PM PDT 24
Peak memory 204960 kb
Host smart-10421fd3-5ed6-4589-97f5-fc4463109c44
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041690384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2041690384
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2674155458
Short name T442
Test name
Test status
Simulation time 105287095 ps
CPU time 3.8 seconds
Started Aug 07 04:46:51 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 205312 kb
Host smart-e83a51ad-ebeb-49f6-9b00-788c1f8cb3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674155458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2674155458
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1393498009
Short name T369
Test name
Test status
Simulation time 40134969955 ps
CPU time 178.58 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:49:47 PM PDT 24
Peak memory 221540 kb
Host smart-c6640f05-8f4a-40e2-9d7a-e239c02387d4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393498009 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1393498009
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1788512828
Short name T322
Test name
Test status
Simulation time 286306881 ps
CPU time 2.97 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:46:51 PM PDT 24
Peak memory 213600 kb
Host smart-42dc88af-3fbb-4e9c-8e85-d555d2f31f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788512828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1788512828
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2520539709
Short name T430
Test name
Test status
Simulation time 2803402369 ps
CPU time 10.49 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:58 PM PDT 24
Peak memory 213612 kb
Host smart-40d4cd0a-947e-4d96-81c9-ddf05aadbafb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520539709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2520539709
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3846865792
Short name T351
Test name
Test status
Simulation time 3300558285 ps
CPU time 65.74 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:47:53 PM PDT 24
Peak memory 205316 kb
Host smart-3d0f551a-4f43-4f45-a817-fd9ac344acbf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846865792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3846865792
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.229957694
Short name T399
Test name
Test status
Simulation time 3702806852 ps
CPU time 36.77 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 205120 kb
Host smart-cd47f406-8151-47f3-a966-23d41f0dbb3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229957694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.229957694
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3622204708
Short name T124
Test name
Test status
Simulation time 156719628 ps
CPU time 1.93 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:46:56 PM PDT 24
Peak memory 213468 kb
Host smart-84e78683-45f6-4023-83d4-6b8dd02d8e9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622204708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3622204708
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2178882678
Short name T356
Test name
Test status
Simulation time 281460159 ps
CPU time 2.6 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:56 PM PDT 24
Peak memory 215536 kb
Host smart-1b4107e1-1542-43cb-9ec0-22baaa862e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178882678 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2178882678
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1504388350
Short name T379
Test name
Test status
Simulation time 461088206 ps
CPU time 1.53 seconds
Started Aug 07 04:46:52 PM PDT 24
Finished Aug 07 04:46:54 PM PDT 24
Peak memory 213488 kb
Host smart-ccf717b7-40e8-4da6-ba24-720648f5f787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504388350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1504388350
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3606568524
Short name T334
Test name
Test status
Simulation time 16417030489 ps
CPU time 27.51 seconds
Started Aug 07 04:46:49 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 205340 kb
Host smart-884044e0-0887-4afa-842b-204c7409a55b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606568524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3606568524
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3854389315
Short name T341
Test name
Test status
Simulation time 27788569845 ps
CPU time 40.29 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 205256 kb
Host smart-905e8127-c050-467b-9861-c34834a93a25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854389315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3854389315
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1437395029
Short name T321
Test name
Test status
Simulation time 3778448582 ps
CPU time 5.33 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:46:53 PM PDT 24
Peak memory 205356 kb
Host smart-8057d7c7-341b-4139-bea6-d66360710407
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437395029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1437395029
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2615522047
Short name T357
Test name
Test status
Simulation time 2398872601 ps
CPU time 5.86 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:59 PM PDT 24
Peak memory 205256 kb
Host smart-24276c16-08ea-422a-bd1b-85c063b1b01e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615522047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
615522047
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1964499885
Short name T422
Test name
Test status
Simulation time 15497310533 ps
CPU time 24.36 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 205220 kb
Host smart-d2b4a8cc-1f13-4fec-a874-3df212349258
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964499885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1964499885
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3836455632
Short name T391
Test name
Test status
Simulation time 498526946 ps
CPU time 0.96 seconds
Started Aug 07 04:46:51 PM PDT 24
Finished Aug 07 04:46:52 PM PDT 24
Peak memory 205024 kb
Host smart-68af097e-23d4-4d49-beb0-afec05ccc591
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836455632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3836455632
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2351845663
Short name T373
Test name
Test status
Simulation time 221974112 ps
CPU time 1.23 seconds
Started Aug 07 04:46:47 PM PDT 24
Finished Aug 07 04:46:49 PM PDT 24
Peak memory 204936 kb
Host smart-50d24c64-c8b5-4ecd-808e-2380743d2b0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351845663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
351845663
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2677144856
Short name T402
Test name
Test status
Simulation time 141263623 ps
CPU time 1.04 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:01 PM PDT 24
Peak memory 205008 kb
Host smart-8a10736b-39a5-40c0-882d-8e288276fc21
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677144856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2677144856
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1223696025
Short name T338
Test name
Test status
Simulation time 72272094 ps
CPU time 0.69 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:47:00 PM PDT 24
Peak memory 205032 kb
Host smart-83d4e44e-9a42-4fe6-a340-44eeb4f6d061
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223696025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1223696025
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2570726228
Short name T431
Test name
Test status
Simulation time 182333080 ps
CPU time 3.04 seconds
Started Aug 07 04:46:48 PM PDT 24
Finished Aug 07 04:46:51 PM PDT 24
Peak memory 213548 kb
Host smart-5bea27c6-27f8-4f5c-8a7a-d3fc0df0403b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570726228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2570726228
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.643029384
Short name T135
Test name
Test status
Simulation time 2439941184 ps
CPU time 21.32 seconds
Started Aug 07 04:46:51 PM PDT 24
Finished Aug 07 04:47:13 PM PDT 24
Peak memory 213556 kb
Host smart-22500d43-6a3d-482d-a54d-32b0f0664d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643029384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.643029384
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3767348613
Short name T456
Test name
Test status
Simulation time 145690377 ps
CPU time 2.52 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 218456 kb
Host smart-7199d77c-f874-4e23-805f-f8e2da75ba61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767348613 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3767348613
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.458312422
Short name T118
Test name
Test status
Simulation time 281880685 ps
CPU time 1.57 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:09 PM PDT 24
Peak memory 213436 kb
Host smart-7bb32cf0-e52d-4883-81ff-9be27027272b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458312422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.458312422
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2423856746
Short name T314
Test name
Test status
Simulation time 52619519973 ps
CPU time 19.65 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 205232 kb
Host smart-6992d74a-8aaf-4879-9e6d-9863e7ab6689
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423856746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2423856746
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3883713615
Short name T327
Test name
Test status
Simulation time 11967941411 ps
CPU time 30.37 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 205260 kb
Host smart-410fabaa-755c-4bc7-ba18-4d383e860716
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883713615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3883713615
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.892585133
Short name T348
Test name
Test status
Simulation time 196987717 ps
CPU time 0.75 seconds
Started Aug 07 04:47:10 PM PDT 24
Finished Aug 07 04:47:10 PM PDT 24
Peak memory 205048 kb
Host smart-5eeadad9-8803-4e76-84b2-64fd763c7f3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892585133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.892585133
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2796757081
Short name T397
Test name
Test status
Simulation time 124406773 ps
CPU time 4.04 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 205276 kb
Host smart-f72bc6cf-ef46-4f53-b29f-386aa6ac0054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796757081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2796757081
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.691039783
Short name T102
Test name
Test status
Simulation time 96693057 ps
CPU time 4.43 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 213576 kb
Host smart-45d8af56-601f-4195-8624-b4955b25308c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691039783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.691039783
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3427333812
Short name T132
Test name
Test status
Simulation time 2064251934 ps
CPU time 10.56 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:22 PM PDT 24
Peak memory 213484 kb
Host smart-626e0082-a585-447d-a649-8adeac89324a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427333812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
427333812
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1507522571
Short name T364
Test name
Test status
Simulation time 157748521 ps
CPU time 2.28 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 215224 kb
Host smart-0ad7e832-a33c-4763-b25a-c1bee18c3636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507522571 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1507522571
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2119129879
Short name T455
Test name
Test status
Simulation time 827826664 ps
CPU time 2.46 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 213412 kb
Host smart-35193b45-db32-4664-90ef-978a4ad5d36a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119129879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2119129879
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.425309799
Short name T453
Test name
Test status
Simulation time 11444371488 ps
CPU time 28.5 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 205256 kb
Host smart-5bea0867-ef38-4fa7-9b53-eed77ebb054a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425309799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rv_dm_jtag_dmi_csr_bit_bash.425309799
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3229287551
Short name T318
Test name
Test status
Simulation time 1756955665 ps
CPU time 5.33 seconds
Started Aug 07 04:47:15 PM PDT 24
Finished Aug 07 04:47:20 PM PDT 24
Peak memory 205220 kb
Host smart-d425ccc3-e06a-4d14-bf62-96b072aa6129
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229287551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3229287551
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.961823720
Short name T454
Test name
Test status
Simulation time 383413966 ps
CPU time 0.77 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:09 PM PDT 24
Peak memory 204940 kb
Host smart-fde37bed-6fc6-45e8-8ec6-d07337a87813
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961823720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.961823720
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3102576712
Short name T440
Test name
Test status
Simulation time 1082010118 ps
CPU time 7.69 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 205304 kb
Host smart-776aa229-e8f7-4d08-ba43-5552e41a8187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102576712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3102576712
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2804405949
Short name T409
Test name
Test status
Simulation time 190875916 ps
CPU time 5.56 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 213612 kb
Host smart-1c68f21c-5b5b-4b49-b075-0a0bb5dad0ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804405949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2804405949
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1826632942
Short name T449
Test name
Test status
Simulation time 4316003575 ps
CPU time 28.33 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 213196 kb
Host smart-349cf881-7083-4ebe-9f2d-ccd9b89fe94d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826632942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
826632942
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.88190799
Short name T103
Test name
Test status
Simulation time 291844860 ps
CPU time 2.31 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 217920 kb
Host smart-c05f5123-d606-409b-b2f3-15f229fc37f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88190799 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.88190799
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2205706412
Short name T383
Test name
Test status
Simulation time 76797330 ps
CPU time 1.49 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 213532 kb
Host smart-4903c893-a484-45eb-a28d-4ebf8def580d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205706412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2205706412
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3820749095
Short name T410
Test name
Test status
Simulation time 26708641883 ps
CPU time 72.89 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:48:19 PM PDT 24
Peak memory 205300 kb
Host smart-1e68e512-b3e8-441d-a581-2a4013c56157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820749095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3820749095
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2466979204
Short name T435
Test name
Test status
Simulation time 1407843537 ps
CPU time 1.5 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:13 PM PDT 24
Peak memory 205148 kb
Host smart-dd1eaa36-2a06-43de-9429-47d63ce6c206
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466979204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2466979204
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2579490230
Short name T464
Test name
Test status
Simulation time 389213760 ps
CPU time 0.93 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:08 PM PDT 24
Peak memory 204980 kb
Host smart-45e4c01b-6a95-4c54-9721-771aeeeab1da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579490230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2579490230
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.208869135
Short name T129
Test name
Test status
Simulation time 1446302624 ps
CPU time 4.32 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 205368 kb
Host smart-33f42fc4-7704-493f-ae4a-091365889177
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208869135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.208869135
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1158535532
Short name T368
Test name
Test status
Simulation time 233279871 ps
CPU time 4.32 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 213552 kb
Host smart-86ec3bb5-f45b-431f-8a5f-3cad7481363f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158535532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1158535532
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.518749959
Short name T163
Test name
Test status
Simulation time 2024046994 ps
CPU time 20.61 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:29 PM PDT 24
Peak memory 213576 kb
Host smart-12224244-2872-459c-91db-d267be9e37f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518749959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.518749959
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3320213977
Short name T400
Test name
Test status
Simulation time 782486425 ps
CPU time 2.58 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 221748 kb
Host smart-094697ca-25d1-44fb-a489-3a97b7a933f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320213977 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3320213977
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4135039596
Short name T320
Test name
Test status
Simulation time 11800687810 ps
CPU time 12.37 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 205308 kb
Host smart-95c1a9a3-45de-4d69-80cc-2e8b0e492f0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135039596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.4135039596
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.378676469
Short name T309
Test name
Test status
Simulation time 1626492909 ps
CPU time 4.43 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 205128 kb
Host smart-6818dfd3-9cb9-46e6-adb9-7950d08fe322
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378676469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.378676469
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.411365736
Short name T355
Test name
Test status
Simulation time 716274856 ps
CPU time 1.04 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:10 PM PDT 24
Peak memory 204976 kb
Host smart-7ce22804-8aa9-4c72-b843-6c51b94aa0d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411365736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.411365736
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3031556979
Short name T376
Test name
Test status
Simulation time 384326657 ps
CPU time 6.6 seconds
Started Aug 07 04:47:10 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 205272 kb
Host smart-79feca21-d6ca-46a6-884a-254111f5a441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031556979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3031556979
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4248229424
Short name T365
Test name
Test status
Simulation time 564470169 ps
CPU time 3.85 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 213644 kb
Host smart-77d8a4f9-7a7c-40e0-bd22-f9d0c48c571d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248229424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4248229424
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3180675074
Short name T82
Test name
Test status
Simulation time 328693174 ps
CPU time 2.58 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 218168 kb
Host smart-c3daf212-0205-4e7b-bb2c-84862c836d47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180675074 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3180675074
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1664777719
Short name T100
Test name
Test status
Simulation time 110933086 ps
CPU time 2.55 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 213560 kb
Host smart-ff693c5a-98a7-46da-a993-0415261eeaaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664777719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1664777719
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4231881620
Short name T413
Test name
Test status
Simulation time 21789901307 ps
CPU time 51.49 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:48:05 PM PDT 24
Peak memory 205292 kb
Host smart-a03d80f9-5b15-4791-990e-c0566b6cce1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231881620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4231881620
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3444236138
Short name T427
Test name
Test status
Simulation time 7232990570 ps
CPU time 6.52 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 205312 kb
Host smart-cc8649d3-a6c6-445e-948f-5d40de55d32f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444236138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3444236138
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2538607023
Short name T404
Test name
Test status
Simulation time 420625356 ps
CPU time 1.24 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 204552 kb
Host smart-36181b73-0c20-4180-8acd-7595a26e8898
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538607023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2538607023
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3412292797
Short name T115
Test name
Test status
Simulation time 1002033736 ps
CPU time 4.47 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:21 PM PDT 24
Peak memory 205320 kb
Host smart-20b61f03-f613-4071-80b3-5b9652340193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412292797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3412292797
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.962916279
Short name T405
Test name
Test status
Simulation time 357668229 ps
CPU time 6.3 seconds
Started Aug 07 04:47:17 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 213564 kb
Host smart-e7f11340-f2fa-495b-a4d8-0cfc550a46b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962916279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.962916279
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1636888309
Short name T419
Test name
Test status
Simulation time 4252195657 ps
CPU time 11.2 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 213576 kb
Host smart-f4b7616f-7bf8-4428-a709-7c3bb7bbd541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636888309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
636888309
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1694879188
Short name T465
Test name
Test status
Simulation time 321436163 ps
CPU time 4.36 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 220264 kb
Host smart-088060ce-4c82-40c2-9c91-f671dc787de9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694879188 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1694879188
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3034453015
Short name T93
Test name
Test status
Simulation time 76222154 ps
CPU time 1.47 seconds
Started Aug 07 04:47:15 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 213380 kb
Host smart-512c8551-a959-4962-a41d-0bae5589974e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034453015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3034453015
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1094808059
Short name T452
Test name
Test status
Simulation time 30030234900 ps
CPU time 72.93 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:48:26 PM PDT 24
Peak memory 205292 kb
Host smart-2d072191-734a-488c-9b53-dabb9d9cd35b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094808059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1094808059
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3146279418
Short name T307
Test name
Test status
Simulation time 8764635142 ps
CPU time 24.66 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 205304 kb
Host smart-c6c15c13-26ca-4167-b4ac-170f242ffc98
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146279418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3146279418
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2369125601
Short name T359
Test name
Test status
Simulation time 194775518 ps
CPU time 0.95 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:26 PM PDT 24
Peak memory 204980 kb
Host smart-1c7a60b6-bd5b-4e57-8d0a-4e5ac6e4934b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369125601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2369125601
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4234128950
Short name T95
Test name
Test status
Simulation time 336291032 ps
CPU time 3.56 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 205320 kb
Host smart-e9c8b8b4-89b4-4012-a7ae-a0bec6d3475d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234128950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4234128950
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3154384134
Short name T448
Test name
Test status
Simulation time 203379320 ps
CPU time 3.01 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 216172 kb
Host smart-9631d8b1-737c-4fe6-9a72-270490a8653b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154384134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3154384134
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3588616614
Short name T411
Test name
Test status
Simulation time 5554381723 ps
CPU time 19.74 seconds
Started Aug 07 04:47:19 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 213644 kb
Host smart-c9999d80-40d1-4f7b-8d08-562d985e670a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588616614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
588616614
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4077539027
Short name T84
Test name
Test status
Simulation time 182758275 ps
CPU time 2.56 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 213560 kb
Host smart-4bb7e349-3ecc-4362-b155-2d6bf4a41bfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077539027 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4077539027
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1613667474
Short name T434
Test name
Test status
Simulation time 87280376 ps
CPU time 1.67 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 213604 kb
Host smart-5faebf6a-6ea7-4300-adcb-c0a78364e247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613667474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1613667474
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4041864115
Short name T426
Test name
Test status
Simulation time 45085414776 ps
CPU time 34.12 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:48:11 PM PDT 24
Peak memory 205300 kb
Host smart-6fc6a565-603a-4fc7-b475-5e10b4554db8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041864115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.4041864115
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1615263344
Short name T375
Test name
Test status
Simulation time 12868408903 ps
CPU time 17.77 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:30 PM PDT 24
Peak memory 205276 kb
Host smart-2f39a4e8-9631-4908-ae11-869c95fdc2dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615263344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1615263344
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3381510429
Short name T420
Test name
Test status
Simulation time 305546593 ps
CPU time 1.49 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 204936 kb
Host smart-9d1566dc-0574-47d6-8926-ed2ed2d809c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381510429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3381510429
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1341057757
Short name T127
Test name
Test status
Simulation time 892584626 ps
CPU time 3.95 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:23 PM PDT 24
Peak memory 205296 kb
Host smart-a9a327bf-4815-4e2f-b78d-34defb502b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341057757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1341057757
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1311851302
Short name T323
Test name
Test status
Simulation time 196650204 ps
CPU time 4.11 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 213552 kb
Host smart-2ad26016-1e37-4b89-839e-e59c06693da2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311851302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1311851302
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.169953087
Short name T336
Test name
Test status
Simulation time 3410629231 ps
CPU time 11.14 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 213580 kb
Host smart-2d4701aa-d552-4d62-82d7-5bb8bb92008a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169953087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.169953087
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3581922382
Short name T385
Test name
Test status
Simulation time 512637239 ps
CPU time 3.75 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 219428 kb
Host smart-bc628c8b-2195-4511-9568-ef82bc7c6b9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581922382 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3581922382
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1443177650
Short name T108
Test name
Test status
Simulation time 432887256 ps
CPU time 2.42 seconds
Started Aug 07 04:47:31 PM PDT 24
Finished Aug 07 04:47:34 PM PDT 24
Peak memory 213452 kb
Host smart-4d33bff8-9269-4581-93b2-b448474df47e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443177650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1443177650
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3013498392
Short name T317
Test name
Test status
Simulation time 58198549506 ps
CPU time 59.22 seconds
Started Aug 07 04:47:15 PM PDT 24
Finished Aug 07 04:48:15 PM PDT 24
Peak memory 205328 kb
Host smart-bb1170fd-0803-44ee-a1b4-ead3a86eb358
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013498392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3013498392
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1711664430
Short name T433
Test name
Test status
Simulation time 2856228463 ps
CPU time 2.59 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 205308 kb
Host smart-093ce370-7ce8-458c-b5c8-006a8fddd486
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711664430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1711664430
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1444808987
Short name T407
Test name
Test status
Simulation time 745882252 ps
CPU time 2.43 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 204976 kb
Host smart-686840de-880d-4860-84f5-dbe6a2a701f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444808987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1444808987
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3760633630
Short name T114
Test name
Test status
Simulation time 351801397 ps
CPU time 4.18 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 205300 kb
Host smart-84a2e681-8d7b-4200-9d4c-cbb81a2753f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760633630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3760633630
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1563614027
Short name T328
Test name
Test status
Simulation time 242940412 ps
CPU time 4.38 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 213604 kb
Host smart-d9b0b1a1-dadd-46e1-b1db-b85ddf8ed854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563614027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1563614027
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3794525083
Short name T417
Test name
Test status
Simulation time 1341202665 ps
CPU time 11.44 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 213668 kb
Host smart-53ced396-3af8-4f8b-83da-c39f0e287433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794525083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
794525083
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1792649372
Short name T372
Test name
Test status
Simulation time 358387125 ps
CPU time 2.08 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 216836 kb
Host smart-41765c31-840e-474d-a146-554e7b9cf434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792649372 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1792649372
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1870774121
Short name T94
Test name
Test status
Simulation time 215190001 ps
CPU time 2.18 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 213436 kb
Host smart-d1d3fd5c-24ad-43c8-8d4c-af5b5f80a6ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870774121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1870774121
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1328231647
Short name T308
Test name
Test status
Simulation time 8269437260 ps
CPU time 3.62 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 205284 kb
Host smart-b2a4f50f-5ac7-4cf3-a189-26767604523f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328231647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1328231647
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4219453651
Short name T312
Test name
Test status
Simulation time 5642347806 ps
CPU time 4.7 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 205344 kb
Host smart-25ceb95c-f8b3-4b2f-9633-76e98b61e977
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219453651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
4219453651
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2925731367
Short name T398
Test name
Test status
Simulation time 500179779 ps
CPU time 1.04 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 205076 kb
Host smart-3185aedb-8c94-4918-8bf1-3f378c616198
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925731367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2925731367
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3913216118
Short name T112
Test name
Test status
Simulation time 1659685371 ps
CPU time 8.15 seconds
Started Aug 07 04:47:18 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 205312 kb
Host smart-ce24604f-9d2c-42b9-bc2c-aaebe00f1683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913216118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3913216118
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2618872355
Short name T386
Test name
Test status
Simulation time 1617453464 ps
CPU time 3.76 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 213616 kb
Host smart-a9319dfc-1a4e-4fe6-874e-fe7a0e61aa34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618872355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2618872355
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3237122474
Short name T432
Test name
Test status
Simulation time 361834348 ps
CPU time 4.34 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:30 PM PDT 24
Peak memory 219972 kb
Host smart-360affe8-8503-45d7-a1c1-f63a1a23fac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237122474 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3237122474
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.646052059
Short name T119
Test name
Test status
Simulation time 166376183 ps
CPU time 1.58 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 213484 kb
Host smart-bcdddead-27fd-4494-9739-444fc90f0bb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646052059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.646052059
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4219312939
Short name T416
Test name
Test status
Simulation time 2543311477 ps
CPU time 4.81 seconds
Started Aug 07 04:47:33 PM PDT 24
Finished Aug 07 04:47:38 PM PDT 24
Peak memory 205228 kb
Host smart-c41f32b6-4d7a-4bd8-9eb6-75a83c7198c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219312939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.4219312939
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2083373682
Short name T340
Test name
Test status
Simulation time 1193575427 ps
CPU time 4.08 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 205148 kb
Host smart-0a60683b-9b40-4aaf-93de-19e7b31d19fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083373682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2083373682
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2111757393
Short name T380
Test name
Test status
Simulation time 385900567 ps
CPU time 1.24 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 204940 kb
Host smart-abe4df6b-73cd-4784-9e4d-d73ea30d22a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111757393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2111757393
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.690948012
Short name T126
Test name
Test status
Simulation time 289902461 ps
CPU time 6.42 seconds
Started Aug 07 04:47:19 PM PDT 24
Finished Aug 07 04:47:26 PM PDT 24
Peak memory 205276 kb
Host smart-f64bb862-f1b3-43c2-89a3-dad9c3a66f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690948012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.690948012
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1380070834
Short name T346
Test name
Test status
Simulation time 144081658 ps
CPU time 3 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 213524 kb
Host smart-84bb71d7-be2b-41a6-900d-ead7ca6225aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380070834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1380070834
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.731317185
Short name T378
Test name
Test status
Simulation time 1493177204 ps
CPU time 8.8 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:22 PM PDT 24
Peak memory 213504 kb
Host smart-7d7d52a2-a25e-41dc-a374-96206d6d574f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731317185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.731317185
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4097236392
Short name T401
Test name
Test status
Simulation time 15713996033 ps
CPU time 78.88 seconds
Started Aug 07 04:46:52 PM PDT 24
Finished Aug 07 04:48:11 PM PDT 24
Peak memory 213576 kb
Host smart-171c768f-c510-4316-ac31-53ef388b0404
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097236392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.4097236392
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4170144107
Short name T92
Test name
Test status
Simulation time 2573399026 ps
CPU time 35.24 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:47:29 PM PDT 24
Peak memory 213516 kb
Host smart-5cbf6e49-a03b-44eb-98bc-c5dace6441e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170144107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4170144107
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.259466846
Short name T447
Test name
Test status
Simulation time 296816868 ps
CPU time 1.7 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 213448 kb
Host smart-d09b47ea-c8ec-48c4-bef9-0c8130965a62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259466846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.259466846
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3026856539
Short name T319
Test name
Test status
Simulation time 285987174 ps
CPU time 2.43 seconds
Started Aug 07 04:46:52 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 218248 kb
Host smart-d18c4c6f-9256-466c-9308-a2e904eefec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026856539 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3026856539
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2906904889
Short name T450
Test name
Test status
Simulation time 164273032 ps
CPU time 2.27 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:46:56 PM PDT 24
Peak memory 213336 kb
Host smart-4c3ed184-1012-4f89-b4db-3a8b44ff8d55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906904889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2906904889
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1086264942
Short name T392
Test name
Test status
Simulation time 28191073697 ps
CPU time 59.34 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 205316 kb
Host smart-15ee1466-c2da-4cc7-b15c-ff7c09815681
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086264942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1086264942
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4101986914
Short name T408
Test name
Test status
Simulation time 37041633167 ps
CPU time 99.02 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:48:39 PM PDT 24
Peak memory 204996 kb
Host smart-9ba6b6a9-cc01-40b0-b67b-037e2cae8bfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101986914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.4101986914
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2789298952
Short name T107
Test name
Test status
Simulation time 7187571514 ps
CPU time 19.58 seconds
Started Aug 07 04:46:55 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 205388 kb
Host smart-aac826fb-fa23-47a9-956f-682e0aac08c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789298952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2789298952
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1234379496
Short name T458
Test name
Test status
Simulation time 967862830 ps
CPU time 2.41 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:56 PM PDT 24
Peak memory 205140 kb
Host smart-be0dc2d3-0106-4914-934e-89ff0adc05d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234379496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
234379496
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4272843109
Short name T68
Test name
Test status
Simulation time 258230526 ps
CPU time 1.08 seconds
Started Aug 07 04:46:55 PM PDT 24
Finished Aug 07 04:46:56 PM PDT 24
Peak memory 204976 kb
Host smart-a2b3bb40-d3b9-4aee-b578-fa75b9003369
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272843109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.4272843109
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4205040108
Short name T326
Test name
Test status
Simulation time 5887114535 ps
CPU time 6.52 seconds
Started Aug 07 04:46:51 PM PDT 24
Finished Aug 07 04:46:58 PM PDT 24
Peak memory 205252 kb
Host smart-0ebf28c2-6216-49ba-ae08-717d5b789a31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205040108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4205040108
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1945855590
Short name T421
Test name
Test status
Simulation time 203085953 ps
CPU time 0.75 seconds
Started Aug 07 04:46:55 PM PDT 24
Finished Aug 07 04:46:56 PM PDT 24
Peak memory 205016 kb
Host smart-52f9b7ad-296d-4e1e-83aa-022579c728c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945855590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1945855590
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2239980915
Short name T396
Test name
Test status
Simulation time 284027056 ps
CPU time 1.05 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 204948 kb
Host smart-43b88073-aa73-4ae1-b4c1-54d270c279d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239980915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
239980915
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1985612099
Short name T315
Test name
Test status
Simulation time 150105836 ps
CPU time 0.9 seconds
Started Aug 07 04:46:54 PM PDT 24
Finished Aug 07 04:46:55 PM PDT 24
Peak memory 205040 kb
Host smart-f3b38936-b4eb-4670-b632-39b537b57322
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985612099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1985612099
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3305550754
Short name T438
Test name
Test status
Simulation time 123173538 ps
CPU time 0.75 seconds
Started Aug 07 04:46:52 PM PDT 24
Finished Aug 07 04:46:53 PM PDT 24
Peak memory 204956 kb
Host smart-b33d6c38-9c64-48fe-a0fb-dfefa238c218
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305550754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3305550754
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.827112958
Short name T101
Test name
Test status
Simulation time 593858228 ps
CPU time 6.36 seconds
Started Aug 07 04:46:58 PM PDT 24
Finished Aug 07 04:47:04 PM PDT 24
Peak memory 205288 kb
Host smart-bdf192d0-dd59-44f7-95aa-f4c4482274c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827112958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.827112958
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2499686045
Short name T436
Test name
Test status
Simulation time 44123442015 ps
CPU time 267.38 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:51:21 PM PDT 24
Peak memory 221868 kb
Host smart-16459442-4dcb-43c1-88e6-2f8063c4ffde
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499686045 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2499686045
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3337526617
Short name T460
Test name
Test status
Simulation time 416665034 ps
CPU time 4.31 seconds
Started Aug 07 04:46:53 PM PDT 24
Finished Aug 07 04:46:58 PM PDT 24
Peak memory 213604 kb
Host smart-b0dc07c5-0b24-4cb8-b1f3-4982dae50f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337526617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3337526617
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1127945473
Short name T117
Test name
Test status
Simulation time 1553397091 ps
CPU time 52.39 seconds
Started Aug 07 04:47:03 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 205228 kb
Host smart-2627e95a-f36f-48e1-ac5f-af709de0ff25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127945473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1127945473
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3698976322
Short name T123
Test name
Test status
Simulation time 270412429 ps
CPU time 2.23 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:47:01 PM PDT 24
Peak memory 213736 kb
Host smart-93a5f99e-e490-4572-a3a6-b0565dfbbf6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698976322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3698976322
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4029590845
Short name T457
Test name
Test status
Simulation time 347840388 ps
CPU time 4.1 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:04 PM PDT 24
Peak memory 219584 kb
Host smart-f4f5b399-2ad6-4f30-a7df-3d7c3cfe2da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029590845 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4029590845
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1176408331
Short name T130
Test name
Test status
Simulation time 113972615 ps
CPU time 2.36 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:47:01 PM PDT 24
Peak memory 213476 kb
Host smart-c7b3a1fe-6141-4666-bdf3-136b5fc65384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176408331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1176408331
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.546582846
Short name T310
Test name
Test status
Simulation time 52795310404 ps
CPU time 148.59 seconds
Started Aug 07 04:47:03 PM PDT 24
Finished Aug 07 04:49:31 PM PDT 24
Peak memory 205300 kb
Host smart-652b9a45-5018-4b87-b006-4bf0d51493b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546582846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.546582846
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3645344530
Short name T347
Test name
Test status
Simulation time 52501804 ps
CPU time 0.69 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:02 PM PDT 24
Peak memory 204976 kb
Host smart-b4d2963b-81a1-4654-ab9c-4338188b8cd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645344530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3645344530
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2254897970
Short name T104
Test name
Test status
Simulation time 4132197473 ps
CPU time 10.75 seconds
Started Aug 07 04:47:03 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 205292 kb
Host smart-f285d372-fc78-4e8f-b760-b2af66c11d56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254897970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2254897970
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3723761193
Short name T325
Test name
Test status
Simulation time 7119878318 ps
CPU time 19.77 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 205280 kb
Host smart-8ddd3cef-5e3e-4264-a17a-322947f59a34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723761193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
723761193
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1505746280
Short name T406
Test name
Test status
Simulation time 588600132 ps
CPU time 2.12 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:06 PM PDT 24
Peak memory 204892 kb
Host smart-66b2bd5e-1f09-44ea-91e5-b78b60d3b405
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505746280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1505746280
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1734445895
Short name T70
Test name
Test status
Simulation time 5001793781 ps
CPU time 15.88 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 205268 kb
Host smart-a3c2ff82-0e80-4634-9377-d11e4efdc984
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734445895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1734445895
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4109410598
Short name T361
Test name
Test status
Simulation time 143986638 ps
CPU time 1.07 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 204992 kb
Host smart-bb212602-0471-4f8d-ac00-bac06e692fa6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109410598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4109410598
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2645072074
Short name T403
Test name
Test status
Simulation time 504108868 ps
CPU time 1.39 seconds
Started Aug 07 04:47:02 PM PDT 24
Finished Aug 07 04:47:03 PM PDT 24
Peak memory 204960 kb
Host smart-305e9559-4093-420a-bde0-125be40d864a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645072074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
645072074
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4018000385
Short name T332
Test name
Test status
Simulation time 47228970 ps
CPU time 0.73 seconds
Started Aug 07 04:47:03 PM PDT 24
Finished Aug 07 04:47:04 PM PDT 24
Peak memory 205052 kb
Host smart-1cea6094-df53-43d4-af4b-9f3784521daa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018000385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.4018000385
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.92644709
Short name T345
Test name
Test status
Simulation time 144086013 ps
CPU time 0.91 seconds
Started Aug 07 04:47:02 PM PDT 24
Finished Aug 07 04:47:03 PM PDT 24
Peak memory 204920 kb
Host smart-12c10933-3313-4428-b81b-fdecd511b72b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92644709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.92644709
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.29552580
Short name T393
Test name
Test status
Simulation time 389557552 ps
CPU time 6.89 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 205340 kb
Host smart-0305ff78-1c15-4b40-bf51-0c18b8e965f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29552580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_cs
r_outstanding.29552580
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3198227029
Short name T169
Test name
Test status
Simulation time 29224158312 ps
CPU time 213 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:50:38 PM PDT 24
Peak memory 221968 kb
Host smart-f838cda8-7f80-493a-82d7-03f8efbfb4c9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198227029 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3198227029
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3318933001
Short name T414
Test name
Test status
Simulation time 2113994595 ps
CPU time 4.37 seconds
Started Aug 07 04:47:03 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 213608 kb
Host smart-1f3255bd-923e-47c5-a2d9-8398b62384f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318933001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3318933001
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3504777237
Short name T121
Test name
Test status
Simulation time 6612575436 ps
CPU time 30.75 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 205380 kb
Host smart-0824c4a7-2407-4269-8b98-d9d5a22e7f6a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504777237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3504777237
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1246885328
Short name T443
Test name
Test status
Simulation time 6428649397 ps
CPU time 73.95 seconds
Started Aug 07 04:47:02 PM PDT 24
Finished Aug 07 04:48:16 PM PDT 24
Peak memory 213580 kb
Host smart-94391072-506f-4631-a019-e517e7d1b660
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246885328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1246885328
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4123582593
Short name T444
Test name
Test status
Simulation time 340306401 ps
CPU time 2.94 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:47:02 PM PDT 24
Peak memory 213484 kb
Host smart-83314e6c-1205-49e2-96f4-7a26843d1181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123582593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4123582593
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2874128389
Short name T412
Test name
Test status
Simulation time 927209908 ps
CPU time 4.14 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 221336 kb
Host smart-d5ec851d-0c4c-47e3-b64b-e8cfb7a41210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874128389 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2874128389
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.810700260
Short name T116
Test name
Test status
Simulation time 289673701 ps
CPU time 1.77 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:03 PM PDT 24
Peak memory 213388 kb
Host smart-96a06014-6d2b-40bd-b608-c855e9ead7ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810700260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.810700260
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2236093092
Short name T394
Test name
Test status
Simulation time 211879909444 ps
CPU time 165.02 seconds
Started Aug 07 04:46:57 PM PDT 24
Finished Aug 07 04:49:42 PM PDT 24
Peak memory 210300 kb
Host smart-b581fd96-36dd-43c1-b239-f22fa58d62f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236093092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2236093092
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3884762420
Short name T463
Test name
Test status
Simulation time 58987028764 ps
CPU time 154.86 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:49:39 PM PDT 24
Peak memory 205028 kb
Host smart-0495bb3e-1978-45e1-b188-c917ec79447d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884762420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3884762420
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2350944228
Short name T105
Test name
Test status
Simulation time 1168429089 ps
CPU time 4.28 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:06 PM PDT 24
Peak memory 205260 kb
Host smart-cc406330-0c37-44b3-8783-689991929619
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350944228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2350944228
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3622403801
Short name T390
Test name
Test status
Simulation time 1223857813 ps
CPU time 1.58 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:05 PM PDT 24
Peak memory 205164 kb
Host smart-f1bacec7-10d2-4d13-85ac-f78c7663accd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622403801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
622403801
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.70866721
Short name T316
Test name
Test status
Simulation time 1158329120 ps
CPU time 3.08 seconds
Started Aug 07 04:47:02 PM PDT 24
Finished Aug 07 04:47:05 PM PDT 24
Peak memory 204984 kb
Host smart-0cf06be3-3540-4e65-948f-9f28987018e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70866721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
aliasing.70866721
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3913685131
Short name T441
Test name
Test status
Simulation time 6459564901 ps
CPU time 17.45 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 205264 kb
Host smart-2705d7eb-9f46-4e5b-916f-b0326831a729
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913685131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3913685131
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.753155316
Short name T437
Test name
Test status
Simulation time 348804256 ps
CPU time 1.62 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 205104 kb
Host smart-b404c151-28e0-4844-a3a8-d70dac9c22e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753155316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.753155316
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.185475344
Short name T350
Test name
Test status
Simulation time 429128455 ps
CPU time 1.68 seconds
Started Aug 07 04:46:58 PM PDT 24
Finished Aug 07 04:47:00 PM PDT 24
Peak memory 204972 kb
Host smart-7b2864a5-5d09-4542-b5f9-3122a94bb80c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185475344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.185475344
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2616632597
Short name T324
Test name
Test status
Simulation time 91799784 ps
CPU time 0.72 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:46:59 PM PDT 24
Peak memory 205024 kb
Host smart-23032319-148f-4517-9af1-336e7e68da15
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616632597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2616632597
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3007077929
Short name T354
Test name
Test status
Simulation time 143872861 ps
CPU time 1.04 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:02 PM PDT 24
Peak memory 204952 kb
Host smart-a680fc19-5cf1-4efc-8113-5c606e281474
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007077929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3007077929
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2417530138
Short name T125
Test name
Test status
Simulation time 436501031 ps
CPU time 6.58 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 205320 kb
Host smart-30f3d613-d1c7-487b-b04b-222f68a666e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417530138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2417530138
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2301016854
Short name T425
Test name
Test status
Simulation time 16529564157 ps
CPU time 17.75 seconds
Started Aug 07 04:47:02 PM PDT 24
Finished Aug 07 04:47:20 PM PDT 24
Peak memory 220244 kb
Host smart-082d4f3a-e64d-4798-a3fa-6477de3fddf6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301016854 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2301016854
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.843176095
Short name T370
Test name
Test status
Simulation time 1262975946 ps
CPU time 5.63 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:06 PM PDT 24
Peak memory 213600 kb
Host smart-9ceb1802-6327-4a30-8652-96cd48735c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843176095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.843176095
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3040213617
Short name T363
Test name
Test status
Simulation time 4439099801 ps
CPU time 19.3 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 213572 kb
Host smart-0a061aad-2ff3-4340-9a41-ae95efc05193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040213617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3040213617
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.298587308
Short name T133
Test name
Test status
Simulation time 783270572 ps
CPU time 3.91 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:04 PM PDT 24
Peak memory 218616 kb
Host smart-fc494059-f83a-4ea8-8e90-6c4c4b5cec51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298587308 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.298587308
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2124121248
Short name T109
Test name
Test status
Simulation time 146056133 ps
CPU time 1.63 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:02 PM PDT 24
Peak memory 213484 kb
Host smart-75216502-799b-469f-b4ca-73803d4ee470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124121248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2124121248
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.668695091
Short name T311
Test name
Test status
Simulation time 20599846535 ps
CPU time 32.09 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:32 PM PDT 24
Peak memory 205312 kb
Host smart-26d66ff1-7291-4055-9cc8-2a364fb4a0c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668695091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.668695091
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.102036417
Short name T384
Test name
Test status
Simulation time 1419950062 ps
CPU time 4.6 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:05 PM PDT 24
Peak memory 205164 kb
Host smart-c1d7334d-c90c-4146-b9b8-82a2040d81ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102036417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.102036417
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.717038753
Short name T313
Test name
Test status
Simulation time 149651724 ps
CPU time 0.79 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:02 PM PDT 24
Peak memory 204936 kb
Host smart-804f66f3-10bd-46c7-9096-bbc0f1ea466e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717038753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.717038753
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3085007712
Short name T429
Test name
Test status
Simulation time 1817534003 ps
CPU time 7.81 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:09 PM PDT 24
Peak memory 205280 kb
Host smart-4d8e9505-2db4-49ef-8c8d-897c6e9493b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085007712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3085007712
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4114417020
Short name T424
Test name
Test status
Simulation time 49728899882 ps
CPU time 44.97 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 222012 kb
Host smart-93a91c6e-b671-4358-8c0e-a7c7c289a65f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114417020 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.4114417020
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1378773935
Short name T415
Test name
Test status
Simulation time 359199273 ps
CPU time 3.59 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 213592 kb
Host smart-e9f4cf0a-00ee-4d77-9b08-914c6513e120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378773935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1378773935
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3002109413
Short name T462
Test name
Test status
Simulation time 529436135 ps
CPU time 9.26 seconds
Started Aug 07 04:46:59 PM PDT 24
Finished Aug 07 04:47:08 PM PDT 24
Peak memory 213484 kb
Host smart-fcc5d1f4-ac4e-42ea-bcb6-1e1179a87c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002109413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3002109413
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2180325372
Short name T381
Test name
Test status
Simulation time 171712760 ps
CPU time 4.25 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:13 PM PDT 24
Peak memory 219988 kb
Host smart-0ac07c20-60ff-4017-9d04-99118dc4b4a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180325372 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2180325372
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2712073504
Short name T428
Test name
Test status
Simulation time 228121927 ps
CPU time 2.41 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:09 PM PDT 24
Peak memory 213484 kb
Host smart-4cb1a81e-0513-45db-898b-68a22988ac8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712073504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2712073504
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1220480225
Short name T339
Test name
Test status
Simulation time 20511684563 ps
CPU time 32.26 seconds
Started Aug 07 04:47:00 PM PDT 24
Finished Aug 07 04:47:33 PM PDT 24
Peak memory 205308 kb
Host smart-26ff0f68-6815-49e9-b1f5-7ebe765bf69a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220480225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1220480225
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1950575252
Short name T306
Test name
Test status
Simulation time 3860916885 ps
CPU time 7.77 seconds
Started Aug 07 04:47:02 PM PDT 24
Finished Aug 07 04:47:10 PM PDT 24
Peak memory 205272 kb
Host smart-08f2e310-618d-48cb-bbb2-5cf85d9edcb1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950575252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
950575252
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3061885991
Short name T366
Test name
Test status
Simulation time 244716355 ps
CPU time 0.89 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:05 PM PDT 24
Peak memory 204896 kb
Host smart-abb0571c-f501-4b9f-81c5-a9bdaace455e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061885991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
061885991
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2510872873
Short name T362
Test name
Test status
Simulation time 864323175 ps
CPU time 6.5 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 205284 kb
Host smart-6fc5553a-a516-4dfd-905d-6f441abcba36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510872873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2510872873
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3313799957
Short name T382
Test name
Test status
Simulation time 59332625791 ps
CPU time 55.4 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:59 PM PDT 24
Peak memory 226300 kb
Host smart-f97607d7-e233-4e75-994f-87c66b579012
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313799957 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3313799957
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1572962607
Short name T423
Test name
Test status
Simulation time 149435818 ps
CPU time 4.57 seconds
Started Aug 07 04:47:01 PM PDT 24
Finished Aug 07 04:47:06 PM PDT 24
Peak memory 213580 kb
Host smart-fc800710-c6ee-4d63-b6a8-caf2d5e5c1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572962607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1572962607
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2215429478
Short name T165
Test name
Test status
Simulation time 5493944806 ps
CPU time 26.96 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 213604 kb
Host smart-a57c842f-5622-4fc9-88e4-3eb41fc42e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215429478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2215429478
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3794875947
Short name T395
Test name
Test status
Simulation time 516932829 ps
CPU time 4 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 218584 kb
Host smart-f9ef1ef7-9721-4cd0-a593-6a35c509bb98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794875947 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3794875947
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3478960827
Short name T374
Test name
Test status
Simulation time 69521873 ps
CPU time 1.6 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 213436 kb
Host smart-e8c8a561-40c2-4f99-a6b5-a75a565fb0a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478960827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3478960827
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3907430671
Short name T388
Test name
Test status
Simulation time 23796012525 ps
CPU time 19.21 seconds
Started Aug 07 04:47:04 PM PDT 24
Finished Aug 07 04:47:23 PM PDT 24
Peak memory 205248 kb
Host smart-21ecdf8b-4270-4eb4-8c52-107d0158dd52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907430671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3907430671
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1339269743
Short name T461
Test name
Test status
Simulation time 4097567689 ps
CPU time 4.98 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 205164 kb
Host smart-d3353f44-f2a5-4a3c-8c9e-c53eb1b90855
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339269743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
339269743
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2524891842
Short name T377
Test name
Test status
Simulation time 541295380 ps
CPU time 1.3 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:09 PM PDT 24
Peak memory 204920 kb
Host smart-c2dcc1d1-eb58-4bb5-ab86-8d5583eb8f22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524891842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
524891842
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.347390045
Short name T389
Test name
Test status
Simulation time 671201893 ps
CPU time 3.89 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:13 PM PDT 24
Peak memory 205320 kb
Host smart-0ad714ed-cc0a-421f-92ef-0d6a24f6501e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347390045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.347390045
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.193460915
Short name T168
Test name
Test status
Simulation time 66056780205 ps
CPU time 31.11 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 230068 kb
Host smart-4c380caf-4880-4367-8fd3-10f43f70165b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193460915 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.193460915
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1807869316
Short name T344
Test name
Test status
Simulation time 101777690 ps
CPU time 2 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:08 PM PDT 24
Peak memory 213640 kb
Host smart-90a63821-d00b-4c6a-99d0-b42df58efc30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807869316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1807869316
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.175418264
Short name T343
Test name
Test status
Simulation time 3042652292 ps
CPU time 10.77 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 213580 kb
Host smart-c807a92f-20a1-4439-9fa9-c47d66d9082c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175418264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.175418264
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3905831753
Short name T371
Test name
Test status
Simulation time 152132933 ps
CPU time 2.05 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:47:07 PM PDT 24
Peak memory 221684 kb
Host smart-ef707062-8b46-4808-ab25-3bc243ef8f87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905831753 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3905831753
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3127011826
Short name T97
Test name
Test status
Simulation time 142915494 ps
CPU time 1.78 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:08 PM PDT 24
Peak memory 213468 kb
Host smart-a21c3777-6893-478f-a3c4-62a08f8a9e29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127011826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3127011826
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1518258878
Short name T446
Test name
Test status
Simulation time 8969679406 ps
CPU time 3.99 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:47:09 PM PDT 24
Peak memory 205280 kb
Host smart-44421476-255d-48c4-a8d9-43f6b81110d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518258878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1518258878
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1193596144
Short name T330
Test name
Test status
Simulation time 6397398095 ps
CPU time 6.68 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 205324 kb
Host smart-7b7b4838-c7e9-4828-999a-47da439af347
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193596144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
193596144
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.740519269
Short name T439
Test name
Test status
Simulation time 138770478 ps
CPU time 1.1 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:10 PM PDT 24
Peak memory 204940 kb
Host smart-04c17d49-6d2f-4204-b740-18b7310fe821
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740519269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.740519269
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4277096837
Short name T111
Test name
Test status
Simulation time 378657785 ps
CPU time 3.75 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:10 PM PDT 24
Peak memory 205252 kb
Host smart-73f40813-45e0-4b74-bdac-2ec379f89896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277096837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4277096837
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1520069680
Short name T66
Test name
Test status
Simulation time 21477131870 ps
CPU time 64.42 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:48:10 PM PDT 24
Peak memory 221068 kb
Host smart-42bf4d8a-95e7-4dc9-a182-a06d6d900a8f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520069680 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1520069680
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.670194192
Short name T342
Test name
Test status
Simulation time 149095816 ps
CPU time 2.09 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:10 PM PDT 24
Peak memory 213572 kb
Host smart-6b3c432d-3aa1-47e2-b684-04d62013ef16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670194192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.670194192
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.715931203
Short name T164
Test name
Test status
Simulation time 1998055009 ps
CPU time 10.86 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:20 PM PDT 24
Peak memory 213508 kb
Host smart-d8de64a5-e8ee-4edc-af2e-cff0d2e3b2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715931203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.715931203
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2994743977
Short name T367
Test name
Test status
Simulation time 533014275 ps
CPU time 3.77 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 219148 kb
Host smart-5fcd5aaa-2579-4ea8-bfe5-7306f4e5d917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994743977 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2994743977
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2195482585
Short name T110
Test name
Test status
Simulation time 50215441 ps
CPU time 2.13 seconds
Started Aug 07 04:47:08 PM PDT 24
Finished Aug 07 04:47:11 PM PDT 24
Peak memory 213392 kb
Host smart-ea78f751-756f-42e5-9e20-862993d2e05d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195482585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2195482585
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3187642904
Short name T352
Test name
Test status
Simulation time 5002138206 ps
CPU time 4.78 seconds
Started Aug 07 04:47:09 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 205288 kb
Host smart-d5888d78-55dd-4e4f-9f2a-5e1f6661b5cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187642904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3187642904
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1854677102
Short name T331
Test name
Test status
Simulation time 5639914281 ps
CPU time 16.38 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:22 PM PDT 24
Peak memory 205284 kb
Host smart-3e58386f-491a-4cee-873c-c234214a409d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854677102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
854677102
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3751598861
Short name T69
Test name
Test status
Simulation time 213492728 ps
CPU time 0.8 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 204936 kb
Host smart-6ed086fa-721f-4216-a7f1-03faaabcbf77
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751598861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
751598861
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2223874152
Short name T128
Test name
Test status
Simulation time 404801251 ps
CPU time 6.77 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 205272 kb
Host smart-aa7eefba-94c2-4d7a-97c2-8995ee82bc07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223874152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2223874152
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2251063186
Short name T170
Test name
Test status
Simulation time 62364521305 ps
CPU time 57.9 seconds
Started Aug 07 04:47:05 PM PDT 24
Finished Aug 07 04:48:03 PM PDT 24
Peak memory 224492 kb
Host smart-06caf12c-af6a-45ef-9ef0-d2fe6da7d67b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251063186 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2251063186
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1142549823
Short name T445
Test name
Test status
Simulation time 350141902 ps
CPU time 6.32 seconds
Started Aug 07 04:47:06 PM PDT 24
Finished Aug 07 04:47:12 PM PDT 24
Peak memory 213600 kb
Host smart-a6627618-a48b-4417-b084-ee3f92d122e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142549823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1142549823
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2980376603
Short name T134
Test name
Test status
Simulation time 4648381467 ps
CPU time 29.95 seconds
Started Aug 07 04:47:07 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 213624 kb
Host smart-98e5c468-4e49-4f7b-9f05-760cbd07e3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980376603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2980376603
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.797658714
Short name T297
Test name
Test status
Simulation time 74709929 ps
CPU time 0.75 seconds
Started Aug 07 04:47:22 PM PDT 24
Finished Aug 07 04:47:23 PM PDT 24
Peak memory 204848 kb
Host smart-fa66cb64-d69a-4362-a197-73206e7bd1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797658714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.797658714
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.716174268
Short name T85
Test name
Test status
Simulation time 7704450989 ps
CPU time 16.03 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 213484 kb
Host smart-d14e23fc-f706-49cc-a0ab-802d6f59c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716174268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.716174268
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2421918439
Short name T238
Test name
Test status
Simulation time 8116206803 ps
CPU time 8.68 seconds
Started Aug 07 04:47:11 PM PDT 24
Finished Aug 07 04:47:20 PM PDT 24
Peak memory 213488 kb
Host smart-540bb9c4-ae9e-491f-9f44-47200db38765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421918439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2421918439
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1534109805
Short name T20
Test name
Test status
Simulation time 260100543 ps
CPU time 1.04 seconds
Started Aug 07 04:47:28 PM PDT 24
Finished Aug 07 04:47:29 PM PDT 24
Peak memory 204948 kb
Host smart-bfb7d9a2-2ab4-4c45-a114-1af018458cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534109805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1534109805
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1579385764
Short name T88
Test name
Test status
Simulation time 630911551 ps
CPU time 2.54 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 204840 kb
Host smart-7126bb36-9e70-4104-8c26-cd20ca3a5eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579385764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1579385764
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3560717182
Short name T171
Test name
Test status
Simulation time 126957466 ps
CPU time 0.74 seconds
Started Aug 07 04:47:19 PM PDT 24
Finished Aug 07 04:47:20 PM PDT 24
Peak memory 204808 kb
Host smart-e4e69fc5-7370-4ed5-bd99-b5f22d9e1385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560717182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3560717182
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2431693890
Short name T271
Test name
Test status
Simulation time 120275233 ps
CPU time 0.94 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:38 PM PDT 24
Peak memory 215332 kb
Host smart-8f428e61-d80e-40b4-9896-a4d1ecb97e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431693890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2431693890
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2077370687
Short name T211
Test name
Test status
Simulation time 4659799033 ps
CPU time 5.71 seconds
Started Aug 07 04:47:12 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 205372 kb
Host smart-28a01399-fb8f-4256-9511-37649f29d32d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077370687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2077370687
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.204888023
Short name T302
Test name
Test status
Simulation time 356338672 ps
CPU time 1.19 seconds
Started Aug 07 04:47:35 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 204840 kb
Host smart-64a427b4-62b6-4da8-ac26-ad5b05cded91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204888023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.204888023
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1757524931
Short name T210
Test name
Test status
Simulation time 338479877 ps
CPU time 1.32 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:15 PM PDT 24
Peak memory 204816 kb
Host smart-75a68194-4574-41ae-a35d-b367c6e23e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757524931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1757524931
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4214021558
Short name T243
Test name
Test status
Simulation time 182675437 ps
CPU time 0.85 seconds
Started Aug 07 04:47:13 PM PDT 24
Finished Aug 07 04:47:14 PM PDT 24
Peak memory 204804 kb
Host smart-4965a39c-5e39-4b15-be65-ec01ee575862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214021558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4214021558
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1542622071
Short name T213
Test name
Test status
Simulation time 1770767682 ps
CPU time 3.17 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:32 PM PDT 24
Peak memory 204716 kb
Host smart-d310fdaf-8c8b-4fc0-8151-4b60f5f5df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542622071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1542622071
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1191113702
Short name T217
Test name
Test status
Simulation time 311024157 ps
CPU time 0.92 seconds
Started Aug 07 04:47:16 PM PDT 24
Finished Aug 07 04:47:18 PM PDT 24
Peak memory 204844 kb
Host smart-1253d777-85cb-4a0b-898b-208d8252f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191113702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1191113702
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1163441323
Short name T206
Test name
Test status
Simulation time 176941356 ps
CPU time 1.14 seconds
Started Aug 07 04:47:15 PM PDT 24
Finished Aug 07 04:47:16 PM PDT 24
Peak memory 204808 kb
Host smart-fca1a87b-699e-41de-9aec-9ec8a25b3956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163441323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1163441323
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4076804316
Short name T34
Test name
Test status
Simulation time 99218488 ps
CPU time 0.95 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:21 PM PDT 24
Peak memory 204824 kb
Host smart-a7f40ada-c91d-4889-9f81-efb797e2fedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076804316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4076804316
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2413826113
Short name T178
Test name
Test status
Simulation time 1445231522 ps
CPU time 4.15 seconds
Started Aug 07 04:47:14 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 204856 kb
Host smart-4cadf9b0-4d5e-4238-b562-2dbe71f216cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413826113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2413826113
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3511077372
Short name T72
Test name
Test status
Simulation time 351813847 ps
CPU time 1.36 seconds
Started Aug 07 04:47:15 PM PDT 24
Finished Aug 07 04:47:17 PM PDT 24
Peak memory 213048 kb
Host smart-3e4254f3-4694-44c3-b9b9-792c585da957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511077372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3511077372
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2565392275
Short name T52
Test name
Test status
Simulation time 1090776485 ps
CPU time 2.27 seconds
Started Aug 07 04:47:32 PM PDT 24
Finished Aug 07 04:47:35 PM PDT 24
Peak memory 204848 kb
Host smart-616a3117-22bd-450e-bcb7-9aa79f9b87c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565392275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2565392275
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2395627875
Short name T11
Test name
Test status
Simulation time 2278885675 ps
CPU time 4.74 seconds
Started Aug 07 04:47:15 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 205388 kb
Host smart-9e3f10e3-2f58-478c-ba6b-3c29757cfe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395627875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2395627875
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3021535324
Short name T56
Test name
Test status
Simulation time 1029035841 ps
CPU time 3.91 seconds
Started Aug 07 04:47:22 PM PDT 24
Finished Aug 07 04:47:26 PM PDT 24
Peak memory 228900 kb
Host smart-5c629372-93d8-42f7-981b-032a2021af1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021535324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3021535324
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1242974625
Short name T293
Test name
Test status
Simulation time 981078935 ps
CPU time 1.72 seconds
Started Aug 07 04:47:17 PM PDT 24
Finished Aug 07 04:47:19 PM PDT 24
Peak memory 204844 kb
Host smart-12166514-5710-4ae3-ae1c-570aafe466e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242974625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1242974625
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2564280647
Short name T18
Test name
Test status
Simulation time 4557367114 ps
CPU time 6.85 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 213416 kb
Host smart-ab535e78-3918-4dfc-ba80-a11d2509fdc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564280647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2564280647
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2762985105
Short name T50
Test name
Test status
Simulation time 334019544993 ps
CPU time 1146.39 seconds
Started Aug 07 04:47:27 PM PDT 24
Finished Aug 07 05:06:34 PM PDT 24
Peak memory 237540 kb
Host smart-80e6652a-4b60-4177-a59a-f7dadc512c7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762985105 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2762985105
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.576019629
Short name T45
Test name
Test status
Simulation time 523151935 ps
CPU time 0.84 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 204948 kb
Host smart-f3a09a17-42df-4810-8678-fcfd5569a333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576019629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.576019629
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3979632672
Short name T225
Test name
Test status
Simulation time 135616083 ps
CPU time 0.85 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:21 PM PDT 24
Peak memory 204820 kb
Host smart-1d421d9b-7b9b-4555-9df1-200dd74390a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979632672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3979632672
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4289171080
Short name T285
Test name
Test status
Simulation time 1521887640 ps
CPU time 1.92 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:25 PM PDT 24
Peak memory 205180 kb
Host smart-825fd511-e8d6-4909-aade-ce458018dbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289171080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4289171080
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.368172913
Short name T14
Test name
Test status
Simulation time 237168305 ps
CPU time 1.11 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:26 PM PDT 24
Peak memory 204836 kb
Host smart-0301e9d8-c3a4-4f0b-847e-9fc8a5978aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368172913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.368172913
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2158220755
Short name T37
Test name
Test status
Simulation time 1128411720 ps
CPU time 3.44 seconds
Started Aug 07 04:47:30 PM PDT 24
Finished Aug 07 04:47:34 PM PDT 24
Peak memory 204848 kb
Host smart-cd86e111-afd5-4f26-b5a9-73503299c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158220755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2158220755
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.759323909
Short name T32
Test name
Test status
Simulation time 349084785 ps
CPU time 0.87 seconds
Started Aug 07 04:47:22 PM PDT 24
Finished Aug 07 04:47:23 PM PDT 24
Peak memory 204824 kb
Host smart-fd8ac7c6-c445-47f5-877c-2c780f83daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759323909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.759323909
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2972991076
Short name T91
Test name
Test status
Simulation time 265121391 ps
CPU time 1.3 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 204856 kb
Host smart-5036daf7-e65d-49b3-b912-c6ff89c1a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972991076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2972991076
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2082849599
Short name T300
Test name
Test status
Simulation time 176571211 ps
CPU time 0.94 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:25 PM PDT 24
Peak memory 215496 kb
Host smart-09a026ac-13f4-4b57-92a6-183159a6a263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082849599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2082849599
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4231791708
Short name T273
Test name
Test status
Simulation time 3791728460 ps
CPU time 11.21 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 205320 kb
Host smart-2ef6bfbb-80c0-423a-acf5-1728c8598645
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231791708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.4231791708
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3512911672
Short name T265
Test name
Test status
Simulation time 410262577 ps
CPU time 0.85 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 204836 kb
Host smart-f978b5b4-db9c-4c44-960f-b6d512ef983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512911672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3512911672
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2882107722
Short name T197
Test name
Test status
Simulation time 205558071 ps
CPU time 1.28 seconds
Started Aug 07 04:47:22 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 204808 kb
Host smart-60d28ad6-1853-4f48-99dd-78713b027354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882107722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2882107722
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.877359391
Short name T266
Test name
Test status
Simulation time 178446463 ps
CPU time 0.88 seconds
Started Aug 07 04:47:19 PM PDT 24
Finished Aug 07 04:47:20 PM PDT 24
Peak memory 204880 kb
Host smart-edd76735-d147-4127-86cd-898233fec467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877359391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.877359391
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3931963927
Short name T74
Test name
Test status
Simulation time 468465468 ps
CPU time 0.96 seconds
Started Aug 07 04:47:35 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 204700 kb
Host smart-1212f262-dfd5-4bc1-875e-2722b17184be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931963927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3931963927
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2206613947
Short name T212
Test name
Test status
Simulation time 482574709 ps
CPU time 1.49 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:22 PM PDT 24
Peak memory 204816 kb
Host smart-65a450b0-a23b-4bfb-8497-a49096c6205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206613947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2206613947
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2602568548
Short name T215
Test name
Test status
Simulation time 114739903 ps
CPU time 0.82 seconds
Started Aug 07 04:47:22 PM PDT 24
Finished Aug 07 04:47:23 PM PDT 24
Peak memory 204816 kb
Host smart-fc3f1803-7ff3-4de0-9ee3-4783c2eca7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602568548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2602568548
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1773450711
Short name T198
Test name
Test status
Simulation time 308860899 ps
CPU time 1.49 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 204836 kb
Host smart-44ea653a-823a-480f-bbb0-b33dbca88245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773450711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1773450711
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2024550537
Short name T177
Test name
Test status
Simulation time 479732897 ps
CPU time 1.28 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:21 PM PDT 24
Peak memory 204852 kb
Host smart-e49ddaa0-bc53-4c90-9735-17c71507bb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024550537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2024550537
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3399000315
Short name T28
Test name
Test status
Simulation time 298720770 ps
CPU time 1.14 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 213048 kb
Host smart-06c00252-6bd8-4547-9f5c-a69dd42bfad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399000315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3399000315
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1551072259
Short name T294
Test name
Test status
Simulation time 1040306884 ps
CPU time 1.43 seconds
Started Aug 07 04:47:22 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 204816 kb
Host smart-f45d9ab4-2627-46eb-833d-f49ca9ac50b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551072259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1551072259
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3565921584
Short name T39
Test name
Test status
Simulation time 125272800 ps
CPU time 0.89 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 04:47:35 PM PDT 24
Peak memory 213116 kb
Host smart-9633e91d-313e-48d2-a19c-c1fceabb4086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565921584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3565921584
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1685824609
Short name T140
Test name
Test status
Simulation time 4027074269 ps
CPU time 6.34 seconds
Started Aug 07 04:47:20 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 205100 kb
Host smart-b26dffe7-23d7-4b14-8f9a-2aeff1f4b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685824609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1685824609
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.286671163
Short name T77
Test name
Test status
Simulation time 2006288227 ps
CPU time 6.32 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 229344 kb
Host smart-a5b1ce48-4d53-407c-992e-33daff62a8e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286671163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.286671163
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.905668422
Short name T251
Test name
Test status
Simulation time 3494279808 ps
CPU time 3.16 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 205120 kb
Host smart-36e608d0-fd9d-4e08-8510-71b587ef5b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905668422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.905668422
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2555793614
Short name T89
Test name
Test status
Simulation time 7941915028 ps
CPU time 6.75 seconds
Started Aug 07 04:47:27 PM PDT 24
Finished Aug 07 04:47:34 PM PDT 24
Peak memory 213380 kb
Host smart-103b4b9a-c7ea-4c4d-a13f-a61ac53e0aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555793614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2555793614
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.1337611061
Short name T51
Test name
Test status
Simulation time 415838648699 ps
CPU time 1184.83 seconds
Started Aug 07 04:47:26 PM PDT 24
Finished Aug 07 05:07:11 PM PDT 24
Peak memory 241680 kb
Host smart-3a3c0617-ca16-463c-bf49-59a5423a4c97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337611061 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.1337611061
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2268175264
Short name T218
Test name
Test status
Simulation time 61180867 ps
CPU time 0.74 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 204884 kb
Host smart-c38ac4cf-caba-42cd-aa11-8c85407181b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268175264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2268175264
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3457354585
Short name T141
Test name
Test status
Simulation time 2196753977 ps
CPU time 6.37 seconds
Started Aug 07 04:47:41 PM PDT 24
Finished Aug 07 04:47:47 PM PDT 24
Peak memory 213480 kb
Host smart-a287d3f3-833e-4553-9c41-0b970b905a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457354585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3457354585
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3101421412
Short name T278
Test name
Test status
Simulation time 2088047150 ps
CPU time 3.96 seconds
Started Aug 07 04:47:51 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 205216 kb
Host smart-1acffc57-c005-4028-880c-af8320904864
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101421412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3101421412
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3604440693
Short name T220
Test name
Test status
Simulation time 6136848841 ps
CPU time 18.35 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 213804 kb
Host smart-aaa52af5-c491-4cb5-ae18-16374178c4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604440693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3604440693
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3898229856
Short name T5
Test name
Test status
Simulation time 6512105001 ps
CPU time 21.74 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:48:04 PM PDT 24
Peak memory 205244 kb
Host smart-cd4e74f0-1fd6-4197-9a3b-22a43e3c4f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898229856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3898229856
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.624275542
Short name T190
Test name
Test status
Simulation time 44875122 ps
CPU time 0.76 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 204848 kb
Host smart-34e96be3-2029-49d2-bef4-6eb0b93223f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624275542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.624275542
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.668086241
Short name T250
Test name
Test status
Simulation time 5235013303 ps
CPU time 4.35 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 213548 kb
Host smart-7223165e-2918-49d9-933e-fd8b8947a0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668086241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.668086241
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1144122246
Short name T232
Test name
Test status
Simulation time 16768793577 ps
CPU time 30.01 seconds
Started Aug 07 04:47:26 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 213592 kb
Host smart-f78adc20-0dd0-41bc-a8ed-45b6aede5993
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144122246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1144122246
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1575882920
Short name T269
Test name
Test status
Simulation time 4027681293 ps
CPU time 7.13 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:53 PM PDT 24
Peak memory 205364 kb
Host smart-e9940b28-3be5-4d66-9811-bb3b19a831be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575882920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1575882920
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2358018667
Short name T16
Test name
Test status
Simulation time 9190846122 ps
CPU time 7.56 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 213364 kb
Host smart-89da823d-5d16-467d-9e5b-2e58ddb2dca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358018667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2358018667
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1135163252
Short name T267
Test name
Test status
Simulation time 74424958 ps
CPU time 0.75 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 204820 kb
Host smart-973916ca-e41c-4f9a-b569-aa629b751909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135163252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1135163252
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3455911275
Short name T185
Test name
Test status
Simulation time 19162938385 ps
CPU time 14.59 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:48:04 PM PDT 24
Peak memory 213588 kb
Host smart-6671468a-6914-4990-899f-d28e29221473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455911275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3455911275
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1358568651
Short name T219
Test name
Test status
Simulation time 797734564 ps
CPU time 1.57 seconds
Started Aug 07 04:47:26 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 205176 kb
Host smart-0ffadc89-da8c-4116-807c-0fcd91a73b38
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358568651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1358568651
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3951466744
Short name T221
Test name
Test status
Simulation time 2738753706 ps
CPU time 8.11 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:47 PM PDT 24
Peak memory 205308 kb
Host smart-dfc70f80-b778-4681-ae45-fffc91c12d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951466744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3951466744
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3064873575
Short name T43
Test name
Test status
Simulation time 4088111104 ps
CPU time 2.32 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:47:49 PM PDT 24
Peak memory 205084 kb
Host smart-12f59ba4-e55b-45ec-9109-dcad10641849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064873575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3064873575
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.671712290
Short name T209
Test name
Test status
Simulation time 80562557 ps
CPU time 0.75 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 204852 kb
Host smart-f96461ea-2b9d-485e-b9a6-57a9f5f73523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671712290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.671712290
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.63342934
Short name T241
Test name
Test status
Simulation time 2147840697 ps
CPU time 3.67 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 205304 kb
Host smart-64eab8c6-12c1-4468-809c-bbb464447c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63342934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.63342934
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2846839556
Short name T263
Test name
Test status
Simulation time 1561465331 ps
CPU time 5.13 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 205268 kb
Host smart-c714a7f0-2570-4f42-9db3-09633b39bca2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846839556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2846839556
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.620899724
Short name T228
Test name
Test status
Simulation time 3033193936 ps
CPU time 3.69 seconds
Started Aug 07 04:47:28 PM PDT 24
Finished Aug 07 04:47:32 PM PDT 24
Peak memory 205328 kb
Host smart-1236663f-3c29-4e4c-b893-10fc00af7e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620899724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.620899724
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1288657960
Short name T144
Test name
Test status
Simulation time 5714197136 ps
CPU time 5.8 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:42 PM PDT 24
Peak memory 213356 kb
Host smart-a6a5624a-5b3c-40b8-907a-99e310060abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288657960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1288657960
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3824340503
Short name T237
Test name
Test status
Simulation time 39248387 ps
CPU time 0.7 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:38 PM PDT 24
Peak memory 204924 kb
Host smart-b4e9d716-5390-4b8a-8211-9020bede976b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824340503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3824340503
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.624589046
Short name T199
Test name
Test status
Simulation time 3586261346 ps
CPU time 11.33 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 205748 kb
Host smart-651c0196-5023-4f9a-a4b2-931a7848eb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624589046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.624589046
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2599952472
Short name T80
Test name
Test status
Simulation time 3539021556 ps
CPU time 3.43 seconds
Started Aug 07 04:47:26 PM PDT 24
Finished Aug 07 04:47:29 PM PDT 24
Peak memory 213528 kb
Host smart-d446f769-2a7d-42ce-af51-51d90a84e96e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599952472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2599952472
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1992605285
Short name T226
Test name
Test status
Simulation time 3676205032 ps
CPU time 2.99 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 213852 kb
Host smart-75fde286-11ad-43e7-8c4f-be6935e0fbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992605285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1992605285
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1087216127
Short name T48
Test name
Test status
Simulation time 2730306264 ps
CPU time 2.41 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:32 PM PDT 24
Peak memory 205276 kb
Host smart-1a02564f-8bce-4d74-ab40-c14366b273d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087216127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1087216127
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1177859173
Short name T53
Test name
Test status
Simulation time 104574629 ps
CPU time 0.76 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 204848 kb
Host smart-9fa4ff2e-072c-4d0a-a2db-46de48199b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177859173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1177859173
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3684383949
Short name T283
Test name
Test status
Simulation time 4944537920 ps
CPU time 4.11 seconds
Started Aug 07 04:47:27 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 213588 kb
Host smart-1e7591a7-a34b-428d-b4d1-6120277d235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684383949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3684383949
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1664666326
Short name T305
Test name
Test status
Simulation time 9242225570 ps
CPU time 26.16 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:48:04 PM PDT 24
Peak memory 213460 kb
Host smart-97db0511-68d2-4db8-a47a-f1d018ad049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664666326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1664666326
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3766153181
Short name T207
Test name
Test status
Simulation time 6125560087 ps
CPU time 13.54 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:42 PM PDT 24
Peak memory 213528 kb
Host smart-80d8106d-eeed-4c93-a583-30cd2caa9f5a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766153181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3766153181
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3313385574
Short name T245
Test name
Test status
Simulation time 6073818624 ps
CPU time 4.46 seconds
Started Aug 07 04:47:41 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 205612 kb
Host smart-f34afb5a-c8b7-4ee0-b483-6677de27346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313385574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3313385574
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1159440583
Short name T295
Test name
Test status
Simulation time 2520047952 ps
CPU time 4.75 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:47:51 PM PDT 24
Peak memory 213408 kb
Host smart-a7f13c69-7f30-4bce-8833-149dc4c43456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159440583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1159440583
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2964730879
Short name T216
Test name
Test status
Simulation time 56739204 ps
CPU time 0.89 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:47:48 PM PDT 24
Peak memory 204780 kb
Host smart-27bc8699-6130-4968-af4d-5ed3037bd1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964730879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2964730879
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.419942768
Short name T196
Test name
Test status
Simulation time 19201524801 ps
CPU time 16.05 seconds
Started Aug 07 04:47:50 PM PDT 24
Finished Aug 07 04:48:06 PM PDT 24
Peak memory 213500 kb
Host smart-1300077e-36b8-49d5-8b3e-94772dc2eabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419942768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.419942768
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.4219621621
Short name T304
Test name
Test status
Simulation time 4430253829 ps
CPU time 12.75 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:48:07 PM PDT 24
Peak memory 205308 kb
Host smart-8f801379-0c2f-4b1b-8c50-db521622a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219621621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.4219621621
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2518265272
Short name T255
Test name
Test status
Simulation time 3401430855 ps
CPU time 6.27 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 205332 kb
Host smart-e53c92a6-a302-4e4e-a904-79766a42d693
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518265272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2518265272
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.812726630
Short name T173
Test name
Test status
Simulation time 3867059855 ps
CPU time 10.28 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 205116 kb
Host smart-6ffa2bd6-1ec1-4235-8fce-d16f809a89e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812726630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.812726630
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3713468485
Short name T260
Test name
Test status
Simulation time 96850748 ps
CPU time 0.81 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 204816 kb
Host smart-804e1051-d87f-4a70-8b97-4f522febc0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713468485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3713468485
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2785055101
Short name T282
Test name
Test status
Simulation time 14403791957 ps
CPU time 14.55 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:48:03 PM PDT 24
Peak memory 213564 kb
Host smart-9c6389b6-9616-4a12-b6ee-ff9bf95eb1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785055101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2785055101
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1738636091
Short name T200
Test name
Test status
Simulation time 3945326102 ps
CPU time 6.48 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 213488 kb
Host smart-63a8a253-cfb6-4d2d-91b6-2832f713956f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738636091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1738636091
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3578807054
Short name T223
Test name
Test status
Simulation time 3564100827 ps
CPU time 6.08 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 205324 kb
Host smart-10410f61-04f7-43fe-a649-635a4c31b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578807054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3578807054
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1110491206
Short name T71
Test name
Test status
Simulation time 11052107214 ps
CPU time 27.61 seconds
Started Aug 07 04:47:33 PM PDT 24
Finished Aug 07 04:48:01 PM PDT 24
Peak memory 213376 kb
Host smart-ccbb6579-e995-4cd6-9853-22a9959cfe53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110491206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1110491206
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.539427999
Short name T86
Test name
Test status
Simulation time 61347325 ps
CPU time 0.82 seconds
Started Aug 07 04:47:48 PM PDT 24
Finished Aug 07 04:47:49 PM PDT 24
Peak memory 204852 kb
Host smart-2b7c19c2-bbcd-47da-8ac7-82651f531411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539427999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.539427999
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2379501426
Short name T183
Test name
Test status
Simulation time 2559317247 ps
CPU time 3.06 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:47:49 PM PDT 24
Peak memory 205316 kb
Host smart-6974fc29-b9d1-4cdf-82f0-7d3fedc033e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379501426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2379501426
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1740737171
Short name T148
Test name
Test status
Simulation time 1574769166 ps
CPU time 1.74 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 213380 kb
Host smart-f904d6a6-07ab-4d10-8f2d-a80902fcce3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740737171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1740737171
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.844574683
Short name T160
Test name
Test status
Simulation time 813525559 ps
CPU time 3.42 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:47:51 PM PDT 24
Peak memory 205188 kb
Host smart-1733f2eb-4d1c-4e60-acb5-8a641ac9fafc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844574683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.844574683
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3703941855
Short name T289
Test name
Test status
Simulation time 5082199551 ps
CPU time 3.99 seconds
Started Aug 07 04:47:57 PM PDT 24
Finished Aug 07 04:48:01 PM PDT 24
Peak memory 205612 kb
Host smart-e1f6c936-97f6-46d4-9631-1ffc75c4a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703941855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3703941855
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3670398774
Short name T12
Test name
Test status
Simulation time 3880279612 ps
CPU time 10.73 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 213356 kb
Host smart-a480d927-ca87-4fd0-b4f4-9ee1b7cbbd06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670398774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3670398774
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.146021484
Short name T298
Test name
Test status
Simulation time 166290642 ps
CPU time 0.83 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 204908 kb
Host smart-295b58b6-df96-44d7-91ba-d62733cf1659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146021484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.146021484
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1328707369
Short name T151
Test name
Test status
Simulation time 50922582863 ps
CPU time 151.24 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:50:16 PM PDT 24
Peak memory 205720 kb
Host smart-ae7d1c0c-f742-424c-8a78-d9b99c067b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328707369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1328707369
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2052870015
Short name T25
Test name
Test status
Simulation time 4016475291 ps
CPU time 6.27 seconds
Started Aug 07 04:47:51 PM PDT 24
Finished Aug 07 04:47:57 PM PDT 24
Peak memory 205284 kb
Host smart-8c737c82-3f30-4268-b501-3ba1643b7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052870015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2052870015
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1614594246
Short name T222
Test name
Test status
Simulation time 1304397995 ps
CPU time 2.13 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 205176 kb
Host smart-3c76a52d-d1b7-4f44-907c-fea55fc87e28
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614594246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1614594246
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2193051962
Short name T291
Test name
Test status
Simulation time 4622147955 ps
CPU time 7.57 seconds
Started Aug 07 04:47:43 PM PDT 24
Finished Aug 07 04:47:51 PM PDT 24
Peak memory 205244 kb
Host smart-3d2a3259-97e2-482c-8f3c-e7f731deb559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193051962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2193051962
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4057486140
Short name T145
Test name
Test status
Simulation time 10203454235 ps
CPU time 28.25 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:48:32 PM PDT 24
Peak memory 205232 kb
Host smart-d9316d97-7c1f-4531-ac75-56a183cbe432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057486140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4057486140
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.4138422694
Short name T230
Test name
Test status
Simulation time 56938091 ps
CPU time 0.77 seconds
Started Aug 07 04:47:41 PM PDT 24
Finished Aug 07 04:47:42 PM PDT 24
Peak memory 204856 kb
Host smart-26ce404f-e1cc-4e21-a30e-d35279a8940f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138422694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4138422694
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.836289733
Short name T205
Test name
Test status
Simulation time 4409635756 ps
CPU time 11.95 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 205316 kb
Host smart-f5b4ccc1-38d8-4326-ab64-0709180cfd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836289733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.836289733
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3966272229
Short name T191
Test name
Test status
Simulation time 1696729948 ps
CPU time 5.2 seconds
Started Aug 07 04:47:19 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 213404 kb
Host smart-771e5802-6a55-4a56-9495-116b6f577d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966272229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3966272229
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3191317108
Short name T214
Test name
Test status
Simulation time 15199363861 ps
CPU time 23.62 seconds
Started Aug 07 04:47:21 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 213516 kb
Host smart-93a1eb48-8306-4661-8d73-e8354bebabbb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191317108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3191317108
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.2393673265
Short name T240
Test name
Test status
Simulation time 1085565473 ps
CPU time 3.85 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 204824 kb
Host smart-4c80817a-0018-4a9a-b14e-e165f840db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393673265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2393673265
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2620122956
Short name T184
Test name
Test status
Simulation time 278668115 ps
CPU time 1.42 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 204836 kb
Host smart-183ef62e-92f9-4652-aeb4-09a56c7e744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620122956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2620122956
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3289184180
Short name T292
Test name
Test status
Simulation time 2361177818 ps
CPU time 4.09 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 04:47:38 PM PDT 24
Peak memory 205296 kb
Host smart-41892602-1265-4a6c-8b31-f9275b338ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289184180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3289184180
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3221675655
Short name T175
Test name
Test status
Simulation time 9606769070 ps
CPU time 4.34 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 213388 kb
Host smart-f1b81319-672d-46e3-8a02-5984239ff49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221675655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3221675655
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3887086928
Short name T44
Test name
Test status
Simulation time 37831241962 ps
CPU time 535.45 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:56:33 PM PDT 24
Peak memory 232108 kb
Host smart-550b48bd-57d7-43f8-bee9-e4ea886a32c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887086928 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3887086928
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3330407834
Short name T233
Test name
Test status
Simulation time 52449158 ps
CPU time 0.77 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 204848 kb
Host smart-1edfc780-1e7d-4ab9-a23a-8090aeb1a75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330407834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3330407834
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.934864877
Short name T176
Test name
Test status
Simulation time 2910226748 ps
CPU time 4.61 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 205204 kb
Host smart-8f772f50-ece3-4367-a4a7-e89ff9e3e416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934864877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.934864877
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1510095751
Short name T303
Test name
Test status
Simulation time 57431033 ps
CPU time 0.74 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:47:43 PM PDT 24
Peak memory 204940 kb
Host smart-381540f2-95fc-4e66-b25a-e4caa060f5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510095751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1510095751
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1493797785
Short name T21
Test name
Test status
Simulation time 7138801667 ps
CPU time 10.59 seconds
Started Aug 07 04:47:53 PM PDT 24
Finished Aug 07 04:48:04 PM PDT 24
Peak memory 205212 kb
Host smart-d87ab0c4-aa24-4921-8de8-f742f40cebde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493797785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1493797785
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3108955638
Short name T234
Test name
Test status
Simulation time 65229033 ps
CPU time 0.72 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:47:43 PM PDT 24
Peak memory 204852 kb
Host smart-299b7d6f-ff49-4d71-9d47-86a465581767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108955638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3108955638
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1581817410
Short name T158
Test name
Test status
Simulation time 13272190047 ps
CPU time 5.96 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 213340 kb
Host smart-6f62a765-cd89-4116-9cbd-c295bcd358e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581817410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1581817410
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.61801390
Short name T181
Test name
Test status
Simulation time 40078045 ps
CPU time 0.79 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:37 PM PDT 24
Peak memory 204852 kb
Host smart-424a42da-f19d-46d0-9017-ba0e087bcf81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61801390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.61801390
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.357124112
Short name T242
Test name
Test status
Simulation time 6891498673 ps
CPU time 11.27 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:47:53 PM PDT 24
Peak memory 213340 kb
Host smart-51ad0523-143b-4853-90a0-9a064bb8bb48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357124112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.357124112
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1369704248
Short name T54
Test name
Test status
Simulation time 155938865 ps
CPU time 0.91 seconds
Started Aug 07 04:47:48 PM PDT 24
Finished Aug 07 04:47:49 PM PDT 24
Peak memory 204884 kb
Host smart-10519e51-0a32-4ee2-8a67-a6804b8ce1fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369704248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1369704248
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2541144931
Short name T33
Test name
Test status
Simulation time 8791000315 ps
CPU time 12.05 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:47:59 PM PDT 24
Peak memory 213560 kb
Host smart-ebdf2421-cd2e-4179-b61f-4e4df855b2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541144931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2541144931
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3307941459
Short name T280
Test name
Test status
Simulation time 52334912 ps
CPU time 0.8 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 204828 kb
Host smart-4a7bf514-8b65-41af-a8ae-4c06cb74819a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307941459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3307941459
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2689251247
Short name T286
Test name
Test status
Simulation time 1302180044 ps
CPU time 4.58 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:49 PM PDT 24
Peak memory 213200 kb
Host smart-70054d75-ce8c-420a-8670-d09e84daf7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689251247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2689251247
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.4187519097
Short name T281
Test name
Test status
Simulation time 61134118 ps
CPU time 0.93 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 204836 kb
Host smart-59cf594c-cceb-4725-b778-1cc8db54ffe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187519097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.4187519097
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1022829036
Short name T146
Test name
Test status
Simulation time 5638656774 ps
CPU time 16.5 seconds
Started Aug 07 04:47:52 PM PDT 24
Finished Aug 07 04:48:08 PM PDT 24
Peak memory 205140 kb
Host smart-d6b4bd02-2664-4539-9d32-b294ccfd0aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022829036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1022829036
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1356912163
Short name T90
Test name
Test status
Simulation time 94102667 ps
CPU time 0.82 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 204872 kb
Host smart-c9aec82d-a1ea-4381-9cd4-f38f1cf5c49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356912163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1356912163
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1995537737
Short name T235
Test name
Test status
Simulation time 67820882 ps
CPU time 0.73 seconds
Started Aug 07 04:47:50 PM PDT 24
Finished Aug 07 04:47:51 PM PDT 24
Peak memory 204824 kb
Host smart-691d55e6-9417-4379-9d30-eea3e4b37d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995537737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1995537737
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3331269901
Short name T4
Test name
Test status
Simulation time 5158505020 ps
CPU time 7.14 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:47:53 PM PDT 24
Peak memory 205172 kb
Host smart-45718c1d-78eb-42cd-b7e4-a7f91b694240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331269901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3331269901
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1245397798
Short name T246
Test name
Test status
Simulation time 168978727 ps
CPU time 0.78 seconds
Started Aug 07 04:48:06 PM PDT 24
Finished Aug 07 04:48:07 PM PDT 24
Peak memory 204804 kb
Host smart-79b7ed2b-3b44-4763-b350-b7ee3f0190bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245397798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1245397798
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.410598624
Short name T258
Test name
Test status
Simulation time 3600155136 ps
CPU time 5.84 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 213320 kb
Host smart-7bdf466f-899e-4da0-90be-2752f6d1f595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410598624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.410598624
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1906467785
Short name T274
Test name
Test status
Simulation time 179471935 ps
CPU time 0.78 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:24 PM PDT 24
Peak memory 204880 kb
Host smart-add51a0c-2a18-4858-af07-54cf65741d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906467785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1906467785
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.4144501313
Short name T150
Test name
Test status
Simulation time 1040437172 ps
CPU time 1.99 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 213572 kb
Host smart-38b715dd-37a1-495e-8568-a2b9a5957d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144501313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.4144501313
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.57622261
Short name T87
Test name
Test status
Simulation time 3132535413 ps
CPU time 10.36 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:54 PM PDT 24
Peak memory 213640 kb
Host smart-fbfd7140-5907-4855-9ada-b868df0bbb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57622261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.57622261
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2609077182
Short name T59
Test name
Test status
Simulation time 740175513 ps
CPU time 2.99 seconds
Started Aug 07 04:47:28 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 205268 kb
Host smart-915bce16-f382-4755-bc71-c994c261c2c2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609077182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2609077182
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.2928324061
Short name T47
Test name
Test status
Simulation time 315091251 ps
CPU time 1.01 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 04:47:35 PM PDT 24
Peak memory 204848 kb
Host smart-d1139f08-d294-422d-ada3-3f0ef244bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928324061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2928324061
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3238776813
Short name T136
Test name
Test status
Simulation time 177122025 ps
CPU time 0.88 seconds
Started Aug 07 04:47:34 PM PDT 24
Finished Aug 07 04:47:35 PM PDT 24
Peak memory 204836 kb
Host smart-defc0cfe-75d9-4f25-b177-8ddecb15f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238776813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3238776813
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3988058235
Short name T142
Test name
Test status
Simulation time 1601384854 ps
CPU time 1.62 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:39 PM PDT 24
Peak memory 205096 kb
Host smart-bfd5c084-0f3d-4487-a073-281429869bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988058235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3988058235
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2096510216
Short name T57
Test name
Test status
Simulation time 411277796 ps
CPU time 2.17 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:38 PM PDT 24
Peak memory 229544 kb
Host smart-76406694-aa8a-40d7-b23b-0842900d0f8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096510216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2096510216
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1209200405
Short name T137
Test name
Test status
Simulation time 8680292888 ps
CPU time 11.93 seconds
Started Aug 07 04:47:33 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 205208 kb
Host smart-225dba99-4ad3-4cdc-857e-5ad8b9206064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209200405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1209200405
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3212630242
Short name T201
Test name
Test status
Simulation time 69901756 ps
CPU time 0.72 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:46 PM PDT 24
Peak memory 204832 kb
Host smart-d3277a36-bcc8-4ae5-826d-64cbb09404bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212630242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3212630242
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3480297851
Short name T270
Test name
Test status
Simulation time 3011618163 ps
CPU time 2.37 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:48:02 PM PDT 24
Peak memory 205188 kb
Host smart-c9db4a1c-ea5e-48c7-b6cc-cb695607dcd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480297851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3480297851
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.846813263
Short name T288
Test name
Test status
Simulation time 219573702 ps
CPU time 0.78 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:47:48 PM PDT 24
Peak memory 204848 kb
Host smart-7ff03787-9d2a-4b78-a8f4-ed30e4a736ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846813263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.846813263
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1932032043
Short name T279
Test name
Test status
Simulation time 1149952482 ps
CPU time 4.02 seconds
Started Aug 07 04:48:04 PM PDT 24
Finished Aug 07 04:48:08 PM PDT 24
Peak memory 213044 kb
Host smart-bf227db4-722a-4cd6-838e-312c4f322339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932032043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1932032043
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3752867241
Short name T187
Test name
Test status
Simulation time 135093382 ps
CPU time 1.03 seconds
Started Aug 07 04:47:50 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 204828 kb
Host smart-559fee4b-28ee-4311-b9dd-8fbcecf7379c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752867241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3752867241
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.4262758456
Short name T284
Test name
Test status
Simulation time 6578626713 ps
CPU time 9.93 seconds
Started Aug 07 04:47:59 PM PDT 24
Finished Aug 07 04:48:09 PM PDT 24
Peak memory 213420 kb
Host smart-6f02aef7-5583-4089-bd0a-1aa8bd9e1533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262758456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.4262758456
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2012436397
Short name T192
Test name
Test status
Simulation time 114401605 ps
CPU time 0.75 seconds
Started Aug 07 04:47:50 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 204848 kb
Host smart-4b9a3056-2689-44a9-8163-ee5ece4db2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012436397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2012436397
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3716329806
Short name T257
Test name
Test status
Simulation time 2700314478 ps
CPU time 2.76 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 213320 kb
Host smart-00124899-ef74-4ef4-acdb-40a0494d8a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716329806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3716329806
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1214250617
Short name T248
Test name
Test status
Simulation time 31411162 ps
CPU time 0.84 seconds
Started Aug 07 04:47:53 PM PDT 24
Finished Aug 07 04:47:54 PM PDT 24
Peak memory 204916 kb
Host smart-e01ecb36-63ff-4fa7-ac5e-4d5cc3ceb8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214250617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1214250617
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.4045936889
Short name T247
Test name
Test status
Simulation time 7977040808 ps
CPU time 11.29 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:48:06 PM PDT 24
Peak memory 205152 kb
Host smart-4705fdc5-d909-4224-a4be-00ef3cad6f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045936889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.4045936889
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4096196194
Short name T195
Test name
Test status
Simulation time 155379970 ps
CPU time 0.72 seconds
Started Aug 07 04:47:50 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 204864 kb
Host smart-d0ac7bde-f92f-47f0-b4c0-e5dd783c74d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096196194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4096196194
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2308383825
Short name T154
Test name
Test status
Simulation time 3732224302 ps
CPU time 10.39 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:47:59 PM PDT 24
Peak memory 205104 kb
Host smart-fde31b0e-2d4b-4204-850f-67a6073fbd14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308383825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2308383825
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1877665598
Short name T73
Test name
Test status
Simulation time 58224451 ps
CPU time 0.76 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 204836 kb
Host smart-ac0e324a-7d8e-4caf-a974-a72021a6d770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877665598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1877665598
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2135859964
Short name T174
Test name
Test status
Simulation time 2697897468 ps
CPU time 8.33 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 213408 kb
Host smart-764678f2-68ce-4b0f-9357-31eee0e7afdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135859964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2135859964
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.683444399
Short name T252
Test name
Test status
Simulation time 37652101 ps
CPU time 0.75 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 204844 kb
Host smart-88d37cf4-37bb-4ecb-ad6b-982449523e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683444399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.683444399
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.4294148937
Short name T6
Test name
Test status
Simulation time 5424009357 ps
CPU time 16.78 seconds
Started Aug 07 04:47:52 PM PDT 24
Finished Aug 07 04:48:09 PM PDT 24
Peak memory 213456 kb
Host smart-769cae01-ea08-439b-8ab2-1a0a1488f05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294148937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4294148937
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.974296181
Short name T290
Test name
Test status
Simulation time 77498941 ps
CPU time 0.74 seconds
Started Aug 07 04:47:52 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 204764 kb
Host smart-a7832e00-6c60-4095-b4f2-a000634efceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974296181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.974296181
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.225755035
Short name T161
Test name
Test status
Simulation time 5035973083 ps
CPU time 7.12 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:51 PM PDT 24
Peak memory 205228 kb
Host smart-a3aa3900-742d-4f06-a3d7-3a168e91e81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225755035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.225755035
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4244224776
Short name T182
Test name
Test status
Simulation time 238351504 ps
CPU time 0.71 seconds
Started Aug 07 04:47:56 PM PDT 24
Finished Aug 07 04:47:57 PM PDT 24
Peak memory 204928 kb
Host smart-d0b51e6b-443e-4360-8455-56864bc335b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244224776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4244224776
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1067128583
Short name T23
Test name
Test status
Simulation time 3410578740 ps
CPU time 3.52 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:47:57 PM PDT 24
Peak memory 205192 kb
Host smart-e628fee8-5d3f-4ec2-80b9-4243a39dd1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067128583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1067128583
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.4009456276
Short name T193
Test name
Test status
Simulation time 207258954 ps
CPU time 0.78 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:25 PM PDT 24
Peak memory 204860 kb
Host smart-2dbfea9a-b94b-4143-bca6-7c9fb37f64f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009456276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.4009456276
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1069600016
Short name T277
Test name
Test status
Simulation time 2067615052 ps
CPU time 2.26 seconds
Started Aug 07 04:47:28 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 213416 kb
Host smart-d4d6c4f2-bf2c-4cb4-9711-78e85eb27fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069600016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1069600016
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1629020996
Short name T259
Test name
Test status
Simulation time 5494245942 ps
CPU time 16.85 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 213484 kb
Host smart-e058eb38-abf0-4853-8046-c84b9577f310
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1629020996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1629020996
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3299118581
Short name T253
Test name
Test status
Simulation time 284440925 ps
CPU time 1.07 seconds
Started Aug 07 04:47:35 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 204852 kb
Host smart-1f8d0032-37d9-446b-be7d-05b37892da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299118581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3299118581
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3870835657
Short name T149
Test name
Test status
Simulation time 1091621273 ps
CPU time 2.91 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 204636 kb
Host smart-ed7e0108-c395-4f85-9c73-76f5abb800ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870835657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3870835657
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1320905123
Short name T227
Test name
Test status
Simulation time 3652291304 ps
CPU time 4.4 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:47:43 PM PDT 24
Peak memory 205388 kb
Host smart-c81dcc8c-34be-45d6-b74d-8783326fb55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320905123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1320905123
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3166141923
Short name T76
Test name
Test status
Simulation time 746364744 ps
CPU time 1.62 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:26 PM PDT 24
Peak memory 229288 kb
Host smart-2c6630e2-3bfc-4a35-89a4-03329cd2bf81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166141923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3166141923
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1391777507
Short name T138
Test name
Test status
Simulation time 93570151 ps
CPU time 0.74 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:47:50 PM PDT 24
Peak memory 204824 kb
Host smart-ae668528-9ecb-49a3-90a5-02807a5f3b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391777507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1391777507
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3469101805
Short name T17
Test name
Test status
Simulation time 5379001850 ps
CPU time 6.36 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:48:01 PM PDT 24
Peak memory 205088 kb
Host smart-289dd295-7f62-4b0f-aba2-48e3d0707369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469101805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3469101805
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1735571421
Short name T179
Test name
Test status
Simulation time 66794729 ps
CPU time 0.83 seconds
Started Aug 07 04:47:57 PM PDT 24
Finished Aug 07 04:47:58 PM PDT 24
Peak memory 204768 kb
Host smart-55300053-8a60-4e8a-936b-d2bf38c46d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735571421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1735571421
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3266141648
Short name T172
Test name
Test status
Simulation time 1972450657 ps
CPU time 3.91 seconds
Started Aug 07 04:47:53 PM PDT 24
Finished Aug 07 04:47:57 PM PDT 24
Peak memory 213272 kb
Host smart-3d73ba81-286f-4a2d-b77a-745d0fb9e42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266141648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3266141648
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4243935983
Short name T264
Test name
Test status
Simulation time 94650766 ps
CPU time 0.88 seconds
Started Aug 07 04:47:53 PM PDT 24
Finished Aug 07 04:47:54 PM PDT 24
Peak memory 204864 kb
Host smart-a486a511-00fd-49d5-8984-76ac8f0ea4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243935983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4243935983
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1236678474
Short name T296
Test name
Test status
Simulation time 3369965569 ps
CPU time 4.55 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:48:00 PM PDT 24
Peak memory 205132 kb
Host smart-48ba5e90-f3ae-498e-b403-98f335b9ed17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236678474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1236678474
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.844322629
Short name T231
Test name
Test status
Simulation time 45729655 ps
CPU time 0.71 seconds
Started Aug 07 04:47:51 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 204840 kb
Host smart-bbff2aae-1d31-4a4a-9e42-b5ada1fcf398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844322629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.844322629
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2069468386
Short name T131
Test name
Test status
Simulation time 109865623 ps
CPU time 0.71 seconds
Started Aug 07 04:47:44 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 204844 kb
Host smart-6124627d-db4e-4478-9feb-f1435bb63382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069468386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2069468386
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2796380621
Short name T19
Test name
Test status
Simulation time 11020935721 ps
CPU time 7.76 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:48:02 PM PDT 24
Peak memory 205240 kb
Host smart-314f35ee-52e7-4d9f-9eca-5b4851a9f016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796380621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2796380621
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2784966147
Short name T203
Test name
Test status
Simulation time 129013869 ps
CPU time 1.01 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 204880 kb
Host smart-b68d7951-e94c-4b13-a30e-bec69591e074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784966147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2784966147
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1394436038
Short name T58
Test name
Test status
Simulation time 7143858509 ps
CPU time 9.98 seconds
Started Aug 07 04:48:18 PM PDT 24
Finished Aug 07 04:48:28 PM PDT 24
Peak memory 213400 kb
Host smart-2de3ae95-1709-48e0-864a-5f47840a45c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394436038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1394436038
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2517565612
Short name T208
Test name
Test status
Simulation time 47194786 ps
CPU time 0.72 seconds
Started Aug 07 04:47:57 PM PDT 24
Finished Aug 07 04:47:58 PM PDT 24
Peak memory 204836 kb
Host smart-65e713ed-7c0b-4d80-87ad-58c44aa7d509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517565612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2517565612
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3057604319
Short name T13
Test name
Test status
Simulation time 1613893225 ps
CPU time 2.85 seconds
Started Aug 07 04:47:54 PM PDT 24
Finished Aug 07 04:47:57 PM PDT 24
Peak memory 213396 kb
Host smart-5148c872-d3cc-4e60-bb63-7747ca90760f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057604319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3057604319
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3484014103
Short name T236
Test name
Test status
Simulation time 77578647 ps
CPU time 0.91 seconds
Started Aug 07 04:47:50 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 204844 kb
Host smart-8130a79c-f226-47bf-accd-e5b6940fce74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484014103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3484014103
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2970325375
Short name T186
Test name
Test status
Simulation time 55258383 ps
CPU time 0.83 seconds
Started Aug 07 04:47:55 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 204816 kb
Host smart-aab535ba-5022-4d12-8864-8547aac4d5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970325375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2970325375
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2671710323
Short name T143
Test name
Test status
Simulation time 3838082135 ps
CPU time 4.83 seconds
Started Aug 07 04:47:51 PM PDT 24
Finished Aug 07 04:47:56 PM PDT 24
Peak memory 213360 kb
Host smart-e58bffe9-1008-47ca-b2d1-eeb889f34fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671710323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2671710323
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4281239803
Short name T244
Test name
Test status
Simulation time 65510851 ps
CPU time 0.83 seconds
Started Aug 07 04:47:57 PM PDT 24
Finished Aug 07 04:47:58 PM PDT 24
Peak memory 204840 kb
Host smart-1d9700a7-6bd7-44c4-9066-84a94606e79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281239803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4281239803
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.4246907263
Short name T156
Test name
Test status
Simulation time 4679427428 ps
CPU time 9.92 seconds
Started Aug 07 04:47:52 PM PDT 24
Finished Aug 07 04:48:03 PM PDT 24
Peak memory 205156 kb
Host smart-09435ba5-c1c2-4c92-97fd-9ab33550a604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246907263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.4246907263
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1163168602
Short name T194
Test name
Test status
Simulation time 41210417 ps
CPU time 0.8 seconds
Started Aug 07 04:47:35 PM PDT 24
Finished Aug 07 04:47:36 PM PDT 24
Peak memory 204856 kb
Host smart-4e6ed86b-5505-4a50-853a-57c4785ad5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163168602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1163168602
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2158899903
Short name T254
Test name
Test status
Simulation time 29532416251 ps
CPU time 58.52 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:48:35 PM PDT 24
Peak memory 213520 kb
Host smart-cd3e9e43-4b88-4270-b1c8-371c097a3607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158899903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2158899903
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3190011235
Short name T10
Test name
Test status
Simulation time 8873192254 ps
CPU time 19.43 seconds
Started Aug 07 04:47:21 PM PDT 24
Finished Aug 07 04:47:40 PM PDT 24
Peak memory 205272 kb
Host smart-f048ffef-b80c-4efe-9da3-6a1777c81ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190011235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3190011235
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.193328911
Short name T276
Test name
Test status
Simulation time 1021204099 ps
CPU time 2.39 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 205284 kb
Host smart-c7d5144d-6c8e-41b2-a008-a57a52932274
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193328911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.193328911
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3205108334
Short name T249
Test name
Test status
Simulation time 542587936 ps
CPU time 1.38 seconds
Started Aug 07 04:47:21 PM PDT 24
Finished Aug 07 04:47:23 PM PDT 24
Peak memory 204808 kb
Host smart-47eaf55c-505e-4ad6-a291-f5c25b5bf92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205108334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3205108334
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.4292253061
Short name T60
Test name
Test status
Simulation time 9226112165 ps
CPU time 17.14 seconds
Started Aug 07 04:47:36 PM PDT 24
Finished Aug 07 04:47:53 PM PDT 24
Peak memory 213496 kb
Host smart-0d4ff0e2-4c36-468c-8bff-7a0054f49589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292253061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4292253061
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2017011819
Short name T40
Test name
Test status
Simulation time 3511329578 ps
CPU time 10.83 seconds
Started Aug 07 04:47:37 PM PDT 24
Finished Aug 07 04:47:48 PM PDT 24
Peak memory 213448 kb
Host smart-6481bd84-573c-4487-8286-a880d9d1fd62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017011819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2017011819
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1947867753
Short name T229
Test name
Test status
Simulation time 47519327 ps
CPU time 0.79 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:47:43 PM PDT 24
Peak memory 204816 kb
Host smart-2b739789-70cb-4a70-abd2-3f5636ca9da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947867753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1947867753
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.692774445
Short name T31
Test name
Test status
Simulation time 6823219100 ps
CPU time 20.16 seconds
Started Aug 07 04:47:46 PM PDT 24
Finished Aug 07 04:48:06 PM PDT 24
Peak memory 213604 kb
Host smart-ac60ade6-0e14-4ea0-82ef-6b03d244ab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692774445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.692774445
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1917941539
Short name T204
Test name
Test status
Simulation time 19700789720 ps
CPU time 50.62 seconds
Started Aug 07 04:47:26 PM PDT 24
Finished Aug 07 04:48:17 PM PDT 24
Peak memory 213504 kb
Host smart-aba75148-1cd5-414f-b256-b363138278b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917941539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1917941539
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1017081118
Short name T272
Test name
Test status
Simulation time 3861948019 ps
CPU time 4.36 seconds
Started Aug 07 04:47:23 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 213604 kb
Host smart-52fd037c-8161-4aba-9d8b-5c8a7d82b569
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017081118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1017081118
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3638113797
Short name T2
Test name
Test status
Simulation time 1307390209 ps
CPU time 4.41 seconds
Started Aug 07 04:47:40 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 204808 kb
Host smart-e8909a26-c70b-477e-8ba4-9d678b239a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638113797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3638113797
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1998127855
Short name T189
Test name
Test status
Simulation time 4318920523 ps
CPU time 7.46 seconds
Started Aug 07 04:47:24 PM PDT 24
Finished Aug 07 04:47:32 PM PDT 24
Peak memory 205312 kb
Host smart-eeae7a12-8f1a-4862-8521-3c7cfa0e6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998127855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1998127855
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.458158000
Short name T22
Test name
Test status
Simulation time 5219511909 ps
CPU time 3.48 seconds
Started Aug 07 04:47:48 PM PDT 24
Finished Aug 07 04:47:52 PM PDT 24
Peak memory 213352 kb
Host smart-67f8ae84-8b41-47e0-99b0-56dad416a7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458158000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.458158000
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.2685228930
Short name T8
Test name
Test status
Simulation time 62712840454 ps
CPU time 1417.22 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 05:11:03 PM PDT 24
Peak memory 239632 kb
Host smart-56401fab-5402-4486-8bd2-365abddad20e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685228930 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.2685228930
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3579195377
Short name T180
Test name
Test status
Simulation time 75585896 ps
CPU time 0.75 seconds
Started Aug 07 04:47:30 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 204844 kb
Host smart-5828d3c7-da10-44dc-835b-24a80aa091a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579195377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3579195377
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3899795165
Short name T299
Test name
Test status
Simulation time 86674916498 ps
CPU time 251.14 seconds
Started Aug 07 04:47:38 PM PDT 24
Finished Aug 07 04:51:50 PM PDT 24
Peak memory 215716 kb
Host smart-d91dea27-d9da-48fc-b617-87553eec53bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899795165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3899795165
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.4004587004
Short name T63
Test name
Test status
Simulation time 1944550644 ps
CPU time 5.47 seconds
Started Aug 07 04:47:49 PM PDT 24
Finished Aug 07 04:47:55 PM PDT 24
Peak memory 213476 kb
Host smart-39dc01df-8026-41c7-860a-8e964b2438ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004587004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.4004587004
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2470875802
Short name T301
Test name
Test status
Simulation time 739143498 ps
CPU time 1.86 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 205240 kb
Host smart-91d651dd-b51a-4e2b-b834-aabc38164b3e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470875802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2470875802
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.2379348729
Short name T268
Test name
Test status
Simulation time 297119019 ps
CPU time 1.18 seconds
Started Aug 07 04:47:28 PM PDT 24
Finished Aug 07 04:47:30 PM PDT 24
Peak memory 204820 kb
Host smart-38a03eed-21c3-422f-9e47-acc9f74d156d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379348729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2379348729
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.4014851956
Short name T9
Test name
Test status
Simulation time 1400925075 ps
CPU time 2.21 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:27 PM PDT 24
Peak memory 205140 kb
Host smart-5d8d9796-af95-4761-94bb-0c5bd545f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014851956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4014851956
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3335411994
Short name T275
Test name
Test status
Simulation time 8887924557 ps
CPU time 5.75 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 213320 kb
Host smart-98ae07e6-f56e-444e-bdb4-1141fa8eee82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335411994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3335411994
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2889596070
Short name T202
Test name
Test status
Simulation time 2149868602 ps
CPU time 1.97 seconds
Started Aug 07 04:47:33 PM PDT 24
Finished Aug 07 04:47:35 PM PDT 24
Peak memory 213512 kb
Host smart-ac4bf5e3-41f3-432e-8108-de6a44d05649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889596070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2889596070
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1368688331
Short name T67
Test name
Test status
Simulation time 2451852721 ps
CPU time 5.63 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:51 PM PDT 24
Peak memory 213600 kb
Host smart-841b8892-e265-4187-a2bb-2a09a51893af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368688331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1368688331
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.729734478
Short name T256
Test name
Test status
Simulation time 1903761578 ps
CPU time 2.76 seconds
Started Aug 07 04:47:42 PM PDT 24
Finished Aug 07 04:47:45 PM PDT 24
Peak memory 213448 kb
Host smart-a08759e7-5052-4e47-9c3f-a54edba418cc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729734478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.729734478
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2526381829
Short name T261
Test name
Test status
Simulation time 2857679287 ps
CPU time 3.32 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:32 PM PDT 24
Peak memory 213524 kb
Host smart-69ccf6fe-95ae-4f67-ae79-c1883b74fb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526381829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2526381829
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.4059349666
Short name T155
Test name
Test status
Simulation time 2519428834 ps
CPU time 1.86 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 205220 kb
Host smart-7c750459-f2c6-41e6-891c-ab2bed558f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059349666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.4059349666
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.4055973359
Short name T224
Test name
Test status
Simulation time 66057149 ps
CPU time 0.91 seconds
Started Aug 07 04:47:47 PM PDT 24
Finished Aug 07 04:47:48 PM PDT 24
Peak memory 204880 kb
Host smart-01c2dea6-73ca-449b-bea9-7d0d3784da9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055973359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4055973359
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.4280877386
Short name T79
Test name
Test status
Simulation time 1405093933 ps
CPU time 2.86 seconds
Started Aug 07 04:47:25 PM PDT 24
Finished Aug 07 04:47:28 PM PDT 24
Peak memory 205156 kb
Host smart-110fbaeb-438f-4c26-a951-d5cac60e5134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280877386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.4280877386
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1407651521
Short name T287
Test name
Test status
Simulation time 4199275649 ps
CPU time 2.11 seconds
Started Aug 07 04:47:45 PM PDT 24
Finished Aug 07 04:47:47 PM PDT 24
Peak memory 213564 kb
Host smart-9ee5b4e9-56e6-4691-9bba-d280ac902c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407651521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1407651521
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3996976326
Short name T239
Test name
Test status
Simulation time 1076293108 ps
CPU time 1.84 seconds
Started Aug 07 04:47:39 PM PDT 24
Finished Aug 07 04:47:41 PM PDT 24
Peak memory 205292 kb
Host smart-c0efd3b7-e0e4-421c-84ae-a67950ea4f1e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996976326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3996976326
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2115011551
Short name T153
Test name
Test status
Simulation time 2387268971 ps
CPU time 6.83 seconds
Started Aug 07 04:47:27 PM PDT 24
Finished Aug 07 04:47:34 PM PDT 24
Peak memory 205360 kb
Host smart-c7c90bfe-225c-40e7-a1c7-9cd128107cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115011551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2115011551
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1081889996
Short name T41
Test name
Test status
Simulation time 2262793625 ps
CPU time 2.05 seconds
Started Aug 07 04:47:29 PM PDT 24
Finished Aug 07 04:47:31 PM PDT 24
Peak memory 205192 kb
Host smart-a00ff92d-9896-44b3-b4be-bf3f6b6cf907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081889996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1081889996
Directory /workspace/9.rv_dm_stress_all/latest
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