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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
84.94 96.32 87.41 92.10 73.75 90.44 98.42 56.10


Total test records in report: 465
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T309 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3556055449 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:55 PM PDT 24 3571527586 ps
T79 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2212284112 Aug 08 05:17:48 PM PDT 24 Aug 08 05:17:50 PM PDT 24 94333165 ps
T80 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.584504275 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:49 PM PDT 24 321781519 ps
T77 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4193080263 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:29 PM PDT 24 407745242 ps
T78 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2391614508 Aug 08 05:17:35 PM PDT 24 Aug 08 05:17:40 PM PDT 24 570483699 ps
T81 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1566526849 Aug 08 05:17:52 PM PDT 24 Aug 08 05:17:55 PM PDT 24 207186264 ps
T310 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.154980161 Aug 08 05:17:25 PM PDT 24 Aug 08 05:25:28 PM PDT 24 212015139239 ps
T82 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.797970509 Aug 08 05:17:36 PM PDT 24 Aug 08 05:18:09 PM PDT 24 4107211480 ps
T54 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3514872893 Aug 08 05:17:25 PM PDT 24 Aug 08 05:22:51 PM PDT 24 53678752691 ps
T83 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4015707345 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:44 PM PDT 24 167208187 ps
T311 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2396274541 Aug 08 05:17:30 PM PDT 24 Aug 08 05:17:35 PM PDT 24 5538736102 ps
T57 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1522072840 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:27 PM PDT 24 539732402 ps
T84 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1686115188 Aug 08 05:17:54 PM PDT 24 Aug 08 05:17:56 PM PDT 24 481949121 ps
T119 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3208316642 Aug 08 05:17:44 PM PDT 24 Aug 08 05:18:04 PM PDT 24 4901095636 ps
T85 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3814743203 Aug 08 05:17:42 PM PDT 24 Aug 08 05:17:47 PM PDT 24 908914980 ps
T120 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4181367186 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:39 PM PDT 24 284539213 ps
T124 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3049950236 Aug 08 05:17:50 PM PDT 24 Aug 08 05:18:15 PM PDT 24 4214522876 ps
T312 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1080301137 Aug 08 05:17:42 PM PDT 24 Aug 08 05:19:51 PM PDT 24 48071244889 ps
T121 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1207489530 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:48 PM PDT 24 499258278 ps
T122 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3583110710 Aug 08 05:17:23 PM PDT 24 Aug 08 05:17:44 PM PDT 24 2238239467 ps
T313 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3515669318 Aug 08 05:17:36 PM PDT 24 Aug 08 05:17:41 PM PDT 24 424844694 ps
T314 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2972130089 Aug 08 05:17:48 PM PDT 24 Aug 08 05:18:08 PM PDT 24 12783219579 ps
T86 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.261577344 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:49 PM PDT 24 167464042 ps
T315 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.253682785 Aug 08 05:17:11 PM PDT 24 Aug 08 05:18:39 PM PDT 24 86931099668 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1685261587 Aug 08 05:17:50 PM PDT 24 Aug 08 05:17:59 PM PDT 24 5148539690 ps
T317 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2128065001 Aug 08 05:17:48 PM PDT 24 Aug 08 05:18:49 PM PDT 24 20809396622 ps
T123 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2447478903 Aug 08 05:17:48 PM PDT 24 Aug 08 05:18:07 PM PDT 24 2400644639 ps
T318 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4019360352 Aug 08 05:17:24 PM PDT 24 Aug 08 05:18:11 PM PDT 24 15449252809 ps
T58 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2453753489 Aug 08 05:17:39 PM PDT 24 Aug 08 05:17:40 PM PDT 24 170170259 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2346877945 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:28 PM PDT 24 1079785626 ps
T87 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2147903537 Aug 08 05:17:35 PM PDT 24 Aug 08 05:17:39 PM PDT 24 244868463 ps
T88 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3346549664 Aug 08 05:17:51 PM PDT 24 Aug 08 05:17:58 PM PDT 24 291675212 ps
T320 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1923246095 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:47 PM PDT 24 474988058 ps
T321 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1308905960 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:47 PM PDT 24 517377000 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4288462127 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:46 PM PDT 24 252102016 ps
T55 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1493662862 Aug 08 05:17:40 PM PDT 24 Aug 08 05:18:07 PM PDT 24 7099648358 ps
T95 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.731764186 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:44 PM PDT 24 111334375 ps
T96 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.408585299 Aug 08 05:17:49 PM PDT 24 Aug 08 05:17:58 PM PDT 24 2113436561 ps
T323 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2967691848 Aug 08 05:17:38 PM PDT 24 Aug 08 05:17:39 PM PDT 24 46277800 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2228500557 Aug 08 05:17:14 PM PDT 24 Aug 08 05:17:15 PM PDT 24 187640732 ps
T325 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1081623253 Aug 08 05:17:45 PM PDT 24 Aug 08 05:18:16 PM PDT 24 21703342136 ps
T173 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3512839632 Aug 08 05:17:45 PM PDT 24 Aug 08 05:18:42 PM PDT 24 60340417089 ps
T326 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2197745158 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:42 PM PDT 24 357941663 ps
T110 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2058588044 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:50 PM PDT 24 1047887531 ps
T327 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1644650400 Aug 08 05:17:43 PM PDT 24 Aug 08 05:17:58 PM PDT 24 2721916556 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1177165186 Aug 08 05:17:15 PM PDT 24 Aug 08 05:17:25 PM PDT 24 5325328583 ps
T329 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.914060547 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:49 PM PDT 24 1116548362 ps
T163 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2036969639 Aug 08 05:17:49 PM PDT 24 Aug 08 05:18:02 PM PDT 24 3392149383 ps
T330 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2375787910 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:49 PM PDT 24 265786156 ps
T111 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3084991379 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:51 PM PDT 24 459002095 ps
T331 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.914200146 Aug 08 05:17:35 PM PDT 24 Aug 08 05:18:06 PM PDT 24 12280528372 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.322265109 Aug 08 05:17:15 PM PDT 24 Aug 08 05:17:16 PM PDT 24 312918813 ps
T333 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3880130736 Aug 08 05:17:43 PM PDT 24 Aug 08 05:17:44 PM PDT 24 92259457 ps
T170 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4165834760 Aug 08 05:17:57 PM PDT 24 Aug 08 05:18:19 PM PDT 24 4422248643 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.224186400 Aug 08 05:17:34 PM PDT 24 Aug 08 05:17:35 PM PDT 24 478991137 ps
T335 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3478362766 Aug 08 05:17:43 PM PDT 24 Aug 08 05:17:46 PM PDT 24 2494009973 ps
T174 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2028887735 Aug 08 05:17:33 PM PDT 24 Aug 08 05:18:33 PM PDT 24 49959440166 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2222025181 Aug 08 05:17:27 PM PDT 24 Aug 08 05:18:11 PM PDT 24 15757700286 ps
T336 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1073597057 Aug 08 05:17:49 PM PDT 24 Aug 08 05:17:53 PM PDT 24 1165219339 ps
T172 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2416291304 Aug 08 05:18:00 PM PDT 24 Aug 08 05:18:10 PM PDT 24 913023386 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4195876896 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:36 PM PDT 24 292165368 ps
T338 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3745855193 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:37 PM PDT 24 208035969 ps
T339 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1815537927 Aug 08 05:17:46 PM PDT 24 Aug 08 05:18:52 PM PDT 24 29804408729 ps
T340 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.58782656 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:46 PM PDT 24 342738254 ps
T341 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2477767342 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:58 PM PDT 24 1818999875 ps
T342 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2121770209 Aug 08 05:17:53 PM PDT 24 Aug 08 05:18:17 PM PDT 24 7956913295 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.738307442 Aug 08 05:17:40 PM PDT 24 Aug 08 05:17:45 PM PDT 24 2427710476 ps
T175 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.577222971 Aug 08 05:17:24 PM PDT 24 Aug 08 05:18:13 PM PDT 24 50710262268 ps
T97 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3176912742 Aug 08 05:17:48 PM PDT 24 Aug 08 05:17:56 PM PDT 24 2227677281 ps
T344 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2132233508 Aug 08 05:17:51 PM PDT 24 Aug 08 05:17:54 PM PDT 24 203925724 ps
T168 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.53055675 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:53 PM PDT 24 3411246865 ps
T345 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.853191942 Aug 08 05:17:40 PM PDT 24 Aug 08 05:18:07 PM PDT 24 1489999607 ps
T346 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2275867067 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:49 PM PDT 24 5085937988 ps
T347 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4156087527 Aug 08 05:17:35 PM PDT 24 Aug 08 05:20:18 PM PDT 24 50313243244 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.164995651 Aug 08 05:17:43 PM PDT 24 Aug 08 05:17:45 PM PDT 24 72103727 ps
T349 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3141937789 Aug 08 05:17:38 PM PDT 24 Aug 08 05:19:09 PM PDT 24 46166002015 ps
T104 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.196477154 Aug 08 05:17:52 PM PDT 24 Aug 08 05:17:54 PM PDT 24 160337509 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.4190957014 Aug 08 05:17:12 PM PDT 24 Aug 08 05:17:12 PM PDT 24 65114881 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3173758159 Aug 08 05:17:32 PM PDT 24 Aug 08 05:17:37 PM PDT 24 512440237 ps
T105 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1507358094 Aug 08 05:17:36 PM PDT 24 Aug 08 05:17:39 PM PDT 24 973817023 ps
T352 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2353794228 Aug 08 05:17:37 PM PDT 24 Aug 08 05:17:39 PM PDT 24 2614324532 ps
T353 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2151430688 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:50 PM PDT 24 13084160286 ps
T106 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1955645565 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:43 PM PDT 24 127307704 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.273298488 Aug 08 05:17:31 PM PDT 24 Aug 08 05:17:32 PM PDT 24 229964822 ps
T355 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1492050498 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:52 PM PDT 24 405076428 ps
T356 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2987152808 Aug 08 05:17:40 PM PDT 24 Aug 08 05:17:42 PM PDT 24 226099338 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1528202722 Aug 08 05:17:11 PM PDT 24 Aug 08 05:17:58 PM PDT 24 21369765040 ps
T107 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2492164401 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:48 PM PDT 24 657535764 ps
T358 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2165240795 Aug 08 05:17:51 PM PDT 24 Aug 08 05:17:56 PM PDT 24 1614098999 ps
T359 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1887931651 Aug 08 05:17:40 PM PDT 24 Aug 08 05:17:45 PM PDT 24 272026945 ps
T360 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3646384858 Aug 08 05:17:13 PM PDT 24 Aug 08 05:17:14 PM PDT 24 138534063 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2383594661 Aug 08 05:17:47 PM PDT 24 Aug 08 05:18:05 PM PDT 24 1488959460 ps
T362 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.518158509 Aug 08 05:17:15 PM PDT 24 Aug 08 05:18:54 PM PDT 24 33624245487 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2517334060 Aug 08 05:17:27 PM PDT 24 Aug 08 05:17:29 PM PDT 24 588134126 ps
T364 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1413266260 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:48 PM PDT 24 4774398565 ps
T365 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.994013723 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:50 PM PDT 24 3775263728 ps
T366 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4084569779 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:50 PM PDT 24 98949879 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3493629107 Aug 08 05:17:39 PM PDT 24 Aug 08 05:17:42 PM PDT 24 172988428 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2475866913 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:27 PM PDT 24 164413996 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4189460154 Aug 08 05:17:42 PM PDT 24 Aug 08 05:17:56 PM PDT 24 2389366654 ps
T369 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2455477530 Aug 08 05:17:40 PM PDT 24 Aug 08 05:18:01 PM PDT 24 33831301791 ps
T370 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3706160605 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:47 PM PDT 24 845852586 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.8475808 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:26 PM PDT 24 117000540 ps
T169 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.14912732 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:47 PM PDT 24 4701047941 ps
T372 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3521090402 Aug 08 05:17:32 PM PDT 24 Aug 08 05:17:35 PM PDT 24 360301076 ps
T373 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2661792478 Aug 08 05:17:35 PM PDT 24 Aug 08 05:17:40 PM PDT 24 380740486 ps
T374 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1650700799 Aug 08 05:17:51 PM PDT 24 Aug 08 05:17:53 PM PDT 24 391551766 ps
T91 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2786900164 Aug 08 05:17:24 PM PDT 24 Aug 08 05:17:28 PM PDT 24 4201646929 ps
T375 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3099128028 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:49 PM PDT 24 838142223 ps
T376 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1911283397 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:52 PM PDT 24 714907948 ps
T377 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3668697430 Aug 08 05:17:42 PM PDT 24 Aug 08 05:17:43 PM PDT 24 164269079 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1392458162 Aug 08 05:17:24 PM PDT 24 Aug 08 05:17:24 PM PDT 24 48165430 ps
T379 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1577964981 Aug 08 05:17:23 PM PDT 24 Aug 08 05:17:24 PM PDT 24 236255264 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4209010657 Aug 08 05:17:31 PM PDT 24 Aug 08 05:17:36 PM PDT 24 1307701866 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3845405608 Aug 08 05:17:23 PM PDT 24 Aug 08 05:17:26 PM PDT 24 4376600861 ps
T382 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4138799871 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:28 PM PDT 24 2945504699 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.708694658 Aug 08 05:17:36 PM PDT 24 Aug 08 05:17:44 PM PDT 24 5613543756 ps
T98 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3865627683 Aug 08 05:17:23 PM PDT 24 Aug 08 05:17:56 PM PDT 24 5167709170 ps
T384 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2267726433 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:50 PM PDT 24 6414360477 ps
T99 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2978061724 Aug 08 05:17:34 PM PDT 24 Aug 08 05:17:40 PM PDT 24 191715294 ps
T385 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.530961537 Aug 08 05:17:48 PM PDT 24 Aug 08 05:17:50 PM PDT 24 182471916 ps
T386 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2028848326 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:28 PM PDT 24 803688651 ps
T112 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4005197195 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:54 PM PDT 24 872287595 ps
T387 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.844251510 Aug 08 05:17:55 PM PDT 24 Aug 08 05:17:58 PM PDT 24 2469340411 ps
T100 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2312188624 Aug 08 05:17:15 PM PDT 24 Aug 08 05:17:48 PM PDT 24 3376779572 ps
T388 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2050829687 Aug 08 05:17:41 PM PDT 24 Aug 08 05:18:11 PM PDT 24 20564106980 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1116870196 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:35 PM PDT 24 161594427 ps
T389 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1506340732 Aug 08 05:17:24 PM PDT 24 Aug 08 05:17:30 PM PDT 24 5292226971 ps
T390 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1261611146 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:50 PM PDT 24 262687625 ps
T391 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.961902183 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:50 PM PDT 24 20138395874 ps
T392 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2585170543 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:47 PM PDT 24 416457739 ps
T393 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3880635759 Aug 08 05:17:46 PM PDT 24 Aug 08 05:18:01 PM PDT 24 5046485857 ps
T394 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1845665535 Aug 08 05:17:27 PM PDT 24 Aug 08 05:17:32 PM PDT 24 383938130 ps
T395 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.254192203 Aug 08 05:17:55 PM PDT 24 Aug 08 05:18:02 PM PDT 24 224584914 ps
T396 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1898973899 Aug 08 05:17:42 PM PDT 24 Aug 08 05:17:43 PM PDT 24 137013129 ps
T397 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1818815397 Aug 08 05:17:15 PM PDT 24 Aug 08 05:17:19 PM PDT 24 1176662892 ps
T398 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1516868068 Aug 08 05:17:35 PM PDT 24 Aug 08 05:17:36 PM PDT 24 159093696 ps
T399 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1761390613 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:49 PM PDT 24 512009937 ps
T165 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3053542403 Aug 08 05:17:42 PM PDT 24 Aug 08 05:18:02 PM PDT 24 1529594990 ps
T400 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2649059751 Aug 08 05:17:55 PM PDT 24 Aug 08 05:18:00 PM PDT 24 648260186 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.144675962 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:37 PM PDT 24 535142961 ps
T401 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3771165474 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:49 PM PDT 24 152199450 ps
T402 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1119256976 Aug 08 05:17:53 PM PDT 24 Aug 08 05:17:56 PM PDT 24 109859698 ps
T403 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1198278959 Aug 08 05:17:40 PM PDT 24 Aug 08 05:17:41 PM PDT 24 627543746 ps
T404 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2249706214 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:42 PM PDT 24 139569390 ps
T405 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1753815347 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:47 PM PDT 24 100305671 ps
T406 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.996369413 Aug 08 05:17:52 PM PDT 24 Aug 08 05:17:57 PM PDT 24 652714518 ps
T407 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1732755970 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:28 PM PDT 24 392633611 ps
T408 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1251561611 Aug 08 05:17:23 PM PDT 24 Aug 08 05:17:51 PM PDT 24 8829795780 ps
T409 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2789412040 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:54 PM PDT 24 646348168 ps
T410 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.920995366 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:49 PM PDT 24 59134222 ps
T411 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3861251388 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:33 PM PDT 24 323658756 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2648748831 Aug 08 05:17:32 PM PDT 24 Aug 08 05:17:50 PM PDT 24 12057038230 ps
T166 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2190654661 Aug 08 05:17:11 PM PDT 24 Aug 08 05:17:24 PM PDT 24 5657070601 ps
T109 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.631655363 Aug 08 05:17:48 PM PDT 24 Aug 08 05:17:50 PM PDT 24 169382771 ps
T413 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4044154517 Aug 08 05:17:27 PM PDT 24 Aug 08 05:17:29 PM PDT 24 163358578 ps
T414 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.288606092 Aug 08 05:17:42 PM PDT 24 Aug 08 05:17:47 PM PDT 24 398464029 ps
T415 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3615185597 Aug 08 05:17:46 PM PDT 24 Aug 08 05:17:48 PM PDT 24 397055877 ps
T416 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2268015860 Aug 08 05:17:42 PM PDT 24 Aug 08 05:18:16 PM PDT 24 37149973355 ps
T417 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.732743079 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:47 PM PDT 24 294115390 ps
T418 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1307012651 Aug 08 05:17:37 PM PDT 24 Aug 08 05:17:50 PM PDT 24 9977797801 ps
T419 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3733120561 Aug 08 05:17:40 PM PDT 24 Aug 08 05:17:41 PM PDT 24 133936307 ps
T420 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1377041161 Aug 08 05:17:26 PM PDT 24 Aug 08 05:18:33 PM PDT 24 4940991952 ps
T164 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.781272121 Aug 08 05:17:36 PM PDT 24 Aug 08 05:17:45 PM PDT 24 5139802022 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2655458753 Aug 08 05:17:35 PM PDT 24 Aug 08 05:17:45 PM PDT 24 1400898347 ps
T422 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.559301715 Aug 08 05:17:41 PM PDT 24 Aug 08 05:18:18 PM PDT 24 13238291925 ps
T423 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3577246947 Aug 08 05:17:53 PM PDT 24 Aug 08 05:17:54 PM PDT 24 274555464 ps
T92 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.852914582 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:42 PM PDT 24 9672536527 ps
T424 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3387962779 Aug 08 05:17:40 PM PDT 24 Aug 08 05:18:07 PM PDT 24 3556933813 ps
T425 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3196107182 Aug 08 05:17:53 PM PDT 24 Aug 08 05:18:20 PM PDT 24 10758455549 ps
T426 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.487355211 Aug 08 05:17:51 PM PDT 24 Aug 08 05:17:58 PM PDT 24 3447612842 ps
T427 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2544794450 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:29 PM PDT 24 585309349 ps
T171 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1122054579 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:55 PM PDT 24 1877270453 ps
T428 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1911866811 Aug 08 05:17:26 PM PDT 24 Aug 08 05:17:27 PM PDT 24 158286032 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1888452531 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:59 PM PDT 24 2408257408 ps
T103 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2272720674 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:48 PM PDT 24 878122401 ps
T430 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1155666654 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:48 PM PDT 24 633167422 ps
T93 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.946264134 Aug 08 05:17:10 PM PDT 24 Aug 08 05:17:13 PM PDT 24 2052774540 ps
T431 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2302810577 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:49 PM PDT 24 691723470 ps
T432 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.990922603 Aug 08 05:17:46 PM PDT 24 Aug 08 05:18:22 PM PDT 24 18049543566 ps
T433 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2407100692 Aug 08 05:17:53 PM PDT 24 Aug 08 05:17:55 PM PDT 24 494705882 ps
T434 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1437415803 Aug 08 05:17:47 PM PDT 24 Aug 08 05:18:52 PM PDT 24 45743463062 ps
T435 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.840330059 Aug 08 05:17:23 PM PDT 24 Aug 08 05:17:27 PM PDT 24 3883116768 ps
T436 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1173676136 Aug 08 05:17:43 PM PDT 24 Aug 08 05:17:46 PM PDT 24 305479036 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3845921077 Aug 08 05:17:11 PM PDT 24 Aug 08 05:17:14 PM PDT 24 939751254 ps
T438 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.4025023112 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:46 PM PDT 24 410241882 ps
T439 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.499308443 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:49 PM PDT 24 712995768 ps
T440 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2077849300 Aug 08 05:17:32 PM PDT 24 Aug 08 05:17:33 PM PDT 24 100298272 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.891740784 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:40 PM PDT 24 4477342197 ps
T441 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3299763461 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:48 PM PDT 24 601253093 ps
T442 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1736179162 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:43 PM PDT 24 151866220 ps
T443 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4267053476 Aug 08 05:17:44 PM PDT 24 Aug 08 05:17:46 PM PDT 24 174722716 ps
T444 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3071076764 Aug 08 05:17:56 PM PDT 24 Aug 08 05:17:59 PM PDT 24 670131937 ps
T445 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1287175256 Aug 08 05:17:39 PM PDT 24 Aug 08 05:17:40 PM PDT 24 767839215 ps
T446 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1893706067 Aug 08 05:17:48 PM PDT 24 Aug 08 05:17:49 PM PDT 24 1193660418 ps
T447 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3384317570 Aug 08 05:17:30 PM PDT 24 Aug 08 05:17:31 PM PDT 24 111876197 ps
T448 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.623686699 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:36 PM PDT 24 646632173 ps
T449 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3553784709 Aug 08 05:17:48 PM PDT 24 Aug 08 05:17:53 PM PDT 24 233134301 ps
T450 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1290869039 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:48 PM PDT 24 409299656 ps
T451 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1211475878 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:42 PM PDT 24 277567208 ps
T452 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.636692253 Aug 08 05:17:34 PM PDT 24 Aug 08 05:18:01 PM PDT 24 1208629370 ps
T453 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4279693415 Aug 08 05:17:24 PM PDT 24 Aug 08 05:17:26 PM PDT 24 162397392 ps
T454 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1363576523 Aug 08 05:17:34 PM PDT 24 Aug 08 05:17:37 PM PDT 24 393907681 ps
T455 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2315820745 Aug 08 05:17:45 PM PDT 24 Aug 08 05:17:48 PM PDT 24 339283734 ps
T456 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3145957855 Aug 08 05:17:47 PM PDT 24 Aug 08 05:17:52 PM PDT 24 310691846 ps
T457 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3445372152 Aug 08 05:17:42 PM PDT 24 Aug 08 05:17:45 PM PDT 24 4604954177 ps
T458 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2159544550 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:43 PM PDT 24 3222813007 ps
T459 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2011010625 Aug 08 05:17:23 PM PDT 24 Aug 08 05:18:03 PM PDT 24 15882354033 ps
T460 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3656898437 Aug 08 05:17:41 PM PDT 24 Aug 08 05:17:47 PM PDT 24 1750716483 ps
T167 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.609373211 Aug 08 05:17:44 PM PDT 24 Aug 08 05:18:02 PM PDT 24 3602773982 ps
T461 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1478123167 Aug 08 05:17:52 PM PDT 24 Aug 08 05:18:00 PM PDT 24 912490763 ps
T462 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1416606039 Aug 08 05:17:33 PM PDT 24 Aug 08 05:17:35 PM PDT 24 42790117 ps
T463 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3642600722 Aug 08 05:17:23 PM PDT 24 Aug 08 05:18:49 PM PDT 24 48861432362 ps
T464 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.517120746 Aug 08 05:17:52 PM PDT 24 Aug 08 05:17:55 PM PDT 24 1510623805 ps
T465 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.773432805 Aug 08 05:17:25 PM PDT 24 Aug 08 05:17:30 PM PDT 24 282989313 ps

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.4131497511
Short name T4
Test name
Test status
Simulation time 79874455971 ps
CPU time 563.16 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:33:08 PM PDT 24
Peak memory 228752 kb
Host smart-91ad3409-329c-4988-b6df-9c0090e60c43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131497511 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.4131497511
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1408758858
Short name T21
Test name
Test status
Simulation time 2829097846 ps
CPU time 4.28 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:49 PM PDT 24
Peak memory 213648 kb
Host smart-a87afe9b-86a2-4161-8a1c-3a3b96c9a8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408758858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1408758858
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.2268007836
Short name T5
Test name
Test status
Simulation time 582029839530 ps
CPU time 2166.93 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 06:00:01 PM PDT 24
Peak memory 255492 kb
Host smart-2f94893d-cccb-4976-b363-be0e4a0d4b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268007836 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.2268007836
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3208316642
Short name T119
Test name
Test status
Simulation time 4901095636 ps
CPU time 19.75 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:18:04 PM PDT 24
Peak memory 213708 kb
Host smart-04efd9c9-9a82-4c05-b095-2851ab722cde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208316642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
208316642
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3512839632
Short name T173
Test name
Test status
Simulation time 60340417089 ps
CPU time 56.41 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:18:42 PM PDT 24
Peak memory 230140 kb
Host smart-a29d702e-ec2c-4122-95af-dea5ab223091
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512839632 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3512839632
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2169843649
Short name T49
Test name
Test status
Simulation time 137685816 ps
CPU time 0.81 seconds
Started Aug 08 05:23:03 PM PDT 24
Finished Aug 08 05:23:04 PM PDT 24
Peak memory 204840 kb
Host smart-3753122f-9698-40e1-b181-86a2bba42f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169843649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2169843649
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1324156874
Short name T47
Test name
Test status
Simulation time 60115785 ps
CPU time 0.84 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:02 PM PDT 24
Peak memory 204972 kb
Host smart-3a4cf71d-b03c-4233-bfde-109ac34af979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324156874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1324156874
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3321365314
Short name T7
Test name
Test status
Simulation time 2143356513 ps
CPU time 2.47 seconds
Started Aug 08 05:23:13 PM PDT 24
Finished Aug 08 05:23:16 PM PDT 24
Peak memory 205136 kb
Host smart-7b1430de-daa8-4564-bab5-5517959644b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321365314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3321365314
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2399292624
Short name T61
Test name
Test status
Simulation time 2453905466 ps
CPU time 7.85 seconds
Started Aug 08 05:23:44 PM PDT 24
Finished Aug 08 05:23:52 PM PDT 24
Peak memory 205452 kb
Host smart-bea0a2cb-578e-49ad-9eca-2fb9341d13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399292624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2399292624
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2219108486
Short name T50
Test name
Test status
Simulation time 133968805 ps
CPU time 1.02 seconds
Started Aug 08 05:23:23 PM PDT 24
Finished Aug 08 05:23:24 PM PDT 24
Peak memory 204920 kb
Host smart-fa8d411d-cc4f-431e-b30f-0485cd2d31a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219108486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2219108486
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.671972959
Short name T40
Test name
Test status
Simulation time 2446030252 ps
CPU time 2.64 seconds
Started Aug 08 05:23:31 PM PDT 24
Finished Aug 08 05:23:34 PM PDT 24
Peak memory 229856 kb
Host smart-5e9bf96e-c103-4ade-a00f-371d2eb19902
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671972959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.671972959
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1679043501
Short name T6
Test name
Test status
Simulation time 3398009519 ps
CPU time 3.49 seconds
Started Aug 08 05:23:31 PM PDT 24
Finished Aug 08 05:23:35 PM PDT 24
Peak memory 213484 kb
Host smart-62d2ca5c-ec3e-416a-a781-ff3f58bddfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679043501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1679043501
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2212284112
Short name T79
Test name
Test status
Simulation time 94333165 ps
CPU time 2.22 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 213532 kb
Host smart-33497a4a-404a-4605-8cb3-d9b580bcbae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212284112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2212284112
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3724927349
Short name T143
Test name
Test status
Simulation time 23563736412 ps
CPU time 36.65 seconds
Started Aug 08 05:23:31 PM PDT 24
Finished Aug 08 05:24:08 PM PDT 24
Peak memory 213528 kb
Host smart-ab396729-647f-4c3f-8124-6b11c22fa4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724927349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3724927349
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3920612718
Short name T15
Test name
Test status
Simulation time 345654809 ps
CPU time 1.21 seconds
Started Aug 08 05:23:21 PM PDT 24
Finished Aug 08 05:23:22 PM PDT 24
Peak memory 205152 kb
Host smart-d2f0d547-8a58-4fef-885b-300ddfbd162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920612718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3920612718
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3053542403
Short name T165
Test name
Test status
Simulation time 1529594990 ps
CPU time 20.13 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:18:02 PM PDT 24
Peak memory 213584 kb
Host smart-9db8f734-1e28-4716-8291-5442b6d79ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053542403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3053542403
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2312188624
Short name T100
Test name
Test status
Simulation time 3376779572 ps
CPU time 32.51 seconds
Started Aug 08 05:17:15 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 205468 kb
Host smart-2f8e366d-79c5-467b-9d5c-79022ad050df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312188624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2312188624
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3583110710
Short name T122
Test name
Test status
Simulation time 2238239467 ps
CPU time 21.54 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:17:44 PM PDT 24
Peak memory 221884 kb
Host smart-1a533708-bb5b-4b1c-bf50-4d65b69c16b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583110710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3583110710
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3126694945
Short name T32
Test name
Test status
Simulation time 153782084 ps
CPU time 0.91 seconds
Started Aug 08 05:23:04 PM PDT 24
Finished Aug 08 05:23:05 PM PDT 24
Peak memory 213168 kb
Host smart-113d5b24-b207-40dd-a5ef-9c8081ea6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126694945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3126694945
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1824328186
Short name T130
Test name
Test status
Simulation time 49664931220 ps
CPU time 45.41 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:46 PM PDT 24
Peak memory 213624 kb
Host smart-10c1b83f-1f97-485f-91db-eefb2dfe8337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824328186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1824328186
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3973556519
Short name T36
Test name
Test status
Simulation time 4213626744 ps
CPU time 2.16 seconds
Started Aug 08 05:24:34 PM PDT 24
Finished Aug 08 05:24:36 PM PDT 24
Peak memory 213472 kb
Host smart-2e61e63d-1c2a-4d3e-8fd5-b9a9be0a6c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973556519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3973556519
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2981888935
Short name T294
Test name
Test status
Simulation time 1633500345 ps
CPU time 4.6 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:24:00 PM PDT 24
Peak memory 205044 kb
Host smart-29528cfd-baa3-4e7b-84f6-79a01f992a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981888935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2981888935
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.492844090
Short name T23
Test name
Test status
Simulation time 91015204 ps
CPU time 0.78 seconds
Started Aug 08 05:23:09 PM PDT 24
Finished Aug 08 05:23:10 PM PDT 24
Peak memory 204876 kb
Host smart-dd788621-e2e2-46d9-b222-e53e2bc48ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492844090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.492844090
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.14912732
Short name T169
Test name
Test status
Simulation time 4701047941 ps
CPU time 21.29 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 213784 kb
Host smart-9122ff45-ff8f-48b5-ba07-b1997755ee9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14912732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.14912732
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2667978135
Short name T43
Test name
Test status
Simulation time 2875614647 ps
CPU time 1.66 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:14 PM PDT 24
Peak memory 205308 kb
Host smart-d0ea1541-1afc-43cb-8c03-bd9a5bef7907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667978135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2667978135
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1177165186
Short name T328
Test name
Test status
Simulation time 5325328583 ps
CPU time 9.79 seconds
Started Aug 08 05:17:15 PM PDT 24
Finished Aug 08 05:17:25 PM PDT 24
Peak memory 205356 kb
Host smart-a850c4b5-9be5-4bb1-803d-e1ed6f7a89da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177165186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1177165186
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3436079591
Short name T38
Test name
Test status
Simulation time 559908575 ps
CPU time 2.11 seconds
Started Aug 08 05:23:03 PM PDT 24
Finished Aug 08 05:23:05 PM PDT 24
Peak memory 204860 kb
Host smart-cd92b8f5-a0bf-43f6-8a76-e7616d1c83b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436079591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3436079591
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.946264134
Short name T93
Test name
Test status
Simulation time 2052774540 ps
CPU time 2.89 seconds
Started Aug 08 05:17:10 PM PDT 24
Finished Aug 08 05:17:13 PM PDT 24
Peak memory 205276 kb
Host smart-f89b3c54-39e5-4c1c-a23e-d888a55a1605
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946264134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.946264134
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.584504275
Short name T80
Test name
Test status
Simulation time 321781519 ps
CPU time 3.77 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 205400 kb
Host smart-a9df96c4-db8c-4cd8-890b-601818e8d01d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584504275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.584504275
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1405257674
Short name T24
Test name
Test status
Simulation time 3546449378 ps
CPU time 3.48 seconds
Started Aug 08 05:24:34 PM PDT 24
Finished Aug 08 05:24:38 PM PDT 24
Peak memory 213404 kb
Host smart-cf264dd8-7dd1-4d9b-aa56-02dbf0534ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405257674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1405257674
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3308832228
Short name T30
Test name
Test status
Simulation time 958781578 ps
CPU time 1.08 seconds
Started Aug 08 05:23:05 PM PDT 24
Finished Aug 08 05:23:06 PM PDT 24
Peak memory 204900 kb
Host smart-9ae5fa1c-ec9c-4ec7-8e66-57581be2d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308832228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3308832228
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2447478903
Short name T123
Test name
Test status
Simulation time 2400644639 ps
CPU time 18.81 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:18:07 PM PDT 24
Peak memory 213604 kb
Host smart-418c9a87-0c25-44d8-9d61-25fa91272fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447478903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
447478903
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2770725369
Short name T11
Test name
Test status
Simulation time 5525819931 ps
CPU time 5.91 seconds
Started Aug 08 05:23:03 PM PDT 24
Finished Aug 08 05:23:09 PM PDT 24
Peak memory 213504 kb
Host smart-e1b5b6eb-aebb-4e79-8d1c-30c20bf717db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770725369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2770725369
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.612317796
Short name T257
Test name
Test status
Simulation time 2578120433 ps
CPU time 2.65 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:25 PM PDT 24
Peak memory 213856 kb
Host smart-ca71a132-ece9-4be3-a262-d8bdde087424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612317796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.612317796
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3164790460
Short name T159
Test name
Test status
Simulation time 100676590 ps
CPU time 0.98 seconds
Started Aug 08 05:23:13 PM PDT 24
Finished Aug 08 05:23:14 PM PDT 24
Peak memory 204960 kb
Host smart-d61a8cc5-22ae-4dff-a944-9c5ced101659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164790460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3164790460
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.859375774
Short name T141
Test name
Test status
Simulation time 1457993338 ps
CPU time 2.12 seconds
Started Aug 08 05:23:13 PM PDT 24
Finished Aug 08 05:23:16 PM PDT 24
Peak memory 205224 kb
Host smart-149c0a77-f0d5-4733-91c3-e9a954931f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859375774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.859375774
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1427604426
Short name T149
Test name
Test status
Simulation time 4411683550 ps
CPU time 7.82 seconds
Started Aug 08 05:24:12 PM PDT 24
Finished Aug 08 05:24:20 PM PDT 24
Peak memory 213404 kb
Host smart-080dbeec-17ef-4f6b-b6bb-b55f4f41f362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427604426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1427604426
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3610455606
Short name T131
Test name
Test status
Simulation time 8419857639 ps
CPU time 5.69 seconds
Started Aug 08 05:24:16 PM PDT 24
Finished Aug 08 05:24:22 PM PDT 24
Peak memory 213400 kb
Host smart-dd641394-3f03-4cf7-a074-f129a5e4207f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610455606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3610455606
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3018645061
Short name T161
Test name
Test status
Simulation time 5741565057 ps
CPU time 5.52 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:37 PM PDT 24
Peak memory 213348 kb
Host smart-5fc6bad8-0963-4935-8a51-ade0bfbb9fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018645061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3018645061
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3892126593
Short name T290
Test name
Test status
Simulation time 2256889855 ps
CPU time 5.92 seconds
Started Aug 08 05:22:56 PM PDT 24
Finished Aug 08 05:23:02 PM PDT 24
Peak memory 213612 kb
Host smart-5af1e00e-cd12-4699-9989-750f98e61792
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892126593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3892126593
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2137740090
Short name T264
Test name
Test status
Simulation time 4225902437 ps
CPU time 4.37 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:24:00 PM PDT 24
Peak memory 213608 kb
Host smart-85ab0c23-a198-476b-9965-6e3eb7a0a238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137740090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2137740090
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1377041161
Short name T420
Test name
Test status
Simulation time 4940991952 ps
CPU time 66.26 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:18:33 PM PDT 24
Peak memory 213588 kb
Host smart-8ab2b481-0318-4ba6-a36e-b53a51d1fd56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377041161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1377041161
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2544794450
Short name T427
Test name
Test status
Simulation time 585309349 ps
CPU time 2.83 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:29 PM PDT 24
Peak memory 213484 kb
Host smart-961c6541-0220-4008-885d-1816f453394f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544794450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2544794450
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2475866913
Short name T367
Test name
Test status
Simulation time 164413996 ps
CPU time 2.26 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:27 PM PDT 24
Peak memory 218184 kb
Host smart-b2d5c411-f2ef-4efa-a8e6-8202a12f9843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475866913 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2475866913
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2517334060
Short name T363
Test name
Test status
Simulation time 588134126 ps
CPU time 1.66 seconds
Started Aug 08 05:17:27 PM PDT 24
Finished Aug 08 05:17:29 PM PDT 24
Peak memory 213588 kb
Host smart-a6d39e8f-39b1-4222-a4ca-814b3ab22ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517334060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2517334060
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.253682785
Short name T315
Test name
Test status
Simulation time 86931099668 ps
CPU time 87.99 seconds
Started Aug 08 05:17:11 PM PDT 24
Finished Aug 08 05:18:39 PM PDT 24
Peak memory 205356 kb
Host smart-286872bb-1b88-4474-9f26-e0e83436d525
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253682785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.253682785
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1528202722
Short name T357
Test name
Test status
Simulation time 21369765040 ps
CPU time 47.1 seconds
Started Aug 08 05:17:11 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 205352 kb
Host smart-57b25dca-6444-4afe-984d-5037b2f1c6c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528202722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1528202722
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.202732772
Short name T308
Test name
Test status
Simulation time 12765442253 ps
CPU time 20.69 seconds
Started Aug 08 05:17:11 PM PDT 24
Finished Aug 08 05:17:32 PM PDT 24
Peak memory 205368 kb
Host smart-9ad329d3-4be3-4a2b-b13d-159f980b790f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202732772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.202732772
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3845921077
Short name T437
Test name
Test status
Simulation time 939751254 ps
CPU time 3.12 seconds
Started Aug 08 05:17:11 PM PDT 24
Finished Aug 08 05:17:14 PM PDT 24
Peak memory 204972 kb
Host smart-32891bd9-6f47-4398-b712-ab555bb4edfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845921077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3845921077
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2228500557
Short name T324
Test name
Test status
Simulation time 187640732 ps
CPU time 0.85 seconds
Started Aug 08 05:17:14 PM PDT 24
Finished Aug 08 05:17:15 PM PDT 24
Peak memory 205040 kb
Host smart-e54b72ff-726f-42a8-86a4-d717555b6455
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228500557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2228500557
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.322265109
Short name T332
Test name
Test status
Simulation time 312918813 ps
CPU time 0.73 seconds
Started Aug 08 05:17:15 PM PDT 24
Finished Aug 08 05:17:16 PM PDT 24
Peak memory 205008 kb
Host smart-5b23ff0a-ad48-459a-a7b2-a4ac0caaa533
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322265109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.322265109
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3646384858
Short name T360
Test name
Test status
Simulation time 138534063 ps
CPU time 0.8 seconds
Started Aug 08 05:17:13 PM PDT 24
Finished Aug 08 05:17:14 PM PDT 24
Peak memory 205144 kb
Host smart-34d2a4d8-d2a8-4b3c-bf28-9920b8bd753c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646384858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3646384858
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.4190957014
Short name T350
Test name
Test status
Simulation time 65114881 ps
CPU time 0.78 seconds
Started Aug 08 05:17:12 PM PDT 24
Finished Aug 08 05:17:12 PM PDT 24
Peak memory 205076 kb
Host smart-1ad2f813-f0be-4c4e-b590-b35b5c13842d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190957014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.4190957014
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3861251388
Short name T411
Test name
Test status
Simulation time 323658756 ps
CPU time 6.85 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:33 PM PDT 24
Peak memory 205368 kb
Host smart-9440ee8c-2eb0-4800-853b-441dbbf08a07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861251388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3861251388
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.518158509
Short name T362
Test name
Test status
Simulation time 33624245487 ps
CPU time 99.13 seconds
Started Aug 08 05:17:15 PM PDT 24
Finished Aug 08 05:18:54 PM PDT 24
Peak memory 221932 kb
Host smart-1f86c25e-f95a-4a22-b52d-3358909682f4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518158509 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.518158509
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1818815397
Short name T397
Test name
Test status
Simulation time 1176662892 ps
CPU time 3.43 seconds
Started Aug 08 05:17:15 PM PDT 24
Finished Aug 08 05:17:19 PM PDT 24
Peak memory 213648 kb
Host smart-8557d92c-eabd-466b-a897-13ae4c869547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818815397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1818815397
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2190654661
Short name T166
Test name
Test status
Simulation time 5657070601 ps
CPU time 12.27 seconds
Started Aug 08 05:17:11 PM PDT 24
Finished Aug 08 05:17:24 PM PDT 24
Peak memory 213720 kb
Host smart-8cf8f56a-43fe-432c-845f-9a495c219d57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190654661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2190654661
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1888452531
Short name T429
Test name
Test status
Simulation time 2408257408 ps
CPU time 33.58 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:59 PM PDT 24
Peak memory 205324 kb
Host smart-f07abfc2-3aaf-48fc-83b1-2adcb34a74c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888452531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1888452531
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2011010625
Short name T459
Test name
Test status
Simulation time 15882354033 ps
CPU time 39.39 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:18:03 PM PDT 24
Peak memory 205420 kb
Host smart-d5e82192-426b-4545-87b9-6f26a0ba7313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011010625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2011010625
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4279693415
Short name T453
Test name
Test status
Simulation time 162397392 ps
CPU time 1.78 seconds
Started Aug 08 05:17:24 PM PDT 24
Finished Aug 08 05:17:26 PM PDT 24
Peak memory 213548 kb
Host smart-2f6f9975-4f84-44b7-b1f7-2f5a5981a881
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279693415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.4279693415
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4193080263
Short name T77
Test name
Test status
Simulation time 407745242 ps
CPU time 4.84 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:29 PM PDT 24
Peak memory 220232 kb
Host smart-fcea4d27-abb4-4615-ba03-ca5a251076f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193080263 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4193080263
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4044154517
Short name T413
Test name
Test status
Simulation time 163358578 ps
CPU time 1.73 seconds
Started Aug 08 05:17:27 PM PDT 24
Finished Aug 08 05:17:29 PM PDT 24
Peak memory 213536 kb
Host smart-d29837aa-7baa-41af-a06e-cf205b2fb0d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044154517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4044154517
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3642600722
Short name T463
Test name
Test status
Simulation time 48861432362 ps
CPU time 85.81 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:18:49 PM PDT 24
Peak memory 205424 kb
Host smart-073d9f76-a275-42ee-8a8a-c18bb3cb605b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642600722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3642600722
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3845405608
Short name T381
Test name
Test status
Simulation time 4376600861 ps
CPU time 3.04 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:17:26 PM PDT 24
Peak memory 205368 kb
Host smart-70800d40-66b4-458d-ab1f-62db3c650af2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845405608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3845405608
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2222025181
Short name T90
Test name
Test status
Simulation time 15757700286 ps
CPU time 43.86 seconds
Started Aug 08 05:17:27 PM PDT 24
Finished Aug 08 05:18:11 PM PDT 24
Peak memory 205432 kb
Host smart-1e5de6dd-4586-4954-8e43-b16d1613764f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222025181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2222025181
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4138799871
Short name T382
Test name
Test status
Simulation time 2945504699 ps
CPU time 3.57 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:28 PM PDT 24
Peak memory 205300 kb
Host smart-ec43be54-459c-4149-b310-6976c480cb5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138799871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
138799871
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1522072840
Short name T57
Test name
Test status
Simulation time 539732402 ps
CPU time 1.56 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:27 PM PDT 24
Peak memory 205068 kb
Host smart-02282317-0583-45aa-b79f-9a78842429f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522072840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1522072840
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1506340732
Short name T389
Test name
Test status
Simulation time 5292226971 ps
CPU time 5.83 seconds
Started Aug 08 05:17:24 PM PDT 24
Finished Aug 08 05:17:30 PM PDT 24
Peak memory 205420 kb
Host smart-a43c0382-f054-49ac-835c-e6f511382e1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506340732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1506340732
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2028848326
Short name T386
Test name
Test status
Simulation time 803688651 ps
CPU time 1.95 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:28 PM PDT 24
Peak memory 204968 kb
Host smart-287b3059-2232-4d9f-be55-4ae6bdaaee6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028848326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2028848326
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1577964981
Short name T379
Test name
Test status
Simulation time 236255264 ps
CPU time 0.87 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:17:24 PM PDT 24
Peak memory 205076 kb
Host smart-03d934ea-4d65-43d0-a08a-9793aa2af8f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577964981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
577964981
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1392458162
Short name T378
Test name
Test status
Simulation time 48165430 ps
CPU time 0.75 seconds
Started Aug 08 05:17:24 PM PDT 24
Finished Aug 08 05:17:24 PM PDT 24
Peak memory 205116 kb
Host smart-9b9c8864-15ce-48d8-901c-58c6b9bdc0c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392458162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1392458162
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.8475808
Short name T371
Test name
Test status
Simulation time 117000540 ps
CPU time 0.71 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:26 PM PDT 24
Peak memory 205028 kb
Host smart-27eac4bc-80dd-4b19-9fc1-eb418ae5d722
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8475808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.8475808
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.840330059
Short name T435
Test name
Test status
Simulation time 3883116768 ps
CPU time 4.91 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:17:27 PM PDT 24
Peak memory 205524 kb
Host smart-5badba86-23cb-4d97-9c0d-10fdb6804d57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840330059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.840330059
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.577222971
Short name T175
Test name
Test status
Simulation time 50710262268 ps
CPU time 48.36 seconds
Started Aug 08 05:17:24 PM PDT 24
Finished Aug 08 05:18:13 PM PDT 24
Peak memory 222020 kb
Host smart-cba1b3d0-ae92-45e5-b1cf-910b57aaf222
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577222971 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.577222971
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1845665535
Short name T394
Test name
Test status
Simulation time 383938130 ps
CPU time 4.96 seconds
Started Aug 08 05:17:27 PM PDT 24
Finished Aug 08 05:17:32 PM PDT 24
Peak memory 213548 kb
Host smart-21e168ca-f6cd-4913-8168-85b304582589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845665535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1845665535
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1761390613
Short name T399
Test name
Test status
Simulation time 512009937 ps
CPU time 4.9 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 219836 kb
Host smart-d5cfc0ff-597d-4fe8-999e-ee93b6ffeb13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761390613 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1761390613
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4084569779
Short name T366
Test name
Test status
Simulation time 98949879 ps
CPU time 2.3 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 213508 kb
Host smart-b22670b4-5404-43a0-84ba-6ba5d95a7523
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084569779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4084569779
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2050829687
Short name T388
Test name
Test status
Simulation time 20564106980 ps
CPU time 30.11 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:18:11 PM PDT 24
Peak memory 205396 kb
Host smart-1a6105dd-1fe1-4665-b874-754ae9840eb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050829687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2050829687
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3478362766
Short name T335
Test name
Test status
Simulation time 2494009973 ps
CPU time 2.9 seconds
Started Aug 08 05:17:43 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 205280 kb
Host smart-06fd5291-2979-4f9f-9457-8f0151121b46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478362766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3478362766
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.499308443
Short name T439
Test name
Test status
Simulation time 712995768 ps
CPU time 2.52 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 204988 kb
Host smart-7e29f105-2a60-4ab4-ad8f-aab23bea4bcb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499308443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.499308443
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3553784709
Short name T449
Test name
Test status
Simulation time 233134301 ps
CPU time 4.19 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:53 PM PDT 24
Peak memory 205376 kb
Host smart-5e92a957-301a-4e00-a1d2-4da16c681671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553784709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3553784709
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1911283397
Short name T376
Test name
Test status
Simulation time 714907948 ps
CPU time 5.08 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:52 PM PDT 24
Peak memory 213588 kb
Host smart-ea8ff8fc-c203-44ec-9a2f-823fb1d922b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911283397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1911283397
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1207489530
Short name T121
Test name
Test status
Simulation time 499258278 ps
CPU time 2.43 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 218084 kb
Host smart-e0223dd2-d31c-400e-a496-0b7e2adb670d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207489530 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1207489530
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.732743079
Short name T417
Test name
Test status
Simulation time 294115390 ps
CPU time 2.51 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 213476 kb
Host smart-b84ad745-786f-49ad-86d6-7877d5de0fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732743079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.732743079
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3556055449
Short name T309
Test name
Test status
Simulation time 3571527586 ps
CPU time 7.95 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:55 PM PDT 24
Peak memory 205260 kb
Host smart-a22f8a94-677d-45ac-be54-58ebe8e7127b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556055449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3556055449
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1073597057
Short name T336
Test name
Test status
Simulation time 1165219339 ps
CPU time 4.02 seconds
Started Aug 08 05:17:49 PM PDT 24
Finished Aug 08 05:17:53 PM PDT 24
Peak memory 205284 kb
Host smart-aba59a8f-4a68-4efb-bda5-ea3328a13ac2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073597057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1073597057
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1923246095
Short name T320
Test name
Test status
Simulation time 474988058 ps
CPU time 1.07 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 205052 kb
Host smart-4527cb5e-0a42-4c8c-9e50-3bf5a02a8f7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923246095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1923246095
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2789412040
Short name T409
Test name
Test status
Simulation time 646348168 ps
CPU time 8.36 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:54 PM PDT 24
Peak memory 205380 kb
Host smart-d9189f5f-9d26-4b70-b654-06c60e0c86cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789412040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2789412040
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1261611146
Short name T390
Test name
Test status
Simulation time 262687625 ps
CPU time 4.33 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 213648 kb
Host smart-122a52ef-5408-4669-b406-dd66ef2b49ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261611146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1261611146
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.609373211
Short name T167
Test name
Test status
Simulation time 3602773982 ps
CPU time 17.04 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:18:02 PM PDT 24
Peak memory 213608 kb
Host smart-3d395c85-3027-48ce-9e5c-ec7f3a9860e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609373211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.609373211
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2375787910
Short name T330
Test name
Test status
Simulation time 265786156 ps
CPU time 2.55 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 215528 kb
Host smart-7e31ea51-5673-414b-a189-2b2133223104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375787910 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2375787910
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1753815347
Short name T405
Test name
Test status
Simulation time 100305671 ps
CPU time 1.6 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 213484 kb
Host smart-bfd99b4e-eef5-44d6-9afe-5026fc68fde0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753815347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1753815347
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3445372152
Short name T457
Test name
Test status
Simulation time 4604954177 ps
CPU time 2.79 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:17:45 PM PDT 24
Peak memory 205416 kb
Host smart-40c3dc2c-8182-4d2a-927e-b849fda7ecd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445372152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3445372152
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3880635759
Short name T393
Test name
Test status
Simulation time 5046485857 ps
CPU time 15.16 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:18:01 PM PDT 24
Peak memory 205420 kb
Host smart-feb9ec4e-5713-4439-949c-a7f4a45c17be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880635759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3880635759
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1198278959
Short name T403
Test name
Test status
Simulation time 627543746 ps
CPU time 1.15 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:17:41 PM PDT 24
Peak memory 204968 kb
Host smart-2dfc6781-a18d-4be0-9be9-7dcb3a3584d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198278959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1198278959
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3771165474
Short name T401
Test name
Test status
Simulation time 152199450 ps
CPU time 3.07 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 213576 kb
Host smart-2dbd6a1e-b0f2-4e53-ab31-af5a57e6d9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771165474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3771165474
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4189460154
Short name T368
Test name
Test status
Simulation time 2389366654 ps
CPU time 13.61 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:17:56 PM PDT 24
Peak memory 213632 kb
Host smart-2737421b-c734-411e-a3b2-f59cb5185229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189460154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.4
189460154
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1155666654
Short name T430
Test name
Test status
Simulation time 633167422 ps
CPU time 2.49 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 221780 kb
Host smart-731ae2c8-f701-45b1-aa75-1dd053085aa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155666654 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1155666654
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.990922603
Short name T432
Test name
Test status
Simulation time 18049543566 ps
CPU time 35.95 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:18:22 PM PDT 24
Peak memory 205420 kb
Host smart-ed0e6b41-e406-48a2-848f-2eba425e2984
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990922603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.990922603
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2275867067
Short name T346
Test name
Test status
Simulation time 5085937988 ps
CPU time 3.95 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 205440 kb
Host smart-18ba8f33-0e74-4022-99c2-c379415d3113
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275867067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2275867067
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1308905960
Short name T321
Test name
Test status
Simulation time 517377000 ps
CPU time 1.04 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 204968 kb
Host smart-1524df8d-b4dc-4854-8809-0bf9ddd8f073
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308905960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1308905960
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2272720674
Short name T103
Test name
Test status
Simulation time 878122401 ps
CPU time 4.19 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 205412 kb
Host smart-1a257fa7-4d6a-4367-9e7c-ce1ce753c100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272720674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2272720674
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1887931651
Short name T359
Test name
Test status
Simulation time 272026945 ps
CPU time 4.72 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:17:45 PM PDT 24
Peak memory 213628 kb
Host smart-85177f2b-7b6b-4cc1-8766-9a69168d5154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887931651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1887931651
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2383594661
Short name T361
Test name
Test status
Simulation time 1488959460 ps
CPU time 18.08 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:18:05 PM PDT 24
Peak memory 213620 kb
Host smart-9ba61e1a-1829-4f88-8f9e-f7c323d911d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383594661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
383594661
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3145957855
Short name T456
Test name
Test status
Simulation time 310691846 ps
CPU time 4.65 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:52 PM PDT 24
Peak memory 218596 kb
Host smart-3d2eade6-4707-47f8-8d06-df9e8708b23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145957855 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3145957855
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2987152808
Short name T356
Test name
Test status
Simulation time 226099338 ps
CPU time 1.59 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 213468 kb
Host smart-3aa4d0b1-1043-417b-b828-7613a571a7d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987152808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2987152808
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1081623253
Short name T325
Test name
Test status
Simulation time 21703342136 ps
CPU time 30.9 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:18:16 PM PDT 24
Peak memory 205388 kb
Host smart-151f17cc-dc07-4e00-a0db-249e00a4a125
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081623253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1081623253
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3656898437
Short name T460
Test name
Test status
Simulation time 1750716483 ps
CPU time 5.86 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 205224 kb
Host smart-e3f5841f-a79f-42db-a96a-3681ce7485a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656898437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3656898437
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1898973899
Short name T396
Test name
Test status
Simulation time 137013129 ps
CPU time 1.03 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:17:43 PM PDT 24
Peak memory 204980 kb
Host smart-c3bf5f89-c293-4b8d-9fee-237ca4bead38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898973899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1898973899
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3084991379
Short name T111
Test name
Test status
Simulation time 459002095 ps
CPU time 3.85 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:51 PM PDT 24
Peak memory 205368 kb
Host smart-26406a0e-2e5d-460e-af22-882568d6b3b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084991379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3084991379
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.914060547
Short name T329
Test name
Test status
Simulation time 1116548362 ps
CPU time 3.07 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 213752 kb
Host smart-f9878f81-fe98-4852-aed7-f046b6e38f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914060547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.914060547
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2036969639
Short name T163
Test name
Test status
Simulation time 3392149383 ps
CPU time 12.6 seconds
Started Aug 08 05:17:49 PM PDT 24
Finished Aug 08 05:18:02 PM PDT 24
Peak memory 213660 kb
Host smart-e7d932a7-e356-4693-9421-a174901310ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036969639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
036969639
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.288606092
Short name T414
Test name
Test status
Simulation time 398464029 ps
CPU time 4 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 221864 kb
Host smart-fe665b6d-13ac-445f-a93c-71dd4114fb0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288606092 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.288606092
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.631655363
Short name T109
Test name
Test status
Simulation time 169382771 ps
CPU time 2.59 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 213476 kb
Host smart-2710a971-7089-4acc-b861-531bcb33e1cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631655363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.631655363
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1815537927
Short name T339
Test name
Test status
Simulation time 29804408729 ps
CPU time 65.9 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:18:52 PM PDT 24
Peak memory 205316 kb
Host smart-443f1550-ce50-4b0e-a611-a6314e8a1475
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815537927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1815537927
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1413266260
Short name T364
Test name
Test status
Simulation time 4774398565 ps
CPU time 2.74 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 205316 kb
Host smart-844440ec-8be9-4282-8365-305c5b930d60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413266260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1413266260
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3299763461
Short name T441
Test name
Test status
Simulation time 601253093 ps
CPU time 1.09 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 204984 kb
Host smart-6a5a5d09-c5ec-4eab-a0dd-d72e2e73bb52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299763461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3299763461
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4005197195
Short name T112
Test name
Test status
Simulation time 872287595 ps
CPU time 7.42 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:54 PM PDT 24
Peak memory 205396 kb
Host smart-2c82b3a4-1b8c-4753-bfde-ce6de7d76864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005197195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4005197195
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.920995366
Short name T410
Test name
Test status
Simulation time 59134222 ps
CPU time 2.47 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 213720 kb
Host smart-e2f1c40c-b609-447c-9098-81be8488d552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920995366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.920995366
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2477767342
Short name T341
Test name
Test status
Simulation time 1818999875 ps
CPU time 11.07 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 213580 kb
Host smart-bae304aa-1a10-46d2-80ba-781cf7d31184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477767342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
477767342
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2302810577
Short name T431
Test name
Test status
Simulation time 691723470 ps
CPU time 3.99 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 221860 kb
Host smart-3c44432a-4075-4071-b04b-41e333e8d788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302810577 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2302810577
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.4025023112
Short name T438
Test name
Test status
Simulation time 410241882 ps
CPU time 2.58 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 213416 kb
Host smart-41615ab5-19b2-4ae7-b613-ceb30a9ce3e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025023112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.4025023112
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1437415803
Short name T434
Test name
Test status
Simulation time 45743463062 ps
CPU time 65.02 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:18:52 PM PDT 24
Peak memory 205420 kb
Host smart-6d2ecbc1-0e31-457d-a7dd-2cbf7a2555f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437415803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1437415803
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2267726433
Short name T384
Test name
Test status
Simulation time 6414360477 ps
CPU time 2.7 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 205420 kb
Host smart-e32d8ba3-31dc-4312-93e6-aac3184c5048
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267726433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2267726433
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3059885700
Short name T56
Test name
Test status
Simulation time 169758263 ps
CPU time 0.73 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 205072 kb
Host smart-b3d386ae-b594-47fd-b881-27579ff2a284
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059885700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3059885700
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2058588044
Short name T110
Test name
Test status
Simulation time 1047887531 ps
CPU time 4.39 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 205404 kb
Host smart-ab716c25-61f9-45f2-9d76-e3898914d5f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058588044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2058588044
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.994013723
Short name T365
Test name
Test status
Simulation time 3775263728 ps
CPU time 5.44 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 213716 kb
Host smart-5d1fd4b8-acf9-40b2-bab9-49dd21258c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994013723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.994013723
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1119256976
Short name T402
Test name
Test status
Simulation time 109859698 ps
CPU time 2.44 seconds
Started Aug 08 05:17:53 PM PDT 24
Finished Aug 08 05:17:56 PM PDT 24
Peak memory 213644 kb
Host smart-f741f8e2-5af0-46d6-9be8-45c69f6000ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119256976 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1119256976
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.196477154
Short name T104
Test name
Test status
Simulation time 160337509 ps
CPU time 1.65 seconds
Started Aug 08 05:17:52 PM PDT 24
Finished Aug 08 05:17:54 PM PDT 24
Peak memory 213388 kb
Host smart-d178735c-f789-476e-a7e3-e89166964abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196477154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.196477154
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2121770209
Short name T342
Test name
Test status
Simulation time 7956913295 ps
CPU time 24.33 seconds
Started Aug 08 05:17:53 PM PDT 24
Finished Aug 08 05:18:17 PM PDT 24
Peak memory 205380 kb
Host smart-6aad870e-88e8-4f93-97ff-b845c7fc959c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121770209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2121770209
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2165240795
Short name T358
Test name
Test status
Simulation time 1614098999 ps
CPU time 5.15 seconds
Started Aug 08 05:17:51 PM PDT 24
Finished Aug 08 05:17:56 PM PDT 24
Peak memory 205252 kb
Host smart-9b4b9ac4-799d-4d73-8a85-0b24a7a32eec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165240795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2165240795
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2407100692
Short name T433
Test name
Test status
Simulation time 494705882 ps
CPU time 1.92 seconds
Started Aug 08 05:17:53 PM PDT 24
Finished Aug 08 05:17:55 PM PDT 24
Peak memory 204992 kb
Host smart-ddac7e3b-32ae-401a-87ec-4f255b2931c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407100692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2407100692
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1478123167
Short name T461
Test name
Test status
Simulation time 912490763 ps
CPU time 7.56 seconds
Started Aug 08 05:17:52 PM PDT 24
Finished Aug 08 05:18:00 PM PDT 24
Peak memory 205408 kb
Host smart-7e0e9317-cfa2-4535-a90b-c5879486cb0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478123167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1478123167
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3071076764
Short name T444
Test name
Test status
Simulation time 670131937 ps
CPU time 3.56 seconds
Started Aug 08 05:17:56 PM PDT 24
Finished Aug 08 05:17:59 PM PDT 24
Peak memory 213668 kb
Host smart-53a8b424-6a77-4098-af92-44ceb4534f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071076764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3071076764
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3049950236
Short name T124
Test name
Test status
Simulation time 4214522876 ps
CPU time 24.77 seconds
Started Aug 08 05:17:50 PM PDT 24
Finished Aug 08 05:18:15 PM PDT 24
Peak memory 213668 kb
Host smart-da830b90-095a-4da0-b055-1419f64cf388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049950236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
049950236
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.517120746
Short name T464
Test name
Test status
Simulation time 1510623805 ps
CPU time 2.47 seconds
Started Aug 08 05:17:52 PM PDT 24
Finished Aug 08 05:17:55 PM PDT 24
Peak memory 216176 kb
Host smart-70536a0d-b544-4773-8774-bd61eca9b4d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517120746 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.517120746
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1686115188
Short name T84
Test name
Test status
Simulation time 481949121 ps
CPU time 2.47 seconds
Started Aug 08 05:17:54 PM PDT 24
Finished Aug 08 05:17:56 PM PDT 24
Peak memory 213532 kb
Host smart-2048d5e9-5240-436f-a9d7-e7b325f3e6e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686115188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1686115188
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.487355211
Short name T426
Test name
Test status
Simulation time 3447612842 ps
CPU time 6.57 seconds
Started Aug 08 05:17:51 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 205356 kb
Host smart-18204ea5-d50e-4c67-8a36-0f5aafc7debe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487355211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.487355211
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1685261587
Short name T316
Test name
Test status
Simulation time 5148539690 ps
CPU time 8.1 seconds
Started Aug 08 05:17:50 PM PDT 24
Finished Aug 08 05:17:59 PM PDT 24
Peak memory 205284 kb
Host smart-27b3a69d-3f4d-40fe-9245-c05bc803b4ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685261587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1685261587
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1650700799
Short name T374
Test name
Test status
Simulation time 391551766 ps
CPU time 1.59 seconds
Started Aug 08 05:17:51 PM PDT 24
Finished Aug 08 05:17:53 PM PDT 24
Peak memory 205088 kb
Host smart-29c8a4bb-071c-4503-9052-23523e14d972
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650700799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1650700799
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.254192203
Short name T395
Test name
Test status
Simulation time 224584914 ps
CPU time 6.71 seconds
Started Aug 08 05:17:55 PM PDT 24
Finished Aug 08 05:18:02 PM PDT 24
Peak memory 205312 kb
Host smart-7dbca53b-9ff5-4a28-b2d7-8d90e9a0bc1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254192203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.254192203
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2649059751
Short name T400
Test name
Test status
Simulation time 648260186 ps
CPU time 4.63 seconds
Started Aug 08 05:17:55 PM PDT 24
Finished Aug 08 05:18:00 PM PDT 24
Peak memory 213624 kb
Host smart-87689353-525a-4517-be9b-30a03bda4b33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649059751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2649059751
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4165834760
Short name T170
Test name
Test status
Simulation time 4422248643 ps
CPU time 21.94 seconds
Started Aug 08 05:17:57 PM PDT 24
Finished Aug 08 05:18:19 PM PDT 24
Peak memory 213800 kb
Host smart-e1945f99-b658-4e60-ad11-cd476ae27ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165834760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
165834760
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2132233508
Short name T344
Test name
Test status
Simulation time 203925724 ps
CPU time 2.53 seconds
Started Aug 08 05:17:51 PM PDT 24
Finished Aug 08 05:17:54 PM PDT 24
Peak memory 221788 kb
Host smart-91a7c55e-5a64-48bb-99f1-645b5d75ba74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132233508 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2132233508
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1566526849
Short name T81
Test name
Test status
Simulation time 207186264 ps
CPU time 2.64 seconds
Started Aug 08 05:17:52 PM PDT 24
Finished Aug 08 05:17:55 PM PDT 24
Peak memory 213500 kb
Host smart-e63002b1-707e-4bc7-b157-f6327bc4f88a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566526849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1566526849
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3196107182
Short name T425
Test name
Test status
Simulation time 10758455549 ps
CPU time 27.24 seconds
Started Aug 08 05:17:53 PM PDT 24
Finished Aug 08 05:18:20 PM PDT 24
Peak memory 205372 kb
Host smart-5bb9bb4c-9338-4085-9c97-9c2673676075
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196107182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3196107182
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.844251510
Short name T387
Test name
Test status
Simulation time 2469340411 ps
CPU time 2.38 seconds
Started Aug 08 05:17:55 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 205276 kb
Host smart-687a2ee0-f87c-44a7-9f07-3a2a852d887b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844251510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.844251510
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3577246947
Short name T423
Test name
Test status
Simulation time 274555464 ps
CPU time 1.03 seconds
Started Aug 08 05:17:53 PM PDT 24
Finished Aug 08 05:17:54 PM PDT 24
Peak memory 205032 kb
Host smart-c0a48fea-a86e-4370-9274-cecdc76ceae8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577246947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3577246947
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3346549664
Short name T88
Test name
Test status
Simulation time 291675212 ps
CPU time 6.81 seconds
Started Aug 08 05:17:51 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 205360 kb
Host smart-c36306ef-d983-42d0-b7eb-6206f144f42f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346549664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3346549664
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.996369413
Short name T406
Test name
Test status
Simulation time 652714518 ps
CPU time 4.92 seconds
Started Aug 08 05:17:52 PM PDT 24
Finished Aug 08 05:17:57 PM PDT 24
Peak memory 213684 kb
Host smart-25c18db4-275d-40f0-bda6-e2deb082aefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996369413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.996369413
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2416291304
Short name T172
Test name
Test status
Simulation time 913023386 ps
CPU time 10.01 seconds
Started Aug 08 05:18:00 PM PDT 24
Finished Aug 08 05:18:10 PM PDT 24
Peak memory 213692 kb
Host smart-6a5d61c3-71fb-4715-ba57-ab4979d6ffe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416291304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
416291304
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3865627683
Short name T98
Test name
Test status
Simulation time 5167709170 ps
CPU time 32.62 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:17:56 PM PDT 24
Peak memory 205408 kb
Host smart-c93cff32-59a5-418c-a52b-c1f98d627fa9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865627683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3865627683
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.559301715
Short name T422
Test name
Test status
Simulation time 13238291925 ps
CPU time 37.26 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:18:18 PM PDT 24
Peak memory 213620 kb
Host smart-08dfed43-e290-454c-a778-60487892c862
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559301715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.559301715
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.731764186
Short name T95
Test name
Test status
Simulation time 111334375 ps
CPU time 2.48 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:44 PM PDT 24
Peak memory 213628 kb
Host smart-27076638-7920-47ce-94b7-3b5d41d24e07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731764186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.731764186
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4195876896
Short name T337
Test name
Test status
Simulation time 292165368 ps
CPU time 2.39 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:36 PM PDT 24
Peak memory 218468 kb
Host smart-96e35a50-3973-46e9-aebf-814771d4216a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195876896 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4195876896
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.164995651
Short name T348
Test name
Test status
Simulation time 72103727 ps
CPU time 1.63 seconds
Started Aug 08 05:17:43 PM PDT 24
Finished Aug 08 05:17:45 PM PDT 24
Peak memory 213440 kb
Host smart-d8bb9c6b-37b5-492c-b983-a3580bc6d378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164995651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.164995651
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.154980161
Short name T310
Test name
Test status
Simulation time 212015139239 ps
CPU time 482.43 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:25:28 PM PDT 24
Peak memory 210428 kb
Host smart-a862789a-2413-49fd-aa94-aa314296bbfe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154980161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.154980161
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4019360352
Short name T318
Test name
Test status
Simulation time 15449252809 ps
CPU time 46.28 seconds
Started Aug 08 05:17:24 PM PDT 24
Finished Aug 08 05:18:11 PM PDT 24
Peak memory 205400 kb
Host smart-e73fd0e0-4e4d-4e24-bb11-afe3ed2e0ad4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019360352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.4019360352
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2786900164
Short name T91
Test name
Test status
Simulation time 4201646929 ps
CPU time 4.23 seconds
Started Aug 08 05:17:24 PM PDT 24
Finished Aug 08 05:17:28 PM PDT 24
Peak memory 205328 kb
Host smart-c65eea77-e5e5-4f44-bca2-5b8f748d24bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786900164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2786900164
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2346877945
Short name T319
Test name
Test status
Simulation time 1079785626 ps
CPU time 2.22 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:28 PM PDT 24
Peak memory 205304 kb
Host smart-5b1bf541-37a0-4c2a-bbf2-1b2067ef15aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346877945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
346877945
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1732755970
Short name T407
Test name
Test status
Simulation time 392633611 ps
CPU time 1.24 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:28 PM PDT 24
Peak memory 204912 kb
Host smart-1bf1abb8-b48f-4f1f-9067-85c257d8137d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732755970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1732755970
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1251561611
Short name T408
Test name
Test status
Simulation time 8829795780 ps
CPU time 27.2 seconds
Started Aug 08 05:17:23 PM PDT 24
Finished Aug 08 05:17:51 PM PDT 24
Peak memory 205288 kb
Host smart-ab4d3855-91dd-4949-815e-d59a55499792
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251561611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1251561611
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3384317570
Short name T447
Test name
Test status
Simulation time 111876197 ps
CPU time 1 seconds
Started Aug 08 05:17:30 PM PDT 24
Finished Aug 08 05:17:31 PM PDT 24
Peak memory 205144 kb
Host smart-48254060-3c1c-4012-b747-b5fd5a2435bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384317570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3384317570
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1911866811
Short name T428
Test name
Test status
Simulation time 158286032 ps
CPU time 0.85 seconds
Started Aug 08 05:17:26 PM PDT 24
Finished Aug 08 05:17:27 PM PDT 24
Peak memory 205096 kb
Host smart-c2c8834d-68ec-4c99-af7f-2e42bc1dae04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911866811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
911866811
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2967691848
Short name T323
Test name
Test status
Simulation time 46277800 ps
CPU time 0.85 seconds
Started Aug 08 05:17:38 PM PDT 24
Finished Aug 08 05:17:39 PM PDT 24
Peak memory 205104 kb
Host smart-d50458e6-9947-4556-a384-2427b0e3fe62
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967691848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2967691848
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2077849300
Short name T440
Test name
Test status
Simulation time 100298272 ps
CPU time 0.76 seconds
Started Aug 08 05:17:32 PM PDT 24
Finished Aug 08 05:17:33 PM PDT 24
Peak memory 205040 kb
Host smart-c49723f3-3c8c-4806-99a7-4a1ddbdafb86
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077849300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2077849300
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.144675962
Short name T102
Test name
Test status
Simulation time 535142961 ps
CPU time 4.26 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 205496 kb
Host smart-a75c18b4-a3cf-48d4-a964-241912c6795b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144675962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.144675962
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3514872893
Short name T54
Test name
Test status
Simulation time 53678752691 ps
CPU time 325.72 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:22:51 PM PDT 24
Peak memory 222032 kb
Host smart-2f96ab6e-34d5-47b1-b95b-35ad5465c5e3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514872893 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3514872893
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.773432805
Short name T465
Test name
Test status
Simulation time 282989313 ps
CPU time 4.99 seconds
Started Aug 08 05:17:25 PM PDT 24
Finished Aug 08 05:17:30 PM PDT 24
Peak memory 213732 kb
Host smart-a0d5f623-cb74-422a-a4d5-4dfc1dccf8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773432805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.773432805
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.797970509
Short name T82
Test name
Test status
Simulation time 4107211480 ps
CPU time 33.1 seconds
Started Aug 08 05:17:36 PM PDT 24
Finished Aug 08 05:18:09 PM PDT 24
Peak memory 213560 kb
Host smart-49a20464-eb39-463d-99e4-2e6dc862cb7e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797970509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.797970509
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3387962779
Short name T424
Test name
Test status
Simulation time 3556933813 ps
CPU time 26.94 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:18:07 PM PDT 24
Peak memory 213644 kb
Host smart-4fd013e6-dbb6-4fe0-a0e7-063aa086d6a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387962779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3387962779
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1116870196
Short name T101
Test name
Test status
Simulation time 161594427 ps
CPU time 1.56 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:35 PM PDT 24
Peak memory 213516 kb
Host smart-fe2678a7-1a50-4bb7-aa2c-ae47ceae7030
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116870196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1116870196
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4288462127
Short name T322
Test name
Test status
Simulation time 252102016 ps
CPU time 2.75 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 221772 kb
Host smart-4ea34e34-3c53-4e33-9c3e-da9a3b04d5d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288462127 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4288462127
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1416606039
Short name T462
Test name
Test status
Simulation time 42790117 ps
CPU time 1.45 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:35 PM PDT 24
Peak memory 213448 kb
Host smart-1bad7c53-f498-4353-99ab-aca93d00da22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416606039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1416606039
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1080301137
Short name T312
Test name
Test status
Simulation time 48071244889 ps
CPU time 128.14 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:19:51 PM PDT 24
Peak memory 205344 kb
Host smart-5d7d766f-6648-40e9-8ee3-6847b6191d76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080301137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1080301137
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2771564953
Short name T306
Test name
Test status
Simulation time 2028107011 ps
CPU time 3.87 seconds
Started Aug 08 05:17:34 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 205244 kb
Host smart-548918e4-5f3a-42c7-93d1-affef8381d38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771564953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2771564953
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.891740784
Short name T94
Test name
Test status
Simulation time 4477342197 ps
CPU time 6.43 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:40 PM PDT 24
Peak memory 205352 kb
Host smart-768bd778-3994-4837-8c0a-b083ebc1b1fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891740784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.891740784
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.708694658
Short name T383
Test name
Test status
Simulation time 5613543756 ps
CPU time 8.22 seconds
Started Aug 08 05:17:36 PM PDT 24
Finished Aug 08 05:17:44 PM PDT 24
Peak memory 205344 kb
Host smart-7a1e64c1-ccc2-4618-a122-2b30afd72da5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708694658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.708694658
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.623686699
Short name T448
Test name
Test status
Simulation time 646632173 ps
CPU time 2.17 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:36 PM PDT 24
Peak memory 204976 kb
Host smart-d82c8412-8e72-4417-b2ed-eaa3ea96b511
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623686699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.623686699
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.914200146
Short name T331
Test name
Test status
Simulation time 12280528372 ps
CPU time 30.99 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:18:06 PM PDT 24
Peak memory 205248 kb
Host smart-34616563-cd0b-4748-8de2-2848c0387785
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914200146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.914200146
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.224186400
Short name T334
Test name
Test status
Simulation time 478991137 ps
CPU time 1.38 seconds
Started Aug 08 05:17:34 PM PDT 24
Finished Aug 08 05:17:35 PM PDT 24
Peak memory 205140 kb
Host smart-9eb0c0cc-c123-42ac-bbc5-90ee0c909098
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224186400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.224186400
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2249706214
Short name T404
Test name
Test status
Simulation time 139569390 ps
CPU time 0.89 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 205104 kb
Host smart-aad6ddb5-5f08-4d40-825d-6117ce1014f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249706214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
249706214
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3880130736
Short name T333
Test name
Test status
Simulation time 92259457 ps
CPU time 0.87 seconds
Started Aug 08 05:17:43 PM PDT 24
Finished Aug 08 05:17:44 PM PDT 24
Peak memory 205060 kb
Host smart-7f8d321a-cd30-4c11-bba2-fcea2a531878
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880130736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3880130736
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1736179162
Short name T442
Test name
Test status
Simulation time 151866220 ps
CPU time 1.01 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:43 PM PDT 24
Peak memory 205024 kb
Host smart-0d662de6-3cd4-43d7-841a-4fe9fad12035
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736179162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1736179162
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1363576523
Short name T454
Test name
Test status
Simulation time 393907681 ps
CPU time 3.64 seconds
Started Aug 08 05:17:34 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 205404 kb
Host smart-7b656f6c-9793-40dc-bfad-3e183660d925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363576523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1363576523
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.961902183
Short name T391
Test name
Test status
Simulation time 20138395874 ps
CPU time 17.31 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 221872 kb
Host smart-3df2744a-44a6-4bcf-8f3e-d708959c32a2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961902183 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.961902183
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2391614508
Short name T78
Test name
Test status
Simulation time 570483699 ps
CPU time 5.17 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:17:40 PM PDT 24
Peak memory 213576 kb
Host smart-257f9e32-88ff-4c89-af57-9c0293e27d56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391614508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2391614508
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1644650400
Short name T327
Test name
Test status
Simulation time 2721916556 ps
CPU time 15.41 seconds
Started Aug 08 05:17:43 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 213488 kb
Host smart-41e43503-35c1-420d-8e5f-545b67d9d0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644650400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1644650400
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.636692253
Short name T452
Test name
Test status
Simulation time 1208629370 ps
CPU time 27.63 seconds
Started Aug 08 05:17:34 PM PDT 24
Finished Aug 08 05:18:01 PM PDT 24
Peak memory 205368 kb
Host smart-60dd697f-2685-46c1-9dc9-719c5d2b1aef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636692253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.636692253
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.853191942
Short name T345
Test name
Test status
Simulation time 1489999607 ps
CPU time 27.1 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:18:07 PM PDT 24
Peak memory 205388 kb
Host smart-f21b7b72-4129-4dfc-b567-29add7318812
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853191942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.853191942
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4015707345
Short name T83
Test name
Test status
Simulation time 167208187 ps
CPU time 2.61 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:44 PM PDT 24
Peak memory 213532 kb
Host smart-04d56775-1deb-4756-a214-6518e685875f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015707345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4015707345
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2315820745
Short name T455
Test name
Test status
Simulation time 339283734 ps
CPU time 2.72 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 221756 kb
Host smart-9efe98e5-852c-47dd-b87f-6b219dfd802f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315820745 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2315820745
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3493629107
Short name T108
Test name
Test status
Simulation time 172988428 ps
CPU time 2.34 seconds
Started Aug 08 05:17:39 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 213472 kb
Host smart-2978d91a-ceb8-49c7-bfa7-d5614d5942bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493629107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3493629107
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2972130089
Short name T314
Test name
Test status
Simulation time 12783219579 ps
CPU time 20.09 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:18:08 PM PDT 24
Peak memory 205340 kb
Host smart-4d9ba0bb-92d8-4626-a39f-9913b069d1a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972130089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2972130089
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.738307442
Short name T343
Test name
Test status
Simulation time 2427710476 ps
CPU time 4.43 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:17:45 PM PDT 24
Peak memory 205284 kb
Host smart-0b042632-6e5e-4d64-bbbc-5d3ac7347ee1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738307442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.738307442
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.852914582
Short name T92
Test name
Test status
Simulation time 9672536527 ps
CPU time 9.49 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 205416 kb
Host smart-ee1075e2-a717-4692-ac3b-dcef1e79a215
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852914582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.852914582
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4209010657
Short name T380
Test name
Test status
Simulation time 1307701866 ps
CPU time 4.69 seconds
Started Aug 08 05:17:31 PM PDT 24
Finished Aug 08 05:17:36 PM PDT 24
Peak memory 205152 kb
Host smart-be97374c-94d9-47a6-b769-0fb09768d012
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209010657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
209010657
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1287175256
Short name T445
Test name
Test status
Simulation time 767839215 ps
CPU time 1.23 seconds
Started Aug 08 05:17:39 PM PDT 24
Finished Aug 08 05:17:40 PM PDT 24
Peak memory 205064 kb
Host smart-1938baf4-0cb4-445b-af91-9c32c5379474
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287175256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1287175256
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2648748831
Short name T412
Test name
Test status
Simulation time 12057038230 ps
CPU time 18.23 seconds
Started Aug 08 05:17:32 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 205424 kb
Host smart-9fcb3943-bfdb-4787-b03e-e2d7f5842547
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648748831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2648748831
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2453753489
Short name T58
Test name
Test status
Simulation time 170170259 ps
CPU time 0.83 seconds
Started Aug 08 05:17:39 PM PDT 24
Finished Aug 08 05:17:40 PM PDT 24
Peak memory 205052 kb
Host smart-2bfdbae3-21e7-48ff-a239-d15b3b92b295
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453753489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2453753489
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.273298488
Short name T354
Test name
Test status
Simulation time 229964822 ps
CPU time 0.92 seconds
Started Aug 08 05:17:31 PM PDT 24
Finished Aug 08 05:17:32 PM PDT 24
Peak memory 204956 kb
Host smart-e00cfa52-7467-45ba-9fa1-7dcea1737071
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273298488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.273298488
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3733120561
Short name T419
Test name
Test status
Simulation time 133936307 ps
CPU time 0.87 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:17:41 PM PDT 24
Peak memory 205144 kb
Host smart-9a2f1abb-dfac-4c98-9fd8-5c80e1b2666a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733120561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3733120561
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1516868068
Short name T398
Test name
Test status
Simulation time 159093696 ps
CPU time 0.75 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:17:36 PM PDT 24
Peak memory 205056 kb
Host smart-24248a90-347e-4e4d-a352-d5bf9ffb4b2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516868068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1516868068
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1173676136
Short name T436
Test name
Test status
Simulation time 305479036 ps
CPU time 3.54 seconds
Started Aug 08 05:17:43 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 205216 kb
Host smart-ea534ca8-97cf-4535-bd6b-fd8112d960c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173676136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1173676136
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1493662862
Short name T55
Test name
Test status
Simulation time 7099648358 ps
CPU time 26.97 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:18:07 PM PDT 24
Peak memory 213792 kb
Host smart-4ca96ee6-3eed-492d-860e-245d38f1bec5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493662862 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1493662862
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3521090402
Short name T372
Test name
Test status
Simulation time 360301076 ps
CPU time 2.53 seconds
Started Aug 08 05:17:32 PM PDT 24
Finished Aug 08 05:17:35 PM PDT 24
Peak memory 213700 kb
Host smart-4859c8c4-38a9-42d4-a89a-de5082396037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521090402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3521090402
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.781272121
Short name T164
Test name
Test status
Simulation time 5139802022 ps
CPU time 9.17 seconds
Started Aug 08 05:17:36 PM PDT 24
Finished Aug 08 05:17:45 PM PDT 24
Peak memory 213720 kb
Host smart-26f91fc0-a25b-4ca9-8eca-45bda9cf9b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781272121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.781272121
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2661792478
Short name T373
Test name
Test status
Simulation time 380740486 ps
CPU time 4.48 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:17:40 PM PDT 24
Peak memory 219948 kb
Host smart-662e9ad5-f96a-4574-a5a5-d69b4b1fabe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661792478 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2661792478
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1955645565
Short name T106
Test name
Test status
Simulation time 127307704 ps
CPU time 1.72 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:43 PM PDT 24
Peak memory 213536 kb
Host smart-cecf1576-fb88-4d25-8224-36e033f85db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955645565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1955645565
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2396274541
Short name T311
Test name
Test status
Simulation time 5538736102 ps
CPU time 4.47 seconds
Started Aug 08 05:17:30 PM PDT 24
Finished Aug 08 05:17:35 PM PDT 24
Peak memory 205424 kb
Host smart-5fbd6e6c-d836-4c24-818c-ba29c19543b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396274541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2396274541
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2159544550
Short name T458
Test name
Test status
Simulation time 3222813007 ps
CPU time 9.77 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:43 PM PDT 24
Peak memory 205276 kb
Host smart-dc5ef0d8-93cf-498e-8fa8-ceb13c964551
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159544550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
159544550
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2585170543
Short name T392
Test name
Test status
Simulation time 416457739 ps
CPU time 0.8 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 205004 kb
Host smart-267890ea-b7eb-45d4-9a72-c1dce0f4e1f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585170543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
585170543
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3814743203
Short name T85
Test name
Test status
Simulation time 908914980 ps
CPU time 4.4 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 205396 kb
Host smart-d49ca7a0-275a-4aac-96cb-6e1fb14644dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814743203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3814743203
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2455477530
Short name T369
Test name
Test status
Simulation time 33831301791 ps
CPU time 19.91 seconds
Started Aug 08 05:17:40 PM PDT 24
Finished Aug 08 05:18:01 PM PDT 24
Peak memory 216736 kb
Host smart-ee3faab3-5dd0-4a5a-9ec1-721f83af4e2b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455477530 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2455477530
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4181367186
Short name T120
Test name
Test status
Simulation time 284539213 ps
CPU time 5.75 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:39 PM PDT 24
Peak memory 213552 kb
Host smart-7040a96f-3532-4936-a49a-ebdc74048a54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181367186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4181367186
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.58782656
Short name T340
Test name
Test status
Simulation time 342738254 ps
CPU time 4.38 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 220164 kb
Host smart-2c864e97-19ca-4b85-88a2-9a779d75125e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58782656 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.58782656
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1507358094
Short name T105
Test name
Test status
Simulation time 973817023 ps
CPU time 2.43 seconds
Started Aug 08 05:17:36 PM PDT 24
Finished Aug 08 05:17:39 PM PDT 24
Peak memory 213500 kb
Host smart-ca760a0d-2b69-426e-bbcd-a8cad496cdc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507358094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1507358094
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2151430688
Short name T353
Test name
Test status
Simulation time 13084160286 ps
CPU time 8.81 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 205272 kb
Host smart-597766d2-7ea2-4206-9505-495995ff0425
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151430688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2151430688
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3706160605
Short name T370
Test name
Test status
Simulation time 845852586 ps
CPU time 1.8 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:47 PM PDT 24
Peak memory 205220 kb
Host smart-9a7deed8-b29e-445b-be3c-3b25e6210a38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706160605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
706160605
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3668697430
Short name T377
Test name
Test status
Simulation time 164269079 ps
CPU time 0.81 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:17:43 PM PDT 24
Peak memory 205032 kb
Host smart-5ada1ed8-8377-4004-87a0-2547446fbedb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668697430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
668697430
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2147903537
Short name T87
Test name
Test status
Simulation time 244868463 ps
CPU time 4 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:17:39 PM PDT 24
Peak memory 205432 kb
Host smart-1907fa7f-7c6c-473e-a9d7-10fe6dd68ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147903537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2147903537
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3141937789
Short name T349
Test name
Test status
Simulation time 46166002015 ps
CPU time 90.76 seconds
Started Aug 08 05:17:38 PM PDT 24
Finished Aug 08 05:19:09 PM PDT 24
Peak memory 222080 kb
Host smart-0915b806-ad8c-4378-abfd-dec7e13944fc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141937789 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3141937789
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3173758159
Short name T351
Test name
Test status
Simulation time 512440237 ps
CPU time 4.33 seconds
Started Aug 08 05:17:32 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 213668 kb
Host smart-27146176-dbc9-481e-b2d8-8826752948f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173758159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3173758159
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.651678989
Short name T76
Test name
Test status
Simulation time 2261383724 ps
CPU time 22.7 seconds
Started Aug 08 05:17:32 PM PDT 24
Finished Aug 08 05:17:55 PM PDT 24
Peak memory 213668 kb
Host smart-e590372f-4c7b-4129-a21b-808aa92afae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651678989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.651678989
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3515669318
Short name T313
Test name
Test status
Simulation time 424844694 ps
CPU time 4.66 seconds
Started Aug 08 05:17:36 PM PDT 24
Finished Aug 08 05:17:41 PM PDT 24
Peak memory 221724 kb
Host smart-86404d3f-c47d-4124-b80a-d0173664a897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515669318 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3515669318
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.261577344
Short name T86
Test name
Test status
Simulation time 167464042 ps
CPU time 2.2 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 213512 kb
Host smart-3dc6a2ab-008d-4685-8d08-450bba22b72b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261577344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.261577344
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2128065001
Short name T317
Test name
Test status
Simulation time 20809396622 ps
CPU time 60.73 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:18:49 PM PDT 24
Peak memory 205356 kb
Host smart-8b96581e-2e32-4927-8b6e-a30ffb7fc44f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128065001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2128065001
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3099128028
Short name T375
Test name
Test status
Simulation time 838142223 ps
CPU time 1.45 seconds
Started Aug 08 05:17:47 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 205216 kb
Host smart-d1f6a361-2d8e-4584-b97b-75067f649e77
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099128028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
099128028
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1211475878
Short name T451
Test name
Test status
Simulation time 277567208 ps
CPU time 0.81 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 205048 kb
Host smart-7243dea4-6b0c-4013-b22d-e7f08ebea30c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211475878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
211475878
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2978061724
Short name T99
Test name
Test status
Simulation time 191715294 ps
CPU time 6.47 seconds
Started Aug 08 05:17:34 PM PDT 24
Finished Aug 08 05:17:40 PM PDT 24
Peak memory 205460 kb
Host smart-e7d3516c-22aa-46c0-9ed3-376c425237fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978061724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2978061724
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2028887735
Short name T174
Test name
Test status
Simulation time 49959440166 ps
CPU time 60.66 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:18:33 PM PDT 24
Peak memory 222160 kb
Host smart-57f346da-f0a8-4e4e-b4c3-5e84a8397a97
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028887735 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2028887735
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3745855193
Short name T338
Test name
Test status
Simulation time 208035969 ps
CPU time 3.64 seconds
Started Aug 08 05:17:33 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 213688 kb
Host smart-824c8d89-ea35-421f-b155-88031f2a221e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745855193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3745855193
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2655458753
Short name T421
Test name
Test status
Simulation time 1400898347 ps
CPU time 9.79 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:17:45 PM PDT 24
Peak memory 213620 kb
Host smart-89062d63-55f5-44f7-9469-5056edc9e805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655458753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2655458753
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1492050498
Short name T355
Test name
Test status
Simulation time 405076428 ps
CPU time 5.28 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:52 PM PDT 24
Peak memory 221840 kb
Host smart-27c5929a-59dc-4805-8baf-cdc28453c986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492050498 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1492050498
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2492164401
Short name T107
Test name
Test status
Simulation time 657535764 ps
CPU time 2.42 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 213480 kb
Host smart-2296797b-5f6e-421e-90e4-f5cec70c1d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492164401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2492164401
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1307012651
Short name T418
Test name
Test status
Simulation time 9977797801 ps
CPU time 13.54 seconds
Started Aug 08 05:17:37 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 205404 kb
Host smart-869a5766-fc7e-48f5-893a-ecc770c901be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307012651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1307012651
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2353794228
Short name T352
Test name
Test status
Simulation time 2614324532 ps
CPU time 1.81 seconds
Started Aug 08 05:17:37 PM PDT 24
Finished Aug 08 05:17:39 PM PDT 24
Peak memory 205332 kb
Host smart-19baa887-00f9-4021-9176-fc8dd021cbda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353794228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
353794228
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1893706067
Short name T446
Test name
Test status
Simulation time 1193660418 ps
CPU time 0.94 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 205036 kb
Host smart-f1019faa-856d-4f53-a8ee-272533ee3f08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893706067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
893706067
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3176912742
Short name T97
Test name
Test status
Simulation time 2227677281 ps
CPU time 7.75 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:56 PM PDT 24
Peak memory 205416 kb
Host smart-2473ae10-450a-482a-961c-82aad6526da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176912742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3176912742
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4156087527
Short name T347
Test name
Test status
Simulation time 50313243244 ps
CPU time 162.18 seconds
Started Aug 08 05:17:35 PM PDT 24
Finished Aug 08 05:20:18 PM PDT 24
Peak memory 221864 kb
Host smart-01da0f61-3c71-4b62-b743-1d7a17c9fb1d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156087527 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4156087527
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.530961537
Short name T385
Test name
Test status
Simulation time 182471916 ps
CPU time 2.49 seconds
Started Aug 08 05:17:48 PM PDT 24
Finished Aug 08 05:17:50 PM PDT 24
Peak memory 213696 kb
Host smart-610434e5-d253-4e2f-9f6a-32c5b42cc73f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530961537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.530961537
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.53055675
Short name T168
Test name
Test status
Simulation time 3411246865 ps
CPU time 11.79 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:53 PM PDT 24
Peak memory 213700 kb
Host smart-f00ec275-07d2-4db9-8f27-56946be365a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53055675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.53055675
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3615185597
Short name T415
Test name
Test status
Simulation time 397055877 ps
CPU time 2.66 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 218640 kb
Host smart-4d516b8e-a5a1-4a70-b0bc-98a25d4818fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615185597 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3615185597
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4267053476
Short name T443
Test name
Test status
Simulation time 174722716 ps
CPU time 2.28 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 213504 kb
Host smart-d046d987-a3f7-40ad-ade0-8026d7f58269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267053476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4267053476
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2268015860
Short name T416
Test name
Test status
Simulation time 37149973355 ps
CPU time 33.21 seconds
Started Aug 08 05:17:42 PM PDT 24
Finished Aug 08 05:18:16 PM PDT 24
Peak memory 205364 kb
Host smart-6917d7ee-8f5e-4dfa-b2ee-feba98e2e5b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268015860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2268015860
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3459714770
Short name T307
Test name
Test status
Simulation time 2161793172 ps
CPU time 1.46 seconds
Started Aug 08 05:17:46 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 205252 kb
Host smart-7164d09a-80eb-41e4-9ba4-638da3325aca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459714770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
459714770
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2197745158
Short name T326
Test name
Test status
Simulation time 357941663 ps
CPU time 1.11 seconds
Started Aug 08 05:17:41 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 204972 kb
Host smart-2c42ae51-dcb8-4c44-afc7-d8da41aa9f74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197745158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
197745158
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.408585299
Short name T96
Test name
Test status
Simulation time 2113436561 ps
CPU time 8.06 seconds
Started Aug 08 05:17:49 PM PDT 24
Finished Aug 08 05:17:58 PM PDT 24
Peak memory 205436 kb
Host smart-95bd2331-1c59-40d2-8665-1f3937c79c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408585299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.408585299
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1290869039
Short name T450
Test name
Test status
Simulation time 409299656 ps
CPU time 2.73 seconds
Started Aug 08 05:17:45 PM PDT 24
Finished Aug 08 05:17:48 PM PDT 24
Peak memory 213680 kb
Host smart-77d3d201-26ed-4ab3-95ef-71086487fd5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290869039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1290869039
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1122054579
Short name T171
Test name
Test status
Simulation time 1877270453 ps
CPU time 10.77 seconds
Started Aug 08 05:17:44 PM PDT 24
Finished Aug 08 05:17:55 PM PDT 24
Peak memory 213652 kb
Host smart-8086b78e-5813-42de-8116-66457b256c62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122054579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1122054579
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2070172252
Short name T199
Test name
Test status
Simulation time 272754406 ps
CPU time 0.76 seconds
Started Aug 08 05:23:20 PM PDT 24
Finished Aug 08 05:23:21 PM PDT 24
Peak memory 205108 kb
Host smart-83cdecff-b69a-45a2-b420-49d4410b510c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070172252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2070172252
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3535888656
Short name T193
Test name
Test status
Simulation time 2335068750 ps
CPU time 2.06 seconds
Started Aug 08 05:22:54 PM PDT 24
Finished Aug 08 05:22:56 PM PDT 24
Peak memory 205444 kb
Host smart-c0b5a698-ccef-4b0d-9639-f1ce440e5e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535888656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3535888656
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.524341534
Short name T226
Test name
Test status
Simulation time 1531266198 ps
CPU time 5.14 seconds
Started Aug 08 05:22:54 PM PDT 24
Finished Aug 08 05:22:59 PM PDT 24
Peak memory 205188 kb
Host smart-2183a02d-ec94-4073-b07e-eab6f000d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524341534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.524341534
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.6478275
Short name T16
Test name
Test status
Simulation time 1334268081 ps
CPU time 2.77 seconds
Started Aug 08 05:22:54 PM PDT 24
Finished Aug 08 05:22:57 PM PDT 24
Peak memory 204864 kb
Host smart-0b85bb02-8cd9-4bfe-8bcc-79b2ee95bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6478275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.6478275
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1460251127
Short name T14
Test name
Test status
Simulation time 188485751 ps
CPU time 0.8 seconds
Started Aug 08 05:22:54 PM PDT 24
Finished Aug 08 05:22:55 PM PDT 24
Peak memory 204940 kb
Host smart-a97fadac-c63e-4115-9375-bf3fe7d9a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460251127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1460251127
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1932430493
Short name T256
Test name
Test status
Simulation time 197354277 ps
CPU time 1.26 seconds
Started Aug 08 05:22:54 PM PDT 24
Finished Aug 08 05:22:55 PM PDT 24
Peak memory 204952 kb
Host smart-cdf8e19c-dd6d-4a51-a366-6eff68f2f0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932430493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1932430493
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2645688203
Short name T189
Test name
Test status
Simulation time 162936786 ps
CPU time 1.14 seconds
Started Aug 08 05:23:04 PM PDT 24
Finished Aug 08 05:23:05 PM PDT 24
Peak memory 204860 kb
Host smart-99791e69-169e-44b3-b89e-680df34cfc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645688203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2645688203
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3720653837
Short name T217
Test name
Test status
Simulation time 47981155 ps
CPU time 0.92 seconds
Started Aug 08 05:23:06 PM PDT 24
Finished Aug 08 05:23:07 PM PDT 24
Peak memory 215332 kb
Host smart-085ceb1c-4a94-47ea-b1c0-bef45f438431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720653837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3720653837
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1576131483
Short name T198
Test name
Test status
Simulation time 510272687 ps
CPU time 1.11 seconds
Started Aug 08 05:23:03 PM PDT 24
Finished Aug 08 05:23:04 PM PDT 24
Peak memory 204948 kb
Host smart-68858edb-c64e-4da7-be5c-0edca62dcc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576131483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1576131483
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3710102109
Short name T216
Test name
Test status
Simulation time 546427914 ps
CPU time 0.87 seconds
Started Aug 08 05:23:05 PM PDT 24
Finished Aug 08 05:23:06 PM PDT 24
Peak memory 204864 kb
Host smart-f8b61d56-daf7-403a-9975-e5009c54c855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710102109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3710102109
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3784959476
Short name T220
Test name
Test status
Simulation time 188753429 ps
CPU time 0.73 seconds
Started Aug 08 05:23:05 PM PDT 24
Finished Aug 08 05:23:06 PM PDT 24
Peak memory 204836 kb
Host smart-79b441c7-cd3f-47fe-95a3-08697fa70887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784959476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3784959476
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3262317463
Short name T192
Test name
Test status
Simulation time 371218521 ps
CPU time 1.08 seconds
Started Aug 08 05:23:02 PM PDT 24
Finished Aug 08 05:23:03 PM PDT 24
Peak memory 204836 kb
Host smart-4bd3ae68-8a85-44d5-a421-d12c3db9430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262317463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3262317463
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1230244984
Short name T242
Test name
Test status
Simulation time 268453242 ps
CPU time 0.84 seconds
Started Aug 08 05:23:05 PM PDT 24
Finished Aug 08 05:23:07 PM PDT 24
Peak memory 204860 kb
Host smart-b32ea98d-07a0-4f03-afcd-6dfa83622799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230244984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1230244984
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3695836660
Short name T202
Test name
Test status
Simulation time 99046055 ps
CPU time 0.84 seconds
Started Aug 08 05:23:05 PM PDT 24
Finished Aug 08 05:23:06 PM PDT 24
Peak memory 204792 kb
Host smart-2041c089-709e-4e42-8efa-e08c58f3b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695836660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3695836660
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1186067207
Short name T190
Test name
Test status
Simulation time 487450139 ps
CPU time 1.94 seconds
Started Aug 08 05:23:08 PM PDT 24
Finished Aug 08 05:23:10 PM PDT 24
Peak memory 204880 kb
Host smart-efdc5421-4d82-4bd8-af74-11cc894da48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186067207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1186067207
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2886268431
Short name T281
Test name
Test status
Simulation time 649839375 ps
CPU time 1.58 seconds
Started Aug 08 05:23:04 PM PDT 24
Finished Aug 08 05:23:06 PM PDT 24
Peak memory 204904 kb
Host smart-c6984245-47f7-408e-b89d-a7fd12d66eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886268431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2886268431
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.620335637
Short name T8
Test name
Test status
Simulation time 137257867 ps
CPU time 0.9 seconds
Started Aug 08 05:23:05 PM PDT 24
Finished Aug 08 05:23:06 PM PDT 24
Peak memory 213076 kb
Host smart-979c00a5-0309-4bd1-b44d-aae22958c2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620335637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.620335637
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2275177145
Short name T305
Test name
Test status
Simulation time 447214127 ps
CPU time 1.42 seconds
Started Aug 08 05:23:08 PM PDT 24
Finished Aug 08 05:23:09 PM PDT 24
Peak memory 204880 kb
Host smart-e75e6212-21b7-49fa-a177-6a9034e81209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275177145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2275177145
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1943588437
Short name T125
Test name
Test status
Simulation time 4785789407 ps
CPU time 8.04 seconds
Started Aug 08 05:23:03 PM PDT 24
Finished Aug 08 05:23:11 PM PDT 24
Peak memory 205220 kb
Host smart-e602e870-5c6e-4997-8fa9-900ac94bcf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943588437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1943588437
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2535783595
Short name T293
Test name
Test status
Simulation time 4767776793 ps
CPU time 13.88 seconds
Started Aug 08 05:22:55 PM PDT 24
Finished Aug 08 05:23:09 PM PDT 24
Peak memory 205392 kb
Host smart-74bb5faa-5d8c-4e09-9936-537aa73c2df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535783595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2535783595
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3224865772
Short name T63
Test name
Test status
Simulation time 468235388 ps
CPU time 1.11 seconds
Started Aug 08 05:23:14 PM PDT 24
Finished Aug 08 05:23:15 PM PDT 24
Peak memory 228484 kb
Host smart-71275d73-ba2f-434a-9338-f2418c9974ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224865772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3224865772
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1303021814
Short name T234
Test name
Test status
Simulation time 5487812006 ps
CPU time 8.48 seconds
Started Aug 08 05:22:56 PM PDT 24
Finished Aug 08 05:23:05 PM PDT 24
Peak memory 205148 kb
Host smart-9081116e-1fde-42e5-a7b3-e16a0f5cadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303021814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1303021814
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2737084157
Short name T74
Test name
Test status
Simulation time 20909734324 ps
CPU time 227.95 seconds
Started Aug 08 05:23:08 PM PDT 24
Finished Aug 08 05:26:56 PM PDT 24
Peak memory 221684 kb
Host smart-f522545e-1599-4353-924d-3a786f0a6494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737084157 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2737084157
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1477054635
Short name T53
Test name
Test status
Simulation time 7798064842 ps
CPU time 21.49 seconds
Started Aug 08 05:22:52 PM PDT 24
Finished Aug 08 05:23:14 PM PDT 24
Peak memory 205168 kb
Host smart-8e5adb68-111a-430d-8436-75cbeb78dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477054635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1477054635
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1830564631
Short name T37
Test name
Test status
Simulation time 157041582 ps
CPU time 0.78 seconds
Started Aug 08 05:23:23 PM PDT 24
Finished Aug 08 05:23:24 PM PDT 24
Peak memory 204876 kb
Host smart-d2ad0b0b-f0b2-4da6-82f2-eb4a3174ac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830564631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1830564631
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2616011120
Short name T235
Test name
Test status
Simulation time 98326647 ps
CPU time 0.76 seconds
Started Aug 08 05:23:21 PM PDT 24
Finished Aug 08 05:23:22 PM PDT 24
Peak memory 204848 kb
Host smart-93b313e1-94cc-47b6-aa8f-3eafc3cb7bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616011120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2616011120
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1316170763
Short name T129
Test name
Test status
Simulation time 11990685827 ps
CPU time 32.27 seconds
Started Aug 08 05:23:15 PM PDT 24
Finished Aug 08 05:23:48 PM PDT 24
Peak memory 213644 kb
Host smart-380fab88-18a2-4ffa-afd6-be8a158ecaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316170763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1316170763
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.404580582
Short name T287
Test name
Test status
Simulation time 575388678 ps
CPU time 1.53 seconds
Started Aug 08 05:23:14 PM PDT 24
Finished Aug 08 05:23:15 PM PDT 24
Peak memory 204844 kb
Host smart-08a850c7-7dfb-4ec2-9675-cc003ddb93c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404580582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.404580582
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1534302508
Short name T29
Test name
Test status
Simulation time 261450271 ps
CPU time 1.1 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:23 PM PDT 24
Peak memory 205152 kb
Host smart-c9889764-e4fe-4ebd-8576-49c718271f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534302508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1534302508
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2183352851
Short name T117
Test name
Test status
Simulation time 451278904 ps
CPU time 2.08 seconds
Started Aug 08 05:23:15 PM PDT 24
Finished Aug 08 05:23:18 PM PDT 24
Peak memory 204936 kb
Host smart-5b453063-7e84-4cb0-9e99-909682417c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183352851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2183352851
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3274379443
Short name T210
Test name
Test status
Simulation time 307734124 ps
CPU time 0.81 seconds
Started Aug 08 05:23:14 PM PDT 24
Finished Aug 08 05:23:15 PM PDT 24
Peak memory 204948 kb
Host smart-17c26d5b-3f53-43ef-8318-28db7559de7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274379443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3274379443
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1532385670
Short name T211
Test name
Test status
Simulation time 93511987 ps
CPU time 0.98 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:23 PM PDT 24
Peak memory 215420 kb
Host smart-28daf458-351e-4f23-a114-d0a0f5c3e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532385670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1532385670
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.117545784
Short name T286
Test name
Test status
Simulation time 3137857464 ps
CPU time 4.65 seconds
Started Aug 08 05:23:15 PM PDT 24
Finished Aug 08 05:23:19 PM PDT 24
Peak memory 213600 kb
Host smart-8856633b-1aab-497f-b796-0b76aa305f6a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117545784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.117545784
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1536830931
Short name T273
Test name
Test status
Simulation time 164984593 ps
CPU time 1.11 seconds
Started Aug 08 05:23:14 PM PDT 24
Finished Aug 08 05:23:15 PM PDT 24
Peak memory 204936 kb
Host smart-4d391a50-77ec-4c6c-aa43-3c37520a9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536830931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1536830931
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2857034081
Short name T153
Test name
Test status
Simulation time 289857872 ps
CPU time 0.87 seconds
Started Aug 08 05:23:12 PM PDT 24
Finished Aug 08 05:23:13 PM PDT 24
Peak memory 204904 kb
Host smart-788b3f42-d079-45dd-b387-83100665a2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857034081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2857034081
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4290492006
Short name T201
Test name
Test status
Simulation time 557628720 ps
CPU time 2.07 seconds
Started Aug 08 05:23:21 PM PDT 24
Finished Aug 08 05:23:24 PM PDT 24
Peak memory 204912 kb
Host smart-d46d9b43-3a78-49f5-9cc3-5f49dabca0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290492006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.4290492006
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2477064532
Short name T195
Test name
Test status
Simulation time 1660502677 ps
CPU time 5.24 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:27 PM PDT 24
Peak memory 205036 kb
Host smart-bf8f4eb1-7e93-4009-bcc5-d3652ffdee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477064532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2477064532
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3777947180
Short name T280
Test name
Test status
Simulation time 893051087 ps
CPU time 1.32 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:23 PM PDT 24
Peak memory 204924 kb
Host smart-e90618fd-c36e-4e26-bc44-734fcdbe3019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777947180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3777947180
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.35948052
Short name T206
Test name
Test status
Simulation time 101519720 ps
CPU time 0.93 seconds
Started Aug 08 05:23:13 PM PDT 24
Finished Aug 08 05:23:14 PM PDT 24
Peak memory 204888 kb
Host smart-cdcd8c32-b2b5-40fe-b03e-2e61225d60fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35948052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.35948052
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3000818259
Short name T240
Test name
Test status
Simulation time 795139671 ps
CPU time 1.91 seconds
Started Aug 08 05:23:13 PM PDT 24
Finished Aug 08 05:23:15 PM PDT 24
Peak memory 204860 kb
Host smart-cd61c782-117b-42c3-a697-daff6e6b4c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000818259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3000818259
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3271057535
Short name T25
Test name
Test status
Simulation time 314286379 ps
CPU time 0.88 seconds
Started Aug 08 05:23:13 PM PDT 24
Finished Aug 08 05:23:14 PM PDT 24
Peak memory 213160 kb
Host smart-3bdcecf0-82e1-42c2-afd7-e0abde9eef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271057535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3271057535
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1117742373
Short name T253
Test name
Test status
Simulation time 417744837 ps
CPU time 0.99 seconds
Started Aug 08 05:23:23 PM PDT 24
Finished Aug 08 05:23:24 PM PDT 24
Peak memory 204852 kb
Host smart-bad40fe4-758b-4106-a1d7-a78783b0ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117742373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1117742373
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1533879091
Short name T31
Test name
Test status
Simulation time 32343552 ps
CPU time 0.82 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:23 PM PDT 24
Peak memory 213104 kb
Host smart-5b819e12-77a2-4c33-8a06-f67338060ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533879091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1533879091
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2218942519
Short name T42
Test name
Test status
Simulation time 850856476 ps
CPU time 1.43 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:23 PM PDT 24
Peak memory 229152 kb
Host smart-b9c409af-9b9c-4d27-a229-3f61cd0ee536
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218942519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2218942519
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1595824101
Short name T176
Test name
Test status
Simulation time 3843211954 ps
CPU time 7.11 seconds
Started Aug 08 05:23:14 PM PDT 24
Finished Aug 08 05:23:21 PM PDT 24
Peak memory 205236 kb
Host smart-d8284523-0262-4408-8bba-43cd350ec37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595824101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1595824101
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1544031455
Short name T255
Test name
Test status
Simulation time 1221962978 ps
CPU time 4.27 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:27 PM PDT 24
Peak memory 205092 kb
Host smart-7bc247ed-be7c-4793-ad78-24a3ede55fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544031455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1544031455
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3744050100
Short name T28
Test name
Test status
Simulation time 41564233 ps
CPU time 0.74 seconds
Started Aug 08 05:23:51 PM PDT 24
Finished Aug 08 05:23:52 PM PDT 24
Peak memory 204928 kb
Host smart-ed5bb2c0-8eb6-49ee-ba98-1fc8aab9558e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744050100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3744050100
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1176973741
Short name T230
Test name
Test status
Simulation time 6887723203 ps
CPU time 6.52 seconds
Started Aug 08 05:23:56 PM PDT 24
Finished Aug 08 05:24:03 PM PDT 24
Peak memory 213600 kb
Host smart-6f13f38c-b8f4-4a68-8cc6-ecbbd879525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176973741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1176973741
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3856329131
Short name T146
Test name
Test status
Simulation time 896057000 ps
CPU time 2.28 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 205328 kb
Host smart-bdf888d5-ad6c-4eec-8d41-aa21b62a8f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856329131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3856329131
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2966345633
Short name T238
Test name
Test status
Simulation time 10056283740 ps
CPU time 27.59 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 05:24:21 PM PDT 24
Peak memory 221744 kb
Host smart-ef761e25-4cb5-4305-a44e-0fd990cd6551
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966345633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2966345633
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2332807801
Short name T64
Test name
Test status
Simulation time 2786747945 ps
CPU time 3.06 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 205408 kb
Host smart-79871cbf-4c72-4f5b-ac94-ae78325272e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332807801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2332807801
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1823459337
Short name T114
Test name
Test status
Simulation time 99182494 ps
CPU time 0.75 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:54 PM PDT 24
Peak memory 204884 kb
Host smart-879ffaf0-ace4-435c-b4b5-60801943d000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823459337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1823459337
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3797510101
Short name T266
Test name
Test status
Simulation time 3073341980 ps
CPU time 4.78 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 214248 kb
Host smart-153877e2-f07b-46b2-a37e-dbef365eb770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797510101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3797510101
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1573347163
Short name T245
Test name
Test status
Simulation time 8710954523 ps
CPU time 24.62 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:24:18 PM PDT 24
Peak memory 213612 kb
Host smart-07c686b5-7696-4fe8-91c1-add7143a3bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573347163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1573347163
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1227910282
Short name T1
Test name
Test status
Simulation time 2759645689 ps
CPU time 3.13 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 213604 kb
Host smart-bab209e9-03b5-4cf5-b7b0-16c50e46449c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227910282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1227910282
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3729301991
Short name T51
Test name
Test status
Simulation time 1363995307 ps
CPU time 2 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 05:23:54 PM PDT 24
Peak memory 205232 kb
Host smart-feac93f2-88db-4ea1-b50e-1eac57449738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729301991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3729301991
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3393853
Short name T139
Test name
Test status
Simulation time 10758960386 ps
CPU time 3.32 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:57 PM PDT 24
Peak memory 205148 kb
Host smart-0181c3fd-86f7-4456-85d4-bd0c2b2f4607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3393853
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.4178089698
Short name T259
Test name
Test status
Simulation time 53800601 ps
CPU time 0.81 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:23:56 PM PDT 24
Peak memory 204844 kb
Host smart-3d176d05-731c-4944-a3d2-30b4ec0e6f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178089698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.4178089698
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2578986572
Short name T244
Test name
Test status
Simulation time 1342576466 ps
CPU time 2.75 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 05:23:55 PM PDT 24
Peak memory 205164 kb
Host smart-077331c3-04ed-4d7e-964c-8f83a8cef404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578986572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2578986572
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1863567642
Short name T45
Test name
Test status
Simulation time 4935594196 ps
CPU time 5.45 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 213492 kb
Host smart-b0ca2c72-0f47-4981-a104-8553f423854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863567642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1863567642
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2302035877
Short name T205
Test name
Test status
Simulation time 8899996875 ps
CPU time 4.72 seconds
Started Aug 08 05:23:57 PM PDT 24
Finished Aug 08 05:24:02 PM PDT 24
Peak memory 213576 kb
Host smart-fd948b8c-2a72-4dc1-b3de-dec8b74a6d51
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302035877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2302035877
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3910535856
Short name T277
Test name
Test status
Simulation time 795253972 ps
CPU time 3.09 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 05:23:57 PM PDT 24
Peak memory 205276 kb
Host smart-43cc04ef-3f02-42e4-85e0-d67ceb64d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910535856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3910535856
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1155140489
Short name T233
Test name
Test status
Simulation time 2652438962 ps
CPU time 8.47 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:24:02 PM PDT 24
Peak memory 213464 kb
Host smart-6c96b7ba-4a72-43df-9b43-d84534e7339f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155140489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1155140489
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4275002662
Short name T185
Test name
Test status
Simulation time 38477952 ps
CPU time 0.77 seconds
Started Aug 08 05:23:57 PM PDT 24
Finished Aug 08 05:23:57 PM PDT 24
Peak memory 204900 kb
Host smart-cb61a44f-326d-4605-a721-d60751695372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275002662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4275002662
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.167720302
Short name T237
Test name
Test status
Simulation time 6553180685 ps
CPU time 10.79 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 05:24:03 PM PDT 24
Peak memory 205352 kb
Host smart-74390a6a-abfb-4978-bcd8-6b2098bc3ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167720302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.167720302
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3633172193
Short name T2
Test name
Test status
Simulation time 4708417151 ps
CPU time 6.13 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 213544 kb
Host smart-29b82bde-48f3-4a12-a317-221b97c80dc5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633172193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3633172193
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3742631450
Short name T3
Test name
Test status
Simulation time 5847627000 ps
CPU time 5.3 seconds
Started Aug 08 05:23:56 PM PDT 24
Finished Aug 08 05:24:02 PM PDT 24
Peak memory 205416 kb
Host smart-c9492355-67fa-4789-a7ce-d7001dcbded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742631450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3742631450
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.415288204
Short name T250
Test name
Test status
Simulation time 6931450996 ps
CPU time 6.64 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 05:24:01 PM PDT 24
Peak memory 213404 kb
Host smart-018ed3d8-21e4-42c1-ab16-a01ad49468de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415288204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.415288204
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.971693242
Short name T283
Test name
Test status
Simulation time 29018847 ps
CPU time 0.79 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:03 PM PDT 24
Peak memory 204888 kb
Host smart-d22b0913-c4b4-4e93-ae35-a6c622c378f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971693242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.971693242
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.642780123
Short name T144
Test name
Test status
Simulation time 19744038217 ps
CPU time 10.34 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:13 PM PDT 24
Peak memory 213568 kb
Host smart-31d5d346-8e27-4adb-82b7-bec00c6381ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642780123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.642780123
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.515623148
Short name T128
Test name
Test status
Simulation time 2392311385 ps
CPU time 7.52 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:09 PM PDT 24
Peak memory 213560 kb
Host smart-d7d9632e-eb7b-4bbf-ad14-8cf87c5384e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515623148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.515623148
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.178655363
Short name T232
Test name
Test status
Simulation time 7826332702 ps
CPU time 21.37 seconds
Started Aug 08 05:24:04 PM PDT 24
Finished Aug 08 05:24:25 PM PDT 24
Peak memory 213648 kb
Host smart-528a17a7-bdcb-4fe5-a5e4-651325c1c67a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178655363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.178655363
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3916686835
Short name T196
Test name
Test status
Simulation time 10161815690 ps
CPU time 7.97 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:09 PM PDT 24
Peak memory 213540 kb
Host smart-fee711d8-f64e-4ccc-8a59-6cb4e7d8e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916686835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3916686835
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1781554480
Short name T20
Test name
Test status
Simulation time 3544487462 ps
CPU time 3.46 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:05 PM PDT 24
Peak memory 205208 kb
Host smart-d787e799-7b22-40cd-9425-71ea177216c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781554480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1781554480
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4286079943
Short name T251
Test name
Test status
Simulation time 164110748 ps
CPU time 0.89 seconds
Started Aug 08 05:24:05 PM PDT 24
Finished Aug 08 05:24:06 PM PDT 24
Peak memory 204908 kb
Host smart-4a1fd96f-95f2-4677-a99a-a172f5945d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286079943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4286079943
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1400681506
Short name T268
Test name
Test status
Simulation time 9435345419 ps
CPU time 10.81 seconds
Started Aug 08 05:24:03 PM PDT 24
Finished Aug 08 05:24:14 PM PDT 24
Peak memory 215264 kb
Host smart-66d08e61-672b-4bb3-a10e-a10866d0f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400681506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1400681506
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3132397554
Short name T247
Test name
Test status
Simulation time 15248926821 ps
CPU time 42.11 seconds
Started Aug 08 05:24:03 PM PDT 24
Finished Aug 08 05:24:45 PM PDT 24
Peak memory 213648 kb
Host smart-88127640-d9a7-4d18-b50f-2cc05de77a4e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132397554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3132397554
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1820693363
Short name T186
Test name
Test status
Simulation time 862091342 ps
CPU time 1.16 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:04 PM PDT 24
Peak memory 205008 kb
Host smart-7f5f860c-24e6-4c90-8167-17b9f4e3ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820693363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1820693363
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.790528461
Short name T13
Test name
Test status
Simulation time 3926192119 ps
CPU time 3.93 seconds
Started Aug 08 05:24:04 PM PDT 24
Finished Aug 08 05:24:08 PM PDT 24
Peak memory 213336 kb
Host smart-8b2b5e66-8de9-41ff-9f28-a9aa664bc8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790528461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.790528461
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3801334394
Short name T44
Test name
Test status
Simulation time 4097707875 ps
CPU time 5.01 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:07 PM PDT 24
Peak memory 213608 kb
Host smart-216493f2-4981-4bb5-b65a-d55421fcf169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801334394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3801334394
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2913081746
Short name T184
Test name
Test status
Simulation time 2260352174 ps
CPU time 3.93 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:05 PM PDT 24
Peak memory 213564 kb
Host smart-74fa6838-e2c6-44e7-be66-8eb5d5d4fabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913081746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2913081746
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1988109142
Short name T279
Test name
Test status
Simulation time 14337194287 ps
CPU time 22.5 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:24 PM PDT 24
Peak memory 213536 kb
Host smart-772fcf0b-4027-48c0-95ea-02691cc6dfcb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988109142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1988109142
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1965708446
Short name T208
Test name
Test status
Simulation time 1628043989 ps
CPU time 2.12 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:04 PM PDT 24
Peak memory 205384 kb
Host smart-880c3a83-0753-4f75-b3c0-62bbfed2a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965708446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1965708446
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1855102452
Short name T132
Test name
Test status
Simulation time 1390794242 ps
CPU time 2.17 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:04 PM PDT 24
Peak memory 205052 kb
Host smart-d633cad4-f933-40ce-8c0d-8b8ce821d40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855102452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1855102452
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.604770569
Short name T241
Test name
Test status
Simulation time 74760133 ps
CPU time 0.82 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:03 PM PDT 24
Peak memory 204872 kb
Host smart-6c1cd299-be3c-4cdb-ae95-a6a2387acb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604770569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.604770569
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2505849063
Short name T22
Test name
Test status
Simulation time 13286595956 ps
CPU time 43.34 seconds
Started Aug 08 05:24:06 PM PDT 24
Finished Aug 08 05:24:50 PM PDT 24
Peak memory 213556 kb
Host smart-9210198c-df68-4999-8867-41e6fe4a8547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505849063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2505849063
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1261547664
Short name T301
Test name
Test status
Simulation time 1929815998 ps
CPU time 6.85 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:09 PM PDT 24
Peak memory 205568 kb
Host smart-6179ead7-181a-4342-8089-7e1e96a29ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261547664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1261547664
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1109992956
Short name T219
Test name
Test status
Simulation time 10499914669 ps
CPU time 10.74 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:13 PM PDT 24
Peak memory 213572 kb
Host smart-76bf3f63-1812-49f1-972d-2fc0d1a3ae6e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109992956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1109992956
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.940954847
Short name T73
Test name
Test status
Simulation time 2496150776 ps
CPU time 2.77 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:05 PM PDT 24
Peak memory 205340 kb
Host smart-0a27e3bf-26ef-470f-b0a1-4d724fe5f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940954847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.940954847
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3622513244
Short name T133
Test name
Test status
Simulation time 13638689511 ps
CPU time 21.93 seconds
Started Aug 08 05:24:05 PM PDT 24
Finished Aug 08 05:24:27 PM PDT 24
Peak memory 213416 kb
Host smart-78488ddd-0d30-40dd-842e-eb93d80a77e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622513244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3622513244
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3048670626
Short name T231
Test name
Test status
Simulation time 57968007 ps
CPU time 0.9 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:02 PM PDT 24
Peak memory 204984 kb
Host smart-de2f074a-dd44-401d-90f0-d272956acbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048670626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3048670626
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3889009013
Short name T304
Test name
Test status
Simulation time 10373267893 ps
CPU time 10.5 seconds
Started Aug 08 05:24:02 PM PDT 24
Finished Aug 08 05:24:12 PM PDT 24
Peak memory 213592 kb
Host smart-0d929786-85d5-4d3c-a420-d2a459513feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889009013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3889009013
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.189786848
Short name T209
Test name
Test status
Simulation time 2049973088 ps
CPU time 3.45 seconds
Started Aug 08 05:24:01 PM PDT 24
Finished Aug 08 05:24:04 PM PDT 24
Peak memory 205496 kb
Host smart-21f293a5-945d-4ee9-9f6b-5f674d77ede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189786848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.189786848
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3047303901
Short name T46
Test name
Test status
Simulation time 4881864412 ps
CPU time 13.67 seconds
Started Aug 08 05:24:06 PM PDT 24
Finished Aug 08 05:24:19 PM PDT 24
Peak memory 213544 kb
Host smart-91c53ac4-cf60-4b62-8661-7bfbf6c17ac5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047303901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3047303901
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3098557704
Short name T275
Test name
Test status
Simulation time 6489369054 ps
CPU time 19.16 seconds
Started Aug 08 05:24:04 PM PDT 24
Finished Aug 08 05:24:24 PM PDT 24
Peak memory 213560 kb
Host smart-ce2e94a6-856e-4025-84b7-0389ff28001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098557704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3098557704
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.930680904
Short name T288
Test name
Test status
Simulation time 2255168163 ps
CPU time 2.58 seconds
Started Aug 08 05:24:06 PM PDT 24
Finished Aug 08 05:24:08 PM PDT 24
Peak memory 213384 kb
Host smart-20388df4-c385-45d3-8a83-a7a14cb2784c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930680904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.930680904
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1981263300
Short name T285
Test name
Test status
Simulation time 93744959 ps
CPU time 0.89 seconds
Started Aug 08 05:24:17 PM PDT 24
Finished Aug 08 05:24:18 PM PDT 24
Peak memory 204928 kb
Host smart-b08a6b9c-9754-446e-802a-05294f2cde8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981263300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1981263300
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3161390495
Short name T276
Test name
Test status
Simulation time 6755839714 ps
CPU time 2.78 seconds
Started Aug 08 05:24:17 PM PDT 24
Finished Aug 08 05:24:20 PM PDT 24
Peak memory 205360 kb
Host smart-491b328d-712d-4fd7-b4a7-a35449fb3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161390495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3161390495
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.145153626
Short name T298
Test name
Test status
Simulation time 1915204445 ps
CPU time 6.67 seconds
Started Aug 08 05:24:14 PM PDT 24
Finished Aug 08 05:24:21 PM PDT 24
Peak memory 213628 kb
Host smart-e8a2c207-fbf4-45e6-873b-73ffd7e0c8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145153626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.145153626
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.116029183
Short name T212
Test name
Test status
Simulation time 6861206658 ps
CPU time 6.41 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:19 PM PDT 24
Peak memory 213596 kb
Host smart-ab04d4cf-e126-4ce9-9270-ff4d1e738f8b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116029183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.116029183
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1846149009
Short name T269
Test name
Test status
Simulation time 4565091997 ps
CPU time 8.34 seconds
Started Aug 08 05:24:03 PM PDT 24
Finished Aug 08 05:24:11 PM PDT 24
Peak memory 213628 kb
Host smart-351f782b-0aa6-4bd5-8400-4c1166c4d555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846149009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1846149009
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3271076221
Short name T135
Test name
Test status
Simulation time 4023779329 ps
CPU time 12.55 seconds
Started Aug 08 05:24:11 PM PDT 24
Finished Aug 08 05:24:24 PM PDT 24
Peak memory 213368 kb
Host smart-f7078e91-af9e-4971-a49b-232ce5d05cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271076221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3271076221
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2773331689
Short name T282
Test name
Test status
Simulation time 168891249 ps
CPU time 0.77 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:31 PM PDT 24
Peak memory 204944 kb
Host smart-e63561bf-01b1-4a54-ad87-1ab034f9cf67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773331689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2773331689
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3530690864
Short name T157
Test name
Test status
Simulation time 68669810878 ps
CPU time 179.29 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:26:21 PM PDT 24
Peak memory 214780 kb
Host smart-a92b9282-895e-49d3-87cb-d006843c00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530690864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3530690864
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.665156851
Short name T179
Test name
Test status
Simulation time 12649919174 ps
CPU time 19.73 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:42 PM PDT 24
Peak memory 215372 kb
Host smart-163604eb-eb4d-4537-9489-c0698c65874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665156851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.665156851
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4067212899
Short name T140
Test name
Test status
Simulation time 13446652664 ps
CPU time 21.94 seconds
Started Aug 08 05:23:24 PM PDT 24
Finished Aug 08 05:23:46 PM PDT 24
Peak memory 213592 kb
Host smart-73a643b8-e77d-40a7-ae25-e0b90c47696b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067212899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.4067212899
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1120617448
Short name T33
Test name
Test status
Simulation time 1496748506 ps
CPU time 4.91 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:27 PM PDT 24
Peak memory 204948 kb
Host smart-4a528132-9f89-4e69-98c9-9f50125912ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120617448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1120617448
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.241616574
Short name T227
Test name
Test status
Simulation time 430177796 ps
CPU time 1 seconds
Started Aug 08 05:23:23 PM PDT 24
Finished Aug 08 05:23:24 PM PDT 24
Peak memory 204904 kb
Host smart-2f00117c-25cd-4b06-8bcf-3e2e427401ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241616574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.241616574
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3196199133
Short name T154
Test name
Test status
Simulation time 3797067419 ps
CPU time 11.2 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:33 PM PDT 24
Peak memory 205384 kb
Host smart-08777ea1-c81d-48e1-8a17-46795ddc6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196199133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3196199133
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1879773002
Short name T155
Test name
Test status
Simulation time 7122764727 ps
CPU time 21.64 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:23:44 PM PDT 24
Peak memory 213488 kb
Host smart-f1c6c464-a395-45b5-af1a-c4fcbd010de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879773002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1879773002
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3921263240
Short name T75
Test name
Test status
Simulation time 19141312428 ps
CPU time 142.15 seconds
Started Aug 08 05:23:22 PM PDT 24
Finished Aug 08 05:25:44 PM PDT 24
Peak memory 221724 kb
Host smart-94ac04fa-26ce-4375-b513-81cfbbf3b6cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921263240 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3921263240
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.4188036506
Short name T39
Test name
Test status
Simulation time 90948423 ps
CPU time 0.75 seconds
Started Aug 08 05:24:12 PM PDT 24
Finished Aug 08 05:24:13 PM PDT 24
Peak memory 204976 kb
Host smart-4c58a5f9-c1d5-49a6-bb82-a2b5fe2cce90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188036506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.4188036506
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1473636104
Short name T65
Test name
Test status
Simulation time 31238325 ps
CPU time 0.78 seconds
Started Aug 08 05:24:12 PM PDT 24
Finished Aug 08 05:24:13 PM PDT 24
Peak memory 204804 kb
Host smart-92a58981-648a-4864-a7b5-199fe5a4dff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473636104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1473636104
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.302543661
Short name T278
Test name
Test status
Simulation time 1740776881 ps
CPU time 4.51 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:17 PM PDT 24
Peak memory 213256 kb
Host smart-6ffd075f-72ae-4a59-b242-b6172ee56fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302543661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.302543661
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.868926069
Short name T207
Test name
Test status
Simulation time 65647686 ps
CPU time 0.74 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:14 PM PDT 24
Peak memory 204928 kb
Host smart-669f3505-8601-44e8-988f-16c0a61fea42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868926069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.868926069
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.537910945
Short name T289
Test name
Test status
Simulation time 3165951926 ps
CPU time 3.26 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:17 PM PDT 24
Peak memory 213516 kb
Host smart-273a20a0-012e-46f6-a359-f1faef0c3aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537910945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.537910945
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3596258988
Short name T68
Test name
Test status
Simulation time 87308082 ps
CPU time 0.8 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:14 PM PDT 24
Peak memory 204980 kb
Host smart-613b62aa-168f-4ae5-9fd6-b648e131f2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596258988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3596258988
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.4186116165
Short name T197
Test name
Test status
Simulation time 1147656980 ps
CPU time 2.44 seconds
Started Aug 08 05:24:16 PM PDT 24
Finished Aug 08 05:24:19 PM PDT 24
Peak memory 204840 kb
Host smart-cea9d2fe-85d0-4b65-84c8-365ecadc7806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186116165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.4186116165
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2611740452
Short name T262
Test name
Test status
Simulation time 89168380 ps
CPU time 0.75 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:14 PM PDT 24
Peak memory 204964 kb
Host smart-d7d0f47b-7a42-4959-ad7e-1dbd874a1bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611740452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2611740452
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.32042827
Short name T69
Test name
Test status
Simulation time 103787691 ps
CPU time 0.84 seconds
Started Aug 08 05:24:17 PM PDT 24
Finished Aug 08 05:24:18 PM PDT 24
Peak memory 204916 kb
Host smart-a793cc7d-2d0f-4795-a241-5e9649e9cd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32042827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.32042827
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.275149459
Short name T265
Test name
Test status
Simulation time 5715253398 ps
CPU time 4.53 seconds
Started Aug 08 05:24:14 PM PDT 24
Finished Aug 08 05:24:18 PM PDT 24
Peak memory 213384 kb
Host smart-1b590206-38fa-451c-9161-0c7c23b07440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275149459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.275149459
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1315995347
Short name T248
Test name
Test status
Simulation time 123508111 ps
CPU time 0.72 seconds
Started Aug 08 05:24:14 PM PDT 24
Finished Aug 08 05:24:14 PM PDT 24
Peak memory 204964 kb
Host smart-45180ed9-13ae-4901-99bc-5c4e9e807430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315995347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1315995347
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1742061229
Short name T271
Test name
Test status
Simulation time 1851279976 ps
CPU time 1.66 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:15 PM PDT 24
Peak memory 205104 kb
Host smart-c963066e-e6ad-4210-ad90-8b2c673a624a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742061229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1742061229
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3325562836
Short name T254
Test name
Test status
Simulation time 102256695 ps
CPU time 0.73 seconds
Started Aug 08 05:24:17 PM PDT 24
Finished Aug 08 05:24:17 PM PDT 24
Peak memory 204868 kb
Host smart-4354ed45-09b7-4fea-bdb0-3b11036b860d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325562836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3325562836
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.467697649
Short name T18
Test name
Test status
Simulation time 2264621074 ps
CPU time 6.74 seconds
Started Aug 08 05:24:12 PM PDT 24
Finished Aug 08 05:24:19 PM PDT 24
Peak memory 213472 kb
Host smart-b2d784dd-b6a1-45af-965d-df201980263f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467697649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.467697649
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1903629970
Short name T187
Test name
Test status
Simulation time 35786417 ps
CPU time 0.77 seconds
Started Aug 08 05:24:16 PM PDT 24
Finished Aug 08 05:24:17 PM PDT 24
Peak memory 204928 kb
Host smart-98272ad2-8d18-4acb-bf35-ae6510e56acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903629970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1903629970
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.417421129
Short name T284
Test name
Test status
Simulation time 35681409 ps
CPU time 0.78 seconds
Started Aug 08 05:24:24 PM PDT 24
Finished Aug 08 05:24:25 PM PDT 24
Peak memory 204872 kb
Host smart-f1e35772-e766-450f-b4fe-5b215965416e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417421129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.417421129
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2734019507
Short name T272
Test name
Test status
Simulation time 1436843225 ps
CPU time 4.15 seconds
Started Aug 08 05:24:13 PM PDT 24
Finished Aug 08 05:24:17 PM PDT 24
Peak memory 204924 kb
Host smart-21aee9b5-c6eb-42b2-bc34-5b62fbf4ff99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734019507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2734019507
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2394218108
Short name T183
Test name
Test status
Simulation time 135083593 ps
CPU time 0.78 seconds
Started Aug 08 05:23:31 PM PDT 24
Finished Aug 08 05:23:32 PM PDT 24
Peak memory 204936 kb
Host smart-5a4cee22-ee4b-4a9f-ba9a-bab8a1f30b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394218108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2394218108
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1539902253
Short name T72
Test name
Test status
Simulation time 15844511326 ps
CPU time 13.35 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:43 PM PDT 24
Peak memory 213576 kb
Host smart-92e6f520-0e95-48b9-a333-4a35fd9de0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539902253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1539902253
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1102482562
Short name T188
Test name
Test status
Simulation time 7065067461 ps
CPU time 3.5 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:34 PM PDT 24
Peak memory 213632 kb
Host smart-6e824101-92a7-4598-9d31-182be9c5606b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102482562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1102482562
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.2519502367
Short name T223
Test name
Test status
Simulation time 237658945 ps
CPU time 1.08 seconds
Started Aug 08 05:23:31 PM PDT 24
Finished Aug 08 05:23:32 PM PDT 24
Peak memory 204872 kb
Host smart-92cb9822-bdcd-49c6-a9a8-b7842c00dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519502367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2519502367
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1892017955
Short name T151
Test name
Test status
Simulation time 1151294198 ps
CPU time 1 seconds
Started Aug 08 05:23:32 PM PDT 24
Finished Aug 08 05:23:33 PM PDT 24
Peak memory 204952 kb
Host smart-eb8879f5-0f84-42fd-943c-5bba1fa6b01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892017955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1892017955
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.37385050
Short name T292
Test name
Test status
Simulation time 3605268921 ps
CPU time 5.57 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:36 PM PDT 24
Peak memory 205468 kb
Host smart-c2748f9a-d953-4b75-b3a4-9e8c93e4810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37385050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.37385050
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.876755065
Short name T41
Test name
Test status
Simulation time 402891193 ps
CPU time 1.64 seconds
Started Aug 08 05:23:31 PM PDT 24
Finished Aug 08 05:23:33 PM PDT 24
Peak memory 229692 kb
Host smart-07a466c5-2034-4926-bfe9-c789060b56f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876755065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.876755065
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1234505246
Short name T156
Test name
Test status
Simulation time 3504158591 ps
CPU time 3.85 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:34 PM PDT 24
Peak memory 213408 kb
Host smart-9e3b1285-9bbb-4a78-88a6-a95051b588db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234505246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1234505246
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.133797065
Short name T115
Test name
Test status
Simulation time 100562320 ps
CPU time 0.73 seconds
Started Aug 08 05:24:21 PM PDT 24
Finished Aug 08 05:24:22 PM PDT 24
Peak memory 204988 kb
Host smart-312a9d03-54f0-4c79-909f-ca9404fb4eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133797065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.133797065
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.900222177
Short name T9
Test name
Test status
Simulation time 7995578060 ps
CPU time 4.02 seconds
Started Aug 08 05:24:24 PM PDT 24
Finished Aug 08 05:24:28 PM PDT 24
Peak memory 213500 kb
Host smart-9a3248f7-1e0f-4413-8990-894634694cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900222177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.900222177
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3199107634
Short name T239
Test name
Test status
Simulation time 130122713 ps
CPU time 0.71 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:23 PM PDT 24
Peak memory 204900 kb
Host smart-b9e106c7-e11c-478b-bb6e-72de2dfa6bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199107634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3199107634
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.132292812
Short name T158
Test name
Test status
Simulation time 1505469328 ps
CPU time 1.42 seconds
Started Aug 08 05:24:24 PM PDT 24
Finished Aug 08 05:24:25 PM PDT 24
Peak memory 213332 kb
Host smart-fa07755d-f676-4a36-a33e-ba027ad914d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132292812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.132292812
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1992418502
Short name T194
Test name
Test status
Simulation time 244407121 ps
CPU time 0.72 seconds
Started Aug 08 05:24:22 PM PDT 24
Finished Aug 08 05:24:23 PM PDT 24
Peak memory 204956 kb
Host smart-e02129ad-e7b8-4e7c-aa17-e85125847ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992418502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1992418502
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2452236718
Short name T224
Test name
Test status
Simulation time 2185594350 ps
CPU time 1.99 seconds
Started Aug 08 05:24:22 PM PDT 24
Finished Aug 08 05:24:24 PM PDT 24
Peak memory 213352 kb
Host smart-37080465-0f7c-4bcd-b11e-0979a85eadc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452236718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2452236718
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.4204543828
Short name T296
Test name
Test status
Simulation time 86132012 ps
CPU time 0.79 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:23 PM PDT 24
Peak memory 204932 kb
Host smart-4f23b8e1-e266-4464-957b-c0acb629e04f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204543828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4204543828
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.984362465
Short name T34
Test name
Test status
Simulation time 4934842505 ps
CPU time 4.07 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:27 PM PDT 24
Peak memory 213388 kb
Host smart-069653de-ea8f-4f1c-9bd5-6617676463e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984362465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.984362465
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.80581029
Short name T228
Test name
Test status
Simulation time 40653034 ps
CPU time 0.75 seconds
Started Aug 08 05:24:25 PM PDT 24
Finished Aug 08 05:24:26 PM PDT 24
Peak memory 204872 kb
Host smart-8061310d-fe96-4c3b-acdf-6e0b95940559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80581029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.80581029
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3000312906
Short name T299
Test name
Test status
Simulation time 6738580376 ps
CPU time 6.17 seconds
Started Aug 08 05:24:22 PM PDT 24
Finished Aug 08 05:24:29 PM PDT 24
Peak memory 213396 kb
Host smart-9d467fca-43c3-4fdc-87f4-88bda55ff9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000312906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3000312906
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4113349914
Short name T66
Test name
Test status
Simulation time 82835461 ps
CPU time 0.78 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:24 PM PDT 24
Peak memory 204956 kb
Host smart-cc346162-45da-4490-8b14-82516e125d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113349914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4113349914
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2507495226
Short name T142
Test name
Test status
Simulation time 3065727003 ps
CPU time 2.24 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:25 PM PDT 24
Peak memory 213420 kb
Host smart-15f8a8ff-adcc-4b89-bc64-3a0fff65536d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507495226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2507495226
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.341781535
Short name T177
Test name
Test status
Simulation time 81249286 ps
CPU time 0.81 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:24 PM PDT 24
Peak memory 204964 kb
Host smart-1876c96b-087d-4c27-b812-b0f676f72134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341781535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.341781535
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1623126446
Short name T258
Test name
Test status
Simulation time 3676243688 ps
CPU time 4.22 seconds
Started Aug 08 05:24:22 PM PDT 24
Finished Aug 08 05:24:27 PM PDT 24
Peak memory 213492 kb
Host smart-dd0bc121-49a6-47b3-a92b-dafa52d527f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623126446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1623126446
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2990309895
Short name T214
Test name
Test status
Simulation time 109859860 ps
CPU time 0.7 seconds
Started Aug 08 05:24:22 PM PDT 24
Finished Aug 08 05:24:23 PM PDT 24
Peak memory 204860 kb
Host smart-f2bb649c-de1d-43d5-a76e-d069628ae36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990309895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2990309895
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1245227817
Short name T137
Test name
Test status
Simulation time 2209632808 ps
CPU time 2.44 seconds
Started Aug 08 05:24:23 PM PDT 24
Finished Aug 08 05:24:25 PM PDT 24
Peak memory 213388 kb
Host smart-0b585921-b841-4754-a067-7aad3900943a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245227817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1245227817
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.106871578
Short name T221
Test name
Test status
Simulation time 60487871 ps
CPU time 0.82 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:32 PM PDT 24
Peak memory 204924 kb
Host smart-ba69fa2d-e139-4956-8a52-9711c9fb302d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106871578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.106871578
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1772905959
Short name T270
Test name
Test status
Simulation time 9523648664 ps
CPU time 6.7 seconds
Started Aug 08 05:24:21 PM PDT 24
Finished Aug 08 05:24:28 PM PDT 24
Peak memory 205416 kb
Host smart-5f4a2011-362d-474a-9370-74b5ede9a20d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772905959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1772905959
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.650864832
Short name T180
Test name
Test status
Simulation time 162239717 ps
CPU time 0.8 seconds
Started Aug 08 05:24:32 PM PDT 24
Finished Aug 08 05:24:33 PM PDT 24
Peak memory 204968 kb
Host smart-e404386b-6ffe-4ca2-a7ad-2c5649c40f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650864832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.650864832
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.674962292
Short name T136
Test name
Test status
Simulation time 3743774847 ps
CPU time 11.5 seconds
Started Aug 08 05:24:37 PM PDT 24
Finished Aug 08 05:24:48 PM PDT 24
Peak memory 213388 kb
Host smart-c406ee07-2cda-498e-bd16-1f3de087f638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674962292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.674962292
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3768994672
Short name T295
Test name
Test status
Simulation time 41121646 ps
CPU time 0.78 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:46 PM PDT 24
Peak memory 204840 kb
Host smart-3b1052b6-3bbe-404b-a813-1cf8f8ed34ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768994672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3768994672
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3006519255
Short name T246
Test name
Test status
Simulation time 161942284219 ps
CPU time 231.49 seconds
Started Aug 08 05:23:32 PM PDT 24
Finished Aug 08 05:27:23 PM PDT 24
Peak memory 221860 kb
Host smart-4b99474f-9f66-489d-a104-68bef9a9a114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006519255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3006519255
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3492897969
Short name T178
Test name
Test status
Simulation time 7200047972 ps
CPU time 6.42 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:37 PM PDT 24
Peak memory 213756 kb
Host smart-71802dc0-43ac-4672-9f90-09ef4f72b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492897969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3492897969
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1615112377
Short name T138
Test name
Test status
Simulation time 5275819058 ps
CPU time 8.5 seconds
Started Aug 08 05:23:34 PM PDT 24
Finished Aug 08 05:23:43 PM PDT 24
Peak memory 205704 kb
Host smart-c06480fe-8cdb-4dfb-9db6-3e5f6d8ee7e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615112377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1615112377
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.890991716
Short name T204
Test name
Test status
Simulation time 829487692 ps
CPU time 2.66 seconds
Started Aug 08 05:23:29 PM PDT 24
Finished Aug 08 05:23:32 PM PDT 24
Peak memory 204896 kb
Host smart-cf06086a-908a-4672-80ff-195b2e07733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890991716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.890991716
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.810303256
Short name T200
Test name
Test status
Simulation time 196624874 ps
CPU time 1.08 seconds
Started Aug 08 05:23:32 PM PDT 24
Finished Aug 08 05:23:34 PM PDT 24
Peak memory 204876 kb
Host smart-6a1b792e-1d9b-4913-a2c7-5833ffdfb3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810303256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.810303256
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.607804448
Short name T303
Test name
Test status
Simulation time 2743852407 ps
CPU time 2.88 seconds
Started Aug 08 05:23:30 PM PDT 24
Finished Aug 08 05:23:33 PM PDT 24
Peak memory 205464 kb
Host smart-4b903173-e0a4-437c-bcb6-8e8866dc8159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607804448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.607804448
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2363473148
Short name T62
Test name
Test status
Simulation time 736961833 ps
CPU time 1.48 seconds
Started Aug 08 05:23:46 PM PDT 24
Finished Aug 08 05:23:48 PM PDT 24
Peak memory 229212 kb
Host smart-1b129f4b-5ea8-4fb8-ab58-9bc04cf80b4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363473148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2363473148
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2260157530
Short name T48
Test name
Test status
Simulation time 52319295962 ps
CPU time 426.19 seconds
Started Aug 08 05:23:46 PM PDT 24
Finished Aug 08 05:30:53 PM PDT 24
Peak memory 224380 kb
Host smart-50491968-db19-4679-8c85-b7c44663ca6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260157530 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2260157530
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3984614735
Short name T116
Test name
Test status
Simulation time 156156030 ps
CPU time 0.81 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:32 PM PDT 24
Peak memory 205008 kb
Host smart-cb9ae496-7129-4591-98d4-fe5fdb8bee81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984614735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3984614735
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2725742811
Short name T70
Test name
Test status
Simulation time 7786640680 ps
CPU time 14.79 seconds
Started Aug 08 05:24:32 PM PDT 24
Finished Aug 08 05:24:47 PM PDT 24
Peak memory 213428 kb
Host smart-27dcd00b-139d-4a98-83c8-1bdece365610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725742811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2725742811
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.191587885
Short name T113
Test name
Test status
Simulation time 92328617 ps
CPU time 0.94 seconds
Started Aug 08 05:24:34 PM PDT 24
Finished Aug 08 05:24:35 PM PDT 24
Peak memory 204884 kb
Host smart-411e3acb-17f5-4737-987e-dbc63af4de0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191587885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.191587885
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.317644388
Short name T27
Test name
Test status
Simulation time 185130770 ps
CPU time 1 seconds
Started Aug 08 05:24:33 PM PDT 24
Finished Aug 08 05:24:34 PM PDT 24
Peak memory 204944 kb
Host smart-c7fe0c9f-0dc8-4196-b1c9-e1e3d53f5e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317644388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.317644388
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1691641544
Short name T162
Test name
Test status
Simulation time 3214381079 ps
CPU time 5.55 seconds
Started Aug 08 05:24:34 PM PDT 24
Finished Aug 08 05:24:40 PM PDT 24
Peak memory 213432 kb
Host smart-dae4b948-7845-45b7-ba3c-ced3873ccccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691641544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1691641544
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1649145524
Short name T225
Test name
Test status
Simulation time 126589205 ps
CPU time 0.74 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:32 PM PDT 24
Peak memory 204904 kb
Host smart-c5e78a5e-6a1a-46c0-9851-f5c9db2bd674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649145524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1649145524
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3139788511
Short name T19
Test name
Test status
Simulation time 3095208293 ps
CPU time 2.02 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:33 PM PDT 24
Peak memory 213308 kb
Host smart-1d01a435-0b13-4b88-8fea-88b914422b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139788511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3139788511
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1553677179
Short name T52
Test name
Test status
Simulation time 32493699 ps
CPU time 0.8 seconds
Started Aug 08 05:24:32 PM PDT 24
Finished Aug 08 05:24:33 PM PDT 24
Peak memory 204952 kb
Host smart-feef991c-56b3-4cd7-902f-a9f08cebc6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553677179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1553677179
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1436404326
Short name T10
Test name
Test status
Simulation time 3044512535 ps
CPU time 9.24 seconds
Started Aug 08 05:24:32 PM PDT 24
Finished Aug 08 05:24:41 PM PDT 24
Peak memory 205268 kb
Host smart-319f10a3-d029-45c2-9986-bf4474ab4b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436404326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1436404326
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2840385051
Short name T236
Test name
Test status
Simulation time 264456502 ps
CPU time 0.75 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:32 PM PDT 24
Peak memory 204928 kb
Host smart-1b21d1a4-3c89-4d8b-91e8-aeae0c049bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840385051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2840385051
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3586590958
Short name T203
Test name
Test status
Simulation time 52491307 ps
CPU time 0.78 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:32 PM PDT 24
Peak memory 204944 kb
Host smart-77982666-4b91-4bae-81e0-79c8ebc647ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586590958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3586590958
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.4081163918
Short name T35
Test name
Test status
Simulation time 2141673335 ps
CPU time 4.5 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:35 PM PDT 24
Peak memory 213388 kb
Host smart-aa9644a3-18a7-416d-9d2f-ec36b346d35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081163918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.4081163918
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3063026125
Short name T267
Test name
Test status
Simulation time 95554627 ps
CPU time 0.77 seconds
Started Aug 08 05:24:33 PM PDT 24
Finished Aug 08 05:24:34 PM PDT 24
Peak memory 204900 kb
Host smart-97fb16df-8188-44d2-8e17-8c4293b75e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063026125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3063026125
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2528644237
Short name T150
Test name
Test status
Simulation time 4599054959 ps
CPU time 4.77 seconds
Started Aug 08 05:24:33 PM PDT 24
Finished Aug 08 05:24:38 PM PDT 24
Peak memory 213448 kb
Host smart-a84ba309-ae31-429e-b6a8-a4ad9b8a8dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528644237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2528644237
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2068953893
Short name T181
Test name
Test status
Simulation time 156394790 ps
CPU time 0.75 seconds
Started Aug 08 05:24:34 PM PDT 24
Finished Aug 08 05:24:35 PM PDT 24
Peak memory 204948 kb
Host smart-2c43c7ce-03a3-4978-a2fc-28c17e511d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068953893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2068953893
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.4153245621
Short name T291
Test name
Test status
Simulation time 5003606994 ps
CPU time 4.06 seconds
Started Aug 08 05:24:31 PM PDT 24
Finished Aug 08 05:24:35 PM PDT 24
Peak memory 205452 kb
Host smart-05ef1496-bee4-45ac-bece-1e4bd0ce4f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153245621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.4153245621
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3234349415
Short name T191
Test name
Test status
Simulation time 28152736 ps
CPU time 0.74 seconds
Started Aug 08 05:24:32 PM PDT 24
Finished Aug 08 05:24:33 PM PDT 24
Peak memory 204828 kb
Host smart-ffb11d15-1912-49f5-9280-15775c76f433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234349415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3234349415
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3175313913
Short name T229
Test name
Test status
Simulation time 74053329 ps
CPU time 0.86 seconds
Started Aug 08 05:23:46 PM PDT 24
Finished Aug 08 05:23:47 PM PDT 24
Peak memory 204968 kb
Host smart-c9a6b10e-8012-4187-bed1-7e6dde92bbdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175313913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3175313913
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3272019639
Short name T215
Test name
Test status
Simulation time 10617891640 ps
CPU time 10.12 seconds
Started Aug 08 05:23:46 PM PDT 24
Finished Aug 08 05:23:56 PM PDT 24
Peak memory 213576 kb
Host smart-35806c26-e452-40fc-9d96-1059f553e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272019639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3272019639
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3623726679
Short name T300
Test name
Test status
Simulation time 6181691415 ps
CPU time 7.35 seconds
Started Aug 08 05:23:44 PM PDT 24
Finished Aug 08 05:23:52 PM PDT 24
Peak memory 214624 kb
Host smart-e229a68d-76b4-4226-9931-719e96ec7fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623726679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3623726679
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.585721050
Short name T71
Test name
Test status
Simulation time 3970023480 ps
CPU time 4.64 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:50 PM PDT 24
Peak memory 213556 kb
Host smart-c9ee5f8f-1864-4208-b4f8-4b0cc275c460
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585721050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.585721050
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2676865143
Short name T222
Test name
Test status
Simulation time 326937540 ps
CPU time 1.71 seconds
Started Aug 08 05:23:46 PM PDT 24
Finished Aug 08 05:23:48 PM PDT 24
Peak memory 204900 kb
Host smart-c0e1d778-024a-4254-82a4-a3637eb57e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676865143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2676865143
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1236154656
Short name T147
Test name
Test status
Simulation time 1788366274 ps
CPU time 4.64 seconds
Started Aug 08 05:23:47 PM PDT 24
Finished Aug 08 05:23:52 PM PDT 24
Peak memory 213336 kb
Host smart-9983deb5-385b-48f7-aa45-10dff7b1aa2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236154656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1236154656
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2069278601
Short name T261
Test name
Test status
Simulation time 72655310 ps
CPU time 0.81 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:46 PM PDT 24
Peak memory 204832 kb
Host smart-ce5114b0-0ca1-461b-b5f8-803040c540a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069278601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2069278601
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1870972484
Short name T274
Test name
Test status
Simulation time 4146139581 ps
CPU time 6.32 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:52 PM PDT 24
Peak memory 205408 kb
Host smart-77d99946-f2cc-4891-8a8f-982b9945b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870972484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1870972484
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1770807250
Short name T59
Test name
Test status
Simulation time 1496361033 ps
CPU time 3.29 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:48 PM PDT 24
Peak memory 205304 kb
Host smart-620ce1ca-bf5e-4277-bec6-e64af7e523c7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770807250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1770807250
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3013511368
Short name T67
Test name
Test status
Simulation time 260033103 ps
CPU time 1.26 seconds
Started Aug 08 05:23:48 PM PDT 24
Finished Aug 08 05:23:49 PM PDT 24
Peak memory 204952 kb
Host smart-05534fea-375b-4dc3-b54e-213040bd0b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013511368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3013511368
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.539270312
Short name T89
Test name
Test status
Simulation time 4364570307 ps
CPU time 4.05 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:49 PM PDT 24
Peak memory 205488 kb
Host smart-3090f201-94fe-4461-870c-58dfec6c0e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539270312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.539270312
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1508969960
Short name T302
Test name
Test status
Simulation time 7093707448 ps
CPU time 20.65 seconds
Started Aug 08 05:23:46 PM PDT 24
Finished Aug 08 05:24:07 PM PDT 24
Peak memory 205244 kb
Host smart-e4d948b0-8924-4704-937e-ae6fab79e0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508969960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1508969960
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3075221567
Short name T218
Test name
Test status
Simulation time 39674818 ps
CPU time 0.78 seconds
Started Aug 08 05:23:51 PM PDT 24
Finished Aug 08 05:23:52 PM PDT 24
Peak memory 204868 kb
Host smart-1d366dee-2e2e-4bdf-a998-6e6bc34bdd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075221567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3075221567
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3779933789
Short name T26
Test name
Test status
Simulation time 3287073919 ps
CPU time 3.29 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 05:23:55 PM PDT 24
Peak memory 213584 kb
Host smart-3ef00341-375e-42ae-8ac5-62b0663a4d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779933789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3779933789
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3387154917
Short name T148
Test name
Test status
Simulation time 1116858896 ps
CPU time 2.53 seconds
Started Aug 08 05:23:56 PM PDT 24
Finished Aug 08 05:23:59 PM PDT 24
Peak memory 205360 kb
Host smart-ee25d1ae-0495-4320-b40b-86a8bdbfdd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387154917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3387154917
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2489679119
Short name T297
Test name
Test status
Simulation time 2137650560 ps
CPU time 7.29 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:53 PM PDT 24
Peak memory 213560 kb
Host smart-5425bfd3-f3e5-4b48-9b5d-a6d4f4a89a82
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489679119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2489679119
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.3852040113
Short name T249
Test name
Test status
Simulation time 640650424 ps
CPU time 1.6 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:55 PM PDT 24
Peak memory 204836 kb
Host smart-6fb3037e-a4d9-44c7-8e4e-6321cd2ceaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852040113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3852040113
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3187303033
Short name T127
Test name
Test status
Simulation time 7647002541 ps
CPU time 4.13 seconds
Started Aug 08 05:23:45 PM PDT 24
Finished Aug 08 05:23:49 PM PDT 24
Peak memory 205448 kb
Host smart-dcfb1ff9-656f-48d7-b628-7fb337e4dcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187303033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3187303033
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.142838263
Short name T118
Test name
Test status
Simulation time 2530112648 ps
CPU time 2.77 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:56 PM PDT 24
Peak memory 213428 kb
Host smart-70f2bef4-20d9-431c-982f-745a1b9db109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142838263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.142838263
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.387208033
Short name T17
Test name
Test status
Simulation time 40586055605 ps
CPU time 908.07 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:39:03 PM PDT 24
Peak memory 232372 kb
Host smart-168f6e16-ad78-44b5-9d19-f32e44c72db7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387208033 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.387208033
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3200545666
Short name T263
Test name
Test status
Simulation time 139169867 ps
CPU time 1.16 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:55 PM PDT 24
Peak memory 204988 kb
Host smart-4492ec60-f35c-4aa1-a437-095056e16256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200545666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3200545666
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.838461391
Short name T252
Test name
Test status
Simulation time 154470644054 ps
CPU time 402.59 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:30:36 PM PDT 24
Peak memory 220832 kb
Host smart-2e46ed02-0ec7-412a-811a-60c02e36644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838461391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.838461391
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.266452284
Short name T126
Test name
Test status
Simulation time 2981833898 ps
CPU time 3.22 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:57 PM PDT 24
Peak memory 205372 kb
Host smart-be754d3e-fb13-4400-bfcc-3ad269d1afa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266452284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.266452284
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3354827618
Short name T213
Test name
Test status
Simulation time 2486741340 ps
CPU time 4.88 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 213572 kb
Host smart-da966f64-00ca-4335-8e93-a2dbfaa15241
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354827618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3354827618
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3472083697
Short name T160
Test name
Test status
Simulation time 3870861587 ps
CPU time 5.63 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 05:23:57 PM PDT 24
Peak memory 205348 kb
Host smart-dc07a785-1c8f-4b94-8e33-c501ecebd352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472083697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3472083697
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3180424791
Short name T152
Test name
Test status
Simulation time 4512303352 ps
CPU time 12.18 seconds
Started Aug 08 05:23:55 PM PDT 24
Finished Aug 08 05:24:08 PM PDT 24
Peak memory 213404 kb
Host smart-3de84250-421f-4fca-990c-1b400efc9226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180424791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3180424791
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.928685163
Short name T12
Test name
Test status
Simulation time 381591722720 ps
CPU time 2210.95 seconds
Started Aug 08 05:23:52 PM PDT 24
Finished Aug 08 06:00:44 PM PDT 24
Peak memory 258996 kb
Host smart-25e6ad42-1b2d-48df-b089-7b1f37f12741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928685163 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.928685163
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3955159907
Short name T182
Test name
Test status
Simulation time 110655867 ps
CPU time 0.93 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 05:23:55 PM PDT 24
Peak memory 204944 kb
Host smart-02df9752-90f7-4c90-8e51-7db21591e948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955159907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3955159907
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2039293390
Short name T243
Test name
Test status
Simulation time 4029948569 ps
CPU time 4.56 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:58 PM PDT 24
Peak memory 213600 kb
Host smart-966e5363-409c-428c-969c-2009277ad082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039293390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2039293390
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2826417452
Short name T134
Test name
Test status
Simulation time 4188195966 ps
CPU time 13.39 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:24:06 PM PDT 24
Peak memory 213564 kb
Host smart-c9d8d695-8ade-475f-a97b-dd7581d61c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826417452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2826417452
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3417859231
Short name T60
Test name
Test status
Simulation time 894705373 ps
CPU time 3.42 seconds
Started Aug 08 05:23:53 PM PDT 24
Finished Aug 08 05:23:57 PM PDT 24
Peak memory 205248 kb
Host smart-a0a14616-942a-4d8b-a437-2ecfe52b1381
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417859231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3417859231
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1996448102
Short name T260
Test name
Test status
Simulation time 1281359717 ps
CPU time 3.88 seconds
Started Aug 08 05:23:57 PM PDT 24
Finished Aug 08 05:24:01 PM PDT 24
Peak memory 213500 kb
Host smart-264d417e-5d92-496e-8fb0-5e6d4a8801f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996448102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1996448102
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1359190738
Short name T145
Test name
Test status
Simulation time 5730686949 ps
CPU time 11.54 seconds
Started Aug 08 05:23:54 PM PDT 24
Finished Aug 08 05:24:06 PM PDT 24
Peak memory 213416 kb
Host smart-6ad7ae3c-36a2-461d-a185-117a05c3a97f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359190738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1359190738
Directory /workspace/9.rv_dm_stress_all/latest
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