SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
84.69 | 96.32 | 86.85 | 92.10 | 72.50 | 90.44 | 98.32 | 56.31 |
T63 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3893033608 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:11 PM PDT 24 | 484335391 ps | ||
T314 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1801716417 | Aug 10 05:02:39 PM PDT 24 | Aug 10 05:08:33 PM PDT 24 | 127814492432 ps | ||
T315 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3079005535 | Aug 10 05:02:38 PM PDT 24 | Aug 10 05:02:43 PM PDT 24 | 3154112415 ps | ||
T82 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2904394146 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:16 PM PDT 24 | 2830948606 ps | ||
T75 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1221220714 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:38 PM PDT 24 | 274047913 ps | ||
T83 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3326948565 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:24 PM PDT 24 | 161588056 ps | ||
T90 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1947648827 | Aug 10 05:02:44 PM PDT 24 | Aug 10 05:03:05 PM PDT 24 | 2164294855 ps | ||
T76 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1301604025 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:54 PM PDT 24 | 2792594320 ps | ||
T77 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2027551451 | Aug 10 05:02:36 PM PDT 24 | Aug 10 05:02:48 PM PDT 24 | 2764681354 ps | ||
T316 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3905988644 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:03:02 PM PDT 24 | 10109380647 ps | ||
T78 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1898525371 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:42 PM PDT 24 | 233736483 ps | ||
T84 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.86032444 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 230946939 ps | ||
T85 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1595393708 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:07 PM PDT 24 | 75407159 ps | ||
T64 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3327612480 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:24 PM PDT 24 | 169010248 ps | ||
T86 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1173355549 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:03:27 PM PDT 24 | 56638649915 ps | ||
T317 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.896842019 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:45 PM PDT 24 | 91262208208 ps | ||
T79 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2212644345 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:41 PM PDT 24 | 3321883489 ps | ||
T318 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.724827483 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 5562405322 ps | ||
T93 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3422298715 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 3844829863 ps | ||
T319 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2419607890 | Aug 10 05:02:30 PM PDT 24 | Aug 10 05:02:31 PM PDT 24 | 198260605 ps | ||
T87 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.785642603 | Aug 10 05:02:38 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 9730333768 ps | ||
T88 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4087928364 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 105636146 ps | ||
T91 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1641986882 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 365029312 ps | ||
T320 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1754212284 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:13 PM PDT 24 | 710569142 ps | ||
T321 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.259572879 | Aug 10 05:02:34 PM PDT 24 | Aug 10 05:03:02 PM PDT 24 | 9367411320 ps | ||
T89 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3048377432 | Aug 10 05:02:03 PM PDT 24 | Aug 10 05:02:30 PM PDT 24 | 732848444 ps | ||
T98 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.379103564 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:41 PM PDT 24 | 300538277 ps | ||
T162 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.484263188 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 1606705714 ps | ||
T322 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4082653747 | Aug 10 05:02:03 PM PDT 24 | Aug 10 05:06:16 PM PDT 24 | 92837264550 ps | ||
T323 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3191268803 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:13 PM PDT 24 | 10106887737 ps | ||
T92 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.27602104 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 234502672 ps | ||
T99 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2515716102 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 84793214 ps | ||
T324 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1943756372 | Aug 10 05:02:42 PM PDT 24 | Aug 10 05:02:45 PM PDT 24 | 684348609 ps | ||
T325 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1302750500 | Aug 10 05:02:34 PM PDT 24 | Aug 10 05:02:38 PM PDT 24 | 2183089121 ps | ||
T326 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4128714683 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 234133757 ps | ||
T327 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2839660487 | Aug 10 05:02:32 PM PDT 24 | Aug 10 05:02:33 PM PDT 24 | 422771967 ps | ||
T100 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.494525687 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 307326106 ps | ||
T328 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3603226296 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:03:18 PM PDT 24 | 47449469212 ps | ||
T101 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4075278987 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:03:12 PM PDT 24 | 5168414597 ps | ||
T102 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1878234745 | Aug 10 05:02:24 PM PDT 24 | Aug 10 05:02:26 PM PDT 24 | 231679340 ps | ||
T329 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3351100393 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:13 PM PDT 24 | 5228016289 ps | ||
T122 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1113426981 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:22 PM PDT 24 | 251155687 ps | ||
T330 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.499821674 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 134968483 ps | ||
T110 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.296301184 | Aug 10 05:02:33 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 149927364 ps | ||
T165 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2248230170 | Aug 10 05:02:34 PM PDT 24 | Aug 10 05:02:45 PM PDT 24 | 2729088653 ps | ||
T331 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1370937286 | Aug 10 05:02:45 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 928440202 ps | ||
T332 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3515374675 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:04:14 PM PDT 24 | 87827722094 ps | ||
T333 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3297964437 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 159226075 ps | ||
T334 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1348896974 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:06 PM PDT 24 | 126760041 ps | ||
T335 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2258458045 | Aug 10 05:02:40 PM PDT 24 | Aug 10 05:02:42 PM PDT 24 | 2110116368 ps | ||
T336 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2244171395 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 649607047 ps | ||
T111 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1183169266 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:03:28 PM PDT 24 | 30564445512 ps | ||
T337 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3580644490 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:03:51 PM PDT 24 | 65228251762 ps | ||
T94 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2935512641 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 4970387889 ps | ||
T112 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3500390885 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 309194268 ps | ||
T160 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.801929282 | Aug 10 05:02:40 PM PDT 24 | Aug 10 05:02:51 PM PDT 24 | 1180414278 ps | ||
T123 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2679376433 | Aug 10 05:02:36 PM PDT 24 | Aug 10 05:02:42 PM PDT 24 | 912010063 ps | ||
T338 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2537505710 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 739530734 ps | ||
T339 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3833021557 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:11 PM PDT 24 | 117082028 ps | ||
T340 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3763151443 | Aug 10 05:02:41 PM PDT 24 | Aug 10 05:02:47 PM PDT 24 | 2472499807 ps | ||
T103 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4004694592 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:29 PM PDT 24 | 820560808 ps | ||
T341 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2541676363 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:32 PM PDT 24 | 1466587288 ps | ||
T342 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2300817614 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:07 PM PDT 24 | 120432993 ps | ||
T343 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2323763257 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:41 PM PDT 24 | 281892531 ps | ||
T120 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.624594280 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:29 PM PDT 24 | 203063244 ps | ||
T344 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2377750371 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:28 PM PDT 24 | 19044479521 ps | ||
T345 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1640186676 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:11 PM PDT 24 | 2108868906 ps | ||
T113 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3660813035 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:33 PM PDT 24 | 94490046 ps | ||
T59 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.572887495 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:03:18 PM PDT 24 | 18794395409 ps | ||
T346 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3254102246 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:12 PM PDT 24 | 346280380 ps | ||
T347 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1419112697 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:20 PM PDT 24 | 2274776811 ps | ||
T348 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1892698109 | Aug 10 05:02:36 PM PDT 24 | Aug 10 05:02:44 PM PDT 24 | 3058371868 ps | ||
T349 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.749584882 | Aug 10 05:02:32 PM PDT 24 | Aug 10 05:02:36 PM PDT 24 | 169980750 ps | ||
T114 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2017693432 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:34 PM PDT 24 | 167799887 ps | ||
T350 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2007955858 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:40 PM PDT 24 | 214951297 ps | ||
T115 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1484430022 | Aug 10 05:02:45 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 93754124 ps | ||
T351 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1454479989 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 503822275 ps | ||
T352 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3419101456 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 123012070 ps | ||
T353 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.291341013 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:33 PM PDT 24 | 505977100 ps | ||
T354 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2168130503 | Aug 10 05:02:36 PM PDT 24 | Aug 10 05:02:55 PM PDT 24 | 19250411983 ps | ||
T355 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3943858197 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 347600953 ps | ||
T356 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3839048018 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:14 PM PDT 24 | 9016087906 ps | ||
T169 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.956453298 | Aug 10 05:02:34 PM PDT 24 | Aug 10 05:03:03 PM PDT 24 | 4555387591 ps | ||
T60 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.320332705 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:03:26 PM PDT 24 | 25979361181 ps | ||
T357 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1940684211 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 1139818494 ps | ||
T104 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3895843438 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:15 PM PDT 24 | 1204013092 ps | ||
T95 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1486591646 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:15 PM PDT 24 | 2556243104 ps | ||
T358 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2075106912 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 1008388680 ps | ||
T359 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3445966026 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:15 PM PDT 24 | 10291494949 ps | ||
T96 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2930982872 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:17 PM PDT 24 | 3933958004 ps | ||
T360 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4174745017 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:05:23 PM PDT 24 | 67249790528 ps | ||
T166 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3624443009 | Aug 10 05:02:46 PM PDT 24 | Aug 10 05:03:07 PM PDT 24 | 1673557634 ps | ||
T361 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2392596227 | Aug 10 05:02:42 PM PDT 24 | Aug 10 05:02:47 PM PDT 24 | 2191837480 ps | ||
T362 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3406128467 | Aug 10 05:02:40 PM PDT 24 | Aug 10 05:02:42 PM PDT 24 | 151446808 ps | ||
T363 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1175903902 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:56 PM PDT 24 | 18428929921 ps | ||
T105 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3441261845 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:03:13 PM PDT 24 | 1099233269 ps | ||
T170 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3261361084 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:50 PM PDT 24 | 29765311949 ps | ||
T364 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4170999517 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:27 PM PDT 24 | 413558847 ps | ||
T118 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1787629769 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 93546572 ps | ||
T365 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.266073917 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:31 PM PDT 24 | 1394804745 ps | ||
T366 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3588565127 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 191878750 ps | ||
T167 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3356000631 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:33 PM PDT 24 | 8633267949 ps | ||
T367 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.493092120 | Aug 10 05:02:03 PM PDT 24 | Aug 10 05:02:07 PM PDT 24 | 876130507 ps | ||
T368 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2656144819 | Aug 10 05:02:38 PM PDT 24 | Aug 10 05:02:41 PM PDT 24 | 281372696 ps | ||
T369 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3729756828 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:03:02 PM PDT 24 | 8137996543 ps | ||
T370 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4051667916 | Aug 10 05:02:32 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 72186723 ps | ||
T371 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1433076340 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:24 PM PDT 24 | 57537292 ps | ||
T372 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4257381587 | Aug 10 05:02:19 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 111795763 ps | ||
T373 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1842690382 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 2757375730 ps | ||
T374 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.126661736 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:03:38 PM PDT 24 | 25535619124 ps | ||
T121 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2456337875 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 426194660 ps | ||
T106 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.755340549 | Aug 10 05:02:39 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 246235513 ps | ||
T375 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.712512085 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:27 PM PDT 24 | 123949278 ps | ||
T376 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2004324612 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:05 PM PDT 24 | 248198701 ps | ||
T377 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2988320226 | Aug 10 05:02:33 PM PDT 24 | Aug 10 05:02:34 PM PDT 24 | 197470849 ps | ||
T378 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.744060629 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:32 PM PDT 24 | 317642474 ps | ||
T379 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1680825743 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 2075367065 ps | ||
T380 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3303083892 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:26 PM PDT 24 | 582571089 ps | ||
T381 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2778319211 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 4992350852 ps | ||
T382 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2556892362 | Aug 10 05:02:18 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 7738744464 ps | ||
T171 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3620446802 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:55 PM PDT 24 | 32265756043 ps | ||
T383 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.262896807 | Aug 10 05:02:12 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 37303587541 ps | ||
T384 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3182198197 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 213221139 ps | ||
T385 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3291545008 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:03:16 PM PDT 24 | 24937383803 ps | ||
T386 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1900736408 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 169940137 ps | ||
T387 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.122908380 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 671538667 ps | ||
T388 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4262803967 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:41 PM PDT 24 | 1989879306 ps | ||
T389 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2909220891 | Aug 10 05:02:36 PM PDT 24 | Aug 10 05:02:37 PM PDT 24 | 268486861 ps | ||
T390 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3873204988 | Aug 10 05:02:42 PM PDT 24 | Aug 10 05:03:10 PM PDT 24 | 5519151248 ps | ||
T391 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2256494015 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:13 PM PDT 24 | 193581301 ps | ||
T392 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3052180865 | Aug 10 05:02:42 PM PDT 24 | Aug 10 05:02:44 PM PDT 24 | 122233832 ps | ||
T393 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4141175015 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 6800758681 ps | ||
T394 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.355903495 | Aug 10 05:02:19 PM PDT 24 | Aug 10 05:02:27 PM PDT 24 | 702400293 ps | ||
T395 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.39721469 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:34 PM PDT 24 | 158279413 ps | ||
T119 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.815657153 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 1414496233 ps | ||
T396 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1438184194 | Aug 10 05:02:34 PM PDT 24 | Aug 10 05:02:34 PM PDT 24 | 313757023 ps | ||
T117 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4159402300 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:37 PM PDT 24 | 53310976 ps | ||
T397 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2316221366 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:03:13 PM PDT 24 | 15708883597 ps | ||
T398 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2295543510 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:21 PM PDT 24 | 225292851 ps | ||
T168 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2478016491 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:42 PM PDT 24 | 3187145275 ps | ||
T399 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3987107296 | Aug 10 05:02:33 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 1281296805 ps | ||
T400 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1690908271 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:26 PM PDT 24 | 132042937 ps | ||
T401 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1760721331 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:26 PM PDT 24 | 2295589436 ps | ||
T402 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2043837230 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 717067400 ps | ||
T403 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3835040323 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:03:27 PM PDT 24 | 23853635211 ps | ||
T404 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.446385254 | Aug 10 05:02:42 PM PDT 24 | Aug 10 05:04:11 PM PDT 24 | 88100559315 ps | ||
T405 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1970621815 | Aug 10 05:02:31 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 911331669 ps | ||
T406 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.813204059 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:41 PM PDT 24 | 1205910173 ps | ||
T407 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1690368043 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:07 PM PDT 24 | 131869351 ps | ||
T408 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1933152364 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:40 PM PDT 24 | 387165085 ps | ||
T409 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2935623972 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 347248057 ps | ||
T410 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3158106458 | Aug 10 05:02:24 PM PDT 24 | Aug 10 05:02:30 PM PDT 24 | 6763110162 ps | ||
T411 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2933897740 | Aug 10 05:02:44 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 137854735 ps | ||
T412 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1001862844 | Aug 10 05:02:39 PM PDT 24 | Aug 10 05:02:43 PM PDT 24 | 1214738961 ps | ||
T413 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2796958552 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:49 PM PDT 24 | 8212268014 ps | ||
T414 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2152447375 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:30 PM PDT 24 | 13273638782 ps | ||
T415 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.422290117 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 93125756 ps | ||
T416 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3490729042 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:28 PM PDT 24 | 572883609 ps | ||
T417 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1161647330 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:03:08 PM PDT 24 | 31495923942 ps | ||
T418 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3889279050 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 63356358 ps | ||
T419 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2577727423 | Aug 10 05:02:02 PM PDT 24 | Aug 10 05:02:48 PM PDT 24 | 27474556299 ps | ||
T420 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2387742174 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:13 PM PDT 24 | 8144543397 ps | ||
T421 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3774701743 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 627633766 ps | ||
T422 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2500657598 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 186774850 ps | ||
T423 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.239791329 | Aug 10 05:02:05 PM PDT 24 | Aug 10 05:02:10 PM PDT 24 | 5593233911 ps | ||
T107 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2449665072 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:12 PM PDT 24 | 661150213 ps | ||
T424 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1583706352 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:16 PM PDT 24 | 13479010152 ps | ||
T425 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.198510048 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:11 PM PDT 24 | 200690593 ps | ||
T426 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.819477489 | Aug 10 05:02:02 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 6706444235 ps | ||
T427 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2724662241 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:26 PM PDT 24 | 201584640 ps | ||
T428 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3887923127 | Aug 10 05:02:45 PM PDT 24 | Aug 10 05:02:49 PM PDT 24 | 311531446 ps | ||
T429 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2842862579 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:07 PM PDT 24 | 76090758 ps | ||
T108 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.813494773 | Aug 10 05:02:33 PM PDT 24 | Aug 10 05:02:37 PM PDT 24 | 1477461877 ps | ||
T430 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2388833774 | Aug 10 05:02:42 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 264138906 ps | ||
T109 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3614460267 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:40 PM PDT 24 | 201256378 ps | ||
T431 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1562975491 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:15 PM PDT 24 | 642510879 ps | ||
T432 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2035724695 | Aug 10 05:02:02 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 33348091482 ps | ||
T433 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4136698067 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 95745421 ps | ||
T116 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1287907662 | Aug 10 05:02:03 PM PDT 24 | Aug 10 05:02:05 PM PDT 24 | 212629019 ps | ||
T434 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.791941878 | Aug 10 05:02:19 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 22197991916 ps | ||
T435 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3772877962 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:38 PM PDT 24 | 1783454655 ps | ||
T436 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3343952101 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:49 PM PDT 24 | 29344495878 ps | ||
T97 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.610432937 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:16 PM PDT 24 | 1755455250 ps | ||
T437 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.92159977 | Aug 10 05:02:10 PM PDT 24 | Aug 10 05:02:13 PM PDT 24 | 173193437 ps | ||
T438 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4158337915 | Aug 10 05:02:44 PM PDT 24 | Aug 10 05:06:08 PM PDT 24 | 83581226963 ps | ||
T439 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1048939968 | Aug 10 05:02:03 PM PDT 24 | Aug 10 05:02:31 PM PDT 24 | 921547257 ps | ||
T440 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3223154485 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:32 PM PDT 24 | 13805004603 ps | ||
T441 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2853225685 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:24 PM PDT 24 | 5017292474 ps | ||
T442 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2039505458 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:50 PM PDT 24 | 1497189526 ps | ||
T443 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2742903854 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:09 PM PDT 24 | 77637088 ps | ||
T444 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2486853300 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:23 PM PDT 24 | 84737677 ps | ||
T445 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3289972634 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:30 PM PDT 24 | 887683358 ps | ||
T446 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3444682198 | Aug 10 05:02:07 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 38704323 ps | ||
T447 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2228661304 | Aug 10 05:02:41 PM PDT 24 | Aug 10 05:02:53 PM PDT 24 | 7529051161 ps | ||
T448 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1909240336 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:28 PM PDT 24 | 7953700420 ps | ||
T449 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1248451722 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:26 PM PDT 24 | 1205745982 ps | ||
T450 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3410154496 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:39 PM PDT 24 | 1012707984 ps | ||
T451 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1129077003 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:38 PM PDT 24 | 220088075 ps | ||
T161 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2162002404 | Aug 10 05:02:33 PM PDT 24 | Aug 10 05:02:54 PM PDT 24 | 6031491578 ps | ||
T452 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1640490830 | Aug 10 05:02:40 PM PDT 24 | Aug 10 05:02:45 PM PDT 24 | 409922680 ps | ||
T453 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4079527141 | Aug 10 05:02:35 PM PDT 24 | Aug 10 05:02:36 PM PDT 24 | 187623599 ps | ||
T454 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4172020036 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:05 PM PDT 24 | 121951243 ps | ||
T455 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2588803222 | Aug 10 05:02:37 PM PDT 24 | Aug 10 05:02:46 PM PDT 24 | 13007776707 ps | ||
T456 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3927198557 | Aug 10 05:02:04 PM PDT 24 | Aug 10 05:02:05 PM PDT 24 | 59329298 ps | ||
T457 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.879823303 | Aug 10 05:02:06 PM PDT 24 | Aug 10 05:02:08 PM PDT 24 | 397203886 ps | ||
T458 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2515108468 | Aug 10 05:02:23 PM PDT 24 | Aug 10 05:03:09 PM PDT 24 | 23982235127 ps | ||
T459 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.167322949 | Aug 10 05:02:08 PM PDT 24 | Aug 10 05:02:29 PM PDT 24 | 7858643285 ps | ||
T460 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3435011815 | Aug 10 05:02:22 PM PDT 24 | Aug 10 05:02:27 PM PDT 24 | 1945763084 ps | ||
T461 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3691335016 | Aug 10 05:02:21 PM PDT 24 | Aug 10 05:02:25 PM PDT 24 | 510967060 ps | ||
T462 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.855826043 | Aug 10 05:02:33 PM PDT 24 | Aug 10 05:02:35 PM PDT 24 | 2659454471 ps | ||
T163 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4138109760 | Aug 10 05:02:32 PM PDT 24 | Aug 10 05:02:54 PM PDT 24 | 5962946179 ps | ||
T463 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1566841724 | Aug 10 05:02:41 PM PDT 24 | Aug 10 05:02:44 PM PDT 24 | 262141025 ps | ||
T164 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1883803799 | Aug 10 05:02:20 PM PDT 24 | Aug 10 05:02:34 PM PDT 24 | 3869866580 ps |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.2494873979 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 6012199440 ps |
CPU time | 9.03 seconds |
Started | Aug 10 04:57:00 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-fa6812cc-a075-41e4-8d8b-2fc4a3f146f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494873979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2494873979 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.3372898757 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 124214433112 ps |
CPU time | 939.58 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 05:12:49 PM PDT 24 |
Peak memory | 231052 kb |
Host | smart-8a6722ac-1ef5-40b2-8f18-4fbaf90e645e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372898757 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.3372898757 |
Directory | /workspace/7.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.279850132 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 5006546726 ps |
CPU time | 10.93 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 213980 kb |
Host | smart-e86d6ae1-7745-494a-acf3-8ce817372184 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279850132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.279850132 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1947648827 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 2164294855 ps |
CPU time | 20.29 seconds |
Started | Aug 10 05:02:44 PM PDT 24 |
Finished | Aug 10 05:03:05 PM PDT 24 |
Peak memory | 213904 kb |
Host | smart-132fc2bd-21d2-4ba9-aabb-85b8d0df5a1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947648827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 947648827 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2577727423 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 27474556299 ps |
CPU time | 45.42 seconds |
Started | Aug 10 05:02:02 PM PDT 24 |
Finished | Aug 10 05:02:48 PM PDT 24 |
Peak memory | 220760 kb |
Host | smart-1f9ff35b-5f48-4251-9f82-4f0251ad28dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577727423 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2577727423 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4146625953 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 50556253957 ps |
CPU time | 76.93 seconds |
Started | Aug 10 04:57:21 PM PDT 24 |
Finished | Aug 10 04:58:38 PM PDT 24 |
Peak memory | 213936 kb |
Host | smart-c57caf53-195c-42a0-9033-deded4adb36c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146625953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.4146625953 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.1138340975 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 27498000783 ps |
CPU time | 437.25 seconds |
Started | Aug 10 04:57:04 PM PDT 24 |
Finished | Aug 10 05:04:21 PM PDT 24 |
Peak memory | 230312 kb |
Host | smart-46bd677a-ab89-4fa4-8bc1-166049207545 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138340975 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.1138340975 |
Directory | /workspace/6.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.3023116658 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 132954095 ps |
CPU time | 0.86 seconds |
Started | Aug 10 04:56:53 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-1409991c-a529-4f67-828b-c6886433a3e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023116658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3023116658 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2007119825 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 80665330 ps |
CPU time | 0.72 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:27 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-09a59d1b-d4b4-4df5-9629-ad6b8f40d07b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007119825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2007119825 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.4291291932 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 21166504482 ps |
CPU time | 30.48 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 217668 kb |
Host | smart-24cd4752-0ab1-40e4-92fe-0d759cd00847 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291291932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.4291291932 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.407416220 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 641277832 ps |
CPU time | 2.49 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:44 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-9e7ee704-4e81-4e17-a5e5-4681a73a4e08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407416220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.407416220 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.2888127565 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3595103267 ps |
CPU time | 5.44 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:15 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-405ebfaa-b5dd-48a3-b0f4-d3fb50f63f93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888127565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2888127565 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2487494739 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1125478258 ps |
CPU time | 3.61 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 229904 kb |
Host | smart-4ae02ae3-e464-4c58-adad-219fd6c46d7e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487494739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2487494739 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1173355549 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 56638649915 ps |
CPU time | 79.99 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:03:27 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-6db36996-b731-40f6-bdd1-625d7448601b |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173355549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.1173355549 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.381727511 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 42568998634 ps |
CPU time | 18.72 seconds |
Started | Aug 10 04:57:11 PM PDT 24 |
Finished | Aug 10 04:57:30 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-a1d0ffb7-ee64-497c-8706-9a1685b1086c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381727511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.381727511 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.3075487002 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 155938675 ps |
CPU time | 0.81 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:43 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-deb61f98-26e9-404d-b4a8-69f14a7edc65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075487002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3075487002 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.2687785284 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1611610595 ps |
CPU time | 3.73 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:36 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-30af945f-94cf-4433-bdc4-1adebc3c28b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687785284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2687785284 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.657230737 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 64031980 ps |
CPU time | 0.91 seconds |
Started | Aug 10 04:56:53 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-dfc07660-8a6f-489b-8951-97a8f251f773 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657230737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.657230737 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.956453298 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 4555387591 ps |
CPU time | 28.81 seconds |
Started | Aug 10 05:02:34 PM PDT 24 |
Finished | Aug 10 05:03:03 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-67d32d93-b62e-44d5-a75f-3b1c195bbcb0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956453298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.956453298 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.85381254 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1435004285 ps |
CPU time | 1.85 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:55 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-e3578104-c436-4f9f-822c-3f16370d0866 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85381254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.85381254 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.57664534 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 343497411 ps |
CPU time | 1.21 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:06 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-38209d95-6233-4651-9ca3-89be34120f17 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57664534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_ hw_reset.57664534 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1287907662 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 212629019 ps |
CPU time | 1.76 seconds |
Started | Aug 10 05:02:03 PM PDT 24 |
Finished | Aug 10 05:02:05 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-d2cace2a-14ec-44a8-80d7-0929b1e5eb71 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287907662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1287907662 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.785642603 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 9730333768 ps |
CPU time | 7.8 seconds |
Started | Aug 10 05:02:38 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-bc3abb74-471f-42d8-9217-60f1b268378f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785642603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.785642603 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.3569103250 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 91335648 ps |
CPU time | 0.79 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-58b0241c-7b1c-4411-b00a-f7b7ebc807d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569103250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3569103250 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4138109760 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 5962946179 ps |
CPU time | 21.27 seconds |
Started | Aug 10 05:02:32 PM PDT 24 |
Finished | Aug 10 05:02:54 PM PDT 24 |
Peak memory | 221288 kb |
Host | smart-9e3f9055-77e6-4d89-bc0f-9d1e7476c99d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138109760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4 138109760 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.292545834 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 772319994 ps |
CPU time | 1.53 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:21 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-639cf8f9-021c-48c0-93a5-d6c1292501e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292545834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.292545834 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3395941151 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 3459532737 ps |
CPU time | 5.24 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:38 PM PDT 24 |
Peak memory | 213784 kb |
Host | smart-d0d55c86-3ce7-496e-8987-86c2ff0eb33f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395941151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3395941151 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.3477216952 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 324802786 ps |
CPU time | 1.71 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:52 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-8c35fb16-a338-458b-98fc-adb93dd1ddbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477216952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3477216952 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1806373190 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 392389113731 ps |
CPU time | 1086.61 seconds |
Started | Aug 10 04:57:11 PM PDT 24 |
Finished | Aug 10 05:15:18 PM PDT 24 |
Peak memory | 235760 kb |
Host | smart-949b6e88-097e-4131-94a7-62149e331d22 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806373190 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1806373190 |
Directory | /workspace/9.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.610432937 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1755455250 ps |
CPU time | 5.75 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:16 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-bbe8f285-f1cb-4e41-b140-1d1f94f9bfbb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610432937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _hw_reset.610432937 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.718295643 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 1538073024 ps |
CPU time | 1.94 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:43 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-1934689a-c849-405f-ad85-db8575cc8995 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718295643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.718295643 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2162002404 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 6031491578 ps |
CPU time | 21.21 seconds |
Started | Aug 10 05:02:33 PM PDT 24 |
Finished | Aug 10 05:02:54 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-d3d5effb-692a-44f3-8e69-b481e29c1907 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162002404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 162002404 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.801929282 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1180414278 ps |
CPU time | 10.77 seconds |
Started | Aug 10 05:02:40 PM PDT 24 |
Finished | Aug 10 05:02:51 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-f2ce0c02-16ea-4c04-a4c5-84fa158e99cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801929282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.801929282 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1883803799 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 3869866580 ps |
CPU time | 13.54 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:34 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-401f3afc-3afe-4df1-8f11-2b33ca09b4b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883803799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1883803799 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.529799046 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 1689439043 ps |
CPU time | 5.8 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:56:56 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-4fc667f3-6811-49b2-b788-99f4270cb1e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529799046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.529799046 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1169491499 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 2926635954 ps |
CPU time | 5.87 seconds |
Started | Aug 10 04:57:17 PM PDT 24 |
Finished | Aug 10 04:57:23 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-312294cf-48e6-46a3-8534-d4f9efd527e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169491499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1169491499 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.95882665 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 4079888685 ps |
CPU time | 11.41 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:39 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-27928ec3-2add-4159-ac4a-6b7109908399 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95882665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.95882665 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.1070449851 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 6231183337 ps |
CPU time | 12.87 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 205684 kb |
Host | smart-2261b7fc-7e4f-47ef-a7f0-8dd23bad386c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070449851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1070449851 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3291545008 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 24937383803 ps |
CPU time | 71.67 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:03:16 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-a8e1fd0e-63ef-49bc-bc35-f441fa0e29ac |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291545008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.3291545008 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3048377432 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 732848444 ps |
CPU time | 27.73 seconds |
Started | Aug 10 05:02:03 PM PDT 24 |
Finished | Aug 10 05:02:30 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-836bbdbb-196c-4f9a-b6e0-99e22bb18822 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048377432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3048377432 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.493092120 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 876130507 ps |
CPU time | 3.78 seconds |
Started | Aug 10 05:02:03 PM PDT 24 |
Finished | Aug 10 05:02:07 PM PDT 24 |
Peak memory | 221952 kb |
Host | smart-25691291-4271-4930-9f5a-b83915793360 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493092120 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.493092120 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1595393708 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 75407159 ps |
CPU time | 1.54 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:07 PM PDT 24 |
Peak memory | 213884 kb |
Host | smart-974d3ffb-0f0e-42e8-bc84-d56891d3a954 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595393708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1595393708 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3580644490 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 65228251762 ps |
CPU time | 104.54 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:03:51 PM PDT 24 |
Peak memory | 205692 kb |
Host | smart-0ca28953-a54e-44fc-bb36-50c2b63a6281 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580644490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3580644490 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3445966026 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 10291494949 ps |
CPU time | 9.5 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:15 PM PDT 24 |
Peak memory | 205620 kb |
Host | smart-79cb473e-553e-424e-9300-6ded6ec5fa07 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445966026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3445966026 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.819477489 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 6706444235 ps |
CPU time | 6.28 seconds |
Started | Aug 10 05:02:02 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-2e80367d-c8d8-4582-8c1b-49c7531b6373 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819477489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.819477489 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2244171395 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 649607047 ps |
CPU time | 1.95 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-0ac973db-274e-445e-941c-7e2c145c33e2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244171395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2244171395 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1175903902 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 18428929921 ps |
CPU time | 52.4 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:56 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-38f5bc5a-eea0-4199-a062-b6e91189bb20 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175903902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1175903902 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3774701743 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 627633766 ps |
CPU time | 1.54 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-4967fa38-d81f-4742-9ed7-7db5991f2fb5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774701743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 774701743 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3927198557 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 59329298 ps |
CPU time | 0.7 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:05 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-e5d26f81-21d1-4277-88e4-08198f322b21 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927198557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.3927198557 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2742903854 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 77637088 ps |
CPU time | 0.71 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-c4e32590-78af-4d7f-a62a-a5f7cfb3e63a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742903854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2742903854 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2456337875 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 426194660 ps |
CPU time | 3.77 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-654b4131-b62f-4a3a-822c-746fbee0b85d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456337875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2456337875 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2152447375 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 13273638782 ps |
CPU time | 23.91 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:30 PM PDT 24 |
Peak memory | 219136 kb |
Host | smart-688f184e-b36c-4165-98a5-27d207ce735d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152447375 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2152447375 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2399860182 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 1520732032 ps |
CPU time | 7.42 seconds |
Started | Aug 10 05:02:03 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 213964 kb |
Host | smart-8fa8e259-7276-49e9-9f14-781c4d8330d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399860182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2399860182 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1419112697 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2274776811 ps |
CPU time | 15.19 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:20 PM PDT 24 |
Peak memory | 213948 kb |
Host | smart-800dd3d7-9ab3-4c69-944f-8720fbe3e4f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419112697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1419112697 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3835040323 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 23853635211 ps |
CPU time | 81.14 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:03:27 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-85234052-21cf-420e-8332-2e59ec186442 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835040323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3835040323 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1048939968 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 921547257 ps |
CPU time | 27.97 seconds |
Started | Aug 10 05:02:03 PM PDT 24 |
Finished | Aug 10 05:02:31 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-c1905d0a-7740-4d52-a9ee-d46998f08bdd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048939968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1048939968 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.92159977 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 173193437 ps |
CPU time | 2.6 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:13 PM PDT 24 |
Peak memory | 213916 kb |
Host | smart-fafef49b-08ea-4cb3-97b2-ca6013122726 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92159977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.92159977 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4128714683 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 234133757 ps |
CPU time | 2.58 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 219828 kb |
Host | smart-b369f6ab-35df-455c-b914-949af7859aa2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128714683 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4128714683 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.815657153 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1414496233 ps |
CPU time | 2.84 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-529dcf24-96da-40dd-8c07-f48092caf942 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815657153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.815657153 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3515374675 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 87827722094 ps |
CPU time | 127.51 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:04:14 PM PDT 24 |
Peak memory | 205636 kb |
Host | smart-1e8bc08e-4e82-44c0-8b43-9981ef17a4a5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515374675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.3515374675 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3191268803 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 10106887737 ps |
CPU time | 8.34 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:13 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-d7aa10f2-5586-482f-87a0-7166a3b0e145 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191268803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.3191268803 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2930982872 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 3933958004 ps |
CPU time | 11.26 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:17 PM PDT 24 |
Peak memory | 205832 kb |
Host | smart-61fea73a-3964-4ac6-8214-f3aabc2677a2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930982872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2930982872 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3351100393 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 5228016289 ps |
CPU time | 7.85 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:13 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-e6f6c36d-3627-4182-849c-82ebeb6b9302 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351100393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3 351100393 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3254102246 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 346280380 ps |
CPU time | 1.7 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:12 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-009e6cee-ea7d-43e9-a584-857f86b81761 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254102246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3254102246 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.724827483 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 5562405322 ps |
CPU time | 2.94 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-1a4b11b7-b074-42f5-9bf7-4f46f04ec2d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724827483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.724827483 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2004324612 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 248198701 ps |
CPU time | 0.97 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:05 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-b14beab4-5906-4bb9-9a04-b7f3cf11f62a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004324612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.2004324612 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1900736408 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 169940137 ps |
CPU time | 0.94 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-7108890f-0bab-4308-911d-d399558fcf2a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900736408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1 900736408 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1690368043 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 131869351 ps |
CPU time | 0.83 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:07 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-1013348f-7225-4120-a8b6-9aba6d57f297 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690368043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1690368043 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4172020036 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 121951243 ps |
CPU time | 0.99 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:05 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-f381a2fa-81d2-4007-9a01-7ce43bff09dd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172020036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4172020036 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2449665072 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 661150213 ps |
CPU time | 7.85 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:12 PM PDT 24 |
Peak memory | 205628 kb |
Host | smart-f0463ec9-e49b-432f-92ca-60a3cd430ee6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449665072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2449665072 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2500657598 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 186774850 ps |
CPU time | 3.11 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 221952 kb |
Host | smart-e8fa20d7-d738-43fc-a511-4c468372a035 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500657598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2500657598 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1562975491 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 642510879 ps |
CPU time | 9.57 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:15 PM PDT 24 |
Peak memory | 213864 kb |
Host | smart-459111e1-cf14-4e0b-a61d-c509acb06a32 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562975491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1562975491 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.749584882 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 169980750 ps |
CPU time | 4.1 seconds |
Started | Aug 10 05:02:32 PM PDT 24 |
Finished | Aug 10 05:02:36 PM PDT 24 |
Peak memory | 221976 kb |
Host | smart-31742cca-4147-47f3-9762-0c47cdad11b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749584882 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.749584882 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3660813035 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 94490046 ps |
CPU time | 1.6 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:33 PM PDT 24 |
Peak memory | 213772 kb |
Host | smart-677ddbae-9891-4559-85be-51a5b0457faa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660813035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3660813035 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.259572879 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 9367411320 ps |
CPU time | 27.57 seconds |
Started | Aug 10 05:02:34 PM PDT 24 |
Finished | Aug 10 05:03:02 PM PDT 24 |
Peak memory | 205504 kb |
Host | smart-1e0a138a-ae2a-401e-badd-28a935a35924 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259572879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rv_dm_jtag_dmi_csr_bit_bash.259572879 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3772877962 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 1783454655 ps |
CPU time | 1.14 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:38 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-311c36d4-4ea4-4bd5-9a46-5e3fdd2b8786 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772877962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3772877962 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2839660487 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 422771967 ps |
CPU time | 1.51 seconds |
Started | Aug 10 05:02:32 PM PDT 24 |
Finished | Aug 10 05:02:33 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-cbb1fb31-f037-4820-9c6b-16b988aae41a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839660487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 2839660487 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1970621815 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 911331669 ps |
CPU time | 4.41 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-76fbe8ca-036e-4614-a367-5f5df2673381 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970621815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.1970621815 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4262803967 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1989879306 ps |
CPU time | 6.26 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:41 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-7e4f7a26-b070-4ab6-8a15-56c90907ae0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262803967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4262803967 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2656144819 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 281372696 ps |
CPU time | 2.93 seconds |
Started | Aug 10 05:02:38 PM PDT 24 |
Finished | Aug 10 05:02:41 PM PDT 24 |
Peak memory | 218332 kb |
Host | smart-797f3eb8-7745-47c5-b39d-e175da894083 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656144819 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2656144819 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2017693432 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 167799887 ps |
CPU time | 2.19 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:34 PM PDT 24 |
Peak memory | 213716 kb |
Host | smart-bd8251d0-ef10-4c6e-9940-d8e61c706ede |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017693432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2017693432 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1801716417 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 127814492432 ps |
CPU time | 353.45 seconds |
Started | Aug 10 05:02:39 PM PDT 24 |
Finished | Aug 10 05:08:33 PM PDT 24 |
Peak memory | 205484 kb |
Host | smart-ac4def81-b41c-4733-8d38-93ade0619513 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801716417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.1801716417 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2778319211 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 4992350852 ps |
CPU time | 7.96 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-3c0f456c-8fce-4183-a556-12d8b0d9f6c5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778319211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 2778319211 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1438184194 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 313757023 ps |
CPU time | 0.77 seconds |
Started | Aug 10 05:02:34 PM PDT 24 |
Finished | Aug 10 05:02:34 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-eddf6b10-b011-4d80-83b8-12cb961f7cb5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438184194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 1438184194 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3614460267 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 201256378 ps |
CPU time | 3.42 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:40 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-5f5ad393-da1e-4c62-b959-60baf05238bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614460267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3614460267 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.39721469 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 158279413 ps |
CPU time | 2.89 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:34 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-96c41f2b-f135-4442-9a90-61a05b533849 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39721469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.39721469 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.122908380 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 671538667 ps |
CPU time | 4.08 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 219992 kb |
Host | smart-d7e7e858-37bc-45b1-a956-d4afd7b5c631 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122908380 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.122908380 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.296301184 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 149927364 ps |
CPU time | 1.42 seconds |
Started | Aug 10 05:02:33 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-a4b8faf3-6c4a-43f0-8984-a06b401414eb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296301184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.296301184 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3905988644 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 10109380647 ps |
CPU time | 30.75 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:03:02 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-6aa2bd80-bb89-4ed7-9892-eb012cc56310 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905988644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.3905988644 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1892698109 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 3058371868 ps |
CPU time | 8.66 seconds |
Started | Aug 10 05:02:36 PM PDT 24 |
Finished | Aug 10 05:02:44 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-64b76459-de5a-4f99-bec8-3f7561580c34 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892698109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 1892698109 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.744060629 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 317642474 ps |
CPU time | 1.19 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:32 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-64ae6357-edef-440c-bb0f-044452911c5b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744060629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.744060629 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4087928364 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 105636146 ps |
CPU time | 3.65 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-995d5e0b-581c-4cd8-b402-717c91b835f7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087928364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.4087928364 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2323763257 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 281892531 ps |
CPU time | 5.55 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:41 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-6b8c1367-0d45-4fd7-bb97-202cfc6a90aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323763257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2323763257 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1301604025 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 2792594320 ps |
CPU time | 19.61 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:54 PM PDT 24 |
Peak memory | 214028 kb |
Host | smart-fec68601-0e71-4d0b-8428-830fe1675f8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301604025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 301604025 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1933152364 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 387165085 ps |
CPU time | 2.98 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:40 PM PDT 24 |
Peak memory | 218476 kb |
Host | smart-05302101-d5a3-45b7-9679-6eef647a31ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933152364 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1933152364 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2988320226 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 197470849 ps |
CPU time | 1.7 seconds |
Started | Aug 10 05:02:33 PM PDT 24 |
Finished | Aug 10 05:02:34 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-9667c16a-b23b-48bf-a4cf-d6da868bb106 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988320226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2988320226 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1842690382 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 2757375730 ps |
CPU time | 3.49 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-d6131046-0e6e-48da-841d-c7b887501dcc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842690382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1842690382 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.855826043 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 2659454471 ps |
CPU time | 2.42 seconds |
Started | Aug 10 05:02:33 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 205668 kb |
Host | smart-420b3b2e-9fcd-4526-838e-5b5cebb45a17 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855826043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.855826043 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4079527141 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 187623599 ps |
CPU time | 0.83 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:36 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-61e1ce95-26fb-48b4-abf0-694e99140122 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079527141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 4079527141 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.813494773 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 1477461877 ps |
CPU time | 3.87 seconds |
Started | Aug 10 05:02:33 PM PDT 24 |
Finished | Aug 10 05:02:37 PM PDT 24 |
Peak memory | 205724 kb |
Host | smart-9bd3250f-cdae-4c92-98d1-4a9da4c1c571 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813494773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.813494773 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4051667916 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 72186723 ps |
CPU time | 2.76 seconds |
Started | Aug 10 05:02:32 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 213972 kb |
Host | smart-49f71cb6-e2f3-4f07-bc38-6b61ce2be28f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051667916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4051667916 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2027551451 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 2764681354 ps |
CPU time | 11.54 seconds |
Started | Aug 10 05:02:36 PM PDT 24 |
Finished | Aug 10 05:02:48 PM PDT 24 |
Peak memory | 222016 kb |
Host | smart-31bbd3c9-0f1a-4a66-bd4f-791438ee4285 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027551451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 027551451 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1001862844 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 1214738961 ps |
CPU time | 3.83 seconds |
Started | Aug 10 05:02:39 PM PDT 24 |
Finished | Aug 10 05:02:43 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-9db2661f-a651-4717-8ecf-7f583d17f630 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001862844 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1001862844 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1775095717 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 202603999 ps |
CPU time | 1.58 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:38 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-02231c4d-5ae6-4c1f-85cf-1a3aed95a0ba |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775095717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1775095717 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4158337915 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 83581226963 ps |
CPU time | 202.87 seconds |
Started | Aug 10 05:02:44 PM PDT 24 |
Finished | Aug 10 05:06:08 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-cc2177a2-5eb3-45fa-b85e-f1bc540643c1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158337915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.4158337915 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3987107296 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 1281296805 ps |
CPU time | 2.35 seconds |
Started | Aug 10 05:02:33 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 205600 kb |
Host | smart-89c7432c-39ae-427a-b8ab-ada104181604 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987107296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3987107296 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1129077003 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 220088075 ps |
CPU time | 1 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:38 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-9c008137-5eaf-41a8-bd87-27b58046155a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129077003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 1129077003 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1302750500 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 2183089121 ps |
CPU time | 4.18 seconds |
Started | Aug 10 05:02:34 PM PDT 24 |
Finished | Aug 10 05:02:38 PM PDT 24 |
Peak memory | 213980 kb |
Host | smart-91af96ca-c32c-4ffd-9f6f-7a8f5834af29 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302750500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1302750500 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1221220714 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 274047913 ps |
CPU time | 2.74 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:38 PM PDT 24 |
Peak memory | 213756 kb |
Host | smart-d4231e29-923a-462a-89f5-9a9313e092ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221220714 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1221220714 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4159402300 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 53310976 ps |
CPU time | 1.53 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:37 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-2c4bf60d-5798-4211-b941-a687c66b0b0c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159402300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4159402300 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3729756828 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 8137996543 ps |
CPU time | 26.15 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:03:02 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-995f3b96-3517-4a39-bac9-aff4530020b7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729756828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.3729756828 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4032392652 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1937290497 ps |
CPU time | 6.82 seconds |
Started | Aug 10 05:02:36 PM PDT 24 |
Finished | Aug 10 05:02:43 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-0c1372df-fca0-4b17-8edb-6da1f17acf44 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032392652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 4032392652 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.291341013 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 505977100 ps |
CPU time | 2.04 seconds |
Started | Aug 10 05:02:31 PM PDT 24 |
Finished | Aug 10 05:02:33 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-359c4252-2481-41d0-8c63-ebbb2e9b4752 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291341013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.291341013 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3410154496 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 1012707984 ps |
CPU time | 4.52 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-180e5ded-4567-4c87-967b-021eff675151 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410154496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.3410154496 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2007955858 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 214951297 ps |
CPU time | 2.72 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:40 PM PDT 24 |
Peak memory | 213980 kb |
Host | smart-71a5812f-0913-48c3-8d1e-c6e05d2d320a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007955858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2007955858 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2248230170 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 2729088653 ps |
CPU time | 11.01 seconds |
Started | Aug 10 05:02:34 PM PDT 24 |
Finished | Aug 10 05:02:45 PM PDT 24 |
Peak memory | 213960 kb |
Host | smart-c78c7be2-fbdc-401a-bddb-8a3cae9e464a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248230170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 248230170 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3887923127 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 311531446 ps |
CPU time | 4.23 seconds |
Started | Aug 10 05:02:45 PM PDT 24 |
Finished | Aug 10 05:02:49 PM PDT 24 |
Peak memory | 220124 kb |
Host | smart-1d3b469b-fd08-4af1-b2a9-e893eed4d5b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887923127 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3887923127 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1484430022 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 93754124 ps |
CPU time | 1.69 seconds |
Started | Aug 10 05:02:45 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-531b6e3d-85ce-4a80-a846-343c37e52c34 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484430022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1484430022 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2168130503 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 19250411983 ps |
CPU time | 19.16 seconds |
Started | Aug 10 05:02:36 PM PDT 24 |
Finished | Aug 10 05:02:55 PM PDT 24 |
Peak memory | 205512 kb |
Host | smart-1d900a3e-38c0-46ee-b4c5-575d8fcaaa0d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168130503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.2168130503 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3079005535 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 3154112415 ps |
CPU time | 5.64 seconds |
Started | Aug 10 05:02:38 PM PDT 24 |
Finished | Aug 10 05:02:43 PM PDT 24 |
Peak memory | 205592 kb |
Host | smart-5d46aa52-0f08-477d-b991-eddd411ab1f3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079005535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 3079005535 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2419607890 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 198260605 ps |
CPU time | 1.12 seconds |
Started | Aug 10 05:02:30 PM PDT 24 |
Finished | Aug 10 05:02:31 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-69a9a691-f94d-4046-831a-9431424c6751 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419607890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2419607890 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.379103564 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 300538277 ps |
CPU time | 3.52 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:41 PM PDT 24 |
Peak memory | 205712 kb |
Host | smart-c8a18ed7-57e7-4359-9df4-6ebbc6f688de |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379103564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_ csr_outstanding.379103564 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1898525371 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 233736483 ps |
CPU time | 5.57 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:42 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-42553db0-9217-4a3b-848d-5525691edc67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898525371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1898525371 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.813204059 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1205910173 ps |
CPU time | 3.85 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:41 PM PDT 24 |
Peak memory | 219060 kb |
Host | smart-a4b84c52-cd98-4501-bedc-3e6393a3c287 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813204059 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.813204059 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3500390885 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 309194268 ps |
CPU time | 2.26 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-afb97f8a-8132-418b-b2f2-62676a64d9b2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500390885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3500390885 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2796958552 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 8212268014 ps |
CPU time | 13.24 seconds |
Started | Aug 10 05:02:35 PM PDT 24 |
Finished | Aug 10 05:02:49 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-07b56b54-09f0-4a0e-b67a-b07e7214194a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796958552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.2796958552 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2588803222 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 13007776707 ps |
CPU time | 8.88 seconds |
Started | Aug 10 05:02:37 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-ff8a5cd3-02a3-4f54-9bb0-667f74f15fae |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588803222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 2588803222 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2933897740 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 137854735 ps |
CPU time | 1.03 seconds |
Started | Aug 10 05:02:44 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-0dd3f76c-8529-412c-a873-e5a68493cbda |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933897740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2933897740 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1640490830 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 409922680 ps |
CPU time | 4.21 seconds |
Started | Aug 10 05:02:40 PM PDT 24 |
Finished | Aug 10 05:02:45 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-906b94b8-7853-40e1-aac3-eddf470aa31e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640490830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.1640490830 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2679376433 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 912010063 ps |
CPU time | 5.38 seconds |
Started | Aug 10 05:02:36 PM PDT 24 |
Finished | Aug 10 05:02:42 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-f35f5330-e4cf-4f93-a1f9-d5ab910018c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679376433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2679376433 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1566841724 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 262141025 ps |
CPU time | 3.01 seconds |
Started | Aug 10 05:02:41 PM PDT 24 |
Finished | Aug 10 05:02:44 PM PDT 24 |
Peak memory | 219440 kb |
Host | smart-b3332fdb-c127-4b3f-a04f-de23a99868ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566841724 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1566841724 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3406128467 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 151446808 ps |
CPU time | 1.82 seconds |
Started | Aug 10 05:02:40 PM PDT 24 |
Finished | Aug 10 05:02:42 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-1a66570e-378b-4d71-9403-88009bdbe0cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406128467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3406128467 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2228661304 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 7529051161 ps |
CPU time | 11.69 seconds |
Started | Aug 10 05:02:41 PM PDT 24 |
Finished | Aug 10 05:02:53 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-c615332a-73b0-4461-9dd2-77a29a723d36 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228661304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.2228661304 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2258458045 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 2110116368 ps |
CPU time | 1.65 seconds |
Started | Aug 10 05:02:40 PM PDT 24 |
Finished | Aug 10 05:02:42 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-372f2239-c0d5-4873-9012-db246c8520ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258458045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 2258458045 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1370937286 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 928440202 ps |
CPU time | 0.98 seconds |
Started | Aug 10 05:02:45 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-51f6706f-7969-472f-8e67-31f3c5eb6388 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370937286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 1370937286 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.755340549 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 246235513 ps |
CPU time | 6.89 seconds |
Started | Aug 10 05:02:39 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-93c55e3b-a0ff-42c1-b8ce-db192a2b4e4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755340549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_ csr_outstanding.755340549 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2392596227 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 2191837480 ps |
CPU time | 4.6 seconds |
Started | Aug 10 05:02:42 PM PDT 24 |
Finished | Aug 10 05:02:47 PM PDT 24 |
Peak memory | 214116 kb |
Host | smart-2b16766f-e38e-4fa9-8508-4bab31697157 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392596227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2392596227 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3873204988 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 5519151248 ps |
CPU time | 27.36 seconds |
Started | Aug 10 05:02:42 PM PDT 24 |
Finished | Aug 10 05:03:10 PM PDT 24 |
Peak memory | 213984 kb |
Host | smart-1115d392-27b4-4d98-a009-06e2a4702d37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873204988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3 873204988 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2388833774 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 264138906 ps |
CPU time | 4.16 seconds |
Started | Aug 10 05:02:42 PM PDT 24 |
Finished | Aug 10 05:02:46 PM PDT 24 |
Peak memory | 220316 kb |
Host | smart-5829f3ac-5bb9-441f-a6c2-d45fb2c6aa60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388833774 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2388833774 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3052180865 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 122233832 ps |
CPU time | 1.56 seconds |
Started | Aug 10 05:02:42 PM PDT 24 |
Finished | Aug 10 05:02:44 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-6225b0dc-faf6-46ab-b99f-adb5d02d811d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052180865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3052180865 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.446385254 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 88100559315 ps |
CPU time | 89.17 seconds |
Started | Aug 10 05:02:42 PM PDT 24 |
Finished | Aug 10 05:04:11 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-2ab4927c-4d92-4d98-9d62-2b367ba30d01 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446385254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rv_dm_jtag_dmi_csr_bit_bash.446385254 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3763151443 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 2472499807 ps |
CPU time | 5.73 seconds |
Started | Aug 10 05:02:41 PM PDT 24 |
Finished | Aug 10 05:02:47 PM PDT 24 |
Peak memory | 205676 kb |
Host | smart-f7dde84b-2130-48c7-afd5-2475b17ce535 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763151443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 3763151443 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2909220891 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 268486861 ps |
CPU time | 0.85 seconds |
Started | Aug 10 05:02:36 PM PDT 24 |
Finished | Aug 10 05:02:37 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-cc5f05da-6cb0-4952-8b1b-b4a8deb97315 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909220891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2909220891 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.817107153 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 327722764 ps |
CPU time | 3.65 seconds |
Started | Aug 10 05:02:44 PM PDT 24 |
Finished | Aug 10 05:02:48 PM PDT 24 |
Peak memory | 205620 kb |
Host | smart-d9de42a1-ce65-4e2f-afe4-a1d0201d9a1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817107153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_ csr_outstanding.817107153 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1943756372 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 684348609 ps |
CPU time | 3.27 seconds |
Started | Aug 10 05:02:42 PM PDT 24 |
Finished | Aug 10 05:02:45 PM PDT 24 |
Peak memory | 213840 kb |
Host | smart-3a18d3de-c52a-4a35-bbd2-45f1f8f38c61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943756372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1943756372 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3624443009 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 1673557634 ps |
CPU time | 21.25 seconds |
Started | Aug 10 05:02:46 PM PDT 24 |
Finished | Aug 10 05:03:07 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-7b1d17a8-ea38-4363-8e38-f0ee57fd8848 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624443009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3 624443009 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1183169266 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 30564445512 ps |
CPU time | 77.37 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:03:28 PM PDT 24 |
Peak memory | 213844 kb |
Host | smart-da2463c4-bca6-4345-bd7e-7da420b52206 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183169266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1183169266 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2515716102 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 84793214 ps |
CPU time | 1.66 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-731558b7-3ff1-46e8-bd73-89640bd3c7b5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515716102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2515716102 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2256494015 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 193581301 ps |
CPU time | 2.73 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:13 PM PDT 24 |
Peak memory | 218484 kb |
Host | smart-aa00f6ec-9faf-4d67-aebc-b2a0c21e3e30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256494015 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2256494015 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.494525687 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 307326106 ps |
CPU time | 1.62 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-667bfc94-56a0-4f3b-a2e2-7e324eeebdcd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494525687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.494525687 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4082653747 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 92837264550 ps |
CPU time | 253.31 seconds |
Started | Aug 10 05:02:03 PM PDT 24 |
Finished | Aug 10 05:06:16 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-9b369e71-c441-44eb-9c21-a037f0eedae9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082653747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.4082653747 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.896842019 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 91262208208 ps |
CPU time | 34.78 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:45 PM PDT 24 |
Peak memory | 205652 kb |
Host | smart-8d5607a2-0900-4608-be79-6df646b4a0de |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896842019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r v_dm_jtag_dmi_csr_bit_bash.896842019 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2935512641 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 4970387889 ps |
CPU time | 5.08 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-0a696d25-f1c6-437b-8981-5ae5f838355d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935512641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2935512641 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.239791329 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 5593233911 ps |
CPU time | 5.11 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-27e1d6fa-742e-4318-8bf5-7af5c3ade9cd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239791329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.239791329 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1640186676 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 2108868906 ps |
CPU time | 6.5 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:11 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-d579332a-c9f2-4346-b13e-d1c87facc80a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640186676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1640186676 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2035724695 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 33348091482 ps |
CPU time | 22.46 seconds |
Started | Aug 10 05:02:02 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-374e700f-2137-446e-b3f0-c91e073c8fd0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035724695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.2035724695 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2537505710 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 739530734 ps |
CPU time | 2.74 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-9606fa53-4de0-4480-8b5f-2be4fa215a7e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537505710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2537505710 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.499821674 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 134968483 ps |
CPU time | 0.76 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-d86d7cb0-a417-4f80-a1d7-1f8eb6a7c7a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499821674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.499821674 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3444682198 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 38704323 ps |
CPU time | 0.75 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-71c48284-564f-44de-a44e-71e54d88eb9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444682198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3444682198 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2842862579 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 76090758 ps |
CPU time | 0.87 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:07 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-324d0d61-1b8e-4b57-80d1-e4d7ae26df02 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842862579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2842862579 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3895843438 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 1204013092 ps |
CPU time | 7.83 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:15 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-bcf929c3-1d59-4fb0-9d51-e0fa9adf3485 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895843438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3895843438 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3343952101 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 29344495878 ps |
CPU time | 44.73 seconds |
Started | Aug 10 05:02:04 PM PDT 24 |
Finished | Aug 10 05:02:49 PM PDT 24 |
Peak memory | 222088 kb |
Host | smart-777f95e6-d9d3-4c34-8f57-66f5c4b2dedd |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343952101 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3343952101 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.422290117 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 93125756 ps |
CPU time | 2.67 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:10 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-e69a5cc1-f1bf-49a1-8b7b-d051c796aceb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422290117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.422290117 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3356000631 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 8633267949 ps |
CPU time | 22.6 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:33 PM PDT 24 |
Peak memory | 214020 kb |
Host | smart-2a382d26-0579-479a-b6e0-0e104ca455f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356000631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3356000631 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4141175015 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 6800758681 ps |
CPU time | 32.15 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-d3d6553a-a607-4375-838d-65f14c5eb27f |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141175015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.4141175015 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4075278987 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 5168414597 ps |
CPU time | 66.11 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:03:12 PM PDT 24 |
Peak memory | 205672 kb |
Host | smart-9e01d416-49fb-4804-a8d4-f9cfb66828f0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075278987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4075278987 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.879823303 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 397203886 ps |
CPU time | 2.45 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:08 PM PDT 24 |
Peak memory | 213784 kb |
Host | smart-6bb50dbd-fd27-4c65-938a-9bdeb4fd0c00 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879823303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.879823303 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1641986882 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 365029312 ps |
CPU time | 2.43 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 213964 kb |
Host | smart-3e265433-8546-4bb7-a5c0-02924cbc35ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641986882 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1641986882 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3889279050 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 63356358 ps |
CPU time | 1.66 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-c46578ff-9ddf-4637-9b1f-4af49e331198 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889279050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3889279050 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2377750371 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 19044479521 ps |
CPU time | 17.13 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:28 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-71e0dc61-a961-406f-9b0a-d028a0d73c28 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377750371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.2377750371 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.262896807 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 37303587541 ps |
CPU time | 27.06 seconds |
Started | Aug 10 05:02:12 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-0ca61276-da68-49af-a9eb-f3c6695bb383 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262896807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r v_dm_jtag_dmi_csr_bit_bash.262896807 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1486591646 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 2556243104 ps |
CPU time | 4.38 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:15 PM PDT 24 |
Peak memory | 205768 kb |
Host | smart-60878a1b-65dd-4bf3-99d4-0d4b1229f3c5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486591646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.1486591646 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3839048018 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 9016087906 ps |
CPU time | 6.28 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:14 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-1efd5bc7-bdc4-42ef-850a-b55fac367375 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839048018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3 839048018 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3893033608 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 484335391 ps |
CPU time | 1.24 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:11 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-3cfb37c9-81cd-487a-90b2-76f696a892cd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893033608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3893033608 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1583706352 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 13479010152 ps |
CPU time | 10.02 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:16 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-6b0bbce8-2f59-467f-91f2-ca9da70304b6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583706352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1583706352 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1754212284 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 710569142 ps |
CPU time | 2.53 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:13 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-872d416b-822f-4b40-be7e-7116d9c3c173 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754212284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1754212284 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3833021557 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 117082028 ps |
CPU time | 0.99 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:02:11 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-c8011b23-cd5a-4733-b01e-4315a9df1d92 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833021557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3 833021557 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1348896974 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 126760041 ps |
CPU time | 0.97 seconds |
Started | Aug 10 05:02:05 PM PDT 24 |
Finished | Aug 10 05:02:06 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-470f82a5-fef2-47dc-92fc-8203964e7cfe |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348896974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1348896974 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3419101456 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 123012070 ps |
CPU time | 0.76 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-02a5cef6-c62a-411c-9a39-a36390e928d1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419101456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3419101456 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2904394146 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 2830948606 ps |
CPU time | 9.22 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:16 PM PDT 24 |
Peak memory | 205728 kb |
Host | smart-4d8bfd74-cc07-43d2-99c9-f375933f4d18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904394146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.2904394146 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.320332705 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 25979361181 ps |
CPU time | 75.81 seconds |
Started | Aug 10 05:02:10 PM PDT 24 |
Finished | Aug 10 05:03:26 PM PDT 24 |
Peak memory | 221528 kb |
Host | smart-f2af7553-af01-4d8b-9f8d-5514edd2a0b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320332705 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.320332705 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.198510048 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 200690593 ps |
CPU time | 3.93 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:11 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-1be55f95-f325-4ca4-9f8f-70aef9958791 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198510048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.198510048 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.167322949 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 7858643285 ps |
CPU time | 21.18 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:29 PM PDT 24 |
Peak memory | 213952 kb |
Host | smart-0ddfe870-ab63-498a-8cd5-cbbe1de4475a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167322949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.167322949 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3441261845 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 1099233269 ps |
CPU time | 65.1 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:03:13 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-b2e3b8c4-4055-4d82-a472-2c591ea2edb7 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441261845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.3441261845 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2039505458 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 1497189526 ps |
CPU time | 28.43 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:50 PM PDT 24 |
Peak memory | 205572 kb |
Host | smart-2478200f-3268-4315-8290-45729bb9e06d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039505458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2039505458 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.86032444 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 230946939 ps |
CPU time | 1.55 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 213764 kb |
Host | smart-a961d045-5320-421b-8ec1-729e7d762ad0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86032444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.86032444 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1940684211 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 1139818494 ps |
CPU time | 2.65 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 218620 kb |
Host | smart-2e459686-ad7a-483a-95d7-62c2bb228de5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940684211 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1940684211 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1787629769 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 93546572 ps |
CPU time | 1.59 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-f70ae0ce-0e27-4af5-ba1d-7da4946e22ab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787629769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1787629769 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3603226296 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 47449469212 ps |
CPU time | 56.49 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:03:18 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-b89b4e97-9f61-4870-a3a0-0a017627cf2c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603226296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3603226296 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.126661736 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 25535619124 ps |
CPU time | 74.23 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:03:38 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-237062c3-5251-4311-b98f-5bdd1cfd12fa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126661736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r v_dm_jtag_dmi_csr_bit_bash.126661736 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3422298715 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3844829863 ps |
CPU time | 2.17 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205756 kb |
Host | smart-2d3d8ec1-5096-4af5-a865-1df00c9912fb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422298715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.3422298715 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1760721331 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 2295589436 ps |
CPU time | 2.78 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:26 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-05d607c1-0378-43df-93c6-3a6c878acf72 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760721331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1 760721331 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3943858197 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 347600953 ps |
CPU time | 1.58 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-be85e012-f99b-4522-97e7-1f85481b176d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943858197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.3943858197 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2387742174 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 8144543397 ps |
CPU time | 6.17 seconds |
Started | Aug 10 05:02:07 PM PDT 24 |
Finished | Aug 10 05:02:13 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-bb669bc2-ea11-4c48-a695-bff8bf234476 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387742174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2387742174 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2935623972 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 347248057 ps |
CPU time | 1.62 seconds |
Started | Aug 10 05:02:08 PM PDT 24 |
Finished | Aug 10 05:02:09 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-c208ec0c-c9e2-44dd-bf84-a0bb76087799 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935623972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.2935623972 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2300817614 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 120432993 ps |
CPU time | 0.78 seconds |
Started | Aug 10 05:02:06 PM PDT 24 |
Finished | Aug 10 05:02:07 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-455d14de-fb6f-4b0b-a5f1-0dd3af3b09bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300817614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 300817614 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3416331704 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 49565995 ps |
CPU time | 0.73 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:21 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-88da0183-eaab-4eed-a244-b2750abc2699 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416331704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.3416331704 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1433076340 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 57537292 ps |
CPU time | 0.77 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:24 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-b39dd06f-58ec-4fee-bbdf-b6891c7a9a0a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433076340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1433076340 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3289972634 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 887683358 ps |
CPU time | 7.6 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:30 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-25e89588-34db-4afa-b2f6-60808d27fc2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289972634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.3289972634 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2515108468 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 23982235127 ps |
CPU time | 45.28 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:03:09 PM PDT 24 |
Peak memory | 222268 kb |
Host | smart-a7014d7e-286c-4f4d-9229-66c3c62ce668 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515108468 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2515108468 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4257381587 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 111795763 ps |
CPU time | 4.29 seconds |
Started | Aug 10 05:02:19 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 213940 kb |
Host | smart-10de1fe9-4c30-4492-9bce-3fa0e4080639 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257381587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4257381587 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2541676363 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 1466587288 ps |
CPU time | 10.79 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:32 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-3d3f68a4-fe26-4fbf-ba55-4aa3ed144401 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541676363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2541676363 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4170999517 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 413558847 ps |
CPU time | 4.85 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:27 PM PDT 24 |
Peak memory | 220276 kb |
Host | smart-0d72d5b1-285e-4368-b7f3-61075df5f096 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170999517 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4170999517 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3303083892 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 582571089 ps |
CPU time | 2.21 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:26 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-4d48f4a8-c120-4e94-8105-74437b847284 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303083892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3303083892 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4174745017 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 67249790528 ps |
CPU time | 182.78 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:05:23 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-5d20b103-49cf-45e1-ad71-4d492c7df061 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174745017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.4174745017 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3223154485 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 13805004603 ps |
CPU time | 10.06 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:32 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-722e2550-a710-4cbe-9056-0da45c761218 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223154485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 223154485 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2486853300 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 84737677 ps |
CPU time | 0.87 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-a74e28dc-8cd6-4c29-86e0-1e783120f663 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486853300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 486853300 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.624594280 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 203063244 ps |
CPU time | 6.7 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:29 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-7633ae88-070e-4231-83b1-dabbd4eb6b1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624594280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c sr_outstanding.624594280 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3620446802 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 32265756043 ps |
CPU time | 31.29 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:55 PM PDT 24 |
Peak memory | 220340 kb |
Host | smart-5d7bf5d7-ea60-44ab-bc93-5069eb264b27 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620446802 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3620446802 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2724662241 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 201584640 ps |
CPU time | 5.39 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:26 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-403da4a5-df31-4f8b-9485-2089a67b12e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724662241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2724662241 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2212644345 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 3321883489 ps |
CPU time | 19.19 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:41 PM PDT 24 |
Peak memory | 214128 kb |
Host | smart-7a98cb7b-d606-4587-b4ea-b525876a0a4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212644345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2212644345 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3691335016 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 510967060 ps |
CPU time | 4.21 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 222004 kb |
Host | smart-8d9d7d02-62db-45f1-9388-b8ebeda49067 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691335016 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3691335016 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3326948565 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 161588056 ps |
CPU time | 1.64 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:24 PM PDT 24 |
Peak memory | 213824 kb |
Host | smart-627e69e8-14be-4459-91ba-513facf0b442 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326948565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3326948565 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1909240336 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 7953700420 ps |
CPU time | 7.61 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:28 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-d03b814b-1e86-4fb7-9f29-ffc79765d6a2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909240336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1909240336 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2853225685 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 5017292474 ps |
CPU time | 3.75 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:24 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-bd0de53d-f0ce-4ed3-b37d-8582ca074f03 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853225685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 853225685 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2295543510 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 225292851 ps |
CPU time | 0.87 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:21 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-9cd6a658-ca7f-4f9f-bf18-12c61e22d5fa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295543510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2 295543510 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.355903495 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 702400293 ps |
CPU time | 7.84 seconds |
Started | Aug 10 05:02:19 PM PDT 24 |
Finished | Aug 10 05:02:27 PM PDT 24 |
Peak memory | 205572 kb |
Host | smart-396369c2-9b9f-4d2f-b603-8128d6bdfc45 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355903495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.355903495 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.572887495 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 18794395409 ps |
CPU time | 56.15 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:03:18 PM PDT 24 |
Peak memory | 219788 kb |
Host | smart-cd89fe55-c6be-4e8d-baad-8e117c7de9e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572887495 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.572887495 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3297964437 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 159226075 ps |
CPU time | 2.65 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-ebe59b42-b555-4450-8705-f7a728e539f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297964437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3297964437 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.484263188 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1606705714 ps |
CPU time | 12.65 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:35 PM PDT 24 |
Peak memory | 213844 kb |
Host | smart-bcd534d6-a068-4a56-9d92-7b02fa52b4bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484263188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.484263188 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4136698067 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 95745421 ps |
CPU time | 1.93 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 213972 kb |
Host | smart-1f399d98-a894-49c1-90af-d00e79eaa1e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136698067 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.4136698067 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1113426981 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 251155687 ps |
CPU time | 1.65 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:22 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-ab0b468c-bbce-4810-abe9-5e2484451175 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113426981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1113426981 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3881831000 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 33769746931 ps |
CPU time | 16.38 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:37 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-b6fce430-4e05-4b58-8def-c66446d9b4e5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881831000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.3881831000 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3158106458 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 6763110162 ps |
CPU time | 5.79 seconds |
Started | Aug 10 05:02:24 PM PDT 24 |
Finished | Aug 10 05:02:30 PM PDT 24 |
Peak memory | 205628 kb |
Host | smart-c8ee5c03-109e-41d2-b192-f8ea2abdc4d4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158106458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 158106458 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2075106912 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 1008388680 ps |
CPU time | 1.37 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-28d96605-6f9e-4e82-bdf3-793bfe00d33d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075106912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2 075106912 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4004694592 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 820560808 ps |
CPU time | 7.31 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:29 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-0f0369a6-9bbb-4e0a-bd8d-a6d43c3e4466 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004694592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.4004694592 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2316221366 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 15708883597 ps |
CPU time | 51.39 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:03:13 PM PDT 24 |
Peak memory | 221616 kb |
Host | smart-ae8c93e3-60ff-46cf-b1fb-c5fe2b7a7568 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316221366 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2316221366 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1690908271 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 132042937 ps |
CPU time | 2.95 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:26 PM PDT 24 |
Peak memory | 213968 kb |
Host | smart-9d078add-51a5-4d81-8266-6f1cba378757 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690908271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1690908271 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.266073917 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 1394804745 ps |
CPU time | 9.92 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:31 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-d366e711-8432-4e03-8166-ab2f88b08096 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266073917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.266073917 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2043837230 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 717067400 ps |
CPU time | 2.4 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 215568 kb |
Host | smart-c8ba9bc7-2458-4ff4-8e41-3bbc481f4740 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043837230 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2043837230 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1878234745 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 231679340 ps |
CPU time | 2.24 seconds |
Started | Aug 10 05:02:24 PM PDT 24 |
Finished | Aug 10 05:02:26 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-ed4e8193-4c9b-4d1a-982d-b3c3b8b76cb4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878234745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1878234745 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2556892362 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 7738744464 ps |
CPU time | 20.67 seconds |
Started | Aug 10 05:02:18 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 205504 kb |
Host | smart-4cf5bf47-b0e2-44cd-b5d3-ed126b35fb9a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556892362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.2556892362 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3435011815 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1945763084 ps |
CPU time | 4.37 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:27 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-c503995b-e983-464b-9960-17ab43bca1a7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435011815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 435011815 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3327612480 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 169010248 ps |
CPU time | 0.75 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:24 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-85e9a8db-3091-4980-b360-64bc63e02cef |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327612480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 327612480 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3490729042 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 572883609 ps |
CPU time | 7.76 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:28 PM PDT 24 |
Peak memory | 205700 kb |
Host | smart-d1741875-cf90-4a4c-b72b-2b9ed70c8617 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490729042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3490729042 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.791941878 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 22197991916 ps |
CPU time | 19.67 seconds |
Started | Aug 10 05:02:19 PM PDT 24 |
Finished | Aug 10 05:02:39 PM PDT 24 |
Peak memory | 214776 kb |
Host | smart-f0286a32-c300-42e7-a520-ff974833b9f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791941878 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.791941878 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3588565127 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 191878750 ps |
CPU time | 3.87 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 213956 kb |
Host | smart-ba56cb92-7b8f-46a9-8bc4-f547a4b81514 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588565127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3588565127 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.712512085 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 123949278 ps |
CPU time | 4.87 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:27 PM PDT 24 |
Peak memory | 219364 kb |
Host | smart-74594975-557c-42f7-9309-d8afa4d972e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712512085 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.712512085 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3182198197 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 213221139 ps |
CPU time | 1.67 seconds |
Started | Aug 10 05:02:23 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-a9d3b90f-ac8c-49bc-b848-80b947ac8e40 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182198197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3182198197 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1161647330 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 31495923942 ps |
CPU time | 45.55 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:03:08 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-0b31cf11-23dd-4a91-b39e-77e790aeaf1a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161647330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.1161647330 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1680825743 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 2075367065 ps |
CPU time | 2.71 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:25 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-d81cde35-7ea7-4139-803c-ab6ca0f77db2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680825743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1 680825743 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1454479989 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 503822275 ps |
CPU time | 2.02 seconds |
Started | Aug 10 05:02:21 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-4b0bf53a-56f4-4c07-946d-fa40e13c50ae |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454479989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 454479989 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1248451722 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 1205745982 ps |
CPU time | 4.42 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:26 PM PDT 24 |
Peak memory | 205556 kb |
Host | smart-f2efd804-8ffb-4fdc-848c-eae3f607636f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248451722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.1248451722 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3261361084 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 29765311949 ps |
CPU time | 28.28 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:50 PM PDT 24 |
Peak memory | 222040 kb |
Host | smart-42ef7ec5-137b-4ff5-9c62-2e2e2a20f313 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261361084 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3261361084 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.27602104 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 234502672 ps |
CPU time | 2.94 seconds |
Started | Aug 10 05:02:20 PM PDT 24 |
Finished | Aug 10 05:02:23 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-5339f95c-26c9-4602-bcc5-a0adce59337f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.27602104 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2478016491 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 3187145275 ps |
CPU time | 20.58 seconds |
Started | Aug 10 05:02:22 PM PDT 24 |
Finished | Aug 10 05:02:42 PM PDT 24 |
Peak memory | 221760 kb |
Host | smart-a88a99f1-71ef-4c6c-85e8-1ed1170fcb93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478016491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2478016491 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.566509903 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 74189947 ps |
CPU time | 0.73 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:56:51 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-57d12bcc-df31-46a1-ac55-5ed0222a7c2b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566509903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.566509903 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.875437571 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 55568882578 ps |
CPU time | 53.09 seconds |
Started | Aug 10 04:56:43 PM PDT 24 |
Finished | Aug 10 04:57:36 PM PDT 24 |
Peak memory | 219620 kb |
Host | smart-1a5ca2d3-ed35-45df-a5f7-3e0e0345aa4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875437571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.875437571 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2437779079 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 978588179 ps |
CPU time | 1.59 seconds |
Started | Aug 10 04:56:42 PM PDT 24 |
Finished | Aug 10 04:56:44 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-5f793373-3258-4527-997b-856492c921f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437779079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2437779079 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2661027511 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 389666602 ps |
CPU time | 1.8 seconds |
Started | Aug 10 04:56:40 PM PDT 24 |
Finished | Aug 10 04:56:42 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-ec52b910-a3df-4e01-9ea9-b014b367b68a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661027511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2661027511 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1489001113 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 308226224 ps |
CPU time | 0.91 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:43 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-9934d662-2285-401b-bdb7-79145dd55e42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489001113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1489001113 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.761701521 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 133871503 ps |
CPU time | 0.97 seconds |
Started | Aug 10 04:56:44 PM PDT 24 |
Finished | Aug 10 04:56:46 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-16b07695-1324-4927-8c76-cf74ddf903d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761701521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.761701521 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.2658927661 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 287583383 ps |
CPU time | 0.85 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 215488 kb |
Host | smart-9e64da31-8128-4ad6-a4ae-420f0d8a9c9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658927661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2658927661 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3084989967 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 2103931014 ps |
CPU time | 6.96 seconds |
Started | Aug 10 04:56:43 PM PDT 24 |
Finished | Aug 10 04:56:50 PM PDT 24 |
Peak memory | 213844 kb |
Host | smart-de34746d-d4dc-4828-a8d3-0934f9f28f97 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3084989967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.3084989967 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.2472601135 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 551681175 ps |
CPU time | 1.04 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-12834cfa-6c1f-4045-b627-bae240f2a638 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472601135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2472601135 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.4142007262 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1036865200 ps |
CPU time | 1.9 seconds |
Started | Aug 10 04:56:43 PM PDT 24 |
Finished | Aug 10 04:56:45 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-b7e32ddf-75a8-41ca-bb8c-cbc459c2b168 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142007262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.4142007262 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.3784685802 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 175495036 ps |
CPU time | 0.98 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:42 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-0c33758a-011f-402a-a346-ea6f2123a276 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784685802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3784685802 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3396130379 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 586278183 ps |
CPU time | 1.48 seconds |
Started | Aug 10 04:56:42 PM PDT 24 |
Finished | Aug 10 04:56:43 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-649615a5-88c9-470d-b7b7-f22d2cccf97c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396130379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3396130379 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3143627628 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 987138002 ps |
CPU time | 3.44 seconds |
Started | Aug 10 04:56:42 PM PDT 24 |
Finished | Aug 10 04:56:46 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-9f4ed7f8-a8d0-444c-a683-758f17ebb53c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143627628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3143627628 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1475801758 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 150701092 ps |
CPU time | 1.14 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:42 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-7ff79883-4131-418f-b84e-ab53488db061 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475801758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1475801758 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3771167689 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 109922741 ps |
CPU time | 0.8 seconds |
Started | Aug 10 04:56:42 PM PDT 24 |
Finished | Aug 10 04:56:43 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-b308f006-10ac-483c-a29b-d7fcaa2751be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771167689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3771167689 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2270083593 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 568338043 ps |
CPU time | 1.51 seconds |
Started | Aug 10 04:56:40 PM PDT 24 |
Finished | Aug 10 04:56:42 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-20653cdf-926a-458d-a3be-e941c8719e09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270083593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2270083593 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2219234673 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 428749743 ps |
CPU time | 1.18 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:42 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-cf4b37b3-573c-4d0b-b389-52b8eab3b342 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219234673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2219234673 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.1093394468 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 221101115 ps |
CPU time | 0.83 seconds |
Started | Aug 10 04:56:41 PM PDT 24 |
Finished | Aug 10 04:56:42 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-80cc912d-acd9-4336-9b80-b109c08f8d9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093394468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1093394468 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2588630491 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 161589235 ps |
CPU time | 0.97 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-cde87899-5148-400a-8876-03404b65def1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588630491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2588630491 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2727727337 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 1317031823 ps |
CPU time | 4.31 seconds |
Started | Aug 10 04:56:38 PM PDT 24 |
Finished | Aug 10 04:56:43 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-d8cd0966-5e95-4299-895e-3843072a2a22 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727727337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2727727337 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.81726593 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 928761693 ps |
CPU time | 1.49 seconds |
Started | Aug 10 04:56:42 PM PDT 24 |
Finished | Aug 10 04:56:44 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-a393989e-509a-45c9-9e56-b71327694ce2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81726593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.81726593 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1751036188 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 4492442023 ps |
CPU time | 13.16 seconds |
Started | Aug 10 04:56:44 PM PDT 24 |
Finished | Aug 10 04:56:57 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-61101e84-7dee-412c-afc4-3368cc72336a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751036188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1751036188 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.3477844010 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 172966552 ps |
CPU time | 0.74 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-b155cb8a-433a-4eba-a643-36b78c1e4e4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477844010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3477844010 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.3932873081 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 103341803 ps |
CPU time | 0.68 seconds |
Started | Aug 10 04:56:49 PM PDT 24 |
Finished | Aug 10 04:56:50 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-8b7b722b-2bea-41b0-9360-7ea981ac9db8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932873081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3932873081 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2469634870 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 759013461 ps |
CPU time | 1.51 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 213756 kb |
Host | smart-718634fb-46c6-452a-8304-0095eeab98a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469634870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2469634870 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.191825378 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 155949600 ps |
CPU time | 1.15 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:52 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-09eb20e1-ac61-4498-870f-a5677a2cfa46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191825378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.191825378 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2901653112 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 298513864 ps |
CPU time | 1.48 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-55f0735e-890f-42dc-9479-b2a452bbd8c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901653112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2901653112 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3601628272 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 400184458 ps |
CPU time | 1.63 seconds |
Started | Aug 10 04:56:53 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-81a915a2-acdc-4745-abf5-b7a927bfbd1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601628272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3601628272 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3976715606 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 565329407 ps |
CPU time | 0.96 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:52 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-53f2efaf-54cc-4827-96e6-108e4fe693ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976715606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3976715606 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.339644418 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 86982801 ps |
CPU time | 0.8 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:52 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-a0718283-d91c-453b-b629-9b797fdf5a44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339644418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.339644418 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2297815036 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 307226608 ps |
CPU time | 0.89 seconds |
Started | Aug 10 04:56:53 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-36c5e368-663f-4be2-9447-4ee2853c9df8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297815036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2297815036 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.771707895 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 8080547491 ps |
CPU time | 23.05 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:57:14 PM PDT 24 |
Peak memory | 213900 kb |
Host | smart-38f17708-6083-453e-aaf0-a99707a65ae5 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=771707895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl _access.771707895 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2804272827 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 526777808 ps |
CPU time | 1.04 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:56:51 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-c05e9a72-b946-4eaa-a594-08342bfb0631 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804272827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2804272827 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.3689589575 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 337503492 ps |
CPU time | 0.99 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-a4f68ba9-15f6-40db-b6ee-0cb74d527366 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689589575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3689589575 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3305045240 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 114127408 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:52 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-aa762cf4-83fe-4508-a351-3eea1917616f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305045240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3305045240 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3874702530 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 451178246 ps |
CPU time | 1.39 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-9743e2c6-b03d-4452-8914-cdf3b2b41de7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3874702530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3874702530 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1128318098 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 148135442 ps |
CPU time | 0.88 seconds |
Started | Aug 10 04:56:49 PM PDT 24 |
Finished | Aug 10 04:56:50 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-31ce9df5-33ae-461a-977c-161058f79fd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128318098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1128318098 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.52819799 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 105443564 ps |
CPU time | 0.94 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-7976e2d1-d43d-41b6-9893-1c44adfbaba9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52819799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.52819799 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3145196599 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 265186361 ps |
CPU time | 0.87 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:56:51 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-09b6a337-6ba2-48af-bf99-63eca7ec0353 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145196599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3145196599 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.319438435 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 2327376815 ps |
CPU time | 2.63 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-083c7eb8-f31e-479f-bd42-2f69b75f647f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319438435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.319438435 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.1064980381 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 681351213 ps |
CPU time | 1.5 seconds |
Started | Aug 10 04:56:49 PM PDT 24 |
Finished | Aug 10 04:56:51 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-fcebd8e8-51ba-40c1-a0d2-aa2286a6a65c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064980381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1064980381 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3015944911 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 284620945 ps |
CPU time | 1.08 seconds |
Started | Aug 10 04:56:53 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-e6ceaf4c-8c9a-4c02-a68a-e625ae37b500 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015944911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3015944911 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.608704722 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 97582282 ps |
CPU time | 0.99 seconds |
Started | Aug 10 04:56:49 PM PDT 24 |
Finished | Aug 10 04:56:50 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-ef91911f-7a58-4455-9089-81ea5b65f2e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608704722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.608704722 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1718713711 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 4861770478 ps |
CPU time | 3.7 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:56 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-b44642b1-660c-4f62-bd52-53ec0eb012af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718713711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1718713711 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.690241290 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 2168611034 ps |
CPU time | 4.35 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:56 PM PDT 24 |
Peak memory | 205820 kb |
Host | smart-7600cee4-0538-4f21-a2dd-56455cb495ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690241290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.690241290 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.2964109970 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 276093893 ps |
CPU time | 1.33 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:52 PM PDT 24 |
Peak memory | 228904 kb |
Host | smart-11d3d57d-2fd8-4eb3-bca0-f2995bc13b25 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964109970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2964109970 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.2924945042 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2856492047 ps |
CPU time | 8.58 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:59 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-2c5d028b-f53f-436c-a961-949a79582910 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924945042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2924945042 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.297499981 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 70583080454 ps |
CPU time | 799.77 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 05:10:12 PM PDT 24 |
Peak memory | 230804 kb |
Host | smart-0f438cf9-9b62-4c2c-bef0-e09bffd37aec |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297499981 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.297499981 |
Directory | /workspace/1.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.612750509 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 93317149 ps |
CPU time | 0.96 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:11 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-f79f655d-f981-42fc-8f6a-8bbaadcc85aa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612750509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.612750509 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1408857289 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1359283755 ps |
CPU time | 1.6 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:11 PM PDT 24 |
Peak memory | 214256 kb |
Host | smart-13bd3b38-79ea-47aa-b937-e6b5fe176470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408857289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1408857289 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2075510110 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 7408993959 ps |
CPU time | 13.22 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:23 PM PDT 24 |
Peak memory | 222000 kb |
Host | smart-48c56cdd-9a61-4eb8-be1e-d2e106076c69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075510110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2075510110 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2810141930 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 2430156162 ps |
CPU time | 3.39 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:13 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-7eae6749-207d-4351-9188-7a5162e15fd3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2810141930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2810141930 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.2858660990 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 3005742498 ps |
CPU time | 9.1 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:20 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-a9ec770e-27ce-482b-9db8-9eae7145c62d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858660990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2858660990 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1429884502 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 76767755 ps |
CPU time | 0.88 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:10 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-78e1a686-a403-47a6-864c-5e85774a59da |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429884502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1429884502 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1766091811 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 4303814841 ps |
CPU time | 9.09 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:19 PM PDT 24 |
Peak memory | 216112 kb |
Host | smart-2f310d7f-014b-4e02-9911-a77e4d72a897 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766091811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1766091811 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2246739211 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 3062123969 ps |
CPU time | 10.51 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:21 PM PDT 24 |
Peak memory | 213996 kb |
Host | smart-470914e3-bca3-45c1-ab16-f58d2e41ed5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246739211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2246739211 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2386573652 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1637608011 ps |
CPU time | 2.02 seconds |
Started | Aug 10 04:57:12 PM PDT 24 |
Finished | Aug 10 04:57:14 PM PDT 24 |
Peak memory | 205620 kb |
Host | smart-cc62bc3d-cbe5-43aa-811d-3697d989d9c1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2386573652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.2386573652 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.4057418846 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 4744513345 ps |
CPU time | 13.42 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:23 PM PDT 24 |
Peak memory | 205704 kb |
Host | smart-678d8dd1-2930-4b1d-90b0-826476d6e8e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057418846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.4057418846 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.30157402 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 32654070 ps |
CPU time | 0.75 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:10 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-b2eb2a11-2a5f-4205-bff2-b55baef7bc2b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30157402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.30157402 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2871363417 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 5517983526 ps |
CPU time | 14.78 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:25 PM PDT 24 |
Peak memory | 213960 kb |
Host | smart-091c04d1-631b-497b-a158-15fd6b1afd39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871363417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2871363417 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4243547756 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1504246741 ps |
CPU time | 1.34 seconds |
Started | Aug 10 04:57:13 PM PDT 24 |
Finished | Aug 10 04:57:14 PM PDT 24 |
Peak memory | 213876 kb |
Host | smart-0e118cb6-ff92-405d-b5e8-e38579dad414 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243547756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4243547756 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.492735216 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 9165757509 ps |
CPU time | 27.73 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:38 PM PDT 24 |
Peak memory | 213952 kb |
Host | smart-d65a2473-4997-4a72-bdba-dfaeed013a20 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=492735216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t l_access.492735216 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.2097664778 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 2197019856 ps |
CPU time | 6.7 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:16 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-f8bdd534-bd17-40cf-92ea-f8e251c9c5de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097664778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2097664778 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.3692594118 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 4667599685 ps |
CPU time | 14.24 seconds |
Started | Aug 10 04:57:11 PM PDT 24 |
Finished | Aug 10 04:57:25 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-4f45aa81-6b10-4006-b16b-deb3a72aaebc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692594118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3692594118 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.4024112201 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 123529674 ps |
CPU time | 0.78 seconds |
Started | Aug 10 04:57:21 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-9c23f992-b0c1-4c29-b130-98e022ba94a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024112201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4024112201 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1302657506 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 4341419683 ps |
CPU time | 7.47 seconds |
Started | Aug 10 04:57:12 PM PDT 24 |
Finished | Aug 10 04:57:20 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-2b5c201c-3b33-4a5c-96d5-9adb0ce91ee6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302657506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1302657506 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4036094471 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 1952225108 ps |
CPU time | 3.98 seconds |
Started | Aug 10 04:57:08 PM PDT 24 |
Finished | Aug 10 04:57:12 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-684b6c21-551b-4bb4-9f78-ec215bedb8cf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4036094471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.4036094471 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.4111106256 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 2860660180 ps |
CPU time | 8.24 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:17 PM PDT 24 |
Peak memory | 205992 kb |
Host | smart-ddd3d1ec-4624-4b58-b092-e69a5467fdb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111106256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4111106256 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.1868497823 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 3327326322 ps |
CPU time | 9.15 seconds |
Started | Aug 10 04:57:11 PM PDT 24 |
Finished | Aug 10 04:57:20 PM PDT 24 |
Peak memory | 213760 kb |
Host | smart-7ed88f79-0cfe-451c-85de-5e4950b57833 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868497823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1868497823 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2538176590 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 106543090 ps |
CPU time | 1.02 seconds |
Started | Aug 10 04:57:22 PM PDT 24 |
Finished | Aug 10 04:57:23 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-2c7b8aaa-cc88-443c-8673-7842e3ed1603 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538176590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2538176590 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2363746780 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 1486035208 ps |
CPU time | 3.77 seconds |
Started | Aug 10 04:57:20 PM PDT 24 |
Finished | Aug 10 04:57:24 PM PDT 24 |
Peak memory | 214776 kb |
Host | smart-a4ffcc29-2191-4a56-8970-80be192187ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363746780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2363746780 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2049608081 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 4026071871 ps |
CPU time | 7.42 seconds |
Started | Aug 10 04:57:20 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-9e5efe63-751a-462a-a5d3-df5bc6650b6b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2049608081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.2049608081 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.3808601381 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 3107434900 ps |
CPU time | 5.08 seconds |
Started | Aug 10 04:57:24 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 205708 kb |
Host | smart-61e65854-75a1-459e-b672-13042ce485e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808601381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3808601381 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.995143955 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 4792067826 ps |
CPU time | 12.74 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:32 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-e19ce595-cd7b-4e49-9c15-d66dd0ad1536 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995143955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.995143955 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.3890870373 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 180583959 ps |
CPU time | 0.8 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:20 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-90675516-c7e1-44c5-80a2-ed49fd3a040b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890870373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3890870373 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3403505305 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 60123218206 ps |
CPU time | 78.21 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:58:37 PM PDT 24 |
Peak memory | 214040 kb |
Host | smart-9749e4e2-620e-4803-8399-04305d8eab46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403505305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3403505305 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2169443567 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1800298374 ps |
CPU time | 2.41 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:21 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-27c0f93e-47fa-475b-a71f-938bba33c7ce |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2169443567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.2169443567 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.884894098 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 2174864247 ps |
CPU time | 6.64 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:26 PM PDT 24 |
Peak memory | 205764 kb |
Host | smart-d5b2be35-622c-42e5-a492-866951ce7c2b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884894098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.884894098 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.3286886657 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 2768011976 ps |
CPU time | 2.73 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-90111729-d844-4c99-8d4f-559d3e07b27e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286886657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3286886657 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.431292704 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 78843415 ps |
CPU time | 0.85 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:19 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-ef9b2e57-17b8-411c-a04b-e98b95bdbd4a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431292704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.431292704 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.595922767 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 6629160920 ps |
CPU time | 10.75 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-be409439-5776-41c2-8d30-f3a6bc351f2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595922767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.595922767 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.897196515 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2623568773 ps |
CPU time | 8.51 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:27 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-39607c9c-5f51-48e8-aba3-7d7aad591bbb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=897196515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t l_access.897196515 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.3857815988 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 12090072384 ps |
CPU time | 10.11 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205748 kb |
Host | smart-e4559ba8-4815-4275-ab79-45df99415643 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857815988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3857815988 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.2957342680 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 9566948083 ps |
CPU time | 3.92 seconds |
Started | Aug 10 04:57:21 PM PDT 24 |
Finished | Aug 10 04:57:26 PM PDT 24 |
Peak memory | 214008 kb |
Host | smart-b303b389-a711-4cec-b85c-3118487e278d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957342680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2957342680 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2266809059 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 42136375 ps |
CPU time | 0.8 seconds |
Started | Aug 10 04:57:24 PM PDT 24 |
Finished | Aug 10 04:57:25 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-e4779db0-a999-40b1-a9ea-386c8fe6b176 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266809059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2266809059 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.84541329 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 5720598643 ps |
CPU time | 7.17 seconds |
Started | Aug 10 04:57:22 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 221976 kb |
Host | smart-62cf658b-4005-47fa-9dd8-959f5fa7eb9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84541329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.84541329 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2129926314 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1884456015 ps |
CPU time | 3.64 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:21 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-6ddd5416-d79a-451e-b4fc-41461a179ae1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129926314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2129926314 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1806634858 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 767963143 ps |
CPU time | 1.17 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:20 PM PDT 24 |
Peak memory | 205592 kb |
Host | smart-ea60ac08-118c-4a73-96f6-98d8e892b1e8 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1806634858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.1806634858 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.2279173159 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 3542794717 ps |
CPU time | 1.96 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:20 PM PDT 24 |
Peak memory | 205652 kb |
Host | smart-56149435-ce7e-481f-a51b-6966b2443372 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279173159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2279173159 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.319908843 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3803665880 ps |
CPU time | 2.73 seconds |
Started | Aug 10 04:57:24 PM PDT 24 |
Finished | Aug 10 04:57:27 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-7b2ff45f-bf4d-4291-8025-9d3e8ab68ff0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319908843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.319908843 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3953375165 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 75012251 ps |
CPU time | 0.74 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:19 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-ce368b53-e80a-472f-9837-990d938b8bb8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953375165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3953375165 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.369742153 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 6262157519 ps |
CPU time | 3.19 seconds |
Started | Aug 10 04:57:20 PM PDT 24 |
Finished | Aug 10 04:57:23 PM PDT 24 |
Peak memory | 213836 kb |
Host | smart-8da5b98b-8af6-48f6-ba1e-8a6ee97cd43f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369742153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.369742153 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1640018143 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 7497749674 ps |
CPU time | 11.78 seconds |
Started | Aug 10 04:57:22 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 213792 kb |
Host | smart-b16a39df-51dc-431a-b7e0-ebcaac3d7344 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640018143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1640018143 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.700606381 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 10893267954 ps |
CPU time | 9.62 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-578bbbdb-1bb3-40bd-a1b4-5bec87f1e673 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=700606381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t l_access.700606381 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.1830909487 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 4280679970 ps |
CPU time | 2.37 seconds |
Started | Aug 10 04:57:21 PM PDT 24 |
Finished | Aug 10 04:57:23 PM PDT 24 |
Peak memory | 214912 kb |
Host | smart-fac07e4f-2d4a-4f20-8db1-2e1c191ca03f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830909487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1830909487 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.2804364395 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 6147860186 ps |
CPU time | 4.63 seconds |
Started | Aug 10 04:57:23 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-b7f32816-a71a-4032-9e73-49366c9e7927 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804364395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2804364395 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.1792136584 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 57776263 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-5522773b-44b5-493d-add3-2334fc8a35bb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792136584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1792136584 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1327097219 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 52639962791 ps |
CPU time | 143.81 seconds |
Started | Aug 10 04:57:21 PM PDT 24 |
Finished | Aug 10 04:59:45 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-7308b909-f824-4861-8813-45b6d0ecad13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327097219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1327097219 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.4223658999 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 8268931715 ps |
CPU time | 23.09 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:42 PM PDT 24 |
Peak memory | 213944 kb |
Host | smart-1d4183ba-ba74-40f1-a758-2858eafe5d80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223658999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.4223658999 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3690778555 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 6682954726 ps |
CPU time | 9.57 seconds |
Started | Aug 10 04:57:18 PM PDT 24 |
Finished | Aug 10 04:57:27 PM PDT 24 |
Peak memory | 215300 kb |
Host | smart-5bae27e7-8a6f-4198-bb4f-c61004d5fad8 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3690778555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.3690778555 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.2974728479 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 4999182764 ps |
CPU time | 5.11 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:24 PM PDT 24 |
Peak memory | 214036 kb |
Host | smart-4d34999e-1b65-4ec6-90a9-e0c0ee1b748c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974728479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2974728479 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.3294212918 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 8289901058 ps |
CPU time | 3.22 seconds |
Started | Aug 10 04:57:19 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 213772 kb |
Host | smart-0dd472ae-86a2-4de4-8001-9764f0b8f161 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294212918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3294212918 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.67261695 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 74915611 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:56:59 PM PDT 24 |
Finished | Aug 10 04:57:00 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-e64af447-fb82-498b-aedb-1c1191ac68ce |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67261695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.67261695 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2600916330 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 5965725687 ps |
CPU time | 5.77 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:57 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-59a86875-9d4b-4e23-b946-df762926736d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600916330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2600916330 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.560387467 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1591247237 ps |
CPU time | 5.03 seconds |
Started | Aug 10 04:56:53 PM PDT 24 |
Finished | Aug 10 04:56:58 PM PDT 24 |
Peak memory | 221964 kb |
Host | smart-e65f8677-5723-4c94-bcca-ab7fe58afbe8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560387467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.560387467 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3894446484 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 3768347161 ps |
CPU time | 6.21 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:56:56 PM PDT 24 |
Peak memory | 205804 kb |
Host | smart-ad8d3151-b88e-4b67-98d1-d76346e0929d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3894446484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.3894446484 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1788276067 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 283314738 ps |
CPU time | 1.61 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-04247ebf-47b0-4dcc-b358-8412628b6f50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788276067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1788276067 |
Directory | /workspace/2.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.161686185 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 776899606 ps |
CPU time | 1.69 seconds |
Started | Aug 10 04:56:51 PM PDT 24 |
Finished | Aug 10 04:56:53 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-d304a8d3-eff4-418c-a6c3-3af13000a0b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161686185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.161686185 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.664979790 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 674030917 ps |
CPU time | 1.88 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:54 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-4ad00232-a4a8-4280-a977-f3a1427e995b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664979790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.664979790 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.1979824754 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1408124761 ps |
CPU time | 4.79 seconds |
Started | Aug 10 04:56:52 PM PDT 24 |
Finished | Aug 10 04:56:57 PM PDT 24 |
Peak memory | 228824 kb |
Host | smart-8d5a3c9f-c0ed-402b-9fa8-93cc5a85b31b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979824754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1979824754 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.1925159959 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 12346080281 ps |
CPU time | 10.12 seconds |
Started | Aug 10 04:56:50 PM PDT 24 |
Finished | Aug 10 04:57:00 PM PDT 24 |
Peak memory | 213744 kb |
Host | smart-fecba915-9e3b-4769-bce3-cd66454915fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925159959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1925159959 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.3568163127 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 240062151 ps |
CPU time | 0.73 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-3aff51ee-b96c-404a-95e6-71fdae3ca08f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568163127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3568163127 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.3218799093 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 3048504289 ps |
CPU time | 3.22 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:30 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-95183450-7855-4d8f-81df-3a2ff34ba8a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218799093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3218799093 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.2286780089 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 254090421 ps |
CPU time | 0.75 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:31 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-ff1f3326-11be-4c3e-80a0-0546e21df2c2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286780089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2286780089 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.2747984214 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 2296232192 ps |
CPU time | 2.21 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:32 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-e22f9160-8a09-47b3-bf66-4ff128686d36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747984214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2747984214 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.3359551538 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 114218198 ps |
CPU time | 0.74 seconds |
Started | Aug 10 04:57:29 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-92ba43ec-f8dc-4568-b790-7a8e42fcacac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359551538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3359551538 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.493828684 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 41868685 ps |
CPU time | 0.78 seconds |
Started | Aug 10 04:57:28 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-11fe9b2a-8031-43d9-a9a3-76bf9c00ab88 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493828684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.493828684 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.1520953625 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 12621185819 ps |
CPU time | 15.93 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:49 PM PDT 24 |
Peak memory | 213744 kb |
Host | smart-8cf4c96d-9100-4b51-96b5-36809b31346b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520953625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1520953625 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.2629276690 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 144682459 ps |
CPU time | 0.84 seconds |
Started | Aug 10 04:57:29 PM PDT 24 |
Finished | Aug 10 04:57:30 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-cc5a0b9e-de84-48ce-a123-fc01ace64d28 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629276690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2629276690 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.2735973647 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 8447642587 ps |
CPU time | 21.04 seconds |
Started | Aug 10 04:57:29 PM PDT 24 |
Finished | Aug 10 04:57:50 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-3c3e1208-f223-43b1-b0b5-11b588ac85b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735973647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2735973647 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.2376871354 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 35740203 ps |
CPU time | 0.77 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:31 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-8f5113da-64df-4bfe-8601-6dea2c06f59b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376871354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2376871354 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.557206248 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 87856988 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-6f6d30cd-ebc6-4137-9081-95b754c2798e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557206248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.557206248 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.608109018 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 2753858153 ps |
CPU time | 7.38 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:41 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-dc70c9cb-b826-49a1-a31d-d91b6ca6a4ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608109018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.608109018 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.804092020 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 99704484 ps |
CPU time | 0.9 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-a2b94e56-a050-4a11-a230-1356f230fa9a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804092020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.804092020 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.3429076111 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 5069516341 ps |
CPU time | 3.47 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:30 PM PDT 24 |
Peak memory | 213828 kb |
Host | smart-015bdc2d-99e7-4548-a8c9-bcc4baabc851 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429076111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3429076111 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.929832894 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 68892797 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:30 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-82dcfdb4-f7b6-40a0-9295-67983a433696 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929832894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.929832894 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.4051648645 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 4134296246 ps |
CPU time | 12.27 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:43 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-ecf9f7f2-9445-4b9f-bab8-fa676fdd101b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051648645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.4051648645 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.2678705674 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 123662538 ps |
CPU time | 0.73 seconds |
Started | Aug 10 04:57:26 PM PDT 24 |
Finished | Aug 10 04:57:27 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-19c9218e-a490-4f78-92fa-18fa10024321 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678705674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2678705674 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.416427776 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 5897615437 ps |
CPU time | 8.49 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:36 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-d13a55d6-db1a-4dec-993c-4d3a71ab4bcd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416427776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.416427776 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.1230405010 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 74656591 ps |
CPU time | 0.73 seconds |
Started | Aug 10 04:57:06 PM PDT 24 |
Finished | Aug 10 04:57:07 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-e6fd56bb-a493-4d32-87a5-4eafb0899426 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230405010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1230405010 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.935569408 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 49874776735 ps |
CPU time | 76.03 seconds |
Started | Aug 10 04:57:02 PM PDT 24 |
Finished | Aug 10 04:58:18 PM PDT 24 |
Peak memory | 213836 kb |
Host | smart-7e5da271-bca8-42c1-a3d0-36d9d2d2ca9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935569408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.935569408 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.867872389 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 16161833247 ps |
CPU time | 12.77 seconds |
Started | Aug 10 04:56:59 PM PDT 24 |
Finished | Aug 10 04:57:12 PM PDT 24 |
Peak memory | 222060 kb |
Host | smart-dcf23848-85ec-485d-aa7e-1a4e5cdef2dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867872389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.867872389 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1581443834 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 3378153968 ps |
CPU time | 9.95 seconds |
Started | Aug 10 04:56:59 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-72b73a50-506f-4f43-a393-28229be0c6ab |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1581443834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.1581443834 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_halt_resume_whereto.3765567691 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1331625142 ps |
CPU time | 3.84 seconds |
Started | Aug 10 04:57:00 PM PDT 24 |
Finished | Aug 10 04:57:04 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-14a9a40b-50e4-42d2-8c33-3e1b0b10c3ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765567691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3765567691 |
Directory | /workspace/3.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.3676108376 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 156376385 ps |
CPU time | 0.98 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:02 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-09960dde-91b3-4ca2-a0a4-2c3d2a359fdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676108376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3676108376 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.2822116775 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 15760443527 ps |
CPU time | 21.16 seconds |
Started | Aug 10 04:57:00 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 205720 kb |
Host | smart-194a3bb8-82e2-4b99-ba5c-e8c4935744f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822116775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2822116775 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.716140750 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2215625658 ps |
CPU time | 1.77 seconds |
Started | Aug 10 04:57:02 PM PDT 24 |
Finished | Aug 10 04:57:04 PM PDT 24 |
Peak memory | 229608 kb |
Host | smart-e5eff652-5313-4a51-a7be-5776bbe13b7a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716140750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.716140750 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.711439968 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 2148494013 ps |
CPU time | 1.65 seconds |
Started | Aug 10 04:57:02 PM PDT 24 |
Finished | Aug 10 04:57:04 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-9aedb372-c9b4-44b0-93e6-efbaffddd168 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711439968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.711439968 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.1326527414 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 30685486 ps |
CPU time | 0.79 seconds |
Started | Aug 10 04:57:28 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-8d8c17f6-673b-46f7-b64b-29d997d1e44a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326527414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1326527414 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.3236672905 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 2228627913 ps |
CPU time | 4.66 seconds |
Started | Aug 10 04:57:31 PM PDT 24 |
Finished | Aug 10 04:57:35 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-23af4e24-c453-44af-a948-a24530b537fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236672905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3236672905 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.2471490723 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 100974711 ps |
CPU time | 0.87 seconds |
Started | Aug 10 04:57:26 PM PDT 24 |
Finished | Aug 10 04:57:27 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-e2ff67a2-4b65-4235-b7ed-cdd29ccc53cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471490723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2471490723 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1300052346 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 5863755244 ps |
CPU time | 3.24 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:36 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-d2c21ce9-5909-46bc-ad9e-30c2f73659b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300052346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1300052346 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.3484866325 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 130610486 ps |
CPU time | 0.82 seconds |
Started | Aug 10 04:57:28 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-0180d88d-c3f2-40fd-ac62-8a698a3ad111 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484866325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3484866325 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.3883531489 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 5577070216 ps |
CPU time | 4.29 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:37 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-99344e3e-56e3-4c6a-aee6-316a2a1047b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883531489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3883531489 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1292078576 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 110690126 ps |
CPU time | 0.8 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-7696d61a-0850-4f03-90d3-16a3bb89afdc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292078576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1292078576 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.1993374422 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 1420079861 ps |
CPU time | 4.66 seconds |
Started | Aug 10 04:57:26 PM PDT 24 |
Finished | Aug 10 04:57:31 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-9b4dbd88-c80a-4ec0-a276-18cbd658d539 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993374422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1993374422 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.1706484498 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 48769651 ps |
CPU time | 0.79 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-3f2fabae-dcd4-4a4d-87f4-2a78bd5c4b68 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706484498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1706484498 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.1400537249 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 5836755179 ps |
CPU time | 3.84 seconds |
Started | Aug 10 04:57:29 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-f2a3db1b-9b45-412d-b1ef-2d40898d37ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400537249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1400537249 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1033951994 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 69992287 ps |
CPU time | 0.87 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-51e855fa-17cb-489e-b616-176c6c81ea8b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033951994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1033951994 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.3641514600 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 3242024775 ps |
CPU time | 4.45 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:32 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-1bd03a95-cc19-4739-ad51-c8eb70ca7c4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641514600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3641514600 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.819110785 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 97948160 ps |
CPU time | 0.73 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-0de453f5-7cf7-47f9-b717-0b51c8c0da98 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819110785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.819110785 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.139897541 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 5173396193 ps |
CPU time | 16.67 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:44 PM PDT 24 |
Peak memory | 205608 kb |
Host | smart-b992855e-8ea8-4d3d-8df4-44e10be6cb91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139897541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.139897541 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.3290043983 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 4066382426 ps |
CPU time | 7.07 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 213804 kb |
Host | smart-715ad871-d2cb-4ec0-a69d-a6653951a622 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290043983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3290043983 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.3894370656 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 42524802 ps |
CPU time | 0.78 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-00f0d410-0926-4856-a66e-5e75f74356b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894370656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3894370656 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.332185459 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1575716489 ps |
CPU time | 3.34 seconds |
Started | Aug 10 04:57:25 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-285a24ce-e269-4a7a-9d8d-a339a0a536ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332185459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.332185459 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.2537214742 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 74380220 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-c3867a72-e99f-4507-890b-54cd685b5524 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537214742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2537214742 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.1311697687 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 5631465105 ps |
CPU time | 5.46 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-a3ca7385-16ea-404f-9a72-0d9dba42bbf9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311697687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1311697687 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.3820733396 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 38482889 ps |
CPU time | 0.76 seconds |
Started | Aug 10 04:57:03 PM PDT 24 |
Finished | Aug 10 04:57:04 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-d501c27c-5eba-4c72-a448-bc44d636cc13 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820733396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3820733396 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3379035190 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 81836722046 ps |
CPU time | 235.53 seconds |
Started | Aug 10 04:57:06 PM PDT 24 |
Finished | Aug 10 05:01:02 PM PDT 24 |
Peak memory | 217608 kb |
Host | smart-25216660-3ef3-41b0-b74d-9db3438d5c70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379035190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3379035190 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2929767676 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 2636275378 ps |
CPU time | 8.08 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-bf6561e3-82ea-4a58-b3b6-c8af607c97c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929767676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2929767676 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.453837619 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 3146243376 ps |
CPU time | 4.11 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 205752 kb |
Host | smart-1da6b31d-cc43-422c-b3fc-ff43294e994a |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=453837619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl _access.453837619 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_halt_resume_whereto.2881190011 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 534075889 ps |
CPU time | 1.49 seconds |
Started | Aug 10 04:56:59 PM PDT 24 |
Finished | Aug 10 04:57:01 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-7a742d0c-f806-4995-a483-832bc8886b4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881190011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2881190011 |
Directory | /workspace/4.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.60573809 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 540898956 ps |
CPU time | 1.4 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:03 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-7d4d32e9-b298-4b8a-8cc5-8f06c19b28a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60573809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.60573809 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.3208809231 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2838693513 ps |
CPU time | 9.82 seconds |
Started | Aug 10 04:57:00 PM PDT 24 |
Finished | Aug 10 04:57:10 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-7cdb64d9-441c-41b4-8b28-1dc7cb917850 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208809231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3208809231 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.2546051486 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1026971449 ps |
CPU time | 2.97 seconds |
Started | Aug 10 04:57:02 PM PDT 24 |
Finished | Aug 10 04:57:06 PM PDT 24 |
Peak memory | 229532 kb |
Host | smart-4890cca5-c2b5-4bc9-bf89-dfeb0e5c837e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546051486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2546051486 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.1662193453 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2750537719 ps |
CPU time | 4.69 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:10 PM PDT 24 |
Peak memory | 213744 kb |
Host | smart-cf9e22ee-8d8c-4119-903e-7bb2f2ccc8a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662193453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1662193453 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2888779000 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 11364602676 ps |
CPU time | 213.14 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 05:00:39 PM PDT 24 |
Peak memory | 222044 kb |
Host | smart-bccad748-e1bd-4fc5-9314-3abc808ebc4c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888779000 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2888779000 |
Directory | /workspace/4.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.2798830321 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 50251242 ps |
CPU time | 0.82 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-61e9a8b4-b257-4e14-a8e3-6315d6a291a0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798830321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2798830321 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.3821466259 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 7437298699 ps |
CPU time | 2.95 seconds |
Started | Aug 10 04:57:26 PM PDT 24 |
Finished | Aug 10 04:57:29 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-171b88e9-95f9-48d0-ad3f-9ad10d5fca9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821466259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3821466259 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3320520745 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 138401893 ps |
CPU time | 0.8 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:35 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-1567d060-86d3-49bd-b290-06e1c15bcb32 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320520745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3320520745 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.2250153505 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 2617878098 ps |
CPU time | 4.51 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:32 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-1dab38bf-1c5a-41a6-84f9-88bd9c397fad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250153505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2250153505 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2268743502 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 97912421 ps |
CPU time | 0.91 seconds |
Started | Aug 10 04:57:26 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-f8ce4901-47f4-45be-8c4d-77bdb0e002d9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268743502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2268743502 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.4000004654 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 5516853539 ps |
CPU time | 5.21 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:32 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-5d07ef10-835c-44de-ad3e-ef620403fa68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000004654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.4000004654 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1760833784 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 64867741 ps |
CPU time | 0.75 seconds |
Started | Aug 10 04:57:25 PM PDT 24 |
Finished | Aug 10 04:57:26 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-b0c7ced7-5c07-4a6f-bf4f-b9b75eae8b6d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760833784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1760833784 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.2089686069 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 81266614 ps |
CPU time | 0.77 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-19fc551e-8d89-48b6-a5d1-e70532665c89 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089686069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2089686069 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.1773501868 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 6918944233 ps |
CPU time | 21.19 seconds |
Started | Aug 10 04:57:29 PM PDT 24 |
Finished | Aug 10 04:57:50 PM PDT 24 |
Peak memory | 213804 kb |
Host | smart-7b720f77-c357-4621-833f-fd5a5be2165c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773501868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1773501868 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.135988730 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 45855318 ps |
CPU time | 0.81 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-e13020fa-8c8d-43d5-b433-9975b3d10ebe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135988730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.135988730 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.1100514516 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 5433211938 ps |
CPU time | 8.34 seconds |
Started | Aug 10 04:57:32 PM PDT 24 |
Finished | Aug 10 04:57:41 PM PDT 24 |
Peak memory | 214056 kb |
Host | smart-cbc29e5f-d467-412d-b791-0a0f0409b999 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100514516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1100514516 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3380580988 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 91972517 ps |
CPU time | 0.73 seconds |
Started | Aug 10 04:57:31 PM PDT 24 |
Finished | Aug 10 04:57:32 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-3e06a656-c96e-482e-bc09-1493dc919d64 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380580988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3380580988 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.1360241165 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 2507739289 ps |
CPU time | 3.18 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:34 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-25240660-ddd8-4e34-8a89-b0aa9db98b6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360241165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1360241165 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.3603668075 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 68844617 ps |
CPU time | 0.77 seconds |
Started | Aug 10 04:57:27 PM PDT 24 |
Finished | Aug 10 04:57:28 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-9adac7a9-167d-4bd6-9c22-2bc8c6312f4f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603668075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3603668075 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.3419990992 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 2037601806 ps |
CPU time | 2.17 seconds |
Started | Aug 10 04:57:31 PM PDT 24 |
Finished | Aug 10 04:57:33 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-94d632c2-52bf-469a-abda-c3c4fe8c07c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419990992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3419990992 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.2750858080 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 69206773 ps |
CPU time | 0.74 seconds |
Started | Aug 10 04:57:29 PM PDT 24 |
Finished | Aug 10 04:57:30 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-5fca934c-707e-4ecd-b75f-47dc8bbfae7c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750858080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2750858080 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.1326477173 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 4478866867 ps |
CPU time | 10.07 seconds |
Started | Aug 10 04:57:31 PM PDT 24 |
Finished | Aug 10 04:57:41 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-2093ad0d-6ee5-44b1-a856-9664cc932652 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326477173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1326477173 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.390314917 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 144485966 ps |
CPU time | 0.75 seconds |
Started | Aug 10 04:57:30 PM PDT 24 |
Finished | Aug 10 04:57:31 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-372081e2-e11d-4b9e-8cd9-2a17435b8d46 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390314917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.390314917 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.3338432347 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 6637327468 ps |
CPU time | 5.01 seconds |
Started | Aug 10 04:57:33 PM PDT 24 |
Finished | Aug 10 04:57:38 PM PDT 24 |
Peak memory | 213864 kb |
Host | smart-dc6302a7-bc22-445e-8a24-4e8df3b86d58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338432347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3338432347 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.2881570312 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 50784238 ps |
CPU time | 0.81 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:02 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-1026cca4-6d57-433e-9391-cc71e06b39d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881570312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2881570312 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.4062708196 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1906049489 ps |
CPU time | 1.52 seconds |
Started | Aug 10 04:57:03 PM PDT 24 |
Finished | Aug 10 04:57:05 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-c2c53bef-4f2e-4b6e-a701-5c8ad443aeff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062708196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.4062708196 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.614408283 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1936497705 ps |
CPU time | 6.33 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:07 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-19a6b83d-e93c-47bd-9d60-1c92da6e6191 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614408283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.614408283 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3613769657 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1419194423 ps |
CPU time | 5.03 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:06 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-08f74225-ed94-400d-9830-3b3044683811 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3613769657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.3613769657 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2193388330 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 502734259 ps |
CPU time | 1.4 seconds |
Started | Aug 10 04:57:00 PM PDT 24 |
Finished | Aug 10 04:57:02 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-8e85ff68-a87c-40f7-a8b1-903fb1322df5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193388330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2193388330 |
Directory | /workspace/5.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.2558950405 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2736719005 ps |
CPU time | 7.71 seconds |
Started | Aug 10 04:57:06 PM PDT 24 |
Finished | Aug 10 04:57:14 PM PDT 24 |
Peak memory | 205800 kb |
Host | smart-fbdb9dc9-9b13-46da-b0eb-052ec51226fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558950405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2558950405 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.3875044146 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 4487640799 ps |
CPU time | 4.27 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-2ef91428-fcff-41c2-99b9-3bf1c1559fd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875044146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3875044146 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3935422067 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 94075363 ps |
CPU time | 0.75 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:57:02 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-6931208b-0d1f-4cad-b294-6ff187806551 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935422067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3935422067 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.379188435 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 57329284523 ps |
CPU time | 111.13 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:58:52 PM PDT 24 |
Peak memory | 222012 kb |
Host | smart-bd4886a3-0067-47fa-9178-ed0b8bb2d58c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379188435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.379188435 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2373321572 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 10414718477 ps |
CPU time | 29.38 seconds |
Started | Aug 10 04:57:06 PM PDT 24 |
Finished | Aug 10 04:57:35 PM PDT 24 |
Peak memory | 221956 kb |
Host | smart-ac0c8f4b-0541-4cef-9233-62c47a9d23c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373321572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2373321572 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1698708961 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 3159185275 ps |
CPU time | 1.75 seconds |
Started | Aug 10 04:57:03 PM PDT 24 |
Finished | Aug 10 04:57:05 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-d0ee06b8-f538-4a00-bd36-e1dc3b57e662 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1698708961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.1698708961 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3024689962 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 354764729 ps |
CPU time | 1.05 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:06 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-3e86c734-557f-4ced-95bf-d10964bf3f2f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024689962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3024689962 |
Directory | /workspace/6.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2311378637 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1368852356 ps |
CPU time | 2.02 seconds |
Started | Aug 10 04:57:06 PM PDT 24 |
Finished | Aug 10 04:57:08 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-8ebee923-1912-4751-966b-133c931753a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311378637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2311378637 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.2674882661 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 6246008378 ps |
CPU time | 6.81 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:12 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-09d4c498-8885-47db-a2f6-f3f82825104d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674882661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2674882661 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.2962866895 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 142868115 ps |
CPU time | 0.88 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:06 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-50bb79a8-e122-4182-8533-ee8c177364d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962866895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2962866895 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4012796578 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 53844560293 ps |
CPU time | 132.56 seconds |
Started | Aug 10 04:57:01 PM PDT 24 |
Finished | Aug 10 04:59:14 PM PDT 24 |
Peak memory | 214944 kb |
Host | smart-14ae222b-79c3-4642-8c86-edb7caf13e74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012796578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4012796578 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.250249002 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 1989958858 ps |
CPU time | 7.1 seconds |
Started | Aug 10 04:57:07 PM PDT 24 |
Finished | Aug 10 04:57:14 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-f6206edb-51c9-431e-8346-2e17d83fb879 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250249002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.250249002 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4232586312 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 5083619479 ps |
CPU time | 15.31 seconds |
Started | Aug 10 04:57:05 PM PDT 24 |
Finished | Aug 10 04:57:21 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-bf186f20-cae5-4ad4-9b85-8768eabfedec |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4232586312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.4232586312 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_halt_resume_whereto.3064917907 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 803951186 ps |
CPU time | 2.76 seconds |
Started | Aug 10 04:57:06 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-17aa4896-b097-478d-90a3-7725211f7ec3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064917907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3064917907 |
Directory | /workspace/7.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.1473587403 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 7208310837 ps |
CPU time | 5.73 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:15 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-45df3cb3-7016-4146-a8fe-21039415f83f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473587403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1473587403 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1633996744 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 32743667 ps |
CPU time | 0.77 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:10 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-84cfbb03-61df-4dff-a8ce-539b24eaf546 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633996744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1633996744 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3861110899 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 20407620385 ps |
CPU time | 58.26 seconds |
Started | Aug 10 04:57:08 PM PDT 24 |
Finished | Aug 10 04:58:06 PM PDT 24 |
Peak memory | 213940 kb |
Host | smart-1d56a5bd-04da-4f16-a9fc-77321398a557 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861110899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3861110899 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1546818952 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 10764624888 ps |
CPU time | 16 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:26 PM PDT 24 |
Peak memory | 213832 kb |
Host | smart-778a5ddb-dd91-4de3-88c0-3beb8f2c164b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1546818952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1546818952 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3320609668 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 3086483256 ps |
CPU time | 5.25 seconds |
Started | Aug 10 04:57:11 PM PDT 24 |
Finished | Aug 10 04:57:16 PM PDT 24 |
Peak memory | 205680 kb |
Host | smart-d776082d-ffe6-4971-998e-34dd6dcae8b9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3320609668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.3320609668 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.2112260005 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 3202463998 ps |
CPU time | 5.39 seconds |
Started | Aug 10 04:57:07 PM PDT 24 |
Finished | Aug 10 04:57:13 PM PDT 24 |
Peak memory | 205724 kb |
Host | smart-9141f08b-5ec3-43a2-9635-f961c56d1424 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112260005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2112260005 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.1542291100 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 2315627014 ps |
CPU time | 4.13 seconds |
Started | Aug 10 04:57:08 PM PDT 24 |
Finished | Aug 10 04:57:12 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-04e3c977-3979-460b-817d-2c4d98a73b97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542291100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1542291100 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.3520166112 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 94345087 ps |
CPU time | 0.91 seconds |
Started | Aug 10 04:57:08 PM PDT 24 |
Finished | Aug 10 04:57:09 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-f05a6e16-1780-4678-8d87-ac4d257ef60d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520166112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3520166112 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3781336678 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 3735665475 ps |
CPU time | 12.04 seconds |
Started | Aug 10 04:57:13 PM PDT 24 |
Finished | Aug 10 04:57:25 PM PDT 24 |
Peak memory | 213968 kb |
Host | smart-4cee342c-b7ee-4f05-8ae1-704b03822933 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781336678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3781336678 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.988837331 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 10543332933 ps |
CPU time | 11.67 seconds |
Started | Aug 10 04:57:10 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 213840 kb |
Host | smart-67793dd0-3755-439d-9d8d-1aee5c07d273 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=988837331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl _access.988837331 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.167102096 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 3570813761 ps |
CPU time | 3.25 seconds |
Started | Aug 10 04:57:09 PM PDT 24 |
Finished | Aug 10 04:57:12 PM PDT 24 |
Peak memory | 205648 kb |
Host | smart-847bf5f0-b457-486e-8f51-06f0fa2fe8be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167102096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.167102096 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.4163206980 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 4299272021 ps |
CPU time | 9.49 seconds |
Started | Aug 10 04:57:13 PM PDT 24 |
Finished | Aug 10 04:57:22 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-3f99bcd3-20a5-4175-8adf-e6dd6b911d45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163206980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4163206980 |
Directory | /workspace/9.rv_dm_stress_all/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |