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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
84.79 96.02 86.85 91.55 75.64 89.08 98.42 55.97


Total test records in report: 394
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T129 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3633672147 Aug 12 04:54:09 PM PDT 24 Aug 12 04:54:10 PM PDT 24 57315840 ps
T281 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1562503536 Aug 12 04:53:34 PM PDT 24 Aug 12 04:53:51 PM PDT 24 12217128572 ps
T282 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2566674958 Aug 12 04:53:49 PM PDT 24 Aug 12 04:53:51 PM PDT 24 616247608 ps
T283 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3748894560 Aug 12 04:54:28 PM PDT 24 Aug 12 04:54:30 PM PDT 24 410936606 ps
T173 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4265111694 Aug 12 04:53:50 PM PDT 24 Aug 12 04:54:10 PM PDT 24 1389217477 ps
T284 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3321541827 Aug 12 04:54:45 PM PDT 24 Aug 12 04:54:47 PM PDT 24 246551818 ps
T166 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3326889138 Aug 12 04:54:36 PM PDT 24 Aug 12 04:54:49 PM PDT 24 1911024707 ps
T285 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3050217232 Aug 12 04:53:59 PM PDT 24 Aug 12 04:54:12 PM PDT 24 7956717068 ps
T167 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2249623788 Aug 12 04:54:38 PM PDT 24 Aug 12 04:54:59 PM PDT 24 5727951216 ps
T286 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4209797235 Aug 12 04:54:50 PM PDT 24 Aug 12 04:54:54 PM PDT 24 286029669 ps
T287 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3006667633 Aug 12 04:54:36 PM PDT 24 Aug 12 04:54:41 PM PDT 24 364011743 ps
T288 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3257880965 Aug 12 04:54:40 PM PDT 24 Aug 12 04:54:44 PM PDT 24 283658372 ps
T123 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.253260756 Aug 12 04:54:09 PM PDT 24 Aug 12 04:54:13 PM PDT 24 456287285 ps
T289 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1918941796 Aug 12 04:54:36 PM PDT 24 Aug 12 04:54:45 PM PDT 24 7390521075 ps
T130 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.326190575 Aug 12 04:53:49 PM PDT 24 Aug 12 04:54:42 PM PDT 24 1474492816 ps
T290 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4052883761 Aug 12 04:53:22 PM PDT 24 Aug 12 04:53:24 PM PDT 24 276969131 ps
T291 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4196154210 Aug 12 04:53:27 PM PDT 24 Aug 12 04:53:31 PM PDT 24 105873806 ps
T168 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2213825213 Aug 12 04:54:03 PM PDT 24 Aug 12 04:54:15 PM PDT 24 2752032853 ps
T292 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3964499387 Aug 12 04:54:09 PM PDT 24 Aug 12 04:54:12 PM PDT 24 443843520 ps
T293 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2069753884 Aug 12 04:54:44 PM PDT 24 Aug 12 04:54:49 PM PDT 24 423628373 ps
T294 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4202428792 Aug 12 04:54:02 PM PDT 24 Aug 12 04:54:19 PM PDT 24 25667086091 ps
T295 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4081668377 Aug 12 04:54:39 PM PDT 24 Aug 12 04:54:40 PM PDT 24 30410948 ps
T124 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2603150651 Aug 12 04:54:10 PM PDT 24 Aug 12 04:54:17 PM PDT 24 443094877 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.932633835 Aug 12 04:53:48 PM PDT 24 Aug 12 04:55:03 PM PDT 24 25915953140 ps
T297 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3641738564 Aug 12 04:54:17 PM PDT 24 Aug 12 04:54:22 PM PDT 24 249841028 ps
T298 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.220033549 Aug 12 04:54:03 PM PDT 24 Aug 12 04:54:05 PM PDT 24 345498248 ps
T299 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1734172260 Aug 12 04:54:06 PM PDT 24 Aug 12 04:54:11 PM PDT 24 1406024778 ps
T300 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1500490464 Aug 12 04:54:19 PM PDT 24 Aug 12 04:54:23 PM PDT 24 4269876627 ps
T79 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3302094134 Aug 12 04:53:13 PM PDT 24 Aug 12 04:53:28 PM PDT 24 24968121131 ps
T301 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.766141332 Aug 12 04:54:32 PM PDT 24 Aug 12 04:54:39 PM PDT 24 7601030190 ps
T302 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1833493363 Aug 12 04:54:09 PM PDT 24 Aug 12 04:54:11 PM PDT 24 358662596 ps
T303 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2081960253 Aug 12 04:54:44 PM PDT 24 Aug 12 04:54:58 PM PDT 24 4684104320 ps
T304 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.620831401 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:27 PM PDT 24 2803574042 ps
T305 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.575434591 Aug 12 04:54:47 PM PDT 24 Aug 12 04:54:55 PM PDT 24 5678241624 ps
T306 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.991072280 Aug 12 04:54:29 PM PDT 24 Aug 12 04:54:35 PM PDT 24 482175681 ps
T78 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1102621793 Aug 12 04:53:55 PM PDT 24 Aug 12 04:54:08 PM PDT 24 15072839418 ps
T307 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.657187819 Aug 12 04:53:08 PM PDT 24 Aug 12 04:53:09 PM PDT 24 437699561 ps
T133 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.309734977 Aug 12 04:54:37 PM PDT 24 Aug 12 04:54:45 PM PDT 24 3737675092 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2759324678 Aug 12 04:53:08 PM PDT 24 Aug 12 04:53:09 PM PDT 24 417949565 ps
T309 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2493272162 Aug 12 04:54:02 PM PDT 24 Aug 12 04:54:11 PM PDT 24 5145528383 ps
T170 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3817828477 Aug 12 04:54:12 PM PDT 24 Aug 12 04:54:30 PM PDT 24 2947950467 ps
T310 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2711619673 Aug 12 04:53:26 PM PDT 24 Aug 12 04:53:27 PM PDT 24 105246205 ps
T175 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.898769550 Aug 12 04:54:19 PM PDT 24 Aug 12 04:54:49 PM PDT 24 6200361027 ps
T311 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1337284739 Aug 12 04:53:16 PM PDT 24 Aug 12 04:53:16 PM PDT 24 55638806 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2099580226 Aug 12 04:53:34 PM PDT 24 Aug 12 04:53:39 PM PDT 24 230186413 ps
T313 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.707325489 Aug 12 04:53:15 PM PDT 24 Aug 12 04:54:58 PM PDT 24 100133986061 ps
T314 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3110276046 Aug 12 04:54:18 PM PDT 24 Aug 12 04:54:20 PM PDT 24 962490163 ps
T69 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2784581714 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:36 PM PDT 24 4481354857 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1281616876 Aug 12 04:53:56 PM PDT 24 Aug 12 04:53:58 PM PDT 24 297642413 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.348307161 Aug 12 04:54:43 PM PDT 24 Aug 12 04:54:48 PM PDT 24 293063235 ps
T92 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3640758485 Aug 12 04:53:58 PM PDT 24 Aug 12 04:54:03 PM PDT 24 4573894189 ps
T89 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.501009408 Aug 12 04:53:48 PM PDT 24 Aug 12 04:53:56 PM PDT 24 2348856939 ps
T317 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3960378622 Aug 12 04:53:36 PM PDT 24 Aug 12 04:53:38 PM PDT 24 1732825697 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.801967360 Aug 12 04:53:56 PM PDT 24 Aug 12 04:57:39 PM PDT 24 84843780068 ps
T319 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2773051387 Aug 12 04:54:36 PM PDT 24 Aug 12 04:54:38 PM PDT 24 146642435 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1657398579 Aug 12 04:53:34 PM PDT 24 Aug 12 04:53:36 PM PDT 24 60107087 ps
T321 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.805664544 Aug 12 04:54:29 PM PDT 24 Aug 12 04:54:48 PM PDT 24 6937548341 ps
T322 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2800419531 Aug 12 04:54:10 PM PDT 24 Aug 12 04:54:12 PM PDT 24 2998740463 ps
T323 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.449420440 Aug 12 04:54:14 PM PDT 24 Aug 12 04:54:19 PM PDT 24 509478090 ps
T324 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3610769801 Aug 12 04:54:31 PM PDT 24 Aug 12 04:54:34 PM PDT 24 373812400 ps
T325 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1146758369 Aug 12 04:54:23 PM PDT 24 Aug 12 04:54:26 PM PDT 24 160988493 ps
T326 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3260303660 Aug 12 04:53:48 PM PDT 24 Aug 12 04:53:50 PM PDT 24 113777840 ps
T327 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2682125922 Aug 12 04:54:16 PM PDT 24 Aug 12 04:54:30 PM PDT 24 15816564511 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1495204515 Aug 12 04:53:37 PM PDT 24 Aug 12 04:53:40 PM PDT 24 653616188 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3792483971 Aug 12 04:53:39 PM PDT 24 Aug 12 04:53:43 PM PDT 24 489701753 ps
T71 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1642885845 Aug 12 04:53:06 PM PDT 24 Aug 12 04:53:11 PM PDT 24 3806619078 ps
T330 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3418496658 Aug 12 04:54:31 PM PDT 24 Aug 12 04:54:50 PM PDT 24 35443316013 ps
T176 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3007407384 Aug 12 04:54:31 PM PDT 24 Aug 12 04:54:55 PM PDT 24 4857984684 ps
T331 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3620060212 Aug 12 04:53:55 PM PDT 24 Aug 12 04:53:56 PM PDT 24 81465361 ps
T332 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4119864975 Aug 12 04:54:04 PM PDT 24 Aug 12 04:54:38 PM PDT 24 12485851910 ps
T333 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1483144471 Aug 12 04:53:47 PM PDT 24 Aug 12 04:53:48 PM PDT 24 110831991 ps
T334 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3724942677 Aug 12 04:54:45 PM PDT 24 Aug 12 04:54:47 PM PDT 24 162137226 ps
T134 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2679894050 Aug 12 04:54:19 PM PDT 24 Aug 12 04:54:26 PM PDT 24 363265742 ps
T75 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2480701581 Aug 12 04:54:47 PM PDT 24 Aug 12 04:54:58 PM PDT 24 3057892166 ps
T177 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2663074986 Aug 12 04:54:17 PM PDT 24 Aug 12 04:54:31 PM PDT 24 3255693336 ps
T335 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3646617856 Aug 12 04:54:25 PM PDT 24 Aug 12 04:54:50 PM PDT 24 36226349839 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.120047471 Aug 12 04:53:22 PM PDT 24 Aug 12 04:53:24 PM PDT 24 337801406 ps
T337 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3155192944 Aug 12 04:54:39 PM PDT 24 Aug 12 04:54:44 PM PDT 24 278187165 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3234999803 Aug 12 04:53:14 PM PDT 24 Aug 12 04:54:20 PM PDT 24 5142303029 ps
T339 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.946231752 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:26 PM PDT 24 256326779 ps
T340 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1557148530 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:43 PM PDT 24 3077653408 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1280626089 Aug 12 04:53:06 PM PDT 24 Aug 12 04:53:38 PM PDT 24 6908740590 ps
T342 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3073399716 Aug 12 04:54:29 PM PDT 24 Aug 12 04:54:31 PM PDT 24 175544908 ps
T343 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2582516659 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:28 PM PDT 24 322219032 ps
T77 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3913845977 Aug 12 04:53:54 PM PDT 24 Aug 12 04:53:55 PM PDT 24 73453704 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3127258477 Aug 12 04:53:15 PM PDT 24 Aug 12 04:53:20 PM PDT 24 680781931 ps
T345 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.190602539 Aug 12 04:54:04 PM PDT 24 Aug 12 04:54:06 PM PDT 24 338873840 ps
T346 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2934394184 Aug 12 04:53:16 PM PDT 24 Aug 12 04:53:18 PM PDT 24 409841845 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3556789285 Aug 12 04:53:21 PM PDT 24 Aug 12 04:54:28 PM PDT 24 2935967373 ps
T347 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2541376675 Aug 12 04:54:04 PM PDT 24 Aug 12 04:54:27 PM PDT 24 1950632174 ps
T348 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.22371086 Aug 12 04:54:45 PM PDT 24 Aug 12 04:54:50 PM PDT 24 465308672 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2948881874 Aug 12 04:53:35 PM PDT 24 Aug 12 04:54:04 PM PDT 24 7095220589 ps
T350 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.195587387 Aug 12 04:53:54 PM PDT 24 Aug 12 04:53:57 PM PDT 24 164507747 ps
T351 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3186787023 Aug 12 04:54:39 PM PDT 24 Aug 12 04:54:43 PM PDT 24 69972991 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2076010885 Aug 12 04:53:49 PM PDT 24 Aug 12 04:53:56 PM PDT 24 7104788976 ps
T353 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3160472567 Aug 12 04:53:42 PM PDT 24 Aug 12 04:53:43 PM PDT 24 175108160 ps
T171 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3246884543 Aug 12 04:54:46 PM PDT 24 Aug 12 04:54:57 PM PDT 24 1186690542 ps
T354 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.813187296 Aug 12 04:54:37 PM PDT 24 Aug 12 04:54:48 PM PDT 24 2880159340 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1251591433 Aug 12 04:53:23 PM PDT 24 Aug 12 04:53:51 PM PDT 24 20332720293 ps
T72 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3357424490 Aug 12 04:53:36 PM PDT 24 Aug 12 04:53:53 PM PDT 24 2104230263 ps
T356 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1299718801 Aug 12 04:54:37 PM PDT 24 Aug 12 04:54:42 PM PDT 24 2112117018 ps
T357 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1816823265 Aug 12 04:54:15 PM PDT 24 Aug 12 04:54:22 PM PDT 24 1086080168 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.631608669 Aug 12 04:53:55 PM PDT 24 Aug 12 04:54:22 PM PDT 24 784905053 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.171878518 Aug 12 04:53:35 PM PDT 24 Aug 12 04:53:42 PM PDT 24 9359418133 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.461468038 Aug 12 04:53:36 PM PDT 24 Aug 12 04:53:52 PM PDT 24 9630895028 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3601000331 Aug 12 04:54:33 PM PDT 24 Aug 12 04:54:37 PM PDT 24 370999342 ps
T362 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2896195840 Aug 12 04:54:44 PM PDT 24 Aug 12 04:54:48 PM PDT 24 227043543 ps
T363 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2383611118 Aug 12 04:54:31 PM PDT 24 Aug 12 04:54:33 PM PDT 24 279301492 ps
T364 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.615835308 Aug 12 04:54:17 PM PDT 24 Aug 12 04:54:23 PM PDT 24 615163121 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1416693324 Aug 12 04:53:06 PM PDT 24 Aug 12 04:53:09 PM PDT 24 3096165904 ps
T366 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1494377411 Aug 12 04:53:49 PM PDT 24 Aug 12 04:53:50 PM PDT 24 163669224 ps
T367 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2702113606 Aug 12 04:54:30 PM PDT 24 Aug 12 04:54:35 PM PDT 24 295153416 ps
T61 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2574661007 Aug 12 04:53:38 PM PDT 24 Aug 12 04:53:49 PM PDT 24 3662451483 ps
T368 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1032337924 Aug 12 04:54:43 PM PDT 24 Aug 12 04:54:46 PM PDT 24 513842469 ps
T76 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3340715188 Aug 12 04:54:17 PM PDT 24 Aug 12 04:54:30 PM PDT 24 1648386208 ps
T369 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4061249370 Aug 12 04:54:14 PM PDT 24 Aug 12 04:54:16 PM PDT 24 436872447 ps
T370 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2899670835 Aug 12 04:54:39 PM PDT 24 Aug 12 04:54:40 PM PDT 24 104146043 ps
T371 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2231944569 Aug 12 04:54:09 PM PDT 24 Aug 12 04:54:10 PM PDT 24 37797664 ps
T372 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1813847926 Aug 12 04:53:50 PM PDT 24 Aug 12 04:54:18 PM PDT 24 1253512794 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3551748782 Aug 12 04:53:27 PM PDT 24 Aug 12 04:53:28 PM PDT 24 140699184 ps
T374 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.698894284 Aug 12 04:54:17 PM PDT 24 Aug 12 04:54:46 PM PDT 24 3852753803 ps
T375 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2976840854 Aug 12 04:54:45 PM PDT 24 Aug 12 04:57:56 PM PDT 24 72831662589 ps
T376 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1713840462 Aug 12 04:53:29 PM PDT 24 Aug 12 04:53:53 PM PDT 24 2648164820 ps
T377 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.174561381 Aug 12 04:53:51 PM PDT 24 Aug 12 04:54:21 PM PDT 24 9982232394 ps
T378 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.410267611 Aug 12 04:54:30 PM PDT 24 Aug 12 04:54:40 PM PDT 24 15365204474 ps
T379 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1061734958 Aug 12 04:54:43 PM PDT 24 Aug 12 04:54:45 PM PDT 24 774749698 ps
T380 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1741539274 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:31 PM PDT 24 934941770 ps
T381 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1926975513 Aug 12 04:54:38 PM PDT 24 Aug 12 04:54:50 PM PDT 24 4539057554 ps
T382 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1100850379 Aug 12 04:54:31 PM PDT 24 Aug 12 04:54:50 PM PDT 24 7106924887 ps
T383 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1136786489 Aug 12 04:54:31 PM PDT 24 Aug 12 04:54:35 PM PDT 24 821342533 ps
T384 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.134789745 Aug 12 04:54:18 PM PDT 24 Aug 12 04:54:19 PM PDT 24 596085872 ps
T385 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1380209777 Aug 12 04:54:43 PM PDT 24 Aug 12 04:54:47 PM PDT 24 204220735 ps
T386 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1224789170 Aug 12 04:54:36 PM PDT 24 Aug 12 04:54:40 PM PDT 24 241692067 ps
T387 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1871346622 Aug 12 04:53:49 PM PDT 24 Aug 12 04:53:57 PM PDT 24 5978776925 ps
T388 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2029392295 Aug 12 04:54:30 PM PDT 24 Aug 12 04:54:34 PM PDT 24 445895531 ps
T172 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3938712103 Aug 12 04:53:59 PM PDT 24 Aug 12 04:54:15 PM PDT 24 1619422611 ps
T389 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4009417080 Aug 12 04:53:35 PM PDT 24 Aug 12 04:54:12 PM PDT 24 13192179213 ps
T70 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1525805491 Aug 12 04:53:49 PM PDT 24 Aug 12 04:53:51 PM PDT 24 569610164 ps
T390 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2732045134 Aug 12 04:54:17 PM PDT 24 Aug 12 04:54:22 PM PDT 24 276856590 ps
T391 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1987084675 Aug 12 04:54:37 PM PDT 24 Aug 12 04:54:43 PM PDT 24 2749247455 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4256655729 Aug 12 04:53:41 PM PDT 24 Aug 12 04:54:05 PM PDT 24 8471283337 ps
T80 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2002872604 Aug 12 04:53:56 PM PDT 24 Aug 12 04:54:06 PM PDT 24 2238210701 ps
T393 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1598785030 Aug 12 04:53:35 PM PDT 24 Aug 12 04:53:40 PM PDT 24 1031576719 ps
T394 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1402689861 Aug 12 04:54:24 PM PDT 24 Aug 12 04:54:25 PM PDT 24 166537991 ps

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.4284572446
Short name T4
Test name
Test status
Simulation time 2264887783 ps
CPU time 27.65 seconds
Started Aug 12 04:55:19 PM PDT 24
Finished Aug 12 04:55:46 PM PDT 24
Peak memory 221964 kb
Host smart-6ff8cf91-309c-4146-a5d8-450c924ce89e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284572446 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.4284572446
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.931837192
Short name T14
Test name
Test status
Simulation time 3190096344 ps
CPU time 4.83 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:52 PM PDT 24
Peak memory 213580 kb
Host smart-3501ecfa-824f-4d8a-9fc5-6654ddeb59cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931837192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.931837192
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2306882228
Short name T26
Test name
Test status
Simulation time 4791825116 ps
CPU time 12.37 seconds
Started Aug 12 04:54:52 PM PDT 24
Finished Aug 12 04:55:04 PM PDT 24
Peak memory 205324 kb
Host smart-7e6788de-1702-4cd0-932a-3be79546a28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306882228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2306882228
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/7.rv_dm_buffered_enable.2755674468
Short name T13
Test name
Test status
Simulation time 324363896 ps
CPU time 1.45 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 234640 kb
Host smart-6993ec1a-fb90-4b56-8eca-f83509d8d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755674468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2755674468
Directory /workspace/7.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.576006436
Short name T55
Test name
Test status
Simulation time 4059871625 ps
CPU time 6.6 seconds
Started Aug 12 04:54:51 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 205420 kb
Host smart-e4de2dcf-8d3c-4075-9e65-4a0642b98524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576006436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.576006436
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.61995267
Short name T98
Test name
Test status
Simulation time 1311197765 ps
CPU time 17.98 seconds
Started Aug 12 04:53:28 PM PDT 24
Finished Aug 12 04:53:46 PM PDT 24
Peak memory 221556 kb
Host smart-c364ae95-7179-41b2-8225-3a655838abf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61995267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.61995267
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.172046031
Short name T43
Test name
Test status
Simulation time 3761545317 ps
CPU time 32.73 seconds
Started Aug 12 04:55:29 PM PDT 24
Finished Aug 12 04:56:02 PM PDT 24
Peak memory 222036 kb
Host smart-ebdace06-32b0-4c87-982a-e62949812a3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172046031 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.172046031
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.675768805
Short name T7
Test name
Test status
Simulation time 2545120106 ps
CPU time 7.67 seconds
Started Aug 12 04:55:34 PM PDT 24
Finished Aug 12 04:55:42 PM PDT 24
Peak memory 213612 kb
Host smart-ec8b2860-7559-4148-9d25-e5dfd95953e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675768805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.675768805
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.808511305
Short name T16
Test name
Test status
Simulation time 91882227390 ps
CPU time 143.21 seconds
Started Aug 12 04:55:21 PM PDT 24
Finished Aug 12 04:57:44 PM PDT 24
Peak memory 236632 kb
Host smart-feae72d1-5378-417f-a680-f0d08e5158ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808511305 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.808511305
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2248415586
Short name T111
Test name
Test status
Simulation time 55041444904 ps
CPU time 82.33 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 213580 kb
Host smart-ca188a05-edf3-414a-8767-bc6f5884fec4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248415586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2248415586
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2574661007
Short name T61
Test name
Test status
Simulation time 3662451483 ps
CPU time 10.61 seconds
Started Aug 12 04:53:38 PM PDT 24
Finished Aug 12 04:53:49 PM PDT 24
Peak memory 205336 kb
Host smart-0c0e72cc-a6e7-40cd-8445-8b1edd6da6e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574661007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2574661007
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2299695639
Short name T1
Test name
Test status
Simulation time 352713893 ps
CPU time 1.11 seconds
Started Aug 12 04:55:21 PM PDT 24
Finished Aug 12 04:55:22 PM PDT 24
Peak memory 228668 kb
Host smart-5bb4d5c3-0992-417c-a993-0254951bea94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299695639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2299695639
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1129346725
Short name T28
Test name
Test status
Simulation time 4242558486 ps
CPU time 4.87 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:55:46 PM PDT 24
Peak memory 213588 kb
Host smart-775fb66b-cad5-4ff4-9e81-b0d54a44deeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129346725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1129346725
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.1015947179
Short name T56
Test name
Test status
Simulation time 111992880 ps
CPU time 0.77 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:05 PM PDT 24
Peak memory 205116 kb
Host smart-1a90dac3-94fd-420f-a31a-f8efe8580eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015947179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1015947179
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3938712103
Short name T172
Test name
Test status
Simulation time 1619422611 ps
CPU time 16.35 seconds
Started Aug 12 04:53:59 PM PDT 24
Finished Aug 12 04:54:15 PM PDT 24
Peak memory 215896 kb
Host smart-b9d3cdae-2454-4ca3-9a56-ab989a81b674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938712103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3938712103
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4204879568
Short name T88
Test name
Test status
Simulation time 24148134385 ps
CPU time 59.22 seconds
Started Aug 12 04:53:15 PM PDT 24
Finished Aug 12 04:54:14 PM PDT 24
Peak memory 205240 kb
Host smart-181e70ce-567a-4d0b-bf1f-75e7663f3a9d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204879568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.4204879568
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3695185181
Short name T17
Test name
Test status
Simulation time 190080469 ps
CPU time 0.81 seconds
Started Aug 12 04:54:51 PM PDT 24
Finished Aug 12 04:54:52 PM PDT 24
Peak memory 205080 kb
Host smart-eb38045b-20fb-4da4-ac0c-37ae5f2b2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695185181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3695185181
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.542569788
Short name T82
Test name
Test status
Simulation time 54077009 ps
CPU time 0.83 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205016 kb
Host smart-33a3ba18-e618-4501-badc-832d95a21614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542569788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.542569788
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2784581714
Short name T69
Test name
Test status
Simulation time 4481354857 ps
CPU time 12.57 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:36 PM PDT 24
Peak memory 216828 kb
Host smart-bacc9bed-90cd-4ae1-baae-f05d5a0de5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784581714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
784581714
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.889441473
Short name T6
Test name
Test status
Simulation time 5936614258 ps
CPU time 12.61 seconds
Started Aug 12 04:55:54 PM PDT 24
Finished Aug 12 04:56:06 PM PDT 24
Peak memory 205456 kb
Host smart-9002fba8-46a0-4cc0-9dd4-55d7552f4f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889441473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.889441473
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2494229998
Short name T20
Test name
Test status
Simulation time 1652891919 ps
CPU time 4.92 seconds
Started Aug 12 04:55:11 PM PDT 24
Finished Aug 12 04:55:17 PM PDT 24
Peak memory 205240 kb
Host smart-af01fa5a-a34a-4dab-a1f0-ee65e9a8b97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494229998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2494229998
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1978205792
Short name T47
Test name
Test status
Simulation time 4669314642 ps
CPU time 6.31 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:56:03 PM PDT 24
Peak memory 205452 kb
Host smart-7f23bb33-ffbc-4e4a-8f81-0fecceaa2b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978205792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1978205792
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2961336686
Short name T39
Test name
Test status
Simulation time 91407063 ps
CPU time 0.85 seconds
Started Aug 12 04:55:06 PM PDT 24
Finished Aug 12 04:55:07 PM PDT 24
Peak memory 213252 kb
Host smart-309cb58e-ba87-4f03-a693-c4379a50dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961336686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2961336686
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3302094134
Short name T79
Test name
Test status
Simulation time 24968121131 ps
CPU time 14.34 seconds
Started Aug 12 04:53:13 PM PDT 24
Finished Aug 12 04:53:28 PM PDT 24
Peak memory 213600 kb
Host smart-bfa23a3f-8563-4652-9ef6-478df99f27fc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302094134 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3302094134
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3556789285
Short name T128
Test name
Test status
Simulation time 2935967373 ps
CPU time 67.01 seconds
Started Aug 12 04:53:21 PM PDT 24
Finished Aug 12 04:54:28 PM PDT 24
Peak memory 219128 kb
Host smart-ddc27aec-7227-4b13-b450-ee152ebcc68d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556789285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3556789285
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3357424490
Short name T72
Test name
Test status
Simulation time 2104230263 ps
CPU time 17.36 seconds
Started Aug 12 04:53:36 PM PDT 24
Finished Aug 12 04:53:53 PM PDT 24
Peak memory 221624 kb
Host smart-5e58dc2b-3b55-49e5-add0-eb8628a8096d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357424490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3357424490
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2971418489
Short name T110
Test name
Test status
Simulation time 282269233 ps
CPU time 4.3 seconds
Started Aug 12 04:53:56 PM PDT 24
Finished Aug 12 04:54:00 PM PDT 24
Peak memory 205244 kb
Host smart-ec0bd7bf-fd77-43c6-93d9-8f097c7c89fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971418489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2971418489
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.570198137
Short name T31
Test name
Test status
Simulation time 3985056853 ps
CPU time 7.75 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:55 PM PDT 24
Peak memory 205428 kb
Host smart-e4769028-a4f4-48f4-ad43-78a2018892a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570198137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.570198137
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3340715188
Short name T76
Test name
Test status
Simulation time 1648386208 ps
CPU time 13.02 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:30 PM PDT 24
Peak memory 221580 kb
Host smart-1eb44dfc-79a9-4902-85bd-7599c005d1f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340715188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3340715188
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.3763479871
Short name T41
Test name
Test status
Simulation time 4821366027 ps
CPU time 107.23 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:57:14 PM PDT 24
Peak memory 221892 kb
Host smart-889762b7-db6a-4225-a7fb-eb362337561f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763479871 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.3763479871
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2703055700
Short name T150
Test name
Test status
Simulation time 6559356064 ps
CPU time 10.88 seconds
Started Aug 12 04:55:33 PM PDT 24
Finished Aug 12 04:55:44 PM PDT 24
Peak memory 205448 kb
Host smart-5aea53a9-004c-4a27-bbe9-a6c814c0992c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703055700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2703055700
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3858636240
Short name T15
Test name
Test status
Simulation time 8271257018 ps
CPU time 6.95 seconds
Started Aug 12 04:55:37 PM PDT 24
Finished Aug 12 04:55:44 PM PDT 24
Peak memory 213556 kb
Host smart-4c023666-23ce-43b1-bfed-ac959635ca03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858636240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3858636240
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.939779493
Short name T19
Test name
Test status
Simulation time 4913341134 ps
CPU time 7.25 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:54 PM PDT 24
Peak memory 205408 kb
Host smart-77d4994c-3fd7-480a-9519-b5da5beec362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939779493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.939779493
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.832291973
Short name T267
Test name
Test status
Simulation time 241845758 ps
CPU time 1.33 seconds
Started Aug 12 04:53:22 PM PDT 24
Finished Aug 12 04:53:24 PM PDT 24
Peak memory 204868 kb
Host smart-7b6963fb-3ebe-4f7d-bc0c-106086949350
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832291973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.832291973
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3161658338
Short name T50
Test name
Test status
Simulation time 135107205 ps
CPU time 1.19 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205048 kb
Host smart-8b46ccb6-60f5-4e49-94ff-8654cc278537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161658338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3161658338
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3030895750
Short name T9
Test name
Test status
Simulation time 2822287571 ps
CPU time 4.25 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:56:01 PM PDT 24
Peak memory 213676 kb
Host smart-8dd40146-c6d6-4e2c-a036-04642fba31e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030895750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3030895750
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3137947993
Short name T37
Test name
Test status
Simulation time 242252903 ps
CPU time 1.21 seconds
Started Aug 12 04:54:50 PM PDT 24
Finished Aug 12 04:54:51 PM PDT 24
Peak memory 205156 kb
Host smart-6d231026-9c8f-453a-aad3-a8ac7bbff0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137947993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3137947993
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.948816291
Short name T96
Test name
Test status
Simulation time 48666837 ps
CPU time 0.78 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:48 PM PDT 24
Peak memory 205128 kb
Host smart-0591b987-ed78-4da5-9595-e761313f8b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948816291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.948816291
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2217184313
Short name T104
Test name
Test status
Simulation time 5157208068 ps
CPU time 9.11 seconds
Started Aug 12 04:54:30 PM PDT 24
Finished Aug 12 04:54:39 PM PDT 24
Peak memory 213636 kb
Host smart-d59eae96-c833-4d00-9eb4-def2541678e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217184313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
217184313
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2213825213
Short name T168
Test name
Test status
Simulation time 2752032853 ps
CPU time 12.02 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:15 PM PDT 24
Peak memory 221744 kb
Host smart-f5f4da7f-6765-4d8c-8610-e8d4be189c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213825213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2213825213
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3079550485
Short name T199
Test name
Test status
Simulation time 224239211 ps
CPU time 1.08 seconds
Started Aug 12 04:55:03 PM PDT 24
Finished Aug 12 04:55:04 PM PDT 24
Peak memory 205080 kb
Host smart-addc51c3-833e-4c48-813b-4cc9d0ab00e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079550485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3079550485
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3206821033
Short name T156
Test name
Test status
Simulation time 871969347 ps
CPU time 1.81 seconds
Started Aug 12 04:55:03 PM PDT 24
Finished Aug 12 04:55:05 PM PDT 24
Peak memory 205092 kb
Host smart-6db7bb96-8892-4b3a-95b5-bb760afa8411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206821033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3206821033
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1350157172
Short name T147
Test name
Test status
Simulation time 2293090455 ps
CPU time 7.4 seconds
Started Aug 12 04:55:25 PM PDT 24
Finished Aug 12 04:55:33 PM PDT 24
Peak memory 205452 kb
Host smart-bf846d64-c8d6-4c80-824b-5aa6c220ac83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350157172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1350157172
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.887009303
Short name T121
Test name
Test status
Simulation time 329851356 ps
CPU time 2.39 seconds
Started Aug 12 04:53:38 PM PDT 24
Finished Aug 12 04:53:41 PM PDT 24
Peak memory 213396 kb
Host smart-fc90c831-5455-428f-af1c-ca819af19d4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887009303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.887009303
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1642885845
Short name T71
Test name
Test status
Simulation time 3806619078 ps
CPU time 4.3 seconds
Started Aug 12 04:53:06 PM PDT 24
Finished Aug 12 04:53:11 PM PDT 24
Peak memory 205272 kb
Host smart-001570ca-d453-4757-ba80-2aadb11a955a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642885845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1642885845
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2680140612
Short name T103
Test name
Test status
Simulation time 9200829870 ps
CPU time 54.13 seconds
Started Aug 12 04:55:11 PM PDT 24
Finished Aug 12 04:56:05 PM PDT 24
Peak memory 218688 kb
Host smart-de8fe5d5-f4eb-43a7-85bc-ce217052b981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680140612 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2680140612
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.930653014
Short name T74
Test name
Test status
Simulation time 79533491 ps
CPU time 2.29 seconds
Started Aug 12 04:54:36 PM PDT 24
Finished Aug 12 04:54:39 PM PDT 24
Peak memory 218616 kb
Host smart-9a22b9aa-5065-42e8-b7af-605f00b71da5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930653014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.930653014
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1102621793
Short name T78
Test name
Test status
Simulation time 15072839418 ps
CPU time 12.64 seconds
Started Aug 12 04:53:55 PM PDT 24
Finished Aug 12 04:54:08 PM PDT 24
Peak memory 205192 kb
Host smart-cac3fc35-8b7f-450d-b3d0-bfbc9478a641
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102621793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1102621793
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1280626089
Short name T341
Test name
Test status
Simulation time 6908740590 ps
CPU time 31.29 seconds
Started Aug 12 04:53:06 PM PDT 24
Finished Aug 12 04:53:38 PM PDT 24
Peak memory 213536 kb
Host smart-e60b887d-3c24-4899-9943-5ee390ffbc60
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280626089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1280626089
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3234999803
Short name T338
Test name
Test status
Simulation time 5142303029 ps
CPU time 65.94 seconds
Started Aug 12 04:53:14 PM PDT 24
Finished Aug 12 04:54:20 PM PDT 24
Peak memory 213584 kb
Host smart-c065c8cb-8964-4966-ad93-b66ea17628a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234999803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3234999803
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1003785978
Short name T122
Test name
Test status
Simulation time 1084593887 ps
CPU time 2.43 seconds
Started Aug 12 04:53:14 PM PDT 24
Finished Aug 12 04:53:17 PM PDT 24
Peak memory 213328 kb
Host smart-114cbf2e-c542-4821-8361-5a6a1ba4ae66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003785978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1003785978
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3082994239
Short name T141
Test name
Test status
Simulation time 496656640 ps
CPU time 2.65 seconds
Started Aug 12 04:53:15 PM PDT 24
Finished Aug 12 04:53:17 PM PDT 24
Peak memory 221640 kb
Host smart-cb667401-9519-4699-83e6-8a8e45f0b88b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082994239 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3082994239
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2934394184
Short name T346
Test name
Test status
Simulation time 409841845 ps
CPU time 2.46 seconds
Started Aug 12 04:53:16 PM PDT 24
Finished Aug 12 04:53:18 PM PDT 24
Peak memory 219336 kb
Host smart-06bf8b0d-fd2d-4c7b-8ef6-30681ff10077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934394184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2934394184
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.707325489
Short name T313
Test name
Test status
Simulation time 100133986061 ps
CPU time 102.95 seconds
Started Aug 12 04:53:15 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 205204 kb
Host smart-9d71b28a-55ab-4fb2-817d-3b31b9456e4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707325489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.707325489
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1838694368
Short name T90
Test name
Test status
Simulation time 3694125803 ps
CPU time 9.68 seconds
Started Aug 12 04:53:14 PM PDT 24
Finished Aug 12 04:53:24 PM PDT 24
Peak memory 205184 kb
Host smart-b22ffcf4-180a-40b4-84c2-284581f89457
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838694368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
838694368
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.657187819
Short name T307
Test name
Test status
Simulation time 437699561 ps
CPU time 0.9 seconds
Started Aug 12 04:53:08 PM PDT 24
Finished Aug 12 04:53:09 PM PDT 24
Peak memory 204836 kb
Host smart-54955df6-960e-441e-9368-1b89cbbca5ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657187819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.657187819
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1416693324
Short name T365
Test name
Test status
Simulation time 3096165904 ps
CPU time 2.47 seconds
Started Aug 12 04:53:06 PM PDT 24
Finished Aug 12 04:53:09 PM PDT 24
Peak memory 205172 kb
Host smart-61d8a283-bb32-4f8d-b5c4-be911f175990
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416693324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1416693324
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2373773850
Short name T273
Test name
Test status
Simulation time 905976797 ps
CPU time 1.33 seconds
Started Aug 12 04:53:05 PM PDT 24
Finished Aug 12 04:53:07 PM PDT 24
Peak memory 204932 kb
Host smart-e686e568-c912-4a38-9044-a60be8bb4e90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373773850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2373773850
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2759324678
Short name T308
Test name
Test status
Simulation time 417949565 ps
CPU time 1.64 seconds
Started Aug 12 04:53:08 PM PDT 24
Finished Aug 12 04:53:09 PM PDT 24
Peak memory 204832 kb
Host smart-6aca0a67-e207-4be7-8f7d-0fd07d35bd1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759324678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
759324678
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1337284739
Short name T311
Test name
Test status
Simulation time 55638806 ps
CPU time 0.72 seconds
Started Aug 12 04:53:16 PM PDT 24
Finished Aug 12 04:53:16 PM PDT 24
Peak memory 204848 kb
Host smart-78d4e5a5-ce9e-45d4-9bbe-77a17b1c1f56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337284739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1337284739
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3357931039
Short name T250
Test name
Test status
Simulation time 120372830 ps
CPU time 0.71 seconds
Started Aug 12 04:53:15 PM PDT 24
Finished Aug 12 04:53:16 PM PDT 24
Peak memory 204888 kb
Host smart-a11b0db2-47ae-46c4-8f2b-8bef81bd43e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357931039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3357931039
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1145953085
Short name T115
Test name
Test status
Simulation time 638176937 ps
CPU time 6.44 seconds
Started Aug 12 04:53:17 PM PDT 24
Finished Aug 12 04:53:24 PM PDT 24
Peak memory 205292 kb
Host smart-dd8eb985-f029-413b-b036-e312b0f38f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145953085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1145953085
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3127258477
Short name T344
Test name
Test status
Simulation time 680781931 ps
CPU time 4.73 seconds
Started Aug 12 04:53:15 PM PDT 24
Finished Aug 12 04:53:20 PM PDT 24
Peak memory 213516 kb
Host smart-aa762d47-3c6c-473c-b634-4b20aeb73ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127258477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3127258477
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.760719193
Short name T143
Test name
Test status
Simulation time 3840892472 ps
CPU time 10.31 seconds
Started Aug 12 04:53:14 PM PDT 24
Finished Aug 12 04:53:25 PM PDT 24
Peak memory 213524 kb
Host smart-c7bc9471-1b94-4c9b-b18b-530a8259842f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760719193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.760719193
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1649428447
Short name T261
Test name
Test status
Simulation time 728943273 ps
CPU time 27.22 seconds
Started Aug 12 04:53:38 PM PDT 24
Finished Aug 12 04:54:05 PM PDT 24
Peak memory 205268 kb
Host smart-a4ba6ec3-8bd9-4631-91d4-606f92d82ec7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649428447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1649428447
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3907056644
Short name T119
Test name
Test status
Simulation time 127461434 ps
CPU time 1.55 seconds
Started Aug 12 04:53:29 PM PDT 24
Finished Aug 12 04:53:30 PM PDT 24
Peak memory 213320 kb
Host smart-1d92d0b5-089b-496a-b8d3-6b4ea7263b7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907056644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3907056644
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2099580226
Short name T312
Test name
Test status
Simulation time 230186413 ps
CPU time 4.47 seconds
Started Aug 12 04:53:34 PM PDT 24
Finished Aug 12 04:53:39 PM PDT 24
Peak memory 219852 kb
Host smart-ea832d66-35dc-4135-8cb4-e4dae07bfcff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099580226 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2099580226
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3551748782
Short name T373
Test name
Test status
Simulation time 140699184 ps
CPU time 1.45 seconds
Started Aug 12 04:53:27 PM PDT 24
Finished Aug 12 04:53:28 PM PDT 24
Peak memory 218288 kb
Host smart-88b11d0b-41a6-462f-abae-02279498258e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551748782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3551748782
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2492915502
Short name T279
Test name
Test status
Simulation time 110366692663 ps
CPU time 296.92 seconds
Started Aug 12 04:53:29 PM PDT 24
Finished Aug 12 04:58:26 PM PDT 24
Peak memory 205220 kb
Host smart-72ed3a2f-00df-42bb-a77f-9d77ce8bb711
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492915502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2492915502
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2702280359
Short name T252
Test name
Test status
Simulation time 88617133900 ps
CPU time 85.62 seconds
Started Aug 12 04:53:26 PM PDT 24
Finished Aug 12 04:54:51 PM PDT 24
Peak memory 205220 kb
Host smart-7b30b07c-3bef-499b-9e59-75d46cef8483
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702280359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2702280359
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1014568382
Short name T60
Test name
Test status
Simulation time 9010741653 ps
CPU time 24.07 seconds
Started Aug 12 04:53:22 PM PDT 24
Finished Aug 12 04:53:46 PM PDT 24
Peak memory 205320 kb
Host smart-3fca7505-78c8-4109-b9f4-33e212d6e174
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014568382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1014568382
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1562503536
Short name T281
Test name
Test status
Simulation time 12217128572 ps
CPU time 16.5 seconds
Started Aug 12 04:53:34 PM PDT 24
Finished Aug 12 04:53:51 PM PDT 24
Peak memory 205196 kb
Host smart-41c70b11-996a-4bf0-8b3a-102f6fadea51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562503536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
562503536
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.120047471
Short name T336
Test name
Test status
Simulation time 337801406 ps
CPU time 1.58 seconds
Started Aug 12 04:53:22 PM PDT 24
Finished Aug 12 04:53:24 PM PDT 24
Peak memory 204880 kb
Host smart-41871aa7-79c0-4607-b829-6c4b66023f35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120047471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.120047471
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1251591433
Short name T355
Test name
Test status
Simulation time 20332720293 ps
CPU time 28.04 seconds
Started Aug 12 04:53:23 PM PDT 24
Finished Aug 12 04:53:51 PM PDT 24
Peak memory 205256 kb
Host smart-16d72faa-2978-485e-8c08-b3cd9931d951
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251591433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1251591433
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4052883761
Short name T290
Test name
Test status
Simulation time 276969131 ps
CPU time 1.4 seconds
Started Aug 12 04:53:22 PM PDT 24
Finished Aug 12 04:53:24 PM PDT 24
Peak memory 204884 kb
Host smart-c778627a-9f20-45fa-8d52-11e13dac287b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052883761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
052883761
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2711619673
Short name T310
Test name
Test status
Simulation time 105246205 ps
CPU time 0.87 seconds
Started Aug 12 04:53:26 PM PDT 24
Finished Aug 12 04:53:27 PM PDT 24
Peak memory 204804 kb
Host smart-fe5ee8f4-c1f2-4a2a-afa2-63adffee6a0a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711619673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2711619673
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1693059746
Short name T265
Test name
Test status
Simulation time 199206053 ps
CPU time 0.75 seconds
Started Aug 12 04:53:30 PM PDT 24
Finished Aug 12 04:53:31 PM PDT 24
Peak memory 204884 kb
Host smart-21657043-ee6e-4e5d-8fe6-e759d75be025
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693059746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1693059746
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.92502954
Short name T132
Test name
Test status
Simulation time 529079314 ps
CPU time 7.42 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:53:43 PM PDT 24
Peak memory 205224 kb
Host smart-e1a7d8c8-c6e2-4238-9907-9e5dc27b85b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92502954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_cs
r_outstanding.92502954
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1713840462
Short name T376
Test name
Test status
Simulation time 2648164820 ps
CPU time 24.59 seconds
Started Aug 12 04:53:29 PM PDT 24
Finished Aug 12 04:53:53 PM PDT 24
Peak memory 216048 kb
Host smart-10c14f19-c9ec-43f1-a6b3-be342bc7bce3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713840462 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1713840462
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4196154210
Short name T291
Test name
Test status
Simulation time 105873806 ps
CPU time 3.92 seconds
Started Aug 12 04:53:27 PM PDT 24
Finished Aug 12 04:53:31 PM PDT 24
Peak memory 213496 kb
Host smart-29cdd704-be24-4fd6-acd2-b7996ef27268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196154210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4196154210
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3878898393
Short name T264
Test name
Test status
Simulation time 185398637 ps
CPU time 2.75 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:27 PM PDT 24
Peak memory 217952 kb
Host smart-b54278b6-5ae9-4ea6-af13-2f365477c3ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878898393 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3878898393
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1854591556
Short name T117
Test name
Test status
Simulation time 197286878 ps
CPU time 2.41 seconds
Started Aug 12 04:54:25 PM PDT 24
Finished Aug 12 04:54:27 PM PDT 24
Peak memory 218876 kb
Host smart-425f7cdc-d1de-4285-a77c-7abed5f9534f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854591556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1854591556
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3646617856
Short name T335
Test name
Test status
Simulation time 36226349839 ps
CPU time 24.44 seconds
Started Aug 12 04:54:25 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 205236 kb
Host smart-31698a71-7fdd-48d1-82f6-95daf1c0a4a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646617856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3646617856
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2329698114
Short name T256
Test name
Test status
Simulation time 1562663214 ps
CPU time 2.18 seconds
Started Aug 12 04:54:23 PM PDT 24
Finished Aug 12 04:54:26 PM PDT 24
Peak memory 205028 kb
Host smart-d227e5cc-a130-4155-b237-cd157cc691da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329698114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2329698114
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.134789745
Short name T384
Test name
Test status
Simulation time 596085872 ps
CPU time 0.99 seconds
Started Aug 12 04:54:18 PM PDT 24
Finished Aug 12 04:54:19 PM PDT 24
Peak memory 204884 kb
Host smart-097b6af1-3eac-4aca-8cdd-9fb21be86e9d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134789745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.134789745
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1741539274
Short name T380
Test name
Test status
Simulation time 934941770 ps
CPU time 7.42 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:31 PM PDT 24
Peak memory 205216 kb
Host smart-36687a81-0cb1-4ee8-8293-c10d9471171d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741539274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1741539274
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1146758369
Short name T325
Test name
Test status
Simulation time 160988493 ps
CPU time 2.64 seconds
Started Aug 12 04:54:23 PM PDT 24
Finished Aug 12 04:54:26 PM PDT 24
Peak memory 213596 kb
Host smart-3bc81e16-ced1-47e4-921a-33c5f7fe49ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146758369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1146758369
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1557148530
Short name T340
Test name
Test status
Simulation time 3077653408 ps
CPU time 18.38 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:43 PM PDT 24
Peak memory 221700 kb
Host smart-1794db49-96dc-49d4-9285-c9085b9fe1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557148530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
557148530
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3073399716
Short name T342
Test name
Test status
Simulation time 175544908 ps
CPU time 2.38 seconds
Started Aug 12 04:54:29 PM PDT 24
Finished Aug 12 04:54:31 PM PDT 24
Peak memory 214992 kb
Host smart-6ec6137d-26e8-4940-96be-21bbc10d9edb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073399716 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3073399716
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.946231752
Short name T339
Test name
Test status
Simulation time 256326779 ps
CPU time 2.07 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:26 PM PDT 24
Peak memory 213408 kb
Host smart-c960bea1-8a5e-48bc-9209-96c75d79047d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946231752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.946231752
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1727645382
Short name T275
Test name
Test status
Simulation time 10552610901 ps
CPU time 23.37 seconds
Started Aug 12 04:54:23 PM PDT 24
Finished Aug 12 04:54:47 PM PDT 24
Peak memory 205156 kb
Host smart-27f523d0-960e-4911-a64b-076136d450a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727645382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1727645382
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.620831401
Short name T304
Test name
Test status
Simulation time 2803574042 ps
CPU time 2.95 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:27 PM PDT 24
Peak memory 205140 kb
Host smart-73c5e84b-c1d9-4aad-83d5-88607b01ea41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620831401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.620831401
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1402689861
Short name T394
Test name
Test status
Simulation time 166537991 ps
CPU time 0.81 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:25 PM PDT 24
Peak memory 204892 kb
Host smart-d28a5230-deb6-48c9-bb19-f9034d81ea61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402689861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1402689861
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2582516659
Short name T343
Test name
Test status
Simulation time 322219032 ps
CPU time 4.58 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:28 PM PDT 24
Peak memory 205280 kb
Host smart-ecd63caf-fdc6-44ec-9e4b-6c9d2774a4fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582516659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2582516659
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3489895377
Short name T278
Test name
Test status
Simulation time 338803196 ps
CPU time 4.79 seconds
Started Aug 12 04:54:24 PM PDT 24
Finished Aug 12 04:54:29 PM PDT 24
Peak memory 213540 kb
Host smart-5b28a112-b20e-45e2-88b5-e668449566c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489895377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3489895377
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1136786489
Short name T383
Test name
Test status
Simulation time 821342533 ps
CPU time 3.61 seconds
Started Aug 12 04:54:31 PM PDT 24
Finished Aug 12 04:54:35 PM PDT 24
Peak memory 216104 kb
Host smart-0d343f8c-f13a-4ebb-85e6-4a3efe0403ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136786489 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1136786489
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2383611118
Short name T363
Test name
Test status
Simulation time 279301492 ps
CPU time 2.37 seconds
Started Aug 12 04:54:31 PM PDT 24
Finished Aug 12 04:54:33 PM PDT 24
Peak memory 218628 kb
Host smart-04b34ac9-cf58-4071-af3f-554bba69fbc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383611118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2383611118
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.766141332
Short name T301
Test name
Test status
Simulation time 7601030190 ps
CPU time 7.73 seconds
Started Aug 12 04:54:32 PM PDT 24
Finished Aug 12 04:54:39 PM PDT 24
Peak memory 205136 kb
Host smart-99c43446-102b-415c-b53c-dd50e5273fdc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766141332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.766141332
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.805664544
Short name T321
Test name
Test status
Simulation time 6937548341 ps
CPU time 18.7 seconds
Started Aug 12 04:54:29 PM PDT 24
Finished Aug 12 04:54:48 PM PDT 24
Peak memory 205212 kb
Host smart-90283687-70ec-4a24-8d1e-57aba14c3cf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805664544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.805664544
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1808245927
Short name T87
Test name
Test status
Simulation time 182167084 ps
CPU time 1.07 seconds
Started Aug 12 04:54:30 PM PDT 24
Finished Aug 12 04:54:31 PM PDT 24
Peak memory 204868 kb
Host smart-46f05494-c904-45e7-ac0b-408246291cee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808245927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1808245927
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2702113606
Short name T367
Test name
Test status
Simulation time 295153416 ps
CPU time 4.47 seconds
Started Aug 12 04:54:30 PM PDT 24
Finished Aug 12 04:54:35 PM PDT 24
Peak memory 205328 kb
Host smart-58dd513e-c2b1-47a4-8b1b-c8ee18b4457d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702113606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2702113606
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.991072280
Short name T306
Test name
Test status
Simulation time 482175681 ps
CPU time 6.14 seconds
Started Aug 12 04:54:29 PM PDT 24
Finished Aug 12 04:54:35 PM PDT 24
Peak memory 213508 kb
Host smart-841c1522-f55e-4045-ad4e-56a1114640a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991072280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.991072280
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3601000331
Short name T361
Test name
Test status
Simulation time 370999342 ps
CPU time 4.02 seconds
Started Aug 12 04:54:33 PM PDT 24
Finished Aug 12 04:54:37 PM PDT 24
Peak memory 221548 kb
Host smart-f0c808e5-73c8-4f69-8014-17232df4f4d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601000331 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3601000331
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3610769801
Short name T324
Test name
Test status
Simulation time 373812400 ps
CPU time 2.47 seconds
Started Aug 12 04:54:31 PM PDT 24
Finished Aug 12 04:54:34 PM PDT 24
Peak memory 219368 kb
Host smart-b6063b3c-f163-4e34-b02a-a6a3441f6790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610769801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3610769801
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3418496658
Short name T330
Test name
Test status
Simulation time 35443316013 ps
CPU time 18.11 seconds
Started Aug 12 04:54:31 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 205176 kb
Host smart-bd2e45a4-58f0-4bd1-8ceb-858dd2ee2de1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418496658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3418496658
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.410267611
Short name T378
Test name
Test status
Simulation time 15365204474 ps
CPU time 10.23 seconds
Started Aug 12 04:54:30 PM PDT 24
Finished Aug 12 04:54:40 PM PDT 24
Peak memory 205180 kb
Host smart-debe0871-4a78-4c46-b868-57a43bbdca73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410267611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.410267611
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3748894560
Short name T283
Test name
Test status
Simulation time 410936606 ps
CPU time 1.64 seconds
Started Aug 12 04:54:28 PM PDT 24
Finished Aug 12 04:54:30 PM PDT 24
Peak memory 204832 kb
Host smart-6b6524da-0902-4475-b6cf-aba65e778ef8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748894560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3748894560
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.218169906
Short name T118
Test name
Test status
Simulation time 317075561 ps
CPU time 4.36 seconds
Started Aug 12 04:54:30 PM PDT 24
Finished Aug 12 04:54:35 PM PDT 24
Peak memory 205312 kb
Host smart-f5345e79-b50c-40b8-8085-f435ae936f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218169906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.218169906
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2029392295
Short name T388
Test name
Test status
Simulation time 445895531 ps
CPU time 3.6 seconds
Started Aug 12 04:54:30 PM PDT 24
Finished Aug 12 04:54:34 PM PDT 24
Peak memory 213472 kb
Host smart-f08df3d0-09f0-442e-88ed-555949e8b195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029392295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2029392295
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3007407384
Short name T176
Test name
Test status
Simulation time 4857984684 ps
CPU time 23.72 seconds
Started Aug 12 04:54:31 PM PDT 24
Finished Aug 12 04:54:55 PM PDT 24
Peak memory 219692 kb
Host smart-78b66102-eaba-46a1-8b4c-f2497a242e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007407384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
007407384
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3006667633
Short name T287
Test name
Test status
Simulation time 364011743 ps
CPU time 3.98 seconds
Started Aug 12 04:54:36 PM PDT 24
Finished Aug 12 04:54:41 PM PDT 24
Peak memory 221708 kb
Host smart-e1c8ea38-ec97-4409-842c-4b1eff0102d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006667633 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3006667633
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2773051387
Short name T319
Test name
Test status
Simulation time 146642435 ps
CPU time 1.46 seconds
Started Aug 12 04:54:36 PM PDT 24
Finished Aug 12 04:54:38 PM PDT 24
Peak memory 218400 kb
Host smart-ee429d48-bdb3-4e5e-98fa-4c65005673e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773051387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2773051387
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4081668377
Short name T295
Test name
Test status
Simulation time 30410948 ps
CPU time 0.72 seconds
Started Aug 12 04:54:39 PM PDT 24
Finished Aug 12 04:54:40 PM PDT 24
Peak memory 204868 kb
Host smart-b30763db-dcf4-42f8-9267-8ff61f76acdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081668377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4081668377
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1100850379
Short name T382
Test name
Test status
Simulation time 7106924887 ps
CPU time 18.64 seconds
Started Aug 12 04:54:31 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 205164 kb
Host smart-ae7fd33f-d851-4139-8a0b-5051b3890fc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100850379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1100850379
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2525741648
Short name T258
Test name
Test status
Simulation time 245903576 ps
CPU time 0.83 seconds
Started Aug 12 04:54:32 PM PDT 24
Finished Aug 12 04:54:33 PM PDT 24
Peak memory 204836 kb
Host smart-e7c0f248-bf41-4678-b6fa-1cd9fd5c8c63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525741648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2525741648
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1224789170
Short name T386
Test name
Test status
Simulation time 241692067 ps
CPU time 3.93 seconds
Started Aug 12 04:54:36 PM PDT 24
Finished Aug 12 04:54:40 PM PDT 24
Peak memory 205348 kb
Host smart-92e12a08-d6ef-4f8d-b254-2d01adbdf0e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224789170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1224789170
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3155192944
Short name T337
Test name
Test status
Simulation time 278187165 ps
CPU time 4.92 seconds
Started Aug 12 04:54:39 PM PDT 24
Finished Aug 12 04:54:44 PM PDT 24
Peak memory 213580 kb
Host smart-6fda66c8-a2e9-4912-aba4-6bf60a0143ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155192944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3155192944
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.813187296
Short name T354
Test name
Test status
Simulation time 2880159340 ps
CPU time 10.91 seconds
Started Aug 12 04:54:37 PM PDT 24
Finished Aug 12 04:54:48 PM PDT 24
Peak memory 221788 kb
Host smart-71e5b0e6-5bbc-41fb-a7c2-cb7c69bcc2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813187296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.813187296
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1299718801
Short name T356
Test name
Test status
Simulation time 2112117018 ps
CPU time 4.48 seconds
Started Aug 12 04:54:37 PM PDT 24
Finished Aug 12 04:54:42 PM PDT 24
Peak memory 219000 kb
Host smart-c2c2889b-3724-4c91-b191-1edd7144d838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299718801 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1299718801
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3444364672
Short name T260
Test name
Test status
Simulation time 47129278636 ps
CPU time 77.84 seconds
Started Aug 12 04:54:39 PM PDT 24
Finished Aug 12 04:55:57 PM PDT 24
Peak memory 205248 kb
Host smart-cdb7793e-8c15-4f40-8031-3d74647f9ffd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444364672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3444364672
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1926975513
Short name T381
Test name
Test status
Simulation time 4539057554 ps
CPU time 12.02 seconds
Started Aug 12 04:54:38 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 205192 kb
Host smart-d3dc14ff-ba88-49f8-a46f-2e893e2b7d44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926975513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1926975513
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1251792776
Short name T271
Test name
Test status
Simulation time 196321604 ps
CPU time 1.03 seconds
Started Aug 12 04:54:39 PM PDT 24
Finished Aug 12 04:54:40 PM PDT 24
Peak memory 204916 kb
Host smart-3df6912c-6b5d-4826-b8bb-4b74dbe240ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251792776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1251792776
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2158085985
Short name T120
Test name
Test status
Simulation time 311383305 ps
CPU time 6.63 seconds
Started Aug 12 04:54:38 PM PDT 24
Finished Aug 12 04:54:45 PM PDT 24
Peak memory 205296 kb
Host smart-cb328419-59c1-49ef-ba21-dd0c9ce9c7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158085985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2158085985
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3257880965
Short name T288
Test name
Test status
Simulation time 283658372 ps
CPU time 3.91 seconds
Started Aug 12 04:54:40 PM PDT 24
Finished Aug 12 04:54:44 PM PDT 24
Peak memory 213468 kb
Host smart-1acf054a-6a0c-488c-acfe-b985086697d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257880965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3257880965
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3326889138
Short name T166
Test name
Test status
Simulation time 1911024707 ps
CPU time 12.46 seconds
Started Aug 12 04:54:36 PM PDT 24
Finished Aug 12 04:54:49 PM PDT 24
Peak memory 221680 kb
Host smart-d472077b-7b70-409b-9b0d-d240b754ca32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326889138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
326889138
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3724942677
Short name T334
Test name
Test status
Simulation time 162137226 ps
CPU time 2.27 seconds
Started Aug 12 04:54:45 PM PDT 24
Finished Aug 12 04:54:47 PM PDT 24
Peak memory 214624 kb
Host smart-61e6eea8-c2b9-4695-b3f2-cab7cc1217b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724942677 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3724942677
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2008985412
Short name T280
Test name
Test status
Simulation time 200266413 ps
CPU time 2.23 seconds
Started Aug 12 04:54:38 PM PDT 24
Finished Aug 12 04:54:41 PM PDT 24
Peak memory 218888 kb
Host smart-a07aeb9b-1308-427b-afe8-4698ba7d99d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008985412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2008985412
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1987084675
Short name T391
Test name
Test status
Simulation time 2749247455 ps
CPU time 5.83 seconds
Started Aug 12 04:54:37 PM PDT 24
Finished Aug 12 04:54:43 PM PDT 24
Peak memory 205124 kb
Host smart-bc950233-fee7-4a8e-884c-bcabea6d37af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987084675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1987084675
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1918941796
Short name T289
Test name
Test status
Simulation time 7390521075 ps
CPU time 8.21 seconds
Started Aug 12 04:54:36 PM PDT 24
Finished Aug 12 04:54:45 PM PDT 24
Peak memory 205140 kb
Host smart-47554acc-f8a0-4c83-908c-3914b8f2c221
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918941796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1918941796
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2899670835
Short name T370
Test name
Test status
Simulation time 104146043 ps
CPU time 0.99 seconds
Started Aug 12 04:54:39 PM PDT 24
Finished Aug 12 04:54:40 PM PDT 24
Peak memory 204808 kb
Host smart-a66ffc95-e39a-49d1-b868-635ed9ad7855
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899670835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2899670835
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.309734977
Short name T133
Test name
Test status
Simulation time 3737675092 ps
CPU time 7.71 seconds
Started Aug 12 04:54:37 PM PDT 24
Finished Aug 12 04:54:45 PM PDT 24
Peak memory 205400 kb
Host smart-a2f77f0d-0ce3-47df-9697-9412fb5b5e8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309734977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.309734977
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3186787023
Short name T351
Test name
Test status
Simulation time 69972991 ps
CPU time 3.47 seconds
Started Aug 12 04:54:39 PM PDT 24
Finished Aug 12 04:54:43 PM PDT 24
Peak memory 213576 kb
Host smart-8590e674-e6a7-4d27-b81a-60273d1c276d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186787023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3186787023
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2249623788
Short name T167
Test name
Test status
Simulation time 5727951216 ps
CPU time 20.38 seconds
Started Aug 12 04:54:38 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 221744 kb
Host smart-e1572ceb-e092-439e-b2cb-040bcce80a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249623788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
249623788
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1032337924
Short name T368
Test name
Test status
Simulation time 513842469 ps
CPU time 2.33 seconds
Started Aug 12 04:54:43 PM PDT 24
Finished Aug 12 04:54:46 PM PDT 24
Peak memory 217740 kb
Host smart-fb6b2b5b-60b4-4e62-9978-22ceeede9c3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032337924 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1032337924
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1524238740
Short name T112
Test name
Test status
Simulation time 182406663 ps
CPU time 1.58 seconds
Started Aug 12 04:54:43 PM PDT 24
Finished Aug 12 04:54:45 PM PDT 24
Peak memory 218164 kb
Host smart-6cec222f-464d-4f8b-868e-3902816db23c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524238740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1524238740
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4078050843
Short name T251
Test name
Test status
Simulation time 27443413605 ps
CPU time 38.67 seconds
Started Aug 12 04:54:47 PM PDT 24
Finished Aug 12 04:55:26 PM PDT 24
Peak memory 205268 kb
Host smart-952f2d6c-047f-4f46-a018-03116c4a5d2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078050843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.4078050843
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2831941437
Short name T91
Test name
Test status
Simulation time 1549386899 ps
CPU time 1.94 seconds
Started Aug 12 04:54:45 PM PDT 24
Finished Aug 12 04:54:47 PM PDT 24
Peak memory 205112 kb
Host smart-fe52c217-c540-4733-a5e7-565dcaaedbd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831941437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2831941437
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1440702531
Short name T266
Test name
Test status
Simulation time 1164241755 ps
CPU time 3.62 seconds
Started Aug 12 04:54:44 PM PDT 24
Finished Aug 12 04:54:48 PM PDT 24
Peak memory 204872 kb
Host smart-1a0225fd-967e-4dc7-9346-70f7fa82260f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440702531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1440702531
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2896195840
Short name T362
Test name
Test status
Simulation time 227043543 ps
CPU time 3.97 seconds
Started Aug 12 04:54:44 PM PDT 24
Finished Aug 12 04:54:48 PM PDT 24
Peak memory 205140 kb
Host smart-3f375854-2778-4256-83fa-0076b9417724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896195840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2896195840
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3321541827
Short name T284
Test name
Test status
Simulation time 246551818 ps
CPU time 2.08 seconds
Started Aug 12 04:54:45 PM PDT 24
Finished Aug 12 04:54:47 PM PDT 24
Peak memory 213448 kb
Host smart-ab981f3c-ff01-47a4-bb6a-e2afcbddc087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321541827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3321541827
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2480701581
Short name T75
Test name
Test status
Simulation time 3057892166 ps
CPU time 11.16 seconds
Started Aug 12 04:54:47 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 221704 kb
Host smart-5558c6f4-571c-40d7-a41b-fc001b4cbbee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480701581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
480701581
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2069753884
Short name T293
Test name
Test status
Simulation time 423628373 ps
CPU time 4.41 seconds
Started Aug 12 04:54:44 PM PDT 24
Finished Aug 12 04:54:49 PM PDT 24
Peak memory 221720 kb
Host smart-61ee93d1-c6a2-4d8d-85e9-7db7a59304a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069753884 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2069753884
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3098667379
Short name T262
Test name
Test status
Simulation time 174266592 ps
CPU time 2.31 seconds
Started Aug 12 04:54:43 PM PDT 24
Finished Aug 12 04:54:46 PM PDT 24
Peak memory 213440 kb
Host smart-00f4d768-967f-40ce-8b70-376047980944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098667379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3098667379
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.529244363
Short name T263
Test name
Test status
Simulation time 4974285039 ps
CPU time 7.75 seconds
Started Aug 12 04:54:47 PM PDT 24
Finished Aug 12 04:54:55 PM PDT 24
Peak memory 205216 kb
Host smart-6ed39277-7b92-44f1-8ff5-b19243c5ce64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529244363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.529244363
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.575434591
Short name T305
Test name
Test status
Simulation time 5678241624 ps
CPU time 8.35 seconds
Started Aug 12 04:54:47 PM PDT 24
Finished Aug 12 04:54:55 PM PDT 24
Peak memory 205184 kb
Host smart-c472adc1-46fa-482b-8055-47231dbadeaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575434591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.575434591
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1061734958
Short name T379
Test name
Test status
Simulation time 774749698 ps
CPU time 1.43 seconds
Started Aug 12 04:54:43 PM PDT 24
Finished Aug 12 04:54:45 PM PDT 24
Peak memory 204864 kb
Host smart-d69ef1d1-157f-46ca-bc1a-3a9a998c8169
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061734958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1061734958
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.22371086
Short name T348
Test name
Test status
Simulation time 465308672 ps
CPU time 4.56 seconds
Started Aug 12 04:54:45 PM PDT 24
Finished Aug 12 04:54:50 PM PDT 24
Peak memory 205328 kb
Host smart-1af35505-c3d7-4bd0-89ee-4468516353e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_c
sr_outstanding.22371086
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.348307161
Short name T316
Test name
Test status
Simulation time 293063235 ps
CPU time 4.64 seconds
Started Aug 12 04:54:43 PM PDT 24
Finished Aug 12 04:54:48 PM PDT 24
Peak memory 213552 kb
Host smart-8d6493b0-aa88-4f25-ac9f-7b02058d50c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348307161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.348307161
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3246884543
Short name T171
Test name
Test status
Simulation time 1186690542 ps
CPU time 10.49 seconds
Started Aug 12 04:54:46 PM PDT 24
Finished Aug 12 04:54:57 PM PDT 24
Peak memory 221640 kb
Host smart-7ef2d996-818b-480d-963e-db66e20ee251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246884543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
246884543
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4209797235
Short name T286
Test name
Test status
Simulation time 286029669 ps
CPU time 3.93 seconds
Started Aug 12 04:54:50 PM PDT 24
Finished Aug 12 04:54:54 PM PDT 24
Peak memory 218704 kb
Host smart-acd97667-bbbf-42fb-8a8e-137a5bf588b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209797235 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4209797235
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.4140845533
Short name T125
Test name
Test status
Simulation time 110133228 ps
CPU time 1.63 seconds
Started Aug 12 04:54:51 PM PDT 24
Finished Aug 12 04:54:52 PM PDT 24
Peak memory 213556 kb
Host smart-e6067f6f-c6a8-472d-bf5d-cc9ca3bd49df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140845533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4140845533
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2976840854
Short name T375
Test name
Test status
Simulation time 72831662589 ps
CPU time 190.9 seconds
Started Aug 12 04:54:45 PM PDT 24
Finished Aug 12 04:57:56 PM PDT 24
Peak memory 205304 kb
Host smart-ba0a5132-c132-4478-aa30-8623dcdee707
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976840854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2976840854
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2081960253
Short name T303
Test name
Test status
Simulation time 4684104320 ps
CPU time 13.72 seconds
Started Aug 12 04:54:44 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 205124 kb
Host smart-8a69fa54-88e3-4439-9dfe-e910f4de73f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081960253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2081960253
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2695314311
Short name T272
Test name
Test status
Simulation time 950137234 ps
CPU time 2.17 seconds
Started Aug 12 04:54:44 PM PDT 24
Finished Aug 12 04:54:47 PM PDT 24
Peak memory 204884 kb
Host smart-878bb843-61b4-4930-a5ae-33ef11977e67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695314311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2695314311
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1696898400
Short name T113
Test name
Test status
Simulation time 942903217 ps
CPU time 4.84 seconds
Started Aug 12 04:54:51 PM PDT 24
Finished Aug 12 04:54:56 PM PDT 24
Peak memory 205156 kb
Host smart-f6b1bb74-b99d-4c9f-9773-87a7c0ed15a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696898400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1696898400
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1380209777
Short name T385
Test name
Test status
Simulation time 204220735 ps
CPU time 3.51 seconds
Started Aug 12 04:54:43 PM PDT 24
Finished Aug 12 04:54:47 PM PDT 24
Peak memory 213452 kb
Host smart-95f1eb68-6d3a-430e-b69e-ae80e4c13b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380209777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1380209777
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2414444042
Short name T174
Test name
Test status
Simulation time 1142398589 ps
CPU time 11.48 seconds
Started Aug 12 04:54:45 PM PDT 24
Finished Aug 12 04:54:56 PM PDT 24
Peak memory 221500 kb
Host smart-b540e47b-d288-4ed0-9314-72cf0a070e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414444042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
414444042
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2948881874
Short name T349
Test name
Test status
Simulation time 7095220589 ps
CPU time 27.96 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:54:04 PM PDT 24
Peak memory 213684 kb
Host smart-aa7a916d-cb80-475d-8def-2c607e27b9d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948881874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2948881874
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3792483971
Short name T329
Test name
Test status
Simulation time 489701753 ps
CPU time 3.98 seconds
Started Aug 12 04:53:39 PM PDT 24
Finished Aug 12 04:53:43 PM PDT 24
Peak memory 218888 kb
Host smart-71228651-fd16-4e21-a32d-e59e42984222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792483971 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3792483971
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3880704745
Short name T127
Test name
Test status
Simulation time 178107622 ps
CPU time 2.24 seconds
Started Aug 12 04:53:37 PM PDT 24
Finished Aug 12 04:53:40 PM PDT 24
Peak memory 213536 kb
Host smart-f47b6777-2581-4be9-b990-a60617803cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880704745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3880704745
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.496448154
Short name T248
Test name
Test status
Simulation time 71531017194 ps
CPU time 184.94 seconds
Started Aug 12 04:53:37 PM PDT 24
Finished Aug 12 04:56:42 PM PDT 24
Peak memory 205140 kb
Host smart-7413bf32-a588-4f43-982f-e86db88ed9e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496448154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.496448154
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4009417080
Short name T389
Test name
Test status
Simulation time 13192179213 ps
CPU time 36.01 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:54:12 PM PDT 24
Peak memory 205200 kb
Host smart-18476c56-2bbb-48d4-9411-9b38781963bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009417080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.4009417080
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3960378622
Short name T317
Test name
Test status
Simulation time 1732825697 ps
CPU time 1.69 seconds
Started Aug 12 04:53:36 PM PDT 24
Finished Aug 12 04:53:38 PM PDT 24
Peak memory 205012 kb
Host smart-9d1ca7e7-7c5f-477f-8819-8d599da2ed44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960378622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
960378622
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1495204515
Short name T328
Test name
Test status
Simulation time 653616188 ps
CPU time 2.56 seconds
Started Aug 12 04:53:37 PM PDT 24
Finished Aug 12 04:53:40 PM PDT 24
Peak memory 204856 kb
Host smart-1f0ce281-edb4-4c0f-9cf9-64ba2655b2b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495204515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1495204515
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.171878518
Short name T359
Test name
Test status
Simulation time 9359418133 ps
CPU time 6.54 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:53:42 PM PDT 24
Peak memory 205184 kb
Host smart-431b5708-e265-4300-a61c-53c1558fff17
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171878518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.171878518
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2560377110
Short name T274
Test name
Test status
Simulation time 329207605 ps
CPU time 0.96 seconds
Started Aug 12 04:53:36 PM PDT 24
Finished Aug 12 04:53:37 PM PDT 24
Peak memory 204888 kb
Host smart-cb454f02-0aa5-4b37-b4c9-e1022bc0be56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560377110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2560377110
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4274961990
Short name T73
Test name
Test status
Simulation time 147481667 ps
CPU time 0.95 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:53:36 PM PDT 24
Peak memory 204840 kb
Host smart-215f222d-5238-455e-ad1d-275d74d328fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274961990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4
274961990
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1657398579
Short name T320
Test name
Test status
Simulation time 60107087 ps
CPU time 0.86 seconds
Started Aug 12 04:53:34 PM PDT 24
Finished Aug 12 04:53:36 PM PDT 24
Peak memory 204864 kb
Host smart-3158ee67-1dad-4d62-b2be-968038f94995
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657398579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1657398579
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.447039483
Short name T249
Test name
Test status
Simulation time 149340204 ps
CPU time 0.77 seconds
Started Aug 12 04:53:37 PM PDT 24
Finished Aug 12 04:53:38 PM PDT 24
Peak memory 204824 kb
Host smart-95e08976-6ab1-4b74-81c8-6d5212d96bc5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447039483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.447039483
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4239885660
Short name T131
Test name
Test status
Simulation time 126571747 ps
CPU time 3.92 seconds
Started Aug 12 04:53:41 PM PDT 24
Finished Aug 12 04:53:45 PM PDT 24
Peak memory 205348 kb
Host smart-ef6fa5db-445d-4c05-9eb1-7d53a8db791a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239885660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.4239885660
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.461468038
Short name T360
Test name
Test status
Simulation time 9630895028 ps
CPU time 16.29 seconds
Started Aug 12 04:53:36 PM PDT 24
Finished Aug 12 04:53:52 PM PDT 24
Peak memory 216660 kb
Host smart-32cdd3e6-b522-4d5b-9ce4-ea9553774cce
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461468038 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.461468038
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1598785030
Short name T393
Test name
Test status
Simulation time 1031576719 ps
CPU time 4.98 seconds
Started Aug 12 04:53:35 PM PDT 24
Finished Aug 12 04:53:40 PM PDT 24
Peak memory 213548 kb
Host smart-1ef6a8ac-7189-483f-9602-a22b7becfc59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598785030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1598785030
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2327135241
Short name T276
Test name
Test status
Simulation time 8267663989 ps
CPU time 32.04 seconds
Started Aug 12 04:53:44 PM PDT 24
Finished Aug 12 04:54:17 PM PDT 24
Peak memory 213584 kb
Host smart-be7b35a9-dda6-418a-a725-a0054cef3916
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327135241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2327135241
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.326190575
Short name T130
Test name
Test status
Simulation time 1474492816 ps
CPU time 52.35 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:54:42 PM PDT 24
Peak memory 205288 kb
Host smart-40de5173-81a0-48c8-b907-846bc35c2173
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326190575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.326190575
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1525805491
Short name T70
Test name
Test status
Simulation time 569610164 ps
CPU time 2.64 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:53:51 PM PDT 24
Peak memory 213448 kb
Host smart-4057e31b-c5fd-4f57-8edb-6f6c6d87f19c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525805491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1525805491
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.921229217
Short name T257
Test name
Test status
Simulation time 91295577 ps
CPU time 2.72 seconds
Started Aug 12 04:53:52 PM PDT 24
Finished Aug 12 04:53:55 PM PDT 24
Peak memory 218120 kb
Host smart-83db656c-bf3e-44b3-aa53-3d1b8635186c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921229217 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.921229217
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3260303660
Short name T326
Test name
Test status
Simulation time 113777840 ps
CPU time 1.73 seconds
Started Aug 12 04:53:48 PM PDT 24
Finished Aug 12 04:53:50 PM PDT 24
Peak memory 213360 kb
Host smart-dd6a3839-22d1-4e33-8ed4-6ddf9053d742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260303660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3260303660
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.932633835
Short name T296
Test name
Test status
Simulation time 25915953140 ps
CPU time 75.56 seconds
Started Aug 12 04:53:48 PM PDT 24
Finished Aug 12 04:55:03 PM PDT 24
Peak memory 205164 kb
Host smart-79cdb11e-3be5-4670-86ae-16780abbb58b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932633835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.932633835
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.174561381
Short name T377
Test name
Test status
Simulation time 9982232394 ps
CPU time 29.32 seconds
Started Aug 12 04:53:51 PM PDT 24
Finished Aug 12 04:54:21 PM PDT 24
Peak memory 205164 kb
Host smart-b0903a81-f85c-4e8e-b217-19940096e571
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174561381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.174561381
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.501009408
Short name T89
Test name
Test status
Simulation time 2348856939 ps
CPU time 7.54 seconds
Started Aug 12 04:53:48 PM PDT 24
Finished Aug 12 04:53:56 PM PDT 24
Peak memory 205264 kb
Host smart-4b4610c3-6944-4645-83bd-59dcbb0937c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501009408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.501009408
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1871346622
Short name T387
Test name
Test status
Simulation time 5978776925 ps
CPU time 8.07 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:53:57 PM PDT 24
Peak memory 205188 kb
Host smart-96f5d690-a7fe-453e-b1f0-adcc419daaad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871346622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
871346622
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2051355710
Short name T85
Test name
Test status
Simulation time 798980086 ps
CPU time 1.31 seconds
Started Aug 12 04:53:42 PM PDT 24
Finished Aug 12 04:53:43 PM PDT 24
Peak memory 204840 kb
Host smart-57ac3c57-2ea3-4e35-b07c-fa7f4873e34f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051355710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2051355710
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4256655729
Short name T392
Test name
Test status
Simulation time 8471283337 ps
CPU time 23.25 seconds
Started Aug 12 04:53:41 PM PDT 24
Finished Aug 12 04:54:05 PM PDT 24
Peak memory 205296 kb
Host smart-5ae538d1-0348-4cb5-a9d9-ea7b8122385e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256655729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.4256655729
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4044532732
Short name T259
Test name
Test status
Simulation time 276583817 ps
CPU time 1.32 seconds
Started Aug 12 04:53:41 PM PDT 24
Finished Aug 12 04:53:43 PM PDT 24
Peak memory 204908 kb
Host smart-8fb4567e-e98c-4a5f-aae2-02c77108d534
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044532732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4044532732
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3160472567
Short name T353
Test name
Test status
Simulation time 175108160 ps
CPU time 0.87 seconds
Started Aug 12 04:53:42 PM PDT 24
Finished Aug 12 04:53:43 PM PDT 24
Peak memory 204828 kb
Host smart-6145f2aa-1a37-4ead-a977-086ea066adf2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160472567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
160472567
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1494377411
Short name T366
Test name
Test status
Simulation time 163669224 ps
CPU time 0.76 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:53:50 PM PDT 24
Peak memory 204848 kb
Host smart-96e96f3b-05e1-444e-bc38-9543949c938e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494377411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1494377411
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1483144471
Short name T333
Test name
Test status
Simulation time 110831991 ps
CPU time 0.76 seconds
Started Aug 12 04:53:47 PM PDT 24
Finished Aug 12 04:53:48 PM PDT 24
Peak memory 204824 kb
Host smart-dd75ebd9-6ecd-40cb-b5a5-770d5da8aa4b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483144471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1483144471
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.750877087
Short name T97
Test name
Test status
Simulation time 2050637764 ps
CPU time 4.48 seconds
Started Aug 12 04:53:50 PM PDT 24
Finished Aug 12 04:53:54 PM PDT 24
Peak memory 205336 kb
Host smart-2281ff62-007a-444c-8e28-e166ffeb8e53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750877087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.750877087
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4056663780
Short name T107
Test name
Test status
Simulation time 1836651091 ps
CPU time 11.17 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:54:01 PM PDT 24
Peak memory 213484 kb
Host smart-23732a4f-f7d5-41bd-971a-524abd02f52f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056663780 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4056663780
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.953330267
Short name T254
Test name
Test status
Simulation time 1592843658 ps
CPU time 5.14 seconds
Started Aug 12 04:53:50 PM PDT 24
Finished Aug 12 04:53:56 PM PDT 24
Peak memory 213460 kb
Host smart-7c90e3f1-253f-420b-b61a-c9c697e182d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953330267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.953330267
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4265111694
Short name T173
Test name
Test status
Simulation time 1389217477 ps
CPU time 19.65 seconds
Started Aug 12 04:53:50 PM PDT 24
Finished Aug 12 04:54:10 PM PDT 24
Peak memory 213428 kb
Host smart-348e2550-8d66-4dd5-86dd-d49cbac3ae8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265111694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.4265111694
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1813847926
Short name T372
Test name
Test status
Simulation time 1253512794 ps
CPU time 28.2 seconds
Started Aug 12 04:53:50 PM PDT 24
Finished Aug 12 04:54:18 PM PDT 24
Peak memory 213548 kb
Host smart-d04b528c-d7e8-4a19-ac47-2836b449a814
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813847926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1813847926
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.631608669
Short name T358
Test name
Test status
Simulation time 784905053 ps
CPU time 26.77 seconds
Started Aug 12 04:53:55 PM PDT 24
Finished Aug 12 04:54:22 PM PDT 24
Peak memory 205308 kb
Host smart-c6c56eda-8da1-4f99-904c-fee61f70c46b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631608669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.631608669
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1281616876
Short name T315
Test name
Test status
Simulation time 297642413 ps
CPU time 1.8 seconds
Started Aug 12 04:53:56 PM PDT 24
Finished Aug 12 04:53:58 PM PDT 24
Peak memory 213500 kb
Host smart-f7ec3e7b-9012-4a45-9949-50dae3d5a59f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281616876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1281616876
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.190602539
Short name T345
Test name
Test status
Simulation time 338873840 ps
CPU time 2.36 seconds
Started Aug 12 04:54:04 PM PDT 24
Finished Aug 12 04:54:06 PM PDT 24
Peak memory 214500 kb
Host smart-c91933bf-14d6-405e-aea3-ebb993dccc2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190602539 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.190602539
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1946583591
Short name T142
Test name
Test status
Simulation time 134878695 ps
CPU time 2.56 seconds
Started Aug 12 04:53:55 PM PDT 24
Finished Aug 12 04:53:58 PM PDT 24
Peak memory 218872 kb
Host smart-dbeb83f0-5fa9-4b3b-bde7-30f7000c4127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946583591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1946583591
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.801967360
Short name T318
Test name
Test status
Simulation time 84843780068 ps
CPU time 222.9 seconds
Started Aug 12 04:53:56 PM PDT 24
Finished Aug 12 04:57:39 PM PDT 24
Peak memory 205172 kb
Host smart-53d1a36d-2e0e-4e63-acbb-3274e7e95556
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801967360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.801967360
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3640758485
Short name T92
Test name
Test status
Simulation time 4573894189 ps
CPU time 4.58 seconds
Started Aug 12 04:53:58 PM PDT 24
Finished Aug 12 04:54:03 PM PDT 24
Peak memory 205296 kb
Host smart-0b1bea91-c72b-4428-a0c5-c86cd27f3ab4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640758485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3640758485
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3050217232
Short name T285
Test name
Test status
Simulation time 7956717068 ps
CPU time 13.41 seconds
Started Aug 12 04:53:59 PM PDT 24
Finished Aug 12 04:54:12 PM PDT 24
Peak memory 205180 kb
Host smart-c66c2a3e-bb67-4c14-aecd-e8ef309d25c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050217232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
050217232
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1113416329
Short name T86
Test name
Test status
Simulation time 404727648 ps
CPU time 1.71 seconds
Started Aug 12 04:53:51 PM PDT 24
Finished Aug 12 04:53:53 PM PDT 24
Peak memory 204832 kb
Host smart-4d5f4c6f-8e6c-4db5-a4b7-a60a588b007a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113416329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1113416329
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2076010885
Short name T352
Test name
Test status
Simulation time 7104788976 ps
CPU time 7.04 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:53:56 PM PDT 24
Peak memory 205204 kb
Host smart-80c99006-5b92-446c-b9c6-5a583fad8b41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076010885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2076010885
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2566674958
Short name T282
Test name
Test status
Simulation time 616247608 ps
CPU time 1.2 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:53:51 PM PDT 24
Peak memory 204896 kb
Host smart-372a9053-00c6-4c83-9f14-875cb61f4a94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566674958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2566674958
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.623330832
Short name T255
Test name
Test status
Simulation time 922253819 ps
CPU time 1.72 seconds
Started Aug 12 04:53:49 PM PDT 24
Finished Aug 12 04:53:51 PM PDT 24
Peak memory 204904 kb
Host smart-10a72f81-5cba-46cf-ae04-f0c0182cfacb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623330832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.623330832
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3620060212
Short name T331
Test name
Test status
Simulation time 81465361 ps
CPU time 0.88 seconds
Started Aug 12 04:53:55 PM PDT 24
Finished Aug 12 04:53:56 PM PDT 24
Peak memory 204868 kb
Host smart-48330760-7dda-44de-ac42-d969b8d1be40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620060212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3620060212
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3913845977
Short name T77
Test name
Test status
Simulation time 73453704 ps
CPU time 0.79 seconds
Started Aug 12 04:53:54 PM PDT 24
Finished Aug 12 04:53:55 PM PDT 24
Peak memory 204916 kb
Host smart-2fcfd30e-ba3f-460b-bff7-fc5cb26a9dd8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913845977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3913845977
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2002872604
Short name T80
Test name
Test status
Simulation time 2238210701 ps
CPU time 9.8 seconds
Started Aug 12 04:53:56 PM PDT 24
Finished Aug 12 04:54:06 PM PDT 24
Peak memory 214576 kb
Host smart-6604271e-8b23-4ec7-89c7-b640981d4c5f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002872604 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2002872604
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.195587387
Short name T350
Test name
Test status
Simulation time 164507747 ps
CPU time 2.61 seconds
Started Aug 12 04:53:54 PM PDT 24
Finished Aug 12 04:53:57 PM PDT 24
Peak memory 213532 kb
Host smart-9977dea8-597f-4080-90fd-0e3df2677262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195587387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.195587387
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3501377559
Short name T106
Test name
Test status
Simulation time 125745859 ps
CPU time 3.17 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:06 PM PDT 24
Peak memory 219556 kb
Host smart-93c890f5-6f26-484e-bf50-43043ba9cfa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501377559 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3501377559
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3366456446
Short name T126
Test name
Test status
Simulation time 413829314 ps
CPU time 2.74 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:06 PM PDT 24
Peak memory 219052 kb
Host smart-0895c988-4475-4f3a-b2e2-61c46f2f4972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366456446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3366456446
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2493272162
Short name T309
Test name
Test status
Simulation time 5145528383 ps
CPU time 8.32 seconds
Started Aug 12 04:54:02 PM PDT 24
Finished Aug 12 04:54:11 PM PDT 24
Peak memory 205240 kb
Host smart-bf09c41c-91b9-4d9e-b95e-78c8bdf27c96
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493272162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2493272162
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4119864975
Short name T332
Test name
Test status
Simulation time 12485851910 ps
CPU time 33.99 seconds
Started Aug 12 04:54:04 PM PDT 24
Finished Aug 12 04:54:38 PM PDT 24
Peak memory 205212 kb
Host smart-89aa5a03-510a-4886-b0f6-4bd5f0095436
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119864975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
119864975
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2298964507
Short name T268
Test name
Test status
Simulation time 311945682 ps
CPU time 1.45 seconds
Started Aug 12 04:54:04 PM PDT 24
Finished Aug 12 04:54:05 PM PDT 24
Peak memory 204864 kb
Host smart-507cf8f9-1581-4ec7-8be9-d051efd73baf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298964507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
298964507
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2046240890
Short name T109
Test name
Test status
Simulation time 1454074849 ps
CPU time 3.76 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:07 PM PDT 24
Peak memory 205268 kb
Host smart-61c01830-7cbb-4687-a02e-1ecb3828f2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046240890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2046240890
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2541376675
Short name T347
Test name
Test status
Simulation time 1950632174 ps
CPU time 22.66 seconds
Started Aug 12 04:54:04 PM PDT 24
Finished Aug 12 04:54:27 PM PDT 24
Peak memory 216060 kb
Host smart-dd9a13f4-a933-4b8f-883c-e3fc988f79bf
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541376675 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2541376675
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.22881734
Short name T105
Test name
Test status
Simulation time 270524786 ps
CPU time 4.91 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:08 PM PDT 24
Peak memory 213516 kb
Host smart-880c85da-71f1-4f91-8429-5169d5019a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.22881734
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3964499387
Short name T292
Test name
Test status
Simulation time 443843520 ps
CPU time 2.35 seconds
Started Aug 12 04:54:09 PM PDT 24
Finished Aug 12 04:54:12 PM PDT 24
Peak memory 217256 kb
Host smart-bfda7c09-a2c5-47b5-bae1-bcbc85d7d41d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964499387 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3964499387
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3633672147
Short name T129
Test name
Test status
Simulation time 57315840 ps
CPU time 1.39 seconds
Started Aug 12 04:54:09 PM PDT 24
Finished Aug 12 04:54:10 PM PDT 24
Peak memory 218676 kb
Host smart-a407fd20-4e2c-4042-a52c-edfb4ac1085b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633672147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3633672147
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4202428792
Short name T294
Test name
Test status
Simulation time 25667086091 ps
CPU time 17.25 seconds
Started Aug 12 04:54:02 PM PDT 24
Finished Aug 12 04:54:19 PM PDT 24
Peak memory 205272 kb
Host smart-9c8f950a-2ced-4af3-aca8-f003e876d5ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202428792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.4202428792
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1734172260
Short name T299
Test name
Test status
Simulation time 1406024778 ps
CPU time 4.95 seconds
Started Aug 12 04:54:06 PM PDT 24
Finished Aug 12 04:54:11 PM PDT 24
Peak memory 205036 kb
Host smart-abbfd137-5323-4207-b109-d4081ad48916
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734172260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
734172260
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.220033549
Short name T298
Test name
Test status
Simulation time 345498248 ps
CPU time 1.49 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:05 PM PDT 24
Peak memory 204852 kb
Host smart-14dc51bc-cd88-4c66-b363-e4e418828a8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220033549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.220033549
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2603150651
Short name T124
Test name
Test status
Simulation time 443094877 ps
CPU time 7.3 seconds
Started Aug 12 04:54:10 PM PDT 24
Finished Aug 12 04:54:17 PM PDT 24
Peak memory 205240 kb
Host smart-72dcdf42-b631-4ded-bd68-6765c1e56a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603150651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2603150651
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4250042220
Short name T84
Test name
Test status
Simulation time 16638226892 ps
CPU time 41.87 seconds
Started Aug 12 04:54:03 PM PDT 24
Finished Aug 12 04:54:45 PM PDT 24
Peak memory 221300 kb
Host smart-c2b8af10-297d-4cb3-9a05-30965658e7f1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250042220 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.4250042220
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.449420440
Short name T323
Test name
Test status
Simulation time 509478090 ps
CPU time 4.45 seconds
Started Aug 12 04:54:14 PM PDT 24
Finished Aug 12 04:54:19 PM PDT 24
Peak memory 213548 kb
Host smart-94e2c713-4fa3-4626-b33f-4d4d0b676e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449420440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.449420440
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3817828477
Short name T170
Test name
Test status
Simulation time 2947950467 ps
CPU time 17.72 seconds
Started Aug 12 04:54:12 PM PDT 24
Finished Aug 12 04:54:30 PM PDT 24
Peak memory 221720 kb
Host smart-f7d6feaa-e626-4a25-a3e7-cecaf6b5d44f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817828477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3817828477
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.23387102
Short name T140
Test name
Test status
Simulation time 109035712 ps
CPU time 2.19 seconds
Started Aug 12 04:54:15 PM PDT 24
Finished Aug 12 04:54:17 PM PDT 24
Peak memory 220708 kb
Host smart-6ab9dd13-8290-4312-8145-61b7a50c0ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387102 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.23387102
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1014233440
Short name T114
Test name
Test status
Simulation time 157511839 ps
CPU time 2.17 seconds
Started Aug 12 04:54:10 PM PDT 24
Finished Aug 12 04:54:12 PM PDT 24
Peak memory 218912 kb
Host smart-48dcb79f-286e-40ec-8228-918bdb77b59d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014233440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1014233440
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2231944569
Short name T371
Test name
Test status
Simulation time 37797664 ps
CPU time 0.83 seconds
Started Aug 12 04:54:09 PM PDT 24
Finished Aug 12 04:54:10 PM PDT 24
Peak memory 204816 kb
Host smart-eeed19c9-fe08-4972-9372-196accacdfe4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231944569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2231944569
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2800419531
Short name T322
Test name
Test status
Simulation time 2998740463 ps
CPU time 2.63 seconds
Started Aug 12 04:54:10 PM PDT 24
Finished Aug 12 04:54:12 PM PDT 24
Peak memory 205236 kb
Host smart-2bdcdba3-dc13-44a1-8824-1954d90f9cb7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800419531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
800419531
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4061249370
Short name T369
Test name
Test status
Simulation time 436872447 ps
CPU time 1.88 seconds
Started Aug 12 04:54:14 PM PDT 24
Finished Aug 12 04:54:16 PM PDT 24
Peak memory 204844 kb
Host smart-5fa7c706-7db9-4587-83f5-b3dd4276ac0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061249370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4
061249370
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.253260756
Short name T123
Test name
Test status
Simulation time 456287285 ps
CPU time 4.19 seconds
Started Aug 12 04:54:09 PM PDT 24
Finished Aug 12 04:54:13 PM PDT 24
Peak memory 205300 kb
Host smart-32e6e1ca-bf7c-44ca-b46a-ace45831aacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253260756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.253260756
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1816823265
Short name T357
Test name
Test status
Simulation time 1086080168 ps
CPU time 7.11 seconds
Started Aug 12 04:54:15 PM PDT 24
Finished Aug 12 04:54:22 PM PDT 24
Peak memory 221608 kb
Host smart-155ece41-47df-4d82-a7d5-bc0e169d61cf
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816823265 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1816823265
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.436535695
Short name T269
Test name
Test status
Simulation time 93342289 ps
CPU time 4.05 seconds
Started Aug 12 04:54:10 PM PDT 24
Finished Aug 12 04:54:14 PM PDT 24
Peak memory 213504 kb
Host smart-55ee404c-ad71-4de7-b186-d36374def959
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436535695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.436535695
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3670173014
Short name T169
Test name
Test status
Simulation time 1595238627 ps
CPU time 8.7 seconds
Started Aug 12 04:54:10 PM PDT 24
Finished Aug 12 04:54:19 PM PDT 24
Peak memory 213424 kb
Host smart-a05a5fe5-a6f2-4ecb-af0e-5f5a43dcddd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670173014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3670173014
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3110276046
Short name T314
Test name
Test status
Simulation time 962490163 ps
CPU time 2.33 seconds
Started Aug 12 04:54:18 PM PDT 24
Finished Aug 12 04:54:20 PM PDT 24
Peak memory 217204 kb
Host smart-3e0c68d0-ef20-4873-897c-7ba0f3a0582b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110276046 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3110276046
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1903977333
Short name T116
Test name
Test status
Simulation time 156115854 ps
CPU time 1.65 seconds
Started Aug 12 04:54:18 PM PDT 24
Finished Aug 12 04:54:20 PM PDT 24
Peak memory 218536 kb
Host smart-bc279d28-f08f-4233-8961-8645d5f61c76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903977333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1903977333
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2682125922
Short name T327
Test name
Test status
Simulation time 15816564511 ps
CPU time 13.99 seconds
Started Aug 12 04:54:16 PM PDT 24
Finished Aug 12 04:54:30 PM PDT 24
Peak memory 205176 kb
Host smart-d6fac10d-a9f4-49e5-80b7-29016b3cd677
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682125922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2682125922
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1941899677
Short name T277
Test name
Test status
Simulation time 7596033316 ps
CPU time 10.69 seconds
Started Aug 12 04:54:09 PM PDT 24
Finished Aug 12 04:54:20 PM PDT 24
Peak memory 205228 kb
Host smart-fd7191d4-b2f0-49e9-bc06-6936c4979ad6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941899677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
941899677
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1833493363
Short name T302
Test name
Test status
Simulation time 358662596 ps
CPU time 1.5 seconds
Started Aug 12 04:54:09 PM PDT 24
Finished Aug 12 04:54:11 PM PDT 24
Peak memory 204820 kb
Host smart-2aaa131c-d99b-476c-bdc2-b0974a9358ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833493363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
833493363
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2732045134
Short name T390
Test name
Test status
Simulation time 276856590 ps
CPU time 4.06 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:22 PM PDT 24
Peak memory 205384 kb
Host smart-246e63da-0335-44a0-9179-b047ee708f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732045134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2732045134
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.698894284
Short name T374
Test name
Test status
Simulation time 3852753803 ps
CPU time 29.03 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:46 PM PDT 24
Peak memory 221280 kb
Host smart-1ed89065-e84d-4e5b-aa42-63c4489228dd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698894284 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.698894284
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2787269694
Short name T139
Test name
Test status
Simulation time 126029260 ps
CPU time 2.79 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:20 PM PDT 24
Peak memory 213608 kb
Host smart-d4adfe84-30a3-4332-872e-a1bb3bce30ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787269694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2787269694
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3641738564
Short name T297
Test name
Test status
Simulation time 249841028 ps
CPU time 4.87 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:22 PM PDT 24
Peak memory 219864 kb
Host smart-5c216d9a-3f57-4ebb-b878-a15a810ca06e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641738564 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3641738564
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.377214055
Short name T135
Test name
Test status
Simulation time 221404632 ps
CPU time 2.34 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:19 PM PDT 24
Peak memory 218992 kb
Host smart-a2f11953-079a-412d-943f-3cda4f1ae097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377214055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.377214055
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.52472328
Short name T270
Test name
Test status
Simulation time 12933790943 ps
CPU time 7.74 seconds
Started Aug 12 04:54:18 PM PDT 24
Finished Aug 12 04:54:26 PM PDT 24
Peak memory 205300 kb
Host smart-e88199a9-e6f2-466d-8004-b1a0c8cf4f1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52472328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv
_dm_jtag_dmi_csr_bit_bash.52472328
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1500490464
Short name T300
Test name
Test status
Simulation time 4269876627 ps
CPU time 3.54 seconds
Started Aug 12 04:54:19 PM PDT 24
Finished Aug 12 04:54:23 PM PDT 24
Peak memory 205120 kb
Host smart-1c281a87-8a59-4053-a18d-d5b35c031d67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500490464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
500490464
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2868667354
Short name T253
Test name
Test status
Simulation time 183436355 ps
CPU time 0.83 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:18 PM PDT 24
Peak memory 204872 kb
Host smart-bfefef80-fc53-4757-8d6f-33b6fd93b03a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868667354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
868667354
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2679894050
Short name T134
Test name
Test status
Simulation time 363265742 ps
CPU time 6.64 seconds
Started Aug 12 04:54:19 PM PDT 24
Finished Aug 12 04:54:26 PM PDT 24
Peak memory 205320 kb
Host smart-a4850c00-b16a-4971-84e8-c9817dd8bb30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679894050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2679894050
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2663074986
Short name T177
Test name
Test status
Simulation time 3255693336 ps
CPU time 14.07 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:31 PM PDT 24
Peak memory 221452 kb
Host smart-825680f8-c0b2-4ed4-bbca-37674fc42685
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663074986 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2663074986
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.615835308
Short name T364
Test name
Test status
Simulation time 615163121 ps
CPU time 6.36 seconds
Started Aug 12 04:54:17 PM PDT 24
Finished Aug 12 04:54:23 PM PDT 24
Peak memory 213496 kb
Host smart-a436f829-500c-4e6c-8da6-ddbc1b70ded3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615835308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.615835308
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.898769550
Short name T175
Test name
Test status
Simulation time 6200361027 ps
CPU time 29.73 seconds
Started Aug 12 04:54:19 PM PDT 24
Finished Aug 12 04:54:49 PM PDT 24
Peak memory 221756 kb
Host smart-964d4730-9e07-4161-b60f-c2b526adc257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898769550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.898769550
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3010118805
Short name T212
Test name
Test status
Simulation time 81643948 ps
CPU time 0.76 seconds
Started Aug 12 04:54:56 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 205084 kb
Host smart-a7704876-3c11-4761-894c-cb0d5572a903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010118805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3010118805
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_buffered_enable.2833180978
Short name T235
Test name
Test status
Simulation time 213423442 ps
CPU time 1.24 seconds
Started Aug 12 04:54:58 PM PDT 24
Finished Aug 12 04:55:00 PM PDT 24
Peak memory 234372 kb
Host smart-938b1568-3b17-46f3-a927-2365812e8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833180978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.2833180978
Directory /workspace/0.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1512149070
Short name T21
Test name
Test status
Simulation time 1005254373 ps
CPU time 3.31 seconds
Started Aug 12 04:54:53 PM PDT 24
Finished Aug 12 04:54:57 PM PDT 24
Peak memory 205052 kb
Host smart-b8a6bd9b-916e-409a-8eae-f28b28f9e3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512149070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1512149070
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2718321463
Short name T205
Test name
Test status
Simulation time 287156255 ps
CPU time 1.39 seconds
Started Aug 12 04:54:51 PM PDT 24
Finished Aug 12 04:54:52 PM PDT 24
Peak memory 205128 kb
Host smart-5b5991fe-526d-4d80-a004-5a9b87d221f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718321463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2718321463
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3007461936
Short name T217
Test name
Test status
Simulation time 183590335 ps
CPU time 0.78 seconds
Started Aug 12 04:54:52 PM PDT 24
Finished Aug 12 04:54:53 PM PDT 24
Peak memory 205060 kb
Host smart-f6bc1392-3664-4305-aab4-83b0509f206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007461936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3007461936
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2530612298
Short name T144
Test name
Test status
Simulation time 72193871 ps
CPU time 1.04 seconds
Started Aug 12 04:54:58 PM PDT 24
Finished Aug 12 04:55:00 PM PDT 24
Peak memory 215304 kb
Host smart-b8f82dd1-f2ac-4594-ba51-f83688d81473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530612298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2530612298
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.356187158
Short name T57
Test name
Test status
Simulation time 160998506 ps
CPU time 0.8 seconds
Started Aug 12 04:54:57 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 205104 kb
Host smart-64e29b1f-83b1-4c8b-bd09-9278bf44a51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356187158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.356187158
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1439793150
Short name T83
Test name
Test status
Simulation time 321693806 ps
CPU time 0.96 seconds
Started Aug 12 04:54:52 PM PDT 24
Finished Aug 12 04:54:53 PM PDT 24
Peak memory 205096 kb
Host smart-00f039d6-9114-4533-aa17-a43f950e53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439793150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1439793150
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4193319583
Short name T189
Test name
Test status
Simulation time 1023832388 ps
CPU time 2.48 seconds
Started Aug 12 04:54:52 PM PDT 24
Finished Aug 12 04:54:54 PM PDT 24
Peak memory 205076 kb
Host smart-8821bff6-7747-4362-be04-774b87b3cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193319583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4193319583
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.1867732346
Short name T30
Test name
Test status
Simulation time 387099211 ps
CPU time 0.9 seconds
Started Aug 12 04:55:01 PM PDT 24
Finished Aug 12 04:55:02 PM PDT 24
Peak memory 205116 kb
Host smart-d3fb3348-98db-451f-b7c5-a7ea8142daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867732346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1867732346
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1335153799
Short name T211
Test name
Test status
Simulation time 151654044 ps
CPU time 0.77 seconds
Started Aug 12 04:54:58 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 205084 kb
Host smart-2a91c5f9-6133-41c6-82ad-b86b12824065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335153799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1335153799
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3995354147
Short name T206
Test name
Test status
Simulation time 548919906 ps
CPU time 1.88 seconds
Started Aug 12 04:54:56 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 204936 kb
Host smart-0e571f43-cd61-4f32-86cd-e116161e5c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995354147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3995354147
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3266113467
Short name T54
Test name
Test status
Simulation time 139074284 ps
CPU time 1.06 seconds
Started Aug 12 04:54:59 PM PDT 24
Finished Aug 12 04:55:01 PM PDT 24
Peak memory 205072 kb
Host smart-32e1a5c6-72fb-444e-b787-f2725a64cba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266113467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3266113467
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2375176325
Short name T214
Test name
Test status
Simulation time 323184656 ps
CPU time 1.61 seconds
Started Aug 12 04:54:57 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 205092 kb
Host smart-8fa55952-a815-43d3-961d-3cae97597aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375176325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2375176325
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4223472599
Short name T165
Test name
Test status
Simulation time 100949474 ps
CPU time 0.94 seconds
Started Aug 12 04:54:50 PM PDT 24
Finished Aug 12 04:54:51 PM PDT 24
Peak memory 205104 kb
Host smart-5dcad51b-51e9-4d30-a698-63d2dae87d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223472599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4223472599
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2352469776
Short name T208
Test name
Test status
Simulation time 587194228 ps
CPU time 0.89 seconds
Started Aug 12 04:54:53 PM PDT 24
Finished Aug 12 04:54:54 PM PDT 24
Peak memory 205176 kb
Host smart-9592ef05-7c4e-4b5c-9697-7683d251fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352469776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2352469776
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2214764696
Short name T34
Test name
Test status
Simulation time 685905233 ps
CPU time 1.25 seconds
Started Aug 12 04:54:57 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 213324 kb
Host smart-66fdfca3-2b64-4212-92ee-f1e798119436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214764696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2214764696
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.48500936
Short name T48
Test name
Test status
Simulation time 315702374 ps
CPU time 1.17 seconds
Started Aug 12 04:54:56 PM PDT 24
Finished Aug 12 04:54:58 PM PDT 24
Peak memory 205084 kb
Host smart-90aa80e2-15ce-4e55-8cc2-03a8d18bf33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48500936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.48500936
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2674505973
Short name T95
Test name
Test status
Simulation time 1284235629 ps
CPU time 1.33 seconds
Started Aug 12 04:54:58 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 229820 kb
Host smart-81806f71-a4d6-41c0-848b-4f8f4a280c19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674505973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2674505973
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1292238312
Short name T58
Test name
Test status
Simulation time 1236232424 ps
CPU time 2.43 seconds
Started Aug 12 04:54:55 PM PDT 24
Finished Aug 12 04:54:57 PM PDT 24
Peak memory 205344 kb
Host smart-8592a2a1-86ef-4126-83ec-1d82cf6aefa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292238312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1292238312
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3221159153
Short name T100
Test name
Test status
Simulation time 5612851542 ps
CPU time 8.1 seconds
Started Aug 12 04:54:57 PM PDT 24
Finished Aug 12 04:55:05 PM PDT 24
Peak memory 213628 kb
Host smart-38303c4f-31b3-496f-b77c-cc91ee79d444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221159153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3221159153
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3205658813
Short name T49
Test name
Test status
Simulation time 172559786 ps
CPU time 0.94 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205076 kb
Host smart-58626c9b-499b-42a4-ad4b-8688f6261ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205658813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3205658813
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2952783336
Short name T232
Test name
Test status
Simulation time 60543457 ps
CPU time 0.75 seconds
Started Aug 12 04:55:12 PM PDT 24
Finished Aug 12 04:55:13 PM PDT 24
Peak memory 205140 kb
Host smart-ab3dcacc-b7c4-4929-ac80-02bdae8deed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952783336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2952783336
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_buffered_enable.2229971912
Short name T11
Test name
Test status
Simulation time 383143135 ps
CPU time 1.84 seconds
Started Aug 12 04:55:15 PM PDT 24
Finished Aug 12 04:55:17 PM PDT 24
Peak memory 234392 kb
Host smart-9c2984d4-89da-4f0b-b7f7-4f267589202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229971912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2229971912
Directory /workspace/1.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2161043455
Short name T204
Test name
Test status
Simulation time 674860917 ps
CPU time 2.13 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:07 PM PDT 24
Peak memory 205052 kb
Host smart-00c8b9a9-84f8-40cd-a17f-130482e3d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161043455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2161043455
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3248537551
Short name T18
Test name
Test status
Simulation time 120812207 ps
CPU time 0.96 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:05 PM PDT 24
Peak memory 205052 kb
Host smart-a5821442-29b5-4336-8fc2-5711e8ca9521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248537551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3248537551
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2086165510
Short name T36
Test name
Test status
Simulation time 1558470538 ps
CPU time 1.06 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205132 kb
Host smart-69a3d957-ea2d-4f0b-ab67-f2a1b6126185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086165510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2086165510
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.563970766
Short name T108
Test name
Test status
Simulation time 169692532 ps
CPU time 0.9 seconds
Started Aug 12 04:54:57 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 205084 kb
Host smart-67cd6138-a224-4fe6-8046-965e89a82fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563970766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.563970766
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.137883870
Short name T93
Test name
Test status
Simulation time 154993057 ps
CPU time 0.94 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:05 PM PDT 24
Peak memory 205108 kb
Host smart-c3113557-ba05-42e0-b500-2081b6e4603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137883870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.137883870
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.402502708
Short name T220
Test name
Test status
Simulation time 110881117 ps
CPU time 1.08 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:05 PM PDT 24
Peak memory 215420 kb
Host smart-d264e3eb-c655-4267-afbe-f4f6cf101f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402502708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.402502708
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.251856871
Short name T221
Test name
Test status
Simulation time 255758070 ps
CPU time 0.81 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205172 kb
Host smart-ac1e8aaa-e56b-4c89-9e85-9c212d2651f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251856871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.251856871
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1575722283
Short name T238
Test name
Test status
Simulation time 832230232 ps
CPU time 1 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205084 kb
Host smart-bbe683fd-c191-4bec-8ccc-f4d704fb325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575722283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1575722283
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3130899278
Short name T196
Test name
Test status
Simulation time 538262977 ps
CPU time 1.01 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205084 kb
Host smart-6081bb0c-dbdd-4a27-bb33-5fa510b36b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130899278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3130899278
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3864151537
Short name T201
Test name
Test status
Simulation time 480646315 ps
CPU time 2.23 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:07 PM PDT 24
Peak memory 204956 kb
Host smart-ba455a03-5dec-4023-aede-f67e7cceb4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864151537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3864151537
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1574987674
Short name T215
Test name
Test status
Simulation time 843651090 ps
CPU time 1.81 seconds
Started Aug 12 04:55:04 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205172 kb
Host smart-0f78ff9c-f55e-45f9-8b8f-bb150cb7d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574987674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1574987674
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2053223927
Short name T138
Test name
Test status
Simulation time 589264581 ps
CPU time 1.49 seconds
Started Aug 12 04:54:58 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 205108 kb
Host smart-0dd5c09f-7e02-40c6-93be-f3582deb5029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053223927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2053223927
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3889843
Short name T231
Test name
Test status
Simulation time 179905068 ps
CPU time 0.94 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 205072 kb
Host smart-9cd25a4b-9a3f-4edb-9362-759d8eac4d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3889843
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2189926718
Short name T219
Test name
Test status
Simulation time 310150524 ps
CPU time 1.32 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:06 PM PDT 24
Peak memory 213352 kb
Host smart-cc4c9b17-629d-4ab1-968f-849d80b7522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189926718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2189926718
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.389304073
Short name T38
Test name
Test status
Simulation time 75190432 ps
CPU time 0.87 seconds
Started Aug 12 04:55:03 PM PDT 24
Finished Aug 12 04:55:04 PM PDT 24
Peak memory 213308 kb
Host smart-1a5928f2-c058-4713-baff-bc004a5ef2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389304073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.389304073
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2282135535
Short name T27
Test name
Test status
Simulation time 2362817333 ps
CPU time 2.42 seconds
Started Aug 12 04:55:05 PM PDT 24
Finished Aug 12 04:55:08 PM PDT 24
Peak memory 205432 kb
Host smart-808b0160-e05a-48af-bb2d-d9e757619a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282135535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2282135535
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3705801041
Short name T52
Test name
Test status
Simulation time 627983480 ps
CPU time 2.51 seconds
Started Aug 12 04:55:12 PM PDT 24
Finished Aug 12 04:55:14 PM PDT 24
Peak memory 228760 kb
Host smart-7aeb6430-7519-4b0e-b23c-194eea4f539f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705801041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3705801041
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3383880823
Short name T241
Test name
Test status
Simulation time 914520813 ps
CPU time 1.68 seconds
Started Aug 12 04:54:57 PM PDT 24
Finished Aug 12 04:54:59 PM PDT 24
Peak memory 205352 kb
Host smart-94fef4f8-27ce-4513-9f5c-aadc9878e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383880823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3383880823
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2520852476
Short name T101
Test name
Test status
Simulation time 1621363729 ps
CPU time 4.79 seconds
Started Aug 12 04:55:11 PM PDT 24
Finished Aug 12 04:55:17 PM PDT 24
Peak memory 205308 kb
Host smart-e96210e4-100b-4f06-87ff-92e2f301f36a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520852476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2520852476
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2125044387
Short name T244
Test name
Test status
Simulation time 152936506 ps
CPU time 0.72 seconds
Started Aug 12 04:55:36 PM PDT 24
Finished Aug 12 04:55:36 PM PDT 24
Peak memory 205176 kb
Host smart-1237e7f2-d8d3-49e6-b911-80a0e822bf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125044387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2125044387
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1371435626
Short name T162
Test name
Test status
Simulation time 2102790751 ps
CPU time 4.99 seconds
Started Aug 12 04:55:34 PM PDT 24
Finished Aug 12 04:55:39 PM PDT 24
Peak memory 213512 kb
Host smart-404b216e-7c42-4446-91ab-2a491a69f0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371435626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1371435626
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.4198534070
Short name T181
Test name
Test status
Simulation time 36641753 ps
CPU time 0.75 seconds
Started Aug 12 04:55:33 PM PDT 24
Finished Aug 12 04:55:34 PM PDT 24
Peak memory 205060 kb
Host smart-4508a86f-b661-4315-ba83-e5297e798454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198534070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4198534070
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2193359417
Short name T33
Test name
Test status
Simulation time 47299483 ps
CPU time 0.82 seconds
Started Aug 12 04:55:34 PM PDT 24
Finished Aug 12 04:55:35 PM PDT 24
Peak memory 205112 kb
Host smart-c7f2b120-b927-4a38-8afc-2de6ea8810f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193359417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2193359417
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1350931767
Short name T146
Test name
Test status
Simulation time 2119806298 ps
CPU time 7 seconds
Started Aug 12 04:55:34 PM PDT 24
Finished Aug 12 04:55:41 PM PDT 24
Peak memory 205304 kb
Host smart-c6dc31ec-80b7-43f8-a927-7bc422d1bd18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350931767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1350931767
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3672418579
Short name T207
Test name
Test status
Simulation time 48368889 ps
CPU time 0.78 seconds
Started Aug 12 04:55:36 PM PDT 24
Finished Aug 12 04:55:37 PM PDT 24
Peak memory 205144 kb
Host smart-d0c3f912-77cc-4fd6-96e2-56ce9faed778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672418579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3672418579
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1891932049
Short name T233
Test name
Test status
Simulation time 87493898 ps
CPU time 0.81 seconds
Started Aug 12 04:55:35 PM PDT 24
Finished Aug 12 04:55:36 PM PDT 24
Peak memory 205168 kb
Host smart-906444e6-9886-4e5c-920a-2c03308fae4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891932049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1891932049
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2365868506
Short name T136
Test name
Test status
Simulation time 96605045 ps
CPU time 0.77 seconds
Started Aug 12 04:55:37 PM PDT 24
Finished Aug 12 04:55:38 PM PDT 24
Peak memory 205132 kb
Host smart-ad073639-16bb-49fc-9fff-b773eb7872c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365868506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2365868506
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.529438264
Short name T164
Test name
Test status
Simulation time 4168127440 ps
CPU time 5.29 seconds
Started Aug 12 04:55:32 PM PDT 24
Finished Aug 12 04:55:38 PM PDT 24
Peak memory 213664 kb
Host smart-f525ea9f-2d90-4237-b9b8-4c9bb6f1e0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529438264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.529438264
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.709337284
Short name T182
Test name
Test status
Simulation time 36426671 ps
CPU time 0.77 seconds
Started Aug 12 04:55:40 PM PDT 24
Finished Aug 12 04:55:41 PM PDT 24
Peak memory 205244 kb
Host smart-e21f6670-8e63-4861-bb96-1d46d1e4c28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709337284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.709337284
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2400553816
Short name T154
Test name
Test status
Simulation time 4457331671 ps
CPU time 2.55 seconds
Started Aug 12 04:55:39 PM PDT 24
Finished Aug 12 04:55:42 PM PDT 24
Peak memory 205408 kb
Host smart-ddb573d6-7e3f-42d8-b197-988f3322578d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400553816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2400553816
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1408066702
Short name T137
Test name
Test status
Simulation time 164820103 ps
CPU time 0.7 seconds
Started Aug 12 04:55:44 PM PDT 24
Finished Aug 12 04:55:44 PM PDT 24
Peak memory 205148 kb
Host smart-4ec3ec21-1f11-4887-86b9-13c30da032ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408066702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1408066702
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.343805923
Short name T186
Test name
Test status
Simulation time 256137841 ps
CPU time 0.75 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:55:42 PM PDT 24
Peak memory 205040 kb
Host smart-5e7dbfc1-a406-4f79-bc0d-78ee390bf815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343805923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.343805923
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1716487673
Short name T159
Test name
Test status
Simulation time 3065227131 ps
CPU time 6.26 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:55:48 PM PDT 24
Peak memory 205468 kb
Host smart-0918bf56-7b6e-4b4d-929a-652cff91f4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716487673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1716487673
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1415302659
Short name T200
Test name
Test status
Simulation time 40900071 ps
CPU time 0.73 seconds
Started Aug 12 04:55:40 PM PDT 24
Finished Aug 12 04:55:41 PM PDT 24
Peak memory 205172 kb
Host smart-037c507c-756d-49e3-b7f5-7fa380b9e9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415302659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1415302659
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1925745036
Short name T22
Test name
Test status
Simulation time 2403046421 ps
CPU time 7.88 seconds
Started Aug 12 04:55:46 PM PDT 24
Finished Aug 12 04:55:54 PM PDT 24
Peak memory 205460 kb
Host smart-d31b36e8-f0a7-42f4-bb18-bccd82b13352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925745036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1925745036
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.82443089
Short name T192
Test name
Test status
Simulation time 59178875 ps
CPU time 0.73 seconds
Started Aug 12 04:55:11 PM PDT 24
Finished Aug 12 04:55:12 PM PDT 24
Peak memory 205120 kb
Host smart-da416469-b09f-472b-9907-44e105924106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82443089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.82443089
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_buffered_enable.3148549346
Short name T59
Test name
Test status
Simulation time 317230890 ps
CPU time 1.6 seconds
Started Aug 12 04:55:12 PM PDT 24
Finished Aug 12 04:55:14 PM PDT 24
Peak memory 234688 kb
Host smart-1b8ced94-e416-4ed0-9d47-fbe266e482cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148549346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3148549346
Directory /workspace/2.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.3516585138
Short name T153
Test name
Test status
Simulation time 819883549 ps
CPU time 2.96 seconds
Started Aug 12 04:55:15 PM PDT 24
Finished Aug 12 04:55:18 PM PDT 24
Peak memory 205088 kb
Host smart-375616c3-1e4f-4f3b-94bc-47ba48968754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516585138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.3516585138
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2077202309
Short name T157
Test name
Test status
Simulation time 572511602 ps
CPU time 1.45 seconds
Started Aug 12 04:55:12 PM PDT 24
Finished Aug 12 04:55:14 PM PDT 24
Peak memory 205084 kb
Host smart-dcb5bba4-556a-4bc2-a07f-63bc062f6e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077202309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2077202309
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2666923629
Short name T53
Test name
Test status
Simulation time 1248321078 ps
CPU time 1.9 seconds
Started Aug 12 04:55:11 PM PDT 24
Finished Aug 12 04:55:14 PM PDT 24
Peak memory 229384 kb
Host smart-fae9cd03-acf2-4c32-9deb-0e527549d10e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666923629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2666923629
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.2635571346
Short name T23
Test name
Test status
Simulation time 9577862957 ps
CPU time 42.79 seconds
Started Aug 12 04:55:13 PM PDT 24
Finished Aug 12 04:55:55 PM PDT 24
Peak memory 221880 kb
Host smart-0e48cf6c-8134-44a8-94e8-4096e05e4a66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635571346 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.2635571346
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.951197798
Short name T228
Test name
Test status
Simulation time 63595599 ps
CPU time 0.86 seconds
Started Aug 12 04:55:50 PM PDT 24
Finished Aug 12 04:55:51 PM PDT 24
Peak memory 205164 kb
Host smart-45810461-a7d2-40bd-9201-a9701ed72302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951197798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.951197798
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3306643018
Short name T202
Test name
Test status
Simulation time 1435283342 ps
CPU time 4.15 seconds
Started Aug 12 04:55:40 PM PDT 24
Finished Aug 12 04:55:44 PM PDT 24
Peak memory 213500 kb
Host smart-4b90fd20-cc79-4370-8f30-99947815c2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306643018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3306643018
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2783246579
Short name T247
Test name
Test status
Simulation time 129025468 ps
CPU time 0.89 seconds
Started Aug 12 04:55:40 PM PDT 24
Finished Aug 12 04:55:41 PM PDT 24
Peak memory 205192 kb
Host smart-7255cf80-813f-4067-9457-9550e9267177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783246579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2783246579
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.287813419
Short name T161
Test name
Test status
Simulation time 4672071849 ps
CPU time 7.89 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 205404 kb
Host smart-b8555ec5-4dda-4d35-93ce-3794e1611e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287813419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.287813419
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2530720382
Short name T239
Test name
Test status
Simulation time 52395564 ps
CPU time 0.7 seconds
Started Aug 12 04:55:46 PM PDT 24
Finished Aug 12 04:55:46 PM PDT 24
Peak memory 205132 kb
Host smart-285576be-b47f-4cd2-b018-f81735ed6ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530720382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2530720382
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2167401094
Short name T163
Test name
Test status
Simulation time 5589245464 ps
CPU time 8.31 seconds
Started Aug 12 04:55:39 PM PDT 24
Finished Aug 12 04:55:48 PM PDT 24
Peak memory 205408 kb
Host smart-4052aae9-c52e-404f-a614-8e8190e3fc09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167401094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2167401094
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3635642595
Short name T185
Test name
Test status
Simulation time 99632135 ps
CPU time 0.84 seconds
Started Aug 12 04:55:51 PM PDT 24
Finished Aug 12 04:55:52 PM PDT 24
Peak memory 205156 kb
Host smart-03f50131-6b50-452c-91a9-f44cf6af50c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635642595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3635642595
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.3279248841
Short name T148
Test name
Test status
Simulation time 1828038887 ps
CPU time 5.97 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:55:47 PM PDT 24
Peak memory 205276 kb
Host smart-4ff4657b-1fc5-4885-b546-5584eb3b7b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279248841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3279248841
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2567855183
Short name T190
Test name
Test status
Simulation time 119496549 ps
CPU time 0.8 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:55:42 PM PDT 24
Peak memory 205088 kb
Host smart-2fed1d66-2d6c-492e-8058-6300f174faa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567855183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2567855183
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.274882076
Short name T45
Test name
Test status
Simulation time 6183648692 ps
CPU time 5.64 seconds
Started Aug 12 04:55:40 PM PDT 24
Finished Aug 12 04:55:46 PM PDT 24
Peak memory 213616 kb
Host smart-30c12be5-24b6-4472-8fb1-b7f7819e56e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274882076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.274882076
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2071483337
Short name T213
Test name
Test status
Simulation time 32702132 ps
CPU time 0.74 seconds
Started Aug 12 04:55:51 PM PDT 24
Finished Aug 12 04:55:52 PM PDT 24
Peak memory 205136 kb
Host smart-289b0d3b-c320-4d3f-ba93-5d86ca9b8a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071483337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2071483337
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2970865558
Short name T240
Test name
Test status
Simulation time 12295565004 ps
CPU time 34.8 seconds
Started Aug 12 04:55:41 PM PDT 24
Finished Aug 12 04:56:16 PM PDT 24
Peak memory 205464 kb
Host smart-8629599c-17b2-40ef-a7ef-f8c9d1a96136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970865558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2970865558
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.235445861
Short name T203
Test name
Test status
Simulation time 124482686 ps
CPU time 0.79 seconds
Started Aug 12 04:55:49 PM PDT 24
Finished Aug 12 04:55:50 PM PDT 24
Peak memory 205164 kb
Host smart-8bbfb9c6-7069-42d4-bf28-13e9ac4f33b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235445861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.235445861
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.912213774
Short name T67
Test name
Test status
Simulation time 172957972 ps
CPU time 0.78 seconds
Started Aug 12 04:55:48 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 205104 kb
Host smart-61a211e2-57f5-4f32-8aae-667b62129eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912213774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.912213774
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.318858758
Short name T229
Test name
Test status
Simulation time 1327129247 ps
CPU time 4.24 seconds
Started Aug 12 04:55:49 PM PDT 24
Finished Aug 12 04:55:53 PM PDT 24
Peak memory 205316 kb
Host smart-bc50a293-0377-49c0-8473-ac89ecd3d2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318858758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.318858758
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3087986360
Short name T194
Test name
Test status
Simulation time 59450134 ps
CPU time 0.79 seconds
Started Aug 12 04:55:48 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 205096 kb
Host smart-7d1c0323-60d9-41a4-835d-ad43004d9c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087986360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3087986360
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3322242677
Short name T237
Test name
Test status
Simulation time 1827283197 ps
CPU time 4.09 seconds
Started Aug 12 04:55:50 PM PDT 24
Finished Aug 12 04:55:55 PM PDT 24
Peak memory 213552 kb
Host smart-a66c886c-e0df-464f-81f7-7630b696089f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322242677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3322242677
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1288381703
Short name T209
Test name
Test status
Simulation time 153330610 ps
CPU time 0.8 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:48 PM PDT 24
Peak memory 205132 kb
Host smart-0afbf5e6-4d9d-4479-a3d6-bfc59d75a461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288381703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1288381703
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.177075790
Short name T5
Test name
Test status
Simulation time 8764926087 ps
CPU time 8.59 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 213628 kb
Host smart-ba722d0e-a90a-4360-9653-6b1338e42a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177075790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.177075790
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.881155706
Short name T191
Test name
Test status
Simulation time 42090179 ps
CPU time 0.79 seconds
Started Aug 12 04:55:18 PM PDT 24
Finished Aug 12 04:55:19 PM PDT 24
Peak memory 205120 kb
Host smart-8e16bf53-2c6b-43b0-8f17-63eeb19aab6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881155706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.881155706
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_buffered_enable.4214768151
Short name T62
Test name
Test status
Simulation time 268952495 ps
CPU time 1.45 seconds
Started Aug 12 04:55:21 PM PDT 24
Finished Aug 12 04:55:23 PM PDT 24
Peak memory 226248 kb
Host smart-81078373-9115-4550-9426-ed898148b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214768151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.4214768151
Directory /workspace/3.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.223640391
Short name T210
Test name
Test status
Simulation time 335555010 ps
CPU time 1.12 seconds
Started Aug 12 04:55:12 PM PDT 24
Finished Aug 12 04:55:13 PM PDT 24
Peak memory 205136 kb
Host smart-64b33a86-d24c-43e9-ae7f-35b1cb78450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223640391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.223640391
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.505697620
Short name T145
Test name
Test status
Simulation time 557559286 ps
CPU time 1.58 seconds
Started Aug 12 04:55:11 PM PDT 24
Finished Aug 12 04:55:13 PM PDT 24
Peak memory 205060 kb
Host smart-12e7d4b9-d98b-48df-8f0d-f2907748c88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505697620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.505697620
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2762549639
Short name T94
Test name
Test status
Simulation time 873702001 ps
CPU time 3.15 seconds
Started Aug 12 04:55:20 PM PDT 24
Finished Aug 12 04:55:23 PM PDT 24
Peak memory 229468 kb
Host smart-1003abc4-d678-4fd7-aa35-5ab69c482bd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762549639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2762549639
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1023622175
Short name T187
Test name
Test status
Simulation time 1854593231 ps
CPU time 6.23 seconds
Started Aug 12 04:55:21 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 213600 kb
Host smart-d1672d67-8adf-4977-b6e3-9e5ac59e87a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023622175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1023622175
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3008199863
Short name T44
Test name
Test status
Simulation time 2916391099 ps
CPU time 2.14 seconds
Started Aug 12 04:55:48 PM PDT 24
Finished Aug 12 04:55:50 PM PDT 24
Peak memory 213644 kb
Host smart-16e50a99-8982-4d0f-97df-be2b7fa812e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008199863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3008199863
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3767035578
Short name T223
Test name
Test status
Simulation time 85697868 ps
CPU time 0.91 seconds
Started Aug 12 04:55:48 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 205164 kb
Host smart-c1389feb-55ec-4759-a393-a3b36e3d8f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767035578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3767035578
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2507255532
Short name T225
Test name
Test status
Simulation time 2738385551 ps
CPU time 2.23 seconds
Started Aug 12 04:55:51 PM PDT 24
Finished Aug 12 04:55:53 PM PDT 24
Peak memory 213628 kb
Host smart-8084c348-13f4-4fd8-9520-485fd85990c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507255532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2507255532
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3892336514
Short name T222
Test name
Test status
Simulation time 81870027 ps
CPU time 0.78 seconds
Started Aug 12 04:55:52 PM PDT 24
Finished Aug 12 04:55:53 PM PDT 24
Peak memory 205136 kb
Host smart-34cc129b-442b-443f-a4c6-d9529f5eb899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892336514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3892336514
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.73491888
Short name T155
Test name
Test status
Simulation time 3700906183 ps
CPU time 3.85 seconds
Started Aug 12 04:55:46 PM PDT 24
Finished Aug 12 04:55:50 PM PDT 24
Peak memory 205536 kb
Host smart-d5e41abe-fb21-4320-8a6d-9d277a9ac4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73491888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.73491888
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3858388284
Short name T178
Test name
Test status
Simulation time 150900067 ps
CPU time 0.69 seconds
Started Aug 12 04:55:49 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 205140 kb
Host smart-1d266cd4-1882-455c-99b8-6c316b7ea655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858388284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3858388284
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.55322352
Short name T179
Test name
Test status
Simulation time 114031288 ps
CPU time 0.85 seconds
Started Aug 12 04:55:48 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 205156 kb
Host smart-b50331f2-44cc-4c26-b073-39d9a922d62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55322352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.55322352
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3460069880
Short name T152
Test name
Test status
Simulation time 1365137523 ps
CPU time 1.74 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:49 PM PDT 24
Peak memory 213296 kb
Host smart-f98023be-1198-4358-9bae-893c5b0ebdca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460069880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3460069880
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3088353081
Short name T180
Test name
Test status
Simulation time 50124218 ps
CPU time 0.75 seconds
Started Aug 12 04:55:47 PM PDT 24
Finished Aug 12 04:55:48 PM PDT 24
Peak memory 205128 kb
Host smart-451d1fa3-2db5-4935-8dbe-def5d7c9cd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088353081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3088353081
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1236357403
Short name T99
Test name
Test status
Simulation time 95914719 ps
CPU time 0.76 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205104 kb
Host smart-3b79d6ca-a5b5-4592-9f4e-53ea3f2bd0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236357403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1236357403
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2428141645
Short name T226
Test name
Test status
Simulation time 1075821172 ps
CPU time 1.55 seconds
Started Aug 12 04:55:48 PM PDT 24
Finished Aug 12 04:55:50 PM PDT 24
Peak memory 205320 kb
Host smart-2dba2c3f-c4aa-4c71-9359-b6fd76b40864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428141645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2428141645
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1715467451
Short name T66
Test name
Test status
Simulation time 51670712 ps
CPU time 0.8 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205168 kb
Host smart-14619a06-9706-47ae-8385-381ad9977393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715467451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1715467451
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1552944912
Short name T46
Test name
Test status
Simulation time 10264303342 ps
CPU time 9.53 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:56:06 PM PDT 24
Peak memory 205480 kb
Host smart-7207bd06-c682-4644-9ddf-9a4d663fc939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552944912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1552944912
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1504550437
Short name T193
Test name
Test status
Simulation time 40934751 ps
CPU time 0.75 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205168 kb
Host smart-097f90f7-142a-4cae-a8ea-36bf39cb9850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504550437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1504550437
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2322508155
Short name T216
Test name
Test status
Simulation time 66832541 ps
CPU time 0.84 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:55:57 PM PDT 24
Peak memory 205196 kb
Host smart-98fd448d-e3d1-406b-aeb8-6c9bb3b083fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322508155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2322508155
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1588807692
Short name T102
Test name
Test status
Simulation time 97821695 ps
CPU time 0.77 seconds
Started Aug 12 04:55:20 PM PDT 24
Finished Aug 12 04:55:21 PM PDT 24
Peak memory 205080 kb
Host smart-4428cb5d-bd59-4029-abdb-12ffa878f7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588807692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1588807692
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_buffered_enable.2183319431
Short name T12
Test name
Test status
Simulation time 296044333 ps
CPU time 1 seconds
Started Aug 12 04:55:20 PM PDT 24
Finished Aug 12 04:55:21 PM PDT 24
Peak memory 225996 kb
Host smart-58ae2de6-f754-4b13-aadf-0131c21521ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183319431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2183319431
Directory /workspace/4.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.4197850011
Short name T197
Test name
Test status
Simulation time 188427374 ps
CPU time 1.17 seconds
Started Aug 12 04:55:19 PM PDT 24
Finished Aug 12 04:55:20 PM PDT 24
Peak memory 205040 kb
Host smart-ccb5b26d-6fcb-438c-aaea-382f47d675aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197850011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.4197850011
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3039730317
Short name T184
Test name
Test status
Simulation time 427966898 ps
CPU time 1.01 seconds
Started Aug 12 04:55:21 PM PDT 24
Finished Aug 12 04:55:22 PM PDT 24
Peak memory 205120 kb
Host smart-b60e675a-4190-41a1-be46-d47305a5596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039730317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3039730317
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3945859429
Short name T149
Test name
Test status
Simulation time 976332387 ps
CPU time 2.39 seconds
Started Aug 12 04:55:19 PM PDT 24
Finished Aug 12 04:55:22 PM PDT 24
Peak memory 213532 kb
Host smart-6f2092fa-3d41-4729-b50e-9ed88ef55627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945859429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3945859429
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3186684903
Short name T242
Test name
Test status
Simulation time 94289892 ps
CPU time 0.78 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205248 kb
Host smart-e0704642-7e50-4d5d-ad1f-12673c65cbbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186684903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3186684903
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.240651689
Short name T40
Test name
Test status
Simulation time 2276938834 ps
CPU time 1.93 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:58 PM PDT 24
Peak memory 205464 kb
Host smart-7e26198d-2e2b-47e1-8ecd-7256630a2486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240651689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.240651689
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3263264920
Short name T65
Test name
Test status
Simulation time 30669815 ps
CPU time 0.76 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:55:57 PM PDT 24
Peak memory 205184 kb
Host smart-82c57c6d-2cf2-4255-9d95-1aaa151b3cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263264920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3263264920
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3327717465
Short name T246
Test name
Test status
Simulation time 1842392362 ps
CPU time 2.26 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:55:59 PM PDT 24
Peak memory 205336 kb
Host smart-2cc9c12e-40e3-4efc-8bd7-1ea763c72f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327717465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3327717465
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1459849207
Short name T68
Test name
Test status
Simulation time 45994090 ps
CPU time 0.74 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:55:58 PM PDT 24
Peak memory 205180 kb
Host smart-680876a5-658d-4b76-9214-6ef5ade800df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459849207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1459849207
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1109599333
Short name T8
Test name
Test status
Simulation time 4394889284 ps
CPU time 6.56 seconds
Started Aug 12 04:55:54 PM PDT 24
Finished Aug 12 04:56:01 PM PDT 24
Peak memory 213620 kb
Host smart-7befa93f-84df-4c39-ba1e-5f4fb205a084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109599333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1109599333
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.4040555946
Short name T10
Test name
Test status
Simulation time 3373255937 ps
CPU time 6.44 seconds
Started Aug 12 04:55:54 PM PDT 24
Finished Aug 12 04:56:01 PM PDT 24
Peak memory 205356 kb
Host smart-6f98f05a-0c9b-4d5d-a4e0-b4a2707e1d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040555946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.4040555946
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2013320060
Short name T236
Test name
Test status
Simulation time 48980977 ps
CPU time 0.79 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205120 kb
Host smart-b3f6df25-886e-4ce8-a846-88ee5a7a1707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013320060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2013320060
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1803951367
Short name T158
Test name
Test status
Simulation time 3552892650 ps
CPU time 6.52 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:56:03 PM PDT 24
Peak memory 205396 kb
Host smart-d33f38ae-fa61-4a83-998e-f6b7198938ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803951367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1803951367
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3190741734
Short name T51
Test name
Test status
Simulation time 103933196 ps
CPU time 0.73 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:55:58 PM PDT 24
Peak memory 205104 kb
Host smart-f4ab3905-ed2d-4eb5-b05f-485792cae7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190741734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3190741734
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.426808072
Short name T227
Test name
Test status
Simulation time 2159268174 ps
CPU time 6.86 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:56:03 PM PDT 24
Peak memory 213672 kb
Host smart-c1bf3dd3-f915-465e-a597-7d816772bd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426808072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.426808072
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3386758904
Short name T198
Test name
Test status
Simulation time 127593742 ps
CPU time 0.77 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:55:58 PM PDT 24
Peak memory 205112 kb
Host smart-0b0b0eb8-49f8-4c5e-8467-221d9e593067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386758904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3386758904
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3676577983
Short name T32
Test name
Test status
Simulation time 128132905 ps
CPU time 0.89 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:56 PM PDT 24
Peak memory 205132 kb
Host smart-59fe8add-6bce-4b95-93f7-16a63a3abd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676577983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3676577983
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2404891199
Short name T151
Test name
Test status
Simulation time 4099324018 ps
CPU time 3.13 seconds
Started Aug 12 04:55:55 PM PDT 24
Finished Aug 12 04:55:59 PM PDT 24
Peak memory 205392 kb
Host smart-b5829d12-e187-4ae1-a0ba-fc13701fd9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404891199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2404891199
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1511534629
Short name T218
Test name
Test status
Simulation time 92212082 ps
CPU time 0.89 seconds
Started Aug 12 04:55:54 PM PDT 24
Finished Aug 12 04:55:55 PM PDT 24
Peak memory 205176 kb
Host smart-7f594e55-4fa3-4710-ad15-99ffe9969eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511534629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1511534629
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2445559012
Short name T2
Test name
Test status
Simulation time 4576906064 ps
CPU time 2.97 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:56:00 PM PDT 24
Peak memory 213700 kb
Host smart-a1df7acb-31e0-45f1-b167-58866398a248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445559012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2445559012
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2640481916
Short name T195
Test name
Test status
Simulation time 83317728 ps
CPU time 0.88 seconds
Started Aug 12 04:55:56 PM PDT 24
Finished Aug 12 04:55:57 PM PDT 24
Peak memory 205136 kb
Host smart-afa79344-f4a9-4db6-a85a-06bb6a521035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640481916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2640481916
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.4280986782
Short name T42
Test name
Test status
Simulation time 9806270201 ps
CPU time 28.03 seconds
Started Aug 12 04:55:57 PM PDT 24
Finished Aug 12 04:56:25 PM PDT 24
Peak memory 205384 kb
Host smart-c4fa7642-fa0c-4d38-8680-ae20fc3673fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280986782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.4280986782
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1558155246
Short name T183
Test name
Test status
Simulation time 156077694 ps
CPU time 1.09 seconds
Started Aug 12 04:55:28 PM PDT 24
Finished Aug 12 04:55:29 PM PDT 24
Peak memory 205096 kb
Host smart-164800a8-120e-40df-92e0-21d915618f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558155246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1558155246
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_buffered_enable.1109232567
Short name T245
Test name
Test status
Simulation time 233251366 ps
CPU time 1.45 seconds
Started Aug 12 04:55:21 PM PDT 24
Finished Aug 12 04:55:22 PM PDT 24
Peak memory 226120 kb
Host smart-a11cba21-6496-4409-b723-1d5a81e34aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109232567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.1109232567
Directory /workspace/5.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3347784001
Short name T29
Test name
Test status
Simulation time 1058609462 ps
CPU time 1.45 seconds
Started Aug 12 04:55:20 PM PDT 24
Finished Aug 12 04:55:21 PM PDT 24
Peak memory 205100 kb
Host smart-9b3829ac-a983-4605-ba6f-8dba7fccd6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347784001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3347784001
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3380834619
Short name T234
Test name
Test status
Simulation time 2233265026 ps
CPU time 2.41 seconds
Started Aug 12 04:55:20 PM PDT 24
Finished Aug 12 04:55:23 PM PDT 24
Peak memory 205400 kb
Host smart-3059cb65-2dc0-4bbf-b1c9-2a2d74d7a867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380834619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3380834619
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3491602062
Short name T188
Test name
Test status
Simulation time 44798710 ps
CPU time 0.74 seconds
Started Aug 12 04:55:29 PM PDT 24
Finished Aug 12 04:55:30 PM PDT 24
Peak memory 205160 kb
Host smart-5bd257f5-d63b-4a4f-bcf7-eee5cba04726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491602062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3491602062
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_buffered_enable.2928432070
Short name T63
Test name
Test status
Simulation time 481857154 ps
CPU time 1.2 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 234264 kb
Host smart-7e7fe5cf-adf8-4dbd-9d6f-9791b622d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928432070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.2928432070
Directory /workspace/6.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.2513277147
Short name T243
Test name
Test status
Simulation time 297082285 ps
CPU time 1 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 205124 kb
Host smart-6ee4f731-a34b-4a95-9725-8d3f9e64b83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513277147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2513277147
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3814999974
Short name T230
Test name
Test status
Simulation time 43992063 ps
CPU time 0.75 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 205124 kb
Host smart-9a906452-0bc0-4410-8bff-ffc07932cd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814999974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3814999974
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.2732319750
Short name T160
Test name
Test status
Simulation time 987248157 ps
CPU time 1.39 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:27 PM PDT 24
Peak memory 205020 kb
Host smart-eb5fb044-a5db-46ff-8a02-3f380407ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732319750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2732319750
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1364028207
Short name T24
Test name
Test status
Simulation time 4506376996 ps
CPU time 6.84 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:33 PM PDT 24
Peak memory 213712 kb
Host smart-4d390253-04e2-47cd-a54e-c0f6b7aadc65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364028207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1364028207
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2293737917
Short name T35
Test name
Test status
Simulation time 174839041 ps
CPU time 1.13 seconds
Started Aug 12 04:55:29 PM PDT 24
Finished Aug 12 04:55:30 PM PDT 24
Peak memory 205140 kb
Host smart-df00d36d-5efc-40d1-9ee9-d1ba4cefa9bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293737917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2293737917
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_buffered_enable.3733226387
Short name T25
Test name
Test status
Simulation time 153769810 ps
CPU time 1.01 seconds
Started Aug 12 04:55:25 PM PDT 24
Finished Aug 12 04:55:26 PM PDT 24
Peak memory 226156 kb
Host smart-de5e38d3-bdba-4541-bfe3-c9bdbed26a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733226387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3733226387
Directory /workspace/8.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3596365170
Short name T3
Test name
Test status
Simulation time 4925448686 ps
CPU time 7.18 seconds
Started Aug 12 04:55:29 PM PDT 24
Finished Aug 12 04:55:37 PM PDT 24
Peak memory 213620 kb
Host smart-d9f6555d-4b41-44b1-b35c-36199c88af13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596365170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3596365170
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2885939617
Short name T81
Test name
Test status
Simulation time 112800161 ps
CPU time 0.71 seconds
Started Aug 12 04:55:29 PM PDT 24
Finished Aug 12 04:55:30 PM PDT 24
Peak memory 205188 kb
Host smart-d09cb663-c345-4b5f-b5cc-35aef48854db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885939617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2885939617
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_buffered_enable.1822376125
Short name T64
Test name
Test status
Simulation time 113075052 ps
CPU time 1.02 seconds
Started Aug 12 04:55:27 PM PDT 24
Finished Aug 12 04:55:28 PM PDT 24
Peak memory 225572 kb
Host smart-92b54afb-b6b7-4c25-8583-6883b148166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822376125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.1822376125
Directory /workspace/9.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2894965164
Short name T224
Test name
Test status
Simulation time 2229857214 ps
CPU time 2.86 seconds
Started Aug 12 04:55:26 PM PDT 24
Finished Aug 12 04:55:29 PM PDT 24
Peak memory 205452 kb
Host smart-651c0bf3-4871-42e7-9577-b89b9c34aaff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894965164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2894965164
Directory /workspace/9.rv_dm_stress_all/latest
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