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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.76 96.32 87.27 92.10 91.03 90.44 98.74 58.45


Total test records in report: 482
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T318 /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1363101574 Aug 14 04:33:16 PM PDT 24 Aug 14 04:33:19 PM PDT 24 7601662833 ps
T319 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.4241899367 Aug 14 04:32:53 PM PDT 24 Aug 14 04:32:54 PM PDT 24 368110975 ps
T45 /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2168824664 Aug 14 04:33:25 PM PDT 24 Aug 14 04:34:30 PM PDT 24 4406275776 ps
T320 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1129581113 Aug 14 04:33:10 PM PDT 24 Aug 14 04:33:11 PM PDT 24 238626564 ps
T83 /workspace/coverage/default/0.rv_dm_tap_fsm.1380226215 Aug 14 04:32:40 PM PDT 24 Aug 14 04:32:44 PM PDT 24 4011371580 ps
T60 /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3244363427 Aug 14 04:33:05 PM PDT 24 Aug 14 04:33:06 PM PDT 24 64111105 ps
T321 /workspace/coverage/default/34.rv_dm_alert_test.927325386 Aug 14 04:33:14 PM PDT 24 Aug 14 04:33:15 PM PDT 24 124437305 ps
T322 /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.199014562 Aug 14 04:33:07 PM PDT 24 Aug 14 04:33:10 PM PDT 24 1333993778 ps
T323 /workspace/coverage/default/49.rv_dm_alert_test.4249518929 Aug 14 04:33:39 PM PDT 24 Aug 14 04:33:45 PM PDT 24 63234116 ps
T88 /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1044266334 Aug 14 04:33:12 PM PDT 24 Aug 14 04:34:12 PM PDT 24 3582650546 ps
T324 /workspace/coverage/default/12.rv_dm_stress_all.2092493984 Aug 14 04:33:13 PM PDT 24 Aug 14 04:33:17 PM PDT 24 3980011578 ps
T325 /workspace/coverage/default/44.rv_dm_stress_all.4104440338 Aug 14 04:33:18 PM PDT 24 Aug 14 04:33:36 PM PDT 24 11297612217 ps
T91 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.523073084 Aug 14 04:30:54 PM PDT 24 Aug 14 04:31:31 PM PDT 24 5203391579 ps
T113 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.202004610 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:52 PM PDT 24 215311325 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3725455232 Aug 14 04:30:40 PM PDT 24 Aug 14 04:31:25 PM PDT 24 3527707094 ps
T114 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3861402342 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:08 PM PDT 24 2772797457 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.189689198 Aug 14 04:30:52 PM PDT 24 Aug 14 04:31:20 PM PDT 24 1528314185 ps
T100 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1711161397 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:19 PM PDT 24 862714870 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3379433945 Aug 14 04:30:38 PM PDT 24 Aug 14 04:30:39 PM PDT 24 43924803 ps
T101 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3606311662 Aug 14 04:30:50 PM PDT 24 Aug 14 04:30:58 PM PDT 24 2393600906 ps
T102 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3112633895 Aug 14 04:31:09 PM PDT 24 Aug 14 04:31:11 PM PDT 24 571460237 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.291828966 Aug 14 04:30:29 PM PDT 24 Aug 14 04:34:41 PM PDT 24 90486853219 ps
T156 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2647596819 Aug 14 04:30:50 PM PDT 24 Aug 14 04:30:53 PM PDT 24 1006172610 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3152598539 Aug 14 04:30:41 PM PDT 24 Aug 14 04:30:42 PM PDT 24 49853570 ps
T116 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.4194237974 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 199691878 ps
T117 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.312522322 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:07 PM PDT 24 232313574 ps
T133 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1054739743 Aug 14 04:30:37 PM PDT 24 Aug 14 04:31:08 PM PDT 24 1803157879 ps
T89 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1886871184 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:02 PM PDT 24 245274334 ps
T163 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.142534508 Aug 14 04:30:49 PM PDT 24 Aug 14 04:31:00 PM PDT 24 2617359873 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4240206657 Aug 14 04:30:41 PM PDT 24 Aug 14 04:30:44 PM PDT 24 536295631 ps
T330 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.697329691 Aug 14 04:30:47 PM PDT 24 Aug 14 04:30:50 PM PDT 24 201761947 ps
T331 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3518735824 Aug 14 04:31:09 PM PDT 24 Aug 14 04:31:13 PM PDT 24 1938077848 ps
T90 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3401967261 Aug 14 04:30:36 PM PDT 24 Aug 14 04:31:56 PM PDT 24 8486339087 ps
T332 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3732061898 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:02 PM PDT 24 630821056 ps
T85 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2344598862 Aug 14 04:31:00 PM PDT 24 Aug 14 04:31:02 PM PDT 24 49216327 ps
T119 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3189750710 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:10 PM PDT 24 1931335292 ps
T333 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.267580374 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:57 PM PDT 24 3377279713 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3664604050 Aug 14 04:30:49 PM PDT 24 Aug 14 04:31:15 PM PDT 24 9504741263 ps
T335 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1256446606 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:13 PM PDT 24 2763680012 ps
T336 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.402033178 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:15 PM PDT 24 112429238 ps
T120 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3733171214 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:08 PM PDT 24 825656693 ps
T157 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.979185941 Aug 14 04:30:41 PM PDT 24 Aug 14 04:31:12 PM PDT 24 1953448465 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1585227462 Aug 14 04:30:53 PM PDT 24 Aug 14 04:30:58 PM PDT 24 83323342 ps
T121 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3722776042 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:13 PM PDT 24 791486265 ps
T338 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.131274717 Aug 14 04:30:40 PM PDT 24 Aug 14 04:30:46 PM PDT 24 152084252 ps
T122 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2056845754 Aug 14 04:30:55 PM PDT 24 Aug 14 04:30:57 PM PDT 24 194602040 ps
T124 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.356088608 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:11 PM PDT 24 1156557818 ps
T339 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.31484593 Aug 14 04:30:32 PM PDT 24 Aug 14 04:30:38 PM PDT 24 1811611513 ps
T158 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1313575674 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:29 PM PDT 24 4085409829 ps
T340 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1512143830 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:08 PM PDT 24 187365267 ps
T341 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3305298903 Aug 14 04:30:57 PM PDT 24 Aug 14 04:30:58 PM PDT 24 162939834 ps
T134 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.597387444 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:54 PM PDT 24 427604767 ps
T342 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1032588189 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:14 PM PDT 24 11609684567 ps
T343 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4124241721 Aug 14 04:30:33 PM PDT 24 Aug 14 04:30:35 PM PDT 24 126450809 ps
T344 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1340675775 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:47 PM PDT 24 254033840 ps
T345 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1478321084 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 179036768 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2841752540 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:53 PM PDT 24 168734907 ps
T347 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3796535615 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:05 PM PDT 24 83182372 ps
T147 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3339834462 Aug 14 04:30:34 PM PDT 24 Aug 14 04:30:42 PM PDT 24 476466636 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2027688799 Aug 14 04:31:03 PM PDT 24 Aug 14 04:33:44 PM PDT 24 62668035613 ps
T349 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2563410495 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:54 PM PDT 24 261737376 ps
T164 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1666806768 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:29 PM PDT 24 2688232894 ps
T148 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1646158724 Aug 14 04:30:33 PM PDT 24 Aug 14 04:30:37 PM PDT 24 224581790 ps
T202 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.749500514 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:07 PM PDT 24 1317017611 ps
T135 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3664056794 Aug 14 04:31:09 PM PDT 24 Aug 14 04:31:12 PM PDT 24 117204693 ps
T98 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3751812391 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:15 PM PDT 24 207120617 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.49264388 Aug 14 04:30:37 PM PDT 24 Aug 14 04:30:39 PM PDT 24 90831699 ps
T149 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.195227359 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:08 PM PDT 24 307415270 ps
T351 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1678673531 Aug 14 04:30:40 PM PDT 24 Aug 14 04:30:43 PM PDT 24 116715829 ps
T352 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2761474841 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:47 PM PDT 24 59942035 ps
T353 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1829585276 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:07 PM PDT 24 214661687 ps
T150 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.612099570 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:16 PM PDT 24 1647554689 ps
T354 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3864502743 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:06 PM PDT 24 1560013247 ps
T355 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.956915602 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:44 PM PDT 24 163938128 ps
T197 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.973429498 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:06 PM PDT 24 887698471 ps
T356 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1293010994 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:08 PM PDT 24 649722054 ps
T357 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1612596900 Aug 14 04:30:52 PM PDT 24 Aug 14 04:30:55 PM PDT 24 296704016 ps
T358 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2612837381 Aug 14 04:30:53 PM PDT 24 Aug 14 04:31:04 PM PDT 24 3633155628 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2725920834 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:53 PM PDT 24 1587321189 ps
T93 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2440338959 Aug 14 04:30:52 PM PDT 24 Aug 14 04:30:56 PM PDT 24 176312374 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3834548711 Aug 14 04:30:53 PM PDT 24 Aug 14 04:31:01 PM PDT 24 5073485817 ps
T361 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2669046888 Aug 14 04:30:47 PM PDT 24 Aug 14 04:30:55 PM PDT 24 2064529735 ps
T362 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3014542619 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:47 PM PDT 24 167639841 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3548079363 Aug 14 04:30:31 PM PDT 24 Aug 14 04:30:35 PM PDT 24 351517991 ps
T364 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.909507341 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:04 PM PDT 24 111143998 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3968442762 Aug 14 04:30:43 PM PDT 24 Aug 14 04:31:11 PM PDT 24 10320628453 ps
T366 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3837074461 Aug 14 04:30:52 PM PDT 24 Aug 14 04:30:55 PM PDT 24 174164711 ps
T367 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2864842474 Aug 14 04:31:25 PM PDT 24 Aug 14 04:31:28 PM PDT 24 125528243 ps
T368 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1827156765 Aug 14 04:30:49 PM PDT 24 Aug 14 04:31:42 PM PDT 24 70058669936 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3560009847 Aug 14 04:30:56 PM PDT 24 Aug 14 04:30:58 PM PDT 24 157977391 ps
T370 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1240630146 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:14 PM PDT 24 5256420169 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3347083540 Aug 14 04:30:50 PM PDT 24 Aug 14 04:30:51 PM PDT 24 142299233 ps
T198 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2301160309 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:24 PM PDT 24 3366872964 ps
T372 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.850658010 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:58 PM PDT 24 6846385085 ps
T192 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3553595403 Aug 14 04:30:54 PM PDT 24 Aug 14 04:31:19 PM PDT 24 7647578988 ps
T140 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2610342818 Aug 14 04:30:44 PM PDT 24 Aug 14 04:31:54 PM PDT 24 2463124021 ps
T373 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1913351078 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:04 PM PDT 24 145430352 ps
T125 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3022734960 Aug 14 04:30:47 PM PDT 24 Aug 14 04:30:59 PM PDT 24 4994183068 ps
T86 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4205267469 Aug 14 04:30:53 PM PDT 24 Aug 14 04:30:56 PM PDT 24 334898572 ps
T374 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1000957131 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:47 PM PDT 24 104823951 ps
T375 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1979709139 Aug 14 04:30:41 PM PDT 24 Aug 14 04:30:42 PM PDT 24 239456949 ps
T96 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2866481999 Aug 14 04:30:42 PM PDT 24 Aug 14 04:30:46 PM PDT 24 90500854 ps
T376 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2640860516 Aug 14 04:30:56 PM PDT 24 Aug 14 04:30:58 PM PDT 24 810227107 ps
T377 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1803335070 Aug 14 04:30:45 PM PDT 24 Aug 14 04:30:47 PM PDT 24 2635687772 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3136911849 Aug 14 04:30:37 PM PDT 24 Aug 14 04:32:03 PM PDT 24 61756564035 ps
T379 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3753914612 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:44 PM PDT 24 66050265 ps
T380 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1207575308 Aug 14 04:30:45 PM PDT 24 Aug 14 04:32:33 PM PDT 24 43538198622 ps
T141 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1246120612 Aug 14 04:30:27 PM PDT 24 Aug 14 04:31:32 PM PDT 24 1135087430 ps
T381 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2949781565 Aug 14 04:30:45 PM PDT 24 Aug 14 04:30:50 PM PDT 24 4166844764 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.898728574 Aug 14 04:30:54 PM PDT 24 Aug 14 04:31:06 PM PDT 24 7844910404 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.28374734 Aug 14 04:30:30 PM PDT 24 Aug 14 04:30:32 PM PDT 24 184342025 ps
T194 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2134299786 Aug 14 04:30:39 PM PDT 24 Aug 14 04:30:57 PM PDT 24 16844959005 ps
T384 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2559426921 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:24 PM PDT 24 44081270651 ps
T385 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.947423119 Aug 14 04:30:53 PM PDT 24 Aug 14 04:31:47 PM PDT 24 5713302474 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3305069348 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:04 PM PDT 24 2454278897 ps
T387 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1804066644 Aug 14 04:30:42 PM PDT 24 Aug 14 04:30:54 PM PDT 24 4104853531 ps
T142 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3779932964 Aug 14 04:30:59 PM PDT 24 Aug 14 04:31:06 PM PDT 24 63361716 ps
T388 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.282264627 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:03 PM PDT 24 163466533 ps
T136 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1826033314 Aug 14 04:30:59 PM PDT 24 Aug 14 04:31:07 PM PDT 24 513542662 ps
T143 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.475551068 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:08 PM PDT 24 120789850 ps
T389 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4074394768 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:12 PM PDT 24 6974244906 ps
T144 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3564648438 Aug 14 04:30:46 PM PDT 24 Aug 14 04:31:13 PM PDT 24 1362257691 ps
T199 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.219148773 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:14 PM PDT 24 1403741034 ps
T390 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3691416299 Aug 14 04:30:46 PM PDT 24 Aug 14 04:31:12 PM PDT 24 15454052047 ps
T391 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3237134456 Aug 14 04:30:50 PM PDT 24 Aug 14 04:30:53 PM PDT 24 534414404 ps
T200 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3885709256 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:15 PM PDT 24 2737297664 ps
T94 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1376476768 Aug 14 04:30:44 PM PDT 24 Aug 14 04:31:26 PM PDT 24 11803253798 ps
T392 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.611064669 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:44 PM PDT 24 13030521859 ps
T393 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.684753753 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:23 PM PDT 24 18613110689 ps
T95 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3046176784 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:38 PM PDT 24 4928045420 ps
T394 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1714340927 Aug 14 04:31:00 PM PDT 24 Aug 14 04:31:01 PM PDT 24 265868334 ps
T395 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3506766637 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:06 PM PDT 24 199227732 ps
T396 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.182346898 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:22 PM PDT 24 99247739 ps
T397 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1843973399 Aug 14 04:30:38 PM PDT 24 Aug 14 04:30:56 PM PDT 24 11382003912 ps
T398 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.36080643 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:19 PM PDT 24 947555939 ps
T399 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3387272441 Aug 14 04:30:31 PM PDT 24 Aug 14 04:30:33 PM PDT 24 93371280 ps
T400 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2667217389 Aug 14 04:31:10 PM PDT 24 Aug 14 04:31:14 PM PDT 24 352110677 ps
T401 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4275994918 Aug 14 04:30:52 PM PDT 24 Aug 14 04:31:04 PM PDT 24 3846587728 ps
T145 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1978325909 Aug 14 04:30:45 PM PDT 24 Aug 14 04:32:06 PM PDT 24 23533960087 ps
T193 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1691041381 Aug 14 04:30:48 PM PDT 24 Aug 14 04:31:03 PM PDT 24 2535749157 ps
T402 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.943567452 Aug 14 04:31:09 PM PDT 24 Aug 14 04:31:17 PM PDT 24 1048552426 ps
T403 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4008858017 Aug 14 04:30:56 PM PDT 24 Aug 14 04:31:25 PM PDT 24 35586997172 ps
T146 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.464310812 Aug 14 04:30:32 PM PDT 24 Aug 14 04:30:35 PM PDT 24 534488473 ps
T404 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.251999728 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:07 PM PDT 24 2004172422 ps
T195 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1035797156 Aug 14 04:30:51 PM PDT 24 Aug 14 04:31:01 PM PDT 24 982617487 ps
T405 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1521212938 Aug 14 04:31:04 PM PDT 24 Aug 14 04:31:36 PM PDT 24 13541115121 ps
T406 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1838051942 Aug 14 04:31:04 PM PDT 24 Aug 14 04:31:05 PM PDT 24 120175803 ps
T196 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1589812809 Aug 14 04:31:15 PM PDT 24 Aug 14 04:31:34 PM PDT 24 9826198458 ps
T407 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3058515566 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:35 PM PDT 24 9518660951 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1569761554 Aug 14 04:30:31 PM PDT 24 Aug 14 04:30:31 PM PDT 24 42258168 ps
T409 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3398814243 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:03 PM PDT 24 54242029 ps
T410 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3612875955 Aug 14 04:30:29 PM PDT 24 Aug 14 04:34:36 PM PDT 24 99288087947 ps
T411 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1725360010 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:48 PM PDT 24 1617819399 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.344357405 Aug 14 04:30:50 PM PDT 24 Aug 14 04:31:15 PM PDT 24 3284513535 ps
T87 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4095076228 Aug 14 04:30:30 PM PDT 24 Aug 14 04:30:59 PM PDT 24 1374294588 ps
T413 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3436307819 Aug 14 04:30:47 PM PDT 24 Aug 14 04:30:58 PM PDT 24 2916558535 ps
T414 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1474622670 Aug 14 04:31:08 PM PDT 24 Aug 14 04:31:12 PM PDT 24 1070793338 ps
T137 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3118542553 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:54 PM PDT 24 686744818 ps
T138 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3145237468 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:07 PM PDT 24 132957656 ps
T415 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1989853898 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:30 PM PDT 24 405628046 ps
T416 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2363467757 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:25 PM PDT 24 2417513042 ps
T417 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2444903068 Aug 14 04:30:56 PM PDT 24 Aug 14 04:30:58 PM PDT 24 176954504 ps
T418 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4060015326 Aug 14 04:30:52 PM PDT 24 Aug 14 04:30:56 PM PDT 24 273460063 ps
T419 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2093021893 Aug 14 04:30:59 PM PDT 24 Aug 14 04:31:03 PM PDT 24 1241314037 ps
T420 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2987704831 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:33 PM PDT 24 1326484588 ps
T421 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2036398548 Aug 14 04:30:36 PM PDT 24 Aug 14 04:30:45 PM PDT 24 2139965131 ps
T422 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.171844234 Aug 14 04:30:58 PM PDT 24 Aug 14 04:30:59 PM PDT 24 460954482 ps
T201 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2259513693 Aug 14 04:31:09 PM PDT 24 Aug 14 04:31:31 PM PDT 24 3514992095 ps
T423 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2027991644 Aug 14 04:30:38 PM PDT 24 Aug 14 04:30:42 PM PDT 24 1887613385 ps
T424 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1775828946 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:00 PM PDT 24 48157094 ps
T139 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.31580216 Aug 14 04:30:49 PM PDT 24 Aug 14 04:30:50 PM PDT 24 86683643 ps
T425 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3008227662 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:46 PM PDT 24 5184034745 ps
T426 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.331480174 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:25 PM PDT 24 2113026444 ps
T427 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1261299065 Aug 14 04:30:57 PM PDT 24 Aug 14 04:31:00 PM PDT 24 2645459880 ps
T428 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.168815410 Aug 14 04:30:36 PM PDT 24 Aug 14 04:30:39 PM PDT 24 219776358 ps
T429 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1288070935 Aug 14 04:31:08 PM PDT 24 Aug 14 04:31:09 PM PDT 24 987934271 ps
T430 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.202908997 Aug 14 04:30:39 PM PDT 24 Aug 14 04:30:40 PM PDT 24 78210897 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4280440438 Aug 14 04:30:54 PM PDT 24 Aug 14 04:30:58 PM PDT 24 210435169 ps
T432 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1889850689 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:19 PM PDT 24 2986806795 ps
T433 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3146435126 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:55 PM PDT 24 217681195 ps
T434 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.653788005 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:50 PM PDT 24 53862841 ps
T435 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4144414033 Aug 14 04:30:45 PM PDT 24 Aug 14 04:30:48 PM PDT 24 120360771 ps
T436 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1338932754 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:08 PM PDT 24 485813555 ps
T97 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2390052416 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:10 PM PDT 24 167455622 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.208071287 Aug 14 04:30:48 PM PDT 24 Aug 14 04:31:43 PM PDT 24 2339582317 ps
T437 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1664219148 Aug 14 04:31:00 PM PDT 24 Aug 14 04:31:23 PM PDT 24 5773465972 ps
T438 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2174065934 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:54 PM PDT 24 5736851501 ps
T439 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3458590970 Aug 14 04:30:59 PM PDT 24 Aug 14 04:31:03 PM PDT 24 312075977 ps
T440 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1149956740 Aug 14 04:30:40 PM PDT 24 Aug 14 04:31:45 PM PDT 24 5132445918 ps
T441 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3825007733 Aug 14 04:30:57 PM PDT 24 Aug 14 04:31:08 PM PDT 24 1127798317 ps
T442 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2001080497 Aug 14 04:30:39 PM PDT 24 Aug 14 04:30:58 PM PDT 24 1355454961 ps
T443 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1287494996 Aug 14 04:30:22 PM PDT 24 Aug 14 04:30:23 PM PDT 24 519657301 ps
T444 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4016079092 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:06 PM PDT 24 2600625235 ps
T445 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1773599110 Aug 14 04:30:56 PM PDT 24 Aug 14 04:30:59 PM PDT 24 815904312 ps
T446 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2236401057 Aug 14 04:30:31 PM PDT 24 Aug 14 04:30:32 PM PDT 24 151035056 ps
T447 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2766559151 Aug 14 04:30:50 PM PDT 24 Aug 14 04:31:54 PM PDT 24 24688131128 ps
T448 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1782158338 Aug 14 04:30:47 PM PDT 24 Aug 14 04:32:01 PM PDT 24 57051727300 ps
T449 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.447009419 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:07 PM PDT 24 380452742 ps
T450 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.405860381 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:15 PM PDT 24 422467605 ps
T451 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2449532223 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:52 PM PDT 24 2299477071 ps
T452 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3965722579 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:55 PM PDT 24 3054432969 ps
T453 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1364405448 Aug 14 04:30:50 PM PDT 24 Aug 14 04:32:04 PM PDT 24 3429713241 ps
T454 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3157452087 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:49 PM PDT 24 215060577 ps
T455 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3361473726 Aug 14 04:30:57 PM PDT 24 Aug 14 04:31:06 PM PDT 24 866716042 ps
T456 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3466106212 Aug 14 04:31:00 PM PDT 24 Aug 14 04:31:13 PM PDT 24 24214042247 ps
T457 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2533404003 Aug 14 04:31:11 PM PDT 24 Aug 14 04:31:13 PM PDT 24 621406713 ps
T458 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3685896650 Aug 14 04:30:54 PM PDT 24 Aug 14 04:30:55 PM PDT 24 119257900 ps
T459 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.728578714 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:36 PM PDT 24 32968189 ps
T460 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2577272056 Aug 14 04:30:45 PM PDT 24 Aug 14 04:30:47 PM PDT 24 215121614 ps
T461 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2328940189 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:46 PM PDT 24 56553561 ps
T462 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1659134066 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:45 PM PDT 24 131267539 ps
T463 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2921053585 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 118543428 ps
T464 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.406984952 Aug 14 04:30:32 PM PDT 24 Aug 14 04:30:44 PM PDT 24 4437554459 ps
T465 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3418142497 Aug 14 04:31:00 PM PDT 24 Aug 14 04:31:14 PM PDT 24 6338139653 ps
T466 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2881493551 Aug 14 04:31:11 PM PDT 24 Aug 14 04:31:34 PM PDT 24 15846840836 ps
T92 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1461557118 Aug 14 04:30:53 PM PDT 24 Aug 14 04:30:57 PM PDT 24 89147995 ps
T467 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2073534147 Aug 14 04:30:54 PM PDT 24 Aug 14 04:30:55 PM PDT 24 406433428 ps
T468 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4187935191 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:18 PM PDT 24 105077685 ps
T469 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3690879867 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:07 PM PDT 24 453139629 ps
T470 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1624197006 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:17 PM PDT 24 1205256238 ps
T471 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2130209547 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:47 PM PDT 24 520612157 ps
T472 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.974382531 Aug 14 04:30:53 PM PDT 24 Aug 14 04:30:54 PM PDT 24 496592950 ps
T473 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1153799201 Aug 14 04:30:58 PM PDT 24 Aug 14 04:31:00 PM PDT 24 702164530 ps
T474 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3488261841 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:48 PM PDT 24 1996719175 ps
T475 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1680473194 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:50 PM PDT 24 505997435 ps
T476 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2069615004 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:27 PM PDT 24 418617614 ps
T477 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.613003336 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:12 PM PDT 24 250305181 ps
T478 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3607773469 Aug 14 04:30:57 PM PDT 24 Aug 14 04:31:01 PM PDT 24 748827011 ps
T479 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2353698110 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:08 PM PDT 24 128514505 ps
T480 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2086139269 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:32 PM PDT 24 16277817915 ps
T481 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1350776075 Aug 14 04:31:11 PM PDT 24 Aug 14 04:31:13 PM PDT 24 156209178 ps
T482 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4051352790 Aug 14 04:30:51 PM PDT 24 Aug 14 04:30:52 PM PDT 24 76575666 ps

Test location /workspace/coverage/default/39.rv_dm_stress_all.921841010
Short name T4
Test name
Test status
Simulation time 4720136086 ps
CPU time 12.41 seconds
Started Aug 14 04:33:21 PM PDT 24
Finished Aug 14 04:33:34 PM PDT 24
Peak memory 205160 kb
Host smart-69c9df7d-114d-4cc2-a271-c25b5a57fded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921841010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.921841010
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.2624700486
Short name T17
Test name
Test status
Simulation time 4438634127 ps
CPU time 99.65 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:35:03 PM PDT 24
Peak memory 229824 kb
Host smart-32fff196-32ab-4d18-ad17-65522e9c9a12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624700486 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.2624700486
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3653234830
Short name T1
Test name
Test status
Simulation time 14731829312 ps
CPU time 22.52 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:36 PM PDT 24
Peak memory 213512 kb
Host smart-c5f1dcb4-01bf-4e18-b64a-fb75c9f1fce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653234830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3653234830
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.142534508
Short name T163
Test name
Test status
Simulation time 2617359873 ps
CPU time 10.78 seconds
Started Aug 14 04:30:49 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 221600 kb
Host smart-1276d5f4-b620-4f6d-813e-e280a9f43c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142534508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.142534508
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3401967261
Short name T90
Test name
Test status
Simulation time 8486339087 ps
CPU time 80.18 seconds
Started Aug 14 04:30:36 PM PDT 24
Finished Aug 14 04:31:56 PM PDT 24
Peak memory 218032 kb
Host smart-1ed0582a-441b-417e-a172-dcfee58b6e47
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401967261 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3401967261
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4294228661
Short name T27
Test name
Test status
Simulation time 10248596735 ps
CPU time 28.83 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:45 PM PDT 24
Peak memory 221700 kb
Host smart-0edb4ef7-ea20-432e-bfbd-bf11cd2d6434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294228661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4294228661
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.2747785333
Short name T9
Test name
Test status
Simulation time 2919200676 ps
CPU time 47.98 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 221668 kb
Host smart-a0fcb8b9-5982-4f07-8889-b2ea9265c35b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747785333 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.2747785333
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1380226215
Short name T83
Test name
Test status
Simulation time 4011371580 ps
CPU time 4.5 seconds
Started Aug 14 04:32:40 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 205092 kb
Host smart-495c832f-8858-4aae-8c0d-690896bc1a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380226215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1380226215
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2396257044
Short name T29
Test name
Test status
Simulation time 64461676 ps
CPU time 0.81 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 205044 kb
Host smart-d781ca4d-2256-4079-a860-ade4a975fe1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396257044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2396257044
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.2081279030
Short name T13
Test name
Test status
Simulation time 13812873525 ps
CPU time 54.14 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:34:00 PM PDT 24
Peak memory 221680 kb
Host smart-c47217e4-d07d-48a1-bf0c-c03eaf869d8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081279030 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.2081279030
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_buffered_enable.385517913
Short name T49
Test name
Test status
Simulation time 197246924 ps
CPU time 1.42 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 225900 kb
Host smart-f3be448d-8533-4a1e-8c73-3fa8f44d9b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385517913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.385517913
Directory /workspace/7.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.3789074746
Short name T51
Test name
Test status
Simulation time 285340121 ps
CPU time 1.38 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 204784 kb
Host smart-53c43b79-fe2b-45e4-9134-3fa0ada126a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789074746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3789074746
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2344598862
Short name T85
Test name
Test status
Simulation time 49216327 ps
CPU time 1.97 seconds
Started Aug 14 04:31:00 PM PDT 24
Finished Aug 14 04:31:02 PM PDT 24
Peak memory 221716 kb
Host smart-963a47ba-69eb-4742-81cc-1948f7865300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344598862 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2344598862
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.4194237974
Short name T116
Test name
Test status
Simulation time 199691878 ps
CPU time 1.49 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 213280 kb
Host smart-80be9765-c8fd-40fb-8b0d-29161e43ceca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194237974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4194237974
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4092002377
Short name T80
Test name
Test status
Simulation time 16331475110 ps
CPU time 44.71 seconds
Started Aug 14 04:33:34 PM PDT 24
Finished Aug 14 04:34:18 PM PDT 24
Peak memory 213496 kb
Host smart-89a8b156-5fb3-4ea8-baf8-ad64a8aac7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092002377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.4092002377
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2440338959
Short name T93
Test name
Test status
Simulation time 176312374 ps
CPU time 3.78 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:30:56 PM PDT 24
Peak memory 221600 kb
Host smart-8c3edff2-cf97-4d46-aa17-847d9a62d3e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440338959 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2440338959
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3847345667
Short name T52
Test name
Test status
Simulation time 211134875 ps
CPU time 0.98 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 204848 kb
Host smart-64fada83-1e47-4165-9142-fa488b3ad122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847345667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3847345667
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3009385692
Short name T297
Test name
Test status
Simulation time 5599929998 ps
CPU time 9.55 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 213460 kb
Host smart-be07da55-5488-4b06-b1f8-112c9c66acd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009385692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3009385692
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.3332045174
Short name T19
Test name
Test status
Simulation time 27387547868 ps
CPU time 79.36 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:34:35 PM PDT 24
Peak memory 229812 kb
Host smart-519fb683-2d2c-4eb1-8d0e-948bd9b4ed98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332045174 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.3332045174
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1448572094
Short name T21
Test name
Test status
Simulation time 4248973341 ps
CPU time 6.8 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 205128 kb
Host smart-483268f7-a78c-4d59-8941-2ebf7dae5dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448572094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1448572094
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3384847926
Short name T35
Test name
Test status
Simulation time 745187618 ps
CPU time 1.58 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 229144 kb
Host smart-5f08d256-f4a4-4279-8b2f-015ff9ddaa2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384847926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3384847926
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3663686552
Short name T16
Test name
Test status
Simulation time 801370664 ps
CPU time 2.88 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 204796 kb
Host smart-2b0b2ee5-54bd-483a-90aa-35ac3bb71a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663686552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3663686552
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2134299786
Short name T194
Test name
Test status
Simulation time 16844959005 ps
CPU time 17.95 seconds
Started Aug 14 04:30:39 PM PDT 24
Finished Aug 14 04:30:57 PM PDT 24
Peak memory 213480 kb
Host smart-33f7b234-70f5-4a6e-9881-7958c3cf7466
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134299786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2134299786
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1033408084
Short name T42
Test name
Test status
Simulation time 50707939 ps
CPU time 0.84 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 212968 kb
Host smart-cbc2c38c-55e6-426c-8726-4fc0c084c66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033408084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1033408084
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3885709256
Short name T200
Test name
Test status
Simulation time 2737297664 ps
CPU time 8.85 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 221600 kb
Host smart-85a1947c-ca32-460c-b8f6-46c6ffd28d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885709256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3885709256
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1212300074
Short name T182
Test name
Test status
Simulation time 1880429268 ps
CPU time 5.97 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 205336 kb
Host smart-226b14bd-c9cf-4afe-9ba2-489f1a308707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212300074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1212300074
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2414419360
Short name T184
Test name
Test status
Simulation time 2725540075 ps
CPU time 4.15 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205092 kb
Host smart-575a5f61-16c8-45fe-8679-f15506135093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414419360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2414419360
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.31580216
Short name T139
Test name
Test status
Simulation time 86683643 ps
CPU time 1.31 seconds
Started Aug 14 04:30:49 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 213228 kb
Host smart-8157e9b6-0fee-4f2d-8844-57b2912adff5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31580216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.31580216
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1562784302
Short name T165
Test name
Test status
Simulation time 799736651 ps
CPU time 1.5 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 204980 kb
Host smart-a3c311bd-c925-4113-9510-adab6561639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562784302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1562784302
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3553595403
Short name T192
Test name
Test status
Simulation time 7647578988 ps
CPU time 24.64 seconds
Started Aug 14 04:30:54 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 221636 kb
Host smart-ba713bc5-a6ae-485c-a0a2-83d6337406ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553595403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
553595403
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.639381060
Short name T46
Test name
Test status
Simulation time 4503650860 ps
CPU time 12.75 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 205112 kb
Host smart-d5d3329a-c9fe-4b1a-a25d-6275adc62a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639381060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.639381060
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.17139939
Short name T20
Test name
Test status
Simulation time 677869546 ps
CPU time 2.33 seconds
Started Aug 14 04:33:08 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 205080 kb
Host smart-7ba8de8e-67c4-457a-9519-fb96c2ec5b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.17139939
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3732061898
Short name T332
Test name
Test status
Simulation time 630821056 ps
CPU time 1.2 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:02 PM PDT 24
Peak memory 204840 kb
Host smart-996fc999-656a-43c1-8de5-b146d4a83f93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732061898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3732061898
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3022734960
Short name T125
Test name
Test status
Simulation time 4994183068 ps
CPU time 8.59 seconds
Started Aug 14 04:30:47 PM PDT 24
Finished Aug 14 04:30:59 PM PDT 24
Peak memory 205244 kb
Host smart-9c9ec9f6-5df6-4704-930e-1a52d0f8bbbf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022734960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3022734960
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3733171214
Short name T120
Test name
Test status
Simulation time 825656693 ps
CPU time 4.37 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 205116 kb
Host smart-e6079ddc-d2c7-4dfa-a51c-1cf9a641acf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733171214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3733171214
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1432889101
Short name T37
Test name
Test status
Simulation time 912079823 ps
CPU time 2.06 seconds
Started Aug 14 04:32:47 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 204712 kb
Host smart-68a1f72c-d56d-40b3-adcf-16048c410731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432889101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1432889101
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1035797156
Short name T195
Test name
Test status
Simulation time 982617487 ps
CPU time 10.35 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:31:01 PM PDT 24
Peak memory 213356 kb
Host smart-a5f189ff-06d5-4e7b-ae9d-9ad1a989d45e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035797156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
035797156
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1214506098
Short name T309
Test name
Test status
Simulation time 177782264 ps
CPU time 1.24 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 204804 kb
Host smart-ce957992-9db3-410b-8420-c90bd6a547a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214506098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1214506098
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3244363427
Short name T60
Test name
Test status
Simulation time 64111105 ps
CPU time 0.78 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 213352 kb
Host smart-3f525aa5-dc5e-40a0-bb95-5432b5c2bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244363427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.3244363427
Directory /workspace/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1665119618
Short name T57
Test name
Test status
Simulation time 74965050 ps
CPU time 0.81 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 213272 kb
Host smart-528f3733-7996-4bd9-8871-12a223178bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665119618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1665119618
Directory /workspace/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2610342818
Short name T140
Test name
Test status
Simulation time 2463124021 ps
CPU time 70.13 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 213432 kb
Host smart-4f52c94b-57bf-46bd-95fe-f11e54b9a205
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610342818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2610342818
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.947423119
Short name T385
Test name
Test status
Simulation time 5713302474 ps
CPU time 53.84 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:31:47 PM PDT 24
Peak memory 213420 kb
Host smart-43b9e500-e839-474f-bd1b-7d5c9bee6a13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947423119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.947423119
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4124241721
Short name T343
Test name
Test status
Simulation time 126450809 ps
CPU time 1.66 seconds
Started Aug 14 04:30:33 PM PDT 24
Finished Aug 14 04:30:35 PM PDT 24
Peak memory 213372 kb
Host smart-aa5537a9-3cc7-413a-ad16-6f1555dfb40d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124241721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4124241721
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2866481999
Short name T96
Test name
Test status
Simulation time 90500854 ps
CPU time 3.4 seconds
Started Aug 14 04:30:42 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 221820 kb
Host smart-30d15f22-6039-41c7-b647-6fe3ec2c4830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866481999 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2866481999
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2577272056
Short name T460
Test name
Test status
Simulation time 215121614 ps
CPU time 2.05 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 213316 kb
Host smart-22cd0ca7-cd8e-464e-b331-2b8c60c36255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577272056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2577272056
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2027688799
Short name T348
Test name
Test status
Simulation time 62668035613 ps
CPU time 160.12 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:33:44 PM PDT 24
Peak memory 205180 kb
Host smart-aab3cac8-fd2f-45d6-80a9-e5140cd20caf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027688799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2027688799
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3664604050
Short name T334
Test name
Test status
Simulation time 9504741263 ps
CPU time 26.3 seconds
Started Aug 14 04:30:49 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 205128 kb
Host smart-e730aa0a-1bfc-4e2f-8721-bef8bcbe1324
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664604050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3664604050
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2027991644
Short name T423
Test name
Test status
Simulation time 1887613385 ps
CPU time 3.69 seconds
Started Aug 14 04:30:38 PM PDT 24
Finished Aug 14 04:30:42 PM PDT 24
Peak memory 204988 kb
Host smart-3cb6ab62-bb75-46d3-a395-98c0c9695a10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027991644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
027991644
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1680473194
Short name T475
Test name
Test status
Simulation time 505997435 ps
CPU time 2 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 204896 kb
Host smart-a2ac479b-80c5-4c7a-b9a6-fe50c0f25156
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680473194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1680473194
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3008227662
Short name T425
Test name
Test status
Simulation time 5184034745 ps
CPU time 3.19 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 205144 kb
Host smart-40188119-8339-4ffd-a70b-546ba881173c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008227662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3008227662
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2130209547
Short name T471
Test name
Test status
Simulation time 520612157 ps
CPU time 1.2 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 204848 kb
Host smart-af88cd0a-f448-4343-b268-c9e45174402e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130209547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2130209547
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2069615004
Short name T476
Test name
Test status
Simulation time 418617614 ps
CPU time 0.95 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:27 PM PDT 24
Peak memory 204844 kb
Host smart-008400f3-4a2a-494c-9e08-367bc0465103
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069615004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
069615004
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.728578714
Short name T459
Test name
Test status
Simulation time 32968189 ps
CPU time 0.74 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:36 PM PDT 24
Peak memory 204784 kb
Host smart-6be50735-40e7-442a-b93a-c8c9f932aff7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728578714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.728578714
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3152598539
Short name T329
Test name
Test status
Simulation time 49853570 ps
CPU time 0.68 seconds
Started Aug 14 04:30:41 PM PDT 24
Finished Aug 14 04:30:42 PM PDT 24
Peak memory 204804 kb
Host smart-846b190e-c897-4ab5-b2b8-69ed93b2397a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152598539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3152598539
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2725920834
Short name T359
Test name
Test status
Simulation time 1587321189 ps
CPU time 7.33 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:53 PM PDT 24
Peak memory 205112 kb
Host smart-e7a2bd1e-c078-44ff-83e3-ca3ad5273c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725920834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2725920834
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.208071287
Short name T99
Test name
Test status
Simulation time 2339582317 ps
CPU time 54.81 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:31:43 PM PDT 24
Peak memory 217132 kb
Host smart-b1737254-fa82-44c4-a7a1-2185a9228f92
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208071287 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.208071287
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3548079363
Short name T363
Test name
Test status
Simulation time 351517991 ps
CPU time 3.81 seconds
Started Aug 14 04:30:31 PM PDT 24
Finished Aug 14 04:30:35 PM PDT 24
Peak memory 213424 kb
Host smart-56b9acf5-d4ba-4aa8-ad93-ae2bf5cbc847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548079363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3548079363
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2001080497
Short name T442
Test name
Test status
Simulation time 1355454961 ps
CPU time 18.15 seconds
Started Aug 14 04:30:39 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 221568 kb
Host smart-0ad712d0-a164-4213-a8ac-22818470279b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001080497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2001080497
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1246120612
Short name T141
Test name
Test status
Simulation time 1135087430 ps
CPU time 64.55 seconds
Started Aug 14 04:30:27 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 218260 kb
Host smart-d6855b35-b175-4da0-90c0-8f19ca9c6847
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246120612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1246120612
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.189689198
Short name T115
Test name
Test status
Simulation time 1528314185 ps
CPU time 27.68 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 205432 kb
Host smart-a55200cc-8a0f-4e49-8794-f92cce2927bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189689198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.189689198
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.464310812
Short name T146
Test name
Test status
Simulation time 534488473 ps
CPU time 2.55 seconds
Started Aug 14 04:30:32 PM PDT 24
Finished Aug 14 04:30:35 PM PDT 24
Peak memory 213440 kb
Host smart-bd3a0e30-3965-4769-917e-5640126ed4ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464310812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.464310812
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4280440438
Short name T431
Test name
Test status
Simulation time 210435169 ps
CPU time 4.22 seconds
Started Aug 14 04:30:54 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 213548 kb
Host smart-3c425aa3-3fb0-4cc9-a003-8e1fbdeb696b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280440438 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4280440438
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2444903068
Short name T417
Test name
Test status
Simulation time 176954504 ps
CPU time 1.65 seconds
Started Aug 14 04:30:56 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 218508 kb
Host smart-ac755cf9-61a8-4523-8631-49b814dcc099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444903068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2444903068
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3612875955
Short name T410
Test name
Test status
Simulation time 99288087947 ps
CPU time 246.86 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:34:36 PM PDT 24
Peak memory 205112 kb
Host smart-f53cbaba-35b1-45a3-8df6-b261acf07b4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612875955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3612875955
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3834548711
Short name T360
Test name
Test status
Simulation time 5073485817 ps
CPU time 7.51 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:31:01 PM PDT 24
Peak memory 205132 kb
Host smart-7a18c71e-51fb-4c6b-bd3e-ff85ebc7d953
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834548711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3834548711
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.850658010
Short name T372
Test name
Test status
Simulation time 6846385085 ps
CPU time 10.62 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 205108 kb
Host smart-41d1a13e-8579-46bb-b0f6-4d85773f12d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850658010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.850658010
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2093021893
Short name T419
Test name
Test status
Simulation time 1241314037 ps
CPU time 4.21 seconds
Started Aug 14 04:30:59 PM PDT 24
Finished Aug 14 04:31:03 PM PDT 24
Peak memory 205052 kb
Host smart-2b18517e-0a3f-410b-9f28-c6df57606b0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093021893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
093021893
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1287494996
Short name T443
Test name
Test status
Simulation time 519657301 ps
CPU time 1.07 seconds
Started Aug 14 04:30:22 PM PDT 24
Finished Aug 14 04:30:23 PM PDT 24
Peak memory 204832 kb
Host smart-5bd4349c-34f3-4677-a916-37e35063cb00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287494996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1287494996
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2086139269
Short name T480
Test name
Test status
Simulation time 16277817915 ps
CPU time 19.33 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 205156 kb
Host smart-4cb608a6-6c23-40ad-b460-44b3bf1c19a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086139269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2086139269
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.171844234
Short name T422
Test name
Test status
Simulation time 460954482 ps
CPU time 1.1 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:30:59 PM PDT 24
Peak memory 204832 kb
Host smart-d8a7642a-81d6-4350-a491-6ac7f51e7fd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171844234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.171844234
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3347083540
Short name T371
Test name
Test status
Simulation time 142299233 ps
CPU time 0.9 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:30:51 PM PDT 24
Peak memory 205124 kb
Host smart-52375296-acb3-49c6-a1c5-ff6805891617
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347083540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
347083540
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4051352790
Short name T482
Test name
Test status
Simulation time 76575666 ps
CPU time 0.84 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:52 PM PDT 24
Peak memory 204840 kb
Host smart-6c0507af-7b66-4d49-9911-377185859a2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051352790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.4051352790
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1569761554
Short name T408
Test name
Test status
Simulation time 42258168 ps
CPU time 0.67 seconds
Started Aug 14 04:30:31 PM PDT 24
Finished Aug 14 04:30:31 PM PDT 24
Peak memory 204840 kb
Host smart-06c7095a-938c-4002-8de2-3ffe5be8ba2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569761554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1569761554
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2987704831
Short name T420
Test name
Test status
Simulation time 1326484588 ps
CPU time 7.46 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:33 PM PDT 24
Peak memory 205204 kb
Host smart-7370cde1-bc60-4d11-a90e-16d6577e92e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987704831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2987704831
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3725455232
Short name T326
Test name
Test status
Simulation time 3527707094 ps
CPU time 40.37 seconds
Started Aug 14 04:30:40 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 217336 kb
Host smart-5bb8eae3-44f3-4222-af48-9f3281784eae
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725455232 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3725455232
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3157452087
Short name T454
Test name
Test status
Simulation time 215060577 ps
CPU time 5.08 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:49 PM PDT 24
Peak memory 213448 kb
Host smart-7e689849-9986-4652-b340-91ed17604880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157452087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3157452087
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2036398548
Short name T421
Test name
Test status
Simulation time 2139965131 ps
CPU time 9.1 seconds
Started Aug 14 04:30:36 PM PDT 24
Finished Aug 14 04:30:45 PM PDT 24
Peak memory 214876 kb
Host smart-23b61b6d-0422-4ace-b5ed-45a035a9046f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036398548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2036398548
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3398814243
Short name T409
Test name
Test status
Simulation time 54242029 ps
CPU time 1.87 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:03 PM PDT 24
Peak memory 213520 kb
Host smart-ee69f33b-a552-4d45-bc2e-95f7aad30af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398814243 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3398814243
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.182346898
Short name T396
Test name
Test status
Simulation time 99247739 ps
CPU time 1.65 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 218792 kb
Host smart-a3d1eba3-575b-4ab5-b1a4-472cf255a718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182346898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.182346898
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1032588189
Short name T342
Test name
Test status
Simulation time 11609684567 ps
CPU time 12.72 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 205120 kb
Host smart-8e390aa1-8ccd-451d-ae61-c63bac1a872d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032588189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1032588189
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2449532223
Short name T451
Test name
Test status
Simulation time 2299477071 ps
CPU time 7.58 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:52 PM PDT 24
Peak memory 205088 kb
Host smart-e99fedc0-1312-47b0-93d8-b8293e5be302
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449532223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2449532223
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.447009419
Short name T449
Test name
Test status
Simulation time 380452742 ps
CPU time 4.59 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 213376 kb
Host smart-3fbb0c78-2200-4435-8575-58e7ea3aefb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447009419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.447009419
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2056845754
Short name T122
Test name
Test status
Simulation time 194602040 ps
CPU time 1.48 seconds
Started Aug 14 04:30:55 PM PDT 24
Finished Aug 14 04:30:57 PM PDT 24
Peak memory 213280 kb
Host smart-a634316d-6603-449f-a3db-19dabdc58f17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056845754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2056845754
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2559426921
Short name T384
Test name
Test status
Simulation time 44081270651 ps
CPU time 21.72 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 205076 kb
Host smart-5cfcddc7-5389-4938-81bf-74a5f778b056
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559426921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2559426921
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4016079092
Short name T444
Test name
Test status
Simulation time 2600625235 ps
CPU time 3.41 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 205132 kb
Host smart-c6f47867-dae4-49c0-8d7c-ebc9217ab7e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016079092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4016079092
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1838051942
Short name T406
Test name
Test status
Simulation time 120175803 ps
CPU time 0.96 seconds
Started Aug 14 04:31:04 PM PDT 24
Finished Aug 14 04:31:05 PM PDT 24
Peak memory 204816 kb
Host smart-5a085313-a7fc-49cf-8bd1-bd8857f8bd72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838051942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1838051942
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3664056794
Short name T135
Test name
Test status
Simulation time 117204693 ps
CPU time 3.63 seconds
Started Aug 14 04:31:09 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 205096 kb
Host smart-79131d67-d396-432c-ba2d-f8e7830d9ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664056794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3664056794
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.653788005
Short name T434
Test name
Test status
Simulation time 53862841 ps
CPU time 2.66 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 213484 kb
Host smart-f6192e24-960a-43b8-90a9-44bbb830b37c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653788005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.653788005
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1313575674
Short name T158
Test name
Test status
Simulation time 4085409829 ps
CPU time 20.9 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:29 PM PDT 24
Peak memory 213508 kb
Host smart-766a78e8-78c8-4714-8a1a-a89e1972ebad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313575674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
313575674
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1829585276
Short name T353
Test name
Test status
Simulation time 214661687 ps
CPU time 3.62 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 218536 kb
Host smart-d1054dbc-22ab-4d17-80e5-18f9a03c8ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829585276 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1829585276
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1775828946
Short name T424
Test name
Test status
Simulation time 48157094 ps
CPU time 1.5 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 218740 kb
Host smart-7f839c47-8685-4b47-8d0e-570bac8d5b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775828946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1775828946
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.684753753
Short name T393
Test name
Test status
Simulation time 18613110689 ps
CPU time 24.9 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 205144 kb
Host smart-d668ec0c-983c-4d24-8af0-3b6ecf300a63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684753753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.684753753
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1256446606
Short name T335
Test name
Test status
Simulation time 2763680012 ps
CPU time 5.45 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 205124 kb
Host smart-6b6cab97-b735-4b33-8a41-10058ed89453
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256446606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1256446606
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.282264627
Short name T388
Test name
Test status
Simulation time 163466533 ps
CPU time 0.84 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:03 PM PDT 24
Peak memory 204868 kb
Host smart-7900c45d-f103-45bc-b55f-32da53271444
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282264627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.282264627
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.943567452
Short name T402
Test name
Test status
Simulation time 1048552426 ps
CPU time 7.7 seconds
Started Aug 14 04:31:09 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 205184 kb
Host smart-1a27645b-8d09-4a59-9ea8-5be80da8b5e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943567452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.943567452
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3690879867
Short name T469
Test name
Test status
Simulation time 453139629 ps
CPU time 4.87 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 213504 kb
Host smart-3a323ae8-5d10-441a-878d-431fd3025c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690879867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3690879867
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.312522322
Short name T117
Test name
Test status
Simulation time 232313574 ps
CPU time 1.74 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 218748 kb
Host smart-8475e1e1-67c6-40f0-89c1-eaa8ce5ca8ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312522322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.312522322
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.402033178
Short name T336
Test name
Test status
Simulation time 112429238 ps
CPU time 0.76 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 204904 kb
Host smart-cc21e055-62b8-4da4-99a1-bc159330557e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402033178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.402033178
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.251999728
Short name T404
Test name
Test status
Simulation time 2004172422 ps
CPU time 3.15 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 205048 kb
Host smart-06df190d-e65e-49c4-a887-0fe5979b0d99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251999728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.251999728
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1293010994
Short name T356
Test name
Test status
Simulation time 649722054 ps
CPU time 2.54 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 204840 kb
Host smart-db75413f-e234-4d62-8a71-4053e8946bdf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293010994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1293010994
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.195227359
Short name T149
Test name
Test status
Simulation time 307415270 ps
CPU time 4.49 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 205176 kb
Host smart-276849c8-0d9b-4402-b53d-c02b584bc6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195227359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.195227359
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2667217389
Short name T400
Test name
Test status
Simulation time 352110677 ps
CPU time 3.7 seconds
Started Aug 14 04:31:10 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 213496 kb
Host smart-9739d436-2551-4c22-8bff-a121cd7df5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667217389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2667217389
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.749500514
Short name T202
Test name
Test status
Simulation time 1317017611 ps
CPU time 8.97 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 213432 kb
Host smart-b4e6ac6d-9367-417c-8cd6-30f9abda3ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749500514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.749500514
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3751812391
Short name T98
Test name
Test status
Simulation time 207120617 ps
CPU time 2.68 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 216520 kb
Host smart-011d1ae7-1550-44dc-9939-1292c7c0f596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751812391 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3751812391
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1153799201
Short name T473
Test name
Test status
Simulation time 702164530 ps
CPU time 2.35 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 219252 kb
Host smart-a50f1ea9-aa06-4312-b812-aaa49f359db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153799201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1153799201
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1782158338
Short name T448
Test name
Test status
Simulation time 57051727300 ps
CPU time 74.18 seconds
Started Aug 14 04:30:47 PM PDT 24
Finished Aug 14 04:32:01 PM PDT 24
Peak memory 205120 kb
Host smart-b5beb333-c4b0-498e-a48a-5ef42c9f6d9a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782158338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1782158338
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3418142497
Short name T465
Test name
Test status
Simulation time 6338139653 ps
CPU time 8.91 seconds
Started Aug 14 04:31:00 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 205132 kb
Host smart-8c3cbbc5-ff6f-449a-bace-326ba01c20da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418142497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3418142497
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1338932754
Short name T436
Test name
Test status
Simulation time 485813555 ps
CPU time 2.02 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 204840 kb
Host smart-46ade00f-cf3c-4067-83a7-00d9f40c23d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338932754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1338932754
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2363467757
Short name T416
Test name
Test status
Simulation time 2417513042 ps
CPU time 7.85 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 205232 kb
Host smart-20612527-a4df-4056-8594-0ddd72a3e3f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363467757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2363467757
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3237134456
Short name T391
Test name
Test status
Simulation time 534414404 ps
CPU time 3.43 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:30:53 PM PDT 24
Peak memory 213460 kb
Host smart-05fe4eee-b09a-4ae7-adb2-8cd77504af77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237134456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3237134456
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1624197006
Short name T470
Test name
Test status
Simulation time 1205256238 ps
CPU time 11.72 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 221564 kb
Host smart-8e8658cb-3a66-4df0-9862-df1cb25d78f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624197006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
624197006
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4187935191
Short name T468
Test name
Test status
Simulation time 105077685 ps
CPU time 3.97 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:18 PM PDT 24
Peak memory 219576 kb
Host smart-7540c5ab-4189-45e2-8b93-e9ecd10b7fc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187935191 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.4187935191
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3506766637
Short name T395
Test name
Test status
Simulation time 199227732 ps
CPU time 2.43 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 213280 kb
Host smart-1325a848-071c-415a-bf99-969b1551eef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506766637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3506766637
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2881493551
Short name T466
Test name
Test status
Simulation time 15846840836 ps
CPU time 23.42 seconds
Started Aug 14 04:31:11 PM PDT 24
Finished Aug 14 04:31:34 PM PDT 24
Peak memory 205172 kb
Host smart-420f04bc-a472-49cb-9d18-1baf33d87094
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881493551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2881493551
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2612837381
Short name T358
Test name
Test status
Simulation time 3633155628 ps
CPU time 10.29 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:31:04 PM PDT 24
Peak memory 205156 kb
Host smart-77b0b1da-cae1-4096-b6df-0e54a0f3d722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612837381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2612837381
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1711161397
Short name T100
Test name
Test status
Simulation time 862714870 ps
CPU time 1.81 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 204800 kb
Host smart-427c1b28-0b60-4893-b84e-f9d7a4197f2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711161397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1711161397
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3864502743
Short name T354
Test name
Test status
Simulation time 1560013247 ps
CPU time 4.09 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 205092 kb
Host smart-6af4aad7-8acf-4f26-b226-8dc39e70e328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864502743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3864502743
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.697329691
Short name T330
Test name
Test status
Simulation time 201761947 ps
CPU time 2.86 seconds
Started Aug 14 04:30:47 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 213444 kb
Host smart-099e2631-692f-4551-acb2-8379a02332ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697329691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.697329691
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1913351078
Short name T373
Test name
Test status
Simulation time 145430352 ps
CPU time 1.93 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:04 PM PDT 24
Peak memory 216760 kb
Host smart-6e0b1e89-72b0-43ef-a55e-b2dec62b6693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913351078 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1913351078
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1350776075
Short name T481
Test name
Test status
Simulation time 156209178 ps
CPU time 2.04 seconds
Started Aug 14 04:31:11 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 213316 kb
Host smart-82a1e481-c5f0-4a22-bd85-a9de83a1ce36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350776075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1350776075
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.611064669
Short name T392
Test name
Test status
Simulation time 13030521859 ps
CPU time 38.13 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:44 PM PDT 24
Peak memory 205180 kb
Host smart-a20f8e01-ad50-4e78-9489-63325fd15dfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611064669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.611064669
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3305069348
Short name T386
Test name
Test status
Simulation time 2454278897 ps
CPU time 2.39 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:04 PM PDT 24
Peak memory 205108 kb
Host smart-24e8869f-0e40-4316-afba-e1b5d25f5c3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305069348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3305069348
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3112633895
Short name T102
Test name
Test status
Simulation time 571460237 ps
CPU time 1.15 seconds
Started Aug 14 04:31:09 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 204840 kb
Host smart-8804b392-25ab-4941-acf8-aef642728dc0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112633895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3112633895
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3189750710
Short name T119
Test name
Test status
Simulation time 1931335292 ps
CPU time 7.19 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:10 PM PDT 24
Peak memory 205208 kb
Host smart-18e13319-f977-4ce6-b776-a254f74d9532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189750710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3189750710
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3796535615
Short name T347
Test name
Test status
Simulation time 83182372 ps
CPU time 2.73 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:05 PM PDT 24
Peak memory 213428 kb
Host smart-0195a3d6-d19c-4ab4-acc6-94eeca57b002
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796535615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3796535615
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.219148773
Short name T199
Test name
Test status
Simulation time 1403741034 ps
CPU time 11.28 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 221488 kb
Host smart-0feae696-2dd1-46c1-a5d0-66d54413748d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219148773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.219148773
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2563410495
Short name T349
Test name
Test status
Simulation time 261737376 ps
CPU time 2.86 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 219464 kb
Host smart-6210f6a4-f0e9-4bae-8dbe-5ad4d077ccdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563410495 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2563410495
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2921053585
Short name T463
Test name
Test status
Simulation time 118543428 ps
CPU time 1.49 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 218320 kb
Host smart-021c2120-479e-42de-8d4a-4313e59e1c15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921053585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2921053585
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4275994918
Short name T401
Test name
Test status
Simulation time 3846587728 ps
CPU time 11.2 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:31:04 PM PDT 24
Peak memory 205108 kb
Host smart-19675503-0087-4a95-a5a9-1935f26a86d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275994918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.4275994918
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1889850689
Short name T432
Test name
Test status
Simulation time 2986806795 ps
CPU time 5.14 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 205120 kb
Host smart-c8d3870c-91d5-4730-9366-e0d3fd6f081b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889850689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1889850689
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.974382531
Short name T472
Test name
Test status
Simulation time 496592950 ps
CPU time 0.92 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 204844 kb
Host smart-57b3bae7-f1e8-4526-b801-6bb4892b5776
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974382531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.974382531
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3722776042
Short name T121
Test name
Test status
Simulation time 791486265 ps
CPU time 7.7 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 205176 kb
Host smart-789d7e26-d324-43dc-a890-2a67755c4ca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722776042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3722776042
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1612596900
Short name T357
Test name
Test status
Simulation time 296704016 ps
CPU time 3.17 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 213460 kb
Host smart-fa2bac4b-6442-487d-961f-5aaec2af27c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612596900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1612596900
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1589812809
Short name T196
Test name
Test status
Simulation time 9826198458 ps
CPU time 18.45 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:34 PM PDT 24
Peak memory 213492 kb
Host smart-c7ae97f6-514e-4c18-9e7f-0b4b586f1505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589812809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
589812809
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1512143830
Short name T340
Test name
Test status
Simulation time 187365267 ps
CPU time 1.95 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 213512 kb
Host smart-4e28b1a7-7d24-4eed-a3c2-2817acbd8f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512143830 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1512143830
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.405860381
Short name T450
Test name
Test status
Simulation time 422467605 ps
CPU time 2.25 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 213416 kb
Host smart-efa8e7d8-a3a1-4233-b623-576410505e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405860381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.405860381
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3518735824
Short name T331
Test name
Test status
Simulation time 1938077848 ps
CPU time 3.6 seconds
Started Aug 14 04:31:09 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 205136 kb
Host smart-8e222397-c5ce-48e6-889f-64c4588ef562
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518735824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3518735824
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.331480174
Short name T426
Test name
Test status
Simulation time 2113026444 ps
CPU time 4.33 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 204988 kb
Host smart-f10b7d88-8ef7-4ccb-8412-f1e50b5fa6a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331480174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.331480174
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1288070935
Short name T429
Test name
Test status
Simulation time 987934271 ps
CPU time 1.3 seconds
Started Aug 14 04:31:08 PM PDT 24
Finished Aug 14 04:31:09 PM PDT 24
Peak memory 204852 kb
Host smart-31a519cd-c529-44da-8190-b53641c867ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288070935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1288070935
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3458590970
Short name T439
Test name
Test status
Simulation time 312075977 ps
CPU time 4.82 seconds
Started Aug 14 04:30:59 PM PDT 24
Finished Aug 14 04:31:03 PM PDT 24
Peak memory 205164 kb
Host smart-28cd6b11-4192-46ed-a486-743de5f35347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458590970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3458590970
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2864842474
Short name T367
Test name
Test status
Simulation time 125528243 ps
CPU time 2.61 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:28 PM PDT 24
Peak memory 213460 kb
Host smart-b65b3dd9-e56b-4b06-adc0-c8876773e7e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864842474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2864842474
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2259513693
Short name T201
Test name
Test status
Simulation time 3514992095 ps
CPU time 21.51 seconds
Started Aug 14 04:31:09 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 221628 kb
Host smart-5dfebf1b-35a8-43fb-b566-5099ab729881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259513693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
259513693
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1886871184
Short name T89
Test name
Test status
Simulation time 245274334 ps
CPU time 3.22 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:02 PM PDT 24
Peak memory 213456 kb
Host smart-0d18637c-5149-4161-837e-cf86b21c8b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886871184 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1886871184
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3058515566
Short name T407
Test name
Test status
Simulation time 9518660951 ps
CPU time 22.61 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:35 PM PDT 24
Peak memory 205116 kb
Host smart-a70b2d47-4bf0-455f-8f56-d46bc8b75791
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058515566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3058515566
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1261299065
Short name T427
Test name
Test status
Simulation time 2645459880 ps
CPU time 2.83 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 205100 kb
Host smart-7fc7c592-7759-4b68-8b71-d7f54aeb6d4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261299065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1261299065
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1478321084
Short name T345
Test name
Test status
Simulation time 179036768 ps
CPU time 0.79 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 204852 kb
Host smart-21ec334a-fe81-4fe2-95a1-c7aa19b81bd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478321084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1478321084
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.612099570
Short name T150
Test name
Test status
Simulation time 1647554689 ps
CPU time 4.32 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:16 PM PDT 24
Peak memory 205076 kb
Host smart-ae27bd30-1f2a-40be-9669-4c648373254e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612099570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.612099570
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.36080643
Short name T398
Test name
Test status
Simulation time 947555939 ps
CPU time 5.58 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 213416 kb
Host smart-bece7ceb-cc59-4bbb-b26a-2b1c20529e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.36080643
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3825007733
Short name T441
Test name
Test status
Simulation time 1127798317 ps
CPU time 10.8 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 221472 kb
Host smart-5a966607-25d7-4f94-837e-ddb4e5b371d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825007733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
825007733
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3564648438
Short name T144
Test name
Test status
Simulation time 1362257691 ps
CPU time 27.17 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 205184 kb
Host smart-c456e51c-3369-43e2-a69d-5a66b1d0f4ab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564648438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3564648438
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1149956740
Short name T440
Test name
Test status
Simulation time 5132445918 ps
CPU time 64.96 seconds
Started Aug 14 04:30:40 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 205176 kb
Host smart-96141b57-992c-4c06-bf94-ad98ea1c3e75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149956740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1149956740
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2328940189
Short name T461
Test name
Test status
Simulation time 56553561 ps
CPU time 1.51 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 213340 kb
Host smart-58056067-631d-40ed-aefc-41505a38b171
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328940189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2328940189
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4144414033
Short name T435
Test name
Test status
Simulation time 120360771 ps
CPU time 3.04 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:30:48 PM PDT 24
Peak memory 219084 kb
Host smart-2e996844-e9e5-411b-85c6-8a3b40d3760f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144414033 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4144414033
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3779932964
Short name T142
Test name
Test status
Simulation time 63361716 ps
CPU time 1.69 seconds
Started Aug 14 04:30:59 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 218864 kb
Host smart-fddcea84-2bec-44df-b6ff-b21f752eeb16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779932964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3779932964
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.291828966
Short name T328
Test name
Test status
Simulation time 90486853219 ps
CPU time 251.66 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:34:41 PM PDT 24
Peak memory 205108 kb
Host smart-fe771177-e342-4383-a42c-5ffe8031ec91
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291828966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.291828966
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3753914612
Short name T379
Test name
Test status
Simulation time 66050265 ps
CPU time 0.71 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:44 PM PDT 24
Peak memory 204832 kb
Host smart-2d7c6ec4-bc99-412c-b4f2-0dacf178232a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753914612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3753914612
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3968442762
Short name T365
Test name
Test status
Simulation time 10320628453 ps
CPU time 27.79 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 205016 kb
Host smart-0c0e4900-6c7b-4016-b8b1-6d72f9c69001
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968442762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3968442762
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1843973399
Short name T397
Test name
Test status
Simulation time 11382003912 ps
CPU time 12.22 seconds
Started Aug 14 04:30:38 PM PDT 24
Finished Aug 14 04:30:56 PM PDT 24
Peak memory 205108 kb
Host smart-9268fad4-b687-472d-bd65-7489b28c8167
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843973399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
843973399
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.31484593
Short name T339
Test name
Test status
Simulation time 1811611513 ps
CPU time 5.21 seconds
Started Aug 14 04:30:32 PM PDT 24
Finished Aug 14 04:30:38 PM PDT 24
Peak memory 204840 kb
Host smart-707d1f88-9ef6-427c-a96e-3ff26c219dbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31484593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
aliasing.31484593
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1804066644
Short name T387
Test name
Test status
Simulation time 4104853531 ps
CPU time 12.36 seconds
Started Aug 14 04:30:42 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 205148 kb
Host smart-84f64138-b25b-45ec-857b-601cab096212
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804066644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1804066644
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.956915602
Short name T355
Test name
Test status
Simulation time 163938128 ps
CPU time 0.75 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:44 PM PDT 24
Peak memory 204832 kb
Host smart-9b87068e-606a-4821-afe8-6e5dc9d7369b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956915602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.956915602
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2533404003
Short name T457
Test name
Test status
Simulation time 621406713 ps
CPU time 2.36 seconds
Started Aug 14 04:31:11 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 204860 kb
Host smart-b3a8caa8-de91-4a79-ab88-7526dfce9be1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533404003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
533404003
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.131274717
Short name T338
Test name
Test status
Simulation time 152084252 ps
CPU time 0.76 seconds
Started Aug 14 04:30:40 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 204872 kb
Host smart-101a8537-da60-4a0e-8b6d-35b4bca11b86
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131274717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.131274717
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2761474841
Short name T352
Test name
Test status
Simulation time 59942035 ps
CPU time 0.71 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 204868 kb
Host smart-c495b9c1-c48d-4f2f-852f-267f7ad3dfaa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761474841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2761474841
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1646158724
Short name T148
Test name
Test status
Simulation time 224581790 ps
CPU time 3.42 seconds
Started Aug 14 04:30:33 PM PDT 24
Finished Aug 14 04:30:37 PM PDT 24
Peak memory 205136 kb
Host smart-34075930-bbde-41e8-8489-c16eb20cf14d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646158724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1646158724
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.613003336
Short name T477
Test name
Test status
Simulation time 250305181 ps
CPU time 4.85 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 213480 kb
Host smart-4bd76b96-ce24-4dbf-9f80-643f3479cffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613003336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.613003336
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1666806768
Short name T164
Test name
Test status
Simulation time 2688232894 ps
CPU time 21.53 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:29 PM PDT 24
Peak memory 213488 kb
Host smart-cf6bc3fe-b3dc-4a6d-ae7c-f35a4bd9af1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666806768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1666806768
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1054739743
Short name T133
Test name
Test status
Simulation time 1803157879 ps
CPU time 30.54 seconds
Started Aug 14 04:30:37 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 205200 kb
Host smart-0e7daeaa-28dd-4aa5-a688-aeb23ab87d04
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054739743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1054739743
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1978325909
Short name T145
Test name
Test status
Simulation time 23533960087 ps
CPU time 80.63 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:32:06 PM PDT 24
Peak memory 213608 kb
Host smart-3920d024-3b1b-4e36-a21a-961a30d135c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978325909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1978325909
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4240206657
Short name T118
Test name
Test status
Simulation time 536295631 ps
CPU time 2.52 seconds
Started Aug 14 04:30:41 PM PDT 24
Finished Aug 14 04:30:44 PM PDT 24
Peak memory 213364 kb
Host smart-a29583b3-e8bf-4cef-8636-58e1444ab71d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240206657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.4240206657
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1461557118
Short name T92
Test name
Test status
Simulation time 89147995 ps
CPU time 3.94 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:30:57 PM PDT 24
Peak memory 220080 kb
Host smart-92b3524a-b283-42c0-be0c-3bfce4d26105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461557118 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1461557118
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.49264388
Short name T350
Test name
Test status
Simulation time 90831699 ps
CPU time 1.62 seconds
Started Aug 14 04:30:37 PM PDT 24
Finished Aug 14 04:30:39 PM PDT 24
Peak memory 213368 kb
Host smart-222e6429-b3cd-4cf7-b4ad-462d9d3ed816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49264388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.49264388
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1827156765
Short name T368
Test name
Test status
Simulation time 70058669936 ps
CPU time 52.7 seconds
Started Aug 14 04:30:49 PM PDT 24
Finished Aug 14 04:31:42 PM PDT 24
Peak memory 205124 kb
Host smart-f47b2302-6aaf-4171-9c8d-759391610ba4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827156765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1827156765
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3136911849
Short name T378
Test name
Test status
Simulation time 61756564035 ps
CPU time 86.15 seconds
Started Aug 14 04:30:37 PM PDT 24
Finished Aug 14 04:32:03 PM PDT 24
Peak memory 205180 kb
Host smart-19a70cd9-4613-40c1-94a4-6fa1430eadcd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136911849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3136911849
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.356088608
Short name T124
Test name
Test status
Simulation time 1156557818 ps
CPU time 4.07 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 205132 kb
Host smart-1e1abfbf-7dff-4fbb-8e0b-3ae878f7221d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356088608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.356088608
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3488261841
Short name T474
Test name
Test status
Simulation time 1996719175 ps
CPU time 5.61 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:48 PM PDT 24
Peak memory 205012 kb
Host smart-d1b314ce-fefa-4e5d-8679-a6db2bd138c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488261841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
488261841
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2236401057
Short name T446
Test name
Test status
Simulation time 151035056 ps
CPU time 1 seconds
Started Aug 14 04:30:31 PM PDT 24
Finished Aug 14 04:30:32 PM PDT 24
Peak memory 204840 kb
Host smart-42152217-0ff6-4778-94af-05c455a18a09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236401057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2236401057
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1207575308
Short name T380
Test name
Test status
Simulation time 43538198622 ps
CPU time 108.28 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:32:33 PM PDT 24
Peak memory 205152 kb
Host smart-efd12672-103f-47f1-8d24-64b10d7a6bf8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207575308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1207575308
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1474622670
Short name T414
Test name
Test status
Simulation time 1070793338 ps
CPU time 3.8 seconds
Started Aug 14 04:31:08 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 204836 kb
Host smart-169d0502-2713-4d81-910e-b95c5ea22142
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474622670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1474622670
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.28374734
Short name T383
Test name
Test status
Simulation time 184342025 ps
CPU time 0.88 seconds
Started Aug 14 04:30:30 PM PDT 24
Finished Aug 14 04:30:32 PM PDT 24
Peak memory 204840 kb
Host smart-367aad25-3f68-41c8-9129-c1f39e585c21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.28374734
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.202908997
Short name T430
Test name
Test status
Simulation time 78210897 ps
CPU time 0.86 seconds
Started Aug 14 04:30:39 PM PDT 24
Finished Aug 14 04:30:40 PM PDT 24
Peak memory 204872 kb
Host smart-5f47a206-b75c-4ccc-8bef-1d5ee689e15b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202908997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.202908997
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1585227462
Short name T337
Test name
Test status
Simulation time 83323342 ps
CPU time 0.73 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 204832 kb
Host smart-894ca229-3021-4281-bb1d-c67c187430b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585227462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1585227462
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.202004610
Short name T113
Test name
Test status
Simulation time 215311325 ps
CPU time 3.71 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:52 PM PDT 24
Peak memory 205184 kb
Host smart-a3cb1b86-aff9-448c-bb90-7cb4ac0b12b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202004610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.202004610
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.523073084
Short name T91
Test name
Test status
Simulation time 5203391579 ps
CPU time 37.77 seconds
Started Aug 14 04:30:54 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 217336 kb
Host smart-66d171cc-2a0b-4ba1-ba78-cf02975d07fa
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523073084 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.523073084
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2841752540
Short name T346
Test name
Test status
Simulation time 168734907 ps
CPU time 2.19 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:53 PM PDT 24
Peak memory 213432 kb
Host smart-4fc170c6-f3ea-4596-b2b7-b5b37c97c709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841752540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2841752540
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.406984952
Short name T464
Test name
Test status
Simulation time 4437554459 ps
CPU time 12.18 seconds
Started Aug 14 04:30:32 PM PDT 24
Finished Aug 14 04:30:44 PM PDT 24
Peak memory 216492 kb
Host smart-2c2bbe87-4b24-45d4-8613-ce25347d0b71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406984952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.406984952
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1364405448
Short name T453
Test name
Test status
Simulation time 3429713241 ps
CPU time 74.19 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:32:04 PM PDT 24
Peak memory 205236 kb
Host smart-15b93422-8516-4ddb-a5b8-f3592c35d0e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364405448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1364405448
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1521212938
Short name T405
Test name
Test status
Simulation time 13541115121 ps
CPU time 32.78 seconds
Started Aug 14 04:31:04 PM PDT 24
Finished Aug 14 04:31:36 PM PDT 24
Peak memory 213400 kb
Host smart-ef9cb147-e716-4996-9394-0cac61c35968
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521212938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1521212938
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3118542553
Short name T137
Test name
Test status
Simulation time 686744818 ps
CPU time 2.41 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 213360 kb
Host smart-0dc7bd94-e43d-4f5c-a044-b753ea78beed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118542553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3118542553
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1659134066
Short name T462
Test name
Test status
Simulation time 131267539 ps
CPU time 1.95 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:45 PM PDT 24
Peak memory 216568 kb
Host smart-bff36898-6b47-489f-90c7-9da29e76f96b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659134066 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1659134066
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4008858017
Short name T403
Test name
Test status
Simulation time 35586997172 ps
CPU time 28.7 seconds
Started Aug 14 04:30:56 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 205108 kb
Host smart-3bf7f49c-f1e5-4c60-9653-655b6a5bae59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008858017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4008858017
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3691416299
Short name T390
Test name
Test status
Simulation time 15454052047 ps
CPU time 26.03 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 205052 kb
Host smart-85d46c0d-1214-4ffd-8d37-5c98e4eb5d4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691416299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3691416299
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.898728574
Short name T382
Test name
Test status
Simulation time 7844910404 ps
CPU time 11.87 seconds
Started Aug 14 04:30:54 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 205088 kb
Host smart-4d19af82-5db3-4aa8-a91d-9061361af891
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898728574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.898728574
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3965722579
Short name T452
Test name
Test status
Simulation time 3054432969 ps
CPU time 5.33 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 205188 kb
Host smart-bbdcd23d-2f11-4b97-b966-cbe733f80432
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965722579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
965722579
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3560009847
Short name T369
Test name
Test status
Simulation time 157977391 ps
CPU time 1.09 seconds
Started Aug 14 04:30:56 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 204836 kb
Host smart-c79fefba-ca89-48d1-9443-49e7b6412354
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560009847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3560009847
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3606311662
Short name T101
Test name
Test status
Simulation time 2393600906 ps
CPU time 7.86 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 205112 kb
Host smart-ecc5e229-f152-4a93-b3cb-7eeac73a5c81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606311662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3606311662
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1989853898
Short name T415
Test name
Test status
Simulation time 405628046 ps
CPU time 0.83 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 204824 kb
Host smart-0ca04c61-ac39-4b58-9fbc-6982b2d06e2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989853898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1989853898
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3014542619
Short name T362
Test name
Test status
Simulation time 167639841 ps
CPU time 1.05 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 204820 kb
Host smart-f0532317-5c05-43c8-9f7e-b10aea0ebbad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014542619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
014542619
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3685896650
Short name T458
Test name
Test status
Simulation time 119257900 ps
CPU time 0.65 seconds
Started Aug 14 04:30:54 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 204804 kb
Host smart-03f1fda2-289b-4439-aa92-92bfcee289c6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685896650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3685896650
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3379433945
Short name T327
Test name
Test status
Simulation time 43924803 ps
CPU time 0.79 seconds
Started Aug 14 04:30:38 PM PDT 24
Finished Aug 14 04:30:39 PM PDT 24
Peak memory 204848 kb
Host smart-c16549bc-50bd-4ecf-b6fb-4fdf2da1ad52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379433945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3379433945
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3339834462
Short name T147
Test name
Test status
Simulation time 476466636 ps
CPU time 7.55 seconds
Started Aug 14 04:30:34 PM PDT 24
Finished Aug 14 04:30:42 PM PDT 24
Peak memory 205192 kb
Host smart-dd209021-4b5a-4544-8372-bf4d661aa11b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339834462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3339834462
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.344357405
Short name T412
Test name
Test status
Simulation time 3284513535 ps
CPU time 24.35 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 221668 kb
Host smart-9c13ba63-4c0e-43c5-a342-7e16aee3bf3c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344357405 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.344357405
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2647596819
Short name T156
Test name
Test status
Simulation time 1006172610 ps
CPU time 3.38 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:30:53 PM PDT 24
Peak memory 213460 kb
Host smart-d9f2fab8-dc44-45f8-a87b-39525ffd0458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647596819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2647596819
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2301160309
Short name T198
Test name
Test status
Simulation time 3366872964 ps
CPU time 22.6 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 221612 kb
Host smart-b3bfee10-30a7-4468-893f-500952e0ab42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301160309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2301160309
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4205267469
Short name T86
Test name
Test status
Simulation time 334898572 ps
CPU time 3.04 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:30:56 PM PDT 24
Peak memory 218788 kb
Host smart-12b75387-815f-4a6c-9fad-7b7ffae95273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205267469 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4205267469
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3145237468
Short name T138
Test name
Test status
Simulation time 132957656 ps
CPU time 1.69 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 218792 kb
Host smart-1812592c-d002-4143-aa27-5e2741ea655b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145237468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3145237468
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3305298903
Short name T341
Test name
Test status
Simulation time 162939834 ps
CPU time 0.77 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 204832 kb
Host smart-95cc2bda-64a0-469c-81e8-d6cf538ae2e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305298903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3305298903
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.267580374
Short name T333
Test name
Test status
Simulation time 3377279713 ps
CPU time 5.48 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:57 PM PDT 24
Peak memory 205168 kb
Host smart-44a0c218-75e0-4603-9bc5-525b8acc6061
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267580374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.267580374
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2640860516
Short name T376
Test name
Test status
Simulation time 810227107 ps
CPU time 1.69 seconds
Started Aug 14 04:30:56 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 204808 kb
Host smart-875cbe80-a2c1-4f80-b5e1-383ac7c2b4c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640860516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
640860516
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1826033314
Short name T136
Test name
Test status
Simulation time 513542662 ps
CPU time 7.73 seconds
Started Aug 14 04:30:59 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 205156 kb
Host smart-c898705e-d0cb-46cf-a058-e88c10461059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826033314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1826033314
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.979185941
Short name T157
Test name
Test status
Simulation time 1953448465 ps
CPU time 30.52 seconds
Started Aug 14 04:30:41 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 221508 kb
Host smart-19c847fb-b3a3-4e96-952f-1223835dd4ef
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979185941 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.979185941
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3146435126
Short name T433
Test name
Test status
Simulation time 217681195 ps
CPU time 4.34 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 213504 kb
Host smart-d1af678a-7454-429f-867c-9eea499b5e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146435126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3146435126
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.973429498
Short name T197
Test name
Test status
Simulation time 887698471 ps
CPU time 8.19 seconds
Started Aug 14 04:30:58 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 213444 kb
Host smart-85c1d4f9-085a-4e70-b32e-b1d2273be540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973429498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.973429498
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3387272441
Short name T399
Test name
Test status
Simulation time 93371280 ps
CPU time 2.47 seconds
Started Aug 14 04:30:31 PM PDT 24
Finished Aug 14 04:30:33 PM PDT 24
Peak memory 216836 kb
Host smart-b555e29a-b969-4ede-b239-08f173d522f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387272441 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3387272441
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2353698110
Short name T479
Test name
Test status
Simulation time 128514505 ps
CPU time 1.59 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 213296 kb
Host smart-69275020-49f8-4271-bb14-d41dfe467bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353698110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2353698110
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3466106212
Short name T456
Test name
Test status
Simulation time 24214042247 ps
CPU time 12.74 seconds
Started Aug 14 04:31:00 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 205080 kb
Host smart-7d1323b5-2079-41cd-979d-9a74af6cb9dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466106212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3466106212
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3436307819
Short name T413
Test name
Test status
Simulation time 2916558535 ps
CPU time 7.54 seconds
Started Aug 14 04:30:47 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 205136 kb
Host smart-0b2db371-05c9-479c-a9af-caba0766c999
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436307819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
436307819
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1979709139
Short name T375
Test name
Test status
Simulation time 239456949 ps
CPU time 0.91 seconds
Started Aug 14 04:30:41 PM PDT 24
Finished Aug 14 04:30:42 PM PDT 24
Peak memory 204868 kb
Host smart-dbe13eff-4ef5-4050-956d-b54d70919f8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979709139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
979709139
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3861402342
Short name T114
Test name
Test status
Simulation time 2772797457 ps
CPU time 4.39 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 204256 kb
Host smart-bdb72e44-4d4a-47fb-b26f-bd018f0d47d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861402342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3861402342
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1376476768
Short name T94
Test name
Test status
Simulation time 11803253798 ps
CPU time 42.32 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 218240 kb
Host smart-20a06533-5bf3-47f0-8976-21fce3433118
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376476768 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1376476768
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4060015326
Short name T418
Test name
Test status
Simulation time 273460063 ps
CPU time 3.32 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:30:56 PM PDT 24
Peak memory 212480 kb
Host smart-35c9271d-0763-444c-995e-de33662aa63c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060015326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4060015326
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3361473726
Short name T455
Test name
Test status
Simulation time 866716042 ps
CPU time 8.96 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:31:06 PM PDT 24
Peak memory 221492 kb
Host smart-2eec6087-481d-4dc3-a9cd-cb69515f3042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361473726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3361473726
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2390052416
Short name T97
Test name
Test status
Simulation time 167455622 ps
CPU time 2.97 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:10 PM PDT 24
Peak memory 219048 kb
Host smart-63f0cdee-0dfb-4fd2-9e43-0466975c70b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390052416 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2390052416
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.475551068
Short name T143
Test name
Test status
Simulation time 120789850 ps
CPU time 1.58 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:08 PM PDT 24
Peak memory 213348 kb
Host smart-048ac223-1e35-417e-b938-34c91852334d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475551068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.475551068
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2766559151
Short name T447
Test name
Test status
Simulation time 24688131128 ps
CPU time 63.71 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 205092 kb
Host smart-fc6604f4-9694-497f-8fbb-bf40d41ab573
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766559151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2766559151
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2174065934
Short name T438
Test name
Test status
Simulation time 5736851501 ps
CPU time 5.68 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 205136 kb
Host smart-958ac1de-eb9f-4169-a1e4-b4bd24d897b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174065934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
174065934
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1714340927
Short name T394
Test name
Test status
Simulation time 265868334 ps
CPU time 0.86 seconds
Started Aug 14 04:31:00 PM PDT 24
Finished Aug 14 04:31:01 PM PDT 24
Peak memory 204868 kb
Host smart-efd23b8b-1410-4104-bc5c-606db0389207
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714340927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
714340927
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2669046888
Short name T361
Test name
Test status
Simulation time 2064529735 ps
CPU time 7.74 seconds
Started Aug 14 04:30:47 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 205072 kb
Host smart-412733c6-0663-4fb2-864e-684c3ecefa88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669046888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2669046888
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1664219148
Short name T437
Test name
Test status
Simulation time 5773465972 ps
CPU time 22.77 seconds
Started Aug 14 04:31:00 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 221560 kb
Host smart-770eb170-8445-45c6-bc31-169febf8a623
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664219148 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1664219148
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.909507341
Short name T364
Test name
Test status
Simulation time 111143998 ps
CPU time 2.14 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:04 PM PDT 24
Peak memory 213408 kb
Host smart-fb9b747f-d246-4b25-ae8d-84dd95437dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909507341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.909507341
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1000957131
Short name T374
Test name
Test status
Simulation time 104823951 ps
CPU time 2.23 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 216588 kb
Host smart-8263831c-de58-451c-9a67-1ae6db9e1072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000957131 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1000957131
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.168815410
Short name T428
Test name
Test status
Simulation time 219776358 ps
CPU time 2.23 seconds
Started Aug 14 04:30:36 PM PDT 24
Finished Aug 14 04:30:39 PM PDT 24
Peak memory 219136 kb
Host smart-3f1b8715-9010-4f22-9519-8fe88301afa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168815410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.168815410
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1803335070
Short name T377
Test name
Test status
Simulation time 2635687772 ps
CPU time 2.11 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 204196 kb
Host smart-3200309c-5c2f-4ff9-ba2b-67ace24e0299
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803335070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1803335070
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4074394768
Short name T389
Test name
Test status
Simulation time 6974244906 ps
CPU time 6.29 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 205176 kb
Host smart-f64b5a33-ee3f-44ea-9293-d95c2d0c1061
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074394768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
074394768
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2073534147
Short name T467
Test name
Test status
Simulation time 406433428 ps
CPU time 1.31 seconds
Started Aug 14 04:30:54 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 204808 kb
Host smart-e8f59c3f-4bd4-4828-b89e-5f5953280574
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073534147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
073534147
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1725360010
Short name T411
Test name
Test status
Simulation time 1617819399 ps
CPU time 7.14 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:48 PM PDT 24
Peak memory 205184 kb
Host smart-af55e66f-de70-4cf5-b440-fd1e679e5024
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725360010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1725360010
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4095076228
Short name T87
Test name
Test status
Simulation time 1374294588 ps
CPU time 29.13 seconds
Started Aug 14 04:30:30 PM PDT 24
Finished Aug 14 04:30:59 PM PDT 24
Peak memory 214660 kb
Host smart-72615d7a-678e-4c8d-9da5-c57a3edd74c5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095076228 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4095076228
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1678673531
Short name T351
Test name
Test status
Simulation time 116715829 ps
CPU time 2.95 seconds
Started Aug 14 04:30:40 PM PDT 24
Finished Aug 14 04:30:43 PM PDT 24
Peak memory 213496 kb
Host smart-4bc04274-e245-4e0b-b241-38ed58cafec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678673531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1678673531
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1773599110
Short name T445
Test name
Test status
Simulation time 815904312 ps
CPU time 2.7 seconds
Started Aug 14 04:30:56 PM PDT 24
Finished Aug 14 04:30:59 PM PDT 24
Peak memory 216056 kb
Host smart-4d3c6773-b351-49b7-a81a-3529d919d160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773599110 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1773599110
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.597387444
Short name T134
Test name
Test status
Simulation time 427604767 ps
CPU time 2.42 seconds
Started Aug 14 04:30:51 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 218904 kb
Host smart-34f0fe38-9848-4e8a-b8de-6809fb35b811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597387444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.597387444
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1240630146
Short name T370
Test name
Test status
Simulation time 5256420169 ps
CPU time 7.38 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 205164 kb
Host smart-32cf6de5-c36b-4b74-b097-cb3ec27601dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240630146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1240630146
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2949781565
Short name T381
Test name
Test status
Simulation time 4166844764 ps
CPU time 4.81 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 205072 kb
Host smart-2ac8aab8-61fb-4480-940e-fcadea2fc6ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949781565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
949781565
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1340675775
Short name T344
Test name
Test status
Simulation time 254033840 ps
CPU time 1.32 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 204848 kb
Host smart-ce4ba189-f19f-419f-866a-a246096fa8c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340675775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
340675775
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3607773469
Short name T478
Test name
Test status
Simulation time 748827011 ps
CPU time 3.98 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:31:01 PM PDT 24
Peak memory 205088 kb
Host smart-6a3e7c21-b9b3-4a96-b0b3-a93d3c851cf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607773469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3607773469
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3046176784
Short name T95
Test name
Test status
Simulation time 4928045420 ps
CPU time 32.12 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 216176 kb
Host smart-991e9a47-2a74-4898-81c9-15893e3f1fbc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046176784 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3046176784
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3837074461
Short name T366
Test name
Test status
Simulation time 174164711 ps
CPU time 2.3 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:30:55 PM PDT 24
Peak memory 213444 kb
Host smart-3046a6a3-2ca0-4417-a506-b85d7e179740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837074461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3837074461
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1691041381
Short name T193
Test name
Test status
Simulation time 2535749157 ps
CPU time 14.87 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:31:03 PM PDT 24
Peak memory 221540 kb
Host smart-5abb9b99-1c07-47c2-ad7d-64a944e91c38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691041381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1691041381
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.393769602
Short name T48
Test name
Test status
Simulation time 411419934 ps
CPU time 1.01 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 204780 kb
Host smart-44dfd6cb-54f9-4162-9d60-edefffca865e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393769602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.393769602
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3382842847
Short name T217
Test name
Test status
Simulation time 121198031 ps
CPU time 1.04 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:03 PM PDT 24
Peak memory 204940 kb
Host smart-c65c6201-8849-4f72-a438-b1220702ccc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382842847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3382842847
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3145795916
Short name T209
Test name
Test status
Simulation time 5086261065 ps
CPU time 9.76 seconds
Started Aug 14 04:32:48 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 213492 kb
Host smart-61d51d3d-d901-4c51-938e-dd224bae6971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145795916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3145795916
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3202696311
Short name T36
Test name
Test status
Simulation time 1556592480 ps
CPU time 1.34 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:07 PM PDT 24
Peak memory 213436 kb
Host smart-319bd43b-7506-49c6-8347-443ac8bc3b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202696311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3202696311
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_buffered_enable.2343489068
Short name T314
Test name
Test status
Simulation time 136908818 ps
CPU time 0.93 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:12 PM PDT 24
Peak memory 234068 kb
Host smart-99676c3c-0f1f-465a-b174-99ef8f0f61ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343489068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.2343489068
Directory /workspace/0.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2623188001
Short name T69
Test name
Test status
Simulation time 1279044476 ps
CPU time 4.13 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 204856 kb
Host smart-25116b4a-ba37-4810-b470-ff52168f0471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623188001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2623188001
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.4241899367
Short name T319
Test name
Test status
Simulation time 368110975 ps
CPU time 0.94 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 204804 kb
Host smart-5c162479-e834-442d-87d1-3dec36ede191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241899367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.4241899367
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1998805047
Short name T241
Test name
Test status
Simulation time 90127741 ps
CPU time 0.76 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 204716 kb
Host smart-c4b58b40-73b2-48cb-8466-fcaf800d85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998805047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1998805047
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3880405457
Short name T274
Test name
Test status
Simulation time 56715912 ps
CPU time 0.85 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 214888 kb
Host smart-a022894c-7203-472d-90eb-47660baa1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880405457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3880405457
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3720976074
Short name T291
Test name
Test status
Simulation time 2684714769 ps
CPU time 3.36 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:56 PM PDT 24
Peak memory 205384 kb
Host smart-c1749d09-51fd-46c7-9e9c-7dfe51d4ac82
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720976074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3720976074
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2228794294
Short name T251
Test name
Test status
Simulation time 250321246 ps
CPU time 1.12 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 204720 kb
Host smart-922b7e17-34b9-4883-8dd6-0c184c70f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228794294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2228794294
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3898342410
Short name T187
Test name
Test status
Simulation time 64025338 ps
CPU time 0.73 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 204788 kb
Host smart-b9eee1f9-323c-4c12-b696-d3c62b8aa66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898342410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3898342410
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3045632803
Short name T305
Test name
Test status
Simulation time 71198235 ps
CPU time 0.86 seconds
Started Aug 14 04:32:43 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 204804 kb
Host smart-39dacbb4-e0ee-4d9b-b44a-b036a5ae5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045632803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3045632803
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2922264282
Short name T207
Test name
Test status
Simulation time 302208992 ps
CPU time 1.51 seconds
Started Aug 14 04:33:01 PM PDT 24
Finished Aug 14 04:33:03 PM PDT 24
Peak memory 204792 kb
Host smart-80b0fc22-c927-4890-b932-8dbf5f87c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922264282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2922264282
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1214574986
Short name T315
Test name
Test status
Simulation time 1484925300 ps
CPU time 1.81 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 204732 kb
Host smart-cf1f8939-90fd-4d6d-b9bf-670e0a7d62ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214574986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1214574986
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2121460980
Short name T242
Test name
Test status
Simulation time 204669208 ps
CPU time 1.24 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:12 PM PDT 24
Peak memory 204800 kb
Host smart-86aa32c3-a4d9-46f9-a7b1-6fc8c93bf1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121460980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2121460980
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3713307176
Short name T112
Test name
Test status
Simulation time 450982902 ps
CPU time 1.94 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 204776 kb
Host smart-04d78d9d-89da-489b-b102-d29276b50ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713307176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3713307176
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.18459788
Short name T81
Test name
Test status
Simulation time 421811689 ps
CPU time 0.91 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 204812 kb
Host smart-767212c0-e05a-4df5-b09d-3b49d02a1e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18459788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.18459788
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4208560639
Short name T26
Test name
Test status
Simulation time 592690891 ps
CPU time 2.19 seconds
Started Aug 14 04:32:56 PM PDT 24
Finished Aug 14 04:32:59 PM PDT 24
Peak memory 204744 kb
Host smart-d73577b1-a350-4f9f-bbc3-0369ae251998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208560639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.4208560639
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.381084868
Short name T105
Test name
Test status
Simulation time 93304882 ps
CPU time 0.95 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:32:55 PM PDT 24
Peak memory 212920 kb
Host smart-0e856455-fc39-485d-978c-834e7d395c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381084868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.381084868
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.500782213
Short name T310
Test name
Test status
Simulation time 901768439 ps
CPU time 1.85 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 204816 kb
Host smart-02aebf3f-f7bd-444a-b2f8-0940c8b182a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500782213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.500782213
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.88054482
Short name T237
Test name
Test status
Simulation time 9930965437 ps
CPU time 29.68 seconds
Started Aug 14 04:32:49 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 213532 kb
Host smart-2c73a093-55c4-423d-b54e-ac3fa779b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88054482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.88054482
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3722209041
Short name T54
Test name
Test status
Simulation time 1045389023 ps
CPU time 1.52 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 204788 kb
Host smart-9a451fd2-a58e-44c9-a8c4-505b3ce9eeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722209041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3722209041
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1453751193
Short name T307
Test name
Test status
Simulation time 7039423579 ps
CPU time 9.34 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 205028 kb
Host smart-6185b02f-3398-47eb-9fc7-f9ba4fc64421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453751193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1453751193
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.759276808
Short name T75
Test name
Test status
Simulation time 1963712820 ps
CPU time 31.62 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:32 PM PDT 24
Peak memory 216900 kb
Host smart-41324dce-27f0-46af-a880-c9974ff98bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759276808 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.759276808
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1148509624
Short name T50
Test name
Test status
Simulation time 595115322 ps
CPU time 1.48 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 204884 kb
Host smart-4731f6e1-bb43-4b22-822b-6dd6f63462c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148509624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1148509624
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2705045352
Short name T64
Test name
Test status
Simulation time 166746274 ps
CPU time 1.09 seconds
Started Aug 14 04:32:52 PM PDT 24
Finished Aug 14 04:32:53 PM PDT 24
Peak memory 204940 kb
Host smart-d5abda80-72e0-4aa7-ac29-a199104f2597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705045352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2705045352
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.210535643
Short name T230
Test name
Test status
Simulation time 30581962987 ps
CPU time 18.82 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 213504 kb
Host smart-cb62a621-94a5-4596-935a-7874aee0499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210535643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.210535643
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1325705887
Short name T271
Test name
Test status
Simulation time 1791507821 ps
CPU time 6.22 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 221596 kb
Host smart-4677a87b-6ff7-4e08-9054-76762c2c21ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325705887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1325705887
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_buffered_enable.3950640278
Short name T304
Test name
Test status
Simulation time 289232885 ps
CPU time 1.59 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 226016 kb
Host smart-bb5c9f69-22e2-4aa7-a004-ef3aea6a5e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950640278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.3950640278
Directory /workspace/1.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2932991172
Short name T264
Test name
Test status
Simulation time 744957116 ps
CPU time 1.14 seconds
Started Aug 14 04:33:03 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 204776 kb
Host smart-7b31a1fe-1c81-4c97-8d62-3735744704e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932991172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2932991172
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3250595946
Short name T7
Test name
Test status
Simulation time 925703062 ps
CPU time 0.88 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 204784 kb
Host smart-2c486db8-719e-40d2-8b4f-80098dccbc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250595946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3250595946
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3685929247
Short name T38
Test name
Test status
Simulation time 103006489 ps
CPU time 0.81 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:07 PM PDT 24
Peak memory 204724 kb
Host smart-e7a5ab8d-27d5-412c-be0e-80efe0260b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685929247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3685929247
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.4108078809
Short name T261
Test name
Test status
Simulation time 283374278 ps
CPU time 1.39 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 204720 kb
Host smart-ffb68bbd-8d5c-4738-ac5c-fad3263815f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108078809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4108078809
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1129581113
Short name T320
Test name
Test status
Simulation time 238626564 ps
CPU time 0.84 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 204744 kb
Host smart-fdcfe379-3420-4c16-844e-2e8da5094d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129581113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1129581113
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2653112340
Short name T222
Test name
Test status
Simulation time 68685794 ps
CPU time 0.82 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 214860 kb
Host smart-6c29fe70-67db-4e21-b198-f9237451d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653112340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2653112340
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3695657037
Short name T30
Test name
Test status
Simulation time 5740360117 ps
CPU time 5.89 seconds
Started Aug 14 04:32:54 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 213416 kb
Host smart-c1d07faf-f28b-4f09-bb2b-b8620076401b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695657037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3695657037
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1236635847
Short name T77
Test name
Test status
Simulation time 1302856928 ps
CPU time 1.72 seconds
Started Aug 14 04:33:34 PM PDT 24
Finished Aug 14 04:33:36 PM PDT 24
Peak memory 204780 kb
Host smart-49f8ece2-6e0a-4d5b-824c-b9c567c57510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236635847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1236635847
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3657328016
Short name T67
Test name
Test status
Simulation time 249465800 ps
CPU time 0.78 seconds
Started Aug 14 04:33:01 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 204744 kb
Host smart-bb0a4c7b-b8d1-4aa2-9726-d4a9c25c5482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657328016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3657328016
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.894876961
Short name T76
Test name
Test status
Simulation time 671848770 ps
CPU time 1.5 seconds
Started Aug 14 04:32:57 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 204892 kb
Host smart-67b98486-fd24-4751-a673-2087fb978ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894876961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.894876961
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1692015804
Short name T248
Test name
Test status
Simulation time 939727908 ps
CPU time 1.84 seconds
Started Aug 14 04:32:58 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 204752 kb
Host smart-d4ac8a5e-08b3-439d-93a9-d18611632df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692015804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1692015804
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3302311960
Short name T188
Test name
Test status
Simulation time 873797937 ps
CPU time 1.33 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 204780 kb
Host smart-09f7965a-420a-4141-97ec-2fe99eb3e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302311960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3302311960
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2612276455
Short name T126
Test name
Test status
Simulation time 128605193 ps
CPU time 0.81 seconds
Started Aug 14 04:32:50 PM PDT 24
Finished Aug 14 04:32:51 PM PDT 24
Peak memory 204700 kb
Host smart-ebbfff66-f30c-4c5c-82bf-d4b4f132ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612276455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2612276455
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2858115316
Short name T131
Test name
Test status
Simulation time 380597013 ps
CPU time 0.99 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:12 PM PDT 24
Peak memory 204800 kb
Host smart-7b837f77-198a-4739-a95e-0cc6efd80ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858115316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2858115316
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.149057684
Short name T8
Test name
Test status
Simulation time 109628860 ps
CPU time 0.99 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 213012 kb
Host smart-8b902591-043e-4cdd-b425-fd8df9ef8803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149057684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.149057684
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3847606754
Short name T270
Test name
Test status
Simulation time 323745132 ps
CPU time 1.68 seconds
Started Aug 14 04:32:55 PM PDT 24
Finished Aug 14 04:32:57 PM PDT 24
Peak memory 204716 kb
Host smart-757e0a1a-df16-47e4-8772-845a5c92ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847606754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3847606754
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1199762249
Short name T41
Test name
Test status
Simulation time 161537014 ps
CPU time 0.89 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 213112 kb
Host smart-91c8070a-5c23-4575-b240-14c7e2fdad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199762249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1199762249
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3834497258
Short name T166
Test name
Test status
Simulation time 3493011818 ps
CPU time 3.43 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 205088 kb
Host smart-11dbf299-6490-4757-a416-f22b0eccd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834497258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3834497258
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2154825369
Short name T71
Test name
Test status
Simulation time 7358810631 ps
CPU time 6.23 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 205240 kb
Host smart-e4000e45-d17f-4ae0-8511-99b634d95e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154825369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2154825369
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1748079536
Short name T62
Test name
Test status
Simulation time 2108497417 ps
CPU time 2.18 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:15 PM PDT 24
Peak memory 229216 kb
Host smart-b98dd095-7d44-4781-ad4e-9456ecacb5de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748079536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1748079536
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3273872270
Short name T275
Test name
Test status
Simulation time 1618713033 ps
CPU time 3.5 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 204740 kb
Host smart-8798d2f1-1036-417d-b927-82049b4efc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273872270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3273872270
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2994460667
Short name T53
Test name
Test status
Simulation time 9140158402 ps
CPU time 75.79 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:34:15 PM PDT 24
Peak memory 229884 kb
Host smart-41380276-2325-471e-ac65-8ab1f33bd0d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994460667 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2994460667
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.665483459
Short name T306
Test name
Test status
Simulation time 30901132 ps
CPU time 0.72 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 204960 kb
Host smart-e3d99a10-bf99-4c66-8088-4efea6fe3a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665483459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.665483459
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.133354940
Short name T278
Test name
Test status
Simulation time 592820140 ps
CPU time 2.31 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:15 PM PDT 24
Peak memory 205176 kb
Host smart-1e9d9438-f64e-47d7-9907-7156cbf2d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133354940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.133354940
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3910096788
Short name T185
Test name
Test status
Simulation time 7096619393 ps
CPU time 16.87 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 205300 kb
Host smart-5f1b57f9-2f1d-4654-a7df-45a6bec72acc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910096788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3910096788
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1246690417
Short name T84
Test name
Test status
Simulation time 1429639090 ps
CPU time 4.94 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 205228 kb
Host smart-8e6da388-b92f-4d55-90dd-6a8c1a0be65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246690417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1246690417
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3008025854
Short name T191
Test name
Test status
Simulation time 2143778871 ps
CPU time 4.43 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 213228 kb
Host smart-ac649e3c-f671-4fb9-9ab0-615a28effee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008025854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3008025854
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2025309431
Short name T239
Test name
Test status
Simulation time 157256682 ps
CPU time 0.84 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 204964 kb
Host smart-4e1de2c0-0f44-4687-9c5f-3af72fcbf0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025309431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2025309431
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.502466825
Short name T219
Test name
Test status
Simulation time 52819191811 ps
CPU time 79.82 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:34:36 PM PDT 24
Peak memory 213556 kb
Host smart-8c9caf63-52c7-4eb6-ac73-5f8486bddce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502466825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.502466825
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2049750869
Short name T258
Test name
Test status
Simulation time 13663326840 ps
CPU time 35.06 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:50 PM PDT 24
Peak memory 213692 kb
Host smart-040d323a-f990-4a13-be90-a5c7ec43157d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049750869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2049750869
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2068058502
Short name T203
Test name
Test status
Simulation time 1737553677 ps
CPU time 2.44 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 205248 kb
Host smart-326c1f33-70ae-4032-aeb4-03a19ed00e6a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068058502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2068058502
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1830883214
Short name T176
Test name
Test status
Simulation time 11292063053 ps
CPU time 28.72 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:45 PM PDT 24
Peak memory 213556 kb
Host smart-950ad23b-812f-4f3d-8b4f-b3cc5c7b72ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830883214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1830883214
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.703155385
Short name T170
Test name
Test status
Simulation time 3719157367 ps
CPU time 6.91 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 213264 kb
Host smart-a21b9a92-150a-4911-8966-228b998624bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703155385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.703155385
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2846540918
Short name T220
Test name
Test status
Simulation time 164733401 ps
CPU time 0.73 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 204928 kb
Host smart-6ddf0648-7061-438e-809a-46fe7bb935a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846540918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2846540918
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1322507094
Short name T259
Test name
Test status
Simulation time 6013365099 ps
CPU time 18.37 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 213496 kb
Host smart-1731b979-0ed3-452d-9e51-34ab4ef036fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322507094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1322507094
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.337863496
Short name T284
Test name
Test status
Simulation time 1510492470 ps
CPU time 5.09 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205228 kb
Host smart-488821f7-fc06-49ed-9366-dabab1e02abf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337863496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.337863496
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.97134985
Short name T263
Test name
Test status
Simulation time 3908086940 ps
CPU time 3.87 seconds
Started Aug 14 04:33:27 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 205396 kb
Host smart-9f14e5f6-9557-4a9b-9fd8-f9c22741412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97134985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.97134985
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2092493984
Short name T324
Test name
Test status
Simulation time 3980011578 ps
CPU time 3.99 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 213348 kb
Host smart-50556c3f-aef4-407a-bc44-a6968a5b3563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092493984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2092493984
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3808067762
Short name T256
Test name
Test status
Simulation time 102463485 ps
CPU time 0.69 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 204956 kb
Host smart-c4c9e9dc-0351-44c5-a0b4-ed0ee2ab25c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808067762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3808067762
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.4141121707
Short name T279
Test name
Test status
Simulation time 1377216837 ps
CPU time 3.78 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 213448 kb
Host smart-1ae487d8-7270-4a15-acbe-08cc0532964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141121707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4141121707
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.34462517
Short name T74
Test name
Test status
Simulation time 2220271744 ps
CPU time 2.47 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205392 kb
Host smart-a8e81e00-2844-4706-bcfa-f2cca3a5b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34462517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.34462517
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1474106891
Short name T231
Test name
Test status
Simulation time 8226464810 ps
CPU time 23.64 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:47 PM PDT 24
Peak memory 213584 kb
Host smart-fa52c89b-974d-45d2-a718-b68d28fbc841
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474106891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1474106891
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.4140544371
Short name T109
Test name
Test status
Simulation time 4415668467 ps
CPU time 2.1 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 213496 kb
Host smart-aa60a262-92bd-4c12-ab3a-fe962b0f529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140544371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4140544371
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.100038680
Short name T168
Test name
Test status
Simulation time 5925054486 ps
CPU time 2.25 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 205052 kb
Host smart-1e8dd5ef-42e6-4a00-9120-0efc635795ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100038680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.100038680
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1129971496
Short name T266
Test name
Test status
Simulation time 70754078 ps
CPU time 0.87 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 204936 kb
Host smart-a38cb58e-844a-4383-908c-37c39d4ba25c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129971496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1129971496
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1581575408
Short name T24
Test name
Test status
Simulation time 3673797012 ps
CPU time 2.13 seconds
Started Aug 14 04:33:21 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 213612 kb
Host smart-814c9faf-6054-4717-a896-ad4fa6aae999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581575408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1581575408
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4207001108
Short name T78
Test name
Test status
Simulation time 4723400647 ps
CPU time 13.79 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 213788 kb
Host smart-897d2124-a5f8-4fa3-a364-bcd77031a515
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207001108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.4207001108
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2719266288
Short name T229
Test name
Test status
Simulation time 5124426731 ps
CPU time 6.51 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 205400 kb
Host smart-533a8df5-652e-466f-85c3-7d3f9bcc6e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719266288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2719266288
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2337478962
Short name T15
Test name
Test status
Simulation time 1078110016 ps
CPU time 1.55 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:22 PM PDT 24
Peak memory 205036 kb
Host smart-bc085e2d-4f37-4068-a61a-35d047921603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337478962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2337478962
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3867658543
Short name T300
Test name
Test status
Simulation time 49533652 ps
CPU time 0.83 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 205196 kb
Host smart-3b1a01d1-19ed-4048-9abd-479bba0bfd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867658543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3867658543
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1566020602
Short name T311
Test name
Test status
Simulation time 14230924862 ps
CPU time 38 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:57 PM PDT 24
Peak memory 205296 kb
Host smart-99e73311-4835-41cf-b921-a3f5849a18c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566020602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1566020602
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.773244910
Short name T175
Test name
Test status
Simulation time 17713154157 ps
CPU time 16.54 seconds
Started Aug 14 04:33:28 PM PDT 24
Finished Aug 14 04:33:45 PM PDT 24
Peak memory 213608 kb
Host smart-3bf33abb-bf51-453a-b644-ac22ead91d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773244910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.773244910
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.12808490
Short name T312
Test name
Test status
Simulation time 956641159 ps
CPU time 1.91 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205244 kb
Host smart-bbfdc3e4-b1c9-4342-a524-4873bb94724c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12808490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl
_access.12808490
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1428914298
Short name T61
Test name
Test status
Simulation time 947051040 ps
CPU time 1.33 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 205368 kb
Host smart-f17d058c-0e7d-47f0-af97-a81e73b1dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428914298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1428914298
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1125192062
Short name T290
Test name
Test status
Simulation time 2758181507 ps
CPU time 3.01 seconds
Started Aug 14 04:33:32 PM PDT 24
Finished Aug 14 04:33:35 PM PDT 24
Peak memory 205124 kb
Host smart-6dbb5b35-4c32-43eb-ba1d-95d4926913e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125192062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1125192062
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.10487758
Short name T154
Test name
Test status
Simulation time 81942163 ps
CPU time 0.7 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 205040 kb
Host smart-60d069df-60b0-45fb-b1a9-330b1acbe829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10487758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.10487758
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2177347527
Short name T3
Test name
Test status
Simulation time 9322855970 ps
CPU time 14.95 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 213436 kb
Host smart-90597803-bc58-4942-ac2c-3fa6a5e522a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177347527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2177347527
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3391774459
Short name T73
Test name
Test status
Simulation time 3676162262 ps
CPU time 6.54 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 205432 kb
Host smart-9c2f702c-8518-4caa-9658-a9ac9f43c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391774459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3391774459
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2375106821
Short name T189
Test name
Test status
Simulation time 988770342 ps
CPU time 2.27 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205276 kb
Host smart-3c62270f-bc9e-448a-9319-74bb401e7041
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375106821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2375106821
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1579194835
Short name T240
Test name
Test status
Simulation time 8147742369 ps
CPU time 22.8 seconds
Started Aug 14 04:33:43 PM PDT 24
Finished Aug 14 04:34:05 PM PDT 24
Peak memory 213640 kb
Host smart-4f84b8b1-c6e7-4b1a-a8e3-6a885df172ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579194835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1579194835
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2433239355
Short name T106
Test name
Test status
Simulation time 2979688542 ps
CPU time 3.07 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 205072 kb
Host smart-11ae8de4-8972-4844-9ba4-0ac0742cfa70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433239355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2433239355
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.725587997
Short name T280
Test name
Test status
Simulation time 167234034 ps
CPU time 0.81 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 204916 kb
Host smart-c7a17bc1-2fe2-4512-9f08-68c984edb615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725587997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.725587997
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.108383479
Short name T277
Test name
Test status
Simulation time 1607218053 ps
CPU time 1.52 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 205296 kb
Host smart-bdceb773-3fec-4d56-aa1d-73147074d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108383479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.108383479
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.174664579
Short name T221
Test name
Test status
Simulation time 8012421567 ps
CPU time 17.65 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 213532 kb
Host smart-724eda34-1c56-4f75-9382-da012ca69a47
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174664579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.174664579
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1673249027
Short name T316
Test name
Test status
Simulation time 13760659635 ps
CPU time 13.43 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:32 PM PDT 24
Peak memory 205284 kb
Host smart-0f90d342-02c0-4f94-97a6-332ac9539af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673249027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1673249027
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3358789564
Short name T12
Test name
Test status
Simulation time 6079081380 ps
CPU time 9.96 seconds
Started Aug 14 04:33:21 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 213260 kb
Host smart-4a2bbf97-cc39-4d5b-ac00-15b1f636745e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358789564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3358789564
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1162165612
Short name T260
Test name
Test status
Simulation time 49051606 ps
CPU time 0.78 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 204940 kb
Host smart-d4ebdb5a-8d64-42a0-bba9-3f726d5f63a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162165612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1162165612
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2957999152
Short name T298
Test name
Test status
Simulation time 12399077829 ps
CPU time 10.77 seconds
Started Aug 14 04:33:43 PM PDT 24
Finished Aug 14 04:33:53 PM PDT 24
Peak memory 213600 kb
Host smart-01c512d1-8d73-42b4-8984-8dbf5cc4eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957999152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2957999152
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3467575333
Short name T244
Test name
Test status
Simulation time 4905911025 ps
CPU time 6.92 seconds
Started Aug 14 04:33:31 PM PDT 24
Finished Aug 14 04:33:43 PM PDT 24
Peak memory 214512 kb
Host smart-a9e42f11-7dc8-4be0-b05a-efb3d289449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467575333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3467575333
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3570289290
Short name T294
Test name
Test status
Simulation time 8990541138 ps
CPU time 23.85 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:44 PM PDT 24
Peak memory 213480 kb
Host smart-0e174383-cf9d-4868-85d6-f1f363e6aa6e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570289290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3570289290
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.684691122
Short name T110
Test name
Test status
Simulation time 6509946993 ps
CPU time 2.94 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 205292 kb
Host smart-894d32c6-9e68-4393-b168-7a5aa9dc5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684691122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.684691122
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2966678771
Short name T254
Test name
Test status
Simulation time 31252055 ps
CPU time 0.74 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 204908 kb
Host smart-38cdb988-bd53-41a6-a418-98d1c617d969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966678771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2966678771
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.904079229
Short name T205
Test name
Test status
Simulation time 6466559569 ps
CPU time 10.86 seconds
Started Aug 14 04:33:39 PM PDT 24
Finished Aug 14 04:33:50 PM PDT 24
Peak memory 205392 kb
Host smart-7b040977-8ed7-4202-9407-ef5f80249322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904079229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.904079229
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3697584687
Short name T238
Test name
Test status
Simulation time 4579624146 ps
CPU time 3.03 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 213552 kb
Host smart-aa2165ba-52f3-4da9-ae7a-812e2f6d9ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697584687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3697584687
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1435699954
Short name T2
Test name
Test status
Simulation time 2274334217 ps
CPU time 4.33 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:15 PM PDT 24
Peak memory 205268 kb
Host smart-a4923143-01a9-4002-a928-42292cb9f5e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435699954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1435699954
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3982950356
Short name T210
Test name
Test status
Simulation time 4910149788 ps
CPU time 5.72 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:28 PM PDT 24
Peak memory 205388 kb
Host smart-c6a8d5f9-7bd9-494d-bf53-08b5545971dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982950356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3982950356
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1237749400
Short name T301
Test name
Test status
Simulation time 7719008216 ps
CPU time 12.07 seconds
Started Aug 14 04:33:34 PM PDT 24
Finished Aug 14 04:33:46 PM PDT 24
Peak memory 213312 kb
Host smart-15534db8-5448-4524-ab7a-60d22d216718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237749400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1237749400
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.55282476
Short name T107
Test name
Test status
Simulation time 101678787 ps
CPU time 0.91 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 204936 kb
Host smart-9608f8a2-eeb9-458f-a18a-b1bd6d6369d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55282476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.55282476
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3548593828
Short name T132
Test name
Test status
Simulation time 4736980408 ps
CPU time 13.9 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 213496 kb
Host smart-1b7db519-0888-4ff6-8b02-610641c6f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548593828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3548593828
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.4229363028
Short name T226
Test name
Test status
Simulation time 2775485630 ps
CPU time 3.06 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:03 PM PDT 24
Peak memory 214528 kb
Host smart-17306cb4-8606-41ab-9a70-4fcaec6dd5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229363028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.4229363028
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_buffered_enable.1112487142
Short name T58
Test name
Test status
Simulation time 139655612 ps
CPU time 1.17 seconds
Started Aug 14 04:32:53 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 225908 kb
Host smart-d5593ebc-3900-45c5-91c1-c5a939eadbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112487142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.1112487142
Directory /workspace/2.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1662841108
Short name T281
Test name
Test status
Simulation time 1137216304 ps
CPU time 2.67 seconds
Started Aug 14 04:32:57 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 205308 kb
Host smart-f885ac17-1403-459c-bc03-e049177e78ef
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662841108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1662841108
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.3887289298
Short name T243
Test name
Test status
Simulation time 1274284943 ps
CPU time 1.5 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 204804 kb
Host smart-fd0c7daf-6538-4201-8e44-10c5aab594b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887289298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.3887289298
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.4181010164
Short name T70
Test name
Test status
Simulation time 189308905 ps
CPU time 1.09 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:03 PM PDT 24
Peak memory 204716 kb
Host smart-9dfac06f-9a41-4910-8be0-78205c59eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181010164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4181010164
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3826110895
Short name T268
Test name
Test status
Simulation time 2312644764 ps
CPU time 6.63 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:09 PM PDT 24
Peak memory 205300 kb
Host smart-a5bdba63-970f-45d5-8770-35882ccb0652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826110895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3826110895
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3495222666
Short name T63
Test name
Test status
Simulation time 278150315 ps
CPU time 1.73 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:06 PM PDT 24
Peak memory 229472 kb
Host smart-7d36841c-bbe8-46d9-8606-6284f52e555a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495222666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3495222666
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.4018602825
Short name T55
Test name
Test status
Simulation time 71061387 ps
CPU time 0.75 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 213260 kb
Host smart-e20feaf0-5b1a-4f6e-8d66-e9108d3130ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018602825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.4018602825
Directory /workspace/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4221491225
Short name T245
Test name
Test status
Simulation time 3740183545 ps
CPU time 3.6 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 213260 kb
Host smart-f0fbfa94-bca9-430c-88ff-da48b85f2a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221491225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4221491225
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.811588629
Short name T151
Test name
Test status
Simulation time 107361303 ps
CPU time 0.77 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 205024 kb
Host smart-bf25b854-93b5-49bc-955d-7a1467f63ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811588629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.811588629
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2035843633
Short name T6
Test name
Test status
Simulation time 2529336200 ps
CPU time 8.08 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:32 PM PDT 24
Peak memory 213264 kb
Host smart-5f1198a4-fa45-4144-a654-eeaa5ea514a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035843633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2035843633
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.807121987
Short name T308
Test name
Test status
Simulation time 270291785 ps
CPU time 0.78 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:15 PM PDT 24
Peak memory 204924 kb
Host smart-3150464d-aa5a-45f3-9ef3-72649c4e88f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807121987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.807121987
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.772166191
Short name T11
Test name
Test status
Simulation time 8486526265 ps
CPU time 3.5 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:29 PM PDT 24
Peak memory 213332 kb
Host smart-d6e5efe6-264b-42d8-b9d0-166b0e9057f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772166191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.772166191
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3792306591
Short name T267
Test name
Test status
Simulation time 65698173 ps
CPU time 0.69 seconds
Started Aug 14 04:33:29 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 205032 kb
Host smart-1e7ea9fb-c6cc-458e-ab48-ed4b410c99f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792306591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3792306591
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1502542487
Short name T39
Test name
Test status
Simulation time 3803756872 ps
CPU time 5.78 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 213380 kb
Host smart-82178ade-8e2e-4312-9ba8-2b1fb4ddc3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502542487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1502542487
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.4054611009
Short name T225
Test name
Test status
Simulation time 86878252 ps
CPU time 0.72 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 205076 kb
Host smart-0f1c0026-960e-41fa-8e3e-2ce2860e4355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054611009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4054611009
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.614436674
Short name T247
Test name
Test status
Simulation time 1751192301 ps
CPU time 3.71 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:22 PM PDT 24
Peak memory 205096 kb
Host smart-7bbdf456-98c1-46d5-a22e-b1c921c99364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614436674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.614436674
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.562981512
Short name T287
Test name
Test status
Simulation time 148841347 ps
CPU time 0.72 seconds
Started Aug 14 04:33:26 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 204964 kb
Host smart-00b25e84-630c-4461-b3af-d692309f33c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562981512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.562981512
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2113697579
Short name T167
Test name
Test status
Simulation time 2059005033 ps
CPU time 2.35 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 205088 kb
Host smart-690cd690-b203-4f06-b49e-8d37de4ba658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113697579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2113697579
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1864505831
Short name T108
Test name
Test status
Simulation time 40720020 ps
CPU time 0.76 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 204932 kb
Host smart-435fc032-744d-4c40-9321-8b9832fa0001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864505831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1864505831
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2140727523
Short name T173
Test name
Test status
Simulation time 4987253611 ps
CPU time 15.65 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:33 PM PDT 24
Peak memory 213348 kb
Host smart-f70c70a4-8cda-437a-876e-138d68093fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140727523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2140727523
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1987924739
Short name T31
Test name
Test status
Simulation time 70500295 ps
CPU time 0.74 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 204920 kb
Host smart-54fdefaf-1ded-45c9-864a-b987109e4fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987924739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1987924739
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1167969224
Short name T155
Test name
Test status
Simulation time 61985337 ps
CPU time 0.71 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 204956 kb
Host smart-20c48fd9-c596-48b5-bc5e-9cd445119feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167969224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1167969224
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1743249906
Short name T79
Test name
Test status
Simulation time 1690029795 ps
CPU time 3.13 seconds
Started Aug 14 04:33:38 PM PDT 24
Finished Aug 14 04:33:41 PM PDT 24
Peak memory 204996 kb
Host smart-38ab14d4-128e-467c-ab6b-724f24992159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743249906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1743249906
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1877224879
Short name T206
Test name
Test status
Simulation time 61198529 ps
CPU time 0.75 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 204960 kb
Host smart-e180ff9d-3479-4d3a-9447-8d038d578ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877224879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1877224879
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1994174635
Short name T28
Test name
Test status
Simulation time 4934568011 ps
CPU time 4.87 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 205080 kb
Host smart-0bfce660-52b2-4bde-87c0-8ee617464421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994174635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1994174635
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.328060029
Short name T265
Test name
Test status
Simulation time 37169928 ps
CPU time 0.7 seconds
Started Aug 14 04:33:25 PM PDT 24
Finished Aug 14 04:33:26 PM PDT 24
Peak memory 204912 kb
Host smart-f7bd2d49-2cea-4394-b2da-788cdabfaa02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328060029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.328060029
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2897191017
Short name T153
Test name
Test status
Simulation time 135472757 ps
CPU time 0.79 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 204956 kb
Host smart-b9b6fa8a-747b-4d29-b2bf-9acd99c906d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897191017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2897191017
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.452010527
Short name T250
Test name
Test status
Simulation time 21447433863 ps
CPU time 28.45 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:39 PM PDT 24
Peak memory 213656 kb
Host smart-b7d0096b-9304-4bf3-97ad-1b7ab005953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452010527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.452010527
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3548660056
Short name T228
Test name
Test status
Simulation time 2643139286 ps
CPU time 8.13 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 205444 kb
Host smart-24e1f29d-6a36-4227-8bf8-3a25383a19fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548660056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3548660056
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_buffered_enable.1875955222
Short name T282
Test name
Test status
Simulation time 252607841 ps
CPU time 1.06 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 225840 kb
Host smart-d04ef554-6991-4008-a87f-ecb79fbb4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875955222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.1875955222
Directory /workspace/3.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1273347344
Short name T289
Test name
Test status
Simulation time 4016377752 ps
CPU time 9.19 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 205304 kb
Host smart-684459a4-aced-401a-9035-9a553f7515d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1273347344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1273347344
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.3680823310
Short name T234
Test name
Test status
Simulation time 499804679 ps
CPU time 1.96 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:07 PM PDT 24
Peak memory 204780 kb
Host smart-136dee0d-4c1a-4642-9f89-32b342505f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680823310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3680823310
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3246648469
Short name T214
Test name
Test status
Simulation time 209015507 ps
CPU time 0.84 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 204932 kb
Host smart-b7649fb3-2504-460a-8361-45ecb54ab4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246648469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3246648469
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3899953895
Short name T224
Test name
Test status
Simulation time 3816780516 ps
CPU time 2.01 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 205296 kb
Host smart-34889af9-6c0c-4345-93ba-bb0ddef9420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899953895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3899953895
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2341907219
Short name T33
Test name
Test status
Simulation time 1400639718 ps
CPU time 1.38 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 229208 kb
Host smart-4479cb7f-30d4-4863-8ed9-e3dd85ea8e91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341907219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2341907219
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.4134881625
Short name T56
Test name
Test status
Simulation time 105334662 ps
CPU time 0.85 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:00 PM PDT 24
Peak memory 213280 kb
Host smart-166205cc-770f-4c3b-8cd9-66b58876590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134881625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.4134881625
Directory /workspace/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3899589020
Short name T23
Test name
Test status
Simulation time 4485985865 ps
CPU time 7.32 seconds
Started Aug 14 04:32:57 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 205048 kb
Host smart-e8a6cd9e-fdb2-4489-8444-92f9d0406415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899589020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3899589020
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.1251824949
Short name T43
Test name
Test status
Simulation time 2056891061 ps
CPU time 16.33 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:28 PM PDT 24
Peak memory 221280 kb
Host smart-1a098eb5-cb3a-401e-be4b-40bf9ae79176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251824949 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.1251824949
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2074796017
Short name T276
Test name
Test status
Simulation time 126739244 ps
CPU time 1.03 seconds
Started Aug 14 04:33:26 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 204944 kb
Host smart-b2030cc1-4ad0-460c-90f6-2789bd958ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074796017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2074796017
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1317001434
Short name T25
Test name
Test status
Simulation time 3166424500 ps
CPU time 4.58 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205052 kb
Host smart-01c98998-e57f-4062-b930-56c5c98e5c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317001434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1317001434
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1799284683
Short name T262
Test name
Test status
Simulation time 34964336 ps
CPU time 0.8 seconds
Started Aug 14 04:33:25 PM PDT 24
Finished Aug 14 04:33:26 PM PDT 24
Peak memory 205032 kb
Host smart-edbe9420-d722-4663-b6eb-e0b665f588bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799284683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1799284683
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3401184212
Short name T186
Test name
Test status
Simulation time 3954958297 ps
CPU time 12.06 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 205024 kb
Host smart-258cb4db-bffc-47c0-acc1-182fc3ced195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401184212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3401184212
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1313419336
Short name T218
Test name
Test status
Simulation time 64785933 ps
CPU time 0.69 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 204820 kb
Host smart-756ee87d-8952-439d-bc84-7cdb0f197c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313419336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1313419336
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2038674745
Short name T14
Test name
Test status
Simulation time 2206251684 ps
CPU time 3.95 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205296 kb
Host smart-4afa97a6-c3a7-4b18-a832-0980ded8ced0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038674745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2038674745
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3362760380
Short name T257
Test name
Test status
Simulation time 44673318 ps
CPU time 0.77 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 204960 kb
Host smart-8a7d6be3-0818-4773-b888-e694e9e0cbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362760380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3362760380
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3233206735
Short name T292
Test name
Test status
Simulation time 2968931844 ps
CPU time 2.58 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 213216 kb
Host smart-4ef0d13e-2576-4b32-9410-a87284710b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233206735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3233206735
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.927325386
Short name T321
Test name
Test status
Simulation time 124437305 ps
CPU time 0.91 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:15 PM PDT 24
Peak memory 205036 kb
Host smart-a668553f-a01e-45cc-9e70-67db37ee29f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927325386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.927325386
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1001949731
Short name T169
Test name
Test status
Simulation time 3083308307 ps
CPU time 5.13 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:22 PM PDT 24
Peak memory 213464 kb
Host smart-baaa58d8-d1bd-42f9-8d5d-5a9b5c48a98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001949731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1001949731
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1926365633
Short name T162
Test name
Test status
Simulation time 75222292 ps
CPU time 0.89 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 205304 kb
Host smart-94456a5f-aeaf-4ae0-8aed-c998e1984d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926365633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1926365633
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2623513849
Short name T180
Test name
Test status
Simulation time 3280802324 ps
CPU time 3.78 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 205084 kb
Host smart-ef1ce6f0-8250-463f-ad99-1727c857e158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623513849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2623513849
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3900550368
Short name T293
Test name
Test status
Simulation time 52935629 ps
CPU time 0.7 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 205060 kb
Host smart-7c584e23-0e2f-434a-8ab3-c3e6e263801c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900550368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3900550368
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.697101092
Short name T183
Test name
Test status
Simulation time 2193174230 ps
CPU time 1.94 seconds
Started Aug 14 04:33:28 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 204872 kb
Host smart-0ace3a64-cc87-4631-942e-0716545db0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697101092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.697101092
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.411929149
Short name T152
Test name
Test status
Simulation time 210004746 ps
CPU time 0.69 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 204904 kb
Host smart-1f0e7f10-c0df-48b4-b02a-c848c126a13b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411929149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.411929149
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.665848281
Short name T190
Test name
Test status
Simulation time 1486937862 ps
CPU time 4.79 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205008 kb
Host smart-3eb0a26a-e208-45b8-922f-6c1380d164f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665848281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.665848281
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3307563958
Short name T233
Test name
Test status
Simulation time 52518524 ps
CPU time 0.7 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 204964 kb
Host smart-eee17f8f-1762-4374-ab63-59b20988dc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307563958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3307563958
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2055363546
Short name T178
Test name
Test status
Simulation time 3091847614 ps
CPU time 4.64 seconds
Started Aug 14 04:33:26 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 205080 kb
Host smart-12aeabad-c00c-4f9a-9826-8a00b3ff41d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055363546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2055363546
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1954012104
Short name T232
Test name
Test status
Simulation time 95843551 ps
CPU time 0.88 seconds
Started Aug 14 04:33:26 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 204912 kb
Host smart-1c91e880-b853-4cd6-8a1d-13d5180e587f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954012104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1954012104
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1780802742
Short name T302
Test name
Test status
Simulation time 46774438 ps
CPU time 0.77 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 205028 kb
Host smart-1acbfa11-f445-4663-8a89-5ee13e9c87c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780802742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1780802742
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2608746794
Short name T313
Test name
Test status
Simulation time 14110022366 ps
CPU time 12.3 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 213404 kb
Host smart-fc6ab6b4-e8bc-47c7-9572-6d4b946eb6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608746794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2608746794
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3757943036
Short name T215
Test name
Test status
Simulation time 4646268623 ps
CPU time 9.15 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 221684 kb
Host smart-a98a7220-7450-4cbc-afb5-695f1288d922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757943036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3757943036
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_buffered_enable.1958495229
Short name T47
Test name
Test status
Simulation time 595341110 ps
CPU time 2.29 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:26 PM PDT 24
Peak memory 225536 kb
Host smart-4d7e2a1e-7be8-4056-95e0-9ac3e8ee822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958495229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.1958495229
Directory /workspace/4.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2114024488
Short name T211
Test name
Test status
Simulation time 1814268088 ps
CPU time 3.44 seconds
Started Aug 14 04:32:51 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 205240 kb
Host smart-25c2a319-ce95-4b50-8f09-9ad2da905f1d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114024488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2114024488
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3064693092
Short name T161
Test name
Test status
Simulation time 425937260 ps
CPU time 1.7 seconds
Started Aug 14 04:33:08 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 204816 kb
Host smart-e42aa5b3-71e6-423b-acf8-95ca879cf8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064693092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3064693092
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2674765325
Short name T317
Test name
Test status
Simulation time 138350540 ps
CPU time 0.92 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 203840 kb
Host smart-1088a66d-e077-441d-a7f5-a6b693ea824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674765325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2674765325
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2019281584
Short name T212
Test name
Test status
Simulation time 4698973250 ps
CPU time 14.13 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 205384 kb
Host smart-fc51b68e-63e1-4ce4-a9e9-d61288477df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019281584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2019281584
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3182628024
Short name T34
Test name
Test status
Simulation time 2920419367 ps
CPU time 3.2 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 229192 kb
Host smart-d1471f84-0359-40f3-91c1-a81d3858efde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182628024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3182628024
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2168824664
Short name T45
Test name
Test status
Simulation time 4406275776 ps
CPU time 64.97 seconds
Started Aug 14 04:33:25 PM PDT 24
Finished Aug 14 04:34:30 PM PDT 24
Peak memory 221696 kb
Host smart-c6a053dc-7f62-44e2-92d4-3b151ace801d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168824664 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2168824664
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1642474374
Short name T204
Test name
Test status
Simulation time 38180857 ps
CPU time 0.71 seconds
Started Aug 14 04:33:35 PM PDT 24
Finished Aug 14 04:33:36 PM PDT 24
Peak memory 205032 kb
Host smart-c708cb68-2233-4d7b-adf5-b1e76d7a1fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642474374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1642474374
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2930419408
Short name T171
Test name
Test status
Simulation time 1989888670 ps
CPU time 3.42 seconds
Started Aug 14 04:33:25 PM PDT 24
Finished Aug 14 04:33:29 PM PDT 24
Peak memory 205148 kb
Host smart-f07dfc77-8c96-4cbe-b9ef-0a2a5371fd7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930419408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2930419408
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.370546696
Short name T66
Test name
Test status
Simulation time 153904010 ps
CPU time 0.76 seconds
Started Aug 14 04:33:39 PM PDT 24
Finished Aug 14 04:33:39 PM PDT 24
Peak memory 204952 kb
Host smart-49f732f6-82dc-4abb-bd9d-418b4e32d316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370546696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.370546696
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3962540792
Short name T5
Test name
Test status
Simulation time 1362927336 ps
CPU time 2.83 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:22 PM PDT 24
Peak memory 213252 kb
Host smart-c43628be-4ca2-49fd-addb-2d4e8e45723a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962540792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3962540792
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.72215188
Short name T128
Test name
Test status
Simulation time 163679516 ps
CPU time 0.79 seconds
Started Aug 14 04:33:29 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 204936 kb
Host smart-b8ad1643-db5d-4319-aa5a-ac33c4282e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72215188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.72215188
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1611821164
Short name T72
Test name
Test status
Simulation time 2414028039 ps
CPU time 7.68 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 205052 kb
Host smart-a5775532-edac-4f3f-b545-1e98c059c2e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611821164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1611821164
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1296088830
Short name T160
Test name
Test status
Simulation time 119658215 ps
CPU time 1 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 204956 kb
Host smart-6f48554f-eb79-4939-974b-0ca99dc68c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296088830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1296088830
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.4151531218
Short name T181
Test name
Test status
Simulation time 7634248644 ps
CPU time 22.42 seconds
Started Aug 14 04:33:21 PM PDT 24
Finished Aug 14 04:33:43 PM PDT 24
Peak memory 205136 kb
Host smart-d2cd5f7a-1b54-4cea-9c9b-4160e311b65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151531218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.4151531218
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1777794165
Short name T213
Test name
Test status
Simulation time 109535697 ps
CPU time 0.71 seconds
Started Aug 14 04:33:22 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 204872 kb
Host smart-ba0d3b82-ba1b-4944-802d-1894b5e4f784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777794165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1777794165
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.4104440338
Short name T325
Test name
Test status
Simulation time 11297612217 ps
CPU time 16.93 seconds
Started Aug 14 04:33:18 PM PDT 24
Finished Aug 14 04:33:36 PM PDT 24
Peak memory 205076 kb
Host smart-995b1f24-b7aa-4f09-bced-bdc67aba142c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104440338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4104440338
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2449831211
Short name T246
Test name
Test status
Simulation time 109149577 ps
CPU time 0.97 seconds
Started Aug 14 04:33:27 PM PDT 24
Finished Aug 14 04:33:28 PM PDT 24
Peak memory 205072 kb
Host smart-c0211b42-227a-43d0-b61d-5b8371b51870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449831211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2449831211
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.844670940
Short name T18
Test name
Test status
Simulation time 2772716010 ps
CPU time 4.72 seconds
Started Aug 14 04:33:38 PM PDT 24
Finished Aug 14 04:33:43 PM PDT 24
Peak memory 205044 kb
Host smart-490e3ec0-606f-499e-b5f5-dc889591d01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844670940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.844670940
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3974308181
Short name T236
Test name
Test status
Simulation time 91366582 ps
CPU time 0.93 seconds
Started Aug 14 04:33:13 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 204932 kb
Host smart-febcfbc6-a460-44c3-bc59-b2cecfcbbd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974308181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3974308181
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2035008285
Short name T129
Test name
Test status
Simulation time 1529351047 ps
CPU time 3.38 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 205184 kb
Host smart-75def942-ede9-4f70-a890-9d1f3e30e110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035008285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2035008285
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.540966225
Short name T68
Test name
Test status
Simulation time 194832618 ps
CPU time 0.72 seconds
Started Aug 14 04:33:30 PM PDT 24
Finished Aug 14 04:33:31 PM PDT 24
Peak memory 204928 kb
Host smart-c53a257c-48a3-4333-af4c-a66e6548101f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540966225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.540966225
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3407214743
Short name T82
Test name
Test status
Simulation time 2861980603 ps
CPU time 2.89 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 212108 kb
Host smart-a5bcdefe-0363-46e9-bd65-797b31d9d23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407214743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3407214743
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2777861151
Short name T32
Test name
Test status
Simulation time 48228447 ps
CPU time 0.77 seconds
Started Aug 14 04:33:25 PM PDT 24
Finished Aug 14 04:33:26 PM PDT 24
Peak memory 204948 kb
Host smart-8662c5e3-984b-4254-9050-4847dd3a32b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777861151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2777861151
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3320990311
Short name T295
Test name
Test status
Simulation time 8270008411 ps
CPU time 7.46 seconds
Started Aug 14 04:33:40 PM PDT 24
Finished Aug 14 04:33:48 PM PDT 24
Peak memory 213256 kb
Host smart-14bc6768-5cfb-4b16-b001-9c056d3e296a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320990311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3320990311
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4249518929
Short name T323
Test name
Test status
Simulation time 63234116 ps
CPU time 0.8 seconds
Started Aug 14 04:33:39 PM PDT 24
Finished Aug 14 04:33:45 PM PDT 24
Peak memory 204908 kb
Host smart-3d6c89f5-ee9a-4c6b-95d0-3edfb3755a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249518929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4249518929
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2340583240
Short name T235
Test name
Test status
Simulation time 4695616018 ps
CPU time 6.36 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:34:04 PM PDT 24
Peak memory 213192 kb
Host smart-b85d2f20-040d-462f-9849-991f50c2396e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340583240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2340583240
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2450855876
Short name T216
Test name
Test status
Simulation time 115326930 ps
CPU time 0.94 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 204928 kb
Host smart-66b0d333-1b5b-43d9-94b4-debbd6886392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450855876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2450855876
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1363101574
Short name T318
Test name
Test status
Simulation time 7601662833 ps
CPU time 3.33 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205360 kb
Host smart-076b99dd-7c46-4577-9df3-1e95097b3d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363101574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1363101574
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.247516401
Short name T179
Test name
Test status
Simulation time 2289215536 ps
CPU time 7.38 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 213504 kb
Host smart-b8589982-cd34-46f6-b3c9-a54c28124ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247516401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.247516401
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_buffered_enable.3978741150
Short name T123
Test name
Test status
Simulation time 171361157 ps
CPU time 0.98 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 226392 kb
Host smart-72ff3169-1602-4c64-85a3-d7666722a550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978741150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.3978741150
Directory /workspace/5.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.723847916
Short name T172
Test name
Test status
Simulation time 1943674013 ps
CPU time 3.35 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 205236 kb
Host smart-4ca61835-fc35-44f9-8892-dd764c9ec17b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723847916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.723847916
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3831035520
Short name T40
Test name
Test status
Simulation time 1062916777 ps
CPU time 2.26 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 204816 kb
Host smart-a9eac816-05d9-463a-84f5-1a1af821f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831035520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3831035520
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3348185640
Short name T272
Test name
Test status
Simulation time 2730382938 ps
CPU time 4.41 seconds
Started Aug 14 04:33:00 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 205248 kb
Host smart-b3fb3323-c47a-4a7f-b48c-b904707c10cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348185640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3348185640
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3605756714
Short name T285
Test name
Test status
Simulation time 1752092807 ps
CPU time 3.36 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:12 PM PDT 24
Peak memory 213164 kb
Host smart-ce0915cb-b8a3-4072-af9e-0752e95fc27e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605756714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3605756714
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.633590973
Short name T255
Test name
Test status
Simulation time 158463027 ps
CPU time 0.98 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:11 PM PDT 24
Peak memory 205052 kb
Host smart-9d15a654-0934-49e4-b9a0-f9a00329515a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633590973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.633590973
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2160579920
Short name T286
Test name
Test status
Simulation time 4043297250 ps
CPU time 3.97 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:13 PM PDT 24
Peak memory 213516 kb
Host smart-7d2ef7ca-5a4d-4b13-aec8-852bc5718b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160579920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2160579920
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.199014562
Short name T322
Test name
Test status
Simulation time 1333993778 ps
CPU time 2.71 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 205276 kb
Host smart-3a3f081a-672f-430c-b232-7a4aef249a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199014562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.199014562
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_buffered_enable.749956483
Short name T288
Test name
Test status
Simulation time 358261305 ps
CPU time 1.04 seconds
Started Aug 14 04:33:10 PM PDT 24
Finished Aug 14 04:33:12 PM PDT 24
Peak memory 234196 kb
Host smart-d130991e-3762-4aaa-bf6c-87cc3754320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749956483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.749956483
Directory /workspace/6.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3378871464
Short name T253
Test name
Test status
Simulation time 7882120048 ps
CPU time 6.83 seconds
Started Aug 14 04:33:07 PM PDT 24
Finished Aug 14 04:33:14 PM PDT 24
Peak memory 213516 kb
Host smart-2992e7e5-870e-4204-9559-19b757c97dbc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378871464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3378871464
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.1335090920
Short name T252
Test name
Test status
Simulation time 962757797 ps
CPU time 1.48 seconds
Started Aug 14 04:33:02 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 204804 kb
Host smart-39a20129-fa4f-49e5-8294-3942f2a87164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335090920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1335090920
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3480388526
Short name T130
Test name
Test status
Simulation time 7170957627 ps
CPU time 21.27 seconds
Started Aug 14 04:33:09 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 205352 kb
Host smart-11bd3c0e-3af2-46f6-8b15-8df478808ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480388526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3480388526
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2448278010
Short name T303
Test name
Test status
Simulation time 3726542828 ps
CPU time 11.82 seconds
Started Aug 14 04:33:06 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 205048 kb
Host smart-d07ef682-0d8c-42a4-be78-9654670269ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448278010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2448278010
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.787768473
Short name T22
Test name
Test status
Simulation time 6088848555 ps
CPU time 60.07 seconds
Started Aug 14 04:33:05 PM PDT 24
Finished Aug 14 04:34:06 PM PDT 24
Peak memory 221536 kb
Host smart-d4b5e2fa-3e7a-4d20-beee-f4cbe021643c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787768473 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.787768473
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2214881105
Short name T208
Test name
Test status
Simulation time 149825939 ps
CPU time 0.84 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 204928 kb
Host smart-83af3481-5ea9-4c3d-8710-f1c0b7a1a300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214881105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2214881105
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.775431764
Short name T127
Test name
Test status
Simulation time 3385438733 ps
CPU time 4.39 seconds
Started Aug 14 04:33:14 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 214904 kb
Host smart-2701e016-e6ee-48bd-b65d-4cb2a0a4b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775431764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.775431764
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1021195462
Short name T296
Test name
Test status
Simulation time 5829163194 ps
CPU time 16.34 seconds
Started Aug 14 04:33:24 PM PDT 24
Finished Aug 14 04:33:41 PM PDT 24
Peak memory 213508 kb
Host smart-82c968c3-5d69-4244-9f9d-a0f9f3d9e06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021195462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1021195462
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1379510469
Short name T104
Test name
Test status
Simulation time 10152015660 ps
CPU time 9.64 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 213564 kb
Host smart-6cfcf4ab-5984-4b0f-a418-39e5dabe4c31
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379510469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1379510469
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.2426961264
Short name T44
Test name
Test status
Simulation time 1466037240 ps
CPU time 1.14 seconds
Started Aug 14 04:33:08 PM PDT 24
Finished Aug 14 04:33:09 PM PDT 24
Peak memory 204764 kb
Host smart-ef0e2720-f453-4cc8-8a37-266fa8126538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426961264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2426961264
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3220864152
Short name T269
Test name
Test status
Simulation time 1013729437 ps
CPU time 1.5 seconds
Started Aug 14 04:33:26 PM PDT 24
Finished Aug 14 04:33:28 PM PDT 24
Peak memory 205324 kb
Host smart-a125bfed-a872-45b6-a0b7-6fd2d054da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220864152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3220864152
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.594459548
Short name T10
Test name
Test status
Simulation time 4536313421 ps
CPU time 7.56 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205076 kb
Host smart-8526e705-6408-4e13-a62f-16843a88e283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594459548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.594459548
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1044266334
Short name T88
Test name
Test status
Simulation time 3582650546 ps
CPU time 60.44 seconds
Started Aug 14 04:33:12 PM PDT 24
Finished Aug 14 04:34:12 PM PDT 24
Peak memory 229764 kb
Host smart-01b01536-72a9-4d92-95ab-342c44a7e58e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044266334 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.1044266334
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.4104278440
Short name T223
Test name
Test status
Simulation time 38626400 ps
CPU time 0.76 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:17 PM PDT 24
Peak memory 204920 kb
Host smart-e1797285-5b67-4e6e-ba12-1d1749d71241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104278440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4104278440
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2246059840
Short name T227
Test name
Test status
Simulation time 5196134581 ps
CPU time 17.12 seconds
Started Aug 14 04:33:25 PM PDT 24
Finished Aug 14 04:33:42 PM PDT 24
Peak memory 213572 kb
Host smart-294b4c71-8b38-44af-be1d-f9bc9c10abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246059840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2246059840
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3123515341
Short name T174
Test name
Test status
Simulation time 8457967899 ps
CPU time 12.53 seconds
Started Aug 14 04:33:08 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 213560 kb
Host smart-141b08ee-5587-41bd-929b-dbb14b315f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123515341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3123515341
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_buffered_enable.2556815666
Short name T59
Test name
Test status
Simulation time 109402149 ps
CPU time 1 seconds
Started Aug 14 04:33:04 PM PDT 24
Finished Aug 14 04:33:05 PM PDT 24
Peak memory 225684 kb
Host smart-a1112dd0-109d-42ae-a3d1-158e514dddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556815666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.2556815666
Directory /workspace/8.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3646829649
Short name T65
Test name
Test status
Simulation time 7755753780 ps
CPU time 7.6 seconds
Started Aug 14 04:33:16 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 205308 kb
Host smart-0100e60a-1577-4d43-ae89-5e60c4902415
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646829649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3646829649
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.436440005
Short name T159
Test name
Test status
Simulation time 1631359788 ps
CPU time 2.15 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205316 kb
Host smart-58857c5c-c0b4-4676-8c8b-e93e6dfe2338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436440005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.436440005
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3549238205
Short name T283
Test name
Test status
Simulation time 1120274863 ps
CPU time 3.85 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205004 kb
Host smart-3f998eb1-6dea-410e-a650-f8a7b943ed57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549238205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3549238205
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2770675055
Short name T273
Test name
Test status
Simulation time 50762484381 ps
CPU time 65.3 seconds
Started Aug 14 04:33:11 PM PDT 24
Finished Aug 14 04:34:16 PM PDT 24
Peak memory 213552 kb
Host smart-bfc9d189-fb20-4148-82b7-3f8ecbc3246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770675055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2770675055
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2724854388
Short name T177
Test name
Test status
Simulation time 1350083289 ps
CPU time 1.71 seconds
Started Aug 14 04:33:17 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 205368 kb
Host smart-e9a86e9c-1073-4433-9ae0-d303d36e5e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724854388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2724854388
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_buffered_enable.3575494747
Short name T103
Test name
Test status
Simulation time 428363220 ps
CPU time 1.12 seconds
Started Aug 14 04:33:15 PM PDT 24
Finished Aug 14 04:33:16 PM PDT 24
Peak memory 225888 kb
Host smart-bb67e2db-54d4-4eaa-8384-f1a91292d945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575494747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.3575494747
Directory /workspace/9.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1201820130
Short name T249
Test name
Test status
Simulation time 590270205 ps
CPU time 1.19 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:25 PM PDT 24
Peak memory 205300 kb
Host smart-43cc234e-dc9f-49e6-864c-3a612983c527
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201820130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1201820130
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1760383757
Short name T111
Test name
Test status
Simulation time 2152493703 ps
CPU time 6.47 seconds
Started Aug 14 04:33:01 PM PDT 24
Finished Aug 14 04:33:08 PM PDT 24
Peak memory 205248 kb
Host smart-8cef873a-ff3e-46e5-beb2-a38e80c21c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760383757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1760383757
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1409277929
Short name T299
Test name
Test status
Simulation time 8723759095 ps
CPU time 18.58 seconds
Started Aug 14 04:33:08 PM PDT 24
Finished Aug 14 04:33:27 PM PDT 24
Peak memory 205072 kb
Host smart-800bec5f-2939-4241-ac94-8d995252607d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409277929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1409277929
Directory /workspace/9.rv_dm_stress_all/latest
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