SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
88.09 | 96.32 | 89.53 | 92.10 | 93.33 | 90.44 | 98.74 | 56.17 |
T319 | /workspace/coverage/default/35.rv_dm_stress_all.1488501460 | Aug 15 04:40:45 PM PDT 24 | Aug 15 04:40:48 PM PDT 24 | 5291597182 ps | ||
T48 | /workspace/coverage/default/33.rv_dm_stress_all.3617226790 | Aug 15 04:40:47 PM PDT 24 | Aug 15 04:40:50 PM PDT 24 | 1671414898 ps | ||
T320 | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.713151202 | Aug 15 04:40:31 PM PDT 24 | Aug 15 04:40:33 PM PDT 24 | 685534642 ps | ||
T321 | /workspace/coverage/default/11.rv_dm_sba_tl_access.3803615809 | Aug 15 04:40:24 PM PDT 24 | Aug 15 04:40:34 PM PDT 24 | 6475285575 ps | ||
T322 | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1424405635 | Aug 15 04:39:20 PM PDT 24 | Aug 15 04:39:26 PM PDT 24 | 20670219471 ps | ||
T323 | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2428462030 | Aug 15 04:40:22 PM PDT 24 | Aug 15 04:40:28 PM PDT 24 | 3260439879 ps | ||
T324 | /workspace/coverage/default/6.rv_dm_buffered_enable.1084489520 | Aug 15 04:40:12 PM PDT 24 | Aug 15 04:40:13 PM PDT 24 | 142470142 ps | ||
T325 | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3035641564 | Aug 15 04:39:47 PM PDT 24 | Aug 15 04:39:48 PM PDT 24 | 114237888 ps | ||
T326 | /workspace/coverage/default/8.rv_dm_stress_all.742383958 | Aug 15 04:40:15 PM PDT 24 | Aug 15 04:40:21 PM PDT 24 | 4654262944 ps | ||
T151 | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.4003450523 | Aug 15 04:39:41 PM PDT 24 | Aug 15 04:39:43 PM PDT 24 | 3735758740 ps | ||
T327 | /workspace/coverage/default/3.rv_dm_sba_tl_access.990741397 | Aug 15 04:39:55 PM PDT 24 | Aug 15 04:40:05 PM PDT 24 | 11195585466 ps | ||
T328 | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.213611418 | Aug 15 04:39:49 PM PDT 24 | Aug 15 04:39:56 PM PDT 24 | 4217252008 ps | ||
T329 | /workspace/coverage/default/41.rv_dm_stress_all.2617193741 | Aug 15 04:40:43 PM PDT 24 | Aug 15 04:40:54 PM PDT 24 | 3123744195 ps | ||
T330 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2919865737 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:37:16 PM PDT 24 | 42002231440 ps | ||
T114 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1464294523 | Aug 15 04:35:13 PM PDT 24 | Aug 15 04:35:20 PM PDT 24 | 2260933408 ps | ||
T331 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2637954569 | Aug 15 04:35:24 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 104297949 ps | ||
T147 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1565354818 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 1717951876 ps | ||
T103 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1829353498 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:35 PM PDT 24 | 117166696 ps | ||
T332 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.109612483 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:43 PM PDT 24 | 265744564 ps | ||
T333 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.370339671 | Aug 15 04:35:54 PM PDT 24 | Aug 15 04:35:59 PM PDT 24 | 1235683414 ps | ||
T104 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2479968521 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:46 PM PDT 24 | 692842905 ps | ||
T334 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.795760670 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:37:52 PM PDT 24 | 83880523065 ps | ||
T335 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3301567789 | Aug 15 04:35:32 PM PDT 24 | Aug 15 04:36:04 PM PDT 24 | 41330048779 ps | ||
T105 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2469723479 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:29 PM PDT 24 | 433363942 ps | ||
T106 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3946065718 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:39 PM PDT 24 | 194154525 ps | ||
T86 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1774442505 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:36:09 PM PDT 24 | 14168153473 ps | ||
T95 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3535720668 | Aug 15 04:35:14 PM PDT 24 | Aug 15 04:35:17 PM PDT 24 | 265435054 ps | ||
T107 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4134799472 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:28 PM PDT 24 | 383524758 ps | ||
T336 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2623139225 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:35:20 PM PDT 24 | 2122037814 ps | ||
T337 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.337938166 | Aug 15 04:35:18 PM PDT 24 | Aug 15 04:35:36 PM PDT 24 | 11927041478 ps | ||
T141 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3060973758 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 352160313 ps | ||
T99 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.161571914 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:26 PM PDT 24 | 515791880 ps | ||
T338 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4197108970 | Aug 15 04:35:14 PM PDT 24 | Aug 15 04:35:17 PM PDT 24 | 84574490 ps | ||
T339 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1516702927 | Aug 15 04:35:15 PM PDT 24 | Aug 15 04:39:45 PM PDT 24 | 111927573449 ps | ||
T148 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.566154132 | Aug 15 04:35:32 PM PDT 24 | Aug 15 04:36:07 PM PDT 24 | 6362109293 ps | ||
T100 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1633532139 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:35:20 PM PDT 24 | 923834219 ps | ||
T340 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3822220241 | Aug 15 04:35:50 PM PDT 24 | Aug 15 04:35:52 PM PDT 24 | 1027679203 ps | ||
T117 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.585230117 | Aug 15 04:35:14 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 1774387882 ps | ||
T142 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.209525838 | Aug 15 04:35:29 PM PDT 24 | Aug 15 04:35:50 PM PDT 24 | 8056700784 ps | ||
T101 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2191532334 | Aug 15 04:35:18 PM PDT 24 | Aug 15 04:35:20 PM PDT 24 | 567471855 ps | ||
T143 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3273771585 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 305598667 ps | ||
T341 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2205178526 | Aug 15 04:35:59 PM PDT 24 | Aug 15 04:36:00 PM PDT 24 | 110913984 ps | ||
T144 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1577481894 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:40 PM PDT 24 | 2521737368 ps | ||
T108 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1224034878 | Aug 15 04:35:46 PM PDT 24 | Aug 15 04:35:54 PM PDT 24 | 2202809450 ps | ||
T342 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3770504908 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:49 PM PDT 24 | 4696794159 ps | ||
T343 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.620168975 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 490329556 ps | ||
T344 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1919173932 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 246762222 ps | ||
T172 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1917963835 | Aug 15 04:35:51 PM PDT 24 | Aug 15 04:36:11 PM PDT 24 | 1803879993 ps | ||
T345 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3805749594 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:34 PM PDT 24 | 221320878 ps | ||
T346 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3698550507 | Aug 15 04:35:24 PM PDT 24 | Aug 15 04:35:27 PM PDT 24 | 121032080 ps | ||
T347 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.692060970 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:58 PM PDT 24 | 28629676721 ps | ||
T348 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3407535937 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:40 PM PDT 24 | 3028302231 ps | ||
T109 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1875877548 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:28 PM PDT 24 | 120204470 ps | ||
T349 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1624974388 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:35:18 PM PDT 24 | 289547782 ps | ||
T110 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1124630732 | Aug 15 04:35:21 PM PDT 24 | Aug 15 04:35:58 PM PDT 24 | 16731153609 ps | ||
T111 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2354509236 | Aug 15 04:35:47 PM PDT 24 | Aug 15 04:35:52 PM PDT 24 | 3311162562 ps | ||
T350 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1027150665 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:36:14 PM PDT 24 | 13225931109 ps | ||
T351 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.585603373 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 147450902 ps | ||
T87 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.931318726 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:36:13 PM PDT 24 | 41517393366 ps | ||
T112 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3288349230 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:36 PM PDT 24 | 77544470 ps | ||
T352 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3715138847 | Aug 15 04:35:31 PM PDT 24 | Aug 15 04:35:32 PM PDT 24 | 64958422 ps | ||
T118 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1490386925 | Aug 15 04:35:18 PM PDT 24 | Aug 15 04:35:27 PM PDT 24 | 745920520 ps | ||
T115 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2847742685 | Aug 15 04:35:42 PM PDT 24 | Aug 15 04:35:48 PM PDT 24 | 3807584307 ps | ||
T353 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4109703841 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:26 PM PDT 24 | 113248689 ps | ||
T135 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.656441392 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 178959861 ps | ||
T136 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2110671826 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:44 PM PDT 24 | 3321123531 ps | ||
T354 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3989922417 | Aug 15 04:35:13 PM PDT 24 | Aug 15 04:35:14 PM PDT 24 | 194080843 ps | ||
T355 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3713389257 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:35:17 PM PDT 24 | 78652561 ps | ||
T356 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1087622426 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:37 PM PDT 24 | 142853137 ps | ||
T125 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1763374373 | Aug 15 04:35:18 PM PDT 24 | Aug 15 04:35:21 PM PDT 24 | 186153926 ps | ||
T357 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2758639133 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:55 PM PDT 24 | 14306175064 ps | ||
T358 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1485447043 | Aug 15 04:35:46 PM PDT 24 | Aug 15 04:35:50 PM PDT 24 | 352244008 ps | ||
T359 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1798881213 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:23 PM PDT 24 | 96852762 ps | ||
T98 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3163657698 | Aug 15 04:35:24 PM PDT 24 | Aug 15 04:35:32 PM PDT 24 | 991628250 ps | ||
T360 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.587584721 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:40:50 PM PDT 24 | 238656537094 ps | ||
T176 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2407799798 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:36:07 PM PDT 24 | 1677303477 ps | ||
T361 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.515709142 | Aug 15 04:36:07 PM PDT 24 | Aug 15 04:36:14 PM PDT 24 | 9252460492 ps | ||
T137 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2186893354 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 557963092 ps | ||
T173 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3069432733 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 4106632518 ps | ||
T362 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.796045443 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:46 PM PDT 24 | 1480403942 ps | ||
T363 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3915696767 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:54 PM PDT 24 | 8816871878 ps | ||
T364 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.331397199 | Aug 15 04:35:32 PM PDT 24 | Aug 15 04:37:13 PM PDT 24 | 4695999719 ps | ||
T96 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2686011639 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 203551026 ps | ||
T138 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.849873491 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 315907100 ps | ||
T177 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3834102424 | Aug 15 04:35:12 PM PDT 24 | Aug 15 04:35:36 PM PDT 24 | 4980956566 ps | ||
T365 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2242224924 | Aug 15 04:35:46 PM PDT 24 | Aug 15 04:35:49 PM PDT 24 | 2663412354 ps | ||
T366 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3279520207 | Aug 15 04:35:10 PM PDT 24 | Aug 15 04:35:12 PM PDT 24 | 75402721 ps | ||
T367 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.903368572 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:59 PM PDT 24 | 42437285320 ps | ||
T368 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3435865844 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:56 PM PDT 24 | 961797378 ps | ||
T139 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.968165950 | Aug 15 04:35:49 PM PDT 24 | Aug 15 04:35:54 PM PDT 24 | 442968563 ps | ||
T369 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2317108311 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 2404587696 ps | ||
T370 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.194920231 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:40 PM PDT 24 | 9691407221 ps | ||
T140 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4056172390 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 268665159 ps | ||
T371 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3231126486 | Aug 15 04:35:12 PM PDT 24 | Aug 15 04:35:13 PM PDT 24 | 56278837 ps | ||
T178 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1705144942 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:52 PM PDT 24 | 1467476192 ps | ||
T126 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.79547845 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:36:11 PM PDT 24 | 5852369504 ps | ||
T372 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2549065308 | Aug 15 04:35:54 PM PDT 24 | Aug 15 04:35:57 PM PDT 24 | 371667827 ps | ||
T373 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.421633805 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 163946510 ps | ||
T116 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2619219786 | Aug 15 04:35:14 PM PDT 24 | Aug 15 04:35:16 PM PDT 24 | 1214203318 ps | ||
T119 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2222901132 | Aug 15 04:35:46 PM PDT 24 | Aug 15 04:35:51 PM PDT 24 | 263933902 ps | ||
T181 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3070918510 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:44 PM PDT 24 | 1818275028 ps | ||
T374 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3656458701 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:40 PM PDT 24 | 99604257 ps | ||
T91 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2299533382 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 148596625 ps | ||
T375 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1425406320 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:36:03 PM PDT 24 | 90970724409 ps | ||
T376 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2699298806 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:36:22 PM PDT 24 | 13183852771 ps | ||
T377 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.979356133 | Aug 15 04:35:50 PM PDT 24 | Aug 15 04:35:52 PM PDT 24 | 6539364108 ps | ||
T378 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1425420321 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 76904189 ps | ||
T379 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3710960618 | Aug 15 04:35:53 PM PDT 24 | Aug 15 04:35:56 PM PDT 24 | 389160776 ps | ||
T174 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.165680672 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 675549415 ps | ||
T127 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2339930625 | Aug 15 04:35:10 PM PDT 24 | Aug 15 04:36:16 PM PDT 24 | 2249848971 ps | ||
T128 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1059399571 | Aug 15 04:36:01 PM PDT 24 | Aug 15 04:36:04 PM PDT 24 | 382441899 ps | ||
T380 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2954771809 | Aug 15 04:35:12 PM PDT 24 | Aug 15 04:35:18 PM PDT 24 | 7300117955 ps | ||
T381 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3090606907 | Aug 15 04:35:12 PM PDT 24 | Aug 15 04:35:16 PM PDT 24 | 931980356 ps | ||
T382 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3089857323 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 975093040 ps | ||
T129 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3812081115 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:37 PM PDT 24 | 76396395 ps | ||
T383 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1232504674 | Aug 15 04:35:48 PM PDT 24 | Aug 15 04:36:18 PM PDT 24 | 21884154271 ps | ||
T384 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1217378795 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:46 PM PDT 24 | 777015344 ps | ||
T385 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1984823943 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:36:06 PM PDT 24 | 1728361042 ps | ||
T386 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.662127001 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 202462767 ps | ||
T387 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3387398549 | Aug 15 04:35:15 PM PDT 24 | Aug 15 04:35:18 PM PDT 24 | 2289776662 ps | ||
T388 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1621972084 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 227291323 ps | ||
T120 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2628395256 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:36 PM PDT 24 | 155727652 ps | ||
T121 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4197514660 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:35:40 PM PDT 24 | 4102552940 ps | ||
T389 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.434011907 | Aug 15 04:35:18 PM PDT 24 | Aug 15 04:35:21 PM PDT 24 | 649258500 ps | ||
T122 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1067698615 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:29 PM PDT 24 | 209540315 ps | ||
T130 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1122162910 | Aug 15 04:35:23 PM PDT 24 | Aug 15 04:35:26 PM PDT 24 | 253898963 ps | ||
T390 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.68747919 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 2088976323 ps | ||
T391 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1077870873 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:49 PM PDT 24 | 7181441189 ps | ||
T131 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1645808617 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:36:50 PM PDT 24 | 6422266115 ps | ||
T392 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3745780297 | Aug 15 04:35:47 PM PDT 24 | Aug 15 04:35:59 PM PDT 24 | 2827347601 ps | ||
T393 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3930836420 | Aug 15 04:35:43 PM PDT 24 | Aug 15 04:35:46 PM PDT 24 | 80850063 ps | ||
T394 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3875776640 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 405515475 ps | ||
T395 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1412694096 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 279456374 ps | ||
T396 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4211909918 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:30 PM PDT 24 | 13007401721 ps | ||
T397 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.837236318 | Aug 15 04:36:02 PM PDT 24 | Aug 15 04:36:07 PM PDT 24 | 216937889 ps | ||
T398 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.37329085 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 488740749 ps | ||
T399 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3416832545 | Aug 15 04:35:23 PM PDT 24 | Aug 15 04:35:24 PM PDT 24 | 232788836 ps | ||
T400 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.755994742 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 987442612 ps | ||
T401 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1613278554 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:43 PM PDT 24 | 124595058 ps | ||
T402 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3231556034 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:35:37 PM PDT 24 | 108668647 ps | ||
T403 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1117653711 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 240082110 ps | ||
T404 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2266875241 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 3636390230 ps | ||
T405 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.25646350 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:36:25 PM PDT 24 | 26115690535 ps | ||
T406 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2199692837 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:58 PM PDT 24 | 13918656047 ps | ||
T407 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2981437706 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 688752581 ps | ||
T408 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3314462542 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:35:18 PM PDT 24 | 117997862 ps | ||
T132 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1620863548 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:37 PM PDT 24 | 319814268 ps | ||
T409 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4288066268 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 172964033 ps | ||
T133 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.978500449 | Aug 15 04:35:32 PM PDT 24 | Aug 15 04:35:35 PM PDT 24 | 169617491 ps | ||
T410 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2722155292 | Aug 15 04:35:24 PM PDT 24 | Aug 15 04:35:26 PM PDT 24 | 163597606 ps | ||
T411 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.495030855 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:39 PM PDT 24 | 100434076 ps | ||
T412 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3506809912 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 138201639 ps | ||
T413 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3006368795 | Aug 15 04:35:45 PM PDT 24 | Aug 15 04:35:46 PM PDT 24 | 180408160 ps | ||
T134 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1439317920 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 543765497 ps | ||
T123 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3726310194 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:36:35 PM PDT 24 | 3727705706 ps | ||
T414 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.927500614 | Aug 15 04:35:36 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 241133361 ps | ||
T415 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.753664982 | Aug 15 04:35:47 PM PDT 24 | Aug 15 04:35:50 PM PDT 24 | 412343722 ps | ||
T124 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.416697270 | Aug 15 04:35:12 PM PDT 24 | Aug 15 04:36:35 PM PDT 24 | 22025820676 ps | ||
T416 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1314236640 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:43 PM PDT 24 | 300122965 ps | ||
T417 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.853010284 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 34990099 ps | ||
T418 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.832882598 | Aug 15 04:35:27 PM PDT 24 | Aug 15 04:35:29 PM PDT 24 | 1364571704 ps | ||
T419 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3017870664 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 133812127 ps | ||
T420 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4185991251 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:36:36 PM PDT 24 | 28106455229 ps | ||
T421 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2641009721 | Aug 15 04:35:32 PM PDT 24 | Aug 15 04:35:34 PM PDT 24 | 269155638 ps | ||
T422 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1574067615 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 4963160663 ps | ||
T423 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1588742770 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:37 PM PDT 24 | 583803984 ps | ||
T424 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1140769991 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:36:42 PM PDT 24 | 11900326015 ps | ||
T425 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4053567768 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:39 PM PDT 24 | 271802695 ps | ||
T426 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2507487332 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 781759742 ps | ||
T427 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.651692008 | Aug 15 04:35:11 PM PDT 24 | Aug 15 04:35:58 PM PDT 24 | 18289964194 ps | ||
T428 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3410466696 | Aug 15 04:35:15 PM PDT 24 | Aug 15 04:35:17 PM PDT 24 | 476720426 ps | ||
T94 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2380551397 | Aug 15 04:35:12 PM PDT 24 | Aug 15 04:36:35 PM PDT 24 | 42822343777 ps | ||
T429 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2352790964 | Aug 15 04:35:26 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 6474249808 ps | ||
T430 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1668278480 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:36:12 PM PDT 24 | 11215223521 ps | ||
T175 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1409040892 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:36:02 PM PDT 24 | 2860733533 ps | ||
T431 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4256170108 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:35:21 PM PDT 24 | 151043800 ps | ||
T432 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3067952630 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 2390939271 ps | ||
T433 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1419972133 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:35 PM PDT 24 | 8407882630 ps | ||
T182 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.378020884 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:36:01 PM PDT 24 | 4930092197 ps | ||
T434 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2828333158 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 194610749 ps | ||
T435 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1770828686 | Aug 15 04:35:24 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 171724759 ps | ||
T180 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1943272353 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 1000810754 ps | ||
T436 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2955010051 | Aug 15 04:35:31 PM PDT 24 | Aug 15 04:35:33 PM PDT 24 | 499163340 ps | ||
T90 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2888465027 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:36:32 PM PDT 24 | 3282516389 ps | ||
T437 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1496128544 | Aug 15 04:35:15 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 15090976416 ps | ||
T438 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1020869073 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:35 PM PDT 24 | 94471241 ps | ||
T439 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2490539517 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:35:35 PM PDT 24 | 238054896 ps | ||
T440 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1782879563 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:40 PM PDT 24 | 163618765 ps | ||
T441 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2067860021 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 137300389 ps | ||
T442 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4128388453 | Aug 15 04:35:32 PM PDT 24 | Aug 15 04:35:34 PM PDT 24 | 2012614879 ps | ||
T88 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1270223286 | Aug 15 04:35:21 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 981116803 ps | ||
T443 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3735210424 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:23 PM PDT 24 | 46259454 ps | ||
T444 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3911422844 | Aug 15 04:35:31 PM PDT 24 | Aug 15 04:35:52 PM PDT 24 | 28051023081 ps | ||
T445 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1892011217 | Aug 15 04:35:11 PM PDT 24 | Aug 15 04:35:13 PM PDT 24 | 57383054 ps | ||
T446 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1598350464 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:42 PM PDT 24 | 3100806218 ps | ||
T447 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2661871551 | Aug 15 04:35:26 PM PDT 24 | Aug 15 04:35:26 PM PDT 24 | 103227664 ps | ||
T448 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2388999464 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:35:28 PM PDT 24 | 1788327063 ps | ||
T449 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3702608693 | Aug 15 04:35:40 PM PDT 24 | Aug 15 04:35:43 PM PDT 24 | 294730943 ps | ||
T450 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1494867714 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:43 PM PDT 24 | 82690514 ps | ||
T451 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2292738587 | Aug 15 04:35:16 PM PDT 24 | Aug 15 04:35:25 PM PDT 24 | 13569477243 ps | ||
T452 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2652653233 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 553707639 ps | ||
T453 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1139269635 | Aug 15 04:35:26 PM PDT 24 | Aug 15 04:35:29 PM PDT 24 | 373084046 ps | ||
T454 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2736001305 | Aug 15 04:35:31 PM PDT 24 | Aug 15 04:35:33 PM PDT 24 | 862261427 ps | ||
T179 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1618488611 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:36:03 PM PDT 24 | 2338878552 ps | ||
T455 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2047747350 | Aug 15 04:35:21 PM PDT 24 | Aug 15 04:36:31 PM PDT 24 | 84101200727 ps | ||
T456 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.876823309 | Aug 15 04:35:11 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 1553727310 ps | ||
T457 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2596349512 | Aug 15 04:35:14 PM PDT 24 | Aug 15 04:35:16 PM PDT 24 | 499933640 ps | ||
T458 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.35469135 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:38 PM PDT 24 | 301592396 ps | ||
T459 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3469414388 | Aug 15 04:35:30 PM PDT 24 | Aug 15 04:35:31 PM PDT 24 | 673607715 ps | ||
T460 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4187982172 | Aug 15 04:35:52 PM PDT 24 | Aug 15 04:36:17 PM PDT 24 | 18236969394 ps | ||
T461 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.359559300 | Aug 15 04:35:41 PM PDT 24 | Aug 15 04:35:49 PM PDT 24 | 2216206693 ps | ||
T462 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4268273023 | Aug 15 04:35:14 PM PDT 24 | Aug 15 04:35:16 PM PDT 24 | 216466932 ps | ||
T463 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1608956090 | Aug 15 04:35:25 PM PDT 24 | Aug 15 04:35:29 PM PDT 24 | 141227507 ps | ||
T464 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.580714778 | Aug 15 04:35:44 PM PDT 24 | Aug 15 04:35:53 PM PDT 24 | 724167300 ps | ||
T465 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1663513224 | Aug 15 04:35:35 PM PDT 24 | Aug 15 04:35:36 PM PDT 24 | 39162040 ps | ||
T466 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.392131557 | Aug 15 04:35:22 PM PDT 24 | Aug 15 04:35:58 PM PDT 24 | 13513681078 ps | ||
T467 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3301013835 | Aug 15 04:35:37 PM PDT 24 | Aug 15 04:35:54 PM PDT 24 | 14234766496 ps | ||
T468 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1818527275 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:35:18 PM PDT 24 | 169329658 ps | ||
T469 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.413087845 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 8345910802 ps | ||
T470 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.96861792 | Aug 15 04:35:18 PM PDT 24 | Aug 15 04:35:21 PM PDT 24 | 1070997742 ps | ||
T471 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.916431558 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:34 PM PDT 24 | 257841837 ps | ||
T472 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.497522982 | Aug 15 04:35:26 PM PDT 24 | Aug 15 04:35:28 PM PDT 24 | 1141485021 ps | ||
T473 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1371708339 | Aug 15 04:35:26 PM PDT 24 | Aug 15 04:35:27 PM PDT 24 | 35729828 ps | ||
T474 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3679795087 | Aug 15 04:35:33 PM PDT 24 | Aug 15 04:35:53 PM PDT 24 | 2646747694 ps | ||
T475 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1099888079 | Aug 15 04:35:39 PM PDT 24 | Aug 15 04:35:41 PM PDT 24 | 109588524 ps | ||
T476 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.770907910 | Aug 15 04:35:38 PM PDT 24 | Aug 15 04:36:08 PM PDT 24 | 6205318665 ps | ||
T477 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.848601875 | Aug 15 04:35:48 PM PDT 24 | Aug 15 04:35:50 PM PDT 24 | 82841686 ps | ||
T478 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.959609775 | Aug 15 04:35:43 PM PDT 24 | Aug 15 04:35:45 PM PDT 24 | 168655413 ps | ||
T479 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1303903994 | Aug 15 04:35:17 PM PDT 24 | Aug 15 04:35:19 PM PDT 24 | 1459093442 ps | ||
T480 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1860465723 | Aug 15 04:35:34 PM PDT 24 | Aug 15 04:36:34 PM PDT 24 | 24171539355 ps | ||
T481 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.463571470 | Aug 15 04:36:00 PM PDT 24 | Aug 15 04:36:17 PM PDT 24 | 1703540648 ps | ||
T482 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2003468379 | Aug 15 04:35:23 PM PDT 24 | Aug 15 04:35:33 PM PDT 24 | 2073983387 ps | ||
T483 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1430846571 | Aug 15 04:35:46 PM PDT 24 | Aug 15 04:35:47 PM PDT 24 | 209174181 ps |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.4240070132 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1455661461 ps |
CPU time | 2.68 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:41 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-be1c5de1-5c1c-4c14-9034-65c9668b3b3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240070132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4240070132 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.2587439580 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 12089583693 ps |
CPU time | 76.65 seconds |
Started | Aug 15 04:40:03 PM PDT 24 |
Finished | Aug 15 04:41:20 PM PDT 24 |
Peak memory | 221588 kb |
Host | smart-af89ac3f-a239-4092-a390-d3d310fafcff |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587439580 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.2587439580 |
Directory | /workspace/5.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3474029369 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 18039453949 ps |
CPU time | 8.15 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:40:28 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-85e57c03-f22c-4ebf-a391-1ea36eb2f81a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474029369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3474029369 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1120843155 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 10622537516 ps |
CPU time | 107.6 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:42:01 PM PDT 24 |
Peak memory | 229900 kb |
Host | smart-0db92f1b-1720-4f51-8f03-545f249df1f3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120843155 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.1120843155 |
Directory | /workspace/7.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1140769991 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 11900326015 ps |
CPU time | 68.28 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:36:42 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-ad19d624-4f2c-4091-a517-7ea72ce1fde2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140769991 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1140769991 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.209525838 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 8056700784 ps |
CPU time | 21.07 seconds |
Started | Aug 15 04:35:29 PM PDT 24 |
Finished | Aug 15 04:35:50 PM PDT 24 |
Peak memory | 221568 kb |
Host | smart-a6147307-79c8-4eaf-a73d-97021f76a1a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209525838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.209525838 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/4.rv_dm_buffered_enable.2744648187 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 211261524 ps |
CPU time | 0.95 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:05 PM PDT 24 |
Peak memory | 234396 kb |
Host | smart-fc7d2cd7-19ea-4c37-94b8-3dd140fabd86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744648187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2744648187 |
Directory | /workspace/4.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2380551397 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 42822343777 ps |
CPU time | 82.03 seconds |
Started | Aug 15 04:35:12 PM PDT 24 |
Finished | Aug 15 04:36:35 PM PDT 24 |
Peak memory | 220952 kb |
Host | smart-53eb2cfb-6da4-4ec6-9865-e775e4ea46f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380551397 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2380551397 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_scanmode.4182014785 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 19534320 ps |
CPU time | 0.68 seconds |
Started | Aug 15 04:39:41 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-33b5dadc-c3fb-4f43-a6d7-41819ed21cee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182014785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.4182014785 |
Directory | /workspace/0.rv_dm_scanmode/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1581797223 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 7950050240 ps |
CPU time | 101.67 seconds |
Started | Aug 15 04:39:57 PM PDT 24 |
Finished | Aug 15 04:41:39 PM PDT 24 |
Peak memory | 221744 kb |
Host | smart-57aec5fc-8d85-467a-939d-fd4105969fc6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581797223 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1581797223 |
Directory | /workspace/2.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.678136487 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 738865931 ps |
CPU time | 3.08 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 229120 kb |
Host | smart-f8ed4169-a682-4640-84b1-fa28fe8803c5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678136487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.678136487 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.514009052 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 246721519 ps |
CPU time | 1.04 seconds |
Started | Aug 15 04:39:30 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-7d6711ad-79e9-445b-b5cf-45c2aeb59521 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514009052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.514009052 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2128915046 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 19314970587 ps |
CPU time | 63.56 seconds |
Started | Aug 15 04:39:38 PM PDT 24 |
Finished | Aug 15 04:40:42 PM PDT 24 |
Peak memory | 219256 kb |
Host | smart-1d39db8f-2515-4c9e-be03-bd1c2e9ab31f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128915046 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2128915046 |
Directory | /workspace/0.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2299533382 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 148596625 ps |
CPU time | 2.03 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 215416 kb |
Host | smart-7d6db41f-95a2-4a2b-a657-daab523f5e76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299533382 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2299533382 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.3670866397 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 6663248942 ps |
CPU time | 6.38 seconds |
Started | Aug 15 04:40:53 PM PDT 24 |
Finished | Aug 15 04:41:00 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-5a0509de-5a6d-4581-ac05-1e305b8d6772 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670866397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3670866397 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2888465027 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 3282516389 ps |
CPU time | 51.06 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:36:32 PM PDT 24 |
Peak memory | 217248 kb |
Host | smart-4d714173-207b-4d7f-8921-60f1fa671fa9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888465027 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2888465027 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2628395256 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 155727652 ps |
CPU time | 2.19 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:36 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-a4b0e3f4-48d4-4f72-9d54-e06b21153a59 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628395256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2628395256 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3689785584 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 20141236528 ps |
CPU time | 28.31 seconds |
Started | Aug 15 04:40:15 PM PDT 24 |
Finished | Aug 15 04:40:44 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-2a381325-47cf-42ed-b038-06092016b1d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689785584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3689785584 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3792803170 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 17884795716 ps |
CPU time | 53.72 seconds |
Started | Aug 15 04:39:47 PM PDT 24 |
Finished | Aug 15 04:40:41 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-07fb31f7-d3d2-4567-84c1-fe0315039203 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792803170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3792803170 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1560231349 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 813783760 ps |
CPU time | 1.95 seconds |
Started | Aug 15 04:39:21 PM PDT 24 |
Finished | Aug 15 04:39:23 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-f6f3f0e4-e382-4b2e-be55-8e3a573c3f60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560231349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1560231349 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.735785916 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 61716764 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:34 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-7f58eced-7f85-4e9e-9174-f2ef66ab6498 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735785916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.735785916 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2354509236 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 3311162562 ps |
CPU time | 5.1 seconds |
Started | Aug 15 04:35:47 PM PDT 24 |
Finished | Aug 15 04:35:52 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-73e7dd86-0cef-4040-8fa7-db2b95d48e78 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354509236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2354509236 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1705144942 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1467476192 ps |
CPU time | 16.29 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:52 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-bf1314b1-3853-4257-ab5a-b41c7751a796 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705144942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 705144942 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.3230590609 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 81968110 ps |
CPU time | 0.99 seconds |
Started | Aug 15 04:39:30 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-a58f30c1-d3a2-43f9-872c-ccc66dcf7dd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230590609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3230590609 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3910489660 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 13450221144 ps |
CPU time | 32.31 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:41:04 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-feed53ce-707a-4bec-a0a6-7200d27b0007 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910489660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3910489660 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1565354818 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1717951876 ps |
CPU time | 8.96 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-a7bc5d40-6b4a-4d53-9da5-fe425aa4ba23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565354818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1565354818 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.910954785 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1932817945 ps |
CPU time | 5.8 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:37 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-bf697693-b340-4673-902d-d706326366fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910954785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.910954785 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.1888018042 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 1026408673 ps |
CPU time | 3.85 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:37 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-946d9284-552c-4d40-9639-0176ecf8ba8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888018042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1888018042 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.4003450523 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3735758740 ps |
CPU time | 1.62 seconds |
Started | Aug 15 04:39:41 PM PDT 24 |
Finished | Aug 15 04:39:43 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-fb9236f7-e2c0-4251-b422-ec1ebf21c76c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003450523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.4003450523 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.1635673563 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 5711141810 ps |
CPU time | 14.82 seconds |
Started | Aug 15 04:39:56 PM PDT 24 |
Finished | Aug 15 04:40:11 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-113e1993-0e77-481b-8660-989acd85bb9d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635673563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1635673563 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.3052242433 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 3616118970 ps |
CPU time | 10.73 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:55 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-80574fc6-9c2a-4855-86d8-a4f55e7792ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052242433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3052242433 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2191532334 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 567471855 ps |
CPU time | 2.34 seconds |
Started | Aug 15 04:35:18 PM PDT 24 |
Finished | Aug 15 04:35:20 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-9852145f-5bb0-4538-b9bb-3579ed20692e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191532334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2191532334 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2619219786 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1214203318 ps |
CPU time | 1.89 seconds |
Started | Aug 15 04:35:14 PM PDT 24 |
Finished | Aug 15 04:35:16 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-e4649a88-078f-4fa8-a518-5cc4bb944603 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619219786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2619219786 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4152105512 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 704528398 ps |
CPU time | 1.3 seconds |
Started | Aug 15 04:39:30 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-a6373eb6-6d02-4a86-bd89-236622ed67f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152105512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4152105512 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.165680672 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 675549415 ps |
CPU time | 9.8 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 221448 kb |
Host | smart-e7850f3d-159d-44fe-84d0-ca1db30692d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165680672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.165680672 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2008504587 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 4687732680 ps |
CPU time | 10.96 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:32 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-4de766e2-5765-45a0-877f-f8b0bc73656e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008504587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2008504587 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3726310194 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 3727705706 ps |
CPU time | 73.4 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:36:35 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-8c62df58-c651-4880-99cb-e8f3ee78433c |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726310194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.3726310194 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.2380440569 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 203055112 ps |
CPU time | 0.87 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:30 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-a9bb04b7-c8b4-402d-87b2-deda0d9456c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380440569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.2380440569 |
Directory | /workspace/0.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1742737246 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 274014840 ps |
CPU time | 0.97 seconds |
Started | Aug 15 04:39:55 PM PDT 24 |
Finished | Aug 15 04:39:56 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-1c7be7e5-a576-447a-8c5c-a2c4177fc8ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742737246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1742737246 |
Directory | /workspace/3.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.566154132 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 6362109293 ps |
CPU time | 34.9 seconds |
Started | Aug 15 04:35:32 PM PDT 24 |
Finished | Aug 15 04:36:07 PM PDT 24 |
Peak memory | 221552 kb |
Host | smart-def13d2b-fe53-486c-a86b-4df1194662df |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566154132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.566154132 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.585230117 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1774387882 ps |
CPU time | 30.94 seconds |
Started | Aug 15 04:35:14 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 214284 kb |
Host | smart-5c15e9b1-6feb-4119-8d73-b83cade0a070 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585230117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.rv_dm_csr_aliasing.585230117 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.79547845 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 5852369504 ps |
CPU time | 55.7 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:36:11 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-7bc868f0-6772-4c3b-abb6-2b0695b952a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79547845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.79547845 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4268273023 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 216466932 ps |
CPU time | 1.82 seconds |
Started | Aug 15 04:35:14 PM PDT 24 |
Finished | Aug 15 04:35:16 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-86b692f1-95d3-4114-a9b7-0c78dc7563de |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268273023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4268273023 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1892011217 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 57383054 ps |
CPU time | 2.18 seconds |
Started | Aug 15 04:35:11 PM PDT 24 |
Finished | Aug 15 04:35:13 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-d861205f-eef6-4d33-9299-6c84b601ee9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892011217 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1892011217 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3713389257 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 78652561 ps |
CPU time | 1.69 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:35:17 PM PDT 24 |
Peak memory | 218456 kb |
Host | smart-fd76dc17-4916-42b3-a231-fc11bc2c0b8e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713389257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3713389257 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.25646350 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 26115690535 ps |
CPU time | 68.16 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:36:25 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-7a3353b5-f9da-4960-a463-8cdd44facafc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25646350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_ aliasing.25646350 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3231126486 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 56278837 ps |
CPU time | 0.77 seconds |
Started | Aug 15 04:35:12 PM PDT 24 |
Finished | Aug 15 04:35:13 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-29d6beb7-e993-4c71-ad32-c54c0a1cb753 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231126486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3231126486 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2954771809 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 7300117955 ps |
CPU time | 5.2 seconds |
Started | Aug 15 04:35:12 PM PDT 24 |
Finished | Aug 15 04:35:18 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-20b26010-ccd5-4bc7-a7fd-8942b4999782 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954771809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2954771809 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3090606907 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 931980356 ps |
CPU time | 3.29 seconds |
Started | Aug 15 04:35:12 PM PDT 24 |
Finished | Aug 15 04:35:16 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-9b48c675-6cee-4f9b-a21d-1e79eef98eda |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090606907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 090606907 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3410466696 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 476720426 ps |
CPU time | 1.97 seconds |
Started | Aug 15 04:35:15 PM PDT 24 |
Finished | Aug 15 04:35:17 PM PDT 24 |
Peak memory | 204612 kb |
Host | smart-8b3e2f42-11c0-4482-889f-77a8b3c0956e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410466696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3410466696 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.651692008 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 18289964194 ps |
CPU time | 46.23 seconds |
Started | Aug 15 04:35:11 PM PDT 24 |
Finished | Aug 15 04:35:58 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-e9a565c4-65e4-4dd2-9941-4d27e13a9ff7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651692008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.651692008 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.434011907 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 649258500 ps |
CPU time | 2.4 seconds |
Started | Aug 15 04:35:18 PM PDT 24 |
Finished | Aug 15 04:35:21 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-1167f6a7-16dc-4231-aea5-84d971744d64 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434011907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.434011907 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1818527275 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 169329658 ps |
CPU time | 0.77 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:35:18 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-de76b81f-ffb7-457e-9f10-6e683ffd8ca0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818527275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1818527275 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3735210424 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 46259454 ps |
CPU time | 0.76 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:23 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-4acdd26a-7b96-4957-9c6f-f10a9e22f9e0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735210424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3735210424 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1490386925 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 745920520 ps |
CPU time | 8.44 seconds |
Started | Aug 15 04:35:18 PM PDT 24 |
Finished | Aug 15 04:35:27 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-f5f41b37-2d56-4090-88a4-ca5c01ac8ff9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490386925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.1490386925 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3314462542 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 117997862 ps |
CPU time | 2.1 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:35:18 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-3c6810b4-2178-4375-be4a-6f4588fd4dc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314462542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3314462542 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2388999464 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 1788327063 ps |
CPU time | 10.98 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:35:28 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-c156c2f0-b8a5-48e5-9856-8ea9ff08c211 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388999464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2388999464 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2339930625 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 2249848971 ps |
CPU time | 66.3 seconds |
Started | Aug 15 04:35:10 PM PDT 24 |
Finished | Aug 15 04:36:16 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-799171e5-2a0d-4c0c-b37e-f82de7868129 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339930625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.2339930625 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.876823309 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 1553727310 ps |
CPU time | 26.84 seconds |
Started | Aug 15 04:35:11 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-c8b488d2-1150-47ba-a372-96445e3acae2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876823309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.876823309 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3279520207 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 75402721 ps |
CPU time | 1.72 seconds |
Started | Aug 15 04:35:10 PM PDT 24 |
Finished | Aug 15 04:35:12 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-5f53bc17-d01c-44b5-9512-f2d37eafcd92 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279520207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3279520207 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3535720668 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 265435054 ps |
CPU time | 2.69 seconds |
Started | Aug 15 04:35:14 PM PDT 24 |
Finished | Aug 15 04:35:17 PM PDT 24 |
Peak memory | 216724 kb |
Host | smart-690713d0-26e3-4610-a4d8-3184e9268adf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535720668 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3535720668 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1763374373 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 186153926 ps |
CPU time | 2.23 seconds |
Started | Aug 15 04:35:18 PM PDT 24 |
Finished | Aug 15 04:35:21 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-d17fe8fe-bf3d-446a-951a-ab70d39fbb27 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763374373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1763374373 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.587584721 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 238656537094 ps |
CPU time | 332.64 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:40:50 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-cf87ed46-32ae-467c-a8c8-43eff8054e8d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587584721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _aliasing.587584721 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2292738587 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 13569477243 ps |
CPU time | 9.28 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-3845f430-a826-4739-b538-2ca3b8b60d90 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292738587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2292738587 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2623139225 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 2122037814 ps |
CPU time | 2.89 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:35:20 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-862bbc7d-09ea-4db0-8768-ae3abb56cbeb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623139225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 623139225 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1633532139 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 923834219 ps |
CPU time | 3.29 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:35:20 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-41a611a7-e69c-407d-8869-834b92de020d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633532139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.1633532139 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1496128544 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 15090976416 ps |
CPU time | 9.25 seconds |
Started | Aug 15 04:35:15 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-dd6db9e1-d26d-475f-8ac8-f3a81a81d911 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496128544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1496128544 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1624974388 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 289547782 ps |
CPU time | 0.88 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:35:18 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-c9656fb6-5906-4799-9039-cfadb204ac65 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624974388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1624974388 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3989922417 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 194080843 ps |
CPU time | 0.85 seconds |
Started | Aug 15 04:35:13 PM PDT 24 |
Finished | Aug 15 04:35:14 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-82f1a77a-70c3-4bce-91fb-1c861ed8825a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989922417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 989922417 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1798881213 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 96852762 ps |
CPU time | 0.77 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:23 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-08df26b1-a989-4301-9679-b688bb4788fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798881213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1798881213 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.853010284 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 34990099 ps |
CPU time | 0.69 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 204612 kb |
Host | smart-f2b4b049-00e4-48c5-9252-0a5e6d1d8dd8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853010284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.853010284 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3067952630 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 2390939271 ps |
CPU time | 8.35 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-9793691b-9a34-42e4-ba09-15630c788888 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067952630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3067952630 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1270223286 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 981116803 ps |
CPU time | 16.91 seconds |
Started | Aug 15 04:35:21 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-d5c45b1a-8e0b-4c41-82c6-911162af52e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270223286 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1270223286 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4256170108 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 151043800 ps |
CPU time | 4.66 seconds |
Started | Aug 15 04:35:16 PM PDT 24 |
Finished | Aug 15 04:35:21 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-575cc703-ed08-4cc8-90a4-2506520ac6bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256170108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4256170108 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3834102424 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 4980956566 ps |
CPU time | 23.55 seconds |
Started | Aug 15 04:35:12 PM PDT 24 |
Finished | Aug 15 04:35:36 PM PDT 24 |
Peak memory | 221500 kb |
Host | smart-03f9e3a5-07af-4705-a12b-56edecb21e17 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834102424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3834102424 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.927500614 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 241133361 ps |
CPU time | 2 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-b1c50e4b-cfdf-4a91-b5c2-674caf38954f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927500614 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.927500614 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1620863548 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 319814268 ps |
CPU time | 1.6 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:37 PM PDT 24 |
Peak memory | 218248 kb |
Host | smart-7aa45239-1c15-4cf6-a0af-8dbfe375090a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620863548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1620863548 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2758639133 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 14306175064 ps |
CPU time | 20.76 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:55 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-4de0d472-1e89-475d-a23e-e5529cf86d91 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758639133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.2758639133 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2199692837 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 13918656047 ps |
CPU time | 20.25 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:58 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-f6f678a5-57a4-47a1-a16e-df3d2564addd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199692837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2199692837 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3656458701 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 99604257 ps |
CPU time | 0.93 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:40 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-f4d9f5c6-532d-45f6-a6da-52609836a23a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656458701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 3656458701 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4197514660 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 4102552940 ps |
CPU time | 4.02 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:35:40 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-87f5f30e-3e8f-4da4-8ad9-b34666277f1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197514660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.4197514660 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1412694096 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 279456374 ps |
CPU time | 4.34 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-783e4cd4-f980-4f57-b082-2d29aad74378 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412694096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1412694096 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1099888079 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 109588524 ps |
CPU time | 1.92 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-17f08a7d-9b3f-45eb-9df3-7b2351819d26 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099888079 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1099888079 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3812081115 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 76396395 ps |
CPU time | 2.19 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:37 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-078ad514-8f15-4417-b149-eeca12eec377 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812081115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3812081115 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1668278480 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 11215223521 ps |
CPU time | 31.05 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:36:12 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-ddafae6d-169d-422c-9c12-9724493bf656 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668278480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.1668278480 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2317108311 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2404587696 ps |
CPU time | 6.63 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-124a2eda-432e-42c3-96e6-7ee060d82544 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317108311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 2317108311 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3231556034 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 108668647 ps |
CPU time | 0.88 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:35:37 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-6ec78a72-ffcd-4da1-9273-95b28cf15066 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231556034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3231556034 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2186893354 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 557963092 ps |
CPU time | 8.38 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-76aa2e68-9c90-4313-bb2a-aefa15f0b60f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186893354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.2186893354 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2828333158 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 194610749 ps |
CPU time | 4.89 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 215452 kb |
Host | smart-128110aa-b28d-425c-ba20-c69b9cbd5b79 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828333158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2828333158 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3017870664 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 133812127 ps |
CPU time | 2.98 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 221128 kb |
Host | smart-4b10965d-64fb-4b22-a754-cf4f07ae6fb5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017870664 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3017870664 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2736001305 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 862261427 ps |
CPU time | 1.63 seconds |
Started | Aug 15 04:35:31 PM PDT 24 |
Finished | Aug 15 04:35:33 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-82498526-70d3-4247-b0b1-2689774da938 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736001305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2736001305 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.795760670 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 83880523065 ps |
CPU time | 135.87 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:37:52 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-b168294a-6c83-4944-ab31-a143d62136ef |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795760670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rv_dm_jtag_dmi_csr_bit_bash.795760670 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3770504908 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 4696794159 ps |
CPU time | 8.12 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:49 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-a877eeeb-e555-404e-9f13-4e5b0847de9f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770504908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3770504908 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2490539517 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 238054896 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:35 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-3b0d2208-7582-4cd2-b50f-d3eb7517664d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490539517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 2490539517 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1217378795 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 777015344 ps |
CPU time | 6.46 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:46 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-419f215c-7606-4741-ab71-18b56ad55905 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217378795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1217378795 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3060973758 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 352160313 ps |
CPU time | 3.71 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-91f52c66-73fa-4da8-b391-01d9381fd0b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060973758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3060973758 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3745780297 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 2827347601 ps |
CPU time | 11.67 seconds |
Started | Aug 15 04:35:47 PM PDT 24 |
Finished | Aug 15 04:35:59 PM PDT 24 |
Peak memory | 214040 kb |
Host | smart-49563103-5cd3-463c-9832-428f7968f951 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745780297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3 745780297 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.109612483 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 265744564 ps |
CPU time | 2.97 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:43 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-deaf0a17-9503-4e30-bedc-e0aa85d9880a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109612483 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.109612483 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3946065718 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 194154525 ps |
CPU time | 2.06 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:39 PM PDT 24 |
Peak memory | 218816 kb |
Host | smart-8e813ef0-cb80-44f9-bac1-33e52fb8ae94 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946065718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3946065718 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.68747919 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 2088976323 ps |
CPU time | 6.13 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-b755f8bd-ef4c-42c7-93d6-e57ace2f8165 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68747919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.r v_dm_jtag_dmi_csr_bit_bash.68747919 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1027150665 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 13225931109 ps |
CPU time | 39.38 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:36:14 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-26c62b1b-306a-4568-abb5-47dc71b2ac14 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027150665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 1027150665 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2507487332 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 781759742 ps |
CPU time | 2.64 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-5b0ed4ee-d188-468e-ab45-dae8fe5bad36 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507487332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2507487332 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.656441392 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 178959861 ps |
CPU time | 3.62 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-ba2cc6ec-993f-49ac-a5a6-644c8794bd11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656441392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.656441392 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.753664982 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 412343722 ps |
CPU time | 2.83 seconds |
Started | Aug 15 04:35:47 PM PDT 24 |
Finished | Aug 15 04:35:50 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-94f09094-42c2-423f-a87d-3a6ecc664970 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753664982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.753664982 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1943272353 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 1000810754 ps |
CPU time | 8.13 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 221440 kb |
Host | smart-ae956ec3-956a-4f67-a95e-88cc6f6f2a79 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943272353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 943272353 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4053567768 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 271802695 ps |
CPU time | 3.74 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:39 PM PDT 24 |
Peak memory | 219292 kb |
Host | smart-e66e5b58-55de-45be-89f2-0c2ea4a0bb6f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053567768 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4053567768 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3911422844 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 28051023081 ps |
CPU time | 21.1 seconds |
Started | Aug 15 04:35:31 PM PDT 24 |
Finished | Aug 15 04:35:52 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-c9594321-dd9e-46ce-92ce-bec714154074 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911422844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.3911422844 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3301013835 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 14234766496 ps |
CPU time | 17.15 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:54 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-c4fb131f-c087-458b-bd3f-ffcf8818c1dc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301013835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3301013835 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2641009721 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 269155638 ps |
CPU time | 1.34 seconds |
Started | Aug 15 04:35:32 PM PDT 24 |
Finished | Aug 15 04:35:34 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-9124d922-09e6-4cba-97ff-e530c71f0622 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641009721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 2641009721 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.580714778 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 724167300 ps |
CPU time | 8.59 seconds |
Started | Aug 15 04:35:44 PM PDT 24 |
Finished | Aug 15 04:35:53 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-87e17884-cd20-4ccd-95de-1da8452797c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580714778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.580714778 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3273771585 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 305598667 ps |
CPU time | 5.49 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-e3c84f9c-d5ec-40fc-9134-7028fda61332 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273771585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3273771585 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3506809912 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 138201639 ps |
CPU time | 3.14 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 217056 kb |
Host | smart-6634561e-f166-4a7f-882f-484c62c4aac3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506809912 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3506809912 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3288349230 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 77544470 ps |
CPU time | 1.57 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:36 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-f16f8f80-0632-4325-af1d-6828ae492efe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288349230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3288349230 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2699298806 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 13183852771 ps |
CPU time | 41.38 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:36:22 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-2d8cac97-4c42-4e08-9225-8130ad0d1d8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699298806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.2699298806 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.194920231 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 9691407221 ps |
CPU time | 4.89 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:40 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-cede978d-71ac-41cd-ad90-7555b7f34502 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194920231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.194920231 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1020869073 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 94471241 ps |
CPU time | 0.96 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:35 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-08d75664-451d-4860-b346-452243997277 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020869073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 1020869073 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.849873491 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 315907100 ps |
CPU time | 4.04 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-a6ef2092-7c20-484c-a805-ad09f30a574a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849873491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.849873491 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1117653711 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 240082110 ps |
CPU time | 3.76 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-441b50f4-b22f-4bd8-aa9c-081f2c5de48f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117653711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1117653711 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3070918510 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1818275028 ps |
CPU time | 10.4 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:35:44 PM PDT 24 |
Peak memory | 221524 kb |
Host | smart-cf7da261-597d-4e3a-84dc-9d73b1708aaa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070918510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3 070918510 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1314236640 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 300122965 ps |
CPU time | 2.4 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:43 PM PDT 24 |
Peak memory | 219176 kb |
Host | smart-90bfa4a2-f7bf-4319-a7e8-248ed4f781b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314236640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1314236640 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.515709142 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 9252460492 ps |
CPU time | 7.03 seconds |
Started | Aug 15 04:36:07 PM PDT 24 |
Finished | Aug 15 04:36:14 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-241b073b-df96-4a93-ac20-fc3ea717add7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515709142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rv_dm_jtag_dmi_csr_bit_bash.515709142 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.413087845 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 8345910802 ps |
CPU time | 6.44 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-77731d75-670e-4f87-aa1e-e2692423ec61 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413087845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.413087845 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.662127001 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 202462767 ps |
CPU time | 0.83 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-37a7f22d-42f3-49a3-a777-bfa95a62218a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662127001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.662127001 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1224034878 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 2202809450 ps |
CPU time | 8.08 seconds |
Started | Aug 15 04:35:46 PM PDT 24 |
Finished | Aug 15 04:35:54 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-a719ce53-a15e-404d-95c3-795128cdcfa3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224034878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.1224034878 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3930836420 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 80850063 ps |
CPU time | 2.74 seconds |
Started | Aug 15 04:35:43 PM PDT 24 |
Finished | Aug 15 04:35:46 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-a957089e-9f8c-4ef6-9973-58523e86622b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930836420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3930836420 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.359559300 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 2216206693 ps |
CPU time | 8.43 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:49 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-b10a2eb9-01f8-4e0f-8d4b-2526c3e4a02a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359559300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.359559300 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1782879563 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 163618765 ps |
CPU time | 1.87 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:40 PM PDT 24 |
Peak memory | 217212 kb |
Host | smart-f445bbe9-c1ed-4775-b55d-07af554c2b87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782879563 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1782879563 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.959609775 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 168655413 ps |
CPU time | 1.52 seconds |
Started | Aug 15 04:35:43 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 213188 kb |
Host | smart-b3133295-4f1b-4edb-9dd1-80f3fea4da14 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959609775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.959609775 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2242224924 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 2663412354 ps |
CPU time | 2.66 seconds |
Started | Aug 15 04:35:46 PM PDT 24 |
Finished | Aug 15 04:35:49 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-0b9de27f-d513-4f82-8eb6-83ab6bef15af |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242224924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.2242224924 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1574067615 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 4963160663 ps |
CPU time | 7.31 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-eb1bd0e1-047b-4c10-8935-a16a517400ab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574067615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 1574067615 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3006368795 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 180408160 ps |
CPU time | 0.85 seconds |
Started | Aug 15 04:35:45 PM PDT 24 |
Finished | Aug 15 04:35:46 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-3a4a6d2d-28de-489c-af7c-e90b06bbea49 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006368795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 3006368795 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2222901132 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 263933902 ps |
CPU time | 4.25 seconds |
Started | Aug 15 04:35:46 PM PDT 24 |
Finished | Aug 15 04:35:51 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-b902a2a0-3256-4211-8762-05e654e6a5da |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222901132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2222901132 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.620168975 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 490329556 ps |
CPU time | 5.46 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-24b08afb-dde3-465e-89ac-63b4be02827e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620168975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.620168975 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1618488611 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 2338878552 ps |
CPU time | 22.39 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:36:03 PM PDT 24 |
Peak memory | 221584 kb |
Host | smart-579fc9cd-b03f-4f89-a576-15f89b5765ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618488611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1 618488611 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2549065308 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 371667827 ps |
CPU time | 3.14 seconds |
Started | Aug 15 04:35:54 PM PDT 24 |
Finished | Aug 15 04:35:57 PM PDT 24 |
Peak memory | 218208 kb |
Host | smart-951c8e6d-8219-4031-8500-fc52cfd1b862 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549065308 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2549065308 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1059399571 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 382441899 ps |
CPU time | 2.54 seconds |
Started | Aug 15 04:36:01 PM PDT 24 |
Finished | Aug 15 04:36:04 PM PDT 24 |
Peak memory | 218792 kb |
Host | smart-517012c8-06eb-4c1d-a1c1-a4ed111fc830 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059399571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1059399571 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4187982172 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 18236969394 ps |
CPU time | 24.62 seconds |
Started | Aug 15 04:35:52 PM PDT 24 |
Finished | Aug 15 04:36:17 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-badc984a-44bf-4198-8698-8e68a49297c7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187982172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.4187982172 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.979356133 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 6539364108 ps |
CPU time | 2.83 seconds |
Started | Aug 15 04:35:50 PM PDT 24 |
Finished | Aug 15 04:35:52 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-59f29460-b10c-4f11-867e-968889759e0e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979356133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.979356133 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1430846571 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 209174181 ps |
CPU time | 0.84 seconds |
Started | Aug 15 04:35:46 PM PDT 24 |
Finished | Aug 15 04:35:47 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-28d7fe85-ba85-4dda-9333-cfb395d26e87 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430846571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 1430846571 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.837236318 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 216937889 ps |
CPU time | 4.21 seconds |
Started | Aug 15 04:36:02 PM PDT 24 |
Finished | Aug 15 04:36:07 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-9c62c037-f061-4e5a-b68d-aa7280447076 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837236318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.837236318 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1917963835 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 1803879993 ps |
CPU time | 19.67 seconds |
Started | Aug 15 04:35:51 PM PDT 24 |
Finished | Aug 15 04:36:11 PM PDT 24 |
Peak memory | 221428 kb |
Host | smart-a2e83b68-06d7-410f-bec5-75e9c0cb24d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917963835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1 917963835 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.848601875 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 82841686 ps |
CPU time | 1.84 seconds |
Started | Aug 15 04:35:48 PM PDT 24 |
Finished | Aug 15 04:35:50 PM PDT 24 |
Peak memory | 215016 kb |
Host | smart-c15f7ff5-82e4-4d2c-a618-2dc0416ff759 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848601875 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.848601875 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3710960618 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 389160776 ps |
CPU time | 2.35 seconds |
Started | Aug 15 04:35:53 PM PDT 24 |
Finished | Aug 15 04:35:56 PM PDT 24 |
Peak memory | 218456 kb |
Host | smart-3d90c7cd-c2c0-4da4-bf0c-59b468aa8719 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710960618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3710960618 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1232504674 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 21884154271 ps |
CPU time | 30.53 seconds |
Started | Aug 15 04:35:48 PM PDT 24 |
Finished | Aug 15 04:36:18 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-aa8ce9e8-dc10-4cad-8c2e-c3e01bde4fcb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232504674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1232504674 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.370339671 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1235683414 ps |
CPU time | 4.21 seconds |
Started | Aug 15 04:35:54 PM PDT 24 |
Finished | Aug 15 04:35:59 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-3ef402d7-342e-49f0-9e9a-0b3600fc2364 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370339671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.370339671 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2205178526 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 110913984 ps |
CPU time | 0.82 seconds |
Started | Aug 15 04:35:59 PM PDT 24 |
Finished | Aug 15 04:36:00 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-a98ce4cc-1a25-43cd-bbb4-fde4438969a5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205178526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2205178526 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.968165950 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 442968563 ps |
CPU time | 4.1 seconds |
Started | Aug 15 04:35:49 PM PDT 24 |
Finished | Aug 15 04:35:54 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-9a10989e-6443-4f0a-b838-56f1083d135a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968165950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_ csr_outstanding.968165950 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1485447043 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 352244008 ps |
CPU time | 3.88 seconds |
Started | Aug 15 04:35:46 PM PDT 24 |
Finished | Aug 15 04:35:50 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-2681858d-159e-4f23-967d-7c708e42b123 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485447043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1485447043 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.463571470 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 1703540648 ps |
CPU time | 16.96 seconds |
Started | Aug 15 04:36:00 PM PDT 24 |
Finished | Aug 15 04:36:17 PM PDT 24 |
Peak memory | 215704 kb |
Host | smart-4ed369a6-6649-4e79-93a0-977305560614 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463571470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.463571470 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.416697270 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 22025820676 ps |
CPU time | 82.52 seconds |
Started | Aug 15 04:35:12 PM PDT 24 |
Finished | Aug 15 04:36:35 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-09cc8c41-2283-41c4-8deb-2c70b2e0d62c |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416697270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.rv_dm_csr_aliasing.416697270 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1124630732 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 16731153609 ps |
CPU time | 36.09 seconds |
Started | Aug 15 04:35:21 PM PDT 24 |
Finished | Aug 15 04:35:58 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-b90be0ca-2d02-4fd0-b6dd-3d8afe0082d7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124630732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1124630732 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.421633805 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 163946510 ps |
CPU time | 1.48 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-c358a654-0dd8-4a15-9ff4-c47aba179217 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421633805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.421633805 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1139269635 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 373084046 ps |
CPU time | 3.05 seconds |
Started | Aug 15 04:35:26 PM PDT 24 |
Finished | Aug 15 04:35:29 PM PDT 24 |
Peak memory | 218452 kb |
Host | smart-5ba21825-1f95-4297-94e6-1370230aa54b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139269635 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1139269635 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1875877548 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 120204470 ps |
CPU time | 2.28 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:28 PM PDT 24 |
Peak memory | 218860 kb |
Host | smart-13108e25-6d61-4b69-8f45-fb8eb4642053 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875877548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1875877548 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1516702927 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 111927573449 ps |
CPU time | 269.21 seconds |
Started | Aug 15 04:35:15 PM PDT 24 |
Finished | Aug 15 04:39:45 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-3ea76cfd-106d-4c1f-8db8-362855ec450d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516702927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.1516702927 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.337938166 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 11927041478 ps |
CPU time | 18.43 seconds |
Started | Aug 15 04:35:18 PM PDT 24 |
Finished | Aug 15 04:35:36 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-5a818829-570b-4f20-9251-5cb0c901b99e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337938166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r v_dm_jtag_dmi_csr_bit_bash.337938166 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1464294523 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 2260933408 ps |
CPU time | 6.63 seconds |
Started | Aug 15 04:35:13 PM PDT 24 |
Finished | Aug 15 04:35:20 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-5b3b3045-211c-41c7-a894-3490b3cfbcb6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464294523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1464294523 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2266875241 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 3636390230 ps |
CPU time | 3.4 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-97c69f56-c235-4b46-ab85-ec1471147cdf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266875241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2 266875241 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.96861792 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 1070997742 ps |
CPU time | 2.66 seconds |
Started | Aug 15 04:35:18 PM PDT 24 |
Finished | Aug 15 04:35:21 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-96199e45-1c4d-443a-85b4-2ee55aaa0602 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96861792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_ aliasing.96861792 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3387398549 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 2289776662 ps |
CPU time | 3.31 seconds |
Started | Aug 15 04:35:15 PM PDT 24 |
Finished | Aug 15 04:35:18 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-3aaff10b-30a8-4a92-a024-7d8d8fe6bd4f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387398549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.3387398549 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1303903994 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 1459093442 ps |
CPU time | 1.87 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:35:19 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-ce2554b8-022b-4919-9a30-3b8315f464b9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303903994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.1303903994 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2596349512 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 499933640 ps |
CPU time | 1.33 seconds |
Started | Aug 15 04:35:14 PM PDT 24 |
Finished | Aug 15 04:35:16 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-42bef0e7-7731-47c1-b737-84a87fbd73db |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596349512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 596349512 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1663513224 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 39162040 ps |
CPU time | 0.76 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:36 PM PDT 24 |
Peak memory | 204772 kb |
Host | smart-0d6bf333-6511-40da-8991-7482913238a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663513224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1663513224 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2637954569 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 104297949 ps |
CPU time | 0.7 seconds |
Started | Aug 15 04:35:24 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-de757ba5-c204-4fbf-bcf5-c7a366863d6c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637954569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2637954569 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.755994742 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 987442612 ps |
CPU time | 4.46 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-d6f098b3-e0e3-4b40-9926-1a79153375bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755994742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c sr_outstanding.755994742 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.931318726 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 41517393366 ps |
CPU time | 55.63 seconds |
Started | Aug 15 04:35:17 PM PDT 24 |
Finished | Aug 15 04:36:13 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-f9b592e8-4314-4b42-990f-6aba23c8c301 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931318726 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.931318726 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4197108970 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 84574490 ps |
CPU time | 2.3 seconds |
Started | Aug 15 04:35:14 PM PDT 24 |
Finished | Aug 15 04:35:17 PM PDT 24 |
Peak memory | 214756 kb |
Host | smart-ac0fa3c8-88f2-471d-9e25-438635afc6e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197108970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4197108970 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3069432733 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 4106632518 ps |
CPU time | 21.96 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-3734b5be-48c8-4129-8c76-efb6421f8580 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069432733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3069432733 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3915696767 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 8816871878 ps |
CPU time | 32.36 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:54 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-baff6f3d-cc80-4dfc-89e5-7d1e070e2b4f |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915696767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.3915696767 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1984823943 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1728361042 ps |
CPU time | 27.89 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:36:06 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-55b62aa1-dcbe-4cb3-bdd4-62dfddb5b9f1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984823943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1984823943 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1122162910 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 253898963 ps |
CPU time | 2.73 seconds |
Started | Aug 15 04:35:23 PM PDT 24 |
Finished | Aug 15 04:35:26 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-b6fa2b8b-8e3f-4079-857f-6ad8fffd0a3a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122162910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1122162910 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2686011639 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 203551026 ps |
CPU time | 3.19 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 218172 kb |
Host | smart-873efd5f-c045-4166-a169-71842a13fea2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686011639 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2686011639 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4134799472 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 383524758 ps |
CPU time | 2.45 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:28 PM PDT 24 |
Peak memory | 218740 kb |
Host | smart-89bb8bcd-02d0-4740-8416-243e5a7a9e06 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134799472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4134799472 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1425406320 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 90970724409 ps |
CPU time | 37.1 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:36:03 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-56293d6a-6a28-44a9-84cd-ba9aae016345 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425406320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.1425406320 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2352790964 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 6474249808 ps |
CPU time | 18.91 seconds |
Started | Aug 15 04:35:26 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-b588b58d-509f-479d-a00c-76abccc64794 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352790964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.2352790964 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1077870873 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 7181441189 ps |
CPU time | 11.16 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:49 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-d0f98f32-4dd8-44b9-aa10-58c217353068 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077870873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.1077870873 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.832882598 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1364571704 ps |
CPU time | 1.86 seconds |
Started | Aug 15 04:35:27 PM PDT 24 |
Finished | Aug 15 04:35:29 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-233ea8f9-0a19-4f99-9953-cd2f41bd28f7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832882598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.832882598 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2955010051 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 499163340 ps |
CPU time | 1.3 seconds |
Started | Aug 15 04:35:31 PM PDT 24 |
Finished | Aug 15 04:35:33 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-5a5caa01-8234-46f6-9011-67341c3cc2b7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955010051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.2955010051 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1419972133 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 8407882630 ps |
CPU time | 13.05 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:35 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-5c95bffa-e1bd-4a88-a717-0ad3f7c75960 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419972133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1419972133 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4109703841 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 113248689 ps |
CPU time | 0.93 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:26 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-5e8db9f6-4744-4c9f-ad15-35753a2e1a32 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109703841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.4109703841 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3469414388 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 673607715 ps |
CPU time | 1.03 seconds |
Started | Aug 15 04:35:30 PM PDT 24 |
Finished | Aug 15 04:35:31 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-71009d1a-b797-4c98-a6c3-98019d215d05 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469414388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3 469414388 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1371708339 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 35729828 ps |
CPU time | 0.7 seconds |
Started | Aug 15 04:35:26 PM PDT 24 |
Finished | Aug 15 04:35:27 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-daa18684-928b-431a-a44f-9fc2b2ea404f |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371708339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1371708339 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3715138847 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 64958422 ps |
CPU time | 0.79 seconds |
Started | Aug 15 04:35:31 PM PDT 24 |
Finished | Aug 15 04:35:32 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-56f3ef98-2577-4e99-9d40-7dfea146dc45 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715138847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3715138847 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1067698615 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 209540315 ps |
CPU time | 3.63 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:29 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-d0d2f16c-8fbf-4ef4-a48f-765ad45e0ee5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067698615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1067698615 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3163657698 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 991628250 ps |
CPU time | 7.86 seconds |
Started | Aug 15 04:35:24 PM PDT 24 |
Finished | Aug 15 04:35:32 PM PDT 24 |
Peak memory | 215152 kb |
Host | smart-bbf34aad-7ecd-4d85-b178-b8a504531448 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163657698 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3163657698 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3698550507 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 121032080 ps |
CPU time | 2.55 seconds |
Started | Aug 15 04:35:24 PM PDT 24 |
Finished | Aug 15 04:35:27 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-48e4b016-d186-490a-be0c-5c69d2114d5c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698550507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3698550507 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2003468379 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 2073983387 ps |
CPU time | 10.41 seconds |
Started | Aug 15 04:35:23 PM PDT 24 |
Finished | Aug 15 04:35:33 PM PDT 24 |
Peak memory | 221644 kb |
Host | smart-3989e31c-c088-4d0e-a0a9-dc39609a49d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003468379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2003468379 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1645808617 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 6422266115 ps |
CPU time | 74.1 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:36:50 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-ab1c8932-11a7-435a-81b5-006cff87daf4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645808617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1645808617 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2722155292 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 163597606 ps |
CPU time | 1.63 seconds |
Started | Aug 15 04:35:24 PM PDT 24 |
Finished | Aug 15 04:35:26 PM PDT 24 |
Peak memory | 213208 kb |
Host | smart-b181c7d6-0681-4d4a-a8d1-e693d0916ec0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722155292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2722155292 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1608956090 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 141227507 ps |
CPU time | 3.27 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:29 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-6b62e501-3962-4979-8ffc-ade15869aa37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608956090 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1608956090 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3416832545 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 232788836 ps |
CPU time | 1.61 seconds |
Started | Aug 15 04:35:23 PM PDT 24 |
Finished | Aug 15 04:35:24 PM PDT 24 |
Peak memory | 218536 kb |
Host | smart-18a917c6-b83e-490b-829f-3d1b7ed5e675 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416832545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3416832545 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2047747350 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 84101200727 ps |
CPU time | 69.5 seconds |
Started | Aug 15 04:35:21 PM PDT 24 |
Finished | Aug 15 04:36:31 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-7c6a0882-8c3b-40d7-a9f6-2e8b81d8c3fc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047747350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.2047747350 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4185991251 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 28106455229 ps |
CPU time | 70.8 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:36:36 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-8333ed63-7429-4991-9677-997236ce91fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185991251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.4185991251 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2847742685 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 3807584307 ps |
CPU time | 6.23 seconds |
Started | Aug 15 04:35:42 PM PDT 24 |
Finished | Aug 15 04:35:48 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-a1858a87-f6e8-4544-9306-cb7c1be6c2b9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847742685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2847742685 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.392131557 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 13513681078 ps |
CPU time | 35.79 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:58 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-1309f6fd-7992-47cd-961e-253783b629ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392131557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.392131557 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.497522982 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 1141485021 ps |
CPU time | 1.39 seconds |
Started | Aug 15 04:35:26 PM PDT 24 |
Finished | Aug 15 04:35:28 PM PDT 24 |
Peak memory | 204612 kb |
Host | smart-3766ed76-c1aa-464a-9ffb-3076008c9139 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497522982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.497522982 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.903368572 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 42437285320 ps |
CPU time | 34.09 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:59 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-9f6431e9-387c-4f14-839f-b48ee5320e8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903368572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.903368572 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1770828686 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 171724759 ps |
CPU time | 0.8 seconds |
Started | Aug 15 04:35:24 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-42d9e8f8-e87e-4528-a608-2a2960e81fde |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770828686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1770828686 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3089857323 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 975093040 ps |
CPU time | 2.6 seconds |
Started | Aug 15 04:35:22 PM PDT 24 |
Finished | Aug 15 04:35:25 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-c9587c59-18c0-4858-93ed-c4b235384661 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089857323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3 089857323 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2661871551 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 103227664 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:35:26 PM PDT 24 |
Finished | Aug 15 04:35:26 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-a12e2c70-9da6-4324-ac82-55c47efb5b96 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661871551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.2661871551 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3805749594 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 221320878 ps |
CPU time | 0.73 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:34 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-6a78eb27-9237-4af8-9889-96af78a144af |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805749594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3805749594 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2469723479 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 433363942 ps |
CPU time | 3.41 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:29 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-c95c1374-d497-48db-8508-5bc1a091adda |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469723479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.2469723479 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3435865844 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 961797378 ps |
CPU time | 22.46 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:56 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-e4ffbb62-cbf7-458c-9c86-d200d57a6f6b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435865844 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3435865844 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1087622426 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 142853137 ps |
CPU time | 2.25 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:37 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-29029c1e-fe6e-4e40-9ef2-f31a0b537d71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087622426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1087622426 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3702608693 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 294730943 ps |
CPU time | 3.36 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:43 PM PDT 24 |
Peak memory | 218852 kb |
Host | smart-85eb2689-03f9-4026-a6eb-044e20b4ba7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702608693 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3702608693 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.495030855 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 100434076 ps |
CPU time | 1.47 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:39 PM PDT 24 |
Peak memory | 213196 kb |
Host | smart-d0178dfe-36be-43f5-8688-7d137b86dc97 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495030855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.495030855 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4211909918 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 13007401721 ps |
CPU time | 4.82 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:30 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-12f8dc92-0feb-4f4a-9d0f-1073feec0d7c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211909918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.4211909918 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3407535937 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 3028302231 ps |
CPU time | 5.31 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:40 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-56e39948-d580-4063-92d4-d3775af0341c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407535937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 407535937 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.161571914 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 515791880 ps |
CPU time | 1.1 seconds |
Started | Aug 15 04:35:25 PM PDT 24 |
Finished | Aug 15 04:35:26 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-b7f9c62d-a46d-4b48-85b3-7414f352d85d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161571914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.161571914 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2110671826 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 3321123531 ps |
CPU time | 4.03 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:44 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-4018217b-aa4c-4834-a7d1-d5225d3b7cca |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110671826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.2110671826 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2981437706 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 688752581 ps |
CPU time | 4.43 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-809684eb-e8a1-473a-865c-46792f690e51 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981437706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2981437706 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1409040892 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 2860733533 ps |
CPU time | 21.39 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:36:02 PM PDT 24 |
Peak memory | 221544 kb |
Host | smart-3adfe7b2-e8b4-4e9f-87ed-0c82cfe501eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409040892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1409040892 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1494867714 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 82690514 ps |
CPU time | 2.44 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:43 PM PDT 24 |
Peak memory | 218852 kb |
Host | smart-29bda1d0-d145-4c79-aaa3-13d828d39449 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494867714 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1494867714 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.978500449 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 169617491 ps |
CPU time | 2.05 seconds |
Started | Aug 15 04:35:32 PM PDT 24 |
Finished | Aug 15 04:35:35 PM PDT 24 |
Peak memory | 218948 kb |
Host | smart-047e97fb-0603-4142-a7a9-38e9db24713c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978500449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.978500449 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.692060970 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 28629676721 ps |
CPU time | 22.64 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:58 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-7faba986-fb90-4760-9e0b-9bbe48eb9aca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692060970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r v_dm_jtag_dmi_csr_bit_bash.692060970 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4128388453 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 2012614879 ps |
CPU time | 1.49 seconds |
Started | Aug 15 04:35:32 PM PDT 24 |
Finished | Aug 15 04:35:34 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-82837e80-30c0-4edb-9fb5-e8b299865975 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128388453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.4 128388453 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.35469135 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 301592396 ps |
CPU time | 0.88 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-59eb7b87-d4e3-4b69-80ee-c51acfbddd67 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35469135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.35469135 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2479968521 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 692842905 ps |
CPU time | 6.4 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:46 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-2824b4fb-49e3-4d78-8d74-726cf3f953d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479968521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.2479968521 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.331397199 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 4695999719 ps |
CPU time | 101.25 seconds |
Started | Aug 15 04:35:32 PM PDT 24 |
Finished | Aug 15 04:37:13 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-abe6696d-328b-4340-9736-5ffec275ea1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331397199 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.331397199 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2652653233 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 553707639 ps |
CPU time | 5.42 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-92661f04-329b-4260-9e64-3aaf49b19a4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652653233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2652653233 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3679795087 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 2646747694 ps |
CPU time | 20.2 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:53 PM PDT 24 |
Peak memory | 221580 kb |
Host | smart-86c0656b-5768-41c0-906c-594421d809cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679795087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3679795087 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1919173932 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 246762222 ps |
CPU time | 3.87 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 219680 kb |
Host | smart-34438966-d95e-4083-b12d-c57d4c02cf44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919173932 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1919173932 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.916431558 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 257841837 ps |
CPU time | 1.61 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:34 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-cf109d77-f4c5-4c7e-b4fb-bfc2e5812867 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916431558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.916431558 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3301567789 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 41330048779 ps |
CPU time | 32.25 seconds |
Started | Aug 15 04:35:32 PM PDT 24 |
Finished | Aug 15 04:36:04 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-1c4d1644-79ac-49b0-b63e-1d7e87a6908c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301567789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.3301567789 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1598350464 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 3100806218 ps |
CPU time | 9.03 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-adec39e8-a3e0-48ac-8a18-432e896b5b19 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598350464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1 598350464 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4288066268 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 172964033 ps |
CPU time | 0.73 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-e1ff3cfd-093b-479f-a102-a1a2423f3bd9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288066268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4 288066268 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4056172390 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 268665159 ps |
CPU time | 4.56 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:42 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-c8444828-4986-48de-acea-e88598a23767 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056172390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.4056172390 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.770907910 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 6205318665 ps |
CPU time | 30.55 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:36:08 PM PDT 24 |
Peak memory | 221592 kb |
Host | smart-72b11c0e-868e-491b-9695-6f4674a3634f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770907910 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.770907910 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1577481894 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 2521737368 ps |
CPU time | 3.6 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:40 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-604dfa63-926d-44f7-b382-e99f0305bc32 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577481894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1577481894 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1425420321 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 76904189 ps |
CPU time | 1.69 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 214324 kb |
Host | smart-404c286f-85f4-4f0c-a618-4f281532042e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425420321 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1425420321 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1439317920 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 543765497 ps |
CPU time | 2.51 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 218768 kb |
Host | smart-6c478c60-eea5-476c-b820-81c4df370bb7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439317920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1439317920 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1860465723 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 24171539355 ps |
CPU time | 60.81 seconds |
Started | Aug 15 04:35:34 PM PDT 24 |
Finished | Aug 15 04:36:34 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-72a43074-0e1c-467e-a0ea-493e25337e26 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860465723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.1860465723 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.796045443 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1480403942 ps |
CPU time | 4.99 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:46 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-953b959e-b2fe-4940-a310-fd7536b69964 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796045443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.796045443 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3875776640 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 405515475 ps |
CPU time | 1.83 seconds |
Started | Aug 15 04:35:37 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-189359bd-3aa3-47d1-8894-6c21cce07a39 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875776640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 875776640 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1588742770 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 583803984 ps |
CPU time | 4.26 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:37 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-98fe304e-8bfc-4fa3-be0a-e4ec95992355 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588742770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.1588742770 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2067860021 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 137300389 ps |
CPU time | 2.77 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:35:38 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-26f35b9d-a095-4941-a831-027c3bdcaf9a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067860021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2067860021 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.378020884 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 4930092197 ps |
CPU time | 22.69 seconds |
Started | Aug 15 04:35:38 PM PDT 24 |
Finished | Aug 15 04:36:01 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-21e66bef-0a1d-4103-a119-e888f57361b4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378020884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.378020884 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1613278554 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 124595058 ps |
CPU time | 2.43 seconds |
Started | Aug 15 04:35:41 PM PDT 24 |
Finished | Aug 15 04:35:43 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-e31cdc9e-4b7a-4682-b68e-078f98db812b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613278554 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1613278554 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1829353498 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 117166696 ps |
CPU time | 2.35 seconds |
Started | Aug 15 04:35:33 PM PDT 24 |
Finished | Aug 15 04:35:35 PM PDT 24 |
Peak memory | 218356 kb |
Host | smart-e30120bc-ad81-4d73-811d-37af808b7fa6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829353498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1829353498 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2919865737 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 42002231440 ps |
CPU time | 100.86 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:37:16 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-066c93a1-9d94-4740-bcd1-1a2bc71007e0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919865737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2919865737 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3822220241 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 1027679203 ps |
CPU time | 1.52 seconds |
Started | Aug 15 04:35:50 PM PDT 24 |
Finished | Aug 15 04:35:52 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-0c087d7c-eae1-495a-a074-0acf868c3755 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822220241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 822220241 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1621972084 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 227291323 ps |
CPU time | 1.26 seconds |
Started | Aug 15 04:35:40 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-0618b370-b6ac-420d-909f-a8e2b59a948f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621972084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 621972084 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.37329085 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 488740749 ps |
CPU time | 6.45 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:35:45 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-d8789732-4198-4648-8ba2-9a2e34f3f334 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs r_outstanding.37329085 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1774442505 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 14168153473 ps |
CPU time | 33.18 seconds |
Started | Aug 15 04:35:35 PM PDT 24 |
Finished | Aug 15 04:36:09 PM PDT 24 |
Peak memory | 217284 kb |
Host | smart-005fbee2-8bc1-4c86-a7d4-750e9bd7c48e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774442505 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1774442505 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.585603373 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 147450902 ps |
CPU time | 4.99 seconds |
Started | Aug 15 04:35:36 PM PDT 24 |
Finished | Aug 15 04:35:41 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-f3abd100-4feb-4bb1-8237-f8e53117c389 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585603373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.585603373 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2407799798 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1677303477 ps |
CPU time | 17.45 seconds |
Started | Aug 15 04:35:39 PM PDT 24 |
Finished | Aug 15 04:36:07 PM PDT 24 |
Peak memory | 215644 kb |
Host | smart-96024fb7-718e-4275-a768-765ffd343bca |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407799798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2407799798 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.3509605729 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 585812204 ps |
CPU time | 1.53 seconds |
Started | Aug 15 04:39:41 PM PDT 24 |
Finished | Aug 15 04:39:43 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-8949868f-399b-47e0-bebb-e32c5a1f5130 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509605729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3509605729 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.3705856407 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 84680995 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:40 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-f949be43-e3cf-4adf-bdc8-a28c049acbee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705856407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3705856407 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1424405635 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 20670219471 ps |
CPU time | 5.57 seconds |
Started | Aug 15 04:39:20 PM PDT 24 |
Finished | Aug 15 04:39:26 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-2b694f39-58bb-4c88-a71b-64aa416f6d83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424405635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1424405635 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1401112738 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 1094848109 ps |
CPU time | 1.73 seconds |
Started | Aug 15 04:39:23 PM PDT 24 |
Finished | Aug 15 04:39:25 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-b90f0ea4-85ce-440d-b7f9-bfe070eb1bab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401112738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1401112738 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_buffered_enable.2053952411 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 240054881 ps |
CPU time | 1.04 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 234660 kb |
Host | smart-36ed8613-9af4-4c49-a86b-ee656d3f8700 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053952411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.2053952411 |
Directory | /workspace/0.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2921104766 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 241373953 ps |
CPU time | 0.97 seconds |
Started | Aug 15 04:39:25 PM PDT 24 |
Finished | Aug 15 04:39:26 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-bb1040aa-d76c-48d2-81eb-646f4dd2f40d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921104766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2921104766 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.724798765 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 440853939 ps |
CPU time | 1.03 seconds |
Started | Aug 15 04:39:24 PM PDT 24 |
Finished | Aug 15 04:39:26 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-a787e34e-4872-43c6-9497-6a5c996d36ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724798765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.724798765 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.184944935 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 91151317 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:30 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-a3568367-2bfc-4a17-b9cf-73a419a7ab43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184944935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.184944935 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.305967181 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 101434821 ps |
CPU time | 0.89 seconds |
Started | Aug 15 04:39:43 PM PDT 24 |
Finished | Aug 15 04:39:44 PM PDT 24 |
Peak memory | 214904 kb |
Host | smart-88a73067-99bc-4a05-a731-7da31996d4eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=305967181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.305967181 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2451576534 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2323895994 ps |
CPU time | 3.04 seconds |
Started | Aug 15 04:39:19 PM PDT 24 |
Finished | Aug 15 04:39:23 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-cd44bed4-0b39-4cb8-abcf-ac131153911b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2451576534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.2451576534 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.4124368613 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 276307237 ps |
CPU time | 0.98 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:30 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-54dae099-3d2c-4ce0-9303-435c98ef15f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4124368613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.4124368613 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1273057995 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 58432784 ps |
CPU time | 0.85 seconds |
Started | Aug 15 04:39:41 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-f6a56ce4-c318-40ec-8cd3-44fd4b70eafb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273057995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1273057995 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.688526872 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 134205770 ps |
CPU time | 0.84 seconds |
Started | Aug 15 04:39:41 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-21077141-6c93-47fe-8a5f-bf446c86d814 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688526872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.688526872 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3809251874 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 649936647 ps |
CPU time | 1.6 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-3b3a8e03-f194-495f-83f4-3c7f59c59e3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809251874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3809251874 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4278084628 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 521906256 ps |
CPU time | 1.01 seconds |
Started | Aug 15 04:39:30 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-3b3d5083-98dc-4820-b914-58c7898bf83e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278084628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4278084628 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.537292889 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 412163812 ps |
CPU time | 1.05 seconds |
Started | Aug 15 04:39:27 PM PDT 24 |
Finished | Aug 15 04:39:28 PM PDT 24 |
Peak memory | 203904 kb |
Host | smart-d1f09a02-fcd4-4ebd-97c8-8bfa2789bf43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537292889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.537292889 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3757746989 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 312955110 ps |
CPU time | 1.15 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:30 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-2ff19bd4-ed2b-4165-8f02-6e46d2873408 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757746989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3757746989 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.412535884 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 173728621 ps |
CPU time | 0.82 seconds |
Started | Aug 15 04:39:21 PM PDT 24 |
Finished | Aug 15 04:39:22 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-b5644be7-d72e-4f80-8ad1-508da93bfc2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412535884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.412535884 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.749192839 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 191538074 ps |
CPU time | 1.22 seconds |
Started | Aug 15 04:39:30 PM PDT 24 |
Finished | Aug 15 04:39:32 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-80b7ca43-2486-41b6-90ca-e6a5be3c7d81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749192839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.749192839 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.3528800346 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 359666008 ps |
CPU time | 0.94 seconds |
Started | Aug 15 04:39:28 PM PDT 24 |
Finished | Aug 15 04:39:29 PM PDT 24 |
Peak memory | 213056 kb |
Host | smart-a5b7330a-398d-43dd-847c-6330cbd46b91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528800346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3528800346 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3158392297 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 269366693 ps |
CPU time | 1.47 seconds |
Started | Aug 15 04:39:29 PM PDT 24 |
Finished | Aug 15 04:39:31 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-32dc8127-b8db-44b8-bd2e-13f33d098fbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158392297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3158392297 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2943811341 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 3320628689 ps |
CPU time | 5.66 seconds |
Started | Aug 15 04:39:21 PM PDT 24 |
Finished | Aug 15 04:39:27 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-e5a878a6-18d9-4a30-87bd-df0d35846c67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943811341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2943811341 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.53778554 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 3440672355 ps |
CPU time | 5.79 seconds |
Started | Aug 15 04:39:21 PM PDT 24 |
Finished | Aug 15 04:39:27 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-85f37681-a974-41c9-b0a5-7fe47bc8a508 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53778554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.53778554 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.911034606 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 4075974806 ps |
CPU time | 4.2 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:44 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-b7417a46-7664-48f9-accb-3df1581b7620 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911034606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.911034606 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.833672550 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 3606294898 ps |
CPU time | 6.8 seconds |
Started | Aug 15 04:39:20 PM PDT 24 |
Finished | Aug 15 04:39:27 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-04b03004-afc9-420c-b6bb-012ab6f61edb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833672550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.833672550 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.868397327 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 154076452 ps |
CPU time | 1.1 seconds |
Started | Aug 15 04:39:48 PM PDT 24 |
Finished | Aug 15 04:39:49 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-3808eb38-7023-42c6-bc36-dbaf03bfc28f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868397327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.868397327 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1975827500 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 72112479 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:39:47 PM PDT 24 |
Finished | Aug 15 04:39:48 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-cc11c931-0e24-448d-a46f-cb70cd08403d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975827500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1975827500 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.179190583 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 6882263027 ps |
CPU time | 12.01 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:52 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-e6256cc3-e6aa-460e-bd9c-ed6039c80535 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179190583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.179190583 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1507334762 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 4111324441 ps |
CPU time | 2.33 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-020fe5a9-d529-46ba-af2f-468e9fdfc721 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507334762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1507334762 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_buffered_enable.1185613143 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 173714076 ps |
CPU time | 1.28 seconds |
Started | Aug 15 04:39:47 PM PDT 24 |
Finished | Aug 15 04:39:49 PM PDT 24 |
Peak memory | 234224 kb |
Host | smart-a1d4fac7-bd92-43eb-99c6-21a0292e247e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185613143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.1185613143 |
Directory | /workspace/1.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2125152273 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 465602437 ps |
CPU time | 1.29 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:41 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-b37afdfe-2c31-43d2-bf0f-5421fdcd52a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125152273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2125152273 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2456121991 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 271309303 ps |
CPU time | 1 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:41 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-d2dbc646-bb67-4e2e-9775-17137c5d690c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456121991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2456121991 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3898231542 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 669274568 ps |
CPU time | 1.67 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-316e2a68-c5c5-4af6-a4a4-5eb5d64c723b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898231542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3898231542 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1196219732 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 582771008 ps |
CPU time | 1.15 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:41 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-1f3b7427-9751-442c-a7b7-b47050b672d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196219732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1196219732 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1930218149 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 267224735 ps |
CPU time | 0.92 seconds |
Started | Aug 15 04:39:41 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-3803c8e1-c369-43a9-b2b8-25070fcd8739 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930218149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1930218149 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.3336097642 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 42896340 ps |
CPU time | 0.92 seconds |
Started | Aug 15 04:39:48 PM PDT 24 |
Finished | Aug 15 04:39:49 PM PDT 24 |
Peak memory | 215052 kb |
Host | smart-45ccae52-8d22-493e-ad8b-068653a5f467 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336097642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3336097642 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2578917351 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1690098366 ps |
CPU time | 3.86 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:44 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-5a589480-dfdd-4dd9-9e23-141786440413 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2578917351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.2578917351 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.3734584944 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 535416090 ps |
CPU time | 1.37 seconds |
Started | Aug 15 04:39:49 PM PDT 24 |
Finished | Aug 15 04:39:50 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-2c14a387-d41f-4c25-b07d-a9cf882989f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734584944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3734584944 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.762800672 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 824675142 ps |
CPU time | 1.75 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:41 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-0ef99561-f007-4f40-a2b7-9b07f882aec3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762800672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.762800672 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.2685147963 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 237397308 ps |
CPU time | 0.89 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:41 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-206dd101-9003-4298-a896-d555ef734a0a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685147963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2685147963 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2191945542 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 668912769 ps |
CPU time | 1.14 seconds |
Started | Aug 15 04:39:48 PM PDT 24 |
Finished | Aug 15 04:39:49 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-4603a5e9-6e4c-4493-a4bd-ab8cf5d18b73 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191945542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2191945542 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4180641319 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 304293383 ps |
CPU time | 0.92 seconds |
Started | Aug 15 04:39:51 PM PDT 24 |
Finished | Aug 15 04:39:52 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-0edc7765-9613-4f83-8303-3988b0f157cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180641319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4180641319 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2316559690 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 122138785 ps |
CPU time | 0.86 seconds |
Started | Aug 15 04:39:49 PM PDT 24 |
Finished | Aug 15 04:39:50 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-81cc48fc-529c-4399-b0b5-d41825cb8418 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2316559690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2316559690 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3035641564 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 114237888 ps |
CPU time | 0.8 seconds |
Started | Aug 15 04:39:47 PM PDT 24 |
Finished | Aug 15 04:39:48 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-cc16d59e-fbfd-4f97-b03a-691db53bd803 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035641564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3035641564 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2586031929 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 95636745 ps |
CPU time | 0.92 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:41 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-f938ba9b-92a2-4621-9404-8539be05e223 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586031929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2586031929 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1714737937 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 588862394 ps |
CPU time | 1.53 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-a3a68cba-07e2-497f-a28c-3c6996db0500 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714737937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1714737937 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.947033350 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 350332699 ps |
CPU time | 1.51 seconds |
Started | Aug 15 04:39:48 PM PDT 24 |
Finished | Aug 15 04:39:50 PM PDT 24 |
Peak memory | 213060 kb |
Host | smart-f29dac60-17aa-495f-8c15-137e488c8609 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947033350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.947033350 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3047057664 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 1061529519 ps |
CPU time | 1.01 seconds |
Started | Aug 15 04:39:51 PM PDT 24 |
Finished | Aug 15 04:39:52 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-d7999963-b4bc-47a6-bbbe-9c0824ce2a47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047057664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3047057664 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.918135757 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 92224889 ps |
CPU time | 1.05 seconds |
Started | Aug 15 04:39:51 PM PDT 24 |
Finished | Aug 15 04:39:52 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-a72f7641-0910-43a1-b80b-cbca9d4e1dd4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918135757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.918135757 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1113452421 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 1808297100 ps |
CPU time | 5.1 seconds |
Started | Aug 15 04:39:38 PM PDT 24 |
Finished | Aug 15 04:39:43 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-139eed34-b425-4129-8753-cd1bada9fbbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113452421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1113452421 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.2331426701 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 2647955039 ps |
CPU time | 3.21 seconds |
Started | Aug 15 04:39:39 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-7251e824-505c-49d8-b38f-84f45922d65b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331426701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2331426701 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.420945048 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 485870270 ps |
CPU time | 2.27 seconds |
Started | Aug 15 04:39:50 PM PDT 24 |
Finished | Aug 15 04:39:52 PM PDT 24 |
Peak memory | 229496 kb |
Host | smart-0425281b-82cc-434a-a6be-b956ea5ee93b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420945048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.420945048 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2016599993 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 3129293533 ps |
CPU time | 2.24 seconds |
Started | Aug 15 04:39:40 PM PDT 24 |
Finished | Aug 15 04:39:42 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-324bf845-9fc1-4627-9dc6-fd8930191fb0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016599993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2016599993 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.294499538 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 284121585 ps |
CPU time | 1 seconds |
Started | Aug 15 04:39:50 PM PDT 24 |
Finished | Aug 15 04:39:51 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-a985c9ca-096a-4029-bb50-92d0628c2cc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294499538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.294499538 |
Directory | /workspace/1.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.733828262 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 8476190864 ps |
CPU time | 8.35 seconds |
Started | Aug 15 04:39:47 PM PDT 24 |
Finished | Aug 15 04:39:56 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-46582311-4458-42e0-a749-12967c312729 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733828262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.733828262 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.470289110 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 5570288791 ps |
CPU time | 16.79 seconds |
Started | Aug 15 04:39:49 PM PDT 24 |
Finished | Aug 15 04:40:05 PM PDT 24 |
Peak memory | 221644 kb |
Host | smart-6f3d6741-43f5-4747-86a2-4eb2eff4d1c1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470289110 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.470289110 |
Directory | /workspace/1.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.2314032936 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 175448450 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:21 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-e7d454c6-03b5-4c8f-8db2-e080e3c31fbf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314032936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2314032936 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1121146213 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 208974148389 ps |
CPU time | 207.3 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:43:48 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-d1ad993b-a27d-4aa2-bc41-4c1ad4e5c2eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121146213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1121146213 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3968853398 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2747081077 ps |
CPU time | 4.47 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:26 PM PDT 24 |
Peak memory | 213948 kb |
Host | smart-d302e9d7-9813-4912-9167-fdc7c83aeee9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968853398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3968853398 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2913483500 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 9524645506 ps |
CPU time | 29.02 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:51 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-ba818300-1be3-4d56-a9c5-d8dae6938d43 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2913483500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2913483500 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3935151726 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 3838941985 ps |
CPU time | 3.1 seconds |
Started | Aug 15 04:40:19 PM PDT 24 |
Finished | Aug 15 04:40:23 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-9574dca6-366c-47d5-b0f0-f4f9d98e84a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935151726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3935151726 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.417090003 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 3483502744 ps |
CPU time | 9.95 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:40:30 PM PDT 24 |
Peak memory | 213264 kb |
Host | smart-cd46e894-c62f-46f8-806a-e80ee3ad7844 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417090003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.417090003 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.2589038135 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 71979101 ps |
CPU time | 0.86 seconds |
Started | Aug 15 04:40:25 PM PDT 24 |
Finished | Aug 15 04:40:26 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-426fb210-e92b-4830-b2a4-459b98a005ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589038135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2589038135 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1057537227 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 6633124889 ps |
CPU time | 18.97 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:40:39 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-d8288c48-2663-4645-a2c2-0f8730d18443 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057537227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1057537227 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3518403266 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 8739903173 ps |
CPU time | 4.22 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:25 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-dbd34671-7ce0-43ce-85ee-4b3ef9a28768 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518403266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3518403266 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3670786734 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 1894309789 ps |
CPU time | 2.17 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:23 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-2eeea822-b99e-45d7-81c7-b71672ca616c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3670786734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3670786734 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.3803615809 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 6475285575 ps |
CPU time | 9.93 seconds |
Started | Aug 15 04:40:24 PM PDT 24 |
Finished | Aug 15 04:40:34 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-8ed373aa-3548-4e08-8c0a-f976638dcd85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803615809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3803615809 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.3780046881 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 3949792782 ps |
CPU time | 9.48 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:40:30 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-0633c9d5-47ce-4453-892f-d56da0d26d77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780046881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3780046881 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.4266303177 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 37044570 ps |
CPU time | 0.7 seconds |
Started | Aug 15 04:40:22 PM PDT 24 |
Finished | Aug 15 04:40:23 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-e840410d-17eb-446e-ade8-6b3d83c31f13 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266303177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.4266303177 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.836213843 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 1511860926 ps |
CPU time | 5.7 seconds |
Started | Aug 15 04:40:19 PM PDT 24 |
Finished | Aug 15 04:40:25 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-4b4d12c7-908f-4d3e-8e9c-2164fc77138b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=836213843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.836213843 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.358623955 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 4654410841 ps |
CPU time | 4.67 seconds |
Started | Aug 15 04:40:19 PM PDT 24 |
Finished | Aug 15 04:40:24 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-758dde79-c26d-4bd7-8cf0-52ab6a84c857 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=358623955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t l_access.358623955 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.3853420495 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 3648110788 ps |
CPU time | 10.96 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:32 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-55f2fcc3-dea2-47d2-82dc-bc2078fb9d4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853420495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3853420495 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.1030167923 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 2355638181 ps |
CPU time | 7.26 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:29 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-644327b2-8283-45c6-87b0-bfe6c95a9dc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030167923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1030167923 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1927907347 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 46715567 ps |
CPU time | 0.74 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:40:21 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-16ced712-3ac4-447b-8bdc-2f2691b37ca9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927907347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1927907347 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.507673770 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 3904013978 ps |
CPU time | 3.73 seconds |
Started | Aug 15 04:40:22 PM PDT 24 |
Finished | Aug 15 04:40:26 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-52da9635-cd9b-4d16-a2fa-99cd92cbad6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507673770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.507673770 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2428462030 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 3260439879 ps |
CPU time | 5.59 seconds |
Started | Aug 15 04:40:22 PM PDT 24 |
Finished | Aug 15 04:40:28 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-8b4575cf-9a58-4dd7-93d9-55091879d52c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428462030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2428462030 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3121328528 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 3224196162 ps |
CPU time | 10.04 seconds |
Started | Aug 15 04:40:22 PM PDT 24 |
Finished | Aug 15 04:40:32 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-5ccba4b5-4846-4cd0-af17-ca2a51f46bb0 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3121328528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.3121328528 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.1945216202 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 7771109628 ps |
CPU time | 6.57 seconds |
Started | Aug 15 04:40:25 PM PDT 24 |
Finished | Aug 15 04:40:32 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-72aa21f2-a482-4ace-b057-bc8437c9653e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945216202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1945216202 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.1448920637 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 11921929960 ps |
CPU time | 13.08 seconds |
Started | Aug 15 04:40:22 PM PDT 24 |
Finished | Aug 15 04:40:35 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-52647d2b-6b26-4328-a9f0-b01e7b3acec0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448920637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1448920637 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.830982624 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 90192666104 ps |
CPU time | 24.33 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:56 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-4fd96ebf-6949-4955-ae8d-970820b3e755 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830982624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.830982624 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1776717536 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 6047175828 ps |
CPU time | 8.42 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:29 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-d890c7b7-18a9-4b6f-b197-858916a60c34 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1776717536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.1776717536 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.1446448361 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2831815741 ps |
CPU time | 2.96 seconds |
Started | Aug 15 04:40:25 PM PDT 24 |
Finished | Aug 15 04:40:28 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-9ec9b2d4-53b6-435f-99a2-9e1aed24e563 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446448361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1446448361 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.3758478690 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 3328563268 ps |
CPU time | 9 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-839bf9e5-0655-49ef-a824-d6175e3afe91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758478690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3758478690 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.352305751 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 124665726 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:33 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-0303dbb9-7232-4991-99aa-a81ed331a881 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352305751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.352305751 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2929277228 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 3155985515 ps |
CPU time | 8.38 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-6d5fe20f-b669-498b-9560-aaa86e4fa41a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929277228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2929277228 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1402966611 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1077591964 ps |
CPU time | 4.11 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:37 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-980442eb-975b-4d78-b369-79ae4a7bff3d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1402966611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.1402966611 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.3291068245 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 895072293 ps |
CPU time | 2.35 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:35 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-1d5e3774-cad6-446e-b951-44e0de6aa20b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291068245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3291068245 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.3142603264 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 2711232566 ps |
CPU time | 2.29 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:35 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-d1d1295c-e05d-4b7f-9d0f-f0b18ad38a9b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142603264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3142603264 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.1722545395 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 164183907 ps |
CPU time | 0.8 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:32 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-812c7a66-56eb-4b7b-bd23-e443d07ebf6e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722545395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1722545395 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3122743227 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 11327026253 ps |
CPU time | 11.77 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-faf0a4e5-26b1-447d-93fa-20a96c3b1c28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122743227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3122743227 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1435519237 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 9605943321 ps |
CPU time | 19.84 seconds |
Started | Aug 15 04:40:34 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-247ad834-9a67-40ce-9fa7-417c4230c7de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435519237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1435519237 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2759905262 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 5923525550 ps |
CPU time | 9.94 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:41 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-47e88c71-3d8e-4c94-bcc8-e6515f515d92 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2759905262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.2759905262 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.2111447785 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 4316365077 ps |
CPU time | 11.26 seconds |
Started | Aug 15 04:40:30 PM PDT 24 |
Finished | Aug 15 04:40:41 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-9af9792c-cd9c-4f5c-abf4-28c85b025a8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111447785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2111447785 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.2121196250 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 1931145951 ps |
CPU time | 3.39 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:36 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-8215f5a3-8fee-47c6-b1d3-4ec609d18de4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121196250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2121196250 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2448789506 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 136532136 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:40:34 PM PDT 24 |
Finished | Aug 15 04:40:35 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-45f0d30d-48d5-40b5-896d-d5dea656dea0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448789506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2448789506 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.766069844 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 2199051388 ps |
CPU time | 7.08 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-e03aca3c-1a6e-4cf6-9436-175171ae8379 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766069844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.766069844 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1978231176 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 5007635386 ps |
CPU time | 6.73 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:38 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-4aa5402a-74c4-48b3-b401-4407848395fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978231176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1978231176 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1552376097 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 1855038287 ps |
CPU time | 2.43 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:34 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-e5a79dac-0f24-46e8-9c7c-a906c4e51c24 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1552376097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.1552376097 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.3963949719 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 3715822625 ps |
CPU time | 6.39 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:39 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-647bb74f-09e0-4801-9cc5-1e5e8b4a373e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963949719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3963949719 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.2966431391 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 85652300 ps |
CPU time | 0.81 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:32 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-6e73504b-9bb7-41ac-b673-e99db414c6a7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966431391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2966431391 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1293751533 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 6519973137 ps |
CPU time | 7.43 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-6e40bda1-9cbd-4ff4-b7b0-3c766cfa65be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293751533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1293751533 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3515686882 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2361626131 ps |
CPU time | 4.93 seconds |
Started | Aug 15 04:40:33 PM PDT 24 |
Finished | Aug 15 04:40:38 PM PDT 24 |
Peak memory | 214528 kb |
Host | smart-4f94ff9e-c43b-4778-b0bc-925145570a9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515686882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3515686882 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.713151202 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 685534642 ps |
CPU time | 1.42 seconds |
Started | Aug 15 04:40:31 PM PDT 24 |
Finished | Aug 15 04:40:33 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-ed1d1cdf-7372-46ab-84dc-a496ebed166b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=713151202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t l_access.713151202 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.3777325771 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 1853043352 ps |
CPU time | 4.15 seconds |
Started | Aug 15 04:40:32 PM PDT 24 |
Finished | Aug 15 04:40:36 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-83906997-6995-435d-9159-e5bc91f13f56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777325771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3777325771 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.2675189362 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 113372859 ps |
CPU time | 1.01 seconds |
Started | Aug 15 04:40:35 PM PDT 24 |
Finished | Aug 15 04:40:36 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-fde1d64d-f081-469b-8030-36988b2f7f7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675189362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2675189362 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1553573087 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 5315800152 ps |
CPU time | 9.29 seconds |
Started | Aug 15 04:40:37 PM PDT 24 |
Finished | Aug 15 04:40:46 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-38311d03-9f77-4454-aa05-6e8fd809a67a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553573087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1553573087 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.185404223 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 12939767356 ps |
CPU time | 9.75 seconds |
Started | Aug 15 04:40:35 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-c85dd7be-1038-470f-9040-2c5512984eb7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185404223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.185404223 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1992537393 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 8926679109 ps |
CPU time | 9.63 seconds |
Started | Aug 15 04:40:36 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-917746f8-f508-46dc-a76d-d08cf4c70e31 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1992537393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.1992537393 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.3748603926 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 6509239179 ps |
CPU time | 5.85 seconds |
Started | Aug 15 04:40:41 PM PDT 24 |
Finished | Aug 15 04:40:47 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-539f3d92-f2bf-4a63-a684-79e38a89feb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748603926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3748603926 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.320521948 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 4244375463 ps |
CPU time | 4.72 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:44 PM PDT 24 |
Peak memory | 213784 kb |
Host | smart-2286a96f-ee66-4548-94a1-c8273b5bb1a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320521948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.320521948 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.232135433 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 59475738 ps |
CPU time | 0.73 seconds |
Started | Aug 15 04:39:55 PM PDT 24 |
Finished | Aug 15 04:39:56 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-726094c3-7ab0-4dba-a2d3-0383a6c99f37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232135433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.232135433 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3813901027 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 3435983298 ps |
CPU time | 4.42 seconds |
Started | Aug 15 04:39:50 PM PDT 24 |
Finished | Aug 15 04:39:54 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-8e033fa3-0b33-4aa9-93d0-673b7db44543 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813901027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3813901027 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_buffered_enable.4241188987 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 203559003 ps |
CPU time | 1.05 seconds |
Started | Aug 15 04:39:57 PM PDT 24 |
Finished | Aug 15 04:39:58 PM PDT 24 |
Peak memory | 226568 kb |
Host | smart-5e207de3-87d7-4eb3-9f6d-92726c23cd06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241188987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.4241188987 |
Directory | /workspace/2.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.213611418 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 4217252008 ps |
CPU time | 7.27 seconds |
Started | Aug 15 04:39:49 PM PDT 24 |
Finished | Aug 15 04:39:56 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-b01b1791-bae8-4766-80e3-80fb56633780 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=213611418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl _access.213611418 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1629116055 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 165584924 ps |
CPU time | 1.25 seconds |
Started | Aug 15 04:39:57 PM PDT 24 |
Finished | Aug 15 04:39:59 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-429ef3c3-64b5-454c-9dbd-4bff4290c894 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629116055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1629116055 |
Directory | /workspace/2.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.3653415820 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 292501527 ps |
CPU time | 1.44 seconds |
Started | Aug 15 04:39:48 PM PDT 24 |
Finished | Aug 15 04:39:50 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-2aed7232-0875-47c8-b6ee-bd3cf1ab6c71 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653415820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3653415820 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.3628435043 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1860385445 ps |
CPU time | 5.3 seconds |
Started | Aug 15 04:39:48 PM PDT 24 |
Finished | Aug 15 04:39:54 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-3e3084e3-3dc2-4ab0-ae18-2b3b5db86233 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628435043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3628435043 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.11846293 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 2735807432 ps |
CPU time | 4.31 seconds |
Started | Aug 15 04:39:55 PM PDT 24 |
Finished | Aug 15 04:39:59 PM PDT 24 |
Peak memory | 229148 kb |
Host | smart-f378544f-270b-4c73-bde2-d8c7b8435eec |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11846293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.11846293 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1058878575 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 227796384 ps |
CPU time | 0.91 seconds |
Started | Aug 15 04:39:57 PM PDT 24 |
Finished | Aug 15 04:39:58 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-7fc3e688-cb75-409b-b05c-5ddbaa0944d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058878575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.1058878575 |
Directory | /workspace/2.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.3771391250 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 117226534 ps |
CPU time | 0.83 seconds |
Started | Aug 15 04:40:37 PM PDT 24 |
Finished | Aug 15 04:40:38 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-c7f48669-a47b-451c-9fb1-9f99900e2557 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771391250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3771391250 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.3350742068 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 6295296680 ps |
CPU time | 5.7 seconds |
Started | Aug 15 04:40:37 PM PDT 24 |
Finished | Aug 15 04:40:43 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-a14f924a-3382-402c-ac85-204c7b475f1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350742068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3350742068 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.430589362 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 59121983 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-0250abad-8d95-46ec-a087-ee42d823647d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430589362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.430589362 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.3474038881 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 5334589589 ps |
CPU time | 6.81 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-ca59b932-1043-4a29-9ad6-e17c78195ff2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474038881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3474038881 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.2197827366 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 58504901 ps |
CPU time | 0.77 seconds |
Started | Aug 15 04:40:37 PM PDT 24 |
Finished | Aug 15 04:40:38 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-4a05c6fb-0196-4070-9e22-be8d7b224466 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197827366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2197827366 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.1180884711 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 987780478 ps |
CPU time | 1.66 seconds |
Started | Aug 15 04:40:36 PM PDT 24 |
Finished | Aug 15 04:40:38 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-c8952aa9-0d3a-45e0-a84c-24ff8a5a6cbb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180884711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1180884711 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3125451304 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 60148950 ps |
CPU time | 0.89 seconds |
Started | Aug 15 04:40:38 PM PDT 24 |
Finished | Aug 15 04:40:39 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-765f9303-f9f5-49d3-a514-a29d8bac2c20 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125451304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3125451304 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.1534414234 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 4337722132 ps |
CPU time | 12.44 seconds |
Started | Aug 15 04:40:41 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-47d41a5e-0b4f-4419-892b-15a7b17185ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534414234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1534414234 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.410855305 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 64248651 ps |
CPU time | 0.77 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-152f8c55-065a-4c2b-8658-48e1f7385aa5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410855305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.410855305 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.1391269304 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 5736665991 ps |
CPU time | 5.43 seconds |
Started | Aug 15 04:40:35 PM PDT 24 |
Finished | Aug 15 04:40:41 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-3761e161-5079-4344-9a60-a14b5940d865 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391269304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1391269304 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.2904914796 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 63558145 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:40:38 PM PDT 24 |
Finished | Aug 15 04:40:39 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-6c53389c-348e-4d96-b3a7-f32e347cb844 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904914796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2904914796 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.2909486577 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 1328439917 ps |
CPU time | 4.04 seconds |
Started | Aug 15 04:40:36 PM PDT 24 |
Finished | Aug 15 04:40:41 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-330e8098-d3d1-4845-9f4f-dfca895a82ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909486577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2909486577 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2562602907 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 82689281 ps |
CPU time | 0.8 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-51af38a8-ae06-41e7-a83b-cb380495bfb1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562602907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2562602907 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.4264501777 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 141380199 ps |
CPU time | 0.94 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:40 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-8d8d7bc2-c56c-4964-9abc-c709e8bb2160 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264501777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4264501777 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.3578828479 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 2942820165 ps |
CPU time | 2.37 seconds |
Started | Aug 15 04:40:41 PM PDT 24 |
Finished | Aug 15 04:40:44 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-561bad21-5b41-402b-b464-5cc8d910f4ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578828479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3578828479 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.603827682 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 78043117 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:40:36 PM PDT 24 |
Finished | Aug 15 04:40:37 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-1e49cd5d-c193-46c6-a23c-6bb540a07214 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603827682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.603827682 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.4057507944 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3436105893 ps |
CPU time | 5.73 seconds |
Started | Aug 15 04:40:37 PM PDT 24 |
Finished | Aug 15 04:40:43 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-24504f91-d4dc-4332-bd7a-38aa6143f30d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057507944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.4057507944 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.2481432277 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 103280333 ps |
CPU time | 0.7 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-3979e551-372c-4ecd-96e4-3ddf53364d3f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481432277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2481432277 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.1039496676 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 4269004609 ps |
CPU time | 6.4 seconds |
Started | Aug 15 04:40:39 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-be23b7cb-608c-4d1a-80dd-709f42508dd0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039496676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1039496676 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.1605388641 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 153380231 ps |
CPU time | 0.74 seconds |
Started | Aug 15 04:39:58 PM PDT 24 |
Finished | Aug 15 04:39:59 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-12028c58-0e20-49c1-a674-3c59b8b86eb4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605388641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1605388641 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2078195936 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 2583369719 ps |
CPU time | 2.94 seconds |
Started | Aug 15 04:39:59 PM PDT 24 |
Finished | Aug 15 04:40:02 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-2370dadc-491d-491e-89c7-09260ca6d9fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078195936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2078195936 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.4088085362 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 11253081004 ps |
CPU time | 16.5 seconds |
Started | Aug 15 04:39:58 PM PDT 24 |
Finished | Aug 15 04:40:14 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-d6d50d3f-8157-4638-aa43-a96fb0cd3218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088085362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.4088085362 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_buffered_enable.2546835185 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 642049704 ps |
CPU time | 1.75 seconds |
Started | Aug 15 04:39:58 PM PDT 24 |
Finished | Aug 15 04:40:00 PM PDT 24 |
Peak memory | 230720 kb |
Host | smart-a360c71a-7dda-4db6-a493-8b46df53c35a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546835185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2546835185 |
Directory | /workspace/3.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.131758782 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 5848564656 ps |
CPU time | 5.35 seconds |
Started | Aug 15 04:39:59 PM PDT 24 |
Finished | Aug 15 04:40:04 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-31eb585e-bd14-4de7-ba7b-7ae4880f660e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=131758782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl _access.131758782 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_halt_resume_whereto.385622295 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 1200738703 ps |
CPU time | 1.75 seconds |
Started | Aug 15 04:39:59 PM PDT 24 |
Finished | Aug 15 04:40:01 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-fc70a2f8-6fbb-4f2f-a76f-2f4630657902 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385622295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.385622295 |
Directory | /workspace/3.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.649064425 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 149772716 ps |
CPU time | 0.76 seconds |
Started | Aug 15 04:39:56 PM PDT 24 |
Finished | Aug 15 04:39:57 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-32fb0719-9ee3-450b-9632-15e949facb1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649064425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.649064425 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.990741397 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 11195585466 ps |
CPU time | 9.37 seconds |
Started | Aug 15 04:39:55 PM PDT 24 |
Finished | Aug 15 04:40:05 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-7ce0e474-cfb6-4ce0-87ef-10cd2771ed06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990741397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.990741397 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.2451599408 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 331353833 ps |
CPU time | 2 seconds |
Started | Aug 15 04:39:57 PM PDT 24 |
Finished | Aug 15 04:40:00 PM PDT 24 |
Peak memory | 229584 kb |
Host | smart-145a0880-8f84-4514-8936-65b2afb7010c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451599408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2451599408 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3387132016 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 7752141801 ps |
CPU time | 22.44 seconds |
Started | Aug 15 04:39:57 PM PDT 24 |
Finished | Aug 15 04:40:20 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-eacbbb06-6d51-49f4-9b48-f6023926ac09 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387132016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3387132016 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.4150536947 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 17488310064 ps |
CPU time | 25.55 seconds |
Started | Aug 15 04:39:58 PM PDT 24 |
Finished | Aug 15 04:40:24 PM PDT 24 |
Peak memory | 217584 kb |
Host | smart-814795a3-7182-4703-9037-720116c086ba |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150536947 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.4150536947 |
Directory | /workspace/3.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.3538733420 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 27403967 ps |
CPU time | 0.8 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-40aa9432-f02f-4b6b-851e-60ebae72a1bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538733420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3538733420 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.1177156133 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1768127641 ps |
CPU time | 5.32 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:50 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-4907e405-12a1-4a72-a67b-dd6f29c85959 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177156133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1177156133 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.2112767760 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 119227142 ps |
CPU time | 0.9 seconds |
Started | Aug 15 04:40:47 PM PDT 24 |
Finished | Aug 15 04:40:48 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-045ec0ee-e277-41b2-814f-954f456ce0c8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112767760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2112767760 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.3325671782 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 66254518 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:46 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-01d5e6d1-e44c-4ab1-9c4b-026041c72b14 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325671782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3325671782 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.3858442437 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 1242671414 ps |
CPU time | 1.23 seconds |
Started | Aug 15 04:40:46 PM PDT 24 |
Finished | Aug 15 04:40:47 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-b6e0af35-316f-40d3-ab2f-981bb614b402 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858442437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3858442437 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1397202370 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 49671335 ps |
CPU time | 0.72 seconds |
Started | Aug 15 04:40:47 PM PDT 24 |
Finished | Aug 15 04:40:48 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-c98479b9-bee4-4b96-862d-fd6d29f17703 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397202370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1397202370 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.3617226790 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1671414898 ps |
CPU time | 2.54 seconds |
Started | Aug 15 04:40:47 PM PDT 24 |
Finished | Aug 15 04:40:50 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-fd39dd15-9b54-478e-9d6d-d7e41a17ba39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617226790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3617226790 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.985482195 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 62156424 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-2c356c93-0124-463f-90c4-1c70d5efbfff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985482195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.985482195 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.1387314288 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 3133682729 ps |
CPU time | 5.11 seconds |
Started | Aug 15 04:40:43 PM PDT 24 |
Finished | Aug 15 04:40:48 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-0e0d587e-c9fd-4b40-a414-d851ae89faec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387314288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1387314288 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.3442316322 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 66508498 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-b465f533-e304-401b-92c9-8f3c808f3418 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442316322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3442316322 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.1488501460 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 5291597182 ps |
CPU time | 3.35 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:48 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-162df13a-a969-4746-a577-bcbcca803008 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488501460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1488501460 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.3674635245 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 91355311 ps |
CPU time | 0.83 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-844ba02e-0943-4079-9a7a-e62b22e6797b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674635245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3674635245 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.3147433544 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 2258598071 ps |
CPU time | 6.5 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:52 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-0943f3cb-f5d9-46dc-a084-1ffdfa6cd277 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147433544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3147433544 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.3672445167 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 62146254 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:47 PM PDT 24 |
Finished | Aug 15 04:40:48 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-471cf55a-f1ce-4ae1-9bc2-c2375db5b54b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672445167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3672445167 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.2041305271 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 9629465895 ps |
CPU time | 9.01 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-f6b07345-800c-45d6-b82d-d58ca82ea743 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041305271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2041305271 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1424821735 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 106691474 ps |
CPU time | 0.76 seconds |
Started | Aug 15 04:40:47 PM PDT 24 |
Finished | Aug 15 04:40:48 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-26f14e4d-81df-4e1f-af77-eb44f9072f9d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424821735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1424821735 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.2247059500 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 4367152121 ps |
CPU time | 4.45 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:49 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-97ffa1b5-23c6-4fe9-af85-b04f33018fc5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247059500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2247059500 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.1180220162 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 42467936 ps |
CPU time | 0.77 seconds |
Started | Aug 15 04:40:44 PM PDT 24 |
Finished | Aug 15 04:40:45 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-74a9eed7-edf0-4027-9034-25dfb0f0e98d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180220162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1180220162 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.3857561286 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 3010174271 ps |
CPU time | 9.18 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:55 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-bea4a172-5019-4ebd-8e41-9e3842ae4912 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857561286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3857561286 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.241765615 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 123305727 ps |
CPU time | 0.85 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:05 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-e6ede87a-80a8-45d7-8f29-34dd4cc6b0f2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241765615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.241765615 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3104258084 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 11853060057 ps |
CPU time | 12.62 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:17 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-754ef295-280c-4063-af7f-5972d929dd72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104258084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3104258084 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.981327268 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 7054945426 ps |
CPU time | 3.33 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:07 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-993793cc-a498-4fc1-95df-e467660a79d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981327268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.981327268 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2465432642 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1907382368 ps |
CPU time | 2.28 seconds |
Started | Aug 15 04:40:03 PM PDT 24 |
Finished | Aug 15 04:40:06 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-74c5919d-0e32-4c8f-adf6-127ded0d8074 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2465432642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.2465432642 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_halt_resume_whereto.47048578 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 1431693273 ps |
CPU time | 3.33 seconds |
Started | Aug 15 04:40:06 PM PDT 24 |
Finished | Aug 15 04:40:10 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-158cc061-ad84-4c07-a451-3063a67a3651 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47048578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.47048578 |
Directory | /workspace/4.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1052534099 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 220288141 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:06 PM PDT 24 |
Finished | Aug 15 04:40:07 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-f3798844-fcaf-4c2b-9798-6d3ce3315c10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052534099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1052534099 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.3556502360 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 2852581058 ps |
CPU time | 9.24 seconds |
Started | Aug 15 04:39:56 PM PDT 24 |
Finished | Aug 15 04:40:05 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-538da600-9198-4ebe-97e0-d3f7fdeb69a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556502360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3556502360 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.3282107594 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 502955660 ps |
CPU time | 2.4 seconds |
Started | Aug 15 04:40:03 PM PDT 24 |
Finished | Aug 15 04:40:05 PM PDT 24 |
Peak memory | 229204 kb |
Host | smart-0f1ff4eb-5471-4b14-9a31-30c95cc35a45 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282107594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3282107594 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.1511537746 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 10173481485 ps |
CPU time | 28.16 seconds |
Started | Aug 15 04:40:02 PM PDT 24 |
Finished | Aug 15 04:40:31 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-d04903c8-a278-41c5-9426-4d879321420b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511537746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1511537746 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2283522411 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 3813840447 ps |
CPU time | 89 seconds |
Started | Aug 15 04:40:05 PM PDT 24 |
Finished | Aug 15 04:41:34 PM PDT 24 |
Peak memory | 221748 kb |
Host | smart-e44daae9-c7a9-455f-b705-972cec36d876 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283522411 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2283522411 |
Directory | /workspace/4.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.4003047322 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 72405073 ps |
CPU time | 0.8 seconds |
Started | Aug 15 04:40:45 PM PDT 24 |
Finished | Aug 15 04:40:46 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-b09ade09-4175-4066-9a5d-b2cf6d7a88fb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003047322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4003047322 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.1707419189 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 5911095094 ps |
CPU time | 5.64 seconds |
Started | Aug 15 04:40:43 PM PDT 24 |
Finished | Aug 15 04:40:49 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-e0fbeabd-44e0-400a-8c9c-6e66d82ec759 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707419189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1707419189 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.4125936551 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 194373158 ps |
CPU time | 0.95 seconds |
Started | Aug 15 04:40:55 PM PDT 24 |
Finished | Aug 15 04:40:56 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-2f2ab942-a9fe-43ff-a575-caf311e02661 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125936551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4125936551 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.2617193741 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 3123744195 ps |
CPU time | 10.05 seconds |
Started | Aug 15 04:40:43 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-807752ee-0337-4d9f-899e-4231e6a0c69f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617193741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2617193741 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3842221978 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 38671016 ps |
CPU time | 0.82 seconds |
Started | Aug 15 04:40:56 PM PDT 24 |
Finished | Aug 15 04:40:57 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-bea9b2cf-86c6-4e74-ab47-efccc8cd661f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842221978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3842221978 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.318913811 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 3273586788 ps |
CPU time | 10.38 seconds |
Started | Aug 15 04:40:53 PM PDT 24 |
Finished | Aug 15 04:41:03 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-c4bf9519-835e-4ccb-87c7-ec57673b92f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318913811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.318913811 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1095823380 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 118266591 ps |
CPU time | 0.72 seconds |
Started | Aug 15 04:40:53 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-c875de22-6ad7-4532-8c57-631ae2796ccb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095823380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1095823380 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.379115896 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3939344268 ps |
CPU time | 11.71 seconds |
Started | Aug 15 04:40:54 PM PDT 24 |
Finished | Aug 15 04:41:06 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-36374f11-5e85-4d65-b982-c92208030dbf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379115896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.379115896 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.2543456676 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 151092498 ps |
CPU time | 0.88 seconds |
Started | Aug 15 04:40:53 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-0f7b84f9-b979-4b93-8388-eb17bef4ed51 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543456676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2543456676 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.2553539141 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 2379370300 ps |
CPU time | 2.52 seconds |
Started | Aug 15 04:40:56 PM PDT 24 |
Finished | Aug 15 04:40:59 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-34ae3554-f0a0-4afb-9ece-abd2cf925657 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553539141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2553539141 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3345582055 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 98414394 ps |
CPU time | 0.76 seconds |
Started | Aug 15 04:40:55 PM PDT 24 |
Finished | Aug 15 04:40:56 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-4958e062-8397-4163-a366-ab047987568a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345582055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3345582055 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.3432910909 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2111002032 ps |
CPU time | 6.07 seconds |
Started | Aug 15 04:40:55 PM PDT 24 |
Finished | Aug 15 04:41:01 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-f3d998bb-4977-45d7-a393-02eb19faa79a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432910909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3432910909 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2600913319 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 95289429 ps |
CPU time | 0.76 seconds |
Started | Aug 15 04:40:55 PM PDT 24 |
Finished | Aug 15 04:40:56 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-5d7ca26d-0771-4919-94f5-ff45154b017e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600913319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2600913319 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.826531283 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 4664182164 ps |
CPU time | 2.51 seconds |
Started | Aug 15 04:40:56 PM PDT 24 |
Finished | Aug 15 04:40:59 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-c6b7c78f-c266-431b-8960-5e3eadaa1800 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826531283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.826531283 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.2943779856 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 58232691 ps |
CPU time | 0.74 seconds |
Started | Aug 15 04:40:58 PM PDT 24 |
Finished | Aug 15 04:40:59 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-0a41b97b-ae38-494a-a873-09565dee2d45 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943779856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2943779856 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.3942896296 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 3790294486 ps |
CPU time | 6.09 seconds |
Started | Aug 15 04:40:54 PM PDT 24 |
Finished | Aug 15 04:41:00 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-81965830-52f0-4fc4-ab35-aa6a050354c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942896296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3942896296 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.1067781185 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 148696234 ps |
CPU time | 0.84 seconds |
Started | Aug 15 04:40:54 PM PDT 24 |
Finished | Aug 15 04:40:55 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-d30196cb-362c-4dd4-ac72-4f946a3f1a17 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067781185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1067781185 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1268099374 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 120186020 ps |
CPU time | 0.69 seconds |
Started | Aug 15 04:40:53 PM PDT 24 |
Finished | Aug 15 04:40:54 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-af553972-eba8-48f3-8ec6-4930a6f1ee0c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268099374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1268099374 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.3817803334 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 1957388774 ps |
CPU time | 5.64 seconds |
Started | Aug 15 04:40:55 PM PDT 24 |
Finished | Aug 15 04:41:01 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-621a34a2-7a2c-4eb4-9e0d-23d1f8120761 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817803334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3817803334 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.3468790608 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 63819937 ps |
CPU time | 0.74 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:04 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-68a9351a-d42c-4f0d-8adc-a1435120e61a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468790608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3468790608 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3053451005 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1794426033 ps |
CPU time | 5.74 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:10 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-5373bc0d-1c8e-43ca-bb08-0d996b94b17d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053451005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3053451005 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2811331311 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 7358096212 ps |
CPU time | 5.06 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:09 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-7d096434-924f-4113-ade1-9d92a46c5a94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811331311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2811331311 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_buffered_enable.1058659073 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 512728872 ps |
CPU time | 2.08 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:06 PM PDT 24 |
Peak memory | 225788 kb |
Host | smart-22ed941d-9fc7-412f-b4b5-5102ee6e8cfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058659073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.1058659073 |
Directory | /workspace/5.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.125041022 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 14231928060 ps |
CPU time | 40.41 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:44 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-89d2c602-85e8-4097-95bb-d5112829fced |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=125041022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl _access.125041022 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2580115797 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1021480694 ps |
CPU time | 1.49 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:06 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-d6bf5644-b2c1-4bcf-9a91-4c83097e0822 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580115797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2580115797 |
Directory | /workspace/5.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.1450292105 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 2217805139 ps |
CPU time | 1.64 seconds |
Started | Aug 15 04:40:06 PM PDT 24 |
Finished | Aug 15 04:40:08 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-9790e604-75e5-4b84-bf5a-62076c48a6ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450292105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1450292105 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.3473829510 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 2296349664 ps |
CPU time | 2.41 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:07 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-d433a105-034b-4770-b21c-2f47a32b66f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473829510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3473829510 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3614552542 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 75007919 ps |
CPU time | 0.82 seconds |
Started | Aug 15 04:40:11 PM PDT 24 |
Finished | Aug 15 04:40:12 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-2afa90f1-3022-46e8-86c0-6e6aab3d7893 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614552542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3614552542 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2274867486 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 6311424327 ps |
CPU time | 8.63 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:22 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-f2dfe30e-4a5f-4793-bfa7-1e312c05f818 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274867486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2274867486 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2153144415 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 1882925688 ps |
CPU time | 4.64 seconds |
Started | Aug 15 04:40:12 PM PDT 24 |
Finished | Aug 15 04:40:17 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-82aa7396-5829-4401-8eba-ead221dcb34a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153144415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2153144415 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_buffered_enable.1084489520 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 142470142 ps |
CPU time | 1.14 seconds |
Started | Aug 15 04:40:12 PM PDT 24 |
Finished | Aug 15 04:40:13 PM PDT 24 |
Peak memory | 226072 kb |
Host | smart-f7d272be-d6b7-41b5-8a88-92749b2a914d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084489520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.1084489520 |
Directory | /workspace/6.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2801531786 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 1790434886 ps |
CPU time | 6.01 seconds |
Started | Aug 15 04:40:06 PM PDT 24 |
Finished | Aug 15 04:40:13 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-23c71c6e-1562-4031-952b-3ba68be7e3c9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2801531786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.2801531786 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3121866452 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 263278090 ps |
CPU time | 0.84 seconds |
Started | Aug 15 04:40:14 PM PDT 24 |
Finished | Aug 15 04:40:15 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-ac43e2e7-6ebe-4311-8066-930c0179e326 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121866452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3121866452 |
Directory | /workspace/6.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.1625930217 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2563039999 ps |
CPU time | 4.18 seconds |
Started | Aug 15 04:40:04 PM PDT 24 |
Finished | Aug 15 04:40:08 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-c2120dc5-f4db-41c1-828e-888752978a9b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625930217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1625930217 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.356197364 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 6036933983 ps |
CPU time | 15.11 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:28 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-3bce4701-f4ea-4a8d-87b1-a0f014a8219f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356197364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.356197364 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.351269640 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1086891615 ps |
CPU time | 18.72 seconds |
Started | Aug 15 04:40:11 PM PDT 24 |
Finished | Aug 15 04:40:30 PM PDT 24 |
Peak memory | 214796 kb |
Host | smart-47dcbcef-249a-4690-ad95-c8d304fd73c6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351269640 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.351269640 |
Directory | /workspace/6.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.4188118668 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 36605352 ps |
CPU time | 0.78 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:14 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-4cbf17c9-816e-4296-a97e-6cc2e52528fd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188118668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4188118668 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.90708657 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 56229096149 ps |
CPU time | 87.06 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:41:40 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-71f522cd-b130-4ad8-8d82-b6e18a9a4516 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90708657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.90708657 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.790132415 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 15048229465 ps |
CPU time | 3.67 seconds |
Started | Aug 15 04:40:11 PM PDT 24 |
Finished | Aug 15 04:40:15 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-4df579c7-bffe-43f7-9018-aa289ccdc5ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790132415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.790132415 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_buffered_enable.2786646745 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 377103427 ps |
CPU time | 1.64 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:15 PM PDT 24 |
Peak memory | 234164 kb |
Host | smart-24c5ed0f-2067-4f21-a4fc-f66dbf0254d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786646745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2786646745 |
Directory | /workspace/7.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1149016259 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 923738796 ps |
CPU time | 1.96 seconds |
Started | Aug 15 04:40:14 PM PDT 24 |
Finished | Aug 15 04:40:16 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-2930ad36-61e6-4c17-9936-e936ef797071 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1149016259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.1149016259 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_halt_resume_whereto.342249630 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 1311890935 ps |
CPU time | 4.11 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:17 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-f08a42a9-9b4b-4d26-a13c-09bffa9b5a6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342249630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.342249630 |
Directory | /workspace/7.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.962045670 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1486291372 ps |
CPU time | 1.76 seconds |
Started | Aug 15 04:40:12 PM PDT 24 |
Finished | Aug 15 04:40:14 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-d7b2b747-aada-4d18-9142-6c0c690c0d18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962045670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.962045670 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.3242382763 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 4597937616 ps |
CPU time | 4.8 seconds |
Started | Aug 15 04:40:11 PM PDT 24 |
Finished | Aug 15 04:40:16 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-99d3af53-0bf6-444d-ba11-5fbb6951297d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242382763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3242382763 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.943217652 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 94956594 ps |
CPU time | 0.75 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:14 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-238aced9-c9d0-4369-a7ad-aac98116b14b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943217652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.943217652 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1472905279 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 2785636347 ps |
CPU time | 2.87 seconds |
Started | Aug 15 04:40:14 PM PDT 24 |
Finished | Aug 15 04:40:17 PM PDT 24 |
Peak memory | 213960 kb |
Host | smart-571290ef-0891-4231-93e8-57960bac3714 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472905279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1472905279 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_buffered_enable.2455512262 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 500238368 ps |
CPU time | 1.19 seconds |
Started | Aug 15 04:40:14 PM PDT 24 |
Finished | Aug 15 04:40:16 PM PDT 24 |
Peak memory | 225840 kb |
Host | smart-b66875b5-e0c3-4b50-a8b5-50f31254299f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455512262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.2455512262 |
Directory | /workspace/8.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2095817243 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 2106416639 ps |
CPU time | 4.41 seconds |
Started | Aug 15 04:40:16 PM PDT 24 |
Finished | Aug 15 04:40:21 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-f0ecd5ea-b5f7-456f-99d0-8fb497b9f4a0 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2095817243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.2095817243 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.3880598417 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 10238123327 ps |
CPU time | 8.95 seconds |
Started | Aug 15 04:40:14 PM PDT 24 |
Finished | Aug 15 04:40:23 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-7c08640b-df79-479f-9ac3-901f9444b5a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880598417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3880598417 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.742383958 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 4654262944 ps |
CPU time | 5.58 seconds |
Started | Aug 15 04:40:15 PM PDT 24 |
Finished | Aug 15 04:40:21 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-383d99a4-040c-4cfb-ba44-fdb77cdcad89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742383958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.742383958 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.2202947386 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 15094655623 ps |
CPU time | 92.23 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:41:46 PM PDT 24 |
Peak memory | 221472 kb |
Host | smart-54caee81-9fdb-4419-bc4b-d9d4579e8544 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202947386 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.2202947386 |
Directory | /workspace/8.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.37027100 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 65598922 ps |
CPU time | 0.74 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:22 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-087e9ff1-de15-4789-870a-f6b6bde732dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37027100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.37027100 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.472388064 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 3238114689 ps |
CPU time | 8.62 seconds |
Started | Aug 15 04:40:21 PM PDT 24 |
Finished | Aug 15 04:40:30 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-d950bb03-8600-4050-b754-44347b85816f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472388064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.472388064 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.4004319448 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 3344728056 ps |
CPU time | 9.89 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:23 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-51469644-0f8d-4630-b942-457124ba9c01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004319448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.4004319448 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_buffered_enable.1186998829 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 132094237 ps |
CPU time | 0.96 seconds |
Started | Aug 15 04:40:20 PM PDT 24 |
Finished | Aug 15 04:40:22 PM PDT 24 |
Peak memory | 226368 kb |
Host | smart-49a63fa1-7715-438c-b506-eda5176a57ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186998829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.1186998829 |
Directory | /workspace/9.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2459626964 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 3601721073 ps |
CPU time | 3.9 seconds |
Started | Aug 15 04:40:15 PM PDT 24 |
Finished | Aug 15 04:40:19 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-85483a8b-748a-43f6-a1c1-f053809b37dc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2459626964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.2459626964 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.4138557586 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 7817157204 ps |
CPU time | 14.3 seconds |
Started | Aug 15 04:40:13 PM PDT 24 |
Finished | Aug 15 04:40:27 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-65f51fd8-bb4d-4c2e-acc7-0ab653a7d5bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138557586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.4138557586 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.1783416621 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 8157295303 ps |
CPU time | 7.06 seconds |
Started | Aug 15 04:40:23 PM PDT 24 |
Finished | Aug 15 04:40:30 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-b808caf5-44f1-448e-9d38-67b840ca673f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783416621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1783416621 |
Directory | /workspace/9.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1168720536 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 850075611 ps |
CPU time | 5.89 seconds |
Started | Aug 15 04:40:22 PM PDT 24 |
Finished | Aug 15 04:40:28 PM PDT 24 |
Peak memory | 220836 kb |
Host | smart-835050c6-dc04-4228-ad63-6f6734336c55 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168720536 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1168720536 |
Directory | /workspace/9.rv_dm_stress_all_with_rand_reset/latest |
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