SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
88.46 | 96.32 | 89.96 | 92.10 | 93.33 | 90.44 | 98.63 | 58.45 |
T325 | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.4250048270 | Aug 16 04:42:15 PM PDT 24 | Aug 16 04:42:27 PM PDT 24 | 6000819747 ps | ||
T41 | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1153810515 | Aug 16 04:41:57 PM PDT 24 | Aug 16 04:41:58 PM PDT 24 | 401119688 ps | ||
T326 | /workspace/coverage/default/27.rv_dm_alert_test.524371109 | Aug 16 04:42:33 PM PDT 24 | Aug 16 04:42:34 PM PDT 24 | 65676812 ps | ||
T327 | /workspace/coverage/default/1.rv_dm_smoke.2824139246 | Aug 16 04:41:57 PM PDT 24 | Aug 16 04:42:01 PM PDT 24 | 2858092474 ps | ||
T328 | /workspace/coverage/default/48.rv_dm_stress_all.3000860772 | Aug 16 04:42:40 PM PDT 24 | Aug 16 04:42:45 PM PDT 24 | 1570708624 ps | ||
T329 | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2192542293 | Aug 16 04:42:10 PM PDT 24 | Aug 16 04:42:12 PM PDT 24 | 1076397133 ps | ||
T330 | /workspace/coverage/default/1.rv_dm_alert_test.2688781550 | Aug 16 04:42:02 PM PDT 24 | Aug 16 04:42:02 PM PDT 24 | 197207304 ps | ||
T331 | /workspace/coverage/default/45.rv_dm_stress_all.525574476 | Aug 16 04:42:39 PM PDT 24 | Aug 16 04:42:42 PM PDT 24 | 2198563029 ps | ||
T332 | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.4259032195 | Aug 16 04:42:23 PM PDT 24 | Aug 16 04:42:26 PM PDT 24 | 2481900357 ps | ||
T54 | /workspace/coverage/default/0.rv_dm_abstractcmd_status.880944100 | Aug 16 04:41:55 PM PDT 24 | Aug 16 04:41:56 PM PDT 24 | 150175843 ps | ||
T73 | /workspace/coverage/default/3.rv_dm_sec_cm.1755931654 | Aug 16 04:42:16 PM PDT 24 | Aug 16 04:42:18 PM PDT 24 | 233398149 ps | ||
T333 | /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2816629060 | Aug 16 04:42:14 PM PDT 24 | Aug 16 04:42:15 PM PDT 24 | 1544004072 ps | ||
T334 | /workspace/coverage/default/2.rv_dm_alert_test.4155779959 | Aug 16 04:42:08 PM PDT 24 | Aug 16 04:42:09 PM PDT 24 | 30616718 ps | ||
T335 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3755209068 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:16 PM PDT 24 | 75119859 ps | ||
T336 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.93024349 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:40:02 PM PDT 24 | 15242576246 ps | ||
T337 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2657780025 | Aug 16 04:39:34 PM PDT 24 | Aug 16 04:39:38 PM PDT 24 | 1151473428 ps | ||
T106 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1833938529 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:21 PM PDT 24 | 158994697 ps | ||
T104 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2042327292 | Aug 16 04:40:30 PM PDT 24 | Aug 16 04:40:32 PM PDT 24 | 81879448 ps | ||
T338 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4194392085 | Aug 16 04:39:31 PM PDT 24 | Aug 16 04:39:32 PM PDT 24 | 104572450 ps | ||
T96 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3099429878 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:41:05 PM PDT 24 | 2475412617 ps | ||
T339 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1943463792 | Aug 16 04:39:41 PM PDT 24 | Aug 16 04:39:42 PM PDT 24 | 117115212 ps | ||
T115 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2026885371 | Aug 16 04:39:58 PM PDT 24 | Aug 16 04:40:00 PM PDT 24 | 78161307 ps | ||
T116 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.124508136 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:39:53 PM PDT 24 | 81863452 ps | ||
T169 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.76919194 | Aug 16 04:39:41 PM PDT 24 | Aug 16 04:39:54 PM PDT 24 | 4081149845 ps | ||
T117 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2588127406 | Aug 16 04:40:08 PM PDT 24 | Aug 16 04:40:12 PM PDT 24 | 244028616 ps | ||
T107 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1397287565 | Aug 16 04:39:42 PM PDT 24 | Aug 16 04:39:44 PM PDT 24 | 418456004 ps | ||
T340 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1824223118 | Aug 16 04:39:30 PM PDT 24 | Aug 16 04:39:52 PM PDT 24 | 7558511111 ps | ||
T341 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1135541329 | Aug 16 04:40:20 PM PDT 24 | Aug 16 04:40:26 PM PDT 24 | 102668627 ps | ||
T118 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2668243922 | Aug 16 04:39:40 PM PDT 24 | Aug 16 04:40:09 PM PDT 24 | 1437086273 ps | ||
T170 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1488917530 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:40:28 PM PDT 24 | 9707896719 ps | ||
T342 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1480498342 | Aug 16 04:40:20 PM PDT 24 | Aug 16 04:40:29 PM PDT 24 | 11700207295 ps | ||
T343 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1391708557 | Aug 16 04:39:38 PM PDT 24 | Aug 16 04:39:41 PM PDT 24 | 64898110 ps | ||
T157 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.641221998 | Aug 16 04:39:30 PM PDT 24 | Aug 16 04:39:36 PM PDT 24 | 797449194 ps | ||
T119 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3785558814 | Aug 16 04:40:15 PM PDT 24 | Aug 16 04:40:22 PM PDT 24 | 759610111 ps | ||
T120 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1378678074 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:40:33 PM PDT 24 | 3847448121 ps | ||
T344 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3156235015 | Aug 16 04:40:08 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 4364306247 ps | ||
T158 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3347902275 | Aug 16 04:40:21 PM PDT 24 | Aug 16 04:40:25 PM PDT 24 | 366658607 ps | ||
T128 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4078020457 | Aug 16 04:39:48 PM PDT 24 | Aug 16 04:39:51 PM PDT 24 | 2123057391 ps | ||
T159 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.932134622 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 225286319 ps | ||
T160 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1647340138 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:27 PM PDT 24 | 4075586355 ps | ||
T345 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2131884642 | Aug 16 04:40:12 PM PDT 24 | Aug 16 04:40:14 PM PDT 24 | 410687703 ps | ||
T108 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1377661233 | Aug 16 04:39:38 PM PDT 24 | Aug 16 04:39:40 PM PDT 24 | 169414266 ps | ||
T121 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4167106419 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:35 PM PDT 24 | 96555558 ps | ||
T346 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.614091312 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:40:02 PM PDT 24 | 15966256265 ps | ||
T347 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2780172444 | Aug 16 04:40:07 PM PDT 24 | Aug 16 04:40:16 PM PDT 24 | 10713173834 ps | ||
T189 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2362886864 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:28 PM PDT 24 | 483279361 ps | ||
T122 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1498231206 | Aug 16 04:40:21 PM PDT 24 | Aug 16 04:40:24 PM PDT 24 | 226030026 ps | ||
T348 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.5588798 | Aug 16 04:40:28 PM PDT 24 | Aug 16 04:40:34 PM PDT 24 | 1652375589 ps | ||
T349 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3068934440 | Aug 16 04:40:02 PM PDT 24 | Aug 16 04:40:07 PM PDT 24 | 756077527 ps | ||
T103 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.353361027 | Aug 16 04:40:21 PM PDT 24 | Aug 16 04:40:25 PM PDT 24 | 132897700 ps | ||
T123 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2904170257 | Aug 16 04:39:25 PM PDT 24 | Aug 16 04:40:50 PM PDT 24 | 18305151355 ps | ||
T153 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1288433902 | Aug 16 04:39:44 PM PDT 24 | Aug 16 04:40:12 PM PDT 24 | 2100118319 ps | ||
T350 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1507119286 | Aug 16 04:39:39 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 19694382985 ps | ||
T94 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.936383065 | Aug 16 04:39:40 PM PDT 24 | Aug 16 04:40:45 PM PDT 24 | 3601295487 ps | ||
T351 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1442251381 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:12 PM PDT 24 | 2499410636 ps | ||
T124 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.664048242 | Aug 16 04:40:08 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 665042126 ps | ||
T130 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4266111222 | Aug 16 04:39:58 PM PDT 24 | Aug 16 04:40:00 PM PDT 24 | 66309324 ps | ||
T95 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.535886777 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:40:37 PM PDT 24 | 4493534162 ps | ||
T352 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.923368187 | Aug 16 04:40:06 PM PDT 24 | Aug 16 04:40:07 PM PDT 24 | 338655867 ps | ||
T353 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.980763402 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:35 PM PDT 24 | 90449673 ps | ||
T354 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3936468400 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:41:15 PM PDT 24 | 64506467122 ps | ||
T131 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1670990023 | Aug 16 04:39:31 PM PDT 24 | Aug 16 04:40:37 PM PDT 24 | 20372683704 ps | ||
T132 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.958762229 | Aug 16 04:40:03 PM PDT 24 | Aug 16 04:40:05 PM PDT 24 | 118151484 ps | ||
T355 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1439465659 | Aug 16 04:39:38 PM PDT 24 | Aug 16 04:39:40 PM PDT 24 | 230185102 ps | ||
T356 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1356059412 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:39:55 PM PDT 24 | 368574621 ps | ||
T357 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3089671366 | Aug 16 04:39:31 PM PDT 24 | Aug 16 04:40:06 PM PDT 24 | 6020848261 ps | ||
T358 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.880917348 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:22 PM PDT 24 | 145478423 ps | ||
T359 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2299152760 | Aug 16 04:39:37 PM PDT 24 | Aug 16 04:40:46 PM PDT 24 | 28823045020 ps | ||
T360 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1345167290 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:06 PM PDT 24 | 74401508 ps | ||
T361 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3565147959 | Aug 16 04:39:27 PM PDT 24 | Aug 16 04:39:50 PM PDT 24 | 15121481945 ps | ||
T362 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4179282628 | Aug 16 04:39:53 PM PDT 24 | Aug 16 04:39:54 PM PDT 24 | 139476933 ps | ||
T363 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3230387639 | Aug 16 04:40:20 PM PDT 24 | Aug 16 04:40:28 PM PDT 24 | 5175886737 ps | ||
T364 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1645601075 | Aug 16 04:39:25 PM PDT 24 | Aug 16 04:39:58 PM PDT 24 | 5148342832 ps | ||
T365 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3460423050 | Aug 16 04:39:52 PM PDT 24 | Aug 16 04:39:53 PM PDT 24 | 24438176 ps | ||
T366 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2934370159 | Aug 16 04:40:22 PM PDT 24 | Aug 16 04:40:26 PM PDT 24 | 3230037272 ps | ||
T367 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3853580535 | Aug 16 04:39:32 PM PDT 24 | Aug 16 04:39:34 PM PDT 24 | 844470598 ps | ||
T141 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.431012844 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 339979022 ps | ||
T368 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1795660419 | Aug 16 04:39:25 PM PDT 24 | Aug 16 04:39:26 PM PDT 24 | 41787137 ps | ||
T369 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2512877566 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:16 PM PDT 24 | 203147942 ps | ||
T154 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2736173503 | Aug 16 04:39:41 PM PDT 24 | Aug 16 04:39:43 PM PDT 24 | 348709738 ps | ||
T370 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1740324688 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:27 PM PDT 24 | 10474874953 ps | ||
T133 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3195188118 | Aug 16 04:39:49 PM PDT 24 | Aug 16 04:39:57 PM PDT 24 | 790523014 ps | ||
T190 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1798027395 | Aug 16 04:40:03 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 2734494086 ps | ||
T134 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1054397561 | Aug 16 04:39:35 PM PDT 24 | Aug 16 04:39:36 PM PDT 24 | 110595661 ps | ||
T371 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2708345281 | Aug 16 04:39:44 PM PDT 24 | Aug 16 04:39:47 PM PDT 24 | 372609133 ps | ||
T92 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4167937545 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:41:08 PM PDT 24 | 58611869985 ps | ||
T372 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2022531204 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:42 PM PDT 24 | 25510752739 ps | ||
T148 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1829551241 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:26 PM PDT 24 | 461722329 ps | ||
T373 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3759282911 | Aug 16 04:39:49 PM PDT 24 | Aug 16 04:39:50 PM PDT 24 | 322439728 ps | ||
T149 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.553212756 | Aug 16 04:40:01 PM PDT 24 | Aug 16 04:40:05 PM PDT 24 | 194713038 ps | ||
T374 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.699575194 | Aug 16 04:39:57 PM PDT 24 | Aug 16 04:40:02 PM PDT 24 | 622545060 ps | ||
T375 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1249629565 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:41:05 PM PDT 24 | 17888281772 ps | ||
T376 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1353043393 | Aug 16 04:40:11 PM PDT 24 | Aug 16 04:40:19 PM PDT 24 | 10878259297 ps | ||
T377 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3469730540 | Aug 16 04:40:27 PM PDT 24 | Aug 16 04:40:29 PM PDT 24 | 286672049 ps | ||
T378 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2656165924 | Aug 16 04:39:44 PM PDT 24 | Aug 16 04:39:46 PM PDT 24 | 425252845 ps | ||
T150 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2709344959 | Aug 16 04:39:57 PM PDT 24 | Aug 16 04:40:02 PM PDT 24 | 317216628 ps | ||
T192 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1919312577 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:42 PM PDT 24 | 5714726902 ps | ||
T151 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2425695076 | Aug 16 04:40:20 PM PDT 24 | Aug 16 04:40:28 PM PDT 24 | 843966336 ps | ||
T379 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1800057918 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:40:03 PM PDT 24 | 1280651582 ps | ||
T380 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3777778297 | Aug 16 04:39:57 PM PDT 24 | Aug 16 04:40:38 PM PDT 24 | 15076391201 ps | ||
T381 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.126066792 | Aug 16 04:39:40 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 16970704040 ps | ||
T193 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.50691504 | Aug 16 04:40:03 PM PDT 24 | Aug 16 04:40:26 PM PDT 24 | 4475768168 ps | ||
T382 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2367680171 | Aug 16 04:39:39 PM PDT 24 | Aug 16 04:40:38 PM PDT 24 | 42168727170 ps | ||
T383 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2577842944 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:04 PM PDT 24 | 265621180 ps | ||
T384 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3081060824 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 2938773218 ps | ||
T142 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.512967812 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:39:53 PM PDT 24 | 274288917 ps | ||
T385 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3284335249 | Aug 16 04:40:01 PM PDT 24 | Aug 16 04:40:04 PM PDT 24 | 4035472195 ps | ||
T386 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2383335029 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:18 PM PDT 24 | 129018591 ps | ||
T191 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.472630828 | Aug 16 04:40:08 PM PDT 24 | Aug 16 04:40:18 PM PDT 24 | 2461441613 ps | ||
T387 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.371670689 | Aug 16 04:40:06 PM PDT 24 | Aug 16 04:40:31 PM PDT 24 | 14405047515 ps | ||
T93 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1254485900 | Aug 16 04:40:01 PM PDT 24 | Aug 16 04:41:21 PM PDT 24 | 12980569741 ps | ||
T196 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3779474173 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:23 PM PDT 24 | 644558764 ps | ||
T388 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2985023949 | Aug 16 04:39:42 PM PDT 24 | Aug 16 04:39:43 PM PDT 24 | 91966206 ps | ||
T389 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1064207274 | Aug 16 04:39:24 PM PDT 24 | Aug 16 04:39:26 PM PDT 24 | 779302017 ps | ||
T390 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1640349402 | Aug 16 04:39:55 PM PDT 24 | Aug 16 04:39:56 PM PDT 24 | 217305078 ps | ||
T391 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1976345387 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:24 PM PDT 24 | 925473069 ps | ||
T392 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2705256280 | Aug 16 04:40:07 PM PDT 24 | Aug 16 04:40:11 PM PDT 24 | 125207785 ps | ||
T393 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4045595666 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:39:55 PM PDT 24 | 737542525 ps | ||
T394 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3776830188 | Aug 16 04:39:53 PM PDT 24 | Aug 16 04:41:11 PM PDT 24 | 110635663154 ps | ||
T200 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4055359206 | Aug 16 04:40:11 PM PDT 24 | Aug 16 04:40:32 PM PDT 24 | 2865612262 ps | ||
T105 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1589447469 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:40:21 PM PDT 24 | 9722399013 ps | ||
T395 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2560959174 | Aug 16 04:39:48 PM PDT 24 | Aug 16 04:39:50 PM PDT 24 | 499343640 ps | ||
T396 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1501664024 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 133372977 ps | ||
T397 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2710865431 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:37 PM PDT 24 | 3389297536 ps | ||
T398 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.28156904 | Aug 16 04:39:39 PM PDT 24 | Aug 16 04:39:47 PM PDT 24 | 4059502955 ps | ||
T135 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3780254800 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:42 PM PDT 24 | 760700342 ps | ||
T152 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2581136699 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:40 PM PDT 24 | 320589476 ps | ||
T97 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2941887890 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:06 PM PDT 24 | 240840410 ps | ||
T136 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3057904740 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 189997286 ps | ||
T399 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2053621094 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 256306674 ps | ||
T400 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1652156023 | Aug 16 04:39:56 PM PDT 24 | Aug 16 04:40:01 PM PDT 24 | 107879784 ps | ||
T401 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3843188667 | Aug 16 04:40:07 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 93537370 ps | ||
T402 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2811373718 | Aug 16 04:40:08 PM PDT 24 | Aug 16 04:40:11 PM PDT 24 | 157192975 ps | ||
T403 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1091093218 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:40:06 PM PDT 24 | 232304085 ps | ||
T404 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1861624531 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:14 PM PDT 24 | 592356094 ps | ||
T137 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2673988426 | Aug 16 04:40:12 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 368732119 ps | ||
T405 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1190230925 | Aug 16 04:40:11 PM PDT 24 | Aug 16 04:40:14 PM PDT 24 | 111709598 ps | ||
T406 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.972256337 | Aug 16 04:40:03 PM PDT 24 | Aug 16 04:40:12 PM PDT 24 | 2822331493 ps | ||
T407 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2893923398 | Aug 16 04:39:38 PM PDT 24 | Aug 16 04:39:41 PM PDT 24 | 4630811379 ps | ||
T408 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.610482171 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:39:53 PM PDT 24 | 590913698 ps | ||
T409 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.131099307 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:34 PM PDT 24 | 9764991466 ps | ||
T410 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.305516188 | Aug 16 04:40:22 PM PDT 24 | Aug 16 04:40:25 PM PDT 24 | 237109628 ps | ||
T411 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4127344844 | Aug 16 04:39:28 PM PDT 24 | Aug 16 04:39:33 PM PDT 24 | 1680532144 ps | ||
T412 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2685699815 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:02 PM PDT 24 | 594537611 ps | ||
T413 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2672376586 | Aug 16 04:39:34 PM PDT 24 | Aug 16 04:39:48 PM PDT 24 | 10497085397 ps | ||
T414 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2949274362 | Aug 16 04:40:17 PM PDT 24 | Aug 16 04:40:21 PM PDT 24 | 392729751 ps | ||
T197 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2640103629 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:40:03 PM PDT 24 | 3167312616 ps | ||
T138 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3196737750 | Aug 16 04:40:21 PM PDT 24 | Aug 16 04:40:23 PM PDT 24 | 146645374 ps | ||
T415 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4142055092 | Aug 16 04:40:21 PM PDT 24 | Aug 16 04:40:23 PM PDT 24 | 244049307 ps | ||
T416 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1143468803 | Aug 16 04:40:22 PM PDT 24 | Aug 16 04:40:24 PM PDT 24 | 64269449 ps | ||
T417 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2309740432 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:40:20 PM PDT 24 | 2487858746 ps | ||
T139 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3506435700 | Aug 16 04:39:39 PM PDT 24 | Aug 16 04:39:47 PM PDT 24 | 556549453 ps | ||
T98 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2122594107 | Aug 16 04:39:32 PM PDT 24 | Aug 16 04:40:47 PM PDT 24 | 20844633864 ps | ||
T418 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2330193850 | Aug 16 04:39:24 PM PDT 24 | Aug 16 04:39:29 PM PDT 24 | 320738473 ps | ||
T419 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2873244506 | Aug 16 04:40:23 PM PDT 24 | Aug 16 04:40:39 PM PDT 24 | 9318181281 ps | ||
T420 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2226578894 | Aug 16 04:40:16 PM PDT 24 | Aug 16 04:40:24 PM PDT 24 | 13978102091 ps | ||
T421 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2057304473 | Aug 16 04:40:01 PM PDT 24 | Aug 16 04:40:04 PM PDT 24 | 1302307682 ps | ||
T422 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3735020179 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:07 PM PDT 24 | 301195020 ps | ||
T423 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.194784824 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 7653353439 ps | ||
T202 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.764468398 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:18 PM PDT 24 | 7160475845 ps | ||
T143 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3413248309 | Aug 16 04:40:06 PM PDT 24 | Aug 16 04:40:09 PM PDT 24 | 196617275 ps | ||
T424 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.225465654 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:03 PM PDT 24 | 526651632 ps | ||
T194 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1700788916 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:22 PM PDT 24 | 10300973657 ps | ||
T144 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2105232188 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:16 PM PDT 24 | 221549721 ps | ||
T140 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.917317048 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:20 PM PDT 24 | 441765981 ps | ||
T425 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1822977300 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:45 PM PDT 24 | 16935170481 ps | ||
T426 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2938758153 | Aug 16 04:40:13 PM PDT 24 | Aug 16 04:40:19 PM PDT 24 | 923308160 ps | ||
T427 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2807376092 | Aug 16 04:40:21 PM PDT 24 | Aug 16 04:40:30 PM PDT 24 | 848334801 ps | ||
T428 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2449528854 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:27 PM PDT 24 | 2065022344 ps | ||
T429 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1001938790 | Aug 16 04:40:33 PM PDT 24 | Aug 16 04:40:35 PM PDT 24 | 382434388 ps | ||
T430 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4041862139 | Aug 16 04:40:28 PM PDT 24 | Aug 16 04:40:32 PM PDT 24 | 430701569 ps | ||
T198 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.696643491 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:31 PM PDT 24 | 7199447994 ps | ||
T431 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1852658028 | Aug 16 04:39:42 PM PDT 24 | Aug 16 04:40:00 PM PDT 24 | 17626779756 ps | ||
T432 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2767926877 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 825824596 ps | ||
T433 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3172276435 | Aug 16 04:39:49 PM PDT 24 | Aug 16 04:40:02 PM PDT 24 | 3995161947 ps | ||
T434 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1305067478 | Aug 16 04:40:07 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 124172157 ps | ||
T435 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.938514447 | Aug 16 04:39:34 PM PDT 24 | Aug 16 04:39:37 PM PDT 24 | 356082504 ps | ||
T145 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2989917554 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:40:04 PM PDT 24 | 4061349707 ps | ||
T436 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.76271981 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 7142987153 ps | ||
T437 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.226742408 | Aug 16 04:40:18 PM PDT 24 | Aug 16 04:40:19 PM PDT 24 | 355582741 ps | ||
T438 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1734752888 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:40:03 PM PDT 24 | 192058333 ps | ||
T146 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2104877841 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:41:08 PM PDT 24 | 4322010495 ps | ||
T439 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3435533596 | Aug 16 04:40:04 PM PDT 24 | Aug 16 04:40:10 PM PDT 24 | 2481985180 ps | ||
T440 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.50209830 | Aug 16 04:40:22 PM PDT 24 | Aug 16 04:40:23 PM PDT 24 | 116677814 ps | ||
T441 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.561392101 | Aug 16 04:39:37 PM PDT 24 | Aug 16 04:39:47 PM PDT 24 | 784886322 ps | ||
T442 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3166561034 | Aug 16 04:40:06 PM PDT 24 | Aug 16 04:40:10 PM PDT 24 | 553924440 ps | ||
T443 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1161059759 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:06 PM PDT 24 | 111314132 ps | ||
T444 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2332970584 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 18303477591 ps | ||
T147 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1882242346 | Aug 16 04:39:37 PM PDT 24 | Aug 16 04:39:40 PM PDT 24 | 700347048 ps | ||
T445 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2762980194 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:39:57 PM PDT 24 | 9459277758 ps | ||
T446 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2341374746 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:09 PM PDT 24 | 15172846553 ps | ||
T129 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1649928815 | Aug 16 04:39:26 PM PDT 24 | Aug 16 04:39:44 PM PDT 24 | 6015476319 ps | ||
T447 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3824043273 | Aug 16 04:40:23 PM PDT 24 | Aug 16 04:40:25 PM PDT 24 | 219100540 ps | ||
T448 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1840035752 | Aug 16 04:39:22 PM PDT 24 | Aug 16 04:39:23 PM PDT 24 | 64983131 ps | ||
T449 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3147782154 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:40:09 PM PDT 24 | 3422900399 ps | ||
T450 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3750222515 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:36 PM PDT 24 | 217063471 ps | ||
T451 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1217324730 | Aug 16 04:40:20 PM PDT 24 | Aug 16 04:40:27 PM PDT 24 | 2192753024 ps | ||
T452 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1103975420 | Aug 16 04:39:32 PM PDT 24 | Aug 16 04:39:33 PM PDT 24 | 43429697 ps | ||
T453 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1357190951 | Aug 16 04:39:26 PM PDT 24 | Aug 16 04:39:28 PM PDT 24 | 557021865 ps | ||
T454 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3647026942 | Aug 16 04:39:40 PM PDT 24 | Aug 16 04:39:41 PM PDT 24 | 743142187 ps | ||
T455 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2176216546 | Aug 16 04:40:14 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 79293128 ps | ||
T456 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2566966835 | Aug 16 04:39:33 PM PDT 24 | Aug 16 04:39:34 PM PDT 24 | 1208096611 ps | ||
T100 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.624037415 | Aug 16 04:40:01 PM PDT 24 | Aug 16 04:40:06 PM PDT 24 | 151580889 ps | ||
T457 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3119670698 | Aug 16 04:40:12 PM PDT 24 | Aug 16 04:40:14 PM PDT 24 | 166287678 ps | ||
T458 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.791633691 | Aug 16 04:40:00 PM PDT 24 | Aug 16 04:40:05 PM PDT 24 | 10413785781 ps | ||
T459 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3135082182 | Aug 16 04:39:30 PM PDT 24 | Aug 16 04:39:35 PM PDT 24 | 2013548687 ps | ||
T460 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2217541596 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:21 PM PDT 24 | 86109070 ps | ||
T461 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2544972028 | Aug 16 04:40:12 PM PDT 24 | Aug 16 04:40:15 PM PDT 24 | 344927391 ps | ||
T462 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1634065210 | Aug 16 04:39:24 PM PDT 24 | Aug 16 04:39:25 PM PDT 24 | 26318731 ps | ||
T463 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.537279162 | Aug 16 04:39:51 PM PDT 24 | Aug 16 04:39:53 PM PDT 24 | 455613222 ps | ||
T464 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.79181928 | Aug 16 04:40:28 PM PDT 24 | Aug 16 04:40:34 PM PDT 24 | 512711989 ps | ||
T465 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.241802527 | Aug 16 04:39:34 PM PDT 24 | Aug 16 04:40:50 PM PDT 24 | 3463710421 ps | ||
T466 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3334615720 | Aug 16 04:39:31 PM PDT 24 | Aug 16 04:44:08 PM PDT 24 | 201579548228 ps | ||
T467 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1097049908 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:40:01 PM PDT 24 | 163441811 ps | ||
T468 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2298934399 | Aug 16 04:40:23 PM PDT 24 | Aug 16 04:40:25 PM PDT 24 | 73846167 ps | ||
T469 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.368036105 | Aug 16 04:39:50 PM PDT 24 | Aug 16 04:41:38 PM PDT 24 | 37442589011 ps | ||
T470 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1904191575 | Aug 16 04:40:03 PM PDT 24 | Aug 16 04:40:24 PM PDT 24 | 5290578757 ps | ||
T471 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.636820226 | Aug 16 04:39:59 PM PDT 24 | Aug 16 04:39:59 PM PDT 24 | 108703361 ps | ||
T472 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1056749014 | Aug 16 04:40:05 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 2754406722 ps | ||
T195 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3041312386 | Aug 16 04:40:27 PM PDT 24 | Aug 16 04:40:44 PM PDT 24 | 1283952594 ps | ||
T473 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2445952142 | Aug 16 04:39:40 PM PDT 24 | Aug 16 04:39:45 PM PDT 24 | 2300416814 ps | ||
T474 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2604417298 | Aug 16 04:40:12 PM PDT 24 | Aug 16 04:40:25 PM PDT 24 | 8028587696 ps | ||
T475 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3353241552 | Aug 16 04:40:29 PM PDT 24 | Aug 16 04:42:04 PM PDT 24 | 72381667486 ps | ||
T476 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2924321049 | Aug 16 04:39:34 PM PDT 24 | Aug 16 04:39:35 PM PDT 24 | 318731725 ps | ||
T477 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2826039577 | Aug 16 04:40:30 PM PDT 24 | Aug 16 04:40:31 PM PDT 24 | 139070198 ps | ||
T478 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1783768149 | Aug 16 04:39:56 PM PDT 24 | Aug 16 04:41:00 PM PDT 24 | 3239112830 ps | ||
T479 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2626452818 | Aug 16 04:40:06 PM PDT 24 | Aug 16 04:40:08 PM PDT 24 | 217642873 ps | ||
T480 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2459468747 | Aug 16 04:40:19 PM PDT 24 | Aug 16 04:40:20 PM PDT 24 | 204007507 ps | ||
T201 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4256156077 | Aug 16 04:40:27 PM PDT 24 | Aug 16 04:40:48 PM PDT 24 | 4287023079 ps | ||
T481 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.552121123 | Aug 16 04:39:56 PM PDT 24 | Aug 16 04:39:58 PM PDT 24 | 130066730 ps | ||
T199 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3425038969 | Aug 16 04:39:26 PM PDT 24 | Aug 16 04:39:56 PM PDT 24 | 5102937765 ps | ||
T482 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.239407328 | Aug 16 04:39:49 PM PDT 24 | Aug 16 04:40:17 PM PDT 24 | 1463941708 ps | ||
T483 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3423825280 | Aug 16 04:39:57 PM PDT 24 | Aug 16 04:39:58 PM PDT 24 | 92227596 ps |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.1663587828 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1875084118 ps |
CPU time | 3.19 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 213060 kb |
Host | smart-b93e8860-fc5c-497c-a6ef-939f27eab69a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663587828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1663587828 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1711370169 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 12928450836 ps |
CPU time | 58.54 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:43:12 PM PDT 24 |
Peak memory | 221720 kb |
Host | smart-5d7e2e76-96e2-4bd7-865c-8c05fd3a98df |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711370169 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.1711370169 |
Directory | /workspace/7.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2937069764 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 17137481062 ps |
CPU time | 36.57 seconds |
Started | Aug 16 04:42:28 PM PDT 24 |
Finished | Aug 16 04:43:05 PM PDT 24 |
Peak memory | 205512 kb |
Host | smart-f1464eb0-2bb1-4f27-a188-b00fa6804f8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937069764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2937069764 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.3938713562 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 3494357132 ps |
CPU time | 54.04 seconds |
Started | Aug 16 04:42:18 PM PDT 24 |
Finished | Aug 16 04:43:13 PM PDT 24 |
Peak memory | 218296 kb |
Host | smart-55b054f3-1bb3-4e17-bbb1-6f51f8e4764c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938713562 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.3938713562 |
Directory | /workspace/9.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1488917530 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 9707896719 ps |
CPU time | 22.8 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:40:28 PM PDT 24 |
Peak memory | 221836 kb |
Host | smart-1c7b1d48-d2ce-4a6e-8f6d-b092787b62e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488917530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1488917530 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.3685229209 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 8785453934 ps |
CPU time | 23.59 seconds |
Started | Aug 16 04:41:54 PM PDT 24 |
Finished | Aug 16 04:42:18 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-cc59c024-ceea-4b93-8c2d-b397d4eae8c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685229209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3685229209 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.1750259758 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 2406124367 ps |
CPU time | 59.2 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:43:04 PM PDT 24 |
Peak memory | 217532 kb |
Host | smart-32926c2e-d0d6-446f-9d24-ad47bd2d3a40 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750259758 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.1750259758 |
Directory | /workspace/1.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3099429878 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 2475412617 ps |
CPU time | 59.94 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:41:05 PM PDT 24 |
Peak memory | 216096 kb |
Host | smart-532edefd-b058-46a4-a727-022cc00f7aa6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099429878 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3099429878 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_buffered_enable.2498040739 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 191880726 ps |
CPU time | 1.01 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 225768 kb |
Host | smart-687f653e-1e2c-4112-b4c5-a7ad282eeb8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498040739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2498040739 |
Directory | /workspace/1.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1846739007 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 11865100521 ps |
CPU time | 18.95 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:42 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-6f68da3c-aa1a-4019-a0cc-82ba4587ce90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846739007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1846739007 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_scanmode.784628946 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 23888558 ps |
CPU time | 0.69 seconds |
Started | Aug 16 04:41:57 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-6b0d0bee-e088-4926-a8fb-7699aa45b839 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784628946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.784628946 |
Directory | /workspace/0.rv_dm_scanmode/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.1850798315 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2283301944 ps |
CPU time | 18.15 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:31 PM PDT 24 |
Peak memory | 221444 kb |
Host | smart-d20f1990-7d8b-41ad-ae49-16827d1be566 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850798315 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.1850798315 |
Directory | /workspace/3.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.1879708407 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 473530911 ps |
CPU time | 1.38 seconds |
Started | Aug 16 04:41:53 PM PDT 24 |
Finished | Aug 16 04:41:55 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-55385978-f1b8-4db1-8de1-0371e08a0969 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879708407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1879708407 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.3304669834 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 83783510 ps |
CPU time | 0.8 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-8b2b50e9-13b5-41b2-b8ef-a84abd479770 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304669834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3304669834 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.535886777 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 4493534162 ps |
CPU time | 37.64 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:40:37 PM PDT 24 |
Peak memory | 222004 kb |
Host | smart-9317bd3a-85f9-4cea-936b-dff2da9b6e50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535886777 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.535886777 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.624037415 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 151580889 ps |
CPU time | 4.51 seconds |
Started | Aug 16 04:40:01 PM PDT 24 |
Finished | Aug 16 04:40:06 PM PDT 24 |
Peak memory | 219624 kb |
Host | smart-cfec2efb-f885-494b-a0fa-7a9dfa5f2527 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624037415 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.624037415 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.1630719851 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 2813701540 ps |
CPU time | 8.75 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:42:04 PM PDT 24 |
Peak memory | 229204 kb |
Host | smart-e8bd0d30-63fa-469d-9f5e-661a65156000 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630719851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1630719851 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.4004249903 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 2731914793 ps |
CPU time | 8.53 seconds |
Started | Aug 16 04:42:30 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-25d165d4-39e1-4a2d-aa9e-e397f9779cc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004249903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.4004249903 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3087446750 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 6311143945 ps |
CPU time | 17.81 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:33 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-65ec2dbd-207f-4218-ab1e-38731f45cffb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087446750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3087446750 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2989917554 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 4061349707 ps |
CPU time | 31.01 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:40:04 PM PDT 24 |
Peak memory | 205484 kb |
Host | smart-305a6d10-fba0-4fcd-adc9-e4d4a15f52f2 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989917554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2989917554 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4055359206 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 2865612262 ps |
CPU time | 20.2 seconds |
Started | Aug 16 04:40:11 PM PDT 24 |
Finished | Aug 16 04:40:32 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-09008321-d591-4572-9437-59ebbbe4ce66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055359206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4 055359206 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.3348765361 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 198377874 ps |
CPU time | 0.88 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-8f07ef6b-0e37-4254-8ce4-b13f9f702d85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348765361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3348765361 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4167106419 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 96555558 ps |
CPU time | 1.85 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:35 PM PDT 24 |
Peak memory | 213916 kb |
Host | smart-d83d1ce6-da1a-4f06-a57e-0f9c7b0094a4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167106419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4167106419 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.2610884673 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 7061656361 ps |
CPU time | 18.25 seconds |
Started | Aug 16 04:42:30 PM PDT 24 |
Finished | Aug 16 04:42:48 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-6132c58e-36c3-4d5a-9f6e-4beb8e90d859 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610884673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2610884673 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.3130263069 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 10666338899 ps |
CPU time | 22.96 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:37 PM PDT 24 |
Peak memory | 229932 kb |
Host | smart-464d01cc-6604-4aec-b81e-a73714f58bb9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130263069 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.3130263069 |
Directory | /workspace/6.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.2941018431 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 144283374 ps |
CPU time | 0.95 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-2681f4b7-7f58-4a93-9a9c-c85d8b9c47fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941018431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2941018431 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3087201043 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 2862560196 ps |
CPU time | 3.36 seconds |
Started | Aug 16 04:42:22 PM PDT 24 |
Finished | Aug 16 04:42:25 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-bcf999aa-7e39-4a5d-a277-d33889c3d413 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087201043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3087201043 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3531735988 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 3947637706 ps |
CPU time | 3.48 seconds |
Started | Aug 16 04:41:53 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-d531c04e-dfd6-485d-9c1b-84f02dcc05ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531735988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3531735988 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3425038969 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 5102937765 ps |
CPU time | 30.11 seconds |
Started | Aug 16 04:39:26 PM PDT 24 |
Finished | Aug 16 04:39:56 PM PDT 24 |
Peak memory | 221784 kb |
Host | smart-410c8a43-f50e-40a6-8390-2c77434b81dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425038969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3425038969 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.882930666 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 2190518341 ps |
CPU time | 4.76 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-e7b3acc9-f595-4f2e-af53-4d0b6c24aeb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882930666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.882930666 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3780254800 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 760700342 ps |
CPU time | 8.65 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:42 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-d7504595-47fd-4937-b5a6-6f29912f6452 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780254800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3780254800 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.880944100 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 150175843 ps |
CPU time | 0.79 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-8431bdde-b6ca-4220-93ce-8cbead5c8738 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880944100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.880944100 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3041312386 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 1283952594 ps |
CPU time | 16.82 seconds |
Started | Aug 16 04:40:27 PM PDT 24 |
Finished | Aug 16 04:40:44 PM PDT 24 |
Peak memory | 221824 kb |
Host | smart-57613128-4a86-4091-aedf-809c1f48d462 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041312386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3 041312386 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.3953355290 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 6748597333 ps |
CPU time | 12.47 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:45 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-8472835d-d59f-42e7-8d54-ca116da70985 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953355290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3953355290 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.4007310977 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 71067733 ps |
CPU time | 0.98 seconds |
Started | Aug 16 04:42:04 PM PDT 24 |
Finished | Aug 16 04:42:05 PM PDT 24 |
Peak memory | 213208 kb |
Host | smart-395fca95-ddd0-4ae5-9a0a-69d103720dd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007310977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.4007310977 |
Directory | /workspace/3.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3565147959 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 15121481945 ps |
CPU time | 23.55 seconds |
Started | Aug 16 04:39:27 PM PDT 24 |
Finished | Aug 16 04:39:50 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-2925feb4-37f0-43e4-954e-f3a8cd731b33 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565147959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.3565147959 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1649928815 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 6015476319 ps |
CPU time | 17.42 seconds |
Started | Aug 16 04:39:26 PM PDT 24 |
Finished | Aug 16 04:39:44 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-b3680664-4b19-4604-bd99-e10559484d01 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649928815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.1649928815 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.658332373 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 3367485312 ps |
CPU time | 10.15 seconds |
Started | Aug 16 04:42:30 PM PDT 24 |
Finished | Aug 16 04:42:40 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-fec58c60-57b2-4cf8-8c0e-0ed0a191d28a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658332373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.658332373 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1254485900 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 12980569741 ps |
CPU time | 80.38 seconds |
Started | Aug 16 04:40:01 PM PDT 24 |
Finished | Aug 16 04:41:21 PM PDT 24 |
Peak memory | 218648 kb |
Host | smart-4224b1eb-2523-4d93-952a-bf473a31ca54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254485900 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1254485900 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3803308708 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 1492175301 ps |
CPU time | 2.1 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:58 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-210525db-4de0-48af-9fa2-593f13826923 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803308708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3803308708 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.472630828 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 2461441613 ps |
CPU time | 10.09 seconds |
Started | Aug 16 04:40:08 PM PDT 24 |
Finished | Aug 16 04:40:18 PM PDT 24 |
Peak memory | 221956 kb |
Host | smart-8fd869fe-7f3d-4b01-9ba6-24b585dfb675 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472630828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.472630828 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1043365654 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 287004009 ps |
CPU time | 1.17 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-0169f63f-a94e-4ed8-a722-9ae5699cc6bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043365654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1043365654 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.2086385016 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 186613370 ps |
CPU time | 0.85 seconds |
Started | Aug 16 04:41:52 PM PDT 24 |
Finished | Aug 16 04:41:54 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-a4e7619b-1c9a-4626-92c2-832b404fe291 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086385016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.2086385016 |
Directory | /workspace/0.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2904170257 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 18305151355 ps |
CPU time | 84.94 seconds |
Started | Aug 16 04:39:25 PM PDT 24 |
Finished | Aug 16 04:40:50 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-9cca7481-7b8e-495f-94f5-8169e3f149c9 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904170257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2904170257 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3089671366 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 6020848261 ps |
CPU time | 33.88 seconds |
Started | Aug 16 04:39:31 PM PDT 24 |
Finished | Aug 16 04:40:06 PM PDT 24 |
Peak memory | 205736 kb |
Host | smart-fc0d4a5b-173a-45de-98fa-df30be6461aa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089671366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3089671366 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.980763402 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 90449673 ps |
CPU time | 2.18 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:35 PM PDT 24 |
Peak memory | 216556 kb |
Host | smart-b5a8e907-1a59-4641-ba61-326b845468b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980763402 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.980763402 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.938514447 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 356082504 ps |
CPU time | 2.41 seconds |
Started | Aug 16 04:39:34 PM PDT 24 |
Finished | Aug 16 04:39:37 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-3fb95c93-8d13-4a5c-bfcd-c5a134576cc1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938514447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.938514447 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3334615720 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 201579548228 ps |
CPU time | 276.57 seconds |
Started | Aug 16 04:39:31 PM PDT 24 |
Finished | Aug 16 04:44:08 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-520ad560-8811-4fa3-b682-31bdd53ba7fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334615720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3334615720 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1795660419 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 41787137 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:39:25 PM PDT 24 |
Finished | Aug 16 04:39:26 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-46d8f983-adf1-4c16-a92e-debabe223080 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795660419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.1795660419 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1824223118 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 7558511111 ps |
CPU time | 21.39 seconds |
Started | Aug 16 04:39:30 PM PDT 24 |
Finished | Aug 16 04:39:52 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-9d3791ae-c8b0-4141-80b8-1c9f9ec2d54d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824223118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1 824223118 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4127344844 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1680532144 ps |
CPU time | 5.09 seconds |
Started | Aug 16 04:39:28 PM PDT 24 |
Finished | Aug 16 04:39:33 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-b427a13c-cf12-48d4-aaa1-74c759b70051 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127344844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.4127344844 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1064207274 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 779302017 ps |
CPU time | 1.86 seconds |
Started | Aug 16 04:39:24 PM PDT 24 |
Finished | Aug 16 04:39:26 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-8e5b1050-40da-4728-a2ac-5bffe67dd82f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064207274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.1064207274 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1357190951 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 557021865 ps |
CPU time | 1.45 seconds |
Started | Aug 16 04:39:26 PM PDT 24 |
Finished | Aug 16 04:39:28 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-e8b3abb8-0385-4f52-8ccf-587c5b5fe986 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357190951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 357190951 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1634065210 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 26318731 ps |
CPU time | 0.71 seconds |
Started | Aug 16 04:39:24 PM PDT 24 |
Finished | Aug 16 04:39:25 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-10639c38-c84c-43b3-845e-7e141e0ad721 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634065210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1634065210 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1840035752 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 64983131 ps |
CPU time | 0.66 seconds |
Started | Aug 16 04:39:22 PM PDT 24 |
Finished | Aug 16 04:39:23 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-b8a703a9-3543-45af-9123-fd9da789faee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840035752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1840035752 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2581136699 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 320589476 ps |
CPU time | 6.92 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:40 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-3e2dbcd6-6d04-458d-b284-cf3e550da506 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581136699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2581136699 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1645601075 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 5148342832 ps |
CPU time | 32.34 seconds |
Started | Aug 16 04:39:25 PM PDT 24 |
Finished | Aug 16 04:39:58 PM PDT 24 |
Peak memory | 213756 kb |
Host | smart-7b27cd1f-8413-4b48-aee5-30681fb8c292 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645601075 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1645601075 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2330193850 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 320738473 ps |
CPU time | 4.7 seconds |
Started | Aug 16 04:39:24 PM PDT 24 |
Finished | Aug 16 04:39:29 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-b77d52b1-e643-46c1-a498-a819cbb0150e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330193850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2330193850 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.241802527 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 3463710421 ps |
CPU time | 75.67 seconds |
Started | Aug 16 04:39:34 PM PDT 24 |
Finished | Aug 16 04:40:50 PM PDT 24 |
Peak memory | 218468 kb |
Host | smart-94bf5c4c-9cb1-4e09-a5c4-7f26b5d955fa |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241802527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.rv_dm_csr_aliasing.241802527 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1670990023 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 20372683704 ps |
CPU time | 66.44 seconds |
Started | Aug 16 04:39:31 PM PDT 24 |
Finished | Aug 16 04:40:37 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-0f2234b8-545b-492b-b7e8-0ea043d78e7b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670990023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1670990023 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1054397561 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 110595661 ps |
CPU time | 1.59 seconds |
Started | Aug 16 04:39:35 PM PDT 24 |
Finished | Aug 16 04:39:36 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-e84ead96-5f60-4361-b78e-a87a1e16e9da |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054397561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1054397561 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3750222515 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 217063471 ps |
CPU time | 2.83 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:36 PM PDT 24 |
Peak memory | 217488 kb |
Host | smart-90de4a38-7eac-4283-9655-59190df38deb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750222515 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3750222515 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1882242346 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 700347048 ps |
CPU time | 2.37 seconds |
Started | Aug 16 04:39:37 PM PDT 24 |
Finished | Aug 16 04:39:40 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-c6a0f24c-05be-482a-9b77-b9eb086c5f97 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882242346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1882242346 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2299152760 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 28823045020 ps |
CPU time | 69.11 seconds |
Started | Aug 16 04:39:37 PM PDT 24 |
Finished | Aug 16 04:40:46 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-6f6f2526-f6b2-4d17-bd7d-a331d3149197 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299152760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2299152760 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2710865431 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 3389297536 ps |
CPU time | 4.05 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:37 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-9e75b6e2-312f-4e69-bee2-62e7a2fce525 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710865431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2710865431 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1507119286 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 19694382985 ps |
CPU time | 37.16 seconds |
Started | Aug 16 04:39:39 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-e3f2e8b4-3a90-485c-b69c-21b1204bf5c3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507119286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.1507119286 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2657780025 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 1151473428 ps |
CPU time | 4.18 seconds |
Started | Aug 16 04:39:34 PM PDT 24 |
Finished | Aug 16 04:39:38 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-cbacb010-6337-43c5-90f7-24dd240c537c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657780025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 657780025 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3135082182 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 2013548687 ps |
CPU time | 5.57 seconds |
Started | Aug 16 04:39:30 PM PDT 24 |
Finished | Aug 16 04:39:35 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-178079c7-6d3c-4860-8c30-363647f31e1b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135082182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3135082182 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2672376586 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 10497085397 ps |
CPU time | 14.08 seconds |
Started | Aug 16 04:39:34 PM PDT 24 |
Finished | Aug 16 04:39:48 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-04b791bd-14dd-4fbf-810b-fa62636714dc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672376586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2672376586 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3647026942 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 743142187 ps |
CPU time | 1.21 seconds |
Started | Aug 16 04:39:40 PM PDT 24 |
Finished | Aug 16 04:39:41 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-8668ab60-8083-4161-b481-95345d0f9f63 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647026942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.3647026942 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3853580535 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 844470598 ps |
CPU time | 1.33 seconds |
Started | Aug 16 04:39:32 PM PDT 24 |
Finished | Aug 16 04:39:34 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-fa0aaf7e-a4ef-47ef-9649-ec53baf92fde |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853580535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 853580535 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1103975420 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 43429697 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:39:32 PM PDT 24 |
Finished | Aug 16 04:39:33 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-a75d050c-130c-4388-8798-835dc9903b2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103975420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1103975420 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4194392085 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 104572450 ps |
CPU time | 0.94 seconds |
Started | Aug 16 04:39:31 PM PDT 24 |
Finished | Aug 16 04:39:32 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-74c53107-eaa3-4bb8-b796-0c93b1914b5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194392085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4194392085 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2122594107 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 20844633864 ps |
CPU time | 75.41 seconds |
Started | Aug 16 04:39:32 PM PDT 24 |
Finished | Aug 16 04:40:47 PM PDT 24 |
Peak memory | 218952 kb |
Host | smart-1601dea0-b57a-47be-b75c-880af810616a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122594107 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2122594107 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.641221998 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 797449194 ps |
CPU time | 5.91 seconds |
Started | Aug 16 04:39:30 PM PDT 24 |
Finished | Aug 16 04:39:36 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-b07e1f07-f16e-43e1-9f1b-eb458a591437 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641221998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.641221998 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.561392101 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 784886322 ps |
CPU time | 10.28 seconds |
Started | Aug 16 04:39:37 PM PDT 24 |
Finished | Aug 16 04:39:47 PM PDT 24 |
Peak memory | 221796 kb |
Host | smart-cebce0b4-48f5-4a39-a52c-e855209d7e02 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561392101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.561392101 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1501664024 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 133372977 ps |
CPU time | 3.56 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-5c6f89ee-b9f8-4ba7-a0b0-82af0474856a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501664024 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1501664024 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3057904740 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 189997286 ps |
CPU time | 2.58 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-b8c38b15-8609-493b-9a7d-52affc1a92ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057904740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3057904740 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3156235015 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 4364306247 ps |
CPU time | 8.29 seconds |
Started | Aug 16 04:40:08 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-20a1ba4a-0059-4734-9d7b-022cf9604016 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156235015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.3156235015 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3435533596 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 2481985180 ps |
CPU time | 5.49 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:10 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-d4fdb6f1-2e53-4bde-ab2c-33efa16bcb85 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435533596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3435533596 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3843188667 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 93537370 ps |
CPU time | 0.92 seconds |
Started | Aug 16 04:40:07 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-0bd141a4-5486-4600-a18e-d8e218b8f6f6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843188667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 3843188667 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2588127406 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 244028616 ps |
CPU time | 4.21 seconds |
Started | Aug 16 04:40:08 PM PDT 24 |
Finished | Aug 16 04:40:12 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-e8b0c4cc-8f38-482b-afe6-4ff0833bd601 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588127406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.2588127406 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3068934440 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 756077527 ps |
CPU time | 5.38 seconds |
Started | Aug 16 04:40:02 PM PDT 24 |
Finished | Aug 16 04:40:07 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-556b74f2-092e-4bde-bfc9-e88de1079899 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068934440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3068934440 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2309740432 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 2487858746 ps |
CPU time | 14.62 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:40:20 PM PDT 24 |
Peak memory | 214380 kb |
Host | smart-3a350348-5a9e-4719-a808-e7a469bf9de0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309740432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 309740432 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3755209068 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 75119859 ps |
CPU time | 1.89 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:16 PM PDT 24 |
Peak memory | 214684 kb |
Host | smart-855b28b5-148a-4829-a814-6dfb1fc5d850 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755209068 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3755209068 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1345167290 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 74401508 ps |
CPU time | 1.64 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:06 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-1fea8f13-5b11-482a-98f0-863bd31ded18 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345167290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1345167290 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.371670689 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 14405047515 ps |
CPU time | 24.25 seconds |
Started | Aug 16 04:40:06 PM PDT 24 |
Finished | Aug 16 04:40:31 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-d24ea8ff-450b-41e5-93ab-e5fa04b25a39 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371670689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.371670689 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1056749014 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 2754406722 ps |
CPU time | 2.83 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-109e1896-16fc-4de9-b5c4-6ddbf20a8795 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056749014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 1056749014 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1305067478 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 124172157 ps |
CPU time | 1 seconds |
Started | Aug 16 04:40:07 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-59872e63-60c3-496a-8fd9-33571799150f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305067478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 1305067478 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3785558814 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 759610111 ps |
CPU time | 6.81 seconds |
Started | Aug 16 04:40:15 PM PDT 24 |
Finished | Aug 16 04:40:22 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-a3d1d29c-7d2f-4b32-8d6e-3a260f684e2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785558814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3785558814 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2544972028 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 344927391 ps |
CPU time | 3.27 seconds |
Started | Aug 16 04:40:12 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-002ece10-40de-4776-a992-9827d210a749 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544972028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2544972028 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1190230925 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 111709598 ps |
CPU time | 3.27 seconds |
Started | Aug 16 04:40:11 PM PDT 24 |
Finished | Aug 16 04:40:14 PM PDT 24 |
Peak memory | 218240 kb |
Host | smart-c5550530-6af3-4e9e-9dfd-03f91b1939a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190230925 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1190230925 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2105232188 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 221549721 ps |
CPU time | 2.31 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:16 PM PDT 24 |
Peak memory | 213760 kb |
Host | smart-560640cc-57be-4671-bfb4-20fc82ac82da |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105232188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2105232188 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.131099307 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 9764991466 ps |
CPU time | 20.82 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:34 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-c7971b2c-e672-4b54-afac-4ea48f34bb2c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131099307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rv_dm_jtag_dmi_csr_bit_bash.131099307 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2604417298 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 8028587696 ps |
CPU time | 12.9 seconds |
Started | Aug 16 04:40:12 PM PDT 24 |
Finished | Aug 16 04:40:25 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-fb67213a-6cb0-460b-9add-5bc3a8963801 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604417298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 2604417298 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1833938529 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 158994697 ps |
CPU time | 0.87 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:21 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-bc780051-76dc-48b5-a0a1-937411e1c8d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833938529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 1833938529 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2673988426 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 368732119 ps |
CPU time | 3.49 seconds |
Started | Aug 16 04:40:12 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 205540 kb |
Host | smart-ec4a9262-8b18-44ef-9993-aa3629f302b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673988426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2673988426 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2383335029 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 129018591 ps |
CPU time | 4.66 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:18 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-7f1d8b43-4094-471a-8549-2a99ce4531ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383335029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2383335029 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1647340138 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 4075586355 ps |
CPU time | 13.11 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:27 PM PDT 24 |
Peak memory | 221832 kb |
Host | smart-ab7dfcee-8de3-4a18-ba28-51e7713754a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647340138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 647340138 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2131884642 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 410687703 ps |
CPU time | 1.68 seconds |
Started | Aug 16 04:40:12 PM PDT 24 |
Finished | Aug 16 04:40:14 PM PDT 24 |
Peak memory | 214932 kb |
Host | smart-4c3554ad-08a4-47b7-aaad-7fff86e08b11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131884642 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2131884642 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.431012844 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 339979022 ps |
CPU time | 1.79 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 218704 kb |
Host | smart-4a0018ac-715d-4d1c-be71-89b84bcfe0fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431012844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.431012844 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1353043393 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 10878259297 ps |
CPU time | 7.46 seconds |
Started | Aug 16 04:40:11 PM PDT 24 |
Finished | Aug 16 04:40:19 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-e63b8f29-0a59-4ae6-91ee-37c587c3124e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353043393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1353043393 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2226578894 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 13978102091 ps |
CPU time | 7.36 seconds |
Started | Aug 16 04:40:16 PM PDT 24 |
Finished | Aug 16 04:40:24 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-6a4b5601-a9b7-4b3f-acf6-a0af07250fad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226578894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 2226578894 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2053621094 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 256306674 ps |
CPU time | 1.18 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-c192fffd-bf62-4231-8fa7-c7bfdd832db5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053621094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2053621094 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.917317048 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 441765981 ps |
CPU time | 7.53 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:20 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-28e940c8-b764-4f96-8cb6-3026f2cd611b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917317048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.917317048 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2512877566 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 203147942 ps |
CPU time | 2.61 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:16 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-f1a814ad-4d33-4ca2-8378-591ad107b4ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512877566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2512877566 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2298934399 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 73846167 ps |
CPU time | 2.32 seconds |
Started | Aug 16 04:40:23 PM PDT 24 |
Finished | Aug 16 04:40:25 PM PDT 24 |
Peak memory | 217688 kb |
Host | smart-e5bb5dc5-1778-4ab2-a8c4-08e2fbfc6060 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298934399 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2298934399 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2176216546 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 79293128 ps |
CPU time | 2.16 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-343313b6-74ca-4448-9498-6edf257a4314 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176216546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2176216546 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1822977300 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 16935170481 ps |
CPU time | 30.11 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:45 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-d444616d-83d0-47d9-b873-80e9e71c77ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822977300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.1822977300 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3081060824 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 2938773218 ps |
CPU time | 3.9 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-d5e13e6c-7dff-462f-a290-194e5b68b676 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081060824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3081060824 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1861624531 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 592356094 ps |
CPU time | 0.77 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:14 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-5993b616-44f8-4d9d-95c0-3e0c7e406991 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861624531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 1861624531 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2425695076 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 843966336 ps |
CPU time | 7.56 seconds |
Started | Aug 16 04:40:20 PM PDT 24 |
Finished | Aug 16 04:40:28 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-a3430ae7-68b1-4d15-adcb-7c6eac49bc46 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425695076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.2425695076 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2938758153 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 923308160 ps |
CPU time | 6.01 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:19 PM PDT 24 |
Peak memory | 215956 kb |
Host | smart-bd393218-908f-41ef-b598-846b96428bed |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938758153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2938758153 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3779474173 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 644558764 ps |
CPU time | 9.12 seconds |
Started | Aug 16 04:40:14 PM PDT 24 |
Finished | Aug 16 04:40:23 PM PDT 24 |
Peak memory | 213908 kb |
Host | smart-f55c44c8-1882-499f-827e-2151f34caa87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779474173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 779474173 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.353361027 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 132897700 ps |
CPU time | 3.44 seconds |
Started | Aug 16 04:40:21 PM PDT 24 |
Finished | Aug 16 04:40:25 PM PDT 24 |
Peak memory | 219696 kb |
Host | smart-7326e848-34a0-42f6-a190-e6b70fa39f3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353361027 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.353361027 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2217541596 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 86109070 ps |
CPU time | 1.63 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:21 PM PDT 24 |
Peak memory | 219140 kb |
Host | smart-05a054e2-5a46-4e3b-b16b-074b6cae272a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217541596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2217541596 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2022531204 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 25510752739 ps |
CPU time | 22.85 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:42 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-f6f4408b-4630-4750-bba3-91f9cf320f6d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022531204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.2022531204 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2934370159 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 3230037272 ps |
CPU time | 4.47 seconds |
Started | Aug 16 04:40:22 PM PDT 24 |
Finished | Aug 16 04:40:26 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-a9731444-f4e2-46c4-b8a0-409ff9539e3e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934370159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 2934370159 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.226742408 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 355582741 ps |
CPU time | 1.19 seconds |
Started | Aug 16 04:40:18 PM PDT 24 |
Finished | Aug 16 04:40:19 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-c4025206-b1ee-485c-9cff-2af293e7cf97 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226742408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.226742408 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2949274362 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 392729751 ps |
CPU time | 3.69 seconds |
Started | Aug 16 04:40:17 PM PDT 24 |
Finished | Aug 16 04:40:21 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-615738f3-2fa8-473d-8499-f7815502aba5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949274362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.2949274362 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1976345387 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 925473069 ps |
CPU time | 4.51 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:24 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-4fc38caf-5e46-4f21-99cf-10b64e74b767 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976345387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1976345387 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1919312577 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 5714726902 ps |
CPU time | 21.96 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:42 PM PDT 24 |
Peak memory | 222020 kb |
Host | smart-ace4bdf8-860b-4550-93f8-a652fa6ff5ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919312577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1 919312577 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.305516188 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 237109628 ps |
CPU time | 3.02 seconds |
Started | Aug 16 04:40:22 PM PDT 24 |
Finished | Aug 16 04:40:25 PM PDT 24 |
Peak memory | 219372 kb |
Host | smart-20533cfb-3a87-4f13-9191-365b2d3fb287 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305516188 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.305516188 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3196737750 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 146645374 ps |
CPU time | 2.54 seconds |
Started | Aug 16 04:40:21 PM PDT 24 |
Finished | Aug 16 04:40:23 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-c09167a4-a54d-45ee-bfa1-41879d223e13 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196737750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3196737750 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1480498342 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 11700207295 ps |
CPU time | 8.89 seconds |
Started | Aug 16 04:40:20 PM PDT 24 |
Finished | Aug 16 04:40:29 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-7e1b19e2-c8ab-435d-b143-1d4645f355b4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480498342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.1480498342 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3230387639 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 5175886737 ps |
CPU time | 7.92 seconds |
Started | Aug 16 04:40:20 PM PDT 24 |
Finished | Aug 16 04:40:28 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-d5b45246-c1dc-4ce3-bb14-f29b146df589 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230387639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 3230387639 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2459468747 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 204007507 ps |
CPU time | 1.05 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:20 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-6329b961-875b-4b17-959c-d3716e67fee9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459468747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2459468747 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1829551241 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 461722329 ps |
CPU time | 7.2 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:26 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-ee49629e-87e9-40a4-a56a-85803631155d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829551241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.1829551241 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1135541329 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 102668627 ps |
CPU time | 5.86 seconds |
Started | Aug 16 04:40:20 PM PDT 24 |
Finished | Aug 16 04:40:26 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-662b94f4-bbe5-4358-9591-f18ac7c720d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135541329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1135541329 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2362886864 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 483279361 ps |
CPU time | 9 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:28 PM PDT 24 |
Peak memory | 221736 kb |
Host | smart-7f8da3d1-8de1-4763-aace-98bf27cfd133 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362886864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2 362886864 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3469730540 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 286672049 ps |
CPU time | 2.02 seconds |
Started | Aug 16 04:40:27 PM PDT 24 |
Finished | Aug 16 04:40:29 PM PDT 24 |
Peak memory | 216532 kb |
Host | smart-edd50ecb-2498-4156-a950-9ef97904532a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469730540 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3469730540 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1498231206 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 226030026 ps |
CPU time | 2.55 seconds |
Started | Aug 16 04:40:21 PM PDT 24 |
Finished | Aug 16 04:40:24 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-66a5d009-f4ff-4472-b285-3fc078a22a6d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498231206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1498231206 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1249629565 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 17888281772 ps |
CPU time | 45.92 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:41:05 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-f56fe3a7-9390-44be-b136-35c6f9e2dd4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249629565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.1249629565 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2873244506 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 9318181281 ps |
CPU time | 15.57 seconds |
Started | Aug 16 04:40:23 PM PDT 24 |
Finished | Aug 16 04:40:39 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-db144d7c-4fc5-4d52-bcbb-bf064e9202ca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873244506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 2873244506 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4142055092 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 244049307 ps |
CPU time | 1.29 seconds |
Started | Aug 16 04:40:21 PM PDT 24 |
Finished | Aug 16 04:40:23 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-01d4d441-cee2-42e4-bf53-d3de5030cf48 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142055092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 4142055092 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2807376092 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 848334801 ps |
CPU time | 8.24 seconds |
Started | Aug 16 04:40:21 PM PDT 24 |
Finished | Aug 16 04:40:30 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-8eee258b-eaaa-480d-9394-26d997bd5125 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807376092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2807376092 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3347902275 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 366658607 ps |
CPU time | 3.52 seconds |
Started | Aug 16 04:40:21 PM PDT 24 |
Finished | Aug 16 04:40:25 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-a02288c3-c90f-4a5d-b5fe-e1d6c6e6da37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347902275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3347902275 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.696643491 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 7199447994 ps |
CPU time | 11.31 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:31 PM PDT 24 |
Peak memory | 213832 kb |
Host | smart-93f32cb7-4f7b-46c4-9c68-24a26bfb3677 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696643491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.696643491 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1143468803 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 64269449 ps |
CPU time | 2.21 seconds |
Started | Aug 16 04:40:22 PM PDT 24 |
Finished | Aug 16 04:40:24 PM PDT 24 |
Peak memory | 213912 kb |
Host | smart-d4650959-958d-4925-99ba-bdc7cab435e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143468803 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1143468803 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3824043273 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 219100540 ps |
CPU time | 1.52 seconds |
Started | Aug 16 04:40:23 PM PDT 24 |
Finished | Aug 16 04:40:25 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-241cdc63-2130-4b86-afa6-979eeebddd20 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824043273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3824043273 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1740324688 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 10474874953 ps |
CPU time | 8.09 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:27 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-6c21ceb3-dd06-4616-b085-fcb82f4d99bc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740324688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1740324688 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1217324730 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 2192753024 ps |
CPU time | 7.15 seconds |
Started | Aug 16 04:40:20 PM PDT 24 |
Finished | Aug 16 04:40:27 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-076973a5-77cd-4f0a-a248-6d32c1bd729a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217324730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 1217324730 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.50209830 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 116677814 ps |
CPU time | 0.77 seconds |
Started | Aug 16 04:40:22 PM PDT 24 |
Finished | Aug 16 04:40:23 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-11cc3139-2546-481e-9621-82cd07ca216e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50209830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.50209830 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2449528854 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 2065022344 ps |
CPU time | 7.61 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:27 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-9f49ff75-5649-41a0-b81a-4db8e58f4458 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449528854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2449528854 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.880917348 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 145478423 ps |
CPU time | 3.02 seconds |
Started | Aug 16 04:40:19 PM PDT 24 |
Finished | Aug 16 04:40:22 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-1b0df262-1aa8-4eee-8ceb-69f5de847459 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880917348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.880917348 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4256156077 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 4287023079 ps |
CPU time | 20.37 seconds |
Started | Aug 16 04:40:27 PM PDT 24 |
Finished | Aug 16 04:40:48 PM PDT 24 |
Peak memory | 221896 kb |
Host | smart-db021d0a-3beb-4f88-85eb-993a587d18f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256156077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4 256156077 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2042327292 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 81879448 ps |
CPU time | 1.92 seconds |
Started | Aug 16 04:40:30 PM PDT 24 |
Finished | Aug 16 04:40:32 PM PDT 24 |
Peak memory | 215948 kb |
Host | smart-e74c1807-0e76-4460-8fdc-e0fb21874912 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042327292 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2042327292 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2826039577 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 139070198 ps |
CPU time | 1.51 seconds |
Started | Aug 16 04:40:30 PM PDT 24 |
Finished | Aug 16 04:40:31 PM PDT 24 |
Peak memory | 219068 kb |
Host | smart-4859e982-5e91-4d82-8b53-c06be58e9d7f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826039577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2826039577 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3353241552 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 72381667486 ps |
CPU time | 95.18 seconds |
Started | Aug 16 04:40:29 PM PDT 24 |
Finished | Aug 16 04:42:04 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-5c6fad9e-7335-46bf-a040-b76acf897264 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353241552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.3353241552 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.5588798 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 1652375589 ps |
CPU time | 5.37 seconds |
Started | Aug 16 04:40:28 PM PDT 24 |
Finished | Aug 16 04:40:34 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-9c926da5-c7cf-4d5c-8a7b-7f778df75083 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5588798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.5588798 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1001938790 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 382434388 ps |
CPU time | 1.1 seconds |
Started | Aug 16 04:40:33 PM PDT 24 |
Finished | Aug 16 04:40:35 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-d4c1af9f-9f00-49f1-8f74-236cd2d7133e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001938790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 1001938790 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4041862139 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 430701569 ps |
CPU time | 3.94 seconds |
Started | Aug 16 04:40:28 PM PDT 24 |
Finished | Aug 16 04:40:32 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-3093a5d8-a524-41c4-92fa-367e558332e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041862139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.4041862139 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.79181928 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 512711989 ps |
CPU time | 5.4 seconds |
Started | Aug 16 04:40:28 PM PDT 24 |
Finished | Aug 16 04:40:34 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-8636e349-754b-4b4f-9a38-2632043e8e8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79181928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.79181928 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2668243922 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 1437086273 ps |
CPU time | 28.49 seconds |
Started | Aug 16 04:39:40 PM PDT 24 |
Finished | Aug 16 04:40:09 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-789c2ec3-3962-4dff-88b0-f220fc0356b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668243922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2668243922 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2736173503 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 348709738 ps |
CPU time | 1.79 seconds |
Started | Aug 16 04:39:41 PM PDT 24 |
Finished | Aug 16 04:39:43 PM PDT 24 |
Peak memory | 213828 kb |
Host | smart-b8794c0b-4a0f-4af6-9268-05fc533796c9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736173503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2736173503 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2708345281 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 372609133 ps |
CPU time | 2.82 seconds |
Started | Aug 16 04:39:44 PM PDT 24 |
Finished | Aug 16 04:39:47 PM PDT 24 |
Peak memory | 217172 kb |
Host | smart-3a734472-2b31-4bfc-97bb-0500ea50fc34 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708345281 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2708345281 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2656165924 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 425252845 ps |
CPU time | 1.49 seconds |
Started | Aug 16 04:39:44 PM PDT 24 |
Finished | Aug 16 04:39:46 PM PDT 24 |
Peak memory | 218268 kb |
Host | smart-d60e7940-c918-4017-9091-d5a7d1be3b2d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656165924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2656165924 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2367680171 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 42168727170 ps |
CPU time | 59.5 seconds |
Started | Aug 16 04:39:39 PM PDT 24 |
Finished | Aug 16 04:40:38 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-4307ebf0-8cc5-4ab4-a1b2-be70f9a56a0a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367680171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2367680171 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2893923398 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 4630811379 ps |
CPU time | 3.01 seconds |
Started | Aug 16 04:39:38 PM PDT 24 |
Finished | Aug 16 04:39:41 PM PDT 24 |
Peak memory | 205452 kb |
Host | smart-815cc922-86de-46c2-8d56-44a05f851737 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893923398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.2893923398 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1852658028 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 17626779756 ps |
CPU time | 18.29 seconds |
Started | Aug 16 04:39:42 PM PDT 24 |
Finished | Aug 16 04:40:00 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-2b974657-9d54-472e-bbda-6245dee6c544 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852658028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1852658028 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.28156904 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 4059502955 ps |
CPU time | 8.22 seconds |
Started | Aug 16 04:39:39 PM PDT 24 |
Finished | Aug 16 04:39:47 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-c0193d5c-bdfe-4b5e-b01f-fd57f437333f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.28156904 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1377661233 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 169414266 ps |
CPU time | 1.11 seconds |
Started | Aug 16 04:39:38 PM PDT 24 |
Finished | Aug 16 04:39:40 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-efc45600-9b9c-4902-a228-60b51f71be98 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377661233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1377661233 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2445952142 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 2300416814 ps |
CPU time | 4.34 seconds |
Started | Aug 16 04:39:40 PM PDT 24 |
Finished | Aug 16 04:39:45 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-918c7e50-6997-496a-a439-badfbff233c0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445952142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.2445952142 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2566966835 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 1208096611 ps |
CPU time | 1.02 seconds |
Started | Aug 16 04:39:33 PM PDT 24 |
Finished | Aug 16 04:39:34 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-2be5655a-94f9-4344-994a-05ecdee9b9c2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566966835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2566966835 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2924321049 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 318731725 ps |
CPU time | 1.02 seconds |
Started | Aug 16 04:39:34 PM PDT 24 |
Finished | Aug 16 04:39:35 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-8999a31a-e561-4729-a73c-d42631cef47f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924321049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 924321049 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1943463792 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 117115212 ps |
CPU time | 0.78 seconds |
Started | Aug 16 04:39:41 PM PDT 24 |
Finished | Aug 16 04:39:42 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-02ed2428-d73b-40c9-b8f8-0548e832c998 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943463792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1943463792 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2985023949 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 91966206 ps |
CPU time | 0.71 seconds |
Started | Aug 16 04:39:42 PM PDT 24 |
Finished | Aug 16 04:39:43 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-d86437d2-f986-43eb-bba5-0ddc9646b445 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985023949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2985023949 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3506435700 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 556549453 ps |
CPU time | 8.06 seconds |
Started | Aug 16 04:39:39 PM PDT 24 |
Finished | Aug 16 04:39:47 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-2d410376-d59f-418d-8cb1-dab378fa50e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506435700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3506435700 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.936383065 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 3601295487 ps |
CPU time | 65.06 seconds |
Started | Aug 16 04:39:40 PM PDT 24 |
Finished | Aug 16 04:40:45 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-1b37df5c-bb6a-4793-8e2a-66e6050ffc07 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936383065 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.936383065 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1391708557 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 64898110 ps |
CPU time | 2.48 seconds |
Started | Aug 16 04:39:38 PM PDT 24 |
Finished | Aug 16 04:39:41 PM PDT 24 |
Peak memory | 213772 kb |
Host | smart-dd58b7d7-efb2-44ca-91a0-7c6a9382c30b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391708557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1391708557 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.76919194 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 4081149845 ps |
CPU time | 12.62 seconds |
Started | Aug 16 04:39:41 PM PDT 24 |
Finished | Aug 16 04:39:54 PM PDT 24 |
Peak memory | 221804 kb |
Host | smart-c13d83b9-bb16-442e-add5-bc24fccd9c08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76919194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.76919194 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1288433902 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 2100118319 ps |
CPU time | 27.49 seconds |
Started | Aug 16 04:39:44 PM PDT 24 |
Finished | Aug 16 04:40:12 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-d96a61cc-6fbc-4484-a7f4-92db128f9dab |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288433902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1288433902 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.239407328 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 1463941708 ps |
CPU time | 28.26 seconds |
Started | Aug 16 04:39:49 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-4d5565fc-fe3a-4181-b73c-7bfdb93d1140 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239407328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.239407328 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.512967812 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 274288917 ps |
CPU time | 2.12 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:39:53 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-8e13ae0a-5ec3-45a6-a264-8d2c7e712515 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512967812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.512967812 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4045595666 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 737542525 ps |
CPU time | 2.87 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:39:55 PM PDT 24 |
Peak memory | 217136 kb |
Host | smart-76b7b41c-e126-46f0-9233-1e1cf5e75ebc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045595666 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4045595666 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.124508136 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 81863452 ps |
CPU time | 2.32 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:39:53 PM PDT 24 |
Peak memory | 219240 kb |
Host | smart-1e5330f2-c480-4a67-9939-2ca2a473fabe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124508136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.124508136 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.368036105 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 37442589011 ps |
CPU time | 107.81 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:41:38 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-a3e68c40-358c-4519-9018-feb47b35e245 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368036105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _aliasing.368036105 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2332970584 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 18303477591 ps |
CPU time | 26.87 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-039fe740-b235-4dbb-a549-8004dfbee9de |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332970584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.2332970584 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4078020457 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 2123057391 ps |
CPU time | 2.23 seconds |
Started | Aug 16 04:39:48 PM PDT 24 |
Finished | Aug 16 04:39:51 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-d6debeb1-fcdd-4426-aa7c-2024762bd651 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078020457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.4078020457 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.93024349 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 15242576246 ps |
CPU time | 11.79 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:40:02 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-82f87892-26ac-406d-8dd4-73f58448e867 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93024349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.93024349 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.610482171 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 590913698 ps |
CPU time | 1.18 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:39:53 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-3112f3ac-4449-40f5-ae8e-165f57a76749 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610482171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _aliasing.610482171 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.126066792 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 16970704040 ps |
CPU time | 27.44 seconds |
Started | Aug 16 04:39:40 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-47c4b134-4836-4405-a3f1-db53fc95aef5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126066792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _bit_bash.126066792 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1397287565 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 418456004 ps |
CPU time | 1.81 seconds |
Started | Aug 16 04:39:42 PM PDT 24 |
Finished | Aug 16 04:39:44 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-4d183cbb-42ef-4bb4-a060-b38fe380de66 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397287565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1397287565 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1439465659 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 230185102 ps |
CPU time | 0.94 seconds |
Started | Aug 16 04:39:38 PM PDT 24 |
Finished | Aug 16 04:39:40 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-4b897270-a73d-4703-bfeb-a2a3990e6f7c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439465659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1 439465659 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3460423050 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 24438176 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:39:52 PM PDT 24 |
Finished | Aug 16 04:39:53 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-b99b56b9-bf2a-45c2-8978-a2ec4d6817d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460423050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.3460423050 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4179282628 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 139476933 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:39:53 PM PDT 24 |
Finished | Aug 16 04:39:54 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-1319cca0-6f6b-4aba-a7a1-0f3cc13d89a4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179282628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4179282628 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3195188118 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 790523014 ps |
CPU time | 7.07 seconds |
Started | Aug 16 04:39:49 PM PDT 24 |
Finished | Aug 16 04:39:57 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-ff60c61b-67a1-49ff-8a47-14cb08cdded9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195188118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.3195188118 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4167937545 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 58611869985 ps |
CPU time | 76.59 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:41:08 PM PDT 24 |
Peak memory | 221016 kb |
Host | smart-957385f5-fb4f-4e99-b4b0-efef4e5b6d83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167937545 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4167937545 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1356059412 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 368574621 ps |
CPU time | 3.93 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:39:55 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-0ee58720-710b-46d1-84df-156a967f333e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356059412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1356059412 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2640103629 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 3167312616 ps |
CPU time | 11.81 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:40:03 PM PDT 24 |
Peak memory | 221856 kb |
Host | smart-87797ab2-7662-4f38-9b93-46ac0f535880 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640103629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2640103629 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2104877841 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 4322010495 ps |
CPU time | 77.9 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:41:08 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-477ec2a0-a094-4e30-86d5-4353fa841978 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104877841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2104877841 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1378678074 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 3847448121 ps |
CPU time | 33.57 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:40:33 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-0c8122a4-1870-46ef-9f97-16c9897ec45f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378678074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1378678074 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1097049908 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 163441811 ps |
CPU time | 1.66 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:40:01 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-5b78bd44-74d7-4a88-8888-3bcbed71e4e3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097049908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1097049908 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2941887890 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 240840410 ps |
CPU time | 1.91 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:06 PM PDT 24 |
Peak memory | 215284 kb |
Host | smart-9acddb91-f800-4919-aebc-7cfdfd183bfe |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941887890 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2941887890 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.552121123 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 130066730 ps |
CPU time | 1.57 seconds |
Started | Aug 16 04:39:56 PM PDT 24 |
Finished | Aug 16 04:39:58 PM PDT 24 |
Peak memory | 218448 kb |
Host | smart-928cf5bf-eec3-413f-848d-3cc9c22ffc81 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552121123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.552121123 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3776830188 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 110635663154 ps |
CPU time | 78.04 seconds |
Started | Aug 16 04:39:53 PM PDT 24 |
Finished | Aug 16 04:41:11 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-6ebc839c-74a3-44da-897a-587cb0f53aee |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776830188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3776830188 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3936468400 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 64506467122 ps |
CPU time | 83.29 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:41:15 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-b1a383d3-9922-4989-bff0-c075077a50b0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936468400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.3936468400 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2762980194 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 9459277758 ps |
CPU time | 6.91 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:39:57 PM PDT 24 |
Peak memory | 205452 kb |
Host | smart-67d962a6-84f3-4f98-95ea-f3847ea22ede |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762980194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2762980194 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3172276435 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 3995161947 ps |
CPU time | 12.32 seconds |
Started | Aug 16 04:39:49 PM PDT 24 |
Finished | Aug 16 04:40:02 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-1d97d5ba-c5b4-4a12-8a09-5580c5c01f82 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172276435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 172276435 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3759282911 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 322439728 ps |
CPU time | 0.78 seconds |
Started | Aug 16 04:39:49 PM PDT 24 |
Finished | Aug 16 04:39:50 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-242bf542-cfc6-4b0f-96db-eca7d63e5d8e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759282911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.3759282911 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.614091312 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 15966256265 ps |
CPU time | 12.24 seconds |
Started | Aug 16 04:39:50 PM PDT 24 |
Finished | Aug 16 04:40:02 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-f44b7180-9c0b-4476-8ec4-9eb3393589ef |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614091312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.614091312 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2560959174 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 499343640 ps |
CPU time | 1.37 seconds |
Started | Aug 16 04:39:48 PM PDT 24 |
Finished | Aug 16 04:39:50 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-91f25fb8-4e14-4e6e-94a1-9f6a9fb716fd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560959174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.2560959174 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.537279162 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 455613222 ps |
CPU time | 1.51 seconds |
Started | Aug 16 04:39:51 PM PDT 24 |
Finished | Aug 16 04:39:53 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-485cae9b-117e-4f5f-a4a1-6c5b7dfaafe6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537279162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.537279162 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3423825280 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 92227596 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:39:57 PM PDT 24 |
Finished | Aug 16 04:39:58 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-3db7dcb2-ed25-4171-91ef-130a5367274b |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423825280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.3423825280 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.636820226 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 108703361 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:39:59 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-4507fd67-e1f6-4d02-8a4c-1503cbc4efa4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636820226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.636820226 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2709344959 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 317216628 ps |
CPU time | 4.35 seconds |
Started | Aug 16 04:39:57 PM PDT 24 |
Finished | Aug 16 04:40:02 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-59ba8b7c-0113-487e-a5c5-dc6e04f41e84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709344959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.2709344959 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1161059759 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 111314132 ps |
CPU time | 5.02 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:06 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-cd1e475f-fddd-4dee-83aa-06b1806b0000 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161059759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1161059759 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.764468398 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 7160475845 ps |
CPU time | 17.65 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:18 PM PDT 24 |
Peak memory | 221804 kb |
Host | smart-a63349cc-af2a-4f60-95e7-f3a75edc5c64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764468398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.764468398 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2577842944 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 265621180 ps |
CPU time | 3.21 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:04 PM PDT 24 |
Peak memory | 221872 kb |
Host | smart-56b1f88d-7d92-48ce-a9f2-b10674225a6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577842944 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2577842944 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4266111222 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 66309324 ps |
CPU time | 1.52 seconds |
Started | Aug 16 04:39:58 PM PDT 24 |
Finished | Aug 16 04:40:00 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-38de9afa-abf7-45de-be3b-6bd037581d74 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266111222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4266111222 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3777778297 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 15076391201 ps |
CPU time | 40.85 seconds |
Started | Aug 16 04:39:57 PM PDT 24 |
Finished | Aug 16 04:40:38 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-4ae76dfa-3086-45ea-a0d8-ba007acb066c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777778297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.3777778297 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3284335249 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 4035472195 ps |
CPU time | 3.14 seconds |
Started | Aug 16 04:40:01 PM PDT 24 |
Finished | Aug 16 04:40:04 PM PDT 24 |
Peak memory | 205504 kb |
Host | smart-db87a44a-8e1d-40bd-b013-ae0f73684576 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284335249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 284335249 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.225465654 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 526651632 ps |
CPU time | 1.96 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:03 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-8b91fb08-f909-4f1c-a72b-6bb6fcf5fcb7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225465654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.225465654 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1734752888 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 192058333 ps |
CPU time | 3.71 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:40:03 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-3264dd12-cc32-4e10-b92a-53c3ec8c8a32 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734752888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1734752888 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1783768149 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 3239112830 ps |
CPU time | 63.37 seconds |
Started | Aug 16 04:39:56 PM PDT 24 |
Finished | Aug 16 04:41:00 PM PDT 24 |
Peak memory | 216984 kb |
Host | smart-36c8d142-b248-4af5-8f01-a75f43b68a8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783768149 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1783768149 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1652156023 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 107879784 ps |
CPU time | 4.51 seconds |
Started | Aug 16 04:39:56 PM PDT 24 |
Finished | Aug 16 04:40:01 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-644a6ed2-2add-43ea-ab33-0445a7a2237a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652156023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1652156023 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1798027395 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 2734494086 ps |
CPU time | 11.66 seconds |
Started | Aug 16 04:40:03 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 221904 kb |
Host | smart-321b55e9-9d97-48ca-83e4-868c1f0410f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798027395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1798027395 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2026885371 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 78161307 ps |
CPU time | 2.12 seconds |
Started | Aug 16 04:39:58 PM PDT 24 |
Finished | Aug 16 04:40:00 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-8bed6a9e-ea05-42ad-8e06-e0dfd0951fc2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026885371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2026885371 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2341374746 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 15172846553 ps |
CPU time | 8.69 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:09 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-cdf33578-cd26-4245-b4fa-99e7d5573496 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341374746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.2341374746 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2057304473 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 1302307682 ps |
CPU time | 2.96 seconds |
Started | Aug 16 04:40:01 PM PDT 24 |
Finished | Aug 16 04:40:04 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-2dc44672-1b9c-41d6-b936-b20cd1b44b21 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057304473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 057304473 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2685699815 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 594537611 ps |
CPU time | 1.43 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:02 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-0ff214e7-940f-4830-a9fb-508dec350060 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685699815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2 685699815 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.553212756 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 194713038 ps |
CPU time | 3.86 seconds |
Started | Aug 16 04:40:01 PM PDT 24 |
Finished | Aug 16 04:40:05 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-4271dec9-82fd-4598-a7a4-fd7c38412a12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553212756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.553212756 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.699575194 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 622545060 ps |
CPU time | 4.76 seconds |
Started | Aug 16 04:39:57 PM PDT 24 |
Finished | Aug 16 04:40:02 PM PDT 24 |
Peak memory | 213708 kb |
Host | smart-06854272-ac13-4f3c-b7ef-0c9142376186 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699575194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.699575194 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.972256337 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 2822331493 ps |
CPU time | 8.6 seconds |
Started | Aug 16 04:40:03 PM PDT 24 |
Finished | Aug 16 04:40:12 PM PDT 24 |
Peak memory | 221832 kb |
Host | smart-de0af634-9fec-4668-952e-1523ccab5ea9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972256337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.972256337 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2705256280 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 125207785 ps |
CPU time | 3.26 seconds |
Started | Aug 16 04:40:07 PM PDT 24 |
Finished | Aug 16 04:40:11 PM PDT 24 |
Peak memory | 220572 kb |
Host | smart-94ac5dfb-3627-4369-9838-e1de894fa567 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705256280 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2705256280 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.958762229 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 118151484 ps |
CPU time | 1.76 seconds |
Started | Aug 16 04:40:03 PM PDT 24 |
Finished | Aug 16 04:40:05 PM PDT 24 |
Peak memory | 218540 kb |
Host | smart-5279dc50-b6f6-416a-982c-ecd7292a2248 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958762229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.958762229 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.791633691 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 10413785781 ps |
CPU time | 4.33 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:05 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-372c6276-29f2-4b08-954d-fa90f651bbff |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791633691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r v_dm_jtag_dmi_csr_bit_bash.791633691 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.76271981 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 7142987153 ps |
CPU time | 7.9 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-6fc931ba-f861-4479-81a3-dc1998cc5fab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76271981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.76271981 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1640349402 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 217305078 ps |
CPU time | 0.82 seconds |
Started | Aug 16 04:39:55 PM PDT 24 |
Finished | Aug 16 04:39:56 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-4d1abd9e-fe0f-4655-9839-66e7d2deabc1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640349402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 640349402 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.664048242 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 665042126 ps |
CPU time | 6.55 seconds |
Started | Aug 16 04:40:08 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-7c726f2c-f0ea-477f-81d2-32a5186d6162 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664048242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c sr_outstanding.664048242 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1589447469 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 9722399013 ps |
CPU time | 21.84 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:40:21 PM PDT 24 |
Peak memory | 217780 kb |
Host | smart-540a9655-6575-48ec-ab65-bd91adc0561d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589447469 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1589447469 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1800057918 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1280651582 ps |
CPU time | 2.96 seconds |
Started | Aug 16 04:39:59 PM PDT 24 |
Finished | Aug 16 04:40:03 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-31dbf2b7-c8f9-4bec-abae-0256165ccc7f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800057918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1800057918 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1700788916 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 10300973657 ps |
CPU time | 22.04 seconds |
Started | Aug 16 04:40:00 PM PDT 24 |
Finished | Aug 16 04:40:22 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-93d57805-c81d-445f-b8b9-e12ae05c72aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700788916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1700788916 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2811373718 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 157192975 ps |
CPU time | 2.27 seconds |
Started | Aug 16 04:40:08 PM PDT 24 |
Finished | Aug 16 04:40:11 PM PDT 24 |
Peak memory | 221832 kb |
Host | smart-bb73d56d-c534-4949-a183-b1cb24ebe315 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811373718 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2811373718 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2626452818 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 217642873 ps |
CPU time | 1.75 seconds |
Started | Aug 16 04:40:06 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-9df29079-6085-4871-a797-60ff6a8015bc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626452818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2626452818 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.194784824 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 7653353439 ps |
CPU time | 10.81 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:15 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-5b006ff8-0781-4ed4-a39d-4d29d199a8aa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194784824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r v_dm_jtag_dmi_csr_bit_bash.194784824 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1442251381 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 2499410636 ps |
CPU time | 7.81 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:12 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-aaa3d31c-e701-4d56-84a6-ec22d21e21fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442251381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1 442251381 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1091093218 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 232304085 ps |
CPU time | 0.83 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:40:06 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-8cffc93a-784e-4fbd-9536-f320a1676e0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091093218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1 091093218 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2767926877 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 825824596 ps |
CPU time | 3.95 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:08 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-401647fe-7c2e-47a5-9406-3d0f26afb0d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767926877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2767926877 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1904191575 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 5290578757 ps |
CPU time | 20.55 seconds |
Started | Aug 16 04:40:03 PM PDT 24 |
Finished | Aug 16 04:40:24 PM PDT 24 |
Peak memory | 217324 kb |
Host | smart-050cb62e-4186-4fb0-92aa-a58104b2dd1e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904191575 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1904191575 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3735020179 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 301195020 ps |
CPU time | 2.65 seconds |
Started | Aug 16 04:40:04 PM PDT 24 |
Finished | Aug 16 04:40:07 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-07e3bc98-cf1d-4f05-904b-3dc93282437c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735020179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3735020179 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3119670698 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 166287678 ps |
CPU time | 2.16 seconds |
Started | Aug 16 04:40:12 PM PDT 24 |
Finished | Aug 16 04:40:14 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-2a5fe2b4-e5da-405f-909b-4c28e4395ff0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119670698 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3119670698 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3413248309 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 196617275 ps |
CPU time | 2.3 seconds |
Started | Aug 16 04:40:06 PM PDT 24 |
Finished | Aug 16 04:40:09 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-0b901533-67dc-4830-a36e-acd9afa5a54e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413248309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3413248309 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2780172444 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 10713173834 ps |
CPU time | 9.36 seconds |
Started | Aug 16 04:40:07 PM PDT 24 |
Finished | Aug 16 04:40:16 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-ca97ddd0-6ee4-40f6-aae3-20301213d7fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780172444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2780172444 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3147782154 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 3422900399 ps |
CPU time | 3.28 seconds |
Started | Aug 16 04:40:05 PM PDT 24 |
Finished | Aug 16 04:40:09 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-bd57ec5e-f097-4da6-a1c3-d3de0de2ce73 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147782154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 147782154 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.923368187 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 338655867 ps |
CPU time | 1.59 seconds |
Started | Aug 16 04:40:06 PM PDT 24 |
Finished | Aug 16 04:40:07 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-8bec44a1-7bf6-4290-b17d-0ee730534750 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923368187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.923368187 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3166561034 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 553924440 ps |
CPU time | 4.16 seconds |
Started | Aug 16 04:40:06 PM PDT 24 |
Finished | Aug 16 04:40:10 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-8ea93223-ebaa-4586-81ba-e693b392bbc8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166561034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.3166561034 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.932134622 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 225286319 ps |
CPU time | 3.71 seconds |
Started | Aug 16 04:40:13 PM PDT 24 |
Finished | Aug 16 04:40:17 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-0db1dbdd-9bf5-49d2-bde1-b800c3885c1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932134622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.932134622 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.50691504 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 4475768168 ps |
CPU time | 23.1 seconds |
Started | Aug 16 04:40:03 PM PDT 24 |
Finished | Aug 16 04:40:26 PM PDT 24 |
Peak memory | 221852 kb |
Host | smart-ca93927d-3d12-4915-9f27-b4e0517b1f5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50691504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.50691504 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1383521052 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 109172167 ps |
CPU time | 0.85 seconds |
Started | Aug 16 04:41:59 PM PDT 24 |
Finished | Aug 16 04:42:00 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-63d60317-d74d-45ef-a6b5-f60fa5efab54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383521052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1383521052 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.4203304823 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 13307514343 ps |
CPU time | 6.4 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:42:02 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-e30a2966-4a96-4956-b8ea-8ca88e488d1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4203304823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4203304823 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3312574853 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1258000416 ps |
CPU time | 1.81 seconds |
Started | Aug 16 04:41:52 PM PDT 24 |
Finished | Aug 16 04:41:54 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-905a33ee-c1f1-459f-86ef-108debd82be9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312574853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3312574853 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_buffered_enable.2771720847 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 505218632 ps |
CPU time | 1.27 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 230824 kb |
Host | smart-162151d9-a2a0-440f-88c2-d4515a321c02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771720847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.2771720847 |
Directory | /workspace/0.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.3649117953 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 427634611 ps |
CPU time | 1.99 seconds |
Started | Aug 16 04:41:52 PM PDT 24 |
Finished | Aug 16 04:41:54 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-7cc7fb48-8381-4e18-8246-948bbdb97a9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3649117953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3649117953 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2772096019 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 198714040 ps |
CPU time | 1 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-5dfb03a3-8082-4544-a819-42ee9f5b6eee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772096019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2772096019 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1023083688 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 147609347 ps |
CPU time | 1.07 seconds |
Started | Aug 16 04:41:54 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-93c85076-df3c-4582-ad15-5a776968bd4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023083688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1023083688 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.2803789326 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 96979787 ps |
CPU time | 0.91 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 214896 kb |
Host | smart-b8336cb1-337c-4a94-8a05-0b472012d933 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803789326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2803789326 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2141337760 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 3621782926 ps |
CPU time | 11.9 seconds |
Started | Aug 16 04:41:54 PM PDT 24 |
Finished | Aug 16 04:42:06 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-073b1e17-5b66-4094-a75b-035fce76b811 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2141337760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.2141337760 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1199481450 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 75202599 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-9b2caeee-5be3-4b5b-af27-1dc8ebf8f842 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1199481450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1199481450 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.3413008338 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 373799107 ps |
CPU time | 1.67 seconds |
Started | Aug 16 04:41:52 PM PDT 24 |
Finished | Aug 16 04:41:54 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-9fa6f114-5d92-40d6-a221-d007c6a359e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413008338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3413008338 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2533681030 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 117384640 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-e5904ca7-5017-438d-a52c-4e12b2cf478d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533681030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2533681030 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3451810686 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 872854601 ps |
CPU time | 2.16 seconds |
Started | Aug 16 04:41:54 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-6fabad21-dc81-480c-979b-03799a1ff45d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451810686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3451810686 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3529408717 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 333847241 ps |
CPU time | 1.08 seconds |
Started | Aug 16 04:41:58 PM PDT 24 |
Finished | Aug 16 04:41:59 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-1121cd44-5e65-43f5-9c47-00a419d13515 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529408717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3529408717 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1528239551 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 660099379 ps |
CPU time | 2.5 seconds |
Started | Aug 16 04:41:57 PM PDT 24 |
Finished | Aug 16 04:42:00 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-a09f39cc-6332-49bb-a3c6-5fbfd5214f7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528239551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1528239551 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3241340541 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 192350941 ps |
CPU time | 0.82 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-358d254b-450c-48cd-bf8c-8969a7dc234e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241340541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3241340541 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.804548778 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 185190883 ps |
CPU time | 1.07 seconds |
Started | Aug 16 04:41:52 PM PDT 24 |
Finished | Aug 16 04:41:53 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-2f82adb4-87c0-422b-ae9c-4a00aea35768 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804548778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.804548778 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.406655365 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 652513591 ps |
CPU time | 1.18 seconds |
Started | Aug 16 04:41:57 PM PDT 24 |
Finished | Aug 16 04:41:58 PM PDT 24 |
Peak memory | 213100 kb |
Host | smart-f5be53f4-8fc9-4681-9c60-f1c930d20d58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406655365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.406655365 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1764380596 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 164850210 ps |
CPU time | 1.18 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-093b8ebd-2717-40ee-90d8-298f04f5ca8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764380596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1764380596 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.1788277763 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 1101270456 ps |
CPU time | 1.77 seconds |
Started | Aug 16 04:41:54 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-6b733318-484d-4f0e-a83b-a97d9568a34d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788277763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1788277763 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.221855339 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1127435306 ps |
CPU time | 4.32 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:42:00 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-a593ffa8-b54e-479b-ab3c-6d631264c0d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221855339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.221855339 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.3437478699 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 2765471870 ps |
CPU time | 4.89 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:42:00 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-43024efb-5b72-41a2-b950-80298356555a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437478699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3437478699 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2256715642 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 2792804928 ps |
CPU time | 23.04 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:42:19 PM PDT 24 |
Peak memory | 220880 kb |
Host | smart-1fdaa538-de53-4ccc-a044-63cbd4144e12 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256715642 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2256715642 |
Directory | /workspace/0.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.2073818449 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 166333430 ps |
CPU time | 0.87 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:07 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-0b762b33-6a92-4c91-a4ca-62eade997145 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073818449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2073818449 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.2688781550 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 197207304 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:02 PM PDT 24 |
Finished | Aug 16 04:42:02 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-17420b12-53b9-4eec-b6bf-1e9e18e44b11 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688781550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2688781550 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3010876613 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 834173182 ps |
CPU time | 2.01 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:58 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-ef2dd970-712c-4f24-8257-140e2982a7f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010876613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3010876613 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4092425995 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 2977161307 ps |
CPU time | 6.32 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:42:01 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-6e138d48-226a-4fe4-b19f-2f1d4359e281 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092425995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4092425995 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2856680423 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 383119350 ps |
CPU time | 1.22 seconds |
Started | Aug 16 04:41:57 PM PDT 24 |
Finished | Aug 16 04:41:59 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-b90381c2-55d8-4561-8720-b41697ca2746 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856680423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2856680423 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.615997733 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 250817765 ps |
CPU time | 1.03 seconds |
Started | Aug 16 04:41:58 PM PDT 24 |
Finished | Aug 16 04:41:59 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-1ae61d24-f9f1-4edc-90f2-6f48964676c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615997733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.615997733 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1153810515 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 401119688 ps |
CPU time | 0.97 seconds |
Started | Aug 16 04:41:57 PM PDT 24 |
Finished | Aug 16 04:41:58 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-8a13069c-4c79-4c23-b023-6349f7f1b4b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153810515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1153810515 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1578420642 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 532103481 ps |
CPU time | 2.22 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:58 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-d384b180-e2f7-425e-9406-5b16c7d5d9f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578420642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1578420642 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.591797259 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 430984069 ps |
CPU time | 1.82 seconds |
Started | Aug 16 04:42:09 PM PDT 24 |
Finished | Aug 16 04:42:11 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-a4b51248-9be4-4dd8-8078-b5f997cc2935 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591797259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.591797259 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.945177044 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 63098967 ps |
CPU time | 0.97 seconds |
Started | Aug 16 04:42:07 PM PDT 24 |
Finished | Aug 16 04:42:08 PM PDT 24 |
Peak memory | 214976 kb |
Host | smart-f0f65c98-5e51-4eec-a3f7-74c0fb0ff819 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945177044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.945177044 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3035909641 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 657013087 ps |
CPU time | 1.6 seconds |
Started | Aug 16 04:41:54 PM PDT 24 |
Finished | Aug 16 04:41:56 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-67cb8cec-6a7e-49a3-8417-fd2a1bc30932 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3035909641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.3035909641 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.4030837226 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 103043588 ps |
CPU time | 0.9 seconds |
Started | Aug 16 04:42:07 PM PDT 24 |
Finished | Aug 16 04:42:08 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-05a3886a-1f9c-48ff-95c0-f966cd0303d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030837226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.4030837226 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.126196888 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 415448233 ps |
CPU time | 1.54 seconds |
Started | Aug 16 04:42:06 PM PDT 24 |
Finished | Aug 16 04:42:07 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-2234f79a-3ccb-4772-b265-9a378c28feb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126196888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.126196888 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.1803146346 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 80087926 ps |
CPU time | 0.78 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-5a6ee3ff-e32c-4386-8396-c271b60ac54e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803146346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1803146346 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3833762801 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 177306015 ps |
CPU time | 0.85 seconds |
Started | Aug 16 04:42:03 PM PDT 24 |
Finished | Aug 16 04:42:04 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-52bbf357-507b-4772-b03f-e737953b09b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833762801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3833762801 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3806242664 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 381016790 ps |
CPU time | 1.17 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:14 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-08890e33-3005-4910-9adc-a4fdcc40b19a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806242664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3806242664 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1473875270 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 304835748 ps |
CPU time | 1.49 seconds |
Started | Aug 16 04:42:00 PM PDT 24 |
Finished | Aug 16 04:42:02 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-ddfbe5ec-33de-4904-b952-abee7ba05326 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473875270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1473875270 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1120076312 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 373206374 ps |
CPU time | 1.71 seconds |
Started | Aug 16 04:42:02 PM PDT 24 |
Finished | Aug 16 04:42:04 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-1fad6601-d91a-4c1d-87b5-3c57843657c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120076312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1120076312 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.980359661 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 454729861 ps |
CPU time | 1.18 seconds |
Started | Aug 16 04:41:56 PM PDT 24 |
Finished | Aug 16 04:41:58 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-1314c8f6-5508-44dc-b3a4-6ed18eaf4da8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980359661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.980359661 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3404484497 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 219023247 ps |
CPU time | 1.32 seconds |
Started | Aug 16 04:41:58 PM PDT 24 |
Finished | Aug 16 04:42:00 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-f2ce3b7a-f0f4-4f50-a989-ed54647b9040 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404484497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3404484497 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.3176936578 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 796981522 ps |
CPU time | 1.46 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:14 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-a1bd9338-deb1-4b2d-8978-e64ad87f3509 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176936578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3176936578 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4247697565 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1108105916 ps |
CPU time | 3.38 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-23b910c8-aefb-4106-ad22-417e54c562cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247697565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4247697565 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.2040711503 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 135244450 ps |
CPU time | 0.93 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:06 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-8069db6d-3323-4c2b-b862-8775e50fb223 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040711503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2040711503 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3896200760 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 957338585 ps |
CPU time | 2.06 seconds |
Started | Aug 16 04:42:04 PM PDT 24 |
Finished | Aug 16 04:42:06 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-90246098-462e-420f-a0ff-37e25b366fc9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896200760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3896200760 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.3603394185 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 928184094 ps |
CPU time | 2.24 seconds |
Started | Aug 16 04:41:55 PM PDT 24 |
Finished | Aug 16 04:41:57 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-19b6240b-70ab-4eb4-b508-61b22ac68d52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603394185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3603394185 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.2899536654 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 640138531 ps |
CPU time | 2.57 seconds |
Started | Aug 16 04:42:11 PM PDT 24 |
Finished | Aug 16 04:42:14 PM PDT 24 |
Peak memory | 229584 kb |
Host | smart-a29d4e9b-7ad1-4fab-beba-b01cd66e4d1d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899536654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2899536654 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2824139246 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 2858092474 ps |
CPU time | 4.66 seconds |
Started | Aug 16 04:41:57 PM PDT 24 |
Finished | Aug 16 04:42:01 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-398e96d9-b960-499d-9b46-c1a5f6ac2033 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824139246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2824139246 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1768356994 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 148089822 ps |
CPU time | 1.16 seconds |
Started | Aug 16 04:42:07 PM PDT 24 |
Finished | Aug 16 04:42:08 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-f363b989-232d-48ac-b936-dea0fea51f36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768356994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1768356994 |
Directory | /workspace/1.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.738138681 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2107657240 ps |
CPU time | 6.44 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:12 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-f80c4c85-1f95-46b3-abe7-9050b8d89602 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738138681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.738138681 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.2901068573 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 119628996 ps |
CPU time | 0.78 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-431810a3-d7b2-48f6-ac5f-51e752b13de2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901068573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2901068573 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1165058774 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 93384993966 ps |
CPU time | 266.18 seconds |
Started | Aug 16 04:42:20 PM PDT 24 |
Finished | Aug 16 04:46:46 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-6d2d70fc-74fd-45fb-8950-3989b8f200c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165058774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1165058774 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2377845877 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2339970854 ps |
CPU time | 8.28 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-3a3b019c-e2be-41ce-b5c4-a04c4bff912f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377845877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2377845877 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3448502577 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 5292185965 ps |
CPU time | 2.74 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-476fdfdc-ea63-4aeb-a580-50dc81b33d6c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3448502577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.3448502577 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3427323852 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2374412764 ps |
CPU time | 8.02 seconds |
Started | Aug 16 04:42:18 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-3a56644b-bc56-48bb-9666-76db44931625 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427323852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3427323852 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.4239977150 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 4291528434 ps |
CPU time | 2.96 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-8f40c301-ed9b-4976-acd1-7e6ca13af233 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239977150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4239977150 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.2939986730 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 70907548 ps |
CPU time | 0.86 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:16 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-a9ed9421-1a4d-490a-83c8-192e005e7852 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939986730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2939986730 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.198590201 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 73642053994 ps |
CPU time | 182.94 seconds |
Started | Aug 16 04:42:20 PM PDT 24 |
Finished | Aug 16 04:45:23 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-c0022cbe-abcf-4fd5-b57c-e22af40fbdb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198590201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.198590201 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3139955711 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 5244871956 ps |
CPU time | 15.11 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:31 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-1eaa9901-c47b-409d-86a7-8ddee15ac36f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3139955711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3139955711 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.3884598040 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1705322684 ps |
CPU time | 5.69 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:22 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-6f8b3bb5-673e-4253-acbc-c6def2b35872 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884598040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3884598040 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.1443111348 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 2328514146 ps |
CPU time | 2.54 seconds |
Started | Aug 16 04:42:19 PM PDT 24 |
Finished | Aug 16 04:42:22 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-76d947dc-9181-49ea-ac96-e9a10b25b7b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443111348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1443111348 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1685952378 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 58029200 ps |
CPU time | 0.79 seconds |
Started | Aug 16 04:42:21 PM PDT 24 |
Finished | Aug 16 04:42:22 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-5fe3e991-c6ea-45be-a3ce-07d279fefa96 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685952378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1685952378 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2698916616 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 3899976770 ps |
CPU time | 10.22 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-538e5b9c-355a-417c-abbb-b7f94d190e87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698916616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2698916616 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.752136250 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 3636973229 ps |
CPU time | 7.05 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:22 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-98ec273c-b6d8-4259-a95f-6cb5e9d2b00e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752136250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.752136250 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2091314553 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 2557118172 ps |
CPU time | 7.57 seconds |
Started | Aug 16 04:42:18 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-bad3ba82-4960-4c59-8e78-30f9c7105342 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2091314553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.2091314553 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.810183573 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 1174089223 ps |
CPU time | 4.43 seconds |
Started | Aug 16 04:42:17 PM PDT 24 |
Finished | Aug 16 04:42:21 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-9f592427-ac9c-493b-8ab3-3bc2566057b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810183573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.810183573 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.678504729 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 44759063 ps |
CPU time | 0.77 seconds |
Started | Aug 16 04:42:20 PM PDT 24 |
Finished | Aug 16 04:42:20 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-0f3e1993-996e-4241-932e-84d110f065ce |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678504729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.678504729 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.159417814 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 3925105598 ps |
CPU time | 4.64 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:21 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-4746d67d-eb88-4e40-95f3-1d6d34695c5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159417814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.159417814 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1800706026 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 10070739373 ps |
CPU time | 26.77 seconds |
Started | Aug 16 04:42:19 PM PDT 24 |
Finished | Aug 16 04:42:46 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-1111955d-51bf-4bc0-94b6-ea05e4d35398 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800706026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1800706026 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1325056212 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 9004148525 ps |
CPU time | 29.16 seconds |
Started | Aug 16 04:42:20 PM PDT 24 |
Finished | Aug 16 04:42:49 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-dd90bb14-a46b-4acb-9c51-1e853f45fe18 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1325056212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.1325056212 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.4144524052 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 2991556142 ps |
CPU time | 8.69 seconds |
Started | Aug 16 04:42:20 PM PDT 24 |
Finished | Aug 16 04:42:29 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-cc44c7cd-b087-4270-b709-fe17f3cdd357 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144524052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4144524052 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.1440945797 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 6535811231 ps |
CPU time | 7.9 seconds |
Started | Aug 16 04:42:18 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-5a582899-5079-49b4-9940-7b17201ccaf6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440945797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1440945797 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1729065082 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 5692377032 ps |
CPU time | 6.54 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-5f43b09c-990f-441a-af9e-fc79e1e67438 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729065082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1729065082 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1783738149 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 5531903120 ps |
CPU time | 12.9 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-60b2ef6a-4048-4c95-944e-55e37a6891ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783738149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1783738149 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3350910306 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 2729966448 ps |
CPU time | 4.84 seconds |
Started | Aug 16 04:42:19 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-0d95532c-4929-4662-ad70-ae431385dd56 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3350910306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.3350910306 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.1386630297 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 2077274019 ps |
CPU time | 4.49 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:28 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-74053813-2eab-4686-ac5b-91d3abae9583 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386630297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1386630297 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.125818965 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 87572014 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-ec2a2905-5f83-48b4-8f1e-22d40f734f4b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125818965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.125818965 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.975975410 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 4779991316 ps |
CPU time | 13.05 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:37 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-1b180d14-1bf4-4fa0-8610-0baa4a1d7d98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975975410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.975975410 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1537307066 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 2088628795 ps |
CPU time | 1.43 seconds |
Started | Aug 16 04:42:27 PM PDT 24 |
Finished | Aug 16 04:42:28 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-699b35f1-74e1-4cb5-bfca-97f0bd962c28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537307066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1537307066 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1397408250 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 1309381040 ps |
CPU time | 2.04 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-c8e4ddc1-7679-4c77-974b-9367c6fa8570 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1397408250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.1397408250 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.1502780341 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 1558513201 ps |
CPU time | 4.39 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-25001502-97a8-434c-b9ba-42b176168658 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502780341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1502780341 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.1014358147 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 7783052161 ps |
CPU time | 10.86 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:35 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-b691c4f2-1a94-4346-99e3-f5725136c0f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014358147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1014358147 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3482621200 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 30490095 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-7c4b9a70-50aa-497f-a8e8-5bf66005bd78 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482621200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3482621200 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2237642928 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 7616495652 ps |
CPU time | 23.26 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:48 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-ec766ec3-e5f6-4382-ba9f-193b0a2dc226 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237642928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2237642928 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1949453273 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 1363932376 ps |
CPU time | 2.52 seconds |
Started | Aug 16 04:42:22 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-6cbf8a74-5955-489f-92e0-34578772de05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949453273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1949453273 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1534526142 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 6696546516 ps |
CPU time | 5.16 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:30 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-b5cb7ecb-824f-4da1-a6ae-97f7e376447c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1534526142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.1534526142 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1827875688 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 6578696398 ps |
CPU time | 10.04 seconds |
Started | Aug 16 04:42:26 PM PDT 24 |
Finished | Aug 16 04:42:36 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-31217cb8-48e0-402d-a0f7-36094cbbefec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827875688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1827875688 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.1699997676 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 5396208490 ps |
CPU time | 9.25 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:33 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-5c706b0e-4139-407f-833a-fdf92116e369 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699997676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1699997676 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3147209300 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 50311382 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:24 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-3ffc773e-89ae-4d79-9c67-6cfe9be2f96a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147209300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3147209300 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.195808433 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 31524848815 ps |
CPU time | 47.98 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:43:11 PM PDT 24 |
Peak memory | 215952 kb |
Host | smart-b9691b76-99f0-483e-a38f-f11d6846b071 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195808433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.195808433 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1592488979 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 12954465008 ps |
CPU time | 37.17 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:43:02 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-3705ecda-32d9-4ef8-8c9b-3fde2ef3a786 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592488979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1592488979 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1945291769 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2068624971 ps |
CPU time | 2.92 seconds |
Started | Aug 16 04:42:28 PM PDT 24 |
Finished | Aug 16 04:42:31 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-d2682d51-473c-44bb-9af7-59996870b928 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1945291769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.1945291769 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.115907564 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 1645514911 ps |
CPU time | 5.73 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:31 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-446ee4a6-2a7f-4cc2-ab13-241c31537cde |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115907564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.115907564 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.2684282040 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 4701448040 ps |
CPU time | 4.31 seconds |
Started | Aug 16 04:42:21 PM PDT 24 |
Finished | Aug 16 04:42:25 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-767650d0-a1ef-4fef-9611-6c20e0e63360 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684282040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2684282040 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3007807974 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 96808809 ps |
CPU time | 0.92 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-7f00fb67-7860-478c-9d66-81a9e967a3a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007807974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3007807974 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2114501444 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 3158805876 ps |
CPU time | 9.26 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:35 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-a45412e4-4b04-475d-a02a-d0594dea1410 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114501444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2114501444 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3360461897 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 3811001021 ps |
CPU time | 4.75 seconds |
Started | Aug 16 04:42:26 PM PDT 24 |
Finished | Aug 16 04:42:31 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-02314b58-214f-4706-bb8e-1a27fe365ecc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3360461897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3360461897 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.4136762660 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 2248760799 ps |
CPU time | 4.36 seconds |
Started | Aug 16 04:42:21 PM PDT 24 |
Finished | Aug 16 04:42:25 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-73e14bc3-92eb-4429-87d0-aa3a58fa422d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136762660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.4136762660 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.2921582875 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1323446278 ps |
CPU time | 2.48 seconds |
Started | Aug 16 04:42:27 PM PDT 24 |
Finished | Aug 16 04:42:29 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-e2ae7f4c-b29d-47f2-9f6f-2987b0c96f43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921582875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2921582875 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.3981220221 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 53857996 ps |
CPU time | 0.85 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-9a03029b-92cd-4186-8ff6-eb53d537413d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981220221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3981220221 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.4259032195 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 2481900357 ps |
CPU time | 2.38 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-f0f558f3-023e-431a-98d7-8dca4c9b772e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259032195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.4259032195 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3418377482 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 2202105599 ps |
CPU time | 6.84 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-403f1528-29d8-44fd-8042-fe71408c8cc2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3418377482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.3418377482 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.68656268 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2488213183 ps |
CPU time | 3.98 seconds |
Started | Aug 16 04:42:25 PM PDT 24 |
Finished | Aug 16 04:42:29 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-d0253220-6922-41b6-bc41-8fbc21f10ed3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68656268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.68656268 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.4155779959 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 30616718 ps |
CPU time | 0.78 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-661a2098-6ece-4406-bd6a-ba170f10a8bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155779959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4155779959 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3513571258 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 31395275454 ps |
CPU time | 96.38 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:43:50 PM PDT 24 |
Peak memory | 217088 kb |
Host | smart-89556233-bbdd-4042-9915-16906d2209b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513571258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3513571258 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3479793628 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1461005819 ps |
CPU time | 2.82 seconds |
Started | Aug 16 04:42:11 PM PDT 24 |
Finished | Aug 16 04:42:14 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-52503ece-fb88-4d09-9f49-2472f6d6e3f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479793628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3479793628 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_buffered_enable.1254616223 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 168291540 ps |
CPU time | 0.96 seconds |
Started | Aug 16 04:42:00 PM PDT 24 |
Finished | Aug 16 04:42:01 PM PDT 24 |
Peak memory | 234412 kb |
Host | smart-cb7d22a3-3ef7-498b-a320-7e2fa1e04dfc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254616223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.1254616223 |
Directory | /workspace/2.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.674537211 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2399635615 ps |
CPU time | 2.55 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:08 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-fb32ff94-602c-4d12-89e4-b8a29408dcbd |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=674537211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl _access.674537211 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_halt_resume_whereto.564480188 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 1253981148 ps |
CPU time | 1.26 seconds |
Started | Aug 16 04:42:00 PM PDT 24 |
Finished | Aug 16 04:42:02 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-9dc1751a-5d02-41b7-919d-465d6acf0c52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564480188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.564480188 |
Directory | /workspace/2.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.2187975464 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 63030046 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:04 PM PDT 24 |
Finished | Aug 16 04:42:05 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-e8b31f67-cc30-4224-9eb4-2856e3a1b751 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187975464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2187975464 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2136790097 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 988249408 ps |
CPU time | 2.64 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:16 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-e7a9eed2-e926-4068-85e8-17c7d9ba9764 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136790097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2136790097 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2742409618 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1210847046 ps |
CPU time | 3.89 seconds |
Started | Aug 16 04:42:03 PM PDT 24 |
Finished | Aug 16 04:42:07 PM PDT 24 |
Peak memory | 229584 kb |
Host | smart-78e440c6-56d2-4202-bd49-c92bb3377a7b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742409618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2742409618 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.1422354077 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 63582097 ps |
CPU time | 0.83 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:06 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-d7178f5a-1734-44ed-bc7e-1e1974ba3966 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422354077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.1422354077 |
Directory | /workspace/2.rv_dm_sparse_lc_gate_fsm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.3304870660 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 5377781648 ps |
CPU time | 2.22 seconds |
Started | Aug 16 04:42:07 PM PDT 24 |
Finished | Aug 16 04:42:10 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-0a33021c-6b4e-44b9-bb44-4f1b5abf643a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304870660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3304870660 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1239454723 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 2756333918 ps |
CPU time | 37.3 seconds |
Started | Aug 16 04:42:02 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 221164 kb |
Host | smart-88b2d522-1f5b-491f-8a6c-198100dabb6f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239454723 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1239454723 |
Directory | /workspace/2.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.1998764936 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 96186013 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:36 PM PDT 24 |
Finished | Aug 16 04:42:37 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-dc06ef03-5e57-4ab9-9e6f-9e79c0464bdf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998764936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1998764936 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.2688872531 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 3718319559 ps |
CPU time | 6.03 seconds |
Started | Aug 16 04:42:30 PM PDT 24 |
Finished | Aug 16 04:42:36 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-befde586-62a4-4a7d-86f3-f30b883a9147 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688872531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2688872531 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.3613973292 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 68788471 ps |
CPU time | 0.81 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-f6e4a78e-4dbb-4501-be3f-a0cba71b75ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613973292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3613973292 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.2619537005 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 4131070828 ps |
CPU time | 6.05 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-a52558d2-a147-4e13-bf2f-5754b4b51d24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619537005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2619537005 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.3698375929 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 35431217 ps |
CPU time | 0.72 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:33 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-e048e06b-aed5-4b66-8b87-b5c0333a84ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698375929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3698375929 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.1538164211 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2385308692 ps |
CPU time | 1.69 seconds |
Started | Aug 16 04:42:30 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-88340629-2d42-4542-8ca6-9b65fd9b8368 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538164211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1538164211 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.673337283 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 40821674 ps |
CPU time | 0.73 seconds |
Started | Aug 16 04:42:34 PM PDT 24 |
Finished | Aug 16 04:42:35 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-44693ccf-d391-4273-a3bf-c8a967900ed8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673337283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.673337283 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.772768016 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 2279801056 ps |
CPU time | 3.13 seconds |
Started | Aug 16 04:42:35 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-613c67c9-b54b-4f76-a9bc-4571bdd8d09c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772768016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.772768016 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.2116202518 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 159629766 ps |
CPU time | 0.8 seconds |
Started | Aug 16 04:42:29 PM PDT 24 |
Finished | Aug 16 04:42:30 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-0222d5d4-b5b9-4b85-afc8-8915be2b1dd6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116202518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2116202518 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.2506587796 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 4514964412 ps |
CPU time | 8.52 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:42 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-416cb5fc-f932-49ef-b516-60f5447ad9cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506587796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2506587796 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.887502577 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 157520772 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:31 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-9dde4fbe-5124-4636-b2a9-653334fe64af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887502577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.887502577 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.576837146 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1175070167 ps |
CPU time | 3.28 seconds |
Started | Aug 16 04:42:31 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-afb08865-a63a-46de-b219-e9f2ba834c4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576837146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.576837146 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.773397836 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 88222459 ps |
CPU time | 0.77 seconds |
Started | Aug 16 04:42:35 PM PDT 24 |
Finished | Aug 16 04:42:36 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-e5c1ff5c-ba79-4e7b-a62e-7e8bf9e63a6e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773397836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.773397836 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.3146878300 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 2122834795 ps |
CPU time | 4.32 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:42 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-9a3ed94f-de14-4793-9da8-6ace01f4769c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146878300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3146878300 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.524371109 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 65676812 ps |
CPU time | 0.84 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-8c90b560-f2e8-4046-9251-7829af063456 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524371109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.524371109 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.254533883 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 2361771527 ps |
CPU time | 2.48 seconds |
Started | Aug 16 04:42:34 PM PDT 24 |
Finished | Aug 16 04:42:36 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-02b4804d-1e6b-4b83-8177-9c03a5aa8133 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254533883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.254533883 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.3541967380 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 79618836 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:31 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-7804ee3c-9227-4f06-9e6e-7a4320728000 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541967380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3541967380 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.2990766621 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 4836970281 ps |
CPU time | 3.41 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:36 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-52e62c94-39e0-4c09-8927-442d085d2d78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990766621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2990766621 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.1514463464 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 177859465 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:34 PM PDT 24 |
Finished | Aug 16 04:42:35 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-a1619a45-8293-4ee9-ac69-be63f438089c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514463464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1514463464 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.2968281415 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 85004953 ps |
CPU time | 0.88 seconds |
Started | Aug 16 04:42:12 PM PDT 24 |
Finished | Aug 16 04:42:13 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-a6027fcd-c647-46f9-98c0-f6242cc03665 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968281415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2968281415 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1325739661 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 3570204681 ps |
CPU time | 3.45 seconds |
Started | Aug 16 04:42:00 PM PDT 24 |
Finished | Aug 16 04:42:04 PM PDT 24 |
Peak memory | 214708 kb |
Host | smart-2a22d2ed-670e-4b7d-8f4c-a95e9da3c7d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325739661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1325739661 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2385319781 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 7475518344 ps |
CPU time | 11.56 seconds |
Started | Aug 16 04:42:01 PM PDT 24 |
Finished | Aug 16 04:42:12 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-448be92e-06bb-4d6c-919d-af0c199a31d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385319781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2385319781 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_buffered_enable.1764495756 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 698094991 ps |
CPU time | 1.61 seconds |
Started | Aug 16 04:42:09 PM PDT 24 |
Finished | Aug 16 04:42:10 PM PDT 24 |
Peak memory | 226120 kb |
Host | smart-cf3c1b18-cc9c-4a3d-bd10-e77bec2d9517 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764495756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.1764495756 |
Directory | /workspace/3.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4038120442 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 5732095804 ps |
CPU time | 5.35 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:18 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-0e704664-7279-4dfc-a810-6f650998edfa |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4038120442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.4038120442 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_halt_resume_whereto.327193783 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 541438229 ps |
CPU time | 0.93 seconds |
Started | Aug 16 04:42:11 PM PDT 24 |
Finished | Aug 16 04:42:12 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-9ef5e16e-c0ac-4a55-89d6-56e93640c00e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327193783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.327193783 |
Directory | /workspace/3.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.2779706568 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 139287501 ps |
CPU time | 0.77 seconds |
Started | Aug 16 04:42:09 PM PDT 24 |
Finished | Aug 16 04:42:10 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-eef15dbd-0497-4f51-8790-ac4b01e7a64f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779706568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2779706568 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.2294763556 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 6261684846 ps |
CPU time | 10.17 seconds |
Started | Aug 16 04:42:03 PM PDT 24 |
Finished | Aug 16 04:42:14 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-f25477cb-2100-4403-b267-066eb9d70619 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294763556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2294763556 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.1755931654 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 233398149 ps |
CPU time | 1.52 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:18 PM PDT 24 |
Peak memory | 229524 kb |
Host | smart-08f022e1-d968-40c6-8e33-d088a01904ab |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755931654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1755931654 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3718389897 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 6395063302 ps |
CPU time | 11.52 seconds |
Started | Aug 16 04:42:07 PM PDT 24 |
Finished | Aug 16 04:42:19 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-f13ddd79-d06a-4c83-b4b9-4803dcb0836c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718389897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3718389897 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.2182424715 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 50458708 ps |
CPU time | 0.68 seconds |
Started | Aug 16 04:42:29 PM PDT 24 |
Finished | Aug 16 04:42:30 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-31b10965-2df5-4a72-b4a7-2fd24d9e4932 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182424715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2182424715 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.2889522167 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1372028392 ps |
CPU time | 4.14 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:37 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-259a273d-9e16-43c8-b1e6-21e28f902ad7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889522167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2889522167 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.3230181254 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 95880041 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-2bb310a0-bb98-4a8c-88b7-76f6ec24d725 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230181254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3230181254 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1144602355 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 16996034993 ps |
CPU time | 25.24 seconds |
Started | Aug 16 04:42:28 PM PDT 24 |
Finished | Aug 16 04:42:53 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-14e5dfa4-ba90-4071-a12e-4e6bc619f50c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144602355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1144602355 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.442449560 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 111344127 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:36 PM PDT 24 |
Finished | Aug 16 04:42:37 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-f1edb68e-1dd8-4698-a71e-6a78eb5e7f0a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442449560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.442449560 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1733974131 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 37651915 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:31 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-a4286ac1-0671-4c21-bf23-1c42f56b5569 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733974131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1733974131 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.3926428221 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1189774992 ps |
CPU time | 2.81 seconds |
Started | Aug 16 04:42:36 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-d533d8dc-6b70-4935-a1fe-d82ca1b84b14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926428221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3926428221 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.3900596494 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 41861096 ps |
CPU time | 0.72 seconds |
Started | Aug 16 04:42:34 PM PDT 24 |
Finished | Aug 16 04:42:35 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-41a2682d-c315-4750-85a9-eb7438e29af9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900596494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3900596494 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.2194545900 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 2107106815 ps |
CPU time | 3.74 seconds |
Started | Aug 16 04:42:30 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-290ef0eb-c103-444e-96b0-06d0a1523240 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194545900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2194545900 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.2545850670 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 39459873 ps |
CPU time | 0.78 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:33 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-47d5a111-5edd-417d-b070-26615d7bf582 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545850670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2545850670 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.2821548324 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 4122911733 ps |
CPU time | 6.68 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-c35b8a99-a9d2-4b32-a25c-16426fe382af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821548324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2821548324 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.456459794 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 76763673 ps |
CPU time | 0.73 seconds |
Started | Aug 16 04:42:31 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-93508576-9224-463a-9722-70e70713529e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456459794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.456459794 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.478402469 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3954749148 ps |
CPU time | 6.34 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:40 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-c5065f0b-a020-4ebf-a6c9-0ed4794a9195 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478402469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.478402469 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2832617371 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 47610512 ps |
CPU time | 0.8 seconds |
Started | Aug 16 04:42:35 PM PDT 24 |
Finished | Aug 16 04:42:36 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-b13e1932-5add-4b78-a9a2-78ac5bca9cc9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832617371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2832617371 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.268438000 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2611086458 ps |
CPU time | 8.62 seconds |
Started | Aug 16 04:42:35 PM PDT 24 |
Finished | Aug 16 04:42:44 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-ceaf64d0-4b77-4cc7-ab71-067ccefe0c4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268438000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.268438000 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.3101916026 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 97400840 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-ab22fc5f-3965-4b63-bf9f-2fa714fcd0e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101916026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3101916026 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.1365941833 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 10428371743 ps |
CPU time | 7 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:40 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-020ea86a-09a0-4091-999f-bf6e47e12f03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365941833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1365941833 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.296098388 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 67884585 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:31 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-10e4922d-1f8f-4086-80ff-32d8e4b04d67 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296098388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.296098388 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.748117155 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 6385437660 ps |
CPU time | 5.39 seconds |
Started | Aug 16 04:42:32 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-920b7a71-3c40-49c8-9b72-f2d08df24ac0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748117155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.748117155 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.1724917767 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 115644666 ps |
CPU time | 0.8 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-1c51459e-0f4e-435e-9c3a-bc3074b8902b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724917767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1724917767 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1347747424 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2625496925 ps |
CPU time | 2.74 seconds |
Started | Aug 16 04:42:07 PM PDT 24 |
Finished | Aug 16 04:42:10 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-2bd3387c-98be-4be8-b4a4-d21e2c4e1285 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347747424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1347747424 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4027012068 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 14691312956 ps |
CPU time | 13.86 seconds |
Started | Aug 16 04:42:04 PM PDT 24 |
Finished | Aug 16 04:42:18 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-ed2605f6-4073-4dd2-bece-bc383c883ffe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027012068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4027012068 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_buffered_enable.3714490121 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 197681352 ps |
CPU time | 0.96 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 225948 kb |
Host | smart-cbc720f6-9795-4376-8fbc-0059b0afb148 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714490121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.3714490121 |
Directory | /workspace/4.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3420333607 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 3267547712 ps |
CPU time | 3.54 seconds |
Started | Aug 16 04:42:05 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-f3377545-c538-4e5c-80ca-90d8c4cbfc14 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3420333607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3420333607 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_halt_resume_whereto.4067681772 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 704041681 ps |
CPU time | 2.46 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:11 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-15975ad5-0dca-4f9c-a108-8eeb18c620eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067681772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.4067681772 |
Directory | /workspace/4.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.2279145391 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 102046220 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:42:09 PM PDT 24 |
Finished | Aug 16 04:42:10 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-100c7f34-6032-4a5a-bd55-082cf96a399c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279145391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2279145391 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.833381366 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 4923437326 ps |
CPU time | 1.72 seconds |
Started | Aug 16 04:42:03 PM PDT 24 |
Finished | Aug 16 04:42:05 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-69fdb4b0-f2b8-476c-a294-cab43d17fd50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833381366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.833381366 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.1101034435 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 811336404 ps |
CPU time | 1.51 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:26 PM PDT 24 |
Peak memory | 228516 kb |
Host | smart-0c92fd55-230b-4967-9479-c8e33e8f0072 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101034435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1101034435 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.508161247 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 2079142890 ps |
CPU time | 2.72 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:11 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-1a3add46-a862-4f30-8571-49729169362f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508161247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.508161247 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2666284849 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 3733734392 ps |
CPU time | 34.06 seconds |
Started | Aug 16 04:42:12 PM PDT 24 |
Finished | Aug 16 04:42:46 PM PDT 24 |
Peak memory | 217964 kb |
Host | smart-a7fa8caa-1ee9-4dd0-927a-99236464af64 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666284849 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2666284849 |
Directory | /workspace/4.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.3103415179 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 106900843 ps |
CPU time | 0.92 seconds |
Started | Aug 16 04:42:33 PM PDT 24 |
Finished | Aug 16 04:42:34 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-b831277d-8069-4ba7-b183-bbc151a33973 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103415179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3103415179 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.2555457145 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 103553691 ps |
CPU time | 0.86 seconds |
Started | Aug 16 04:42:36 PM PDT 24 |
Finished | Aug 16 04:42:37 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-e811dd39-58bf-43fc-a6c2-17a31672cac4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555457145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2555457145 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.2356163229 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 1386617655 ps |
CPU time | 2.94 seconds |
Started | Aug 16 04:42:37 PM PDT 24 |
Finished | Aug 16 04:42:40 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-7a15099d-ab81-4003-84e3-15d71b32885c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356163229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2356163229 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2593421852 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 66991482 ps |
CPU time | 0.86 seconds |
Started | Aug 16 04:42:38 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-25e9ba05-6fcf-414e-ba8a-4e536fe6b772 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593421852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2593421852 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.1553750880 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 4131791449 ps |
CPU time | 6.39 seconds |
Started | Aug 16 04:42:38 PM PDT 24 |
Finished | Aug 16 04:42:44 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-b9b3753d-c1f5-4afc-8d6b-c0365c73da8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553750880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1553750880 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.3743411460 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 61731297 ps |
CPU time | 0.71 seconds |
Started | Aug 16 04:42:37 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-354f46f0-d56d-44a4-860c-9535cff04842 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743411460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3743411460 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.336958927 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 4890853652 ps |
CPU time | 12.69 seconds |
Started | Aug 16 04:42:39 PM PDT 24 |
Finished | Aug 16 04:42:52 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-92ec58f2-3e0d-405f-8b11-085227183636 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336958927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.336958927 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.482992244 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 57113965 ps |
CPU time | 0.68 seconds |
Started | Aug 16 04:42:42 PM PDT 24 |
Finished | Aug 16 04:42:44 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-fc4063fd-14e8-4fda-a31c-c62cc5ec6f1e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482992244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.482992244 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.3670549214 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 3052127860 ps |
CPU time | 2.93 seconds |
Started | Aug 16 04:42:38 PM PDT 24 |
Finished | Aug 16 04:42:41 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-a11b6cea-2215-4c08-9928-fe7f9f1e9bd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670549214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3670549214 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.1079812397 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 43383320 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:42:38 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-6f175eee-9b8b-457f-b9a3-5822e4d635f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079812397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1079812397 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.525574476 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 2198563029 ps |
CPU time | 2.48 seconds |
Started | Aug 16 04:42:39 PM PDT 24 |
Finished | Aug 16 04:42:42 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-d85da478-42b8-4b0c-89c3-12a8b8a59a35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525574476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.525574476 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.1140868582 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 37448921 ps |
CPU time | 0.74 seconds |
Started | Aug 16 04:42:38 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-18b4c30c-585e-49ea-a6ba-372e625d8324 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140868582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1140868582 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.188587970 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 4336121726 ps |
CPU time | 4.01 seconds |
Started | Aug 16 04:42:41 PM PDT 24 |
Finished | Aug 16 04:42:46 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-c020304f-718a-4853-9964-c7d057a489c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188587970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.188587970 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.1531903387 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 112369195 ps |
CPU time | 0.99 seconds |
Started | Aug 16 04:42:39 PM PDT 24 |
Finished | Aug 16 04:42:41 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-cee0371a-6020-40fb-8461-424551793ff8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531903387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1531903387 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.3486580600 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 3560419674 ps |
CPU time | 5.64 seconds |
Started | Aug 16 04:42:41 PM PDT 24 |
Finished | Aug 16 04:42:48 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-c49ed80a-a454-4b24-b750-177372d441dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486580600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3486580600 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.3378851216 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 34791126 ps |
CPU time | 0.79 seconds |
Started | Aug 16 04:42:37 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-0aa1a5ff-812e-49de-b47f-052624c2198f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378851216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3378851216 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.3000860772 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1570708624 ps |
CPU time | 4.58 seconds |
Started | Aug 16 04:42:40 PM PDT 24 |
Finished | Aug 16 04:42:45 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-2c0a3f60-e784-4af7-84c7-c363ea3a2ce0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000860772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3000860772 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.3896996085 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 55194162 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:38 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-590c371b-fd46-44c2-b7b8-26f8548b2397 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896996085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3896996085 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.2003339926 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 2466533744 ps |
CPU time | 2.08 seconds |
Started | Aug 16 04:42:37 PM PDT 24 |
Finished | Aug 16 04:42:39 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-3cf8dba3-d666-43e0-aa3e-bf2ff0289aa0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003339926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2003339926 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.3277286600 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 147492698 ps |
CPU time | 0.88 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:09 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-ea315c14-f38e-4268-ae2c-e2ce45b81f7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277286600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3277286600 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1196870438 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 9014262738 ps |
CPU time | 8.38 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:23 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-9ac87162-9612-466b-bdd8-3e9d99cb1bfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196870438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1196870438 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.938443796 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2024256271 ps |
CPU time | 1.52 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:16 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-69fd3f00-c9c4-43f9-aea2-11642be97689 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938443796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.938443796 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_buffered_enable.484833457 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 115136235 ps |
CPU time | 1.15 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:16 PM PDT 24 |
Peak memory | 225660 kb |
Host | smart-59df694e-f26e-4984-a972-1dead47db7b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484833457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.484833457 |
Directory | /workspace/5.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.128627911 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 7420599494 ps |
CPU time | 5.58 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:20 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-16efefc6-dcb1-4812-90e2-4603e4cd6c7f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=128627911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl _access.128627911 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_halt_resume_whereto.2816629060 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1544004072 ps |
CPU time | 1.33 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:15 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-079fac57-b04a-433e-af18-cc07d78a1ce0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816629060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2816629060 |
Directory | /workspace/5.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.2770802617 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 5947255181 ps |
CPU time | 4.44 seconds |
Started | Aug 16 04:42:12 PM PDT 24 |
Finished | Aug 16 04:42:17 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-79eed791-2f43-4c3c-87c6-6f4fe70f5a07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770802617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2770802617 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.3235322009 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1944482835 ps |
CPU time | 6.65 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:19 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-5b43f65b-2bdd-43d9-94aa-1e70d609f824 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235322009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3235322009 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.736742092 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 2972748860 ps |
CPU time | 50.68 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:43:15 PM PDT 24 |
Peak memory | 217648 kb |
Host | smart-edaad7f2-d092-4e51-a9ee-25a82fb5d9fd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736742092 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.736742092 |
Directory | /workspace/5.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3797886904 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 96858157 ps |
CPU time | 0.76 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:15 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-96ff3e01-3028-4fd2-8cb1-0a2ddefb6417 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797886904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3797886904 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.649480244 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 2353631211 ps |
CPU time | 7.53 seconds |
Started | Aug 16 04:42:24 PM PDT 24 |
Finished | Aug 16 04:42:32 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-b41fea7d-ecb5-41ac-be11-43b1f89ccf5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649480244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.649480244 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2192542293 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 1076397133 ps |
CPU time | 2.02 seconds |
Started | Aug 16 04:42:10 PM PDT 24 |
Finished | Aug 16 04:42:12 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-d58733be-401f-4373-ad0b-c68bc92fa9d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192542293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2192542293 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_buffered_enable.3470858996 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 148199754 ps |
CPU time | 1.25 seconds |
Started | Aug 16 04:42:11 PM PDT 24 |
Finished | Aug 16 04:42:13 PM PDT 24 |
Peak memory | 234296 kb |
Host | smart-62460c8a-a033-4549-82db-95bf9ba6081f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470858996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.3470858996 |
Directory | /workspace/6.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2407822548 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 6783196717 ps |
CPU time | 20.4 seconds |
Started | Aug 16 04:42:08 PM PDT 24 |
Finished | Aug 16 04:42:28 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-c1350470-d742-4f3a-aeaa-841c11d66ecf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2407822548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.2407822548 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_halt_resume_whereto.2011783998 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 619188785 ps |
CPU time | 1.16 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:15 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-6e43e5f5-aab0-46e6-958b-b8b99a859a55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011783998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.2011783998 |
Directory | /workspace/6.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2222314543 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 811955057 ps |
CPU time | 3.03 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:16 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-81d25622-628a-4ca9-939a-60ceafcf2c9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222314543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2222314543 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.1288155805 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 4813543384 ps |
CPU time | 8.22 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:22 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-cca8059b-4c86-4baf-8223-e3ee98e8b954 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288155805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1288155805 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.2250594433 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 44309544 ps |
CPU time | 0.75 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:15 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-0bd3323c-43fe-4a23-ad9a-059508276cc3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250594433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2250594433 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1786020776 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 3167886067 ps |
CPU time | 6.65 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:20 PM PDT 24 |
Peak memory | 205680 kb |
Host | smart-b2b9272c-a404-40db-9d17-ffc6c02b80e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786020776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1786020776 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_buffered_enable.1719985115 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 113690242 ps |
CPU time | 1.2 seconds |
Started | Aug 16 04:42:09 PM PDT 24 |
Finished | Aug 16 04:42:11 PM PDT 24 |
Peak memory | 226756 kb |
Host | smart-dd7b8a68-0134-4775-8278-eb30a5bd3bf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719985115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.1719985115 |
Directory | /workspace/7.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.243725642 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 8133657670 ps |
CPU time | 24.65 seconds |
Started | Aug 16 04:42:13 PM PDT 24 |
Finished | Aug 16 04:42:38 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-2b44b1f6-5a65-4c27-95c1-584319b15516 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=243725642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl _access.243725642 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_halt_resume_whereto.4230789407 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 528699642 ps |
CPU time | 2.21 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:19 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-ee0d2189-dbea-4be6-85a3-8c66216c731c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230789407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.4230789407 |
Directory | /workspace/7.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.505499230 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 4004833376 ps |
CPU time | 4 seconds |
Started | Aug 16 04:42:17 PM PDT 24 |
Finished | Aug 16 04:42:21 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-505856f1-be8a-413f-9422-fa0b2194dbdf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505499230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.505499230 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.592006099 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 3271799593 ps |
CPU time | 3.66 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:20 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-ce21735c-0adc-4313-aa16-064be2b8bf34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592006099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.592006099 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1114292733 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 154041077 ps |
CPU time | 1.12 seconds |
Started | Aug 16 04:42:22 PM PDT 24 |
Finished | Aug 16 04:42:23 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-b693d9d8-c189-4aae-b7f4-858a313420ed |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114292733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1114292733 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2979754998 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 8136448217 ps |
CPU time | 8.55 seconds |
Started | Aug 16 04:42:18 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-92360c2a-2117-4386-8374-4763166501c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979754998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2979754998 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2154992841 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 3054324978 ps |
CPU time | 4.7 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:20 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-f3922b4c-2e13-416f-b2dc-d2c39aee2b06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154992841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2154992841 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_buffered_enable.2270773027 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 318003905 ps |
CPU time | 1.32 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:17 PM PDT 24 |
Peak memory | 234328 kb |
Host | smart-9fab253a-aba6-48e4-a644-6609052ed760 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270773027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.2270773027 |
Directory | /workspace/8.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.4250048270 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 6000819747 ps |
CPU time | 11.87 seconds |
Started | Aug 16 04:42:15 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-d0160d0d-ec63-4343-af9b-b3ccdef1471f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4250048270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.4250048270 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.2460301599 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 3297272978 ps |
CPU time | 4.02 seconds |
Started | Aug 16 04:42:09 PM PDT 24 |
Finished | Aug 16 04:42:13 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-35c78b41-451c-4082-b381-908993a9ac3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460301599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2460301599 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.4040619758 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 3736802141 ps |
CPU time | 2.24 seconds |
Started | Aug 16 04:42:19 PM PDT 24 |
Finished | Aug 16 04:42:21 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-72e973b1-bd27-4663-b563-ec18ecae5f29 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040619758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.4040619758 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.60570094 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 9499190596 ps |
CPU time | 56.53 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:43:13 PM PDT 24 |
Peak memory | 221680 kb |
Host | smart-a38833a3-e26a-4a79-879d-11638c53ef21 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60570094 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.60570094 |
Directory | /workspace/8.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2622132176 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 60455012 ps |
CPU time | 0.84 seconds |
Started | Aug 16 04:42:18 PM PDT 24 |
Finished | Aug 16 04:42:19 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-0b346023-4c94-43e2-92dd-2b2b7e8b4831 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622132176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2622132176 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3603783286 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 45889688645 ps |
CPU time | 21.98 seconds |
Started | Aug 16 04:42:19 PM PDT 24 |
Finished | Aug 16 04:42:41 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-799cda54-7932-4ad7-bc7b-cbafca3e521c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603783286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3603783286 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.842334930 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1478675215 ps |
CPU time | 5.48 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:22 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-2ea37f51-827d-4cd5-8f2b-0f6c04bfb07a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842334930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.842334930 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_buffered_enable.851657484 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 344683083 ps |
CPU time | 1.13 seconds |
Started | Aug 16 04:42:17 PM PDT 24 |
Finished | Aug 16 04:42:18 PM PDT 24 |
Peak memory | 225872 kb |
Host | smart-02fca206-40a2-46fd-bf8e-adc4a46238fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851657484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.851657484 |
Directory | /workspace/9.rv_dm_buffered_enable/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3065751877 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 8006457976 ps |
CPU time | 4.99 seconds |
Started | Aug 16 04:42:16 PM PDT 24 |
Finished | Aug 16 04:42:21 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-da491a79-9626-4e34-8b67-2f51051d6301 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3065751877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.3065751877 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.3229537347 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1156139997 ps |
CPU time | 4 seconds |
Started | Aug 16 04:42:23 PM PDT 24 |
Finished | Aug 16 04:42:27 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-c3283ac1-3f21-48b9-905e-ea0f94eb783b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229537347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3229537347 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.1502976018 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 1805039670 ps |
CPU time | 2.17 seconds |
Started | Aug 16 04:42:14 PM PDT 24 |
Finished | Aug 16 04:42:16 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-6552ba7f-6a92-467c-abe7-09457320b212 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502976018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1502976018 |
Directory | /workspace/9.rv_dm_stress_all/latest |
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