Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.20 96.32 89.82 92.10 96.00 90.44 98.74 54.00


Total test records in report: 481
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T320 /workspace/coverage/default/21.rv_dm_alert_test.2888940188 Aug 19 04:35:23 PM PDT 24 Aug 19 04:35:24 PM PDT 24 166890636 ps
T321 /workspace/coverage/default/45.rv_dm_stress_all.981155354 Aug 19 04:35:38 PM PDT 24 Aug 19 04:35:44 PM PDT 24 7033134156 ps
T322 /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.987014749 Aug 19 04:35:00 PM PDT 24 Aug 19 04:35:19 PM PDT 24 6380567212 ps
T323 /workspace/coverage/default/37.rv_dm_stress_all.2945014248 Aug 19 04:35:43 PM PDT 24 Aug 19 04:35:45 PM PDT 24 4008149339 ps
T324 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2896256357 Aug 19 04:34:56 PM PDT 24 Aug 19 04:34:57 PM PDT 24 206793539 ps
T325 /workspace/coverage/default/19.rv_dm_stress_all.1501449892 Aug 19 04:35:21 PM PDT 24 Aug 19 04:35:27 PM PDT 24 2651828227 ps
T326 /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.978745362 Aug 19 04:34:57 PM PDT 24 Aug 19 04:34:58 PM PDT 24 315709362 ps
T327 /workspace/coverage/default/44.rv_dm_alert_test.3621617595 Aug 19 04:35:26 PM PDT 24 Aug 19 04:35:27 PM PDT 24 32707993 ps
T328 /workspace/coverage/default/20.rv_dm_alert_test.2183035470 Aug 19 04:35:22 PM PDT 24 Aug 19 04:35:22 PM PDT 24 53773253 ps
T329 /workspace/coverage/default/2.rv_dm_alert_test.2330538392 Aug 19 04:35:15 PM PDT 24 Aug 19 04:35:16 PM PDT 24 52875882 ps
T330 /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2156427416 Aug 19 04:34:56 PM PDT 24 Aug 19 04:34:57 PM PDT 24 120272830 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.342439422 Aug 19 04:29:47 PM PDT 24 Aug 19 04:29:48 PM PDT 24 645551807 ps
T115 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2121179540 Aug 19 04:29:38 PM PDT 24 Aug 19 04:30:40 PM PDT 24 20098601385 ps
T116 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2400122807 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:55 PM PDT 24 137947066 ps
T112 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2131880478 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:02 PM PDT 24 818065732 ps
T113 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1975093740 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:07 PM PDT 24 422087351 ps
T117 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1405562482 Aug 19 04:29:47 PM PDT 24 Aug 19 04:29:49 PM PDT 24 52232664 ps
T118 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.225552134 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:32 PM PDT 24 2311702965 ps
T128 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3407717160 Aug 19 04:29:52 PM PDT 24 Aug 19 04:30:04 PM PDT 24 10011646812 ps
T119 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1747665413 Aug 19 04:29:40 PM PDT 24 Aug 19 04:29:42 PM PDT 24 80598713 ps
T331 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4151371872 Aug 19 04:29:53 PM PDT 24 Aug 19 04:31:33 PM PDT 24 38893229739 ps
T163 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3210817071 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:57 PM PDT 24 211494660 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3227032644 Aug 19 04:29:51 PM PDT 24 Aug 19 04:30:00 PM PDT 24 3145061960 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.672918694 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:54 PM PDT 24 104644270 ps
T334 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1323682017 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:28 PM PDT 24 14929786903 ps
T335 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.764829268 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:05 PM PDT 24 7246439697 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.461467985 Aug 19 04:29:59 PM PDT 24 Aug 19 04:29:59 PM PDT 24 80144292 ps
T114 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1993650750 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:24 PM PDT 24 4217102109 ps
T107 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.610239805 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:11 PM PDT 24 171452281 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1403744970 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:01 PM PDT 24 1839722512 ps
T125 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.516655815 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:07 PM PDT 24 384838203 ps
T120 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2431946995 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:02 PM PDT 24 79845452 ps
T108 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1540109517 Aug 19 04:30:16 PM PDT 24 Aug 19 04:30:18 PM PDT 24 693917813 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1267496982 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:57 PM PDT 24 233839999 ps
T98 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.107036412 Aug 19 04:29:45 PM PDT 24 Aug 19 04:30:36 PM PDT 24 3679386422 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.484660064 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:09 PM PDT 24 125348355 ps
T340 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1018835201 Aug 19 04:30:21 PM PDT 24 Aug 19 04:30:48 PM PDT 24 9596638817 ps
T341 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3676792516 Aug 19 04:29:52 PM PDT 24 Aug 19 04:29:53 PM PDT 24 88134460 ps
T121 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3647195444 Aug 19 04:30:02 PM PDT 24 Aug 19 04:30:06 PM PDT 24 303685174 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4162217574 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:56 PM PDT 24 50224435 ps
T122 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2393628500 Aug 19 04:29:47 PM PDT 24 Aug 19 04:29:51 PM PDT 24 974684713 ps
T123 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1536699860 Aug 19 04:30:10 PM PDT 24 Aug 19 04:30:18 PM PDT 24 1978529666 ps
T124 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2361739322 Aug 19 04:29:50 PM PDT 24 Aug 19 04:30:28 PM PDT 24 3949588728 ps
T164 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1290310568 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:00 PM PDT 24 430335263 ps
T156 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.168414277 Aug 19 04:30:01 PM PDT 24 Aug 19 04:30:06 PM PDT 24 955165828 ps
T140 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2264633307 Aug 19 04:29:48 PM PDT 24 Aug 19 04:29:51 PM PDT 24 648753722 ps
T172 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1615185033 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:13 PM PDT 24 468517827 ps
T173 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2416994181 Aug 19 04:29:40 PM PDT 24 Aug 19 04:29:48 PM PDT 24 713965615 ps
T343 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1160438624 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:00 PM PDT 24 235261442 ps
T344 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.598020186 Aug 19 04:30:17 PM PDT 24 Aug 19 04:30:19 PM PDT 24 45210056 ps
T174 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2089684356 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:09 PM PDT 24 2473101592 ps
T157 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.624706698 Aug 19 04:30:02 PM PDT 24 Aug 19 04:30:08 PM PDT 24 735073618 ps
T61 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.84830739 Aug 19 04:30:09 PM PDT 24 Aug 19 04:31:13 PM PDT 24 35603106613 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.481664787 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:03 PM PDT 24 5222350117 ps
T141 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3440803779 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:58 PM PDT 24 87202469 ps
T346 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3243939570 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:20 PM PDT 24 7533333650 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3600008704 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:11 PM PDT 24 228748549 ps
T142 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1178126956 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:10 PM PDT 24 204026873 ps
T348 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.287824282 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:48 PM PDT 24 29914413325 ps
T349 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3820515756 Aug 19 04:30:02 PM PDT 24 Aug 19 04:30:11 PM PDT 24 7623317777 ps
T350 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1249247181 Aug 19 04:30:10 PM PDT 24 Aug 19 04:30:11 PM PDT 24 326715250 ps
T351 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.698045427 Aug 19 04:29:58 PM PDT 24 Aug 19 04:30:00 PM PDT 24 455399768 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.579345747 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:31 PM PDT 24 171441951 ps
T199 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2918802794 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:23 PM PDT 24 1044408612 ps
T99 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2531164111 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:39 PM PDT 24 3567851541 ps
T143 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3216644263 Aug 19 04:30:01 PM PDT 24 Aug 19 04:30:10 PM PDT 24 7807205836 ps
T353 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.753566048 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:04 PM PDT 24 170691484 ps
T354 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.250262527 Aug 19 04:30:12 PM PDT 24 Aug 19 04:30:20 PM PDT 24 15786172685 ps
T355 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.114199653 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:55 PM PDT 24 121634893 ps
T356 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4172535030 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:54 PM PDT 24 150677120 ps
T152 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2971401472 Aug 19 04:29:45 PM PDT 24 Aug 19 04:29:47 PM PDT 24 52548248 ps
T357 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2478995121 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:06 PM PDT 24 521171328 ps
T358 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.164371222 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:45 PM PDT 24 160841434 ps
T359 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.133359 Aug 19 04:29:50 PM PDT 24 Aug 19 04:30:00 PM PDT 24 2850812699 ps
T360 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.819222537 Aug 19 04:29:58 PM PDT 24 Aug 19 04:29:59 PM PDT 24 82570685 ps
T201 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1611829215 Aug 19 04:30:18 PM PDT 24 Aug 19 04:30:39 PM PDT 24 4644012653 ps
T361 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1659908750 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:11 PM PDT 24 60075227 ps
T362 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3422019092 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:54 PM PDT 24 69138558 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1034575202 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:56 PM PDT 24 4195307324 ps
T154 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3189554479 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:57 PM PDT 24 629646533 ps
T364 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2626846727 Aug 19 04:29:51 PM PDT 24 Aug 19 04:30:03 PM PDT 24 2585143572 ps
T365 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3727311948 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:02 PM PDT 24 2540076490 ps
T366 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.784869970 Aug 19 04:29:57 PM PDT 24 Aug 19 04:29:58 PM PDT 24 933053898 ps
T100 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2003529281 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:04 PM PDT 24 106673197 ps
T200 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2915265871 Aug 19 04:29:47 PM PDT 24 Aug 19 04:30:10 PM PDT 24 5628417457 ps
T155 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3349975076 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:39 PM PDT 24 8920082164 ps
T158 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1308904233 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:10 PM PDT 24 294840892 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1569990707 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:57 PM PDT 24 189074659 ps
T144 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1629979987 Aug 19 04:29:51 PM PDT 24 Aug 19 04:30:57 PM PDT 24 4551713080 ps
T159 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2515258334 Aug 19 04:29:43 PM PDT 24 Aug 19 04:29:50 PM PDT 24 774118368 ps
T368 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2650763866 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:57 PM PDT 24 6254835585 ps
T369 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3174844133 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:12 PM PDT 24 5381906262 ps
T370 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.415677421 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:14 PM PDT 24 13439805517 ps
T371 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2378519933 Aug 19 04:29:50 PM PDT 24 Aug 19 04:29:51 PM PDT 24 179112757 ps
T372 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1505692075 Aug 19 04:30:10 PM PDT 24 Aug 19 04:30:26 PM PDT 24 17397201780 ps
T373 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.923348039 Aug 19 04:30:02 PM PDT 24 Aug 19 04:30:03 PM PDT 24 129778917 ps
T374 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4275905734 Aug 19 04:29:39 PM PDT 24 Aug 19 04:30:48 PM PDT 24 27186811987 ps
T375 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2207789582 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:54 PM PDT 24 155596982 ps
T376 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4129621993 Aug 19 04:29:49 PM PDT 24 Aug 19 04:29:52 PM PDT 24 219115357 ps
T377 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.563577514 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:05 PM PDT 24 96088880 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3699468778 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:59 PM PDT 24 1261275263 ps
T202 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.865617448 Aug 19 04:30:14 PM PDT 24 Aug 19 04:30:25 PM PDT 24 896760280 ps
T379 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2817273421 Aug 19 04:29:52 PM PDT 24 Aug 19 04:29:58 PM PDT 24 3369460134 ps
T160 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.883006353 Aug 19 04:29:42 PM PDT 24 Aug 19 04:29:48 PM PDT 24 165259671 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.954352647 Aug 19 04:29:55 PM PDT 24 Aug 19 04:30:09 PM PDT 24 4546746052 ps
T381 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4266000762 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:03 PM PDT 24 95025000 ps
T204 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2146195160 Aug 19 04:29:42 PM PDT 24 Aug 19 04:30:04 PM PDT 24 4258436049 ps
T382 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.504423456 Aug 19 04:30:08 PM PDT 24 Aug 19 04:30:13 PM PDT 24 213507725 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.161455932 Aug 19 04:29:44 PM PDT 24 Aug 19 04:29:45 PM PDT 24 168885372 ps
T384 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2582805349 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:06 PM PDT 24 137659358 ps
T385 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.274987709 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:38 PM PDT 24 79322925 ps
T386 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2426196315 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:01 PM PDT 24 569108375 ps
T387 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1576813386 Aug 19 04:29:49 PM PDT 24 Aug 19 04:29:50 PM PDT 24 215655777 ps
T388 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4057065510 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:09 PM PDT 24 8338406062 ps
T205 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4094205283 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:19 PM PDT 24 1193773306 ps
T389 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1622327065 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:57 PM PDT 24 220464603 ps
T390 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2454024085 Aug 19 04:29:50 PM PDT 24 Aug 19 04:30:11 PM PDT 24 3670724454 ps
T161 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.752127766 Aug 19 04:30:02 PM PDT 24 Aug 19 04:30:06 PM PDT 24 221668337 ps
T391 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.755431357 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:39 PM PDT 24 10723163305 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.813307612 Aug 19 04:29:45 PM PDT 24 Aug 19 04:30:15 PM PDT 24 10646024842 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1018952855 Aug 19 04:30:03 PM PDT 24 Aug 19 04:31:53 PM PDT 24 40413989921 ps
T393 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.913229737 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:09 PM PDT 24 5242942009 ps
T394 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3796202705 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:34 PM PDT 24 11212541206 ps
T162 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1581099432 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:10 PM PDT 24 722678753 ps
T395 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1944148756 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:19 PM PDT 24 109586260 ps
T210 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3527454302 Aug 19 04:29:48 PM PDT 24 Aug 19 04:30:08 PM PDT 24 1798496429 ps
T396 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2662800979 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:12 PM PDT 24 1375210474 ps
T397 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1133631926 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:05 PM PDT 24 351865476 ps
T398 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3392786408 Aug 19 04:30:20 PM PDT 24 Aug 19 04:30:29 PM PDT 24 1878276710 ps
T399 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.852837295 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:42 PM PDT 24 13930168096 ps
T400 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1872072587 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:55 PM PDT 24 266122791 ps
T401 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3029302333 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:47 PM PDT 24 3215026986 ps
T145 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2803983075 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:55 PM PDT 24 157277184 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2972516592 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:05 PM PDT 24 151552778 ps
T146 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.133362969 Aug 19 04:29:52 PM PDT 24 Aug 19 04:29:54 PM PDT 24 58153410 ps
T104 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1186630119 Aug 19 04:29:33 PM PDT 24 Aug 19 04:30:12 PM PDT 24 9788482009 ps
T403 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1823441991 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:48 PM PDT 24 195307021 ps
T404 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4203035159 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:00 PM PDT 24 348760940 ps
T405 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1250787068 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:35 PM PDT 24 2638583598 ps
T406 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2673372952 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:45 PM PDT 24 21818888999 ps
T407 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3088547930 Aug 19 04:30:12 PM PDT 24 Aug 19 04:30:12 PM PDT 24 193913313 ps
T408 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2596725343 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:00 PM PDT 24 328083939 ps
T409 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.120529599 Aug 19 04:29:55 PM PDT 24 Aug 19 04:30:07 PM PDT 24 2826484411 ps
T410 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2570355697 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:59 PM PDT 24 299987613 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2329317135 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:59 PM PDT 24 221516230 ps
T103 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3412049888 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:19 PM PDT 24 336817549 ps
T412 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1047696749 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:02 PM PDT 24 493787892 ps
T413 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2666818330 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:21 PM PDT 24 12585976983 ps
T414 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2722217607 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 25853946919 ps
T415 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.264902177 Aug 19 04:30:18 PM PDT 24 Aug 19 04:30:24 PM PDT 24 5503336068 ps
T416 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2677547469 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:58 PM PDT 24 488922430 ps
T417 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.197621654 Aug 19 04:29:58 PM PDT 24 Aug 19 04:30:01 PM PDT 24 105142714 ps
T418 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1015814062 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:54 PM PDT 24 11804472536 ps
T419 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2360499354 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:07 PM PDT 24 292402137 ps
T420 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2382644067 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:08 PM PDT 24 214763745 ps
T421 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.768127072 Aug 19 04:29:48 PM PDT 24 Aug 19 04:30:07 PM PDT 24 19023772261 ps
T422 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.162410119 Aug 19 04:30:17 PM PDT 24 Aug 19 04:30:35 PM PDT 24 2541079605 ps
T423 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.537841633 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:04 PM PDT 24 261018286 ps
T424 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.571553366 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:42 PM PDT 24 16212720625 ps
T425 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.792449266 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:57 PM PDT 24 177006895 ps
T208 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1951342524 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:25 PM PDT 24 8180420242 ps
T129 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.30132937 Aug 19 04:29:54 PM PDT 24 Aug 19 04:30:45 PM PDT 24 21092442362 ps
T426 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1504030426 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:36 PM PDT 24 4304537685 ps
T427 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1307158375 Aug 19 04:29:58 PM PDT 24 Aug 19 04:30:01 PM PDT 24 504426265 ps
T428 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1247814137 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:09 PM PDT 24 114290619 ps
T147 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1982404504 Aug 19 04:29:54 PM PDT 24 Aug 19 04:31:14 PM PDT 24 8908171121 ps
T429 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1581003832 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:14 PM PDT 24 88377906 ps
T430 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3299826710 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:55 PM PDT 24 363652886 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2855017597 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:52 PM PDT 24 209470950 ps
T432 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1565490389 Aug 19 04:29:54 PM PDT 24 Aug 19 04:32:34 PM PDT 24 109599861031 ps
T433 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1438293245 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:06 PM PDT 24 1963207624 ps
T434 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.133331691 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:57 PM PDT 24 172817076 ps
T148 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3401230319 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:06 PM PDT 24 450403094 ps
T149 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3339232245 Aug 19 04:29:46 PM PDT 24 Aug 19 04:30:18 PM PDT 24 11706811609 ps
T435 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.285990779 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:20 PM PDT 24 2968369425 ps
T436 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3076382444 Aug 19 04:29:53 PM PDT 24 Aug 19 04:29:55 PM PDT 24 57688516 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.675691619 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:22 PM PDT 24 19049616210 ps
T438 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3339341391 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:55 PM PDT 24 79036870 ps
T130 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2377464114 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:52 PM PDT 24 19874308979 ps
T439 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2710072166 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:58 PM PDT 24 246701694 ps
T440 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1100156131 Aug 19 04:29:50 PM PDT 24 Aug 19 04:29:50 PM PDT 24 69449948 ps
T441 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3194600956 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:12 PM PDT 24 558059803 ps
T442 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1360841800 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:06 PM PDT 24 95048817 ps
T443 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.618213985 Aug 19 04:29:52 PM PDT 24 Aug 19 04:29:52 PM PDT 24 53328453 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1285185136 Aug 19 04:29:33 PM PDT 24 Aug 19 04:30:33 PM PDT 24 2351604556 ps
T444 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.242893153 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:03 PM PDT 24 135748199 ps
T445 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.100568270 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:07 PM PDT 24 162194937 ps
T446 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1423066343 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:59 PM PDT 24 583285278 ps
T447 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2161686157 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:59 PM PDT 24 2952131290 ps
T150 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1274002888 Aug 19 04:29:50 PM PDT 24 Aug 19 04:29:54 PM PDT 24 3996833656 ps
T448 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.966642416 Aug 19 04:29:40 PM PDT 24 Aug 19 04:29:59 PM PDT 24 4164540945 ps
T449 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3162619520 Aug 19 04:29:55 PM PDT 24 Aug 19 04:30:03 PM PDT 24 1065092334 ps
T450 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3657104962 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:00 PM PDT 24 623947800 ps
T451 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1759191139 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:11 PM PDT 24 3033857266 ps
T452 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2849772381 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:59 PM PDT 24 759823035 ps
T453 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2623616065 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:40 PM PDT 24 4996143186 ps
T454 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1496424140 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:10 PM PDT 24 340024594 ps
T455 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.338785463 Aug 19 04:29:34 PM PDT 24 Aug 19 04:30:49 PM PDT 24 30433003446 ps
T456 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.800777826 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:08 PM PDT 24 521507519 ps
T105 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3432588331 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:00 PM PDT 24 66852889 ps
T457 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1499832800 Aug 19 04:29:54 PM PDT 24 Aug 19 04:30:42 PM PDT 24 60877626472 ps
T458 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1415573549 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:48 PM PDT 24 907245117 ps
T459 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3507409450 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:08 PM PDT 24 470472178 ps
T460 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.547606840 Aug 19 04:29:57 PM PDT 24 Aug 19 04:29:58 PM PDT 24 287234612 ps
T461 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2898719806 Aug 19 04:29:55 PM PDT 24 Aug 19 04:30:00 PM PDT 24 3645760628 ps
T462 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.627304521 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:09 PM PDT 24 199201677 ps
T463 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2669355246 Aug 19 04:29:48 PM PDT 24 Aug 19 04:29:49 PM PDT 24 178531360 ps
T464 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.550544283 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:56 PM PDT 24 402675868 ps
T151 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.843353094 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:09 PM PDT 24 620974662 ps
T465 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.329361650 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:53 PM PDT 24 237044816 ps
T466 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.691886755 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:59 PM PDT 24 45070319 ps
T206 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2433623604 Aug 19 04:30:18 PM PDT 24 Aug 19 04:30:37 PM PDT 24 4367298726 ps
T467 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.585754195 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:09 PM PDT 24 627786502 ps
T468 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1487345646 Aug 19 04:29:31 PM PDT 24 Aug 19 04:33:21 PM PDT 24 83495429978 ps
T469 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.445229354 Aug 19 04:30:25 PM PDT 24 Aug 19 04:30:28 PM PDT 24 169722333 ps
T470 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3889002685 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:47 PM PDT 24 32149061096 ps
T203 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4274491216 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:20 PM PDT 24 3284633376 ps
T471 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3044604330 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:08 PM PDT 24 574036259 ps
T209 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1699952788 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:02 PM PDT 24 677415780 ps
T472 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2363981784 Aug 19 04:29:57 PM PDT 24 Aug 19 04:30:01 PM PDT 24 1657146917 ps
T473 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3765202521 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:06 PM PDT 24 284988955 ps
T474 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2869199735 Aug 19 04:29:33 PM PDT 24 Aug 19 04:29:38 PM PDT 24 5790799990 ps
T475 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2027120960 Aug 19 04:29:53 PM PDT 24 Aug 19 04:31:55 PM PDT 24 38756555920 ps
T476 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4092911140 Aug 19 04:29:50 PM PDT 24 Aug 19 04:30:08 PM PDT 24 22234231629 ps
T153 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3970039263 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:58 PM PDT 24 137386211 ps
T477 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.346725203 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:56 PM PDT 24 154287064 ps
T478 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3112998251 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:09 PM PDT 24 1021123845 ps
T207 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1541838333 Aug 19 04:30:12 PM PDT 24 Aug 19 04:30:23 PM PDT 24 2058633204 ps
T479 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4044225908 Aug 19 04:29:56 PM PDT 24 Aug 19 04:30:05 PM PDT 24 152431813 ps
T480 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3081873894 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:02 PM PDT 24 1479628669 ps
T481 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.725544611 Aug 19 04:29:58 PM PDT 24 Aug 19 04:30:14 PM PDT 24 1281340527 ps

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.3303767750
Short name T3
Test name
Test status
Simulation time 1967037412 ps
CPU time 23.97 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 220480 kb
Host smart-64407c39-fa3f-411b-8948-2eeb2544d087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303767750 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.3303767750
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1825098414
Short name T15
Test name
Test status
Simulation time 1831024746 ps
CPU time 3.78 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 205456 kb
Host smart-bb1de015-9682-4017-8d3f-400341c7c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825098414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1825098414
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2092430082
Short name T6
Test name
Test status
Simulation time 2470493018 ps
CPU time 1.88 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 205244 kb
Host smart-1957ab85-d601-44d7-82ac-c3dbe13e3ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092430082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2092430082
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.3136225982
Short name T53
Test name
Test status
Simulation time 8473791244 ps
CPU time 109.9 seconds
Started Aug 19 04:34:53 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 229888 kb
Host smart-f7657a01-6379-4d1a-a90a-c339939507b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136225982 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.3136225982
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1993650750
Short name T114
Test name
Test status
Simulation time 4217102109 ps
CPU time 23.71 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:24 PM PDT 24
Peak memory 221980 kb
Host smart-0f762c77-90c7-4d38-bd9f-8a2c41e16f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993650750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
993650750
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2361745940
Short name T90
Test name
Test status
Simulation time 6915603427 ps
CPU time 7.62 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:35:04 PM PDT 24
Peak memory 205252 kb
Host smart-7ad24da3-df14-4169-96c9-12107f86fd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361745940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2361745940
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_buffered_enable.172415955
Short name T55
Test name
Test status
Simulation time 487527149 ps
CPU time 2.13 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 225920 kb
Host smart-dd476f77-5d81-405f-87d1-fc52489a1637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172415955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.172415955
Directory /workspace/1.rv_dm_buffered_enable/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.107036412
Short name T98
Test name
Test status
Simulation time 3679386422 ps
CPU time 50.69 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:30:36 PM PDT 24
Peak memory 213752 kb
Host smart-c869988f-9ab7-4340-a5f4-073e17b9b14f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107036412 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.107036412
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2186719847
Short name T314
Test name
Test status
Simulation time 79424864919 ps
CPU time 97.36 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:36:33 PM PDT 24
Peak memory 213536 kb
Host smart-dd68c7b5-3af8-421b-8211-579e1b0b88d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186719847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2186719847
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3554200876
Short name T51
Test name
Test status
Simulation time 2748834064 ps
CPU time 58.8 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:36:20 PM PDT 24
Peak memory 217716 kb
Host smart-cefbde62-0421-4d29-b22c-a5d221de2f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554200876 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3554200876
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_scanmode.1474579615
Short name T82
Test name
Test status
Simulation time 23280983 ps
CPU time 0.68 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 204976 kb
Host smart-14c8078d-51b3-4662-88a1-4c98808ba4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474579615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.1474579615
Directory /workspace/0.rv_dm_scanmode/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1773934115
Short name T26
Test name
Test status
Simulation time 2955126207 ps
CPU time 5.99 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 213712 kb
Host smart-1c59d7db-aafc-4e47-96aa-600f20cdefd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773934115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1773934115
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2730507263
Short name T12
Test name
Test status
Simulation time 4220086649 ps
CPU time 4.13 seconds
Started Aug 19 04:35:39 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 213556 kb
Host smart-a2820276-2e75-417e-8def-9aa4095a6575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730507263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2730507263
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.817484830
Short name T60
Test name
Test status
Simulation time 196488597 ps
CPU time 1.02 seconds
Started Aug 19 04:35:10 PM PDT 24
Finished Aug 19 04:35:11 PM PDT 24
Peak memory 205032 kb
Host smart-846d6c5f-9cb0-4618-b52d-59e5689e80bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817484830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.817484830
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2945831424
Short name T35
Test name
Test status
Simulation time 1330565956 ps
CPU time 1.66 seconds
Started Aug 19 04:35:01 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 229624 kb
Host smart-f284c67a-4b26-4af8-9938-32c1d9e7e1bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945831424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2945831424
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.3737539601
Short name T10
Test name
Test status
Simulation time 4124577414 ps
CPU time 35.07 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:36:05 PM PDT 24
Peak memory 221720 kb
Host smart-9bc7bc73-a20f-4c1a-85ab-ffc77cb6bb6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737539601 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.3737539601
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1405562482
Short name T117
Test name
Test status
Simulation time 52232664 ps
CPU time 1.41 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:29:49 PM PDT 24
Peak memory 213772 kb
Host smart-fbff1b46-7ee1-4246-9f4a-0ef46163f2e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405562482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1405562482
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1285185136
Short name T101
Test name
Test status
Simulation time 2351604556 ps
CPU time 60.44 seconds
Started Aug 19 04:29:33 PM PDT 24
Finished Aug 19 04:30:33 PM PDT 24
Peak memory 217296 kb
Host smart-4220360c-88cc-42ca-a196-33572c10d435
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285185136 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1285185136
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1186630119
Short name T104
Test name
Test status
Simulation time 9788482009 ps
CPU time 39.15 seconds
Started Aug 19 04:29:33 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 217888 kb
Host smart-195dc55e-e9b5-4283-b4dc-f6e79faf695d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186630119 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1186630119
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.84830739
Short name T61
Test name
Test status
Simulation time 35603106613 ps
CPU time 58.28 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 219852 kb
Host smart-6c320998-dd36-48c0-aec8-c422b4bc02cd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84830739 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.84830739
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3013318498
Short name T177
Test name
Test status
Simulation time 5987290540 ps
CPU time 10.56 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 213660 kb
Host smart-93978ba2-049b-4542-bdd4-fcde312d3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013318498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3013318498
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1408414248
Short name T18
Test name
Test status
Simulation time 142516800 ps
CPU time 1.12 seconds
Started Aug 19 04:35:08 PM PDT 24
Finished Aug 19 04:35:10 PM PDT 24
Peak memory 205020 kb
Host smart-2dbeb7c6-636d-4734-9226-34d7c396dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408414248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1408414248
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.4069923420
Short name T134
Test name
Test status
Simulation time 3197336023 ps
CPU time 9.5 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 205328 kb
Host smart-136212f8-ac2a-4d27-886f-5146fa87e2b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069923420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.4069923420
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2400194910
Short name T41
Test name
Test status
Simulation time 72629303 ps
CPU time 0.85 seconds
Started Aug 19 04:35:13 PM PDT 24
Finished Aug 19 04:35:14 PM PDT 24
Peak memory 213292 kb
Host smart-f523ec82-3ec4-4693-8e16-0740bd8178a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400194910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2400194910
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2163173146
Short name T2
Test name
Test status
Simulation time 30485824 ps
CPU time 0.74 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 205024 kb
Host smart-52e140ca-db6e-422b-9651-ea98d22311fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163173146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2163173146
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2433623604
Short name T206
Test name
Test status
Simulation time 4367298726 ps
CPU time 19.58 seconds
Started Aug 19 04:30:18 PM PDT 24
Finished Aug 19 04:30:37 PM PDT 24
Peak memory 213804 kb
Host smart-d1c520bd-a53f-455a-aff7-5f1ad25ea4be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433623604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2433623604
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.346453322
Short name T23
Test name
Test status
Simulation time 1091861521 ps
CPU time 3.93 seconds
Started Aug 19 04:35:05 PM PDT 24
Finished Aug 19 04:35:09 PM PDT 24
Peak memory 205020 kb
Host smart-ae10f5b7-e120-491d-ba9b-88ab19822497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346453322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.346453322
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.4263653780
Short name T44
Test name
Test status
Simulation time 7111219259 ps
CPU time 20.31 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 205264 kb
Host smart-3faf3fb8-b735-43e3-a033-9367163c0f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263653780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.4263653780
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.372017676
Short name T175
Test name
Test status
Simulation time 680407762 ps
CPU time 2.52 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 205224 kb
Host smart-27df83e9-6fe7-47d4-9221-b2ee92f908e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372017676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.372017676
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3973701315
Short name T70
Test name
Test status
Simulation time 197868076 ps
CPU time 1.18 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 205032 kb
Host smart-1771e07c-ee1b-45df-bbd0-37faa51ea85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973701315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3973701315
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3980617311
Short name T50
Test name
Test status
Simulation time 5529833837 ps
CPU time 14.62 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:41 PM PDT 24
Peak memory 205348 kb
Host smart-9fb986b3-c725-4ecf-8606-7b30c478c533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980617311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3980617311
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1951342524
Short name T208
Test name
Test status
Simulation time 8180420242 ps
CPU time 19.49 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 213856 kb
Host smart-b131a7cd-3133-4157-b95d-ecd844384932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951342524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
951342524
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.342439422
Short name T106
Test name
Test status
Simulation time 645551807 ps
CPU time 0.98 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 205300 kb
Host smart-de6d8c89-4d01-4ba2-b3ec-9553589fb207
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342439422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.342439422
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1629979987
Short name T144
Test name
Test status
Simulation time 4551713080 ps
CPU time 65.9 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 213876 kb
Host smart-2d8da75c-a4ea-4bdc-9050-92d89520d796
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629979987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1629979987
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.883006353
Short name T160
Test name
Test status
Simulation time 165259671 ps
CPU time 5.91 seconds
Started Aug 19 04:29:42 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 205508 kb
Host smart-feed6ce5-f498-4faa-a5a3-6ff3e1c6710c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883006353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.883006353
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2377464114
Short name T130
Test name
Test status
Simulation time 19874308979 ps
CPU time 14.85 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:52 PM PDT 24
Peak memory 205536 kb
Host smart-c6f2d46a-1ee4-4ab4-9c14-386891e2120a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377464114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2377464114
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2023682604
Short name T39
Test name
Test status
Simulation time 747915822 ps
CPU time 2.03 seconds
Started Aug 19 04:35:13 PM PDT 24
Finished Aug 19 04:35:15 PM PDT 24
Peak memory 205012 kb
Host smart-c3a79af3-087f-46f4-9bd4-a73483222eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023682604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2023682604
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4274491216
Short name T203
Test name
Test status
Simulation time 3284633376 ps
CPU time 24.15 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 213820 kb
Host smart-cb520a85-9a50-4933-a229-b30c9e55cd7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274491216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4274491216
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2746586181
Short name T81
Test name
Test status
Simulation time 1167465580 ps
CPU time 2.2 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 205040 kb
Host smart-ac288945-04b8-4767-ad2c-f3365829e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746586181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2746586181
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2571134909
Short name T188
Test name
Test status
Simulation time 3615620572 ps
CPU time 9.78 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 205216 kb
Host smart-502131ee-a017-4240-a690-59925c2ffaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571134909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2571134909
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3048124090
Short name T315
Test name
Test status
Simulation time 2636967457 ps
CPU time 2.04 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 214664 kb
Host smart-60884814-04db-4a0b-85c6-e9d36aca31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048124090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3048124090
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1154707099
Short name T183
Test name
Test status
Simulation time 17875230538 ps
CPU time 25.78 seconds
Started Aug 19 04:35:17 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 213720 kb
Host smart-b8cf213e-5d73-4881-b5ba-25c21ebbdcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154707099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1154707099
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.2912771133
Short name T185
Test name
Test status
Simulation time 2916762286 ps
CPU time 8.95 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:41 PM PDT 24
Peak memory 205272 kb
Host smart-e97c5ff8-44ed-47be-aaf3-492145037288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912771133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2912771133
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2803983075
Short name T145
Test name
Test status
Simulation time 157277184 ps
CPU time 1.71 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 218708 kb
Host smart-f22f6440-3f1b-4c91-9b54-15b4d940af42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803983075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2803983075
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_sparse_lc_gate_fsm.3366917581
Short name T62
Test name
Test status
Simulation time 167725346 ps
CPU time 0.95 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 213360 kb
Host smart-981a1845-4629-4c58-9a46-7bc2a5221704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366917581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.3366917581
Directory /workspace/0.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/2.rv_dm_sparse_lc_gate_fsm.697693301
Short name T67
Test name
Test status
Simulation time 162968268 ps
CPU time 0.86 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 213312 kb
Host smart-9da45337-d479-4be2-b911-0561e21e9ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697693301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.697693301
Directory /workspace/2.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3339232245
Short name T149
Test name
Test status
Simulation time 11706811609 ps
CPU time 31.14 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 215120 kb
Host smart-b7fdab3f-2103-4cbd-a53a-5b834e1df129
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339232245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3339232245
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1499832800
Short name T457
Test name
Test status
Simulation time 60877626472 ps
CPU time 47.98 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:30:42 PM PDT 24
Peak memory 213700 kb
Host smart-5b91f06f-e777-4ded-99c1-e044dc8f7965
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499832800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1499832800
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2264633307
Short name T140
Test name
Test status
Simulation time 648753722 ps
CPU time 2.68 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:29:51 PM PDT 24
Peak memory 213552 kb
Host smart-b53c7b32-ef1d-43b7-8a1d-e52ce922f9ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264633307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2264633307
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4129621993
Short name T376
Test name
Test status
Simulation time 219115357 ps
CPU time 2.47 seconds
Started Aug 19 04:29:49 PM PDT 24
Finished Aug 19 04:29:52 PM PDT 24
Peak memory 218008 kb
Host smart-0d93f221-77a7-4c90-a5e1-38f73f19393f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129621993 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.4129621993
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2971401472
Short name T152
Test name
Test status
Simulation time 52548248 ps
CPU time 2.09 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 213748 kb
Host smart-f7d12ac1-ccff-49cf-b980-6815f0c5368c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971401472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2971401472
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1487345646
Short name T468
Test name
Test status
Simulation time 83495429978 ps
CPU time 229.48 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:33:21 PM PDT 24
Peak memory 205468 kb
Host smart-e2dbd575-f95c-433a-91c0-4505a8352d22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487345646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1487345646
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.675691619
Short name T437
Test name
Test status
Simulation time 19049616210 ps
CPU time 28.76 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:22 PM PDT 24
Peak memory 205504 kb
Host smart-130d9485-10bb-4b29-8d66-fcd52f169754
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675691619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.675691619
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2898719806
Short name T461
Test name
Test status
Simulation time 3645760628 ps
CPU time 4.77 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 205476 kb
Host smart-97fd8ab2-0248-4f38-9617-c9dbf3be7968
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898719806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2898719806
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2869199735
Short name T474
Test name
Test status
Simulation time 5790799990 ps
CPU time 4.6 seconds
Started Aug 19 04:29:33 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 205472 kb
Host smart-8fc7afbf-cffc-4d26-9c56-05d4d29b26f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869199735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
869199735
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.338785463
Short name T455
Test name
Test status
Simulation time 30433003446 ps
CPU time 75.76 seconds
Started Aug 19 04:29:34 PM PDT 24
Finished Aug 19 04:30:49 PM PDT 24
Peak memory 205376 kb
Host smart-6656aa73-ff05-41fa-b127-3d2772571bb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338785463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.338785463
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2710072166
Short name T439
Test name
Test status
Simulation time 246701694 ps
CPU time 1.18 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 205256 kb
Host smart-5f1d82d8-2822-4a8b-b168-e8f83cb824ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710072166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2710072166
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.161455932
Short name T383
Test name
Test status
Simulation time 168885372 ps
CPU time 1.16 seconds
Started Aug 19 04:29:44 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 205532 kb
Host smart-aac9735c-b4c9-4bb3-806c-f184005b27e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161455932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.161455932
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2378519933
Short name T371
Test name
Test status
Simulation time 179112757 ps
CPU time 1.06 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:29:51 PM PDT 24
Peak memory 205208 kb
Host smart-be44c0e0-8513-41f2-89dd-464aedbd0c8d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378519933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2378519933
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.923348039
Short name T373
Test name
Test status
Simulation time 129778917 ps
CPU time 0.7 seconds
Started Aug 19 04:30:02 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 205132 kb
Host smart-3c931943-9cac-4a6b-bd25-5d45dfc205c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923348039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.923348039
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1423066343
Short name T446
Test name
Test status
Simulation time 583285278 ps
CPU time 7.69 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 205416 kb
Host smart-bf691bcb-6967-4b03-b819-ba21fc4a4ca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423066343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1423066343
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2454024085
Short name T390
Test name
Test status
Simulation time 3670724454 ps
CPU time 20.53 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 215924 kb
Host smart-061e7601-8522-4af6-95d4-18dc1575f267
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454024085 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2454024085
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.484660064
Short name T339
Test name
Test status
Simulation time 125348355 ps
CPU time 5.4 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 213756 kb
Host smart-7bc48137-fca5-4410-8625-c38bee29a55a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484660064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.484660064
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2416994181
Short name T173
Test name
Test status
Simulation time 713965615 ps
CPU time 8.07 seconds
Started Aug 19 04:29:40 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 221880 kb
Host smart-7b41ea73-e37b-4f47-b9d4-b62175b4a425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416994181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2416994181
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4275905734
Short name T374
Test name
Test status
Simulation time 27186811987 ps
CPU time 68.53 seconds
Started Aug 19 04:29:39 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 205624 kb
Host smart-fa2474fa-a852-4834-8491-b5abaf497fd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275905734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4275905734
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.164371222
Short name T358
Test name
Test status
Simulation time 160841434 ps
CPU time 2.3 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 213696 kb
Host smart-87144b2d-5f2d-46c2-97a4-8899ece63f5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164371222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.164371222
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2329317135
Short name T411
Test name
Test status
Simulation time 221516230 ps
CPU time 3.01 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 221524 kb
Host smart-8043fc3e-2f9f-4ddb-a91a-95eab011a982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329317135 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2329317135
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1576813386
Short name T387
Test name
Test status
Simulation time 215655777 ps
CPU time 1.48 seconds
Started Aug 19 04:29:49 PM PDT 24
Finished Aug 19 04:29:50 PM PDT 24
Peak memory 213748 kb
Host smart-3864b52d-f10c-4d1a-b329-24e00a7af4ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576813386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1576813386
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4151371872
Short name T331
Test name
Test status
Simulation time 38893229739 ps
CPU time 99.4 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:31:33 PM PDT 24
Peak memory 205472 kb
Host smart-3f1e9c8c-b948-413a-b48b-3b29ffda031f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151371872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4151371872
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.768127072
Short name T421
Test name
Test status
Simulation time 19023772261 ps
CPU time 18.85 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 205348 kb
Host smart-ece08bcf-6f20-4672-b948-adc0c0df7ed1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768127072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.768127072
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1504030426
Short name T426
Test name
Test status
Simulation time 4304537685 ps
CPU time 5.21 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:36 PM PDT 24
Peak memory 205340 kb
Host smart-2a6eb823-ed53-4bcb-94ac-c4c466457033
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504030426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1504030426
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3227032644
Short name T332
Test name
Test status
Simulation time 3145061960 ps
CPU time 8.07 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 205472 kb
Host smart-6ca10513-4a17-48aa-9afa-cc80c3a6ce54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227032644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
227032644
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3699468778
Short name T378
Test name
Test status
Simulation time 1261275263 ps
CPU time 2.59 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 205144 kb
Host smart-c41ee4eb-1806-4877-816c-7856218ad5b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699468778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3699468778
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4092911140
Short name T476
Test name
Test status
Simulation time 22234231629 ps
CPU time 18.18 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 205372 kb
Host smart-ddf23002-0335-42a5-a6c0-5980ef8faed0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092911140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4092911140
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.537841633
Short name T423
Test name
Test status
Simulation time 261018286 ps
CPU time 1.12 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 205256 kb
Host smart-e1c15465-8672-497a-a8fc-42d08a7c1a64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537841633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.537841633
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2207789582
Short name T375
Test name
Test status
Simulation time 155596982 ps
CPU time 1.08 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:54 PM PDT 24
Peak memory 205148 kb
Host smart-fb5599c9-4e72-4b1b-bd28-7f7d0f1d7878
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207789582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
207789582
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.461467985
Short name T336
Test name
Test status
Simulation time 80144292 ps
CPU time 0.67 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 205200 kb
Host smart-8b2af8c0-2b1a-46c6-a1db-fa9c01eecdf6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461467985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.461467985
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.672918694
Short name T333
Test name
Test status
Simulation time 104644270 ps
CPU time 0.92 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:54 PM PDT 24
Peak memory 205264 kb
Host smart-3c996ee1-10f8-449f-a891-e13ea2c075ab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672918694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.672918694
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1823441991
Short name T403
Test name
Test status
Simulation time 195307021 ps
CPU time 1.88 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 213616 kb
Host smart-7f4202c2-8ed5-455c-b65c-efda5096cca7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823441991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1823441991
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1699952788
Short name T209
Test name
Test status
Simulation time 677415780 ps
CPU time 9.11 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 221928 kb
Host smart-abafb6a0-2f2d-4d78-8044-133f27831935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699952788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1699952788
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4044225908
Short name T479
Test name
Test status
Simulation time 152431813 ps
CPU time 3.29 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 219380 kb
Host smart-3768adfe-89b3-4307-9e45-09dab3a14c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044225908 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.4044225908
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.133362969
Short name T146
Test name
Test status
Simulation time 58153410 ps
CPU time 2.14 seconds
Started Aug 19 04:29:52 PM PDT 24
Finished Aug 19 04:29:54 PM PDT 24
Peak memory 213604 kb
Host smart-5910f8c2-87ab-4669-a12b-5ac403cac88e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133362969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.133362969
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.287824282
Short name T348
Test name
Test status
Simulation time 29914413325 ps
CPU time 49.4 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 205396 kb
Host smart-8a65f245-77b2-40f8-a47e-dbec4d0451fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287824282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.287824282
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1403744970
Short name T337
Test name
Test status
Simulation time 1839722512 ps
CPU time 2.43 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 205336 kb
Host smart-386911b1-360a-4b13-9b70-945cd7df939c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403744970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1403744970
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.114199653
Short name T355
Test name
Test status
Simulation time 121634893 ps
CPU time 0.68 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 205264 kb
Host smart-00e079cb-a797-4229-8d19-83b339ad4e29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114199653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.114199653
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.168414277
Short name T156
Test name
Test status
Simulation time 955165828 ps
CPU time 4.47 seconds
Started Aug 19 04:30:01 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 205532 kb
Host smart-38584298-bff3-41b2-90f4-c27b4370548d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168414277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.168414277
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3657104962
Short name T450
Test name
Test status
Simulation time 623947800 ps
CPU time 2.47 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 213732 kb
Host smart-20ea9551-17fa-4b5c-8edb-d3a0a13c6f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657104962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3657104962
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1975093740
Short name T113
Test name
Test status
Simulation time 422087351 ps
CPU time 3.08 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 217848 kb
Host smart-5bab5784-813c-4933-8970-f67ed10f37ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975093740 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1975093740
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.133359
Short name T359
Test name
Test status
Simulation time 2850812699 ps
CPU time 9.31 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 205464 kb
Host smart-fd7c56c0-47c0-4be6-9a83-896c3b0b59b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_
dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_
dm_jtag_dmi_csr_bit_bash.133359
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2626846727
Short name T364
Test name
Test status
Simulation time 2585143572 ps
CPU time 6.58 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 205544 kb
Host smart-01aa589c-c085-4b90-bd1b-4937813a0ec1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626846727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2626846727
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.753566048
Short name T353
Test name
Test status
Simulation time 170691484 ps
CPU time 0.93 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 205144 kb
Host smart-21231ac1-d81b-49e8-ae84-8d8d8693d41d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753566048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.753566048
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2393628500
Short name T122
Test name
Test status
Simulation time 974684713 ps
CPU time 4.03 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:29:51 PM PDT 24
Peak memory 205524 kb
Host smart-b36352d8-d7d5-4b00-968c-3f704eb364bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393628500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2393628500
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2677547469
Short name T416
Test name
Test status
Simulation time 488922430 ps
CPU time 2.87 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 213696 kb
Host smart-99a1633c-47a5-4064-bed1-5d943ad30282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677547469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2677547469
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.865617448
Short name T202
Test name
Test status
Simulation time 896760280 ps
CPU time 11 seconds
Started Aug 19 04:30:14 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 221724 kb
Host smart-288c7aef-c536-4d42-8f9d-7fe15109bd88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865617448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.865617448
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3076382444
Short name T436
Test name
Test status
Simulation time 57688516 ps
CPU time 1.95 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 216780 kb
Host smart-efc09c1d-67f7-4928-b5a9-693085432fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076382444 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3076382444
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2722217607
Short name T414
Test name
Test status
Simulation time 25853946919 ps
CPU time 61.27 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 205348 kb
Host smart-09c920e2-dc78-453f-860e-a04edf7344ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722217607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2722217607
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3174844133
Short name T369
Test name
Test status
Simulation time 5381906262 ps
CPU time 16 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 205468 kb
Host smart-bbcbd5ba-6f0b-4b0c-a836-b976b2751be8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174844133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3174844133
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.819222537
Short name T360
Test name
Test status
Simulation time 82570685 ps
CPU time 0.87 seconds
Started Aug 19 04:29:58 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 205132 kb
Host smart-3203c1f0-2091-41d5-993e-6ee92131e6d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819222537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.819222537
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3507409450
Short name T459
Test name
Test status
Simulation time 470472178 ps
CPU time 4.03 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 205620 kb
Host smart-092019db-041e-4b8f-8eef-6048304221fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507409450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3507409450
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1160438624
Short name T343
Test name
Test status
Simulation time 235261442 ps
CPU time 2.67 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 213628 kb
Host smart-aa965355-35b1-40d6-a293-9ec97c67544c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160438624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1160438624
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2089684356
Short name T174
Test name
Test status
Simulation time 2473101592 ps
CPU time 9.14 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 221824 kb
Host smart-bdd4b3bb-61ea-4511-98e8-fc1d143ba5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089684356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
089684356
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3432588331
Short name T105
Test name
Test status
Simulation time 66852889 ps
CPU time 3.84 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 219916 kb
Host smart-dafc0f65-27c8-4cf7-b10e-0c1787ff1a45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432588331 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3432588331
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.329361650
Short name T465
Test name
Test status
Simulation time 237044816 ps
CPU time 2.15 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:53 PM PDT 24
Peak memory 219024 kb
Host smart-7d769e1a-3d10-4c4e-9fb6-51af6bcb6117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329361650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.329361650
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.571553366
Short name T424
Test name
Test status
Simulation time 16212720625 ps
CPU time 45.72 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:42 PM PDT 24
Peak memory 205340 kb
Host smart-5d9a9352-69e7-41fb-8f7f-3a27c4f9db3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571553366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.571553366
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3727311948
Short name T365
Test name
Test status
Simulation time 2540076490 ps
CPU time 4.63 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 205540 kb
Host smart-6af743d3-f92c-4401-b2b6-b165f6ceba99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727311948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3727311948
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1415573549
Short name T458
Test name
Test status
Simulation time 907245117 ps
CPU time 1.34 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 205128 kb
Host smart-1dd297ba-fe7f-44f3-a8c1-04eb017167c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415573549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1415573549
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3216644263
Short name T143
Test name
Test status
Simulation time 7807205836 ps
CPU time 8.32 seconds
Started Aug 19 04:30:01 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 205624 kb
Host smart-422f6592-f371-4c41-9644-fc8620f97a8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216644263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3216644263
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.197621654
Short name T417
Test name
Test status
Simulation time 105142714 ps
CPU time 2.63 seconds
Started Aug 19 04:29:58 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 213724 kb
Host smart-ccbbb392-1ac9-453b-9a79-0ec2b73ec3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197621654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.197621654
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1541838333
Short name T207
Test name
Test status
Simulation time 2058633204 ps
CPU time 11.19 seconds
Started Aug 19 04:30:12 PM PDT 24
Finished Aug 19 04:30:23 PM PDT 24
Peak memory 221812 kb
Host smart-1f22e1d8-4394-42fa-922b-af407cbff6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541838333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
541838333
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.100568270
Short name T445
Test name
Test status
Simulation time 162194937 ps
CPU time 3.99 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 221628 kb
Host smart-c69d7a63-b9f4-49b1-bba4-063012c76d2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100568270 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.100568270
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2360499354
Short name T419
Test name
Test status
Simulation time 292402137 ps
CPU time 1.59 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 219164 kb
Host smart-431af6b5-f4ac-4595-aba0-07b65ae68c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360499354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2360499354
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.764829268
Short name T335
Test name
Test status
Simulation time 7246439697 ps
CPU time 4.82 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 205348 kb
Host smart-4e6e0bf3-9512-46f1-97fd-44a1d4dd1498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764829268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.764829268
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2650763866
Short name T368
Test name
Test status
Simulation time 6254835585 ps
CPU time 5.61 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 205468 kb
Host smart-d8f3fd87-0d1f-4e5c-ba5b-aeda80469e79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650763866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2650763866
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2596725343
Short name T408
Test name
Test status
Simulation time 328083939 ps
CPU time 1.22 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 205264 kb
Host smart-73822384-03ee-474f-9e86-3ca9e99f07df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596725343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2596725343
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.843353094
Short name T151
Test name
Test status
Simulation time 620974662 ps
CPU time 6.41 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 205604 kb
Host smart-e3c8456c-783d-4fae-abc0-f867aa42088d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843353094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.843353094
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.691886755
Short name T466
Test name
Test status
Simulation time 45070319 ps
CPU time 2.49 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 213708 kb
Host smart-0f92db49-218c-42c5-9dc6-82cfb947c7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691886755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.691886755
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2918802794
Short name T199
Test name
Test status
Simulation time 1044408612 ps
CPU time 16.97 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:23 PM PDT 24
Peak memory 221952 kb
Host smart-9880f9db-e56f-4d12-9d9d-3ecf975e8b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918802794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
918802794
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4266000762
Short name T381
Test name
Test status
Simulation time 95025000 ps
CPU time 3.07 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 218724 kb
Host smart-eca58d71-0bb9-4f89-878e-7d808b4c1bad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266000762 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.4266000762
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1178126956
Short name T142
Test name
Test status
Simulation time 204026873 ps
CPU time 2.59 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 213812 kb
Host smart-1a1881ad-86f2-4971-b451-f58cf926452f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178126956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1178126956
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2673372952
Short name T406
Test name
Test status
Simulation time 21818888999 ps
CPU time 47.8 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:45 PM PDT 24
Peak memory 205432 kb
Host smart-e3d836ab-28b6-4276-8154-40b4ee6ec14c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673372952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2673372952
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2363981784
Short name T472
Test name
Test status
Simulation time 1657146917 ps
CPU time 3.66 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 205248 kb
Host smart-5dd670e6-6947-46dd-8a0a-887b14cfd974
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363981784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2363981784
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1133631926
Short name T397
Test name
Test status
Simulation time 351865476 ps
CPU time 1.13 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 205260 kb
Host smart-a5da4624-0290-4f2e-b355-49dd396e6387
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133631926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1133631926
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.752127766
Short name T161
Test name
Test status
Simulation time 221668337 ps
CPU time 3.92 seconds
Started Aug 19 04:30:02 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 205376 kb
Host smart-fc77e271-01eb-4412-b376-b517393dfba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752127766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.752127766
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1307158375
Short name T427
Test name
Test status
Simulation time 504426265 ps
CPU time 2.98 seconds
Started Aug 19 04:29:58 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 213736 kb
Host smart-10b8b1f2-786a-4b5b-89dc-ba55854ddc00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307158375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1307158375
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1944148756
Short name T395
Test name
Test status
Simulation time 109586260 ps
CPU time 3.66 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:19 PM PDT 24
Peak memory 219840 kb
Host smart-6c33a835-02b6-4d78-907a-3608f46dd27a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944148756 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1944148756
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.627304521
Short name T462
Test name
Test status
Simulation time 199201677 ps
CPU time 1.64 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 213796 kb
Host smart-7a5f74a0-ce95-4c07-9003-dc3e93082f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627304521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.627304521
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1505692075
Short name T372
Test name
Test status
Simulation time 17397201780 ps
CPU time 16.03 seconds
Started Aug 19 04:30:10 PM PDT 24
Finished Aug 19 04:30:26 PM PDT 24
Peak memory 205488 kb
Host smart-eea6d67b-d7a2-4c4e-a88b-6d60f6e0d0a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505692075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1505692075
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4057065510
Short name T388
Test name
Test status
Simulation time 8338406062 ps
CPU time 6.18 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 205420 kb
Host smart-1af347b6-b6fa-4463-ab4e-69050af6538b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057065510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4057065510
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4172535030
Short name T356
Test name
Test status
Simulation time 150677120 ps
CPU time 1.02 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:54 PM PDT 24
Peak memory 205260 kb
Host smart-e4e28ef7-6c08-48b4-8eb5-7440ea83b507
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172535030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
4172535030
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1581099432
Short name T162
Test name
Test status
Simulation time 722678753 ps
CPU time 6.37 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 205540 kb
Host smart-b80b5a14-54bc-46f4-a3c2-40b58f16c5ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581099432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1581099432
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.242893153
Short name T444
Test name
Test status
Simulation time 135748199 ps
CPU time 3.96 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 213720 kb
Host smart-dd7eb468-5108-4e11-a2f6-ed4c1881a60e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242893153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.242893153
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1611829215
Short name T201
Test name
Test status
Simulation time 4644012653 ps
CPU time 20.77 seconds
Started Aug 19 04:30:18 PM PDT 24
Finished Aug 19 04:30:39 PM PDT 24
Peak memory 213684 kb
Host smart-12326a39-c57f-45ff-8593-7b5d0a11f278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611829215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
611829215
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2003529281
Short name T100
Test name
Test status
Simulation time 106673197 ps
CPU time 3.51 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 219900 kb
Host smart-08a5861f-4844-4210-856d-7f8de9bc0e96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003529281 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2003529281
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2382644067
Short name T420
Test name
Test status
Simulation time 214763745 ps
CPU time 1.58 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 219048 kb
Host smart-3ce8689b-d7c4-40cd-82b4-6c882eabd90b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382644067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2382644067
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1018835201
Short name T340
Test name
Test status
Simulation time 9596638817 ps
CPU time 27.22 seconds
Started Aug 19 04:30:21 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 205384 kb
Host smart-6efd7bce-c4b7-4c4b-a8b1-07ee245b7a8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018835201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1018835201
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3081873894
Short name T480
Test name
Test status
Simulation time 1479628669 ps
CPU time 2.77 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 205404 kb
Host smart-ba874cc2-ae4a-4612-bd2c-9380d8194bb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081873894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3081873894
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.784869970
Short name T366
Test name
Test status
Simulation time 933053898 ps
CPU time 0.97 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 205128 kb
Host smart-77382057-e95e-470e-bb18-becfd0819e92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784869970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.784869970
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1536699860
Short name T123
Test name
Test status
Simulation time 1978529666 ps
CPU time 7.03 seconds
Started Aug 19 04:30:10 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 205536 kb
Host smart-ea942662-5224-4564-96c6-7422b6201a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536699860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1536699860
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2131880478
Short name T112
Test name
Test status
Simulation time 818065732 ps
CPU time 5.52 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 221788 kb
Host smart-c2e72384-d26f-45bb-b6c0-955fc0b348c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131880478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2131880478
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.162410119
Short name T422
Test name
Test status
Simulation time 2541079605 ps
CPU time 17.72 seconds
Started Aug 19 04:30:17 PM PDT 24
Finished Aug 19 04:30:35 PM PDT 24
Peak memory 213808 kb
Host smart-f80d2978-d617-418a-9fa7-a0ac91d6e228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162410119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.162410119
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1360841800
Short name T442
Test name
Test status
Simulation time 95048817 ps
CPU time 2.04 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 213744 kb
Host smart-697b129d-0f24-4aef-b59e-d63aa2b3769d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360841800 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1360841800
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.563577514
Short name T377
Test name
Test status
Simulation time 96088880 ps
CPU time 1.6 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 219132 kb
Host smart-42259e8e-1e59-4517-b47f-b35a215bd76d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563577514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.563577514
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.852837295
Short name T399
Test name
Test status
Simulation time 13930168096 ps
CPU time 35.12 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:42 PM PDT 24
Peak memory 205388 kb
Host smart-1f915547-3a37-4d74-b537-6ec49af010c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852837295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.852837295
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1438293245
Short name T433
Test name
Test status
Simulation time 1963207624 ps
CPU time 2.53 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 205384 kb
Host smart-a378dadb-44eb-42dc-a994-3ba21b51bf84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438293245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1438293245
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3765202521
Short name T473
Test name
Test status
Simulation time 284988955 ps
CPU time 1.4 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 205148 kb
Host smart-ed807ad2-5091-41e2-9e1c-f499accd475c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765202521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3765202521
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1308904233
Short name T158
Test name
Test status
Simulation time 294840892 ps
CPU time 4.56 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 205464 kb
Host smart-bf078d83-1ec6-479b-b4fc-c56e396066e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308904233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1308904233
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.585754195
Short name T467
Test name
Test status
Simulation time 627786502 ps
CPU time 3.57 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 213644 kb
Host smart-aa24d31a-c280-4850-a318-2ea403e2b21d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585754195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.585754195
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3392786408
Short name T398
Test name
Test status
Simulation time 1878276710 ps
CPU time 8.86 seconds
Started Aug 19 04:30:20 PM PDT 24
Finished Aug 19 04:30:29 PM PDT 24
Peak memory 213684 kb
Host smart-971a72e1-4594-47bb-bdb5-1913ef74f6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392786408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
392786408
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1615185033
Short name T172
Test name
Test status
Simulation time 468517827 ps
CPU time 3.25 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:13 PM PDT 24
Peak memory 221076 kb
Host smart-693033cf-8859-4969-b0c4-1b57a1be49c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615185033 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1615185033
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3112998251
Short name T478
Test name
Test status
Simulation time 1021123845 ps
CPU time 1.84 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 218648 kb
Host smart-ef822dbb-42ab-41c0-a477-849b06ccfbba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112998251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3112998251
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.250262527
Short name T354
Test name
Test status
Simulation time 15786172685 ps
CPU time 7.1 seconds
Started Aug 19 04:30:12 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 205464 kb
Host smart-45c784c6-a8e4-4843-8f2a-8a4a00144969
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250262527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.250262527
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1323682017
Short name T334
Test name
Test status
Simulation time 14929786903 ps
CPU time 21.06 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 205452 kb
Host smart-76b63d17-8d97-4cef-ae90-238773d12425
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323682017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1323682017
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1540109517
Short name T108
Test name
Test status
Simulation time 693917813 ps
CPU time 2.15 seconds
Started Aug 19 04:30:16 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 205140 kb
Host smart-b7401ee5-df4e-4d68-bfba-66e81fd48e7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540109517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1540109517
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3401230319
Short name T148
Test name
Test status
Simulation time 450403094 ps
CPU time 3.54 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 205624 kb
Host smart-302b6e4f-0874-4dd9-bb7c-c42ea284d587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401230319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3401230319
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.800777826
Short name T456
Test name
Test status
Simulation time 521507519 ps
CPU time 3.64 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 213568 kb
Host smart-cde232d3-88c8-4078-8a8e-57c342e8d24f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800777826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.800777826
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4094205283
Short name T205
Test name
Test status
Simulation time 1193773306 ps
CPU time 9.85 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:19 PM PDT 24
Peak memory 215732 kb
Host smart-e4f553cf-a69f-445b-98d4-aa6e49a4eb26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094205283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
094205283
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3349975076
Short name T155
Test name
Test status
Simulation time 8920082164 ps
CPU time 32.24 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:39 PM PDT 24
Peak memory 205612 kb
Host smart-6f254070-ef22-471a-b699-0c4d53d240d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349975076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3349975076
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.285990779
Short name T435
Test name
Test status
Simulation time 2968369425 ps
CPU time 26.35 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 205640 kb
Host smart-a4ed2722-0604-4581-ad01-0b7a758e9b13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285990779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.285990779
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3970039263
Short name T153
Test name
Test status
Simulation time 137386211 ps
CPU time 1.8 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 213584 kb
Host smart-fc3d7171-c962-4ffd-ac5e-63ce29505186
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970039263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3970039263
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.792449266
Short name T425
Test name
Test status
Simulation time 177006895 ps
CPU time 2.12 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 215844 kb
Host smart-2edd7571-11bc-4419-9a51-af84b6408f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792449266 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.792449266
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3440803779
Short name T141
Test name
Test status
Simulation time 87202469 ps
CPU time 2.19 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 218964 kb
Host smart-72c5ceac-8758-4e70-b2c2-2fa298694c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440803779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3440803779
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3889002685
Short name T470
Test name
Test status
Simulation time 32149061096 ps
CPU time 15.88 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 205520 kb
Host smart-84ef9510-e2ad-4edc-8775-48c0399d7378
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889002685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3889002685
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1569990707
Short name T367
Test name
Test status
Simulation time 189074659 ps
CPU time 0.69 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 205256 kb
Host smart-fcd0f55a-bce8-401a-8659-23f904f19a25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569990707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1569990707
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1250787068
Short name T405
Test name
Test status
Simulation time 2638583598 ps
CPU time 4.81 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:35 PM PDT 24
Peak memory 205476 kb
Host smart-3e96cbfb-369f-4dd5-bf3a-2eae45c4d506
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250787068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
250787068
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3194600956
Short name T441
Test name
Test status
Simulation time 558059803 ps
CPU time 0.79 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 205232 kb
Host smart-18d8f7f8-7788-4a16-af4c-8e69e717374c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194600956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3194600956
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.481664787
Short name T345
Test name
Test status
Simulation time 5222350117 ps
CPU time 3.71 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 205472 kb
Host smart-353b1f66-8721-450f-a619-61f5934d8930
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481664787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.481664787
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2855017597
Short name T431
Test name
Test status
Simulation time 209470950 ps
CPU time 0.99 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:52 PM PDT 24
Peak memory 205260 kb
Host smart-9ce4abe7-aba9-49fc-bb0b-09f0009cb1ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855017597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2855017597
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.550544283
Short name T464
Test name
Test status
Simulation time 402675868 ps
CPU time 1.64 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 205268 kb
Host smart-59702bff-c710-492d-9093-eaa8e30dfa8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550544283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.550544283
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3422019092
Short name T362
Test name
Test status
Simulation time 69138558 ps
CPU time 0.71 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:54 PM PDT 24
Peak memory 204880 kb
Host smart-49ac4282-bfd2-41a2-b7e3-90d279fc0e35
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422019092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3422019092
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3676792516
Short name T341
Test name
Test status
Simulation time 88134460 ps
CPU time 0.88 seconds
Started Aug 19 04:29:52 PM PDT 24
Finished Aug 19 04:29:53 PM PDT 24
Peak memory 205148 kb
Host smart-1aa375df-36e0-4ebe-ae6e-f6cf1c1b280d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676792516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3676792516
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2515258334
Short name T159
Test name
Test status
Simulation time 774118368 ps
CPU time 6.99 seconds
Started Aug 19 04:29:43 PM PDT 24
Finished Aug 19 04:29:50 PM PDT 24
Peak memory 205616 kb
Host smart-007d4eee-50b5-4454-878a-a4e5a5eedd75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515258334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2515258334
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2426196315
Short name T386
Test name
Test status
Simulation time 569108375 ps
CPU time 5.1 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 213732 kb
Host smart-1f49ca00-f691-412e-85db-0a30d1380942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426196315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2426196315
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.966642416
Short name T448
Test name
Test status
Simulation time 4164540945 ps
CPU time 18.66 seconds
Started Aug 19 04:29:40 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 221992 kb
Host smart-7e586c0a-e374-4221-8f6a-8943cc8e3f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966642416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.966642416
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1982404504
Short name T147
Test name
Test status
Simulation time 8908171121 ps
CPU time 79.73 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:31:14 PM PDT 24
Peak memory 213876 kb
Host smart-c8bc4455-6e6a-44f6-a1c3-9a6f57a5af50
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982404504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1982404504
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2121179540
Short name T115
Test name
Test status
Simulation time 20098601385 ps
CPU time 52.49 seconds
Started Aug 19 04:29:38 PM PDT 24
Finished Aug 19 04:30:40 PM PDT 24
Peak memory 213852 kb
Host smart-8be11a01-4d3e-482f-a223-cab8fdd1ac2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121179540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2121179540
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3299826710
Short name T430
Test name
Test status
Simulation time 363652886 ps
CPU time 1.63 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 213568 kb
Host smart-51a9ed6e-d32e-41e0-99d1-e90367905d1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299826710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3299826710
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2570355697
Short name T410
Test name
Test status
Simulation time 299987613 ps
CPU time 3.76 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 219324 kb
Host smart-f1775ebf-6eae-4070-a844-71b74381a832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570355697 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2570355697
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.274987709
Short name T385
Test name
Test status
Simulation time 79322925 ps
CPU time 1.53 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 218824 kb
Host smart-73391ef1-0089-4394-b638-97f5a9538059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274987709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.274987709
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1018952855
Short name T392
Test name
Test status
Simulation time 40413989921 ps
CPU time 109.54 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:31:53 PM PDT 24
Peak memory 205520 kb
Host smart-d3906aeb-2fd2-44ce-a0df-f10d25e3f88a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018952855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1018952855
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.755431357
Short name T391
Test name
Test status
Simulation time 10723163305 ps
CPU time 7.46 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 205428 kb
Host smart-3fb6b988-1022-4362-91f4-02ec4382374a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755431357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.755431357
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3407717160
Short name T128
Test name
Test status
Simulation time 10011646812 ps
CPU time 11.94 seconds
Started Aug 19 04:29:52 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 205564 kb
Host smart-c376efec-2c96-4acd-a067-d3c7ffa6baca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407717160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3407717160
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3029302333
Short name T401
Test name
Test status
Simulation time 3215026986 ps
CPU time 9.49 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 205308 kb
Host smart-15d23ab7-a56a-4336-bd9f-3ab823498616
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029302333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
029302333
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2669355246
Short name T463
Test name
Test status
Simulation time 178531360 ps
CPU time 0.9 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:29:49 PM PDT 24
Peak memory 205260 kb
Host smart-e7b0a8f6-5660-4b1d-a8bb-a60e6fa7d754
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669355246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2669355246
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.415677421
Short name T370
Test name
Test status
Simulation time 13439805517 ps
CPU time 20.86 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:14 PM PDT 24
Peak memory 205492 kb
Host smart-f3bba626-08c8-4ba6-9f0e-0ba2b0ff2313
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415677421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.415677421
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.698045427
Short name T351
Test name
Test status
Simulation time 455399768 ps
CPU time 1.77 seconds
Started Aug 19 04:29:58 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 205140 kb
Host smart-d90c3f3a-ad1e-44f5-a09f-045741fa1fd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698045427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.698045427
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.133331691
Short name T434
Test name
Test status
Simulation time 172817076 ps
CPU time 1.03 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 205264 kb
Host smart-2228bdad-9741-4f15-bcc4-abac454324f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133331691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.133331691
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1100156131
Short name T440
Test name
Test status
Simulation time 69449948 ps
CPU time 0.74 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:29:50 PM PDT 24
Peak memory 205084 kb
Host smart-e0d96f8f-df15-40fa-a7cf-0be461192acb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100156131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1100156131
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3339341391
Short name T438
Test name
Test status
Simulation time 79036870 ps
CPU time 0.71 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 205144 kb
Host smart-1cdba712-5641-4f50-8da9-01139bb7917e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339341391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3339341391
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2849772381
Short name T452
Test name
Test status
Simulation time 759823035 ps
CPU time 4.15 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 205392 kb
Host smart-0d3a5055-62e2-4990-bf2e-65be84eadf2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849772381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2849772381
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.813307612
Short name T96
Test name
Test status
Simulation time 10646024842 ps
CPU time 29.59 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:30:15 PM PDT 24
Peak memory 217436 kb
Host smart-6021b912-4a16-42ee-8f26-f57ed3ad3fc1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813307612 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.813307612
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2582805349
Short name T384
Test name
Test status
Simulation time 137659358 ps
CPU time 2.74 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 213736 kb
Host smart-9436ca56-1f67-4b49-b950-73ce0ad985eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582805349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2582805349
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3527454302
Short name T210
Test name
Test status
Simulation time 1798496429 ps
CPU time 19.94 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 221800 kb
Host smart-b2531e8e-7e71-47c3-80ae-8c816d6265ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527454302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3527454302
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.225552134
Short name T118
Test name
Test status
Simulation time 2311702965 ps
CPU time 27.7 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:32 PM PDT 24
Peak memory 205488 kb
Host smart-33e407fe-3c45-46f5-b694-208912faa16f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225552134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.225552134
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2361739322
Short name T124
Test name
Test status
Simulation time 3949588728 ps
CPU time 38.02 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 213820 kb
Host smart-f59e79dc-f910-4f82-8e14-a20974d13ba6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361739322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2361739322
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2400122807
Short name T116
Test name
Test status
Simulation time 137947066 ps
CPU time 1.76 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 213692 kb
Host smart-2a19e857-c09c-44d1-9c93-1bfc205080a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400122807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2400122807
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3600008704
Short name T347
Test name
Test status
Simulation time 228748549 ps
CPU time 1.96 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 213744 kb
Host smart-e184a816-8534-4f79-bb8f-0dd36cb1c3bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600008704 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3600008704
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1247814137
Short name T428
Test name
Test status
Simulation time 114290619 ps
CPU time 1.64 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 218268 kb
Host smart-9ee10dd3-bec1-4082-90c6-0618108f6f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247814137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1247814137
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1565490389
Short name T432
Test name
Test status
Simulation time 109599861031 ps
CPU time 159.29 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:32:34 PM PDT 24
Peak memory 205524 kb
Host smart-1a62dcee-76b8-459d-993c-87c69f28b192
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565490389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1565490389
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.954352647
Short name T380
Test name
Test status
Simulation time 4546746052 ps
CPU time 9.3 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 205336 kb
Host smart-1283af4b-1374-4075-b7f4-2f5bc9978fa7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954352647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.954352647
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.30132937
Short name T129
Test name
Test status
Simulation time 21092442362 ps
CPU time 51.05 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:30:45 PM PDT 24
Peak memory 205416 kb
Host smart-8e306a85-abcc-459a-ab52-c3e2928fb166
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30132937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_
hw_reset.30132937
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1034575202
Short name T363
Test name
Test status
Simulation time 4195307324 ps
CPU time 4.02 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 205388 kb
Host smart-0cc67bd8-e576-4a29-9e28-2bd9e04257e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034575202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
034575202
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.547606840
Short name T460
Test name
Test status
Simulation time 287234612 ps
CPU time 1.35 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 205248 kb
Host smart-eb882bc8-6ee6-468b-8f07-ad10ac33b134
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547606840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.547606840
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3820515756
Short name T349
Test name
Test status
Simulation time 7623317777 ps
CPU time 8.76 seconds
Started Aug 19 04:30:02 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 205396 kb
Host smart-f04964ad-79fc-4d18-9606-cbf8511becdd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820515756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3820515756
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.579345747
Short name T352
Test name
Test status
Simulation time 171441951 ps
CPU time 1.07 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 205252 kb
Host smart-4a52f394-e0e0-44b5-be00-926cd1032e4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579345747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.579345747
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1267496982
Short name T338
Test name
Test status
Simulation time 233839999 ps
CPU time 0.96 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 205252 kb
Host smart-2b4bfec0-8abc-4384-8c57-6a50eac88d3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267496982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
267496982
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2972516592
Short name T402
Test name
Test status
Simulation time 151552778 ps
CPU time 1.01 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 205036 kb
Host smart-ea53646c-5ad4-4e61-885d-19456a544109
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972516592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2972516592
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3088547930
Short name T407
Test name
Test status
Simulation time 193913313 ps
CPU time 0.78 seconds
Started Aug 19 04:30:12 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 205248 kb
Host smart-bc454bd8-bfd3-4a58-8a90-dc057b0b1949
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088547930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3088547930
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3647195444
Short name T121
Test name
Test status
Simulation time 303685174 ps
CPU time 3.57 seconds
Started Aug 19 04:30:02 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 205536 kb
Host smart-328e0426-4400-499d-9302-8428198959cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647195444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3647195444
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1015814062
Short name T418
Test name
Test status
Simulation time 11804472536 ps
CPU time 47.37 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 213824 kb
Host smart-42840f77-8993-4ebb-a368-8aced9ef008d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015814062 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1015814062
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4162217574
Short name T342
Test name
Test status
Simulation time 50224435 ps
CPU time 2.15 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 213620 kb
Host smart-27241f42-edd1-45d0-8bfb-0851f111f76d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162217574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4162217574
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2915265871
Short name T200
Test name
Test status
Simulation time 5628417457 ps
CPU time 23.27 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 221972 kb
Host smart-e6a4004d-6468-4f6f-9a28-c8420bc25146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915265871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2915265871
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3210817071
Short name T163
Test name
Test status
Simulation time 211494660 ps
CPU time 2.03 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 213672 kb
Host smart-8c479117-0e81-42f2-b0da-4ce4a640f766
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210817071 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3210817071
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2431946995
Short name T120
Test name
Test status
Simulation time 79845452 ps
CPU time 2.18 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 213808 kb
Host smart-ad92fee3-b208-48bb-96cf-f0116b76e95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431946995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2431946995
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2623616065
Short name T453
Test name
Test status
Simulation time 4996143186 ps
CPU time 2.74 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:40 PM PDT 24
Peak memory 205516 kb
Host smart-eb64a8ba-e00f-43c1-8d62-3b045700e559
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623616065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2623616065
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2161686157
Short name T447
Test name
Test status
Simulation time 2952131290 ps
CPU time 4.75 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 205468 kb
Host smart-1fc0e662-5048-46ae-bf7e-34e8d672111d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161686157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
161686157
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4203035159
Short name T404
Test name
Test status
Simulation time 348760940 ps
CPU time 1.58 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 205264 kb
Host smart-9a9a81a4-cf94-49f5-b2d9-bf3972d133b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203035159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4
203035159
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.624706698
Short name T157
Test name
Test status
Simulation time 735073618 ps
CPU time 6.28 seconds
Started Aug 19 04:30:02 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 205468 kb
Host smart-d3d9af35-f5dc-43c6-a23b-3be231a7ebed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624706698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.624706698
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.504423456
Short name T382
Test name
Test status
Simulation time 213507725 ps
CPU time 5.41 seconds
Started Aug 19 04:30:08 PM PDT 24
Finished Aug 19 04:30:13 PM PDT 24
Peak memory 213784 kb
Host smart-50320fc9-9547-4dbc-bcf8-972547f6a515
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504423456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.504423456
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2146195160
Short name T204
Test name
Test status
Simulation time 4258436049 ps
CPU time 21.95 seconds
Started Aug 19 04:29:42 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 213876 kb
Host smart-94893300-195a-4026-a044-9a3a7cdf64b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146195160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2146195160
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1290310568
Short name T164
Test name
Test status
Simulation time 430335263 ps
CPU time 2.82 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 217740 kb
Host smart-90600d7b-7e0e-4bfb-80c5-d9f5fcfb9cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290310568 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1290310568
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2478995121
Short name T357
Test name
Test status
Simulation time 521171328 ps
CPU time 2.25 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 219248 kb
Host smart-4f8e731e-6681-4eef-8dda-df7684d66218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478995121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2478995121
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2666818330
Short name T413
Test name
Test status
Simulation time 12585976983 ps
CPU time 17.65 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:21 PM PDT 24
Peak memory 205504 kb
Host smart-908afe0a-f5fb-453b-a217-2c71b120a28e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666818330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2666818330
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.264902177
Short name T415
Test name
Test status
Simulation time 5503336068 ps
CPU time 4.98 seconds
Started Aug 19 04:30:18 PM PDT 24
Finished Aug 19 04:30:24 PM PDT 24
Peak memory 205472 kb
Host smart-fc633cbe-4232-4a51-8e47-3f679d004b36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264902177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.264902177
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1872072587
Short name T400
Test name
Test status
Simulation time 266122791 ps
CPU time 0.89 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 205260 kb
Host smart-9cc1c3c9-7495-4918-8c7e-c6648aaa0818
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872072587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
872072587
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3162619520
Short name T449
Test name
Test status
Simulation time 1065092334 ps
CPU time 7.41 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 205484 kb
Host smart-63bce654-62c9-4b39-b762-5aeb87b08cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162619520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3162619520
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1581003832
Short name T429
Test name
Test status
Simulation time 88377906 ps
CPU time 2.88 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:14 PM PDT 24
Peak memory 213744 kb
Host smart-a9ef5c5e-875a-4597-a8de-1c2474117fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581003832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1581003832
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1622327065
Short name T389
Test name
Test status
Simulation time 220464603 ps
CPU time 3.64 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 221764 kb
Host smart-5fae3b22-0bef-4f44-8a6e-2d62b384f150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622327065 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1622327065
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3189554479
Short name T154
Test name
Test status
Simulation time 629646533 ps
CPU time 2.15 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 213764 kb
Host smart-4ac09bdf-1340-456b-bbef-05fff432531e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189554479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3189554479
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2817273421
Short name T379
Test name
Test status
Simulation time 3369460134 ps
CPU time 5.96 seconds
Started Aug 19 04:29:52 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 205304 kb
Host smart-5e48e34e-a006-4c5f-b2d6-4c44f031c8b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817273421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2817273421
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1759191139
Short name T451
Test name
Test status
Simulation time 3033857266 ps
CPU time 3.71 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 205480 kb
Host smart-2dd5847d-393c-4f35-b614-7b2e9057a15c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759191139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
759191139
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1249247181
Short name T350
Test name
Test status
Simulation time 326715250 ps
CPU time 0.81 seconds
Started Aug 19 04:30:10 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 205140 kb
Host smart-0bac02f9-878b-4c31-bd8f-e7e5cc13c3ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249247181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
249247181
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1274002888
Short name T150
Test name
Test status
Simulation time 3996833656 ps
CPU time 4.16 seconds
Started Aug 19 04:29:50 PM PDT 24
Finished Aug 19 04:29:54 PM PDT 24
Peak memory 205532 kb
Host smart-ed7c3217-190b-4aad-aad8-b2d2b95c8bf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274002888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1274002888
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2027120960
Short name T475
Test name
Test status
Simulation time 38756555920 ps
CPU time 121.8 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 213860 kb
Host smart-689bd916-2c35-4e12-957f-32968207d768
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027120960 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2027120960
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.445229354
Short name T469
Test name
Test status
Simulation time 169722333 ps
CPU time 2.47 seconds
Started Aug 19 04:30:25 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 213616 kb
Host smart-ecef92cc-38f0-409c-9641-a18f49af0bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445229354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.445229354
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.120529599
Short name T409
Test name
Test status
Simulation time 2826484411 ps
CPU time 11.65 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 220972 kb
Host smart-478241cd-3f92-49ff-aeaf-14a560071f24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120529599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.120529599
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.598020186
Short name T344
Test name
Test status
Simulation time 45210056 ps
CPU time 1.9 seconds
Started Aug 19 04:30:17 PM PDT 24
Finished Aug 19 04:30:19 PM PDT 24
Peak memory 213692 kb
Host smart-d642332a-ff2c-473e-b5f7-a55b5d6d5a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598020186 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.598020186
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1747665413
Short name T119
Test name
Test status
Simulation time 80598713 ps
CPU time 1.58 seconds
Started Aug 19 04:29:40 PM PDT 24
Finished Aug 19 04:29:42 PM PDT 24
Peak memory 218588 kb
Host smart-3c7d919e-26b8-49d8-860b-0b450247bbd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747665413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1747665413
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.618213985
Short name T443
Test name
Test status
Simulation time 53328453 ps
CPU time 0.75 seconds
Started Aug 19 04:29:52 PM PDT 24
Finished Aug 19 04:29:52 PM PDT 24
Peak memory 205252 kb
Host smart-20186012-8c97-4ab5-a348-e589d44185ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618213985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.618213985
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3243939570
Short name T346
Test name
Test status
Simulation time 7533333650 ps
CPU time 19.84 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 205420 kb
Host smart-af951ea9-1a53-4a75-a6b1-2a2e31f100d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243939570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
243939570
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1496424140
Short name T454
Test name
Test status
Simulation time 340024594 ps
CPU time 1.07 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 205144 kb
Host smart-308ffb3f-ca51-4598-8ddb-025cfa5251b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496424140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
496424140
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2662800979
Short name T396
Test name
Test status
Simulation time 1375210474 ps
CPU time 8.22 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 205584 kb
Host smart-a4f7efb1-c6de-4e59-9277-297ffcf13a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662800979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2662800979
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2531164111
Short name T99
Test name
Test status
Simulation time 3567851541 ps
CPU time 37.32 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:30:39 PM PDT 24
Peak memory 216356 kb
Host smart-eefb299f-d248-4b06-9345-1803572a90e1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531164111 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2531164111
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1659908750
Short name T361
Test name
Test status
Simulation time 60075227 ps
CPU time 2.86 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 213660 kb
Host smart-86491a66-64c7-4be8-99bf-472364d67d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659908750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1659908750
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.725544611
Short name T481
Test name
Test status
Simulation time 1281340527 ps
CPU time 16.16 seconds
Started Aug 19 04:29:58 PM PDT 24
Finished Aug 19 04:30:14 PM PDT 24
Peak memory 213688 kb
Host smart-d9347ba1-fac5-4f2c-bd09-4499040ab3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725544611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.725544611
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.346725203
Short name T477
Test name
Test status
Simulation time 154287064 ps
CPU time 2.03 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 217276 kb
Host smart-2528a31b-204a-44fe-a993-dc9aacc4db81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346725203 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.346725203
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1047696749
Short name T412
Test name
Test status
Simulation time 493787892 ps
CPU time 2.09 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 213580 kb
Host smart-f25a1457-ae87-478a-8f46-8563ad08ca47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047696749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1047696749
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3796202705
Short name T394
Test name
Test status
Simulation time 11212541206 ps
CPU time 33.7 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:34 PM PDT 24
Peak memory 205496 kb
Host smart-2c892cb6-d9b9-4a52-9a74-bef0be0aa824
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796202705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3796202705
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.913229737
Short name T393
Test name
Test status
Simulation time 5242942009 ps
CPU time 4.15 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 205400 kb
Host smart-ecc5debb-2ca9-4fd1-93f7-ecf557f4b75b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913229737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.913229737
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.610239805
Short name T107
Test name
Test status
Simulation time 171452281 ps
CPU time 1.15 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 205192 kb
Host smart-fc3eb466-e1dc-4aca-99fe-4671069a7fe6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610239805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.610239805
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3044604330
Short name T471
Test name
Test status
Simulation time 574036259 ps
CPU time 4.06 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 205556 kb
Host smart-14a28873-abb5-4f0c-a52f-a4e401d482e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044604330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3044604330
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3412049888
Short name T103
Test name
Test status
Simulation time 336817549 ps
CPU time 4.55 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:19 PM PDT 24
Peak memory 221948 kb
Host smart-9eaa570d-8b31-43f3-a793-1ef828d399ae
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412049888 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3412049888
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.516655815
Short name T125
Test name
Test status
Simulation time 384838203 ps
CPU time 2.67 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 213664 kb
Host smart-daff781d-231b-404e-8eca-7276d5f4cc14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516655815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.516655815
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2309283332
Short name T57
Test name
Test status
Simulation time 85384865 ps
CPU time 0.79 seconds
Started Aug 19 04:35:01 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 205004 kb
Host smart-1eab16f4-bc6b-4097-bebe-737fe2cfbf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309283332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2309283332
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3464107369
Short name T308
Test name
Test status
Simulation time 152685176 ps
CPU time 0.8 seconds
Started Aug 19 04:35:05 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 204984 kb
Host smart-fd2bf2c4-ec73-49fd-8d61-fa531156c093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464107369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3464107369
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1800009363
Short name T240
Test name
Test status
Simulation time 61109502022 ps
CPU time 81.79 seconds
Started Aug 19 04:34:53 PM PDT 24
Finished Aug 19 04:36:15 PM PDT 24
Peak memory 218800 kb
Host smart-0d0fc87d-9f01-42dd-b4c4-9a5eced2abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800009363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1800009363
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.407677732
Short name T242
Test name
Test status
Simulation time 4301986370 ps
CPU time 13.89 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 205512 kb
Host smart-199d474c-11f6-42fb-92a3-e9df8e0bdf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407677732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.407677732
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_buffered_enable.3324290824
Short name T293
Test name
Test status
Simulation time 615581795 ps
CPU time 2.35 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 226060 kb
Host smart-c9c4b4e0-21c6-4bfb-a24c-a57c8a88d3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324290824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.3324290824
Directory /workspace/0.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1563305190
Short name T286
Test name
Test status
Simulation time 200718684 ps
CPU time 1.16 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 205036 kb
Host smart-9ffc6ed8-7e0b-456e-84c6-d63f2f35f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563305190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1563305190
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.349343296
Short name T19
Test name
Test status
Simulation time 481912590 ps
CPU time 0.89 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 204964 kb
Host smart-46ff2624-dead-44de-bee1-ab47d19e7a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349343296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.349343296
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1539210702
Short name T302
Test name
Test status
Simulation time 559425928 ps
CPU time 0.87 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 205000 kb
Host smart-68151599-6b72-4aef-9492-50b65ee212ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539210702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1539210702
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.978745362
Short name T326
Test name
Test status
Simulation time 315709362 ps
CPU time 0.9 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 205004 kb
Host smart-01018e28-16ed-4a2e-8eee-b7bf56a59d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978745362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.978745362
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.4051655512
Short name T72
Test name
Test status
Simulation time 69635344 ps
CPU time 0.81 seconds
Started Aug 19 04:35:04 PM PDT 24
Finished Aug 19 04:35:05 PM PDT 24
Peak memory 215088 kb
Host smart-27e9b265-ad0f-4524-be72-f63496af016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051655512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4051655512
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1804240435
Short name T291
Test name
Test status
Simulation time 4251898387 ps
CPU time 12.23 seconds
Started Aug 19 04:34:54 PM PDT 24
Finished Aug 19 04:35:07 PM PDT 24
Peak memory 205520 kb
Host smart-16312c6b-6629-44dd-8666-7f6a97097580
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804240435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1804240435
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1587382575
Short name T252
Test name
Test status
Simulation time 126648751 ps
CPU time 0.73 seconds
Started Aug 19 04:35:03 PM PDT 24
Finished Aug 19 04:35:03 PM PDT 24
Peak memory 204976 kb
Host smart-dc961961-7179-43c4-a574-f4105186d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587382575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1587382575
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3236207869
Short name T243
Test name
Test status
Simulation time 159708949 ps
CPU time 0.76 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 205028 kb
Host smart-9fa2e5e7-970c-4382-8625-80a3660ee6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236207869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3236207869
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2156427416
Short name T330
Test name
Test status
Simulation time 120272830 ps
CPU time 0.8 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 205000 kb
Host smart-b06c9ef8-9164-4003-9747-1c95a756f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156427416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2156427416
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.755139463
Short name T262
Test name
Test status
Simulation time 616521699 ps
CPU time 1.72 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:15 PM PDT 24
Peak memory 205028 kb
Host smart-9af6b350-c11c-4b9b-a284-180227baf70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755139463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.755139463
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2160131620
Short name T219
Test name
Test status
Simulation time 413220770 ps
CPU time 1.44 seconds
Started Aug 19 04:35:08 PM PDT 24
Finished Aug 19 04:35:09 PM PDT 24
Peak memory 204932 kb
Host smart-7ae3375b-98fe-4d3b-9b60-44ad0b37d6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160131620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2160131620
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1998699228
Short name T189
Test name
Test status
Simulation time 148871952 ps
CPU time 1.14 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 205020 kb
Host smart-813a223d-1fb7-43ea-b399-fc5f8408f059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998699228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1998699228
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2896256357
Short name T324
Test name
Test status
Simulation time 206793539 ps
CPU time 0.8 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 204916 kb
Host smart-c137bab1-e0ab-4287-b800-2f763a317361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896256357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2896256357
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3618087569
Short name T28
Test name
Test status
Simulation time 711374045 ps
CPU time 2.62 seconds
Started Aug 19 04:35:06 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 204992 kb
Host smart-35430ac7-8616-4ca8-be83-c0ae47b6e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618087569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3618087569
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.554496392
Short name T318
Test name
Test status
Simulation time 437133581 ps
CPU time 1.44 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 213236 kb
Host smart-8f493dc5-90ea-45a4-a66e-1dddfe1e39b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554496392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.554496392
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.163510453
Short name T282
Test name
Test status
Simulation time 189967344 ps
CPU time 1.26 seconds
Started Aug 19 04:35:05 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 205028 kb
Host smart-e0107fda-9ec8-4909-ab35-fffd21cf8b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163510453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.163510453
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.528378838
Short name T193
Test name
Test status
Simulation time 2176962522 ps
CPU time 2.82 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 205500 kb
Host smart-5e463d1e-d53c-4802-8680-9bb7d92d2bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528378838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.528378838
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1707104945
Short name T36
Test name
Test status
Simulation time 566996849 ps
CPU time 1.35 seconds
Started Aug 19 04:35:05 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 229348 kb
Host smart-b37a9a5b-00b4-4e7c-8c6f-8c821b10db40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707104945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1707104945
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3847273771
Short name T169
Test name
Test status
Simulation time 1047884145 ps
CPU time 1.82 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 204972 kb
Host smart-a12a2096-1ce4-4bd5-af75-38c07fa1e2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847273771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3847273771
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.962986748
Short name T5
Test name
Test status
Simulation time 2385314756 ps
CPU time 7.55 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:35:05 PM PDT 24
Peak memory 205276 kb
Host smart-9e4dea23-7fd0-4e84-8e9a-7d4d0ded7247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962986748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.962986748
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2219200469
Short name T56
Test name
Test status
Simulation time 198740086 ps
CPU time 1.23 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 205032 kb
Host smart-fcebea16-d59e-4fd4-bcfc-87d345dca7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219200469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2219200469
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3886953576
Short name T247
Test name
Test status
Simulation time 64314015 ps
CPU time 0.77 seconds
Started Aug 19 04:35:09 PM PDT 24
Finished Aug 19 04:35:10 PM PDT 24
Peak memory 205036 kb
Host smart-65027c64-28ad-4f93-b8a9-1b54c49b954b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886953576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3886953576
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.666213890
Short name T214
Test name
Test status
Simulation time 31838582675 ps
CPU time 86.73 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:36:24 PM PDT 24
Peak memory 213700 kb
Host smart-a2b45e86-e094-4ab1-86f9-f1f36e13ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666213890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.666213890
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.833798757
Short name T309
Test name
Test status
Simulation time 2585066921 ps
CPU time 8.41 seconds
Started Aug 19 04:35:12 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 213736 kb
Host smart-2b69d9ce-d0e3-4702-a20f-736aecbb523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833798757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.833798757
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3519515948
Short name T38
Test name
Test status
Simulation time 187303831 ps
CPU time 0.81 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 205028 kb
Host smart-ee4efa55-37c3-49ef-8ca5-4130916f6cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519515948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3519515948
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.635522696
Short name T248
Test name
Test status
Simulation time 61169412 ps
CPU time 0.74 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 205008 kb
Host smart-6961659f-fa55-4953-b56b-98ba9e9be018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635522696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.635522696
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1920078186
Short name T258
Test name
Test status
Simulation time 95757354 ps
CPU time 0.85 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 215084 kb
Host smart-99f10abd-74b4-4c99-8e41-035c18a3251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920078186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1920078186
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2605889015
Short name T238
Test name
Test status
Simulation time 8427255895 ps
CPU time 14.42 seconds
Started Aug 19 04:35:05 PM PDT 24
Finished Aug 19 04:35:19 PM PDT 24
Peak memory 213608 kb
Host smart-02a95d92-4163-46b2-ba01-a2d6cfb4f131
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605889015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2605889015
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3147518305
Short name T59
Test name
Test status
Simulation time 155411108 ps
CPU time 0.84 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 204980 kb
Host smart-11dbb32f-8891-45ef-966f-e85cbeb08c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147518305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3147518305
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3014511111
Short name T259
Test name
Test status
Simulation time 230747058 ps
CPU time 0.81 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 205032 kb
Host smart-9524a175-e794-4b37-b74e-55c79b1d4268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014511111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3014511111
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3772298387
Short name T251
Test name
Test status
Simulation time 137744717 ps
CPU time 0.81 seconds
Started Aug 19 04:35:00 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 204980 kb
Host smart-a6efbede-0b8a-4621-9787-636c9b8672dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772298387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3772298387
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1566862313
Short name T264
Test name
Test status
Simulation time 133248092 ps
CPU time 1.04 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 204968 kb
Host smart-3b6af59f-d1c4-40af-aa5c-bb812e6e7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566862313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1566862313
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1939958204
Short name T253
Test name
Test status
Simulation time 1041093267 ps
CPU time 3.38 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 204904 kb
Host smart-e07bbebf-1836-41aa-9c9d-3b5cfdcc5b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939958204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1939958204
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3521217508
Short name T139
Test name
Test status
Simulation time 701016277 ps
CPU time 1.28 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 205024 kb
Host smart-ce009d4e-519b-434d-b019-5c74e4499d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521217508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3521217508
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3497060658
Short name T317
Test name
Test status
Simulation time 612766051 ps
CPU time 2.49 seconds
Started Aug 19 04:35:11 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 205008 kb
Host smart-ee86beba-121f-4c84-a919-99dfc60afd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497060658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3497060658
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1308900934
Short name T192
Test name
Test status
Simulation time 293348230 ps
CPU time 1.51 seconds
Started Aug 19 04:35:12 PM PDT 24
Finished Aug 19 04:35:14 PM PDT 24
Peak memory 205016 kb
Host smart-5de1c75b-f7f5-4170-b378-1b09efc9747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308900934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1308900934
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.821258204
Short name T227
Test name
Test status
Simulation time 334556639 ps
CPU time 0.92 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 205036 kb
Host smart-5ca3cae2-67a9-4cd8-9219-dd701ed299f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821258204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.821258204
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.801317889
Short name T32
Test name
Test status
Simulation time 116201528 ps
CPU time 0.93 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 213256 kb
Host smart-32a70199-b227-4cd0-ae74-6efc3c3ec9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801317889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.801317889
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1390032624
Short name T261
Test name
Test status
Simulation time 1173495726 ps
CPU time 2.39 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:18 PM PDT 24
Peak memory 205020 kb
Host smart-c83cb56c-14c9-4b9e-a83f-faceee8eaef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390032624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1390032624
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2145730055
Short name T42
Test name
Test status
Simulation time 203812398 ps
CPU time 0.88 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 213248 kb
Host smart-ee53e7f0-30b1-43e3-ac4d-b9467d800b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145730055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2145730055
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.334865103
Short name T176
Test name
Test status
Simulation time 946261972 ps
CPU time 3.19 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 205272 kb
Host smart-9b4c84a2-b974-41af-ba9e-1306f2e611f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334865103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.334865103
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.783270996
Short name T244
Test name
Test status
Simulation time 7748248524 ps
CPU time 12.3 seconds
Started Aug 19 04:35:11 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 213600 kb
Host smart-81b3508a-120f-420e-aed6-e302b329b981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783270996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.783270996
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.210254795
Short name T215
Test name
Test status
Simulation time 496942366 ps
CPU time 1.57 seconds
Started Aug 19 04:35:04 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 205000 kb
Host smart-af286807-7b8a-433d-ac7a-8a155992a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210254795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.210254795
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3931972361
Short name T64
Test name
Test status
Simulation time 271591689 ps
CPU time 1.15 seconds
Started Aug 19 04:35:05 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 213352 kb
Host smart-0a579b63-8761-47f6-93d0-b56c59f361c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931972361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3931972361
Directory /workspace/1.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3041509461
Short name T14
Test name
Test status
Simulation time 3398234943 ps
CPU time 9.04 seconds
Started Aug 19 04:35:02 PM PDT 24
Finished Aug 19 04:35:11 PM PDT 24
Peak memory 213464 kb
Host smart-c41f8cd1-9f9c-401f-a785-21a89671fcb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041509461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3041509461
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.392001869
Short name T229
Test name
Test status
Simulation time 139213735 ps
CPU time 0.86 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 205032 kb
Host smart-149e0ac0-f65f-4443-a1b1-68c38cb6024a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392001869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.392001869
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1434175171
Short name T279
Test name
Test status
Simulation time 7984721466 ps
CPU time 6.69 seconds
Started Aug 19 04:35:08 PM PDT 24
Finished Aug 19 04:35:14 PM PDT 24
Peak memory 213684 kb
Host smart-e203eb82-0e35-45cf-8ecb-de8479f24606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434175171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1434175171
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3436694340
Short name T8
Test name
Test status
Simulation time 928466423 ps
CPU time 2.11 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 205668 kb
Host smart-15c5b970-e327-4c81-b227-7e3c929597f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436694340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3436694340
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.99756488
Short name T299
Test name
Test status
Simulation time 5507271331 ps
CPU time 6.91 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 213640 kb
Host smart-6a469a68-3e25-4606-ab66-25512efbbebb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99756488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl
_access.99756488
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3125259030
Short name T257
Test name
Test status
Simulation time 9926889427 ps
CPU time 13.48 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 213740 kb
Host smart-f51b0499-589f-41e1-b314-42909a2af0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125259030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3125259030
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3432306527
Short name T24
Test name
Test status
Simulation time 4483973271 ps
CPU time 7.49 seconds
Started Aug 19 04:35:13 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 205340 kb
Host smart-68b3712d-3d96-4675-8b68-0b840be54f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432306527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3432306527
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3943783263
Short name T31
Test name
Test status
Simulation time 59958029886 ps
CPU time 22.09 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 213668 kb
Host smart-a9f08167-03cc-4404-8530-e9f251f15ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943783263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3943783263
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1296016366
Short name T97
Test name
Test status
Simulation time 2664566402 ps
CPU time 4.92 seconds
Started Aug 19 04:35:17 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 213640 kb
Host smart-29f47290-ec86-4637-b453-da6d6a41b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296016366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1296016366
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2063002034
Short name T195
Test name
Test status
Simulation time 2614371621 ps
CPU time 1.98 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205524 kb
Host smart-8b2d8006-f078-4082-a913-39b996334ef0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063002034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2063002034
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2259557008
Short name T84
Test name
Test status
Simulation time 5421043685 ps
CPU time 9.17 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 213616 kb
Host smart-22000b09-0ce9-4896-9430-92821c0c50bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259557008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2259557008
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1013981859
Short name T228
Test name
Test status
Simulation time 34812416 ps
CPU time 0.75 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 205000 kb
Host smart-aebba11c-25eb-4ffa-b604-45631529f030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013981859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1013981859
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1674265951
Short name T295
Test name
Test status
Simulation time 880503770 ps
CPU time 3.36 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 213632 kb
Host smart-8279c6f9-b526-45f4-b698-b9d7d2c78238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674265951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1674265951
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3390136417
Short name T288
Test name
Test status
Simulation time 3270835839 ps
CPU time 2.68 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:18 PM PDT 24
Peak memory 205428 kb
Host smart-971ef864-b604-41ee-8d8a-d81cb0f4ce4b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390136417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3390136417
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4088138912
Short name T167
Test name
Test status
Simulation time 9188089350 ps
CPU time 25.25 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 213668 kb
Host smart-ba02df66-58a7-40a8-9bdc-4da58d6b6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088138912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4088138912
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3316372953
Short name T301
Test name
Test status
Simulation time 2126375751 ps
CPU time 4.25 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 213420 kb
Host smart-92d69e59-1986-4b45-a214-9b2e1412740a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316372953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3316372953
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4181768309
Short name T239
Test name
Test status
Simulation time 192200504 ps
CPU time 0.83 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 204972 kb
Host smart-4a7578dc-1549-4783-b718-9db789910099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181768309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4181768309
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3991205137
Short name T168
Test name
Test status
Simulation time 49529063996 ps
CPU time 38.7 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:55 PM PDT 24
Peak memory 213700 kb
Host smart-89db85d0-fa3d-47be-9241-286cbe1f4b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991205137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3991205137
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2719108589
Short name T131
Test name
Test status
Simulation time 11434405782 ps
CPU time 20.28 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:50 PM PDT 24
Peak memory 213604 kb
Host smart-fac4488e-f494-4f44-b4fa-09685a54ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719108589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2719108589
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.119388423
Short name T305
Test name
Test status
Simulation time 1606539831 ps
CPU time 3.44 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:41 PM PDT 24
Peak memory 213548 kb
Host smart-615f6282-2a51-4643-ab67-960b91c91056
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119388423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.119388423
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1687401964
Short name T138
Test name
Test status
Simulation time 4513093325 ps
CPU time 7.28 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 205516 kb
Host smart-3b3b4db9-36b2-4d61-9d9b-5186e75dd596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687401964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1687401964
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2811872351
Short name T9
Test name
Test status
Simulation time 6369087286 ps
CPU time 5.29 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:29 PM PDT 24
Peak memory 213508 kb
Host smart-8b13071f-c6ac-4ea7-b071-013a7a7bd22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811872351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2811872351
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.169825264
Short name T234
Test name
Test status
Simulation time 64353702 ps
CPU time 0.74 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:29 PM PDT 24
Peak memory 205028 kb
Host smart-43f8cbb6-cc33-48f7-8fe5-ac52e874e5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169825264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.169825264
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3408159214
Short name T246
Test name
Test status
Simulation time 19210394086 ps
CPU time 26.93 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:57 PM PDT 24
Peak memory 213612 kb
Host smart-26ce12bb-f7aa-4cbc-bde1-1bfbb3a35a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408159214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3408159214
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3548211458
Short name T109
Test name
Test status
Simulation time 1055575892 ps
CPU time 3.23 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 205396 kb
Host smart-a9fe88a4-46eb-4b88-8892-74f8838f8fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548211458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3548211458
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2927653377
Short name T94
Test name
Test status
Simulation time 8018237388 ps
CPU time 13.02 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 205516 kb
Host smart-53c3907c-0334-4bd9-bff4-057857b2eb44
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927653377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2927653377
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2703818984
Short name T268
Test name
Test status
Simulation time 3678914815 ps
CPU time 11.9 seconds
Started Aug 19 04:35:33 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 205460 kb
Host smart-1a791ecb-4a97-4249-98a2-bc560b3d5158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703818984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2703818984
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3142065329
Short name T180
Test name
Test status
Simulation time 2799875439 ps
CPU time 3.2 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 205288 kb
Host smart-45b1ce5f-49ed-45d7-82a7-7f49c940869f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142065329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3142065329
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.643578929
Short name T79
Test name
Test status
Simulation time 78690961 ps
CPU time 0.72 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 204884 kb
Host smart-c54bd50c-3429-4ded-b351-a72a20e138b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643578929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.643578929
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2851762940
Short name T29
Test name
Test status
Simulation time 18473465310 ps
CPU time 27.27 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 213664 kb
Host smart-3e68361b-b46c-4c72-9a57-e2f4d776e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851762940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2851762940
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1151859152
Short name T16
Test name
Test status
Simulation time 9321872752 ps
CPU time 28.11 seconds
Started Aug 19 04:35:13 PM PDT 24
Finished Aug 19 04:35:41 PM PDT 24
Peak memory 205332 kb
Host smart-c48765ab-825d-4b27-ab27-268dd9945132
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151859152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1151859152
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1104562665
Short name T271
Test name
Test status
Simulation time 5582450677 ps
CPU time 8.76 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 205436 kb
Host smart-16f075d4-ec7b-4aa6-b332-653495077c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104562665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1104562665
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.374795005
Short name T86
Test name
Test status
Simulation time 1253396290 ps
CPU time 2.39 seconds
Started Aug 19 04:35:36 PM PDT 24
Finished Aug 19 04:35:38 PM PDT 24
Peak memory 213456 kb
Host smart-ce86fe2a-617a-42af-8181-6f186d198a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374795005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.374795005
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2162196396
Short name T34
Test name
Test status
Simulation time 37912792 ps
CPU time 0.76 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205040 kb
Host smart-9dbdf406-288c-42d0-8d49-baecbfdefd04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162196396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2162196396
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3507340618
Short name T181
Test name
Test status
Simulation time 10305463211 ps
CPU time 11.89 seconds
Started Aug 19 04:35:36 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 213668 kb
Host smart-08485266-d2d9-4c97-b15a-e0658cc3a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507340618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3507340618
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.4272237232
Short name T266
Test name
Test status
Simulation time 3050145416 ps
CPU time 2.88 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:19 PM PDT 24
Peak memory 205600 kb
Host smart-dcaba0bd-11b5-4c94-b08f-2298138d1f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272237232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.4272237232
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2559759961
Short name T310
Test name
Test status
Simulation time 12175861143 ps
CPU time 33.33 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:58 PM PDT 24
Peak memory 213536 kb
Host smart-f228a195-8dc7-4fa1-9537-cfc8be8d9bf8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559759961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2559759961
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1564063321
Short name T235
Test name
Test status
Simulation time 3345073919 ps
CPU time 3.48 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 205484 kb
Host smart-85f2b2bf-0a75-4889-bf8a-d1f1253a5c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564063321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1564063321
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.3095454736
Short name T182
Test name
Test status
Simulation time 5954590798 ps
CPU time 10.01 seconds
Started Aug 19 04:35:36 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 205316 kb
Host smart-23b6982f-767a-469d-b371-1b43a6c5313d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095454736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3095454736
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1525036521
Short name T276
Test name
Test status
Simulation time 152428928 ps
CPU time 0.79 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 205080 kb
Host smart-30ccadb6-0b6f-4d69-b40f-1ec7d6286180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525036521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1525036521
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.4080137261
Short name T78
Test name
Test status
Simulation time 5298907928 ps
CPU time 7.68 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 213604 kb
Host smart-519d4488-38a4-4fdf-a678-a8bb3bacc9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080137261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.4080137261
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1035301052
Short name T306
Test name
Test status
Simulation time 11805910974 ps
CPU time 8.9 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 214748 kb
Host smart-25bc2891-8c10-4f62-bc4f-0d0ca27f5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035301052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1035301052
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3828001710
Short name T224
Test name
Test status
Simulation time 2210610032 ps
CPU time 2.61 seconds
Started Aug 19 04:35:27 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 205412 kb
Host smart-17ff0f6e-c02b-4e0c-9e97-901bb19eb4f2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828001710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3828001710
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2079429275
Short name T272
Test name
Test status
Simulation time 2590030680 ps
CPU time 7.43 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 205468 kb
Host smart-59c5a11f-09fa-4114-8489-f49774989bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079429275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2079429275
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2548408398
Short name T285
Test name
Test status
Simulation time 32306040 ps
CPU time 0.76 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 205052 kb
Host smart-ae1faadf-5151-4ed6-80f9-179bc80cb9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548408398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2548408398
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1315751589
Short name T269
Test name
Test status
Simulation time 2437286388 ps
CPU time 7.57 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 213676 kb
Host smart-9e464e4c-4d70-4ad2-9421-4f2544f72ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315751589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1315751589
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.4042542232
Short name T273
Test name
Test status
Simulation time 4533765521 ps
CPU time 7.41 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:38 PM PDT 24
Peak memory 213648 kb
Host smart-79244c73-d04b-40b2-be3f-25a2fa80b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042542232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4042542232
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.321125972
Short name T254
Test name
Test status
Simulation time 1592353681 ps
CPU time 2.03 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 205400 kb
Host smart-3d6b6caa-5f18-44f0-a22e-5d630d4db33e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321125972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.321125972
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2682374070
Short name T137
Test name
Test status
Simulation time 4284343371 ps
CPU time 4.96 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 205520 kb
Host smart-d9657b73-99c4-4b62-9373-48dc6eff4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682374070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2682374070
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1401388765
Short name T194
Test name
Test status
Simulation time 5805940858 ps
CPU time 11.94 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 213476 kb
Host smart-9b227cb2-9265-47f4-a0bb-2ddd566fe28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401388765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1401388765
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1417585967
Short name T77
Test name
Test status
Simulation time 53806072 ps
CPU time 0.81 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 205008 kb
Host smart-da721f69-8b05-4442-a36f-05f0d943230d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417585967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1417585967
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3037161481
Short name T300
Test name
Test status
Simulation time 9123544912 ps
CPU time 7.75 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 213696 kb
Host smart-ddda12af-3515-4265-8522-571f7c2fcfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037161481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3037161481
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3070981366
Short name T250
Test name
Test status
Simulation time 2465259584 ps
CPU time 2.24 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 205536 kb
Host smart-d7869bd3-384b-47fc-b14c-29ad477099bf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070981366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3070981366
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3482726399
Short name T80
Test name
Test status
Simulation time 2556270590 ps
CPU time 7.31 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 205424 kb
Host smart-de190ad3-8fb9-405e-894c-beffc50ac0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482726399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3482726399
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1501449892
Short name T325
Test name
Test status
Simulation time 2651828227 ps
CPU time 6.66 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 205312 kb
Host smart-6fa7a9c9-8d94-4f31-806d-5b4b67a7c04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501449892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1501449892
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2330538392
Short name T329
Test name
Test status
Simulation time 52875882 ps
CPU time 0.7 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 205004 kb
Host smart-4c281837-718a-420a-b7e2-5f3ff265cb2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330538392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2330538392
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_buffered_enable.646215726
Short name T69
Test name
Test status
Simulation time 117625934 ps
CPU time 1.06 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:15 PM PDT 24
Peak memory 225772 kb
Host smart-62725335-f261-4df1-b1a6-ca1bc5eb8ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646215726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.646215726
Directory /workspace/2.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3530434497
Short name T218
Test name
Test status
Simulation time 6095250136 ps
CPU time 17.65 seconds
Started Aug 19 04:35:10 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 213680 kb
Host smart-dbfe6a4e-4346-46ba-828b-f1c291ac5e48
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530434497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3530434497
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1941181221
Short name T312
Test name
Test status
Simulation time 585567138 ps
CPU time 2.3 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205024 kb
Host smart-0d186e95-39c5-4ae6-9803-aa6dad7bc32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941181221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1941181221
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3703751652
Short name T245
Test name
Test status
Simulation time 94455830 ps
CPU time 0.94 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 204904 kb
Host smart-ce5c5b48-2031-40b2-9b98-9ce1686416a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703751652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3703751652
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4209496493
Short name T166
Test name
Test status
Simulation time 7312138047 ps
CPU time 8.85 seconds
Started Aug 19 04:35:18 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 205496 kb
Host smart-b1a274ef-4044-46ed-a9f8-01e47412a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209496493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4209496493
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.4029567132
Short name T37
Test name
Test status
Simulation time 1251181700 ps
CPU time 4.72 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:35:03 PM PDT 24
Peak memory 229368 kb
Host smart-47caea42-1469-43d5-adb3-3ac70cf36edb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029567132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4029567132
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3108121695
Short name T292
Test name
Test status
Simulation time 1277473154 ps
CPU time 4.37 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:35:03 PM PDT 24
Peak memory 213424 kb
Host smart-a2914798-9d7f-47de-88ca-27f4176fe50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108121695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3108121695
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.401640850
Short name T102
Test name
Test status
Simulation time 2952690362 ps
CPU time 73.17 seconds
Started Aug 19 04:35:01 PM PDT 24
Finished Aug 19 04:36:14 PM PDT 24
Peak memory 218296 kb
Host smart-92210587-9f01-44b7-ae33-86c508d6c32c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401640850 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.401640850
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2183035470
Short name T328
Test name
Test status
Simulation time 53773253 ps
CPU time 0.73 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 205028 kb
Host smart-c20c69d1-3c4d-49f5-ac21-e540c83b9b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183035470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2183035470
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2888940188
Short name T320
Test name
Test status
Simulation time 166890636 ps
CPU time 0.74 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 205040 kb
Host smart-7840ea38-0d43-4551-a824-ba75f69f3d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888940188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2888940188
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3929981170
Short name T48
Test name
Test status
Simulation time 5914101728 ps
CPU time 2.72 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 213456 kb
Host smart-74019c96-4fa9-4dd5-826a-ea6d4b2ddcd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929981170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3929981170
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.185712587
Short name T92
Test name
Test status
Simulation time 129772677 ps
CPU time 1.01 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 204992 kb
Host smart-07cf7aa6-10d4-4bcb-9eac-a1272551ee4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185712587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.185712587
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.435190162
Short name T17
Test name
Test status
Simulation time 1548587545 ps
CPU time 4.43 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 213420 kb
Host smart-a22d92a3-d7a9-4db7-b024-65fa9be612b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435190162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.435190162
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3447274386
Short name T87
Test name
Test status
Simulation time 142148338 ps
CPU time 0.88 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 205004 kb
Host smart-8116227f-593b-4591-8f01-425727b6aa2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447274386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3447274386
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.647219978
Short name T27
Test name
Test status
Simulation time 5664442631 ps
CPU time 7.31 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 205336 kb
Host smart-2fd64e3d-e010-43be-bc22-5c03b489f82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647219978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.647219978
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2412623411
Short name T231
Test name
Test status
Simulation time 51881174 ps
CPU time 0.82 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 204956 kb
Host smart-92ebfe9c-6543-4751-9f25-0627edb4caed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412623411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2412623411
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1770377539
Short name T198
Test name
Test status
Simulation time 2891220942 ps
CPU time 3.19 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 213512 kb
Host smart-6d6fd555-12a0-457e-a409-99587dc13df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770377539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1770377539
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1845972163
Short name T170
Test name
Test status
Simulation time 50345014 ps
CPU time 0.68 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:29 PM PDT 24
Peak memory 205032 kb
Host smart-f83cf44f-1184-4634-98ba-925bd305b43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845972163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1845972163
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.901131086
Short name T297
Test name
Test status
Simulation time 65685888 ps
CPU time 0.71 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 204996 kb
Host smart-874d62dd-a204-42a4-b181-b81171f43856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901131086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.901131086
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.306474493
Short name T191
Test name
Test status
Simulation time 3838643027 ps
CPU time 6.72 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205256 kb
Host smart-5519eba4-ded8-4868-8595-4a76b4b27bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306474493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.306474493
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2998570258
Short name T283
Test name
Test status
Simulation time 80884677 ps
CPU time 0.79 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 205072 kb
Host smart-7c7f8fe3-8757-4e3c-a954-97fbd604787d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998570258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2998570258
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3200179531
Short name T132
Test name
Test status
Simulation time 39527800 ps
CPU time 0.81 seconds
Started Aug 19 04:35:33 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 204956 kb
Host smart-6d447fa8-3991-4830-b6e4-65bdcfaae0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200179531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3200179531
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3627375593
Short name T20
Test name
Test status
Simulation time 2934199300 ps
CPU time 2.99 seconds
Started Aug 19 04:35:39 PM PDT 24
Finished Aug 19 04:35:42 PM PDT 24
Peak memory 205256 kb
Host smart-f6d147c0-fec4-46b0-bb20-5dede950115f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627375593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3627375593
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2471878307
Short name T73
Test name
Test status
Simulation time 67179008 ps
CPU time 0.83 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 205032 kb
Host smart-463f9c4d-c0f6-476e-be03-271c08d468cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471878307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2471878307
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2617922644
Short name T22
Test name
Test status
Simulation time 4768698487 ps
CPU time 3.24 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 213556 kb
Host smart-a0925fd8-2000-4c22-bcad-0e5492fa58ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617922644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2617922644
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1473743038
Short name T290
Test name
Test status
Simulation time 165655542 ps
CPU time 0.75 seconds
Started Aug 19 04:35:13 PM PDT 24
Finished Aug 19 04:35:14 PM PDT 24
Peak memory 205000 kb
Host smart-6fa79b8d-6233-4b59-b532-e1d04b92020f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473743038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1473743038
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.987014749
Short name T322
Test name
Test status
Simulation time 6380567212 ps
CPU time 18.47 seconds
Started Aug 19 04:35:00 PM PDT 24
Finished Aug 19 04:35:19 PM PDT 24
Peak memory 213624 kb
Host smart-5956cde9-fd46-4b59-a687-415b35956078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987014749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.987014749
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3272814006
Short name T265
Test name
Test status
Simulation time 1208654045 ps
CPU time 3.75 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:11 PM PDT 24
Peak memory 205388 kb
Host smart-82f5dc06-335d-4c27-869d-3896e2a05ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272814006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3272814006
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_buffered_enable.3626717158
Short name T255
Test name
Test status
Simulation time 685029879 ps
CPU time 1.2 seconds
Started Aug 19 04:35:12 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 225876 kb
Host smart-538cfa18-9e08-4e36-ac35-4c1dc5d76637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626717158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3626717158
Directory /workspace/3.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2716538487
Short name T65
Test name
Test status
Simulation time 1249527251 ps
CPU time 4.53 seconds
Started Aug 19 04:35:08 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 205424 kb
Host smart-da4546c5-f52d-4fb1-9f0e-732d1f915b84
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716538487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2716538487
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.3871409539
Short name T46
Test name
Test status
Simulation time 545645216 ps
CPU time 1.18 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 205040 kb
Host smart-2b3da04e-eea7-4ac8-9c51-8e627075763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871409539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3871409539
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.981241405
Short name T110
Test name
Test status
Simulation time 305711308 ps
CPU time 0.73 seconds
Started Aug 19 04:35:01 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 205016 kb
Host smart-330c50c3-b48f-4ad4-9bfc-e740f9095f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981241405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.981241405
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.749380298
Short name T165
Test name
Test status
Simulation time 2626758417 ps
CPU time 4.49 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:19 PM PDT 24
Peak memory 205432 kb
Host smart-e4c746ac-b0fb-4318-bcdb-1b145da6995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749380298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.749380298
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2545967794
Short name T74
Test name
Test status
Simulation time 601661919 ps
CPU time 1.17 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 229448 kb
Host smart-fb4c85b7-c8ae-4fbd-b8ca-3f192dabebcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545967794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2545967794
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1214208676
Short name T63
Test name
Test status
Simulation time 188993157 ps
CPU time 0.94 seconds
Started Aug 19 04:35:08 PM PDT 24
Finished Aug 19 04:35:09 PM PDT 24
Peak memory 213368 kb
Host smart-63e355c3-4ca8-430b-837c-4ac3e8d546cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214208676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1214208676
Directory /workspace/3.rv_dm_sparse_lc_gate_fsm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1744603241
Short name T307
Test name
Test status
Simulation time 3020645912 ps
CPU time 4.25 seconds
Started Aug 19 04:35:00 PM PDT 24
Finished Aug 19 04:35:04 PM PDT 24
Peak memory 213532 kb
Host smart-d46a18d2-2a80-470b-81bf-56720cf2a57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744603241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1744603241
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.604972762
Short name T88
Test name
Test status
Simulation time 158927593 ps
CPU time 0.73 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 205032 kb
Host smart-a5f757da-4c82-419c-8cf2-e4eb3d9a912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604972762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.604972762
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.625130561
Short name T54
Test name
Test status
Simulation time 2918610949 ps
CPU time 2.88 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 205316 kb
Host smart-c526d8be-639b-46c8-bf3e-d09afa73f300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625130561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.625130561
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3653272582
Short name T287
Test name
Test status
Simulation time 104689302 ps
CPU time 0.77 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 205004 kb
Host smart-e9c8a0c1-f0a6-4e7c-aa04-ad441bc53d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653272582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3653272582
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2743070684
Short name T270
Test name
Test status
Simulation time 3026227567 ps
CPU time 4.07 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 205316 kb
Host smart-64ad7903-3969-4eb1-ac2c-ee2cf2574da5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743070684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2743070684
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1996856474
Short name T233
Test name
Test status
Simulation time 90247778 ps
CPU time 0.69 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 205048 kb
Host smart-ab6506a8-d8ab-48c4-937b-0e232fc9b718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996856474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1996856474
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2063424090
Short name T179
Test name
Test status
Simulation time 3602358115 ps
CPU time 10.3 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 205404 kb
Host smart-1649ae99-043f-4776-bb10-788209646180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063424090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2063424090
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2810830444
Short name T1
Test name
Test status
Simulation time 37179676 ps
CPU time 0.79 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 205072 kb
Host smart-31faddcc-2ef0-4541-a7ff-385d305c06d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810830444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2810830444
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3090923089
Short name T284
Test name
Test status
Simulation time 4960510617 ps
CPU time 4.48 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 205304 kb
Host smart-5c7c0f8d-7843-471a-9549-335759dd79c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090923089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3090923089
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3173711497
Short name T216
Test name
Test status
Simulation time 57701341 ps
CPU time 0.77 seconds
Started Aug 19 04:36:03 PM PDT 24
Finished Aug 19 04:36:04 PM PDT 24
Peak memory 205036 kb
Host smart-e4b25c47-7021-4b06-8c9c-b6eb2cb9318a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173711497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3173711497
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1892710119
Short name T298
Test name
Test status
Simulation time 4222121581 ps
CPU time 3.39 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 205320 kb
Host smart-c45f3877-25db-49f9-916b-99b70c482b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892710119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1892710119
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.203563212
Short name T256
Test name
Test status
Simulation time 69442472 ps
CPU time 0.69 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 205028 kb
Host smart-dd7ff49b-3c6c-49ee-bb84-cdee4652a3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203563212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.203563212
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2250682026
Short name T21
Test name
Test status
Simulation time 1954175517 ps
CPU time 3.26 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 204980 kb
Host smart-4a2e7c53-fdfc-4b73-bd1b-e6a6eae03f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250682026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2250682026
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2642481756
Short name T211
Test name
Test status
Simulation time 121944823 ps
CPU time 0.75 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205000 kb
Host smart-7ea522bc-950a-4f1e-87e6-b75ff9a4af1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642481756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2642481756
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1705304606
Short name T263
Test name
Test status
Simulation time 88883836 ps
CPU time 0.73 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:29 PM PDT 24
Peak memory 205048 kb
Host smart-4017f080-9801-4abd-b2af-c23dcc2da026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705304606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1705304606
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2945014248
Short name T323
Test name
Test status
Simulation time 4008149339 ps
CPU time 2.09 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 205312 kb
Host smart-7c314cbb-366d-4b58-b9a3-c449369c1d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945014248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2945014248
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2910417824
Short name T222
Test name
Test status
Simulation time 120165029 ps
CPU time 0.86 seconds
Started Aug 19 04:35:42 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 204996 kb
Host smart-209cb48a-6385-47a7-94b6-cd2951efc774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910417824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2910417824
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.74936544
Short name T275
Test name
Test status
Simulation time 3159347357 ps
CPU time 10.12 seconds
Started Aug 19 04:36:01 PM PDT 24
Finished Aug 19 04:36:11 PM PDT 24
Peak memory 205280 kb
Host smart-62135d9a-48e1-4965-8c1d-20cc6d14ea78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74936544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.74936544
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1928400987
Short name T316
Test name
Test status
Simulation time 72071066 ps
CPU time 0.69 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 205008 kb
Host smart-98315bef-43ba-4710-a60d-d4b7c8b3dee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928400987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1928400987
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1391683147
Short name T83
Test name
Test status
Simulation time 1959363587 ps
CPU time 2.42 seconds
Started Aug 19 04:35:33 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 213420 kb
Host smart-c541b83e-c2e1-4b69-b556-312d03d116c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391683147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1391683147
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.898537935
Short name T133
Test name
Test status
Simulation time 53033895 ps
CPU time 0.81 seconds
Started Aug 19 04:35:17 PM PDT 24
Finished Aug 19 04:35:18 PM PDT 24
Peak memory 205000 kb
Host smart-f0d83db3-9836-4649-8d90-c584a16521d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898537935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.898537935
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2129943867
Short name T289
Test name
Test status
Simulation time 30888553410 ps
CPU time 86.24 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 213708 kb
Host smart-ed57be0e-50f5-40ff-9b55-70f11c214352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129943867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2129943867
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.781377050
Short name T126
Test name
Test status
Simulation time 3044169379 ps
CPU time 4.93 seconds
Started Aug 19 04:35:18 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205484 kb
Host smart-175cdaca-54cd-47d4-9a8e-278be60bb344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781377050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.781377050
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_buffered_enable.2646350398
Short name T127
Test name
Test status
Simulation time 103547753 ps
CPU time 0.92 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 234268 kb
Host smart-e28d71c3-b877-4383-ada9-2340987544db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646350398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.2646350398
Directory /workspace/4.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1762707281
Short name T226
Test name
Test status
Simulation time 6121492747 ps
CPU time 6.93 seconds
Started Aug 19 04:35:04 PM PDT 24
Finished Aug 19 04:35:12 PM PDT 24
Peak memory 205344 kb
Host smart-0c8a11dd-ec8f-4436-90a7-8f2115cca352
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762707281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1762707281
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3525464548
Short name T43
Test name
Test status
Simulation time 717831677 ps
CPU time 1.56 seconds
Started Aug 19 04:35:11 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 204996 kb
Host smart-e56e18ea-89c7-4ed3-a806-f20ea796ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525464548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3525464548
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2215068595
Short name T296
Test name
Test status
Simulation time 123850825 ps
CPU time 1.02 seconds
Started Aug 19 04:35:16 PM PDT 24
Finished Aug 19 04:35:18 PM PDT 24
Peak memory 205016 kb
Host smart-46c61f43-ac20-44c2-83cd-320c4d8ae798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215068595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2215068595
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.476610552
Short name T303
Test name
Test status
Simulation time 6663692840 ps
CPU time 5.26 seconds
Started Aug 19 04:35:02 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 205448 kb
Host smart-f6589512-066b-4607-9796-816bc17e65ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476610552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.476610552
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.643028993
Short name T75
Test name
Test status
Simulation time 793294238 ps
CPU time 2.09 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 229400 kb
Host smart-a76a7073-f128-4d44-8672-7e3e5c838a38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643028993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.643028993
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1755160130
Short name T178
Test name
Test status
Simulation time 4610552133 ps
CPU time 4.29 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 205236 kb
Host smart-02487268-e02f-4cd8-8cad-5072bc0d7aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755160130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1755160130
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3949220004
Short name T13
Test name
Test status
Simulation time 5476402124 ps
CPU time 58.49 seconds
Started Aug 19 04:35:09 PM PDT 24
Finished Aug 19 04:36:08 PM PDT 24
Peak memory 221668 kb
Host smart-32ab9b61-c4fe-4337-a490-954551c7066c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949220004 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.3949220004
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1360191715
Short name T249
Test name
Test status
Simulation time 94632426 ps
CPU time 0.7 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 204980 kb
Host smart-5d8dfb1c-b822-4f35-9a45-25b6c3e9fed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360191715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1360191715
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3571109036
Short name T221
Test name
Test status
Simulation time 76988794 ps
CPU time 0.79 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 205008 kb
Host smart-d7900ee0-c238-4d53-b623-758c6859bbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571109036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3571109036
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1385781673
Short name T135
Test name
Test status
Simulation time 2067191901 ps
CPU time 4.09 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 205192 kb
Host smart-14d8dced-8f6f-4c1b-9d89-c2749b1724f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385781673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1385781673
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1756484440
Short name T281
Test name
Test status
Simulation time 49674316 ps
CPU time 0.82 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205044 kb
Host smart-ef42f1b4-1a48-4148-9265-c8dc4a2367fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756484440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1756484440
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2040453695
Short name T25
Test name
Test status
Simulation time 2483977216 ps
CPU time 7.27 seconds
Started Aug 19 04:35:35 PM PDT 24
Finished Aug 19 04:35:42 PM PDT 24
Peak memory 213560 kb
Host smart-0e029741-b088-4964-9deb-e5d5c80413db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040453695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2040453695
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1607183883
Short name T223
Test name
Test status
Simulation time 125436702 ps
CPU time 0.88 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 205004 kb
Host smart-0fea8262-50f9-4b7b-b3a3-1dd87595dc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607183883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1607183883
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.364048836
Short name T313
Test name
Test status
Simulation time 2236664163 ps
CPU time 1.64 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 205320 kb
Host smart-70bae93a-33bd-4054-b5c8-2ca3d4fb47f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364048836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.364048836
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3621617595
Short name T327
Test name
Test status
Simulation time 32707993 ps
CPU time 0.85 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 205036 kb
Host smart-ea261b8b-d048-42f2-a6f3-5d55eacdbf76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621617595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3621617595
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2722916572
Short name T33
Test name
Test status
Simulation time 3403909794 ps
CPU time 3.9 seconds
Started Aug 19 04:35:28 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 213480 kb
Host smart-c94afc88-7d30-4989-95d5-4130ab0b5dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722916572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2722916572
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2783806595
Short name T294
Test name
Test status
Simulation time 38524544 ps
CPU time 0.7 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 204984 kb
Host smart-29e90735-8327-457e-a17f-ca7783f9d865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783806595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2783806595
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.981155354
Short name T321
Test name
Test status
Simulation time 7033134156 ps
CPU time 5.41 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 205260 kb
Host smart-29ce8f6d-faa4-420c-82a1-3c45343f9b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981155354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.981155354
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3315630587
Short name T217
Test name
Test status
Simulation time 90973942 ps
CPU time 0.92 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 204980 kb
Host smart-764d40e6-1451-4816-97eb-c2c0ce02c03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315630587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3315630587
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1434355804
Short name T11
Test name
Test status
Simulation time 2060932898 ps
CPU time 2.08 seconds
Started Aug 19 04:35:29 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 213440 kb
Host smart-2314e3b8-f17d-4e27-9d4c-763f8e0016b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434355804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1434355804
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3593454690
Short name T85
Test name
Test status
Simulation time 37299423 ps
CPU time 0.7 seconds
Started Aug 19 04:35:13 PM PDT 24
Finished Aug 19 04:35:14 PM PDT 24
Peak memory 205000 kb
Host smart-9f71586a-9450-4dec-96a6-a31898bfc390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593454690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3593454690
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3761209940
Short name T49
Test name
Test status
Simulation time 4436053517 ps
CPU time 4.56 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 205208 kb
Host smart-5222fd90-43e3-4630-bfcd-18e8b823a2d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761209940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3761209940
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.979135126
Short name T213
Test name
Test status
Simulation time 28192724 ps
CPU time 0.75 seconds
Started Aug 19 04:35:34 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 204984 kb
Host smart-17a62c07-8bb0-41b3-b8b0-fa0b88064923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979135126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.979135126
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3722055023
Short name T186
Test name
Test status
Simulation time 3070450612 ps
CPU time 5.17 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 205252 kb
Host smart-d8b32121-2536-4fa8-b906-f997443d0aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722055023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3722055023
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4057944651
Short name T71
Test name
Test status
Simulation time 94622650 ps
CPU time 0.73 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205004 kb
Host smart-72f8694e-e318-41f2-ad3a-fa9a2e86d670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057944651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4057944651
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.4046048263
Short name T187
Test name
Test status
Simulation time 4455441480 ps
CPU time 10.53 seconds
Started Aug 19 04:35:34 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 213560 kb
Host smart-6a45dc9a-e910-46ea-afdc-7804ddd1f84f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046048263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.4046048263
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1972444499
Short name T93
Test name
Test status
Simulation time 57897092 ps
CPU time 0.82 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:15 PM PDT 24
Peak memory 204964 kb
Host smart-9027c9b2-bb6a-42e0-97db-69e670f01290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972444499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1972444499
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2920241446
Short name T30
Test name
Test status
Simulation time 2361507488 ps
CPU time 4.47 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:11 PM PDT 24
Peak memory 213680 kb
Host smart-40e2cd5a-2eb9-488f-a083-277a6a24f3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920241446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2920241446
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.4098059103
Short name T136
Test name
Test status
Simulation time 7105189002 ps
CPU time 9.7 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 213704 kb
Host smart-c776c2e5-3c92-46aa-adac-5fa9a1ce47dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098059103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.4098059103
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_buffered_enable.3448731494
Short name T278
Test name
Test status
Simulation time 379007148 ps
CPU time 1.36 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:22 PM PDT 24
Peak memory 234236 kb
Host smart-545604ca-70cb-49af-b324-6e8cca57cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448731494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.3448731494
Directory /workspace/5.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.839520686
Short name T304
Test name
Test status
Simulation time 4593732061 ps
CPU time 7.81 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205432 kb
Host smart-0ec8e619-707d-4956-bd54-92d8e9095e43
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839520686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.839520686
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.236035752
Short name T45
Test name
Test status
Simulation time 347456071 ps
CPU time 1.53 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 204904 kb
Host smart-9e2a51b0-2764-4f9d-ac0e-c8c269d5a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236035752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.236035752
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2878900087
Short name T241
Test name
Test status
Simulation time 4535681279 ps
CPU time 13.02 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 205468 kb
Host smart-f127f96c-95ab-4e28-bc27-c47cf5a10dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878900087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2878900087
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1412305213
Short name T184
Test name
Test status
Simulation time 810176335 ps
CPU time 2.63 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 205272 kb
Host smart-eb0808bb-0130-4725-9b74-e40ef0e3e928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412305213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1412305213
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.3347551366
Short name T52
Test name
Test status
Simulation time 2852313335 ps
CPU time 45.46 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:36:06 PM PDT 24
Peak memory 229928 kb
Host smart-0a1c0ac3-5be5-4a61-84a9-f2cb24f5f5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347551366 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.3347551366
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1147231223
Short name T91
Test name
Test status
Simulation time 108619649 ps
CPU time 0.78 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 205048 kb
Host smart-d6a5831b-f8b6-41a0-96a3-80a86ff971d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147231223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1147231223
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.927412110
Short name T267
Test name
Test status
Simulation time 5033675245 ps
CPU time 14.36 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:40 PM PDT 24
Peak memory 213664 kb
Host smart-67bce4f9-4418-4bbf-a38a-1938d98c90c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927412110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.927412110
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2369555098
Short name T274
Test name
Test status
Simulation time 8971698697 ps
CPU time 14.3 seconds
Started Aug 19 04:35:12 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 213656 kb
Host smart-eaab9304-25f7-42ec-bcb4-81cf7317a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369555098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2369555098
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_buffered_enable.624164804
Short name T89
Test name
Test status
Simulation time 177473821 ps
CPU time 0.88 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 225812 kb
Host smart-9195730c-18b6-4445-9bb7-1a2759925f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624164804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.624164804
Directory /workspace/6.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3794979793
Short name T236
Test name
Test status
Simulation time 2152120557 ps
CPU time 4.25 seconds
Started Aug 19 04:35:11 PM PDT 24
Finished Aug 19 04:35:15 PM PDT 24
Peak memory 213580 kb
Host smart-9ad6a850-61d0-4bba-a1d1-91a4b8119701
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794979793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3794979793
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3560729341
Short name T47
Test name
Test status
Simulation time 559138533 ps
CPU time 2.16 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 205020 kb
Host smart-15147cc0-9c56-4cdb-a94d-fb3d1d0c2b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560729341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3560729341
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1419626994
Short name T319
Test name
Test status
Simulation time 1607048449 ps
CPU time 1.6 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205408 kb
Host smart-cbae81cd-39f2-4334-9989-4a6b8eb0994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419626994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1419626994
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2460820607
Short name T196
Test name
Test status
Simulation time 1779471001 ps
CPU time 4.8 seconds
Started Aug 19 04:35:19 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 205220 kb
Host smart-d336f1f1-8089-418b-8baf-1cd25349d080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460820607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2460820607
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2404088821
Short name T212
Test name
Test status
Simulation time 237488284 ps
CPU time 0.73 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 205032 kb
Host smart-49b319b9-eee6-44ed-9400-796835027d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404088821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2404088821
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3952994824
Short name T190
Test name
Test status
Simulation time 26853029341 ps
CPU time 18.05 seconds
Started Aug 19 04:35:09 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 213716 kb
Host smart-4f692c11-4099-4bea-bb25-1931d8698812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952994824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3952994824
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.4232284262
Short name T311
Test name
Test status
Simulation time 6099698479 ps
CPU time 8.65 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 214716 kb
Host smart-954d0b76-10f5-49a7-be61-d386dc29b3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232284262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.4232284262
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_buffered_enable.32320542
Short name T171
Test name
Test status
Simulation time 359880773 ps
CPU time 0.89 seconds
Started Aug 19 04:35:09 PM PDT 24
Finished Aug 19 04:35:10 PM PDT 24
Peak memory 226120 kb
Host smart-f8f8cf06-60c7-41a6-bb7a-ea1846587955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32320542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.32320542
Directory /workspace/7.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2679048048
Short name T66
Test name
Test status
Simulation time 2966458442 ps
CPU time 2.98 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 205428 kb
Host smart-09632580-b138-4760-b4d5-766ab5c4d4d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679048048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2679048048
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.3369693009
Short name T4
Test name
Test status
Simulation time 364354538 ps
CPU time 1.65 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 204904 kb
Host smart-aaf7372c-f59b-45da-aa45-35a147601bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369693009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.3369693009
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.4185581383
Short name T225
Test name
Test status
Simulation time 2212456560 ps
CPU time 3.77 seconds
Started Aug 19 04:35:17 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205488 kb
Host smart-2adb074f-0450-4c40-9f41-108394648d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185581383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4185581383
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.15096301
Short name T7
Test name
Test status
Simulation time 2536620373 ps
CPU time 4.79 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 205300 kb
Host smart-cee6046c-4ee2-45a2-b112-fbc90072ad9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.15096301
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1325168050
Short name T237
Test name
Test status
Simulation time 79141881 ps
CPU time 0.79 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205024 kb
Host smart-498bedcc-b84c-48c9-8d9c-87d1ed64ec77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325168050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1325168050
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.313805459
Short name T277
Test name
Test status
Simulation time 5821028091 ps
CPU time 2.82 seconds
Started Aug 19 04:35:22 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 213652 kb
Host smart-54042889-e47c-4906-b73b-40a8cfda176c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313805459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.313805459
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1201513243
Short name T220
Test name
Test status
Simulation time 5922965368 ps
CPU time 18.01 seconds
Started Aug 19 04:35:17 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 213660 kb
Host smart-84a51a96-866e-44ca-b86d-d9f060c5e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201513243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1201513243
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_buffered_enable.3547795098
Short name T68
Test name
Test status
Simulation time 115457620 ps
CPU time 1.19 seconds
Started Aug 19 04:35:20 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 233236 kb
Host smart-2e9f429f-8ee9-4a16-91df-1373b15b80b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547795098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.3547795098
Directory /workspace/8.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3584030234
Short name T232
Test name
Test status
Simulation time 3992839058 ps
CPU time 11.85 seconds
Started Aug 19 04:35:09 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 213768 kb
Host smart-7aec01fb-a2d5-473e-ac33-feaae60a6da1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584030234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3584030234
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2737432893
Short name T95
Test name
Test status
Simulation time 4196698813 ps
CPU time 4.11 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:11 PM PDT 24
Peak memory 205448 kb
Host smart-1d5e429c-5539-4de4-a46e-9ed7a022bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737432893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2737432893
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3351577906
Short name T58
Test name
Test status
Simulation time 4912733013 ps
CPU time 3.52 seconds
Started Aug 19 04:35:15 PM PDT 24
Finished Aug 19 04:35:19 PM PDT 24
Peak memory 213504 kb
Host smart-99d820c4-ff1a-49cc-ad71-546c9ba2cbdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351577906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3351577906
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2298404230
Short name T230
Test name
Test status
Simulation time 138535859 ps
CPU time 0.73 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 205008 kb
Host smart-87817686-7b61-461d-97db-8dc988e05f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298404230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2298404230
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.27614617
Short name T76
Test name
Test status
Simulation time 23475000482 ps
CPU time 75.15 seconds
Started Aug 19 04:35:12 PM PDT 24
Finished Aug 19 04:36:27 PM PDT 24
Peak memory 213808 kb
Host smart-dde375f5-ecca-4699-b43f-7fd91fcef4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27614617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.27614617
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_buffered_enable.3444452244
Short name T280
Test name
Test status
Simulation time 478773572 ps
CPU time 1.57 seconds
Started Aug 19 04:35:10 PM PDT 24
Finished Aug 19 04:35:12 PM PDT 24
Peak memory 234220 kb
Host smart-5a3bc6ee-54db-4014-9a03-7843eaf8ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444452244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.3444452244
Directory /workspace/9.rv_dm_buffered_enable/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2889905993
Short name T197
Test name
Test status
Simulation time 2744772920 ps
CPU time 2.88 seconds
Started Aug 19 04:35:21 PM PDT 24
Finished Aug 19 04:35:29 PM PDT 24
Peak memory 205436 kb
Host smart-f2d168d2-5354-4662-8845-3639e55c0fec
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889905993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2889905993
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2180932299
Short name T260
Test name
Test status
Simulation time 1126505812 ps
CPU time 3.62 seconds
Started Aug 19 04:35:09 PM PDT 24
Finished Aug 19 04:35:13 PM PDT 24
Peak memory 205332 kb
Host smart-fdc3c26a-7a2e-4b25-a656-3094e00d84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180932299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2180932299
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3564545741
Short name T40
Test name
Test status
Simulation time 2101569574 ps
CPU time 2.89 seconds
Started Aug 19 04:35:18 PM PDT 24
Finished Aug 19 04:35:21 PM PDT 24
Peak memory 205220 kb
Host smart-4db7891c-8ef6-425b-a95f-dff3320b0f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564545741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3564545741
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.2786530278
Short name T111
Test name
Test status
Simulation time 10296672204 ps
CPU time 23.9 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 229976 kb
Host smart-74c545a8-0501-4be3-84e2-6c8405f88ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786530278 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.2786530278
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%