RV_DM Lint Results
Wednesday February 21 2024 20:04:41 UTC
Branch: os_regression
Tool: VERILATOR
| Build Mode |
Flow Warnings |
Flow Errors |
Lint Warnings |
Lint Errors |
| default |
0 |
2 |
5 |
0 |
Messages for Build Mode 'default'
Flow Errors
ERROR: %Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:87:41: Operator VAR 'RomBaseAddr' expects 12 bits on the Initial value, but Initial value's VARREF 'HaltAddress' generates 64 bits.
ERROR: Failed to build lowrisc:ip:rv_dm:0.1 : '['make', 'Vrv_dm.mk']' exited with an error: 2
Lint Warnings
%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:90:41: Operator VAR 'RomEndAddr' expects 12 bits on the Initial value, but Initial value's ADD generates 64 bits.
%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:282:47: Operator SUB expects 32 bits on the LHS, but LHS's VARREF 'DataCount' generates 4 bits.
%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:277:47: Operator SUB expects 32 bits on the LHS, but LHS's SEL generates 10 bits.
%Warning-WIDTH: ../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv:277:47: Operator SUB expects 32 bits on the RHS, but RHS's SEL generates 10 bits.
%Warning-UNOPTFLAT: ../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv:228:12: Signal unoptimizable: Feedback to clock or circular logic: 'rv_dm.u_tlul_lc_gate_rom.tl_d2h_error'
Past Results