RV_TIMER Simulation Results

Thursday November 04 2021 01:48:19 UTC

GitHub Revision: `f5d8bbc5a`

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	random	rv_timer_random	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	20	20	100.00
V1		TOTAL	255	255	100.00
V2	random_reset	rv_timer_random_reset	50	50	100.00
V2	disabled	rv_timer_disabled	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	50	50	100.00
V2	stress	rv_timer_stress_all	47	50	94.00
V2	intr_test	rv_timer_intr_test	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	5	5	100.00
		rv_timer_csr_rw	20	20	100.00
		rv_timer_csr_aliasing	5	5	100.00
		rv_timer_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	5	5	100.00
		rv_timer_csr_rw	20	20	100.00
		rv_timer_csr_aliasing	5	5	100.00
		rv_timer_same_csr_outstanding	20	20	100.00
V2		TOTAL	287	290	98.97
V2S		TOTAL	0	0	--
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	50	50	100.00
V3	tl_intg_err	rv_timer_tl_intg_err	20	20	100.00
V3		TOTAL	70	70	100.00
		TOTAL	612	615	99.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	100.00	100.00	98.89	--	100.00	99.34	99.54

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test rv_timer_stress_all has 3 failures.

14.rv_timer_stress_all.1366103383
Line 37, in log /usr/local/google/home/chencindy/nightly_openTitan/master/rv_timer-sim-vcs/14.rv_timer_stress_all/out/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
  --- UVM Report Summary ---
  
  Quit count :     0 of     1

31.rv_timer_stress_all.1759377758
Line 37, in log /usr/local/google/home/chencindy/nightly_openTitan/master/rv_timer-sim-vcs/31.rv_timer_stress_all/out/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
  --- UVM Report Summary ---
  
  Quit count :     0 of     1

... and 1 more failures.