RV_TIMER Simulation Results

Thursday November 18 2021 03:06:23 UTC

GitHub Revision: `050d7b361`

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	random	rv_timer_random	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	20	20	100.00
V1		TOTAL	255	255	100.00
V2	random_reset	rv_timer_random_reset	50	50	100.00
V2	disabled	rv_timer_disabled	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	50	50	100.00
V2	stress	rv_timer_stress_all	50	50	100.00
V2	intr_test	rv_timer_intr_test	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	5	5	100.00
		rv_timer_csr_rw	20	20	100.00
		rv_timer_csr_aliasing	5	5	100.00
		rv_timer_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	5	5	100.00
		rv_timer_csr_rw	20	20	100.00
		rv_timer_csr_aliasing	5	5	100.00
		rv_timer_same_csr_outstanding	20	20	100.00
V2		TOTAL	290	290	100.00
V2S	tl_intg_err	rv_timer_tl_intg_err	0	20	0.00
V2S		TOTAL	0	20	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	50	50	100.00
V3		TOTAL	50	50	100.00
		TOTAL	595	615	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	7	100.00
V2S	1	1	0	0.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.65	99.78	100.00	95.00	--	99.29	99.34	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:536) virtual_sequencer [rv_timer_common_vseq] expect alert:fatal_fault to fire has 20 failures:

Test rv_timer_tl_intg_err has 20 failures.

0.rv_timer_tl_intg_err.858912633
Line 39, in log /usr/local/google/home/chencindy/nightly_openTitan/master/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/out/run.log

  UVM_ERROR @   3193369 ps: (cip_base_vseq.sv:536) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] expect alert:fatal_fault to fire
  UVM_INFO @   3193369 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
  --- UVM Report Summary ---
  
  Quit count reached!

1.rv_timer_tl_intg_err.1830040755
Line 39, in log /usr/local/google/home/chencindy/nightly_openTitan/master/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/out/run.log

  UVM_ERROR @   1182220 ps: (cip_base_vseq.sv:536) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] expect alert:fatal_fault to fire
  UVM_INFO @   1182220 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
  --- UVM Report Summary ---
  
  Quit count reached!

... and 18 more failures.