RV_TIMER Simulation Results

Saturday November 20 2021 03:14:24 UTC

GitHub Revision: 41fc13b60

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 random rv_timer_random 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 5 5 100.00
V1 csr_rw rv_timer_csr_rw 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 20 20 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 50 50 100.00
V2 disabled rv_timer_disabled 50 50 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 50 50 100.00
V2 stress rv_timer_stress_all 50 50 100.00
V2 intr_test rv_timer_intr_test 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 5 5 100.00
rv_timer_csr_rw 20 20 100.00
rv_timer_csr_aliasing 5 5 100.00
rv_timer_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 5 5 100.00
rv_timer_csr_rw 20 20 100.00
rv_timer_csr_aliasing 5 5 100.00
rv_timer_same_csr_outstanding 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err rv_timer_tl_intg_err 20 20 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 615 615 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 1 1 1 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.67 100.00 100.00 98.89 -- 100.00 99.34 99.77

Past Results