Module Definition
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Module : timer_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_harts[0].u_core 100.00 100.00 100.00



Module Instance : tb.dut.gen_harts[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 100.00 99.40 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : timer_core
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS2877100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
30 1 1
31 1 1
32 1 1
33 1 1
35 1 1
39 1 1
41 1 1
46 1 1


Branch Coverage for Module : timer_core
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_ni)) -2-: 30 if ((!active)) -3-: 32 if ((tick_count == prescaler))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%