Module Definition
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Module : rv_timer_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_timer_csr_assert 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.rv_timer_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 100.00 99.40 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_timer_csr_assert_fpv
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS5388100.00
CONT_ASSIGN7611100.00
ALWAYS802323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv' or '../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
45 1 1
46 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
76 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
90 1 1
91 1 1
92 1 1
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
MISSING_ELSE
99 1 1
100 1 1
101 1 1
102 1 1
MISSING_ELSE
104 1 1
MISSING_ELSE
106 1 1
107 1 1
MISSING_ELSE
MISSING_ELSE


Cond Coverage for Module : rv_timer_csr_assert_fpv
TotalCoveredPercent
Conditions1414100.00
Logical1414100.00
Non-Logical00
Event00

 LINE       43
 EXPRESSION (h2d.a_mask[0] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       44
 EXPRESSION (h2d.a_mask[1] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       45
 EXPRESSION (h2d.a_mask[2] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       46
 EXPRESSION (h2d.a_mask[3] ? '1 : '0)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       90
 EXPRESSION (h2d.a_valid && d2h.a_ready)
             -----1-----    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T12,T13
11CoveredT1,T2,T3

 LINE       106
 EXPRESSION (h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1))
             -----1-----    ----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T14,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : rv_timer_csr_assert_fpv
Line No.TotalCoveredPercent
Branches 27 27 100.00
TERNARY 43 2 2 100.00
TERNARY 44 2 2 100.00
TERNARY 45 2 2 100.00
TERNARY 46 2 2 100.00
CASE 53 8 8 100.00
IF 80 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv' or '../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 43 (h2d.a_mask[0]) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 44 (h2d.a_mask[1]) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 45 (h2d.a_mask[2]) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 46 (h2d.a_mask[3]) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 53 case (pend_trans[d2h.d_source].addr)

Branches:
-1-StatusTests
0 Covered T1,T2,T3
4 Covered T1,T2,T3
256 Covered T1,T2,T3
268 Covered T1,T2,T3
272 Covered T1,T2,T3
276 Covered T1,T2,T3
284 Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 80 if ((!rst_ni)) -2-: 90 if ((h2d.a_valid && d2h.a_ready)) -3-: 92 if ((h2d.a_opcode inside {PutFullData, PutPartialData})) -4-: 95 if ((h2d.a_opcode == Get)) -5-: 99 if (d2h.d_valid) -6-: 100 if ((pend_trans[d2h.d_source].wr_pending == 1'b1)) -7-: 101 if ((!d2h.d_error)) -8-: 106 if ((h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1)))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
1 - - - - - - - Covered T1,T2,T3
0 1 1 - - - - - Covered T1,T2,T3
0 1 0 1 - - - - Covered T1,T2,T3
0 1 0 0 - - - - Covered T11,T12,T13
0 0 - - - - - - Covered T1,T2,T3
0 - - - 1 1 1 - Covered T1,T2,T3
0 - - - 1 1 0 - Covered T11,T12,T13
0 - - - 1 0 - - Covered T1,T2,T3
0 - - - 1 - - 1 Covered T1,T2,T3
0 - - - 1 - - 0 Covered T1,T2,T3
0 - - - 0 - - - Covered T1,T2,T3


Assert Coverage for Module : rv_timer_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
cfg0_rd_A 2147483647 13599 0 0
compare_lower0_0_rd_A 2147483647 10109 0 0
compare_upper0_0_rd_A 2147483647 14017 0 0
ctrl_rd_A 2147483647 10103 0 0
intr_enable0_rd_A 2147483647 12243 0 0


cfg0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 13599 0 0
T11 650617 1204 0 0
T12 563377 988 0 0
T21 609392 867 0 0
T26 452462 860 0 0
T27 279783 485 0 0
T29 115034 2031 0 0
T31 245020 358 0 0
T35 372408 650 0 0
T36 317212 610 0 0
T41 465343 930 0 0

compare_lower0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 10109 0 0
T11 650617 826 0 0
T12 563377 890 0 0
T21 609392 793 0 0
T26 452462 698 0 0
T27 279783 393 0 0
T29 115034 1227 0 0
T31 245020 280 0 0
T35 372408 539 0 0
T36 317212 516 0 0
T41 465343 661 0 0

compare_upper0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 14017 0 0
T11 650617 1260 0 0
T12 563377 1085 0 0
T21 609392 993 0 0
T26 452462 881 0 0
T27 279783 510 0 0
T29 115034 1916 0 0
T31 245020 370 0 0
T35 372408 794 0 0
T36 317212 590 0 0
T41 465343 1001 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 10103 0 0
T11 650617 871 0 0
T12 563377 767 0 0
T21 609392 611 0 0
T26 452462 654 0 0
T27 279783 357 0 0
T29 115034 1310 0 0
T31 245020 285 0 0
T35 372408 590 0 0
T36 317212 538 0 0
T41 465343 688 0 0

intr_enable0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 12243 0 0
T11 650617 867 0 0
T12 563377 852 0 0
T21 609392 762 0 0
T26 452462 671 0 0
T27 279783 488 0 0
T42 491058 37 0 0
T43 187053 70 0 0
T44 577516 57 0 0
T45 201469 26 0 0
T46 1432 55 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%