Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57669958	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	57207409	1		T1	40276		T2	155224		T3	7935

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values_4	114450200	1		T1	79977		T2	310321		T3	15720
values_0	55149	1		T1	7		T2	121		T3	20
values_1	372018	1		T1	12		T2	105		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46841750	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	68035617	1		T1	47497		T2	183872		T3	9449

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources_00	869208	1		T1	322		T3	54		T4	15
valid_sources_01	390890	1		T1	298		T3	73		T4	8
valid_sources_02	634146	1		T1	320		T3	55		T4	5
valid_sources_03	345085	1		T1	325		T3	63		T4	12
valid_sources_04	348419	1		T1	272		T3	79		T4	10
valid_sources_05	350199	1		T1	301		T3	72		T4	3
valid_sources_06	353543	1		T1	285		T3	54		T4	4
valid_sources_07	348897	1		T1	303		T3	47		T4	2
valid_sources_08	347873	1		T1	309		T3	50		T4	3
valid_sources_09	344220	1		T1	277		T3	69		T4	4
valid_sources_0a	354901	1		T1	279		T3	49		T4	7
valid_sources_0b	609114	1		T1	327		T3	74		T4	11
valid_sources_0c	347450	1		T1	322		T3	69		T4	12
valid_sources_0d	347828	1		T1	302		T3	61		T4	11
valid_sources_0e	350522	1		T1	294		T3	53		T4	14
valid_sources_0f	350273	1		T1	292		T3	57		T4	2
valid_sources_10	351253	1		T1	252		T3	60		T4	11
valid_sources_11	347701	1		T1	302		T3	45		T4	5
valid_sources_12	348170	1		T1	348		T3	60		T16	196
valid_sources_13	359374	1		T1	275		T3	65		T4	3
valid_sources_14	353290	1		T1	295		T3	72		T4	7
valid_sources_15	348934	1		T1	277		T3	72		T4	4
valid_sources_16	351669	1		T1	300		T3	57		T4	12
valid_sources_17	347968	1		T1	211		T3	69		T4	6
valid_sources_18	347979	1		T1	251		T3	65		T4	10
valid_sources_19	350954	1		T1	279		T3	73		T4	8
valid_sources_1a	347594	1		T1	306		T3	74		T4	6
valid_sources_1b	348986	1		T1	358		T3	61		T4	10
valid_sources_1c	2326534	1		T1	298		T3	58		T4	13
valid_sources_1d	351233	1		T1	347		T3	46		T4	12
valid_sources_1e	601751	1		T1	354		T3	55		T4	9
valid_sources_1f	347571	1		T1	301		T3	65		T4	4
valid_sources_20	350013	1		T1	326		T3	67		T4	11
valid_sources_21	346986	1		T1	345		T3	64		T4	5
valid_sources_22	347142	1		T1	310		T3	66		T4	6
valid_sources_23	349281	1		T1	268		T3	55		T4	9
valid_sources_24	356923	1		T1	319		T3	58		T4	15
valid_sources_25	345194	1		T1	290		T3	59		T4	3
valid_sources_26	3447570	1		T1	312		T2	310344		T3	61
valid_sources_27	344918	1		T1	329		T3	80		T4	10
valid_sources_28	350524	1		T1	217		T3	58		T4	3
valid_sources_29	362538	1		T1	282		T3	50		T4	13
valid_sources_2a	350894	1		T1	365		T3	47		T4	5
valid_sources_2b	343895	1		T1	318		T3	65		T4	6
valid_sources_2c	347124	1		T1	317		T3	48		T4	7
valid_sources_2d	346124	1		T1	380		T3	67		T4	12
valid_sources_2e	349262	1		T1	320		T3	62		T4	10
valid_sources_2f	348731	1		T1	230		T3	65		T4	9
valid_sources_30	977384	1		T1	342		T3	47		T4	10
valid_sources_31	348550	1		T1	275		T3	73		T4	9
valid_sources_32	347525	1		T1	344		T3	57		T4	13
valid_sources_33	347306	1		T1	250		T3	51		T4	6
valid_sources_34	347929	1		T1	257		T3	60		T4	2
valid_sources_35	348855	1		T1	335		T3	51		T4	12
valid_sources_36	1025194	1		T1	346		T3	66		T4	6
valid_sources_37	347981	1		T1	286		T3	60		T4	9
valid_sources_38	348403	1		T1	261		T3	60		T4	4
valid_sources_39	807343	1		T1	346		T3	81		T4	11
valid_sources_3a	345644	1		T1	256		T3	57		T4	8
valid_sources_3b	347778	1		T1	246		T3	61		T4	4
valid_sources_3c	347686	1		T1	309		T3	60		T4	3
valid_sources_3d	348637	1		T1	236		T3	62		T4	23
valid_sources_3e	351015	1		T1	371		T3	50		T4	2
valid_sources_3f	348506	1		T1	295		T3	55		T4	10
valid_sources_40	466172	1		T1	269		T3	57		T4	2
valid_sources_41	597604	1		T1	315		T3	83		T4	14
valid_sources_42	594531	1		T1	356		T3	74		T4	11
valid_sources_43	354802	1		T1	317		T3	41		T4	4
valid_sources_44	348288	1		T1	240		T3	64		T4	10
valid_sources_45	350586	1		T1	304		T3	73		T4	6
valid_sources_46	346777	1		T1	308		T3	63		T4	3
valid_sources_47	2338198	1		T1	304		T3	50		T4	13
valid_sources_48	349011	1		T1	361		T3	63		T4	5
valid_sources_49	347341	1		T1	350		T3	62		T4	5
valid_sources_4a	349239	1		T1	264		T3	65		T4	12
valid_sources_4b	345982	1		T1	387		T3	83		T4	2
valid_sources_4c	347891	1		T1	363		T3	56		T4	13
valid_sources_4d	776155	1		T1	244		T3	59		T4	5
valid_sources_4e	350193	1		T1	362		T3	69		T4	8
valid_sources_4f	902266	1		T1	320		T3	51		T4	9
valid_sources_50	351072	1		T1	347		T3	59		T4	20
valid_sources_51	346347	1		T1	327		T3	44		T4	1
valid_sources_52	349654	1		T1	333		T3	55		T4	2
valid_sources_53	359498	1		T1	387		T3	65		T4	8
valid_sources_54	3646969	1		T1	334		T3	53		T4	5
valid_sources_55	347697	1		T1	324		T3	72		T4	18
valid_sources_56	347670	1		T1	257		T3	73		T4	2
valid_sources_57	350766	1		T1	256		T3	60		T4	5
valid_sources_58	559388	1		T1	306		T3	55		T4	16
valid_sources_59	358183	1		T1	298		T3	60		T4	5
valid_sources_5a	358094	1		T1	348		T3	48		T4	11
valid_sources_5b	361330	1		T1	282		T3	88		T4	9
valid_sources_5c	346298	1		T1	319		T3	55		T4	9
valid_sources_5d	347600	1		T1	287		T3	77		T4	12
valid_sources_5e	347899	1		T1	251		T3	53		T4	8
valid_sources_5f	349298	1		T1	287		T3	45		T4	20
valid_sources_60	348822	1		T1	289		T3	62		T4	10
valid_sources_61	346355	1		T1	280		T3	54		T4	11
valid_sources_62	345618	1		T1	335		T3	76		T4	6
valid_sources_63	386309	1		T1	354		T3	44		T4	7
valid_sources_64	2280911	1		T1	391		T3	51		T4	6
valid_sources_65	345449	1		T1	320		T3	72		T4	6
valid_sources_66	351937	1		T1	384		T3	60		T4	6
valid_sources_67	522489	1		T1	203		T3	58		T4	27
valid_sources_68	352914	1		T1	362		T3	41		T4	7
valid_sources_69	749055	1		T1	346		T3	69		T4	3
valid_sources_6a	364201	1		T1	262		T3	60		T4	11
valid_sources_6b	352354	1		T1	355		T3	45		T4	7
valid_sources_6c	347027	1		T1	270		T3	50		T4	1
valid_sources_6d	346933	1		T1	347		T3	72		T4	10
valid_sources_6e	349299	1		T1	313		T3	65		T4	11
valid_sources_6f	351842	1		T1	275		T3	55		T4	17
valid_sources_70	347067	1		T1	312		T3	70		T4	7
valid_sources_71	344488	1		T1	323		T3	68		T4	3
valid_sources_72	347898	1		T1	318		T3	62		T4	9
valid_sources_73	359556	1		T1	281		T3	58		T4	11
valid_sources_74	349547	1		T1	308		T3	56		T4	7
valid_sources_75	346303	1		T1	315		T3	55		T4	8
valid_sources_76	350513	1		T1	273		T3	64		T4	10
valid_sources_77	348821	1		T1	311		T3	62		T16	173
valid_sources_78	1689793	1		T1	306		T3	61		T4	4
valid_sources_79	408394	1		T1	324		T3	63		T4	11
valid_sources_7a	349452	1		T1	309		T3	46		T4	5
valid_sources_7b	346202	1		T1	327		T3	56		T4	10
valid_sources_7c	346038	1		T1	269		T3	72		T4	12
valid_sources_7d	347698	1		T1	331		T3	68		T4	4
valid_sources_7e	372869	1		T1	296		T3	55		T4	8
valid_sources_7f	471707	1		T1	322		T3	40		T4	10
valid_sources_80	346245	1		T1	325		T3	46		T4	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values_4

all_enables

biggest_size

57177619

1

T1

40262

T2

155210

T3

7910

values_0

all_enables

biggest_size

16044

1

T1

6

T2

82

T3

18

values_1

all_enables

biggest_size

13746

1

T1

8

T2

55

T3

7