Module Definition
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Module : tlul_adapter_reg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_reg_if 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL3535100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6811100.00
ALWAYS7266100.00
ALWAYS7888100.00
ALWAYS9166100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13611100.00
ALWAYS14333100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
55 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
63 1 1
68 1 1
72 2 2
73 2 2
74 2 2
MISSING_ELSE
78 1 1
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
86 1 1
MISSING_ELSE
91 1 1
92 1 1
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
113 1 1
133 1 1
136 1 1
143 1 1
145 1 1
148 1 1


Cond Coverage for Module : tlul_adapter_reg
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       86
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       95
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       95
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT10,T11,T12
100CoveredT10,T11,T12

Branch Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 72 4 4 100.00
IF 78 4 4 100.00
IF 91 4 4 100.00
IF 143 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 72 if ((!rst_ni)) -2-: 73 if (a_ack) -3-: 74 if (d_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 78 if ((!rst_ni)) -2-: 82 if (a_ack) -3-: 86 (rd_req) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 91 if ((!rst_ni)) -2-: 94 if (a_ack) -3-: 95 (((error_i || err_internal) || wr_req)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 143 if (wr_req)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MatchedWidthAssert 615 615 0 0


MatchedWidthAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 615 615 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%