Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
ALWAYS	53	17	17	100.00
CONT_ASSIGN	92	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
50	1	1
53	1	1
54	1	1
55	1	1
57	1	1
58	1	1
60	1	1
61	1	1
62	1	1
66	1	1
68	1	1
70	1	1
74	1	1
75	1	1
76	1	1
86	1	1
87	1	1
88	1	1
92	1	1

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	57	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	57	if (tl_i.a_valid)
-2-:	58	case (tl_i.a_size)
-3-:	68	(tl_i.a_address[1]) ? 
-4-:	70	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T1,T2,T3
1	'h1	1	-	Covered	T1,T2,T3
1	'h1	0	-	Covered	T1,T2,T3
1	'h1	-	1	Covered	T1,T2,T3
1	'h1	-	0	Covered	T1,T2,T3
1	'h00000002	-	-	Covered	T1,T2,T3
1	default	-	-	Covered	T1,T2,T3
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	615	615	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615	615	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0