Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 67222424 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 66824125 1 T1 16 T2 203879 T3 175601



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 133675739 1 T1 20 T2 407204 T3 352043
values_0 51310 1 T1 7 T2 12 T3 20
values_1 319500 1 T1 11 T2 9 T3 21



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 54658356 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 79388193 1 T1 22 T2 241415 T3 208216



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 365296 1 T2 1514 T3 1279 T4 527
valid_sources_01 362508 1 T2 1556 T3 1311 T4 527
valid_sources_02 359486 1 T2 1583 T3 1459 T4 535
valid_sources_03 361600 1 T2 1636 T3 1383 T4 562
valid_sources_04 363418 1 T2 1534 T3 1385 T4 520
valid_sources_05 357791 1 T2 1499 T3 1431 T4 510
valid_sources_06 600456 1 T2 1540 T3 1351 T4 492
valid_sources_07 1605395 1 T2 1453 T3 1387 T4 517
valid_sources_08 361954 1 T2 1597 T3 1433 T4 527
valid_sources_09 360972 1 T2 1557 T3 1392 T4 528
valid_sources_0a 361421 1 T2 1536 T3 1349 T4 549
valid_sources_0b 362623 1 T2 1565 T3 1460 T4 533
valid_sources_0c 537455 1 T2 1472 T3 1329 T4 519
valid_sources_0d 363238 1 T2 1545 T3 1408 T4 501
valid_sources_0e 359720 1 T2 1576 T3 1299 T4 552
valid_sources_0f 386272 1 T2 1586 T3 1447 T4 510
valid_sources_10 360048 1 T2 1493 T3 1384 T4 511
valid_sources_11 1016029 1 T2 1616 T3 1373 T12 644091
valid_sources_12 365776 1 T2 1638 T3 1414 T4 542
valid_sources_13 364786 1 T2 1633 T3 1381 T4 532
valid_sources_14 397449 1 T2 1522 T3 1320 T4 516
valid_sources_15 621402 1 T2 1503 T3 1312 T4 540
valid_sources_16 361638 1 T2 1523 T3 1317 T4 541
valid_sources_17 359448 1 T2 1469 T3 1247 T4 527
valid_sources_18 532521 1 T2 1656 T3 1286 T4 467
valid_sources_19 362162 1 T2 1628 T3 1372 T4 551
valid_sources_1a 414149 1 T2 1609 T3 1433 T4 510
valid_sources_1b 364213 1 T2 1532 T3 1396 T4 497
valid_sources_1c 641078 1 T2 1498 T3 1431 T4 596
valid_sources_1d 4907911 1 T2 1632 T3 1395 T4 537
valid_sources_1e 365687 1 T2 1663 T3 1348 T4 525
valid_sources_1f 360417 1 T2 1655 T3 1395 T4 522
valid_sources_20 361642 1 T2 1665 T3 1409 T4 527
valid_sources_21 361751 1 T2 1582 T3 1411 T4 521
valid_sources_22 429747 1 T2 1596 T3 1434 T4 546
valid_sources_23 422590 1 T2 1636 T3 1372 T4 533
valid_sources_24 366623 1 T2 1619 T3 1312 T4 522
valid_sources_25 362751 1 T2 1653 T3 1405 T4 566
valid_sources_26 485257 1 T2 1585 T3 1390 T4 514
valid_sources_27 361101 1 T2 1582 T3 1396 T4 554
valid_sources_28 364797 1 T2 1508 T3 1385 T4 535
valid_sources_29 359737 1 T2 1619 T3 1401 T4 523
valid_sources_2a 360733 1 T2 1603 T3 1328 T4 498
valid_sources_2b 374005 1 T2 1648 T3 1392 T4 502
valid_sources_2c 360224 1 T2 1581 T3 1440 T4 568
valid_sources_2d 360384 1 T2 1584 T3 1445 T4 500
valid_sources_2e 365950 1 T2 1598 T3 1275 T4 537
valid_sources_2f 363247 1 T2 1625 T3 1407 T4 554
valid_sources_30 361578 1 T2 1634 T3 1471 T4 518
valid_sources_31 599607 1 T2 1694 T3 1405 T4 519
valid_sources_32 3215207 1 T2 1525 T3 1399 T4 561
valid_sources_33 363673 1 T2 1745 T3 1376 T4 512
valid_sources_34 364779 1 T2 1645 T3 1451 T4 563
valid_sources_35 360504 1 T2 1566 T3 1392 T4 542
valid_sources_36 364452 1 T2 1617 T3 1414 T4 506
valid_sources_37 366015 1 T2 1642 T3 1381 T4 557
valid_sources_38 358600 1 T2 1627 T3 1365 T4 545
valid_sources_39 368725 1 T2 1587 T3 1464 T4 503
valid_sources_3a 359634 1 T2 1539 T3 1304 T4 536
valid_sources_3b 363786 1 T2 1573 T3 1508 T4 526
valid_sources_3c 564890 1 T2 1532 T3 1237 T4 529
valid_sources_3d 364905 1 T2 1585 T3 1364 T4 553
valid_sources_3e 413463 1 T2 1582 T3 1297 T4 527
valid_sources_3f 2445819 1 T2 1513 T3 1417 T4 540
valid_sources_40 361104 1 T2 1557 T3 1332 T4 519
valid_sources_41 380405 1 T2 1626 T3 1409 T4 590
valid_sources_42 365154 1 T2 1493 T3 1392 T4 532
valid_sources_43 365130 1 T2 1559 T3 1310 T4 528
valid_sources_44 446150 1 T2 1638 T3 1436 T4 524
valid_sources_45 2743763 1 T2 1585 T3 1365 T4 557
valid_sources_46 362798 1 T2 1619 T3 1311 T4 541
valid_sources_47 482582 1 T2 1536 T3 1323 T4 522
valid_sources_48 480089 1 T2 1587 T3 1438 T4 527
valid_sources_49 377866 1 T2 1581 T3 1394 T4 506
valid_sources_4a 360032 1 T2 1633 T3 1281 T4 505
valid_sources_4b 3449355 1 T2 1705 T3 1445 T4 496
valid_sources_4c 365092 1 T2 1716 T3 1383 T4 504
valid_sources_4d 359888 1 T2 1679 T3 1317 T4 518
valid_sources_4e 363520 1 T2 1692 T3 1279 T4 552
valid_sources_4f 362895 1 T1 38 T2 1617 T3 1443
valid_sources_50 4758889 1 T2 1595 T3 1364 T4 562
valid_sources_51 361044 1 T2 1542 T3 1395 T4 535
valid_sources_52 363903 1 T2 1571 T3 1263 T4 521
valid_sources_53 360782 1 T2 1612 T3 1432 T4 561
valid_sources_54 363254 1 T2 1607 T3 1396 T4 501
valid_sources_55 361643 1 T2 1571 T3 1397 T4 510
valid_sources_56 366325 1 T2 1627 T3 1412 T4 527
valid_sources_57 1005163 1 T2 1634 T3 1390 T4 538
valid_sources_58 364477 1 T2 1519 T3 1404 T4 555
valid_sources_59 371772 1 T2 1535 T3 1335 T4 472
valid_sources_5a 363000 1 T2 1575 T3 1454 T4 565
valid_sources_5b 371411 1 T2 1587 T3 1322 T4 488
valid_sources_5c 362692 1 T2 1610 T3 1368 T4 555
valid_sources_5d 403473 1 T2 1594 T3 1360 T4 509
valid_sources_5e 760468 1 T2 1622 T3 1345 T4 517
valid_sources_5f 372602 1 T2 1589 T3 1317 T4 517
valid_sources_60 360606 1 T2 1527 T3 1383 T4 491
valid_sources_61 449382 1 T2 1647 T3 1405 T4 533
valid_sources_62 504824 1 T2 1722 T3 1377 T4 512
valid_sources_63 363582 1 T2 1585 T3 1388 T4 527
valid_sources_64 361137 1 T2 1576 T3 1393 T4 502
valid_sources_65 373285 1 T2 1629 T3 1365 T4 490
valid_sources_66 362271 1 T2 1602 T3 1304 T4 549
valid_sources_67 363159 1 T2 1641 T3 1376 T4 487
valid_sources_68 365969 1 T2 1485 T3 1479 T4 564
valid_sources_69 419676 1 T2 1589 T3 1361 T4 539
valid_sources_6a 363774 1 T2 1603 T3 1363 T4 571
valid_sources_6b 362997 1 T2 1523 T3 1344 T4 536
valid_sources_6c 380646 1 T2 1657 T3 1417 T4 573
valid_sources_6d 362331 1 T2 1573 T3 1363 T4 571
valid_sources_6e 364844 1 T2 1570 T3 1307 T4 547
valid_sources_6f 369702 1 T2 1663 T3 1353 T4 566
valid_sources_70 392951 1 T2 1590 T3 1320 T4 529
valid_sources_71 365512 1 T2 1674 T3 1295 T4 539
valid_sources_72 361041 1 T2 1722 T3 1390 T4 527
valid_sources_73 362002 1 T2 1592 T3 1410 T4 552
valid_sources_74 1703807 1 T2 1488 T3 1487 T4 545
valid_sources_75 374486 1 T2 1609 T3 1373 T4 546
valid_sources_76 362859 1 T2 1627 T3 1378 T4 529
valid_sources_77 360109 1 T2 1666 T3 1299 T4 568
valid_sources_78 361672 1 T2 1602 T3 1403 T4 473
valid_sources_79 447387 1 T2 1630 T3 1278 T4 595
valid_sources_7a 361679 1 T2 1588 T3 1340 T4 511
valid_sources_7b 465457 1 T2 1555 T3 1434 T4 553
valid_sources_7c 383443 1 T2 1538 T3 1286 T4 562
valid_sources_7d 359405 1 T2 1580 T3 1304 T4 550
valid_sources_7e 361692 1 T2 1616 T3 1357 T4 561
valid_sources_7f 361060 1 T2 1511 T3 1404 T4 521
valid_sources_80 361566 1 T2 1594 T3 1324 T4 521



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 66792947 1 T1 11 T2 203866 T3 175575
values_0 all_enables biggest_size 16939 1 T1 5 T2 9 T3 12
values_1 all_enables biggest_size 14239 1 T2 4 T3 14 T12 16

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%