Module Definition
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Module Instance : tb.dut.u_reg.u_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg0_prescale

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_cfg0_step

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_timer_v_lower0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_timer_v_upper0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_compare_lower0_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_compare_upper0_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_intr_enable0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_intr_state0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_q_buf 100.00 100.00
u_wr_en_buf 100.00 100.00
wr_en_data_arb 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_ctrl
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg0_prescale
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_cfg0_prescale
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg0_step
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_cfg0_step
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timer_v_lower0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_timer_v_lower0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timer_v_upper0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_timer_v_upper0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_compare_lower0_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_compare_lower0_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_compare_upper0_0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_compare_upper0_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_state0
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS4933100.00
ALWAYS6544100.00
CONT_ASSIGN8011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
50 1 1
52 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
80 1 1


Branch Coverage for Instance : tb.dut.u_reg.u_intr_state0
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 49 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 49 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (wr_en_buf)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%