Module Definition
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Module : rv_timer_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 100.00 99.40 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_cfg0_prescale 100.00 100.00 100.00 100.00
u_cfg0_step 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00
u_compare_lower0_0 100.00 100.00 100.00 100.00
u_compare_upper0_0 100.00 100.00 100.00 100.00
u_ctrl 100.00 100.00 100.00 100.00
u_intr_enable0 100.00 100.00 100.00 100.00
u_intr_state0 100.00 100.00 100.00
u_intr_test0 100.00 100.00
u_reg_if 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_timer_v_lower0 100.00 100.00 100.00 100.00
u_timer_v_upper0 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_timer_reg_top
Line No.TotalCoveredPercent
TOTAL5959100.00
ALWAYS5844100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
ALWAYS4141111100.00
CONT_ASSIGN42711100.00
ALWAYS43111100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44811100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN46511100.00
CONT_ASSIGN46611100.00
CONT_ASSIGN46811100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47111100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47411100.00
ALWAYS4781313100.00
CONT_ASSIGN53311100.00
ALWAYS53522100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
59 1 1
60 1 1
61 1 1
MISSING_ELSE
67 1 1
105 1 1
106 1 1
414 1 1
415 1 1
416 1 1
417 1 1
418 1 1
419 1 1
420 1 1
421 1 1
422 1 1
423 1 1
424 1 1
427 1 1
431 1 1
443 1 1
445 1 1
446 1 1
448 1 1
449 1 1
451 1 1
453 1 1
454 1 1
456 1 1
457 1 1
459 1 1
460 1 1
462 1 1
463 1 1
465 1 1
466 1 1
468 1 1
469 1 1
471 1 1
472 1 1
474 1 1
478 1 1
479 1 1
481 1 1
485 1 1
489 1 1
490 1 1
494 1 1
498 1 1
502 1 1
506 1 1
510 1 1
514 1 1
518 1 1
533 1 1
535 1 1
536 1 1
550 1 1
551 1 1


Cond Coverage for Module : rv_timer_reg_top
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       427
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       427
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

Branch Coverage for Module : rv_timer_reg_top
Line No.TotalCoveredPercent
Branches 17 17 100.00
TERNARY 427 2 2 100.00
IF 58 3 3 100.00
CASE 479 11 11 100.00
CASE 536 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 427 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 58 if ((!rst_ni)) -2-: 60 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T10,T11
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 479 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 536 case (1'b1)

Branches:
-1-StatusTests
default Covered T1,T2,T3


Assert Coverage for Module : rv_timer_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 2147483647 134003689 0 0
reAfterRv 2147483647 134003680 0 0
rePulse 2147483647 133675730 0 0
wePulse 2147483647 327950 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 134003689 0 0
T1 836 38 0 0
T2 589296 407225 0 0
T3 953101 352084 0 0
T4 436120 134694 0 0
T12 116274 644091 0 0
T18 116763 46065 0 0
T19 131493 26281 0 0
T20 654247 37874 0 0
T21 845010 10614 0 0
T22 959731 301611 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 134003680 0 0
T1 836 38 0 0
T2 589296 407225 0 0
T3 953101 352084 0 0
T4 436120 134693 0 0
T12 116274 644091 0 0
T18 116763 46065 0 0
T19 131493 26281 0 0
T20 654247 37874 0 0
T21 845010 10614 0 0
T22 959731 301611 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 133675730 0 0
T1 836 20 0 0
T2 589296 407204 0 0
T3 953101 352043 0 0
T4 436120 126615 0 0
T12 116274 644041 0 0
T18 116763 46025 0 0
T19 131493 26218 0 0
T20 654247 37846 0 0
T21 845010 10594 0 0
T22 959731 301581 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 327950 0 0
T1 836 18 0 0
T2 589296 21 0 0
T3 953101 41 0 0
T4 436120 8078 0 0
T12 116274 50 0 0
T18 116763 40 0 0
T19 131493 63 0 0
T20 654247 28 0 0
T21 845010 20 0 0
T22 959731 30 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%