Line Coverage for Module :
rv_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
66 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
132 |
1 |
1 |
Toggle Coverage for Module :
rv_timer
| Total | Covered | Percent |
Totals |
27 |
26 |
96.30 |
Total Bits |
336 |
334 |
99.40 |
Total Bits 0->1 |
168 |
167 |
99.40 |
Total Bits 1->0 |
168 |
167 |
99.40 |
| | | |
Ports |
27 |
26 |
96.30 |
Port Bits |
336 |
334 |
99.40 |
Port Bits 0->1 |
168 |
167 |
99.40 |
Port Bits 1->0 |
168 |
167 |
99.40 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T8,T10,T40 |
Yes |
T8,T10,T40 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T4,T13,T8 |
Yes |
T4,T13,T8 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T12 |
Yes |
T1,T2,T12 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
OUTPUT |
intr_timer_expired_hart0_timer0_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
Assert Coverage for Module :
rv_timer
Assertion Details
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
836 |
751 |
0 |
0 |
T2 |
589296 |
589287 |
0 |
0 |
T3 |
953101 |
953095 |
0 |
0 |
T4 |
436120 |
436107 |
0 |
0 |
T12 |
116274 |
116274 |
0 |
0 |
T18 |
116763 |
116762 |
0 |
0 |
T19 |
131493 |
131492 |
0 |
0 |
T20 |
654247 |
654239 |
0 |
0 |
T21 |
845010 |
845003 |
0 |
0 |
T22 |
959731 |
959726 |
0 |
0 |
IntrTimerExpiredHart0Timer0Known
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
836 |
751 |
0 |
0 |
T2 |
589296 |
589287 |
0 |
0 |
T3 |
953101 |
953095 |
0 |
0 |
T4 |
436120 |
436107 |
0 |
0 |
T12 |
116274 |
116274 |
0 |
0 |
T18 |
116763 |
116762 |
0 |
0 |
T19 |
131493 |
131492 |
0 |
0 |
T20 |
654247 |
654239 |
0 |
0 |
T21 |
845010 |
845003 |
0 |
0 |
T22 |
959731 |
959726 |
0 |
0 |
TlOAReadyKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
836 |
751 |
0 |
0 |
T2 |
589296 |
589287 |
0 |
0 |
T3 |
953101 |
953095 |
0 |
0 |
T4 |
436120 |
436107 |
0 |
0 |
T12 |
116274 |
116274 |
0 |
0 |
T18 |
116763 |
116762 |
0 |
0 |
T19 |
131493 |
131492 |
0 |
0 |
T20 |
654247 |
654239 |
0 |
0 |
T21 |
845010 |
845003 |
0 |
0 |
T22 |
959731 |
959726 |
0 |
0 |
TlODValidKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
836 |
751 |
0 |
0 |
T2 |
589296 |
589287 |
0 |
0 |
T3 |
953101 |
953095 |
0 |
0 |
T4 |
436120 |
436107 |
0 |
0 |
T12 |
116274 |
116274 |
0 |
0 |
T18 |
116763 |
116762 |
0 |
0 |
T19 |
131493 |
131492 |
0 |
0 |
T20 |
654247 |
654239 |
0 |
0 |
T21 |
845010 |
845003 |
0 |
0 |
T22 |
959731 |
959726 |
0 |
0 |