Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 65140609 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 64730334 1 T1 2466 T2 146609 T3 661



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 129486246 1 T1 4822 T2 293855 T3 1357
values_0 52889 1 T1 5 T2 35 T3 3
values_1 331808 1 T1 6 T2 26 T3 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 52957372 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 76913571 1 T1 2899 T2 173611 T3 793



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 369474 1 T1 20 T2 1125 T3 4
valid_sources_01 377577 1 T1 23 T2 1104 T3 5
valid_sources_02 377590 1 T1 18 T2 1095 T3 5
valid_sources_03 368692 1 T1 21 T2 1086 T3 4
valid_sources_04 368740 1 T1 13 T2 1042 T3 3
valid_sources_05 369788 1 T1 14 T2 1249 T3 4
valid_sources_06 373542 1 T1 16 T2 1187 T3 5
valid_sources_07 366054 1 T1 14 T2 1247 T3 5
valid_sources_08 368742 1 T1 20 T2 1111 T3 5
valid_sources_09 2405350 1 T1 20 T2 1177 T3 5
valid_sources_0a 370360 1 T1 18 T2 1181 T3 5
valid_sources_0b 370258 1 T1 23 T2 1260 T3 5
valid_sources_0c 373674 1 T1 23 T2 1198 T3 7
valid_sources_0d 368516 1 T1 17 T2 1089 T3 4
valid_sources_0e 368820 1 T1 12 T2 1122 T3 6
valid_sources_0f 802579 1 T1 15 T2 1168 T3 2
valid_sources_10 367690 1 T1 15 T2 1314 T3 4
valid_sources_11 367884 1 T1 16 T2 1132 T3 6
valid_sources_12 371494 1 T1 10 T2 1287 T3 5
valid_sources_13 375611 1 T1 19 T2 1159 T3 8
valid_sources_14 370274 1 T1 12 T2 1091 T3 5
valid_sources_15 370247 1 T1 16 T2 1157 T3 2
valid_sources_16 368220 1 T1 28 T2 1185 T3 7
valid_sources_17 369030 1 T1 24 T2 1172 T3 6
valid_sources_18 456080 1 T1 20 T2 1015 T3 2
valid_sources_19 367042 1 T1 20 T2 1106 T3 6
valid_sources_1a 381627 1 T1 13 T2 1142 T3 6
valid_sources_1b 366586 1 T1 11 T2 1125 T3 4
valid_sources_1c 367445 1 T1 17 T2 1024 T3 3
valid_sources_1d 367254 1 T1 30 T2 1195 T3 3
valid_sources_1e 371758 1 T1 17 T2 1118 T3 3
valid_sources_1f 387043 1 T1 14 T2 1174 T3 9
valid_sources_20 372859 1 T1 17 T2 1228 T3 5
valid_sources_21 398675 1 T1 22 T2 1124 T3 3
valid_sources_22 428589 1 T1 19 T2 1030 T3 2
valid_sources_23 387182 1 T1 22 T2 1157 T3 7
valid_sources_24 372146 1 T1 19 T2 1043 T3 7
valid_sources_25 369619 1 T1 13 T2 1180 T3 3
valid_sources_26 386945 1 T1 19 T2 1138 T3 4
valid_sources_27 372609 1 T1 17 T2 1094 T3 4
valid_sources_28 370583 1 T1 29 T2 1047 T3 7
valid_sources_29 5005426 1 T1 18 T2 1098 T3 5
valid_sources_2a 3216231 1 T1 10 T2 1189 T3 5
valid_sources_2b 369864 1 T1 17 T2 1023 T3 6
valid_sources_2c 372030 1 T1 23 T2 1112 T3 8
valid_sources_2d 371752 1 T1 22 T2 1157 T3 5
valid_sources_2e 2090575 1 T1 25 T2 1111 T3 3
valid_sources_2f 367725 1 T1 17 T2 1180 T3 8
valid_sources_30 370512 1 T1 22 T2 1192 T3 4
valid_sources_31 540663 1 T1 18 T2 1364 T3 7
valid_sources_32 434881 1 T1 10 T2 1175 T3 9
valid_sources_33 373356 1 T1 24 T2 1175 T3 2
valid_sources_34 372282 1 T1 22 T2 1270 T3 1
valid_sources_35 372533 1 T1 11 T2 1077 T3 7
valid_sources_36 369519 1 T1 14 T2 1215 T3 7
valid_sources_37 430179 1 T1 14 T2 1229 T3 5
valid_sources_38 372352 1 T1 17 T2 1169 T3 4
valid_sources_39 685146 1 T1 16 T2 1134 T3 5
valid_sources_3a 365746 1 T1 25 T2 1174 T3 4
valid_sources_3b 368912 1 T1 22 T2 1140 T3 3
valid_sources_3c 371504 1 T1 25 T2 1274 T3 6
valid_sources_3d 368606 1 T1 24 T2 1160 T3 4
valid_sources_3e 380089 1 T1 24 T2 1156 T3 5
valid_sources_3f 635344 1 T1 21 T2 1047 T3 3
valid_sources_40 372005 1 T1 13 T2 1218 T3 7
valid_sources_41 371026 1 T1 18 T2 1175 T3 5
valid_sources_42 532073 1 T1 14 T2 1238 T3 5
valid_sources_43 367863 1 T1 24 T2 1134 T3 6
valid_sources_44 369668 1 T1 12 T2 1107 T3 6
valid_sources_45 372389 1 T1 22 T2 1276 T3 5
valid_sources_46 370793 1 T1 16 T2 1112 T3 6
valid_sources_47 367020 1 T1 18 T2 1200 T3 7
valid_sources_48 371061 1 T1 16 T2 1170 T3 5
valid_sources_49 366816 1 T1 18 T2 1045 T3 6
valid_sources_4a 373586 1 T1 26 T2 1109 T3 5
valid_sources_4b 385077 1 T1 12 T2 1274 T3 3
valid_sources_4c 371333 1 T1 20 T2 1241 T3 6
valid_sources_4d 366925 1 T1 17 T2 1109 T3 4
valid_sources_4e 956352 1 T1 26 T2 1178 T3 6
valid_sources_4f 369518 1 T1 11 T2 1041 T3 6
valid_sources_50 371152 1 T1 19 T2 993 T3 5
valid_sources_51 528231 1 T1 20 T2 1166 T3 7
valid_sources_52 792968 1 T1 14 T2 1226 T3 7
valid_sources_53 373851 1 T1 15 T2 1113 T3 1
valid_sources_54 369148 1 T1 17 T2 970 T3 9
valid_sources_55 374310 1 T1 13 T2 1159 T3 10
valid_sources_56 554391 1 T1 21 T2 1145 T3 7
valid_sources_57 369052 1 T1 33 T2 1142 T3 4
valid_sources_58 427117 1 T1 26 T2 1228 T3 4
valid_sources_59 373668 1 T1 19 T2 1247 T3 6
valid_sources_5a 372036 1 T1 23 T2 1130 T3 6
valid_sources_5b 376597 1 T1 17 T2 1142 T3 4
valid_sources_5c 370629 1 T1 22 T2 1198 T3 5
valid_sources_5d 369652 1 T1 12 T2 1081 T3 5
valid_sources_5e 367743 1 T1 17 T2 1201 T3 3
valid_sources_5f 568916 1 T1 11 T2 1068 T3 3
valid_sources_60 368384 1 T1 10 T2 1066 T3 3
valid_sources_61 421907 1 T1 17 T2 1185 T3 2
valid_sources_62 370352 1 T1 11 T2 1133 T3 5
valid_sources_63 369282 1 T1 19 T2 1141 T3 4
valid_sources_64 370591 1 T1 18 T2 1037 T3 4
valid_sources_65 367182 1 T1 28 T2 1098 T3 11
valid_sources_66 368824 1 T1 18 T2 1138 T3 4
valid_sources_67 370730 1 T1 21 T2 1250 T3 4
valid_sources_68 370944 1 T1 17 T2 1155 T15 21
valid_sources_69 375139 1 T1 18 T2 1150 T3 6
valid_sources_6a 374169 1 T1 14 T2 1181 T3 5
valid_sources_6b 406995 1 T1 22 T2 1048 T3 6
valid_sources_6c 374864 1 T1 8 T2 1227 T3 7
valid_sources_6d 370669 1 T1 13 T2 1143 T3 8
valid_sources_6e 372700 1 T1 16 T2 1068 T3 6
valid_sources_6f 370443 1 T1 23 T2 1281 T3 3
valid_sources_70 380641 1 T1 14 T2 1116 T3 4
valid_sources_71 374112 1 T1 11 T2 1108 T3 5
valid_sources_72 374152 1 T1 22 T2 1174 T3 10
valid_sources_73 369264 1 T1 31 T2 1044 T3 7
valid_sources_74 372388 1 T1 29 T2 1134 T3 4
valid_sources_75 368679 1 T1 22 T2 1161 T3 4
valid_sources_76 379127 1 T1 19 T2 1039 T3 7
valid_sources_77 702844 1 T1 13 T2 969 T3 6
valid_sources_78 395847 1 T1 18 T2 1177 T3 7
valid_sources_79 370532 1 T1 10 T2 1122 T3 7
valid_sources_7a 369876 1 T1 13 T2 1283 T3 5
valid_sources_7b 367005 1 T1 29 T2 1055 T3 8
valid_sources_7c 378549 1 T1 28 T2 1130 T3 6
valid_sources_7d 369626 1 T1 18 T2 1085 T3 7
valid_sources_7e 369104 1 T1 32 T2 1092 T3 2
valid_sources_7f 468373 1 T1 21 T2 1055 T15 12
valid_sources_80 410770 1 T1 17 T2 1206 T3 9



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 64698977 1 T1 2460 T2 146569 T3 656
values_0 all_enables biggest_size 16973 1 T1 3 T2 26 T3 3
values_1 all_enables biggest_size 14384 1 T1 3 T2 14 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%