Module Definition
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Module : prim_alert_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alert_tx[0].u_prim_alert_sender 91.67 91.67



Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 100.00 99.40 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 11 91.67
Total Bits 24 22 91.67
Total Bits 0->1 12 11 91.67
Total Bits 1->0 12 11 91.67

Ports 12 11 91.67
Port Bits 24 22 91.67
Port Bits 0->1 12 11 91.67
Port Bits 1->0 12 11 91.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
alert_req_i Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_ack_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_state_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
alert_rx_i.ping_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT

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