Unified Coverage Report :: Module :: prim_subreg

Module : prim_subreg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_ctrl	100.00	100.00				100.00
tb.dut.u_reg.u_cfg0_prescale	100.00	100.00				100.00
tb.dut.u_reg.u_cfg0_step	100.00	100.00				100.00
tb.dut.u_reg.u_timer_v_lower0	100.00	100.00				100.00
tb.dut.u_reg.u_timer_v_upper0	100.00	100.00				100.00
tb.dut.u_reg.u_compare_lower0_0	100.00	100.00				100.00
tb.dut.u_reg.u_compare_upper0_0	100.00	100.00				100.00
tb.dut.u_reg.u_intr_enable0	100.00	100.00				100.00
tb.dut.u_reg.u_intr_state0	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg0_prescale

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg0_step

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_timer_v_lower0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_timer_v_upper0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_compare_lower0_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_compare_upper0_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_intr_enable0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_intr_state0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_q_buf	100.00	100.00
u_wr_en_buf	100.00	100.00
wr_en_data_arb	100.00	100.00

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_ctrl

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg0_prescale

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg0_prescale

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg0_step

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg0_step

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timer_v_lower0

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_timer_v_lower0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_timer_v_upper0

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_timer_v_upper0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_compare_lower0_0

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_compare_lower0_0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_compare_upper0_0

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_compare_upper0_0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable0

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_state0

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	49	3	3	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	80	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
80	1	1

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_state0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	49	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	49	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (wr_en_buf)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3