Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.80 100.00 99.40 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 99.80 100.00 99.40 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.80 100.00 99.40 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 100.00 100.00 98.89 100.00 99.34


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 91.67 91.67
gen_harts[0].u_core 100.00 100.00 100.00
gen_harts[0].u_intr_hw 100.00 100.00 100.00
rv_timer_csr_assert 100.00 100.00 100.00 100.00 100.00
tlul_assert_device 99.77 100.00 100.00 99.30
u_reg 100.00 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_timer
Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
66 1 1
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
74 1 1
132 1 1

Toggle Coverage for Module : rv_timer
TotalCoveredPercent
Totals 27 26 96.30
Total Bits 336 334 99.40
Total Bits 0->1 168 167 99.40
Total Bits 1->0 168 167 99.40

Ports 27 26 96.30
Port Bits 336 334 99.40
Port Bits 0->1 168 167 99.40
Port Bits 1->0 168 167 99.40

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T10,T36,T37 Yes T10,T36,T37 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T6,T13,T14 Yes T6,T13,T14 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T15 Yes T1,T2,T15 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes T1,T2,T15 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
intr_timer_expired_hart0_timer0_o Yes Yes T1,T2,T16 Yes T1,T2,T16 OUTPUT

Assert Coverage for Module : rv_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 2147483647 2147483647 0 0
IntrTimerExpiredHart0Timer0Known 2147483647 2147483647 0 0
TlOAReadyKnown 2147483647 2147483647 0 0
TlODValidKnown 2147483647 2147483647 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 113966 113957 0 0
T2 140942 140942 0 0
T3 270729 270723 0 0
T4 41452 41340 0 0
T5 409043 409030 0 0
T15 709618 709611 0 0
T16 373208 373208 0 0
T17 142116 142116 0 0
T18 226009 226008 0 0
T19 124627 124626 0 0

IntrTimerExpiredHart0Timer0Known
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 113966 113957 0 0
T2 140942 140942 0 0
T3 270729 270723 0 0
T4 41452 41340 0 0
T5 409043 409030 0 0
T15 709618 709611 0 0
T16 373208 373208 0 0
T17 142116 142116 0 0
T18 226009 226008 0 0
T19 124627 124626 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 113966 113957 0 0
T2 140942 140942 0 0
T3 270729 270723 0 0
T4 41452 41340 0 0
T5 409043 409030 0 0
T15 709618 709611 0 0
T16 373208 373208 0 0
T17 142116 142116 0 0
T18 226009 226008 0 0
T19 124627 124626 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 113966 113957 0 0
T2 140942 140942 0 0
T3 270729 270723 0 0
T4 41452 41340 0 0
T5 409043 409030 0 0
T15 709618 709611 0 0
T16 373208 373208 0 0
T17 142116 142116 0 0
T18 226009 226008 0 0
T19 124627 124626 0 0

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