Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 100.00 100.00 98.89 100.00 99.34


Total modules in report: 23
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_alert_sender 91.67 91.67
tlul_assert 99.77 100.00 100.00 99.30
rv_timer 99.80 100.00 99.40 100.00
rv_timer_reg_top 100.00 100.00 100.00 100.00 100.00
rv_timer_csr_assert_fpv 100.00 100.00 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
tlul_rsp_intg_gen 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00
prim_secded_64_57_dec 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 + DW=12,SwAccess=0 + DW=8,SwAccess=0 + DW=32,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3 ) 100.00 100.00
prim_subreg_arb ( parameter DW=12,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0 ) 100.00 100.00
prim_secded_39_32_enc 100.00 100.00
tlul_adapter_reg 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_64_57_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
timer_core 100.00 100.00 100.00
prim_secded_39_32_dec 100.00 100.00
tlul_data_integ_enc
prim_buf
tb
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