Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 67917357 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 67529158 1 T1 9 T2 2186 T3 1546



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 135077525 1 T1 11 T2 4317 T3 3784
values_0 50687 1 T1 4 T2 6 T3 392
values_1 318303 1 T1 5 T2 4 T3 3278



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 55232059 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 80214456 1 T1 12 T2 2569 T3 4401



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 514388 1 T2 20 T3 11 T15 71
valid_sources_01 417052 1 T2 22 T3 20 T15 95
valid_sources_02 421194 1 T2 13 T3 52 T15 86
valid_sources_03 423960 1 T2 14 T3 11 T15 82
valid_sources_04 416927 1 T2 31 T3 31 T15 78
valid_sources_05 418956 1 T2 18 T3 20 T15 91
valid_sources_06 417802 1 T2 19 T3 15 T15 70
valid_sources_07 433276 1 T2 15 T3 30 T15 97
valid_sources_08 429054 1 T2 22 T3 93 T15 93
valid_sources_09 419311 1 T2 12 T3 24 T15 94
valid_sources_0a 456328 1 T2 12 T3 31 T15 85
valid_sources_0b 421115 1 T2 16 T3 31 T15 58
valid_sources_0c 422029 1 T2 17 T3 22 T15 97
valid_sources_0d 417540 1 T2 22 T3 27 T15 80
valid_sources_0e 418760 1 T2 29 T3 29 T15 81
valid_sources_0f 420089 1 T2 20 T3 32 T15 91
valid_sources_10 418729 1 T2 11 T3 19 T15 73
valid_sources_11 422938 1 T2 26 T3 23 T15 77
valid_sources_12 424616 1 T2 17 T3 23 T15 96
valid_sources_13 419937 1 T2 8 T3 22 T15 84
valid_sources_14 433113 1 T2 34 T3 32 T15 88
valid_sources_15 423833 1 T2 13 T3 50 T15 64
valid_sources_16 418564 1 T2 14 T3 17 T15 63
valid_sources_17 917494 1 T2 13 T3 30 T15 87
valid_sources_18 1601045 1 T2 7 T3 29 T15 85
valid_sources_19 419330 1 T2 35 T3 22 T15 81
valid_sources_1a 423422 1 T2 15 T3 44 T15 73
valid_sources_1b 423000 1 T2 18 T3 17 T15 81
valid_sources_1c 424155 1 T2 20 T3 42 T15 71
valid_sources_1d 431152 1 T2 14 T3 24 T15 73
valid_sources_1e 448971 1 T2 34 T3 37 T15 80
valid_sources_1f 419682 1 T2 19 T3 30 T15 63
valid_sources_20 420824 1 T2 28 T3 51 T15 81
valid_sources_21 421127 1 T2 15 T3 15 T15 81
valid_sources_22 420646 1 T2 18 T3 28 T15 89
valid_sources_23 421528 1 T2 12 T3 11 T15 89
valid_sources_24 435868 1 T2 8 T3 35 T15 65
valid_sources_25 422603 1 T2 18 T3 47 T15 85
valid_sources_26 446373 1 T2 21 T3 17 T15 80
valid_sources_27 1328697 1 T2 24 T3 28 T15 74
valid_sources_28 571035 1 T2 16 T3 22 T15 93
valid_sources_29 419311 1 T2 25 T3 20 T15 62
valid_sources_2a 421955 1 T2 16 T3 24 T15 89
valid_sources_2b 419967 1 T2 9 T3 14 T15 77
valid_sources_2c 416776 1 T2 22 T3 25 T15 88
valid_sources_2d 419254 1 T2 22 T3 33 T15 85
valid_sources_2e 567917 1 T2 18 T3 16 T15 107
valid_sources_2f 420032 1 T2 24 T3 11 T15 78
valid_sources_30 419734 1 T2 17 T3 26 T15 70
valid_sources_31 417405 1 T2 15 T3 27 T15 90
valid_sources_32 511941 1 T2 13 T3 41 T15 67
valid_sources_33 432851 1 T2 14 T3 22 T15 82
valid_sources_34 417693 1 T2 11 T3 77 T15 74
valid_sources_35 420524 1 T2 30 T3 27 T15 95
valid_sources_36 420091 1 T2 9 T3 28 T15 85
valid_sources_37 419921 1 T2 14 T3 12 T15 64
valid_sources_38 430475 1 T2 18 T3 22 T15 68
valid_sources_39 416763 1 T2 26 T3 16 T15 77
valid_sources_3a 602624 1 T2 2 T3 23 T15 63
valid_sources_3b 420549 1 T2 14 T3 30 T15 88
valid_sources_3c 420160 1 T2 9 T3 15 T15 82
valid_sources_3d 1288255 1 T2 20 T3 34 T15 66
valid_sources_3e 422029 1 T2 11 T3 55 T15 103
valid_sources_3f 1091765 1 T2 15 T3 11 T15 121
valid_sources_40 463115 1 T2 21 T3 58 T15 102
valid_sources_41 640197 1 T2 16 T3 21 T15 91
valid_sources_42 418692 1 T2 17 T3 18 T15 79
valid_sources_43 432458 1 T2 15 T3 22 T15 81
valid_sources_44 421610 1 T2 16 T3 81 T15 92
valid_sources_45 421341 1 T2 28 T3 49 T15 68
valid_sources_46 421474 1 T2 7 T3 14 T15 124
valid_sources_47 417289 1 T2 14 T3 18 T15 90
valid_sources_48 416007 1 T2 11 T3 27 T15 78
valid_sources_49 421912 1 T2 30 T3 21 T15 79
valid_sources_4a 2025307 1 T2 10 T3 50 T15 64
valid_sources_4b 2143284 1 T2 20 T3 40 T15 72
valid_sources_4c 421491 1 T2 15 T3 23 T15 76
valid_sources_4d 1364208 1 T2 8 T3 20 T15 76
valid_sources_4e 420219 1 T2 12 T3 26 T15 99
valid_sources_4f 419281 1 T2 20 T3 24 T15 73
valid_sources_50 979596 1 T2 14 T3 22 T15 90
valid_sources_51 420159 1 T2 10 T3 28 T15 79
valid_sources_52 420712 1 T2 6 T3 35 T15 89
valid_sources_53 420933 1 T2 15 T3 22 T15 85
valid_sources_54 420964 1 T2 16 T3 38 T15 85
valid_sources_55 422224 1 T2 13 T3 32 T15 56
valid_sources_56 423488 1 T2 10 T3 38 T15 100
valid_sources_57 421316 1 T2 21 T3 17 T15 71
valid_sources_58 548700 1 T2 16 T3 40 T15 84
valid_sources_59 418538 1 T2 26 T3 25 T15 97
valid_sources_5a 421699 1 T2 8 T3 30 T15 69
valid_sources_5b 418637 1 T2 16 T3 16 T15 82
valid_sources_5c 420435 1 T2 8 T3 32 T15 98
valid_sources_5d 418478 1 T2 16 T3 35 T15 75
valid_sources_5e 423369 1 T2 21 T3 73 T15 95
valid_sources_5f 420608 1 T2 23 T3 25 T15 72
valid_sources_60 416807 1 T2 22 T3 15 T15 91
valid_sources_61 421261 1 T2 11 T3 27 T15 97
valid_sources_62 423820 1 T2 16 T3 85 T15 82
valid_sources_63 417872 1 T2 15 T3 17 T15 102
valid_sources_64 429159 1 T2 24 T3 64 T15 100
valid_sources_65 3796047 1 T2 14 T3 18 T15 88
valid_sources_66 423097 1 T2 8 T3 94 T15 90
valid_sources_67 429432 1 T2 9 T3 35 T15 79
valid_sources_68 418330 1 T2 30 T3 13 T15 83
valid_sources_69 419542 1 T2 21 T3 54 T15 72
valid_sources_6a 422052 1 T2 15 T3 38 T15 78
valid_sources_6b 421228 1 T2 23 T3 19 T15 101
valid_sources_6c 418820 1 T2 13 T3 10 T15 87
valid_sources_6d 419871 1 T2 14 T3 14 T15 70
valid_sources_6e 2959252 1 T2 9 T3 11 T15 91
valid_sources_6f 420886 1 T2 4 T3 32 T15 93
valid_sources_70 418376 1 T2 10 T3 27 T15 96
valid_sources_71 418887 1 T2 25 T3 26 T15 50
valid_sources_72 490139 1 T2 6 T3 33 T15 87
valid_sources_73 419685 1 T2 9 T3 23 T15 59
valid_sources_74 419707 1 T2 14 T3 22 T15 87
valid_sources_75 419894 1 T2 17 T3 23 T15 77
valid_sources_76 449676 1 T2 11 T3 33 T15 75
valid_sources_77 420681 1 T2 22 T3 26 T15 104
valid_sources_78 421312 1 T2 23 T3 21 T15 78
valid_sources_79 419601 1 T2 26 T3 24 T15 92
valid_sources_7a 419050 1 T2 16 T3 20 T15 79
valid_sources_7b 415905 1 T2 18 T3 16 T15 98
valid_sources_7c 546969 1 T2 10 T3 12 T15 88
valid_sources_7d 442025 1 T2 10 T3 24 T15 89
valid_sources_7e 418408 1 T2 11 T3 20 T15 95
valid_sources_7f 428524 1 T2 13 T3 21 T15 69
valid_sources_80 444663 1 T2 16 T3 23 T15 83



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 67499468 1 T1 7 T2 2178 T3 1437
values_0 all_enables biggest_size 16177 1 T1 2 T2 6 T3 64
values_1 all_enables biggest_size 13513 1 T2 2 T3 45 T15 10

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%