Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_subreg_ext
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_alert_test 100.00 100.00
tb.dut.u_reg.u_intr_test0 100.00 100.00



Module Instance : tb.dut.u_reg.u_alert_test

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2300
CONT_ASSIGN2411100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 unreachable
24 1 1
25 1 1
26 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_alert_test
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2300
CONT_ASSIGN2411100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 unreachable
24 1 1
25 1 1
26 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_intr_test0
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2300
CONT_ASSIGN2411100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN2600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 unreachable
24 1 1
25 1 1
26 unreachable

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%