Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	100.00		99.40			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_timer_csr_assert_fpv

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	53	8	8	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	80	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv' or '../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
45	1	1
46	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
76	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
			MISSING_ELSE
99	1	1
100	1	1
101	1	1
102	1	1
			MISSING_ELSE
104	1	1
			MISSING_ELSE
106	1	1
107	1	1
			MISSING_ELSE
			MISSING_ELSE

---

Cond Coverage for Module : rv_timer_csr_assert_fpv

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (h2d.a_mask[0] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (h2d.a_mask[1] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       45
 EXPRESSION (h2d.a_mask[2] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 EXPRESSION (h2d.a_mask[3] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (h2d.a_valid && d2h.a_ready)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T11
1	1	Covered	T1,T2,T3

 LINE       106
 EXPRESSION (h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1))
             -----1-----    ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : rv_timer_csr_assert_fpv

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	43	2	2	100.00
TERNARY	44	2	2	100.00
TERNARY	45	2	2	100.00
TERNARY	46	2	2	100.00
CASE	53	8	8	100.00
IF	80	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv' or '../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	43	(h2d.a_mask[0]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	44	(h2d.a_mask[1]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	45	(h2d.a_mask[2]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	46	(h2d.a_mask[3]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	53	case (pend_trans[d2h.d_source].addr)

Branches:

-1-	Status	Tests
0	Covered	T1,T2,T3
4	Covered	T1,T2,T3
256	Covered	T1,T2,T3
268	Covered	T1,T2,T3
272	Covered	T1,T2,T3
276	Covered	T1,T2,T3
284	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	80	if ((!rst_ni))
-2-:	90	if ((h2d.a_valid && d2h.a_ready))
-3-:	92	if ((h2d.a_opcode inside {PutFullData, PutPartialData}))
-4-:	95	if ((h2d.a_opcode == Get))
-5-:	99	if (d2h.d_valid)
-6-:	100	if ((pend_trans[d2h.d_source].wr_pending == 1'b1))
-7-:	101	if ((!d2h.d_error))
-8-:	106	if ((h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T2,T3
0	1	0	1	-	-	-	-	Covered	T1,T2,T3
0	1	0	0	-	-	-	-	Covered	T3,T4,T11
0	0	-	-	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	1	1	-	Covered	T1,T2,T3
0	-	-	-	1	1	0	-	Covered	T3,T4,T11
0	-	-	-	1	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	-	1	Covered	T1,T2,T3
0	-	-	-	1	-	-	0	Covered	T1,T2,T3
0	-	-	-	0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
cfg0_rd_A	2147483647	10306	0	0
compare_lower0_0_rd_A	2147483647	7167	0	0
compare_upper0_0_rd_A	2147483647	10309	0	0
ctrl_rd_A	2147483647	7323	0	0
intr_enable0_rd_A	2147483647	8944	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10306	0	0
T18	553827	978	0	0
T22	613267	789	0	0
T23	264219	532	0	0
T27	322747	535	0	0
T30	482078	796	0	0
T31	874711	1436	0	0
T38	471360	878	0	0
T39	414487	822	0	0
T40	395933	623	0	0
T41	979839	1379	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7167	0	0
T18	553827	671	0	0
T22	613267	439	0	0
T23	264219	440	0	0
T27	322747	308	0	0
T30	482078	545	0	0
T31	874711	1075	0	0
T38	471360	661	0	0
T39	414487	651	0	0
T40	395933	474	0	0
T41	979839	898	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10309	0	0
T18	553827	850	0	0
T22	613267	718	0	0
T23	264219	561	0	0
T27	322747	475	0	0
T30	482078	722	0	0
T31	874711	1673	0	0
T38	471360	861	0	0
T39	414487	896	0	0
T40	395933	762	0	0
T41	979839	1302	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323	0	0
T18	553827	724	0	0
T22	613267	526	0	0
T23	264219	375	0	0
T27	322747	364	0	0
T30	482078	466	0	0
T31	874711	1095	0	0
T38	471360	542	0	0
T39	414487	675	0	0
T40	395933	498	0	0
T41	979839	978	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8944	0	0
T18	553827	696	0	0
T22	613267	637	0	0
T23	264219	507	0	0
T27	322747	560	0	0
T30	482078	666	0	0
T38	471360	721	0	0
T42	101667	31	0	0
T43	481	13	0	0
T44	553784	49	0	0
T45	514863	32	0	0