d498f91d6d498f91d6| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 195 | 200 | 97.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 250 | 255 | 98.04 | |
| V2 | random_reset | rv_timer_random_reset | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 49 | 50 | 98.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 49 | 50 | 98.00 |
| V2 | stress | rv_timer_stress_all | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 49 | 50 | 98.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |
| V2S | tl_intg_err | rv_timer_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |
| TOTAL | 607 | 615 | 98.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.18 | 100.00 | 84.08 | 100.00 | -- | 100.00 | 99.36 | 99.66 |
Exit reason: Error: User command failed Job returned non-zero exit code has 8 failures:
Test rv_timer_same_csr_outstanding has 1 failures.
13.rv_timer_same_csr_outstanding.1691001069
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/out/run.log
[make]: simulate
cd /workspace/13.rv_timer_same_csr_outstanding/out && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691001069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.1691001069
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 01:22 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
Test rv_timer_intr_test has 1 failures.
31.rv_timer_intr_test.3816173449
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_intr_test/out/run.log
[make]: simulate
cd /workspace/31.rv_timer_intr_test/out && /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816173449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3816173449
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 01:22 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
Test rv_timer_cfg_update_on_fly has 1 failures.
40.rv_timer_cfg_update_on_fly.3049517782
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/out/run.log
[make]: simulate
cd /workspace/40.rv_timer_cfg_update_on_fly/out && /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049517782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3049517782
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 01:20 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
Test rv_timer_random has 5 failures.
71.rv_timer_random.3162073213
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/71.rv_timer_random/out/run.log
[make]: simulate
cd /workspace/71.rv_timer_random/out && /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162073213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3162073213
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 01:23 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
100.rv_timer_random.2128600574
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/100.rv_timer_random/out/run.log
[make]: simulate
cd /workspace/100.rv_timer_random/out && /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128600574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2128600574
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 01:24 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
... and 3 more failures.