RV_TIMER Simulation Results

Wednesday May 18 2022 08:08:47 UTC

GitHub Revision: d498f91d6
Foundry Revision: d498f91d6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1087921459

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 random rv_timer_random 195 200 97.50
V1 csr_hw_reset rv_timer_csr_hw_reset 5 5 100.00
V1 csr_rw rv_timer_csr_rw 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 20 20 100.00
rv_timer_csr_aliasing 5 5 100.00
V1 TOTAL 250 255 98.04
V2 random_reset rv_timer_random_reset 50 50 100.00
V2 disabled rv_timer_disabled 50 50 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 49 50 98.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 49 50 98.00
V2 stress rv_timer_stress_all 50 50 100.00
V2 intr_test rv_timer_intr_test 49 50 98.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 5 5 100.00
rv_timer_csr_rw 20 20 100.00
rv_timer_csr_aliasing 5 5 100.00
rv_timer_same_csr_outstanding 19 20 95.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 5 5 100.00
rv_timer_csr_rw 20 20 100.00
rv_timer_csr_aliasing 5 5 100.00
rv_timer_same_csr_outstanding 19 20 95.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err rv_timer_tl_intg_err 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 607 615 98.70

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 7 7 4 57.14
V2S 2 1 1 50.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.18 100.00 84.08 100.00 -- 100.00 99.36 99.66

Failure Buckets

Past Results