RV_TIMER Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 35.506m 109.037ms 191 200 95.50
V1 csr_hw_reset rv_timer_csr_hw_reset 0.630s 27.051us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.630s 16.619us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.530s 1.843ms 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.870s 135.618us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.410s 30.096us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.630s 16.619us 20 20 100.00
rv_timer_csr_aliasing 0.870s 135.618us 5 5 100.00
V1 TOTAL 246 255 96.47
V2 random_reset rv_timer_random_reset 24.065m 46.795ms 50 50 100.00
V2 disabled rv_timer_disabled 4.961m 232.291ms 48 50 96.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 16.230m 1.045s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 16.230m 1.045s 50 50 100.00
V2 stress rv_timer_stress_all 1.006h 1.457s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.650s 41.081us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.530s 375.434us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.530s 375.434us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.630s 27.051us 5 5 100.00
rv_timer_csr_rw 0.630s 16.619us 20 20 100.00
rv_timer_csr_aliasing 0.870s 135.618us 5 5 100.00
rv_timer_same_csr_outstanding 0.820s 56.326us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.630s 27.051us 5 5 100.00
rv_timer_csr_rw 0.630s 16.619us 20 20 100.00
rv_timer_csr_aliasing 0.870s 135.618us 5 5 100.00
rv_timer_same_csr_outstanding 0.820s 56.326us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err rv_timer_sec_cm 0.940s 97.603us 5 5 100.00
rv_timer_tl_intg_err 1.400s 451.271us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.400s 451.271us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 22.476m 99.028ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 609 620 98.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.65 99.38 98.73 100.00 -- 100.00 100.00 99.77

Failure Buckets

Past Results