RV_TIMER Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 58.114m 246.569ms 194 200 97.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.580s 50.300us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.640s 14.449us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.030s 90.843us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.830s 243.181us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.310s 160.778us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.640s 14.449us 20 20 100.00
rv_timer_csr_aliasing 0.830s 243.181us 5 5 100.00
V1 TOTAL 249 255 97.65
V2 random_reset rv_timer_random_reset 28.166m 49.207ms 49 50 98.00
V2 disabled rv_timer_disabled 5.338m 200.174ms 46 50 92.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 34.836m 5.882s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 34.836m 5.882s 50 50 100.00
V2 stress rv_timer_stress_all 1.933h 2.834s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.610s 27.549us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 2.750s 60.454us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 2.750s 60.454us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.580s 50.300us 5 5 100.00
rv_timer_csr_rw 0.640s 14.449us 20 20 100.00
rv_timer_csr_aliasing 0.830s 243.181us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 36.789us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.580s 50.300us 5 5 100.00
rv_timer_csr_rw 0.640s 14.449us 20 20 100.00
rv_timer_csr_aliasing 0.830s 243.181us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 36.789us 20 20 100.00
V2 TOTAL 285 290 98.28
V2S tl_intg_err rv_timer_sec_cm 0.900s 306.280us 5 5 100.00
rv_timer_tl_intg_err 1.410s 210.118us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.410s 210.118us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 20.117m 203.961ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 609 620 98.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 7 7 5 71.43
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.57 99.38 98.73 100.00 -- 100.00 100.00 99.32

Failure Buckets

Past Results