RV_TIMER Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	45.343m	361.831ms	198	200	99.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.590s	32.138us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.600s	28.926us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.230s	187.757us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.640s	72.282us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.860s	71.748us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.600s	28.926us	20	20	100.00
		rv_timer_csr_aliasing	0.640s	72.282us	5	5	100.00
V1		TOTAL			253	255	99.22
V2	random_reset	rv_timer_random_reset	31.521m	718.008ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.849m	678.518ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	16.387m	1.078s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	16.387m	1.078s	50	50	100.00
V2	stress	rv_timer_stress_all	50.754m	515.679ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.610s	14.410us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.420s	677.934us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.420s	677.934us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.590s	32.138us	5	5	100.00
		rv_timer_csr_rw	0.600s	28.926us	20	20	100.00
		rv_timer_csr_aliasing	0.640s	72.282us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	152.681us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.590s	32.138us	5	5	100.00
		rv_timer_csr_rw	0.600s	28.926us	20	20	100.00
		rv_timer_csr_aliasing	0.640s	72.282us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	152.681us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	335.302us	5	5	100.00
		rv_timer_tl_intg_err	1.300s	231.880us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.300s	231.880us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	30.426m	289.804ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			614	620	99.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.38	98.73	100.00	--	100.00	100.00	99.77

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:

Test rv_timer_disabled has 3 failures.

6.rv_timer_disabled.849260388
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.rv_timer_disabled.1431329544
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_timer_stress_all has 1 failures.

22.rv_timer_stress_all.586770603
Line 246, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_random has 2 failures.

50.rv_timer_random.2448144605
Line 219, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/50.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

160.rv_timer_random.1720207441
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/160.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---