RV_TIMER Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	51.510m	1.000s	194	200	97.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.600s	134.249us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.660s	84.755us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.220s	470.052us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.790s	33.085us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.550s	400.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.660s	84.755us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	33.085us	5	5	100.00
V1		TOTAL			249	255	97.65
V2	random_reset	rv_timer_random_reset	21.306m	77.341ms	49	50	98.00
V2	disabled	rv_timer_disabled	4.476m	326.309ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	21.088m	2.317s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	21.088m	2.317s	50	50	100.00
V2	stress	rv_timer_stress_all	1.700h	370.561ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.630s	45.688us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.780s	58.762us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.780s	58.762us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.600s	134.249us	5	5	100.00
		rv_timer_csr_rw	0.660s	84.755us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	33.085us	5	5	100.00
		rv_timer_same_csr_outstanding	0.870s	45.496us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.600s	134.249us	5	5	100.00
		rv_timer_csr_rw	0.660s	84.755us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	33.085us	5	5	100.00
		rv_timer_same_csr_outstanding	0.870s	45.496us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.930s	176.419us	5	5	100.00
		rv_timer_tl_intg_err	1.460s	112.592us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.460s	112.592us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	33.341m	777.370ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			611	620	98.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	4	57.14
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.38	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:

Test rv_timer_disabled has 1 failures.

2.rv_timer_disabled.253178377
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_random_reset has 1 failures.

8.rv_timer_random_reset.1631386908
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_random_reset/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_random has 6 failures.

22.rv_timer_random.2146100893
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.rv_timer_random.3536590529
Line 217, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test rv_timer_stress_all has 1 failures.

34.rv_timer_stress_all.1384785741
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---