c06cc3921
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | random | rv_timer_random | 45.185m | 679.133ms | 191 | 200 | 95.50 |
V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 62.292us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_timer_csr_rw | 0.640s | 14.151us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.180s | 165.813us | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_timer_csr_aliasing | 0.830s | 31.666us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.640s | 127.230us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 14.151us | 20 | 20 | 100.00 |
rv_timer_csr_aliasing | 0.830s | 31.666us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 246 | 255 | 96.47 | |||
V2 | random_reset | rv_timer_random_reset | 25.690m | 46.493ms | 48 | 50 | 96.00 |
V2 | disabled | rv_timer_disabled | 5.538m | 725.445ms | 49 | 50 | 98.00 |
V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 19.562m | 2.814s | 50 | 50 | 100.00 |
V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 19.562m | 2.814s | 50 | 50 | 100.00 |
V2 | stress | rv_timer_stress_all | 1.740h | 2.765s | 50 | 50 | 100.00 |
V2 | intr_test | rv_timer_intr_test | 0.640s | 23.361us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.500s | 818.581us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.500s | 818.581us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 62.292us | 5 | 5 | 100.00 |
rv_timer_csr_rw | 0.640s | 14.151us | 20 | 20 | 100.00 | ||
rv_timer_csr_aliasing | 0.830s | 31.666us | 5 | 5 | 100.00 | ||
rv_timer_same_csr_outstanding | 0.870s | 80.850us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 62.292us | 5 | 5 | 100.00 |
rv_timer_csr_rw | 0.640s | 14.151us | 20 | 20 | 100.00 | ||
rv_timer_csr_aliasing | 0.830s | 31.666us | 5 | 5 | 100.00 | ||
rv_timer_same_csr_outstanding | 0.870s | 80.850us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | rv_timer_sec_cm | 0.880s | 263.449us | 5 | 5 | 100.00 |
rv_timer_tl_intg_err | 1.420s | 187.417us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 187.417us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 34.926m | 323.460ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 608 | 620 | 98.06 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 5 | 83.33 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.53 | 99.38 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.09 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 12 failures:
Test rv_timer_random_reset has 2 failures.
6.rv_timer_random_reset.2179913466
Line 221, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_timer_random_reset.4259425480
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random has 9 failures.
34.rv_timer_random.3839243259
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_random/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
80.rv_timer_random.1954652354
Line 217, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/80.rv_timer_random/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test rv_timer_disabled has 1 failures.
36.rv_timer_disabled.3890732983
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---