Unified Coverage Report :: Group :: rv_timer_env_pkg::rv_timer_cfg_cov_obj::timer_cfg_cg

Group : rv_timer_env_pkg::rv_timer_cfg_cov_obj::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
14.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_timer_env_0.1/rv_timer_env_cov.sv

---

Summary for Group rv_timer_env_pkg::rv_timer_cfg_cov_obj::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	611	524	87	14.24

Variables for Group rv_timer_env_pkg::rv_timer_cfg_cov_obj::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mtime	50	28	22	44.00	100	1	1	50
cp_mtime_cmp	50	28	22	44.00	100	1	1	50
cp_prescale	256	234	22	8.59	100	1	1	256
cp_step	255	234	21	8.24	100	1	1	0

Summary for Variable cp_mtime

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	50	28	22	44.00

Automatically Generated Bins for cp_mtime

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0a3d70a3d70a3d70:0f5c28f5c28f5c27] - auto[147ae147ae147ae0:1999999999999997]]	--	--	3
[auto[23d70a3d70a3d708:28f5c28f5c28f5bf] - auto[2e147ae147ae1478:333333333333332f]]	--	--	3
[auto[3851eb851eb851e8:3d70a3d70a3d709f] - auto[3d70a3d70a3d70a0:428f5c28f5c28f57]]	--	--	2
[auto[47ae147ae147ae10:4cccccccccccccc7] - auto[4cccccccccccccc8:51eb851eb851eb7f]]	--	--	2
[auto[6147ae147ae147a8:666666666666665f] - auto[6666666666666660:6b851eb851eb8517]]	--	--	2
[auto[70a3d70a3d70a3d0:75c28f5c28f5c287]]	0	1	1
[auto[851eb851eb851eb0:8a3d70a3d70a3d67]]	0	1	1
[auto[8f5c28f5c28f5c20:947ae147ae147ad7]]	0	1	1
[auto[9eb851eb851eb848:a3d70a3d70a3d6ff] - auto[a8f5c28f5c28f5b8:ae147ae147ae146f]]	--	--	3
[auto[b851eb851eb851e0:bd70a3d70a3d7097]]	0	1	1
[auto[c28f5c28f5c28f50:c7ae147ae147ae07]]	0	1	1
[auto[d70a3d70a3d70a30:dc28f5c28f5c28e7] - auto[fae147ae147ae138:ffffffffffffffff]]	--	--	8

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0000000000000000:051eb851eb851eb7]	50	1		T7	1		T59	1		T60	1
auto[051eb851eb851eb8:0a3d70a3d70a3d6f]	50	1		T7	1		T59	1		T60	1
auto[1999999999999998:1eb851eb851eb84f]	50	1		T7	1		T59	1		T60	1
auto[1eb851eb851eb850:23d70a3d70a3d707]	100	1		T4	1		T7	1		T10	1
auto[3333333333333330:3851eb851eb851e7]	50	1		T7	1		T59	1		T60	1
auto[428f5c28f5c28f58:47ae147ae147ae0f]	50	1		T7	1		T59	1		T60	1
auto[51eb851eb851eb80:570a3d70a3d70a37]	50	1		T7	1		T59	1		T60	1
auto[570a3d70a3d70a38:5c28f5c28f5c28ef]	50	1		T7	1		T59	1		T60	1
auto[5c28f5c28f5c28f0:6147ae147ae147a7]	50	1		T7	1		T59	1		T60	1
auto[6b851eb851eb8518:70a3d70a3d70a3cf]	50	1		T7	1		T59	1		T60	1
auto[75c28f5c28f5c288:7ae147ae147ae13f]	50	1		T7	1		T59	1		T60	1
auto[7ae147ae147ae140:7ffffffffffffff7]	50	1		T7	1		T59	1		T60	1
auto[7ffffffffffffff8:851eb851eb851eaf]	50	1		T7	1		T59	1		T60	1
auto[8a3d70a3d70a3d68:8f5c28f5c28f5c1f]	50	1		T63	1		T64	1		T65	1
auto[947ae147ae147ad8:999999999999998f]	50	1		T4	1		T10	1		T11	1
auto[9999999999999990:9eb851eb851eb847]	50	1		T8	1		T37	1		T66	1
auto[ae147ae147ae1470:b333333333333327]	50	1		T63	1		T64	1		T65	1
auto[b333333333333328:b851eb851eb851df]	50	1		T8	1		T37	1		T66	1
auto[bd70a3d70a3d7098:c28f5c28f5c28f4f]	50	1		T7	1		T59	1		T60	1
auto[c7ae147ae147ae08:ccccccccccccccbf]	100	1		T7	2		T59	2		T60	2
auto[ccccccccccccccc0:d1eb851eb851eb77]	50	1		T7	1		T59	1		T60	1
auto[d1eb851eb851eb78:d70a3d70a3d70a2f]	200	1		T2	1		T3	1		T5	1

---

Summary for Variable cp_mtime_cmp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	50	28	22	44.00

Automatically Generated Bins for cp_mtime_cmp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0a3d70a3d70a3d70:0f5c28f5c28f5c27] - auto[147ae147ae147ae0:1999999999999997]]	--	--	3
[auto[23d70a3d70a3d708:28f5c28f5c28f5bf] - auto[2e147ae147ae1478:333333333333332f]]	--	--	3
[auto[3851eb851eb851e8:3d70a3d70a3d709f] - auto[3d70a3d70a3d70a0:428f5c28f5c28f57]]	--	--	2
[auto[47ae147ae147ae10:4cccccccccccccc7] - auto[4cccccccccccccc8:51eb851eb851eb7f]]	--	--	2
[auto[6147ae147ae147a8:666666666666665f] - auto[6666666666666660:6b851eb851eb8517]]	--	--	2
[auto[70a3d70a3d70a3d0:75c28f5c28f5c287]]	0	1	1
[auto[851eb851eb851eb0:8a3d70a3d70a3d67]]	0	1	1
[auto[8f5c28f5c28f5c20:947ae147ae147ad7]]	0	1	1
[auto[9eb851eb851eb848:a3d70a3d70a3d6ff] - auto[a8f5c28f5c28f5b8:ae147ae147ae146f]]	--	--	3
[auto[b851eb851eb851e0:bd70a3d70a3d7097]]	0	1	1
[auto[c28f5c28f5c28f50:c7ae147ae147ae07]]	0	1	1
[auto[d70a3d70a3d70a30:dc28f5c28f5c28e7] - auto[fae147ae147ae138:ffffffffffffffff]]	--	--	8

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0000000000000000:051eb851eb851eb7]	50	1		T7	1		T59	1		T60	1
auto[051eb851eb851eb8:0a3d70a3d70a3d6f]	50	1		T7	1		T59	1		T60	1
auto[1999999999999998:1eb851eb851eb84f]	50	1		T7	1		T59	1		T60	1
auto[1eb851eb851eb850:23d70a3d70a3d707]	100	1		T4	1		T7	1		T10	1
auto[3333333333333330:3851eb851eb851e7]	50	1		T7	1		T59	1		T60	1
auto[428f5c28f5c28f58:47ae147ae147ae0f]	50	1		T7	1		T59	1		T60	1
auto[51eb851eb851eb80:570a3d70a3d70a37]	50	1		T7	1		T59	1		T60	1
auto[570a3d70a3d70a38:5c28f5c28f5c28ef]	50	1		T7	1		T59	1		T60	1
auto[5c28f5c28f5c28f0:6147ae147ae147a7]	50	1		T7	1		T59	1		T60	1
auto[6b851eb851eb8518:70a3d70a3d70a3cf]	50	1		T7	1		T59	1		T60	1
auto[75c28f5c28f5c288:7ae147ae147ae13f]	50	1		T7	1		T59	1		T60	1
auto[7ae147ae147ae140:7ffffffffffffff7]	50	1		T7	1		T59	1		T60	1
auto[7ffffffffffffff8:851eb851eb851eaf]	50	1		T7	1		T59	1		T60	1
auto[8a3d70a3d70a3d68:8f5c28f5c28f5c1f]	50	1		T63	1		T64	1		T65	1
auto[947ae147ae147ad8:999999999999998f]	50	1		T4	1		T10	1		T11	1
auto[9999999999999990:9eb851eb851eb847]	50	1		T8	1		T37	1		T66	1
auto[ae147ae147ae1470:b333333333333327]	50	1		T63	1		T64	1		T65	1
auto[b333333333333328:b851eb851eb851df]	50	1		T8	1		T37	1		T66	1
auto[bd70a3d70a3d7098:c28f5c28f5c28f4f]	50	1		T7	1		T59	1		T60	1
auto[c7ae147ae147ae08:ccccccccccccccbf]	100	1		T7	2		T59	2		T60	2
auto[ccccccccccccccc0:d1eb851eb851eb77]	50	1		T7	1		T59	1		T60	1
auto[d1eb851eb851eb78:d70a3d70a3d70a2f]	200	1		T2	1		T3	1		T5	1

---

Summary for Variable cp_prescale

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	256	234	22	8.59

Automatically Generated Bins for cp_prescale

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0:15] - auto[336:351]]	--	--	22
[auto[368:383] - auto[816:831]]	--	--	29
[auto[848:863] - auto[928:943]]	--	--	6
[auto[960:975] - auto[976:991]]	--	--	2
[auto[1008:1023] - auto[1056:1071]]	--	--	4
[auto[1088:1103] - auto[1152:1167]]	--	--	5
[auto[1184:1199] - auto[1280:1295]]	--	--	7
[auto[1312:1327] - auto[1648:1663]]	--	--	22
[auto[1680:1695] - auto[1744:1759]]	--	--	5
[auto[1776:1791] - auto[1952:1967]]	--	--	12
[auto[1984:1999] - auto[2256:2271]]	--	--	18
[auto[2288:2303]]	0	1	1
[auto[2320:2335] - auto[2432:2447]]	--	--	8
[auto[2464:2479] - auto[2560:2575]]	--	--	7
[auto[2592:2607] - auto[2768:2783]]	--	--	12
[auto[2800:2815] - auto[3136:3151]]	--	--	22
[auto[3168:3183] - auto[3712:3727]]	--	--	35
[auto[3744:3759] - auto[3840:3855]]	--	--	7
[auto[3872:3887] - auto[3904:3919]]	--	--	3
[auto[3952:3967] - auto[3984:3999]]	--	--	3
[auto[4016:4031] - auto[4032:4047]]	--	--	2
[auto[4064:4079] - auto[4080:4095]]	--	--	2

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[352:367]	50	1		T7	1		T59	1		T60	1
auto[832:847]	50	1		T4	1		T10	1		T11	1
auto[944:959]	50	1		T7	1		T59	1		T60	1
auto[992:1007]	50	1		T7	1		T59	1		T60	1
auto[1072:1087]	50	1		T7	1		T59	1		T60	1
auto[1168:1183]	50	1		T63	1		T64	1		T65	1
auto[1296:1311]	50	1		T7	1		T59	1		T60	1
auto[1664:1679]	50	1		T7	1		T59	1		T60	1
auto[1760:1775]	50	1		T7	1		T59	1		T60	1
auto[1968:1983]	50	1		T7	1		T59	1		T60	1
auto[2272:2287]	50	1		T7	1		T59	1		T60	1
auto[2304:2319]	50	1		T7	1		T59	1		T60	1
auto[2448:2463]	200	1		T2	1		T3	1		T5	1
auto[2576:2591]	50	1		T7	1		T59	1		T60	1
auto[2784:2799]	50	1		T7	1		T59	1		T60	1
auto[3152:3167]	50	1		T7	1		T59	1		T60	1
auto[3728:3743]	50	1		T4	1		T10	1		T11	1
auto[3856:3871]	100	1		T7	1		T59	1		T60	1
auto[3920:3935]	50	1		T8	1		T37	1		T66	1
auto[3936:3951]	50	1		T7	1		T59	1		T60	1
auto[4000:4015]	100	1		T7	2		T59	2		T60	2
auto[4048:4063]	50	1		T8	1		T37	1		T66	1

---

Summary for Variable cp_step

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	255	234	21	8.24

User Defined Bins for cp_step

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
step_all_val[2]	0	1	1
step_all_val[3]	0	1	1
step_all_val[4]	0	1	1
step_all_val[5]	0	1	1
step_all_val[6]	0	1	1
step_all_val[7]	0	1	1
step_all_val[8]	0	1	1
step_all_val[9]	0	1	1
step_all_val[10]	0	1	1
step_all_val[11]	0	1	1
step_all_val[12]	0	1	1
step_all_val[13]	0	1	1
step_all_val[14]	0	1	1
step_all_val[15]	0	1	1
step_all_val[16]	0	1	1
step_all_val[17]	0	1	1
step_all_val[18]	0	1	1
step_all_val[19]	0	1	1
step_all_val[20]	0	1	1
step_all_val[21]	0	1	1
step_all_val[23]	0	1	1
step_all_val[24]	0	1	1
step_all_val[25]	0	1	1
step_all_val[27]	0	1	1
step_all_val[28]	0	1	1
step_all_val[30]	0	1	1
step_all_val[31]	0	1	1
step_all_val[32]	0	1	1
step_all_val[33]	0	1	1
step_all_val[34]	0	1	1
step_all_val[35]	0	1	1
step_all_val[36]	0	1	1
step_all_val[37]	0	1	1
step_all_val[38]	0	1	1
step_all_val[39]	0	1	1
step_all_val[40]	0	1	1
step_all_val[41]	0	1	1
step_all_val[42]	0	1	1
step_all_val[43]	0	1	1
step_all_val[44]	0	1	1
step_all_val[45]	0	1	1
step_all_val[46]	0	1	1
step_all_val[47]	0	1	1
step_all_val[48]	0	1	1
step_all_val[49]	0	1	1
step_all_val[50]	0	1	1
step_all_val[51]	0	1	1
step_all_val[52]	0	1	1
step_all_val[53]	0	1	1
step_all_val[54]	0	1	1
step_all_val[55]	0	1	1
step_all_val[56]	0	1	1
step_all_val[57]	0	1	1
step_all_val[58]	0	1	1
step_all_val[61]	0	1	1
step_all_val[62]	0	1	1
step_all_val[63]	0	1	1
step_all_val[64]	0	1	1
step_all_val[65]	0	1	1
step_all_val[66]	0	1	1
step_all_val[67]	0	1	1
step_all_val[69]	0	1	1
step_all_val[70]	0	1	1
step_all_val[72]	0	1	1
step_all_val[73]	0	1	1
step_all_val[74]	0	1	1
step_all_val[75]	0	1	1
step_all_val[76]	0	1	1
step_all_val[77]	0	1	1
step_all_val[78]	0	1	1
step_all_val[79]	0	1	1
step_all_val[80]	0	1	1
step_all_val[81]	0	1	1
step_all_val[82]	0	1	1
step_all_val[83]	0	1	1
step_all_val[84]	0	1	1
step_all_val[85]	0	1	1
step_all_val[86]	0	1	1
step_all_val[87]	0	1	1
step_all_val[90]	0	1	1
step_all_val[91]	0	1	1
step_all_val[92]	0	1	1
step_all_val[93]	0	1	1
step_all_val[94]	0	1	1
step_all_val[95]	0	1	1
step_all_val[96]	0	1	1
step_all_val[97]	0	1	1
step_all_val[98]	0	1	1
step_all_val[99]	0	1	1
step_all_val[100]	0	1	1
step_all_val[101]	0	1	1
step_all_val[102]	0	1	1
step_all_val[103]	0	1	1
step_all_val[104]	0	1	1
step_all_val[105]	0	1	1
step_all_val[106]	0	1	1
step_all_val[107]	0	1	1
step_all_val[108]	0	1	1
step_all_val[109]	0	1	1
step_all_val[110]	0	1	1
step_all_val[111]	0	1	1
step_all_val[112]	0	1	1
step_all_val[113]	0	1	1
step_all_val[114]	0	1	1
step_all_val[115]	0	1	1
step_all_val[116]	0	1	1
step_all_val[117]	0	1	1
step_all_val[118]	0	1	1
step_all_val[119]	0	1	1
step_all_val[120]	0	1	1
step_all_val[121]	0	1	1
step_all_val[122]	0	1	1
step_all_val[123]	0	1	1
step_all_val[124]	0	1	1
step_all_val[126]	0	1	1
step_all_val[127]	0	1	1
step_all_val[128]	0	1	1
step_all_val[129]	0	1	1
step_all_val[130]	0	1	1
step_all_val[131]	0	1	1
step_all_val[132]	0	1	1
step_all_val[133]	0	1	1
step_all_val[134]	0	1	1
step_all_val[135]	0	1	1
step_all_val[136]	0	1	1
step_all_val[138]	0	1	1
step_all_val[139]	0	1	1
step_all_val[140]	0	1	1
step_all_val[141]	0	1	1
step_all_val[142]	0	1	1
step_all_val[143]	0	1	1
step_all_val[144]	0	1	1
step_all_val[145]	0	1	1
step_all_val[146]	0	1	1
step_all_val[147]	0	1	1
step_all_val[148]	0	1	1
step_all_val[149]	0	1	1
step_all_val[150]	0	1	1
step_all_val[151]	0	1	1
step_all_val[152]	0	1	1
step_all_val[154]	0	1	1
step_all_val[155]	0	1	1
step_all_val[156]	0	1	1
step_all_val[158]	0	1	1
step_all_val[159]	0	1	1
step_all_val[160]	0	1	1
step_all_val[161]	0	1	1
step_all_val[162]	0	1	1
step_all_val[163]	0	1	1
step_all_val[164]	0	1	1
step_all_val[165]	0	1	1
step_all_val[166]	0	1	1
step_all_val[167]	0	1	1
step_all_val[168]	0	1	1
step_all_val[169]	0	1	1
step_all_val[170]	0	1	1
step_all_val[171]	0	1	1
step_all_val[172]	0	1	1
step_all_val[173]	0	1	1
step_all_val[174]	0	1	1
step_all_val[175]	0	1	1
step_all_val[176]	0	1	1
step_all_val[177]	0	1	1
step_all_val[178]	0	1	1
step_all_val[179]	0	1	1
step_all_val[180]	0	1	1
step_all_val[181]	0	1	1
step_all_val[182]	0	1	1
step_all_val[183]	0	1	1
step_all_val[184]	0	1	1
step_all_val[185]	0	1	1
step_all_val[187]	0	1	1
step_all_val[188]	0	1	1
step_all_val[189]	0	1	1
step_all_val[190]	0	1	1
step_all_val[191]	0	1	1
step_all_val[192]	0	1	1
step_all_val[193]	0	1	1
step_all_val[194]	0	1	1
step_all_val[195]	0	1	1
step_all_val[196]	0	1	1
step_all_val[197]	0	1	1
step_all_val[198]	0	1	1
step_all_val[199]	0	1	1
step_all_val[200]	0	1	1
step_all_val[201]	0	1	1
step_all_val[202]	0	1	1
step_all_val[203]	0	1	1
step_all_val[204]	0	1	1
step_all_val[205]	0	1	1
step_all_val[206]	0	1	1
step_all_val[207]	0	1	1
step_all_val[208]	0	1	1
step_all_val[209]	0	1	1
step_all_val[210]	0	1	1
step_all_val[211]	0	1	1
step_all_val[212]	0	1	1
step_all_val[213]	0	1	1
step_all_val[214]	0	1	1
step_all_val[215]	0	1	1
step_all_val[216]	0	1	1
step_all_val[217]	0	1	1
step_all_val[219]	0	1	1
step_all_val[220]	0	1	1
step_all_val[221]	0	1	1
step_all_val[222]	0	1	1
step_all_val[223]	0	1	1
step_all_val[224]	0	1	1
step_all_val[225]	0	1	1
step_all_val[226]	0	1	1
step_all_val[227]	0	1	1
step_all_val[228]	0	1	1
step_all_val[229]	0	1	1
step_all_val[230]	0	1	1
step_all_val[231]	0	1	1
step_all_val[233]	0	1	1
step_all_val[234]	0	1	1
step_all_val[235]	0	1	1
step_all_val[236]	0	1	1
step_all_val[237]	0	1	1
step_all_val[238]	0	1	1
step_all_val[239]	0	1	1
step_all_val[240]	0	1	1
step_all_val[241]	0	1	1
step_all_val[242]	0	1	1
step_all_val[243]	0	1	1
step_all_val[244]	0	1	1
step_all_val[245]	0	1	1
step_all_val[246]	0	1	1
step_all_val[250]	0	1	1
step_all_val[252]	0	1	1
step_all_val[253]	0	1	1
step_all_val[254]	0	1	1
step_all_val[255]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
step_all_val[1]	50	1		T7	1		T59	1		T60	1
step_all_val[22]	50	1		T7	1		T59	1		T60	1
step_all_val[26]	50	1		T7	1		T59	1		T60	1
step_all_val[29]	50	1		T7	1		T59	1		T60	1
step_all_val[59]	50	1		T63	1		T64	1		T65	1
step_all_val[60]	100	1		T7	2		T59	2		T60	2
step_all_val[68]	50	1		T7	1		T59	1		T60	1
step_all_val[71]	50	1		T4	1		T10	1		T11	1
step_all_val[88]	250	1		T2	1		T3	1		T5	1
step_all_val[89]	50	1		T7	1		T59	1		T60	1
step_all_val[125]	50	1		T7	1		T59	1		T60	1
step_all_val[137]	50	1		T7	1		T59	1		T60	1
step_all_val[153]	100	1		T7	2		T59	2		T60	2
step_all_val[157]	50	1		T7	1		T59	1		T60	1
step_all_val[186]	50	1		T4	1		T10	1		T11	1
step_all_val[218]	50	1		T7	1		T59	1		T60	1
step_all_val[232]	50	1		T8	1		T37	1		T66	1
step_all_val[247]	50	1		T7	1		T59	1		T60	1
step_all_val[248]	50	1		T8	1		T37	1		T66	1
step_all_val[249]	50	1		T63	1		T64	1		T65	1
step_all_val[251]	50	1		T7	1		T59	1		T60	1