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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.65 99.36 98.73 100.00 100.00 99.35 40.43


Total test records in report: 620
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T501 /workspace/coverage/default/1.rv_timer_random_reset.103190175752804972969174137364100121240214794741437936224467677795351649840036 Nov 22 01:03:59 PM PST 23 Nov 22 01:08:57 PM PST 23 60703901037 ps
T502 /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.16406392096140227039735820738546392158617377556710964512053690957321684094829 Nov 22 01:05:08 PM PST 23 Nov 22 01:15:12 PM PST 23 544575976458 ps
T503 /workspace/coverage/default/2.rv_timer_random_reset.110118010420773699183105130308721427465502212772321347238881060291652635690403 Nov 22 01:04:09 PM PST 23 Nov 22 01:09:09 PM PST 23 60703901037 ps
T504 /workspace/coverage/default/90.rv_timer_random.28310121128625994781358054170161944543114099365278398857410916750964070268906 Nov 22 01:05:53 PM PST 23 Nov 22 01:07:06 PM PST 23 70917337186 ps
T505 /workspace/coverage/default/180.rv_timer_random.20176889129983109686283747124310581901762157196041793903960604150709837125147 Nov 22 01:06:26 PM PST 23 Nov 22 01:07:40 PM PST 23 70917337186 ps
T506 /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.103011688567663725027814869246702341467770497804460224361156376958867349457127 Nov 22 01:05:14 PM PST 23 Nov 22 01:15:27 PM PST 23 544575976458 ps
T507 /workspace/coverage/default/69.rv_timer_random.90072450194066846446206734688657144221726547452328548886813179655300696827314 Nov 22 01:05:47 PM PST 23 Nov 22 01:07:04 PM PST 23 70917337186 ps
T508 /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.88346252552616835838522101354125345062824788314295683679940933091160113794478 Nov 22 01:05:03 PM PST 23 Nov 22 01:15:08 PM PST 23 544575976458 ps
T509 /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.9598365911351578302612582945639770915036922690098475793853790933800774665454 Nov 22 01:05:27 PM PST 23 Nov 22 01:19:08 PM PST 23 207522994332 ps
T510 /workspace/coverage/default/119.rv_timer_random.52832641476423795650793383677837125896776648758669930856996027532708043212830 Nov 22 01:06:08 PM PST 23 Nov 22 01:07:23 PM PST 23 70917337186 ps
T511 /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.71680212358520646774923794836743035575306918710436106021721287781177134049039 Nov 22 01:05:26 PM PST 23 Nov 22 01:15:50 PM PST 23 544575976458 ps
T512 /workspace/coverage/default/10.rv_timer_random_reset.68412723693221769072086919193327658116721804776927197306642012330671288311547 Nov 22 01:04:15 PM PST 23 Nov 22 01:09:18 PM PST 23 60703901037 ps
T513 /workspace/coverage/default/28.rv_timer_random.32165289084919410861502177377509556758759245354563271130720583536157514192359 Nov 22 01:05:01 PM PST 23 Nov 22 01:06:17 PM PST 23 70917337186 ps
T514 /workspace/coverage/default/175.rv_timer_random.108112224762853973737388607213037016398599176658740885088437858813583832712012 Nov 22 01:06:21 PM PST 23 Nov 22 01:07:35 PM PST 23 70917337186 ps
T515 /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.69015178326856487852452926360370616757091248744036454213543698875502777401316 Nov 22 01:05:00 PM PST 23 Nov 22 01:18:25 PM PST 23 207522994332 ps
T516 /workspace/coverage/default/41.rv_timer_stress_all.12848241738773652325870553803107665417577883635712866282638266937823896923340 Nov 22 01:05:36 PM PST 23 Nov 22 01:32:27 PM PST 23 1048433034855 ps
T517 /workspace/coverage/default/104.rv_timer_random.3475609711747525955615833312824290568974462337665840719381921944102446228664 Nov 22 01:06:08 PM PST 23 Nov 22 01:07:20 PM PST 23 70917337186 ps
T518 /workspace/coverage/default/108.rv_timer_random.97881706254223813475455305176133568016477192720951169992792240701384071459933 Nov 22 01:06:08 PM PST 23 Nov 22 01:07:25 PM PST 23 70917337186 ps
T519 /workspace/coverage/default/138.rv_timer_random.6617492722431118591318571637827665212783091584392291819132897091689164653039 Nov 22 01:06:06 PM PST 23 Nov 22 01:07:20 PM PST 23 70917337186 ps
T520 /workspace/coverage/default/29.rv_timer_random_reset.109798490407149535528117593852928333487962308346057559559584670680024836702836 Nov 22 01:05:08 PM PST 23 Nov 22 01:10:03 PM PST 23 60703901037 ps
T521 /workspace/coverage/default/22.rv_timer_random_reset.58308800208214544775882076718687561394198131409446708037959510281796194311051 Nov 22 01:05:03 PM PST 23 Nov 22 01:10:01 PM PST 23 60703901037 ps
T522 /workspace/coverage/default/46.rv_timer_disabled.41362603363701037972729580913251723041065852666436143280905794666136575540735 Nov 22 01:05:39 PM PST 23 Nov 22 01:06:11 PM PST 23 32101379859 ps
T523 /workspace/coverage/default/42.rv_timer_random.87990533700185163156212925633296570981403089910620082330058757148164805953183 Nov 22 01:05:45 PM PST 23 Nov 22 01:07:00 PM PST 23 70917337186 ps
T524 /workspace/coverage/default/0.rv_timer_random_reset.30255977258028700177097062451081151301494307406862535231236216528891330703333 Nov 22 01:03:56 PM PST 23 Nov 22 01:08:47 PM PST 23 60703901037 ps
T525 /workspace/coverage/default/18.rv_timer_disabled.84458410119080975122671233832090958955816325773660802466455560072862920929189 Nov 22 01:05:02 PM PST 23 Nov 22 01:05:33 PM PST 23 32101379859 ps
T526 /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.103920662027624710642209258733966022624502312673975667145995765394256730933070 Nov 22 01:04:09 PM PST 23 Nov 22 01:14:15 PM PST 23 544575976458 ps
T527 /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.34160119797637386861790375401496498024859880547273361204902226210113851504794 Nov 22 01:05:02 PM PST 23 Nov 22 01:15:09 PM PST 23 544575976458 ps
T528 /workspace/coverage/default/188.rv_timer_random.78391881714486678467089651783129670138746919286241722461855238902534396086837 Nov 22 01:06:15 PM PST 23 Nov 22 01:07:29 PM PST 23 70917337186 ps
T529 /workspace/coverage/default/46.rv_timer_stress_all.66464252247717918295700213652037953444244228572556092997051103767404763163296 Nov 22 01:05:56 PM PST 23 Nov 22 01:32:06 PM PST 23 1048433034855 ps
T530 /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.40793350934290692937707240711367392417866006809220303217197269367945685632806 Nov 22 01:05:12 PM PST 23 Nov 22 01:18:46 PM PST 23 207522994332 ps
T531 /workspace/coverage/default/7.rv_timer_random.76210142208159639744243142892048560221441793670200649300753046476012435686087 Nov 22 01:04:03 PM PST 23 Nov 22 01:05:21 PM PST 23 70917337186 ps
T532 /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.74516744643250739958273624685374524522269691328016971871106001164813166745742 Nov 22 01:04:52 PM PST 23 Nov 22 01:14:57 PM PST 23 544575976458 ps
T533 /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.38983684077535946592463799800133065118920928586487634734886833179179433545520 Nov 22 01:05:29 PM PST 23 Nov 22 01:15:43 PM PST 23 544575976458 ps
T534 /workspace/coverage/default/14.rv_timer_random.19775360864754938358563627271029598019504395154832103832946445872158148456061 Nov 22 01:04:56 PM PST 23 Nov 22 01:06:14 PM PST 23 70917337186 ps
T535 /workspace/coverage/default/118.rv_timer_random.2724707928970931216910481586600240883905753739155393033120571897028257068756 Nov 22 01:06:08 PM PST 23 Nov 22 01:07:23 PM PST 23 70917337186 ps
T536 /workspace/coverage/default/7.rv_timer_stress_all.80510557071706069594285963129591063640788021993437014259394423447536405599579 Nov 22 01:04:09 PM PST 23 Nov 22 01:30:40 PM PST 23 1048433034855 ps
T537 /workspace/coverage/default/4.rv_timer_disabled.54325308601822090617090958240860702280788052135974668263877011530187444698136 Nov 22 01:03:57 PM PST 23 Nov 22 01:04:35 PM PST 23 32101379859 ps
T538 /workspace/coverage/default/107.rv_timer_random.15999579413013973623380734688473902627724204970376420986044030738921449561262 Nov 22 01:06:10 PM PST 23 Nov 22 01:07:23 PM PST 23 70917337186 ps
T539 /workspace/coverage/default/128.rv_timer_random.63823415036974132636463589769445124122903064428475125348831386204167810404486 Nov 22 01:06:10 PM PST 23 Nov 22 01:07:24 PM PST 23 70917337186 ps
T540 /workspace/coverage/default/33.rv_timer_random.104023928662571160115121148353636567648982201344721886106923036095961914328440 Nov 22 01:05:28 PM PST 23 Nov 22 01:06:45 PM PST 23 70917337186 ps
T541 /workspace/coverage/default/9.rv_timer_random.36368062641192243036022225688320458436812331848119940183002587141098112312024 Nov 22 01:04:09 PM PST 23 Nov 22 01:05:29 PM PST 23 70917337186 ps
T542 /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.43552003165841291298744160957688866640650926732767230265096031119779800415832 Nov 22 01:05:06 PM PST 23 Nov 22 01:18:38 PM PST 23 207522994332 ps
T543 /workspace/coverage/default/4.rv_timer_stress_all.25621458552390459022728811465725241741701519423765423895550194140788727909677 Nov 22 01:04:15 PM PST 23 Nov 22 01:30:46 PM PST 23 1048433034855 ps
T544 /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.75248853072641051096639957873589652729352770896009242925902282587695462769276 Nov 22 01:04:14 PM PST 23 Nov 22 01:14:25 PM PST 23 544575976458 ps
T545 /workspace/coverage/default/7.rv_timer_random_reset.61523199449899146415779342360935719197946577416478114686214642760311089369062 Nov 22 01:04:11 PM PST 23 Nov 22 01:09:04 PM PST 23 60703901037 ps
T546 /workspace/coverage/default/34.rv_timer_random_reset.32084135690771913631336672051732619228905809932423675857576104046574295484264 Nov 22 01:05:12 PM PST 23 Nov 22 01:10:13 PM PST 23 60703901037 ps
T547 /workspace/coverage/default/129.rv_timer_random.12737977741546464174051786056365889274416187617568626164634110955977891392243 Nov 22 01:06:06 PM PST 23 Nov 22 01:07:20 PM PST 23 70917337186 ps
T548 /workspace/coverage/default/3.rv_timer_random.29187949299035870543655971429783679249059076442744760747557071879602799552825 Nov 22 01:04:09 PM PST 23 Nov 22 01:05:27 PM PST 23 70917337186 ps
T549 /workspace/coverage/default/156.rv_timer_random.52451704400710066149094063643341511127294789828123237495538961911638585636568 Nov 22 01:06:16 PM PST 23 Nov 22 01:07:31 PM PST 23 70917337186 ps
T550 /workspace/coverage/default/30.rv_timer_random.58763099390920131175224382366559130269142941805227435115846943680626161716874 Nov 22 01:05:02 PM PST 23 Nov 22 01:06:16 PM PST 23 70917337186 ps
T551 /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.129573044899106645673991670474242649666980024718027164409033410426574930521 Nov 22 01:05:49 PM PST 23 Nov 22 01:19:33 PM PST 23 207522994332 ps
T552 /workspace/coverage/default/141.rv_timer_random.48691961246067755944458280993877586651371432386067323409054367797123456060069 Nov 22 01:06:08 PM PST 23 Nov 22 01:07:23 PM PST 23 70917337186 ps
T553 /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.81450995397083788543164731550647631331688689036753420930032326455142337331078 Nov 22 01:05:28 PM PST 23 Nov 22 01:19:12 PM PST 23 207522994332 ps
T554 /workspace/coverage/default/13.rv_timer_stress_all.77475856139677758927652421104890813275737258224604372993698690203319965637967 Nov 22 01:04:42 PM PST 23 Nov 22 01:31:22 PM PST 23 1048433034855 ps
T555 /workspace/coverage/default/30.rv_timer_stress_all.74637861169792867208833160669047693444250652091629208936272540061838143989050 Nov 22 01:05:10 PM PST 23 Nov 22 01:32:03 PM PST 23 1048433034855 ps
T556 /workspace/coverage/default/24.rv_timer_random.29642736483270527697419766790110048148440626724332442325535372154234855388314 Nov 22 01:04:48 PM PST 23 Nov 22 01:06:02 PM PST 23 70917337186 ps
T557 /workspace/coverage/default/140.rv_timer_random.101014518329150434252449551067869175149848020914138198676914554694317882905066 Nov 22 01:06:04 PM PST 23 Nov 22 01:07:18 PM PST 23 70917337186 ps
T558 /workspace/coverage/default/54.rv_timer_random.21159552183019069251297768947216062207446532500961220841772608733406011624056 Nov 22 01:05:47 PM PST 23 Nov 22 01:07:03 PM PST 23 70917337186 ps
T559 /workspace/coverage/default/36.rv_timer_disabled.6672104031256455135400126273394674579825127877881114027467381891811735098270 Nov 22 01:05:21 PM PST 23 Nov 22 01:05:53 PM PST 23 32101379859 ps
T560 /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.20224173088284050881018410830979406894852423972252361827260546857841039859044 Nov 22 01:04:57 PM PST 23 Nov 22 01:15:12 PM PST 23 544575976458 ps
T561 /workspace/coverage/default/23.rv_timer_random_reset.103361717380024425865883757970861433028406984151322307878492826859219388443898 Nov 22 01:04:53 PM PST 23 Nov 22 01:09:55 PM PST 23 60703901037 ps
T562 /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.87175888246875717314130036138684490022020105388658327153390217682124168947275 Nov 22 01:05:32 PM PST 23 Nov 22 01:18:57 PM PST 23 207522994332 ps
T563 /workspace/coverage/default/5.rv_timer_stress_all.37442026726149531899661431463895669900666424610271622038161391622086778774108 Nov 22 01:04:09 PM PST 23 Nov 22 01:31:19 PM PST 23 1048433034855 ps
T564 /workspace/coverage/default/173.rv_timer_random.58818689914102989196777188313368665118948708489267497387711943564110133460633 Nov 22 01:06:26 PM PST 23 Nov 22 01:07:41 PM PST 23 70917337186 ps
T565 /workspace/coverage/default/33.rv_timer_disabled.64085982991304514871521425284861173206454830560225344147195339969685234822440 Nov 22 01:05:29 PM PST 23 Nov 22 01:06:01 PM PST 23 32101379859 ps
T566 /workspace/coverage/default/13.rv_timer_random_reset.43989960950361187266636195347864513840100541033890829421719889400848367342584 Nov 22 01:04:43 PM PST 23 Nov 22 01:09:39 PM PST 23 60703901037 ps
T567 /workspace/coverage/default/31.rv_timer_stress_all.27219381037744061109813046989190538118540790274943501860877759731310916659272 Nov 22 01:05:09 PM PST 23 Nov 22 01:31:51 PM PST 23 1048433034855 ps
T568 /workspace/coverage/default/150.rv_timer_random.106779776151270784143133661684996829081419930690358249614955121863148180021717 Nov 22 01:06:24 PM PST 23 Nov 22 01:07:38 PM PST 23 70917337186 ps
T569 /workspace/coverage/default/29.rv_timer_disabled.47050752018967376018089910963158362200622278982227083090873665884991765316449 Nov 22 01:05:01 PM PST 23 Nov 22 01:05:33 PM PST 23 32101379859 ps
T570 /workspace/coverage/default/19.rv_timer_disabled.49352880233366182192833637123001992186759356977701160853698632506205530694607 Nov 22 01:05:04 PM PST 23 Nov 22 01:05:37 PM PST 23 32101379859 ps
T571 /workspace/coverage/default/66.rv_timer_random.19791138183926175074922909814766226801689536786252487225465964912591209581289 Nov 22 01:05:47 PM PST 23 Nov 22 01:07:03 PM PST 23 70917337186 ps
T572 /workspace/coverage/default/34.rv_timer_stress_all.28425698472543046765334529889922567529410164196365747065869772076062532592776 Nov 22 01:05:27 PM PST 23 Nov 22 01:32:32 PM PST 23 1048433034855 ps
T573 /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.60686492757581923838074195550795346599908201338843667189549640636901169605353 Nov 22 01:05:42 PM PST 23 Nov 22 01:19:21 PM PST 23 207522994332 ps
T574 /workspace/coverage/default/43.rv_timer_random.43845094845888103894666785707738246254193641272464311420627137025388346356995 Nov 22 01:05:34 PM PST 23 Nov 22 01:06:49 PM PST 23 70917337186 ps
T575 /workspace/coverage/default/39.rv_timer_random.112044217474904276559769160088829699372210948563251482095602240683184605490793 Nov 22 01:05:28 PM PST 23 Nov 22 01:06:44 PM PST 23 70917337186 ps
T576 /workspace/coverage/default/43.rv_timer_random_reset.71468593515924484186675310616712674479397094305794936481894717386037676592511 Nov 22 01:05:32 PM PST 23 Nov 22 01:10:33 PM PST 23 60703901037 ps
T577 /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.15472817191693922761338103555915805345121601857608587355405403940248279029069 Nov 22 01:04:50 PM PST 23 Nov 22 01:15:01 PM PST 23 544575976458 ps
T578 /workspace/coverage/default/21.rv_timer_disabled.5036551198456958454894531821008613279429104654583903562864905721755812860942 Nov 22 01:05:07 PM PST 23 Nov 22 01:05:39 PM PST 23 32101379859 ps
T579 /workspace/coverage/default/45.rv_timer_disabled.100197975357743740735720446928577847847650213050652291323136928342630370620472 Nov 22 01:05:44 PM PST 23 Nov 22 01:06:17 PM PST 23 32101379859 ps
T580 /workspace/coverage/default/24.rv_timer_stress_all.47279144027171833370051327695553171753386089275085057930835354370280543911753 Nov 22 01:05:05 PM PST 23 Nov 22 01:31:58 PM PST 23 1048433034855 ps
T581 /workspace/coverage/default/11.rv_timer_random.64830738934937055538692902569606767054008070255701058262810590643011892288035 Nov 22 01:04:15 PM PST 23 Nov 22 01:05:28 PM PST 23 70917337186 ps
T582 /workspace/coverage/default/88.rv_timer_random.56287641986140714741493827412849727302036212714251228546030694158846074945487 Nov 22 01:05:57 PM PST 23 Nov 22 01:07:12 PM PST 23 70917337186 ps
T583 /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.635856403138967615005323689725626156671310547042639762661035929424462089023 Nov 22 01:05:45 PM PST 23 Nov 22 01:15:59 PM PST 23 544575976458 ps
T584 /workspace/coverage/default/26.rv_timer_random_reset.41853258261255730759742037690980550429241555898504583907022502671015698920506 Nov 22 01:05:05 PM PST 23 Nov 22 01:10:08 PM PST 23 60703901037 ps
T585 /workspace/coverage/default/49.rv_timer_disabled.85518948666817673207879801683900837304410741374185584844182960653792190001935 Nov 22 01:05:45 PM PST 23 Nov 22 01:06:17 PM PST 23 32101379859 ps
T586 /workspace/coverage/default/38.rv_timer_random.22564363635291107411241672944936276472160062409960315393724414676688905135125 Nov 22 01:05:27 PM PST 23 Nov 22 01:06:44 PM PST 23 70917337186 ps
T587 /workspace/coverage/default/185.rv_timer_random.78772038314869954980203411390819721482994370498699427420932467768150128143804 Nov 22 01:06:27 PM PST 23 Nov 22 01:07:42 PM PST 23 70917337186 ps
T588 /workspace/coverage/default/109.rv_timer_random.7293943400813043973598493145078391715141537088565957821237799685381972807766 Nov 22 01:06:11 PM PST 23 Nov 22 01:07:24 PM PST 23 70917337186 ps
T589 /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.45800346936133538978306960093241833574690348715326333876572625810300625335844 Nov 22 01:04:15 PM PST 23 Nov 22 01:18:03 PM PST 23 207522994332 ps
T590 /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.41567320192802749789579189464861485780695687016558569028743350514544907913409 Nov 22 01:05:33 PM PST 23 Nov 22 01:15:55 PM PST 23 544575976458 ps
T591 /workspace/coverage/default/110.rv_timer_random.78432749696138599617000201793091493518621796525764859241734013123791058183565 Nov 22 01:06:09 PM PST 23 Nov 22 01:07:23 PM PST 23 70917337186 ps
T592 /workspace/coverage/default/31.rv_timer_random.75030606669002988095901122134427354385565508466708272326333780411386113259508 Nov 22 01:05:07 PM PST 23 Nov 22 01:06:23 PM PST 23 70917337186 ps
T593 /workspace/coverage/default/191.rv_timer_random.108777362309049780273516992291111055175990364271809758390484490699931663813281 Nov 22 01:06:20 PM PST 23 Nov 22 01:07:34 PM PST 23 70917337186 ps
T594 /workspace/coverage/default/30.rv_timer_random_reset.2697139342059689310093361528445946087253490906235244985701361336192610184688 Nov 22 01:05:03 PM PST 23 Nov 22 01:09:57 PM PST 23 60703901037 ps
T595 /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.97637516864325868024455852022325295841298455190050627073469784010534752426401 Nov 22 01:04:05 PM PST 23 Nov 22 01:17:44 PM PST 23 207522994332 ps
T596 /workspace/coverage/default/74.rv_timer_random.304837802819745252690640973331355158479769792821501290951314153900546258494 Nov 22 01:05:51 PM PST 23 Nov 22 01:07:06 PM PST 23 70917337186 ps
T597 /workspace/coverage/default/19.rv_timer_stress_all.91554304703489604089633494079017762815827413388241083900418706928004068432064 Nov 22 01:05:03 PM PST 23 Nov 22 01:31:35 PM PST 23 1048433034855 ps
T598 /workspace/coverage/default/182.rv_timer_random.95394508229814075259904073568339301227442846829603696954810190508490395927260 Nov 22 01:06:19 PM PST 23 Nov 22 01:07:35 PM PST 23 70917337186 ps
T599 /workspace/coverage/default/72.rv_timer_random.22906538134088112221044998231151248827519955246585146359730447519361087625832 Nov 22 01:05:47 PM PST 23 Nov 22 01:07:03 PM PST 23 70917337186 ps
T600 /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.40290955154350586543662807515052123817205491295499611444076935066339572868824 Nov 22 01:04:57 PM PST 23 Nov 22 01:18:49 PM PST 23 207522994332 ps
T601 /workspace/coverage/default/6.rv_timer_disabled.32721469496909431790679416241223700366377855298739572977203173318078887294499 Nov 22 01:03:56 PM PST 23 Nov 22 01:04:28 PM PST 23 32101379859 ps
T602 /workspace/coverage/default/4.rv_timer_random.40634695021044474208863229408910961146970068433724261789043388889945021423771 Nov 22 01:04:05 PM PST 23 Nov 22 01:05:27 PM PST 23 70917337186 ps
T603 /workspace/coverage/default/12.rv_timer_random.55491898798014167172169411689822777653875462923968340944456638046538835232478 Nov 22 01:04:15 PM PST 23 Nov 22 01:05:29 PM PST 23 70917337186 ps
T604 /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.96854248586719901152090641153183413866534366233452909054763107829074587617751 Nov 22 01:05:03 PM PST 23 Nov 22 01:15:20 PM PST 23 544575976458 ps
T605 /workspace/coverage/default/42.rv_timer_random_reset.55138222159562438487880874653874084636905517343330118514805896469247346989724 Nov 22 01:05:41 PM PST 23 Nov 22 01:10:40 PM PST 23 60703901037 ps
T606 /workspace/coverage/default/0.rv_timer_random.70227875274758451451135558500696795719518406263835286059438652799970949262335 Nov 22 01:03:52 PM PST 23 Nov 22 01:05:06 PM PST 23 70917337186 ps
T607 /workspace/coverage/default/27.rv_timer_stress_all.100638317088816954590064185968571173988204548185020061602387292784587555222644 Nov 22 01:05:01 PM PST 23 Nov 22 01:32:19 PM PST 23 1048433034855 ps
T608 /workspace/coverage/default/51.rv_timer_random.18669055653096774261152931543157138610770053968458199744124684946496531729838 Nov 22 01:05:48 PM PST 23 Nov 22 01:07:04 PM PST 23 70917337186 ps
T609 /workspace/coverage/default/6.rv_timer_random_reset.78036578626683630433559478925892034166514304976290641972307161816806250195043 Nov 22 01:04:07 PM PST 23 Nov 22 01:09:09 PM PST 23 60703901037 ps
T610 /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.25066873469842810417588413068353011389163222254480756315416657526395718463428 Nov 22 01:05:17 PM PST 23 Nov 22 01:18:49 PM PST 23 207522994332 ps
T611 /workspace/coverage/default/14.rv_timer_stress_all.69172716865309687100712106184038688736844712534681162139647637632750693579329 Nov 22 01:04:47 PM PST 23 Nov 22 01:31:34 PM PST 23 1048433034855 ps
T612 /workspace/coverage/default/92.rv_timer_random.64821107293678211386560641240264332442828145303102137851402563948638718868038 Nov 22 01:05:53 PM PST 23 Nov 22 01:07:06 PM PST 23 70917337186 ps
T613 /workspace/coverage/default/60.rv_timer_random.12132247417441703254727535005789773483415524642161853144537009429586413079609 Nov 22 01:05:50 PM PST 23 Nov 22 01:07:04 PM PST 23 70917337186 ps
T614 /workspace/coverage/default/79.rv_timer_random.88816741894182977748048618000419711752642354013939985564612295877394285721091 Nov 22 01:05:56 PM PST 23 Nov 22 01:07:08 PM PST 23 70917337186 ps
T615 /workspace/coverage/default/105.rv_timer_random.60110736258719205011154490096058147751216458420508918665798773197031771177749 Nov 22 01:06:12 PM PST 23 Nov 22 01:07:26 PM PST 23 70917337186 ps
T616 /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.105268868830464180464056516651697821571975514083689321727798980069238341707065 Nov 22 01:05:16 PM PST 23 Nov 22 01:15:35 PM PST 23 544575976458 ps
T617 /workspace/coverage/default/16.rv_timer_stress_all.91678203113377815133451307689398043319134355126241708148678354556148117191431 Nov 22 01:04:56 PM PST 23 Nov 22 01:31:50 PM PST 23 1048433034855 ps
T618 /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.107792032376474134167417595249818901233267949932895039743967744653229979543727 Nov 22 01:05:23 PM PST 23 Nov 22 01:19:04 PM PST 23 207522994332 ps
T619 /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.44869418873638167403144241219228771379806008333644770479540353242894561080821 Nov 22 01:05:55 PM PST 23 Nov 22 01:15:53 PM PST 23 544575976458 ps
T620 /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.89393507665765874640311576615212379822130653688665002755816340997523559311088 Nov 22 01:05:21 PM PST 23 Nov 22 01:15:35 PM PST 23 544575976458 ps

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.25631533334122788789163026174370931889748126004675252692007294696545228861898
Short name T10
Test name
Test status
Simulation time 207522994332 ps
CPU time 811.25 seconds
Started Nov 22 01:05:16 PM PST 23
Finished Nov 22 01:18:48 PM PST 23
Peak memory 199000 kb
Host smart-db6a521a-9f90-4f3b-aabe-12a0c1838e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563153333412278878916
3026174370931889748126004675252692007294696545228861898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_res
et.25631533334122788789163026174370931889748126004675252692007294696545228861898
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.38226100523356023773651010322426441999555916389139380224046449643482726945383
Short name T7
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1578.17 seconds
Started Nov 22 01:04:02 PM PST 23
Finished Nov 22 01:30:26 PM PST 23
Peak memory 191124 kb
Host smart-10349cae-08a6-48e4-9b1e-0f4b2830c174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38226100523356023773651010322426441999555916389139380224046449643482726945383 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.38226100523356023773651010322426441999555916389139380224046449643482726945383
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.95455019067971243724669921057871979781600749793388936274983468019271479868492
Short name T35
Test name
Test status
Simulation time 191367284 ps
CPU time 1.34 seconds
Started Nov 22 12:30:15 PM PST 23
Finished Nov 22 12:30:17 PM PST 23
Peak memory 195692 kb
Host smart-d0e26d84-3ecf-419b-9445-c6665c4a66ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95455019067971243724669921057871979781600749793388936274983468019271479868492 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.95455019067971243724669921057871979781600749793388936274983468019271479868492
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.44534007300863793537856802808096505860947686398026285466671750812865688869437
Short name T17
Test name
Test status
Simulation time 135135591 ps
CPU time 0.89 seconds
Started Nov 22 01:04:00 PM PST 23
Finished Nov 22 01:04:08 PM PST 23
Peak memory 214324 kb
Host smart-d18f34f0-86a7-41ff-9fe5-38ac2607657c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44534007300863793537856802808096505860947686398026285466671750812865688869437 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.44534007300863793537856802808096505860947686398026285466671750812865688869437
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.41745074014815680893356948525234912136015393754781238701137498665238592409789
Short name T42
Test name
Test status
Simulation time 61136183 ps
CPU time 0.86 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 183144 kb
Host smart-c0860ff8-9f4a-459c-9977-2a092ff02b53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745074014815680893356948525234912136015393754781238701137498665238592409789 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.41745074014815680893356948525234912136015393754781238701137498665238592409789
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.102038698159496132354021310354550523683462376191307523682199648250478052434634
Short name T262
Test name
Test status
Simulation time 544575976458 ps
CPU time 609.39 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:13:57 PM PST 23
Peak memory 182936 kb
Host smart-cdab7788-b821-438d-9825-c86c9d3e8ac0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020386981594961323540213103545505236834623761913075236821996482504780524346
34 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.1020386981594961323540213103545505236834623761913
07523682199648250478052434634
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.74317440350278204988489521461447754393118602622573936663272204416070452291260
Short name T81
Test name
Test status
Simulation time 60703901037 ps
CPU time 305.07 seconds
Started Nov 22 01:04:48 PM PST 23
Finished Nov 22 01:09:55 PM PST 23
Peak memory 191260 kb
Host smart-13a254ed-a25f-40d9-97b4-9258a0733436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74317440350278204988489521461447754393118602622573936663272204416070452291260 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.rv_timer_random_reset.74317440350278204988489521461447754393118602622573936663272204416070452291260
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_random.39345824930908050762220263991003932739700967563511595687241926230014637499992
Short name T5
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.23 seconds
Started Nov 22 01:04:00 PM PST 23
Finished Nov 22 01:05:22 PM PST 23
Peak memory 183068 kb
Host smart-c4e6b065-8e45-4618-825c-99b999331e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39345824930908050762220263991003932739700967563511595687241926230014637499992 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.39345824930908050762220263991003932739700967563511595687241926230014637499992
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.31264989164204026952903510122525254153381332226379444842411925046076060487224
Short name T58
Test name
Test status
Simulation time 63082596 ps
CPU time 0.8 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 192236 kb
Host smart-cfdbf085-0ca4-405d-886d-ce0cc69ae878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264989164204026952903510122525254153381332226379444842411925046076060487224
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.31264989164204026952903510122525254153381332226379444
842411925046076060487224
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.23754307684896182022596316093002093884621438266610911055715648180720575951834
Short name T114
Test name
Test status
Simulation time 639238701 ps
CPU time 3.76 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:39 PM PST 23
Peak memory 192884 kb
Host smart-d4a0a7b3-b8cc-4e6b-8ef4-f859d3439968
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754307684896182022596316093002093884621438266610911055715648180720575951834 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.23754307684896182022596316093002093884621438266610911055715648180720575951834
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.110233293898567921124043576543415239256275993139652738145905973373062473215787
Short name T226
Test name
Test status
Simulation time 29618578 ps
CPU time 0.6 seconds
Started Nov 22 12:30:12 PM PST 23
Finished Nov 22 12:30:14 PM PST 23
Peak memory 183152 kb
Host smart-1b55499e-b6ed-41be-abac-0771c956fa88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110233293898567921124043576543415239256275993139652738145905973373062473215787 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.110233293898567921124043576543415239256275993139652738145905973373062473215787
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.115708452539732994719796265580996288676886270422496880529167016728891262987482
Short name T126
Test name
Test status
Simulation time 50082700 ps
CPU time 0.83 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 197048 kb
Host smart-e5a2cf05-4954-4bfe-9a12-3d82be33f495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157084525397329947197962655809962886768862
70422496880529167016728891262987482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.115708452539
732994719796265580996288676886270422496880529167016728891262987482
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.7653512777783287150997554632009897589064606481559985588616961228090950205836
Short name T222
Test name
Test status
Simulation time 24154336 ps
CPU time 0.57 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 183164 kb
Host smart-4f0e1880-8a31-4648-8f1a-4147d6434ecf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7653512777783287150997554632009897589064606481559985588616961228090950205836 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.7653512777783287150997554632009897589064606481559985588616961228090950205836
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.57574032649708194899086575782286814491746055992053626542630769288204280184106
Short name T229
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:17 PM PST 23
Finished Nov 22 12:30:19 PM PST 23
Peak memory 182808 kb
Host smart-b8e7f2ee-06f2-4d05-9177-3a1d10ee7ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57574032649708194899086575782286814491746055992053626542630769288204280184106 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.57574032649708194899086575782286814491746055992053626542630769288204280184106
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.82358880985675841856111767149567415600946616365550744447423557465788185208467
Short name T156
Test name
Test status
Simulation time 63082596 ps
CPU time 0.8 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:35 PM PST 23
Peak memory 193624 kb
Host smart-88218ee7-9e11-4461-85a6-b6b754ed376d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82358880985675841856111767149567415600946616365550744447423557465788185208467
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.823588809856758418561117671495674156009466163655507444
47423557465788185208467
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.70411627189618030915294736627940270353178599539629650172905565924681480964056
Short name T234
Test name
Test status
Simulation time 261313153 ps
CPU time 2.66 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:38 PM PST 23
Peak memory 197936 kb
Host smart-b344e09d-c45e-41c8-9036-57f44f7967ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70411627189618030915294736627940270353178599539629650172905565924681480964056 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.70411627189618030915294736627940270353178599539629650172905565924681480964056
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.50035277482492788222861937374172826597823563672026954725820495360793965884018
Short name T215
Test name
Test status
Simulation time 191367284 ps
CPU time 1.34 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 195672 kb
Host smart-4278b3de-4f6b-4cb9-aa8c-b28366664049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50035277482492788222861937374172826597823563672026954725820495360793965884018 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.50035277482492788222861937374172826597823563672026954725820495360793965884018
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.65343870169323930922184546344688799082810232678504152196081424845047045846077
Short name T51
Test name
Test status
Simulation time 61136183 ps
CPU time 0.81 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 182908 kb
Host smart-cdcce2c6-886b-4a14-b93f-3c62935d0c20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65343870169323930922184546344688799082810232678504152196081424845047045846077 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.65343870169323930922184546344688799082810232678504152196081424845047045846077
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.79573931997866676766227715341763522742848663097367950111185420379949947262600
Short name T12
Test name
Test status
Simulation time 639238701 ps
CPU time 3.66 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 192916 kb
Host smart-094b5063-c6cb-4caf-ac00-517378111bee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79573931997866676766227715341763522742848663097367950111185420379949947262600 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.79573931997866676766227715341763522742848663097367950111185420379949947262600
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.75017594193791715048778793513573390126035729690176076674755642728012685030242
Short name T178
Test name
Test status
Simulation time 29618578 ps
CPU time 0.58 seconds
Started Nov 22 12:30:08 PM PST 23
Finished Nov 22 12:30:10 PM PST 23
Peak memory 183380 kb
Host smart-e14dc385-79e7-4469-b86e-ab5659d17ec5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75017594193791715048778793513573390126035729690176076674755642728012685030242 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.75017594193791715048778793513573390126035729690176076674755642728012685030242
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.88209248120443295815547647777879877114100078126314501984192710512515849769518
Short name T159
Test name
Test status
Simulation time 50082700 ps
CPU time 0.83 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 196880 kb
Host smart-e63b9b5c-735a-48e5-8171-33fe9f9120ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8820924812044329581554764777787987711410007
8126314501984192710512515849769518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.8820924812044
3295815547647777879877114100078126314501984192710512515849769518
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.103325681474423473731229956718147364244693303076491135934991988721178925884915
Short name T154
Test name
Test status
Simulation time 24154336 ps
CPU time 0.58 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:21 PM PST 23
Peak memory 183172 kb
Host smart-11766c61-1a9c-4d8e-8099-299e7357492f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103325681474423473731229956718147364244693303076491135934991988721178925884915 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.103325681474423473731229956718147364244693303076491135934991988721178925884915
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.38994119750142856403260464333724776645815133079968714932470306716197619350588
Short name T162
Test name
Test status
Simulation time 27797164 ps
CPU time 0.57 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 182820 kb
Host smart-2c08a079-dfbe-4f34-a7d1-ee7cb30edaaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38994119750142856403260464333724776645815133079968714932470306716197619350588 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.38994119750142856403260464333724776645815133079968714932470306716197619350588
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.9716082233918719910258283610076257548240773699434047649886349655798892002448
Short name T221
Test name
Test status
Simulation time 63082596 ps
CPU time 0.78 seconds
Started Nov 22 12:30:15 PM PST 23
Finished Nov 22 12:30:17 PM PST 23
Peak memory 193640 kb
Host smart-c0786e12-bbf4-479a-b269-649a3e3e1da8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9716082233918719910258283610076257548240773699434047649886349655798892002448 -
assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.9716082233918719910258283610076257548240773699434047649
886349655798892002448
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.28667899577685994432269675390857641816009250807798177504303877668700428971127
Short name T231
Test name
Test status
Simulation time 261313153 ps
CPU time 2.7 seconds
Started Nov 22 12:30:13 PM PST 23
Finished Nov 22 12:30:17 PM PST 23
Peak memory 197924 kb
Host smart-2a1c55c3-ad86-4444-886b-5123d748e197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28667899577685994432269675390857641816009250807798177504303877668700428971127 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.28667899577685994432269675390857641816009250807798177504303877668700428971127
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.9272877656482346365636105164034573217875215367032379536882152790992003088856
Short name T224
Test name
Test status
Simulation time 50082700 ps
CPU time 0.9 seconds
Started Nov 22 12:30:35 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 197128 kb
Host smart-9827587c-bbae-41f9-8e55-7d7ddd64af01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9272877656482346365636105164034573217875215
367032379536882152790992003088856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.9272877656482
346365636105164034573217875215367032379536882152790992003088856
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.93390604094270559245481453073535679621322186521851876674674329956193210513442
Short name T210
Test name
Test status
Simulation time 24154336 ps
CPU time 0.61 seconds
Started Nov 22 12:30:34 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 182980 kb
Host smart-7d25759c-02e7-4f28-b364-1e91ed936c6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93390604094270559245481453073535679621322186521851876674674329956193210513442 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.93390604094270559245481453073535679621322186521851876674674329956193210513442
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.12647345219504528789720457105225578013377818938286668475204589137945425840247
Short name T186
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 182848 kb
Host smart-7f43b0c6-b03e-456b-b5a0-737e1d3f908b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12647345219504528789720457105225578013377818938286668475204589137945425840247 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.12647345219504528789720457105225578013377818938286668475204589137945425840247
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.22158925995023475364684718399479113273150411825977354772334734416435365618026
Short name T206
Test name
Test status
Simulation time 63082596 ps
CPU time 0.85 seconds
Started Nov 22 12:30:30 PM PST 23
Finished Nov 22 12:30:33 PM PST 23
Peak memory 192228 kb
Host smart-a25cfeb5-79d5-43eb-b208-efee81e9b7d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22158925995023475364684718399479113273150411825977354772334734416435365618026
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.22158925995023475364684718399479113273150411825977354
772334734416435365618026
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.44687886701022637654509845425504949409454504021995461777260311858387506871515
Short name T135
Test name
Test status
Simulation time 261313153 ps
CPU time 2.71 seconds
Started Nov 22 12:30:34 PM PST 23
Finished Nov 22 12:30:39 PM PST 23
Peak memory 197908 kb
Host smart-329e72ad-699d-49c5-ad00-496b524f5219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44687886701022637654509845425504949409454504021995461777260311858387506871515 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.44687886701022637654509845425504949409454504021995461777260311858387506871515
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.59938619339011140653866809279492841511771965136026023813695001217763038800440
Short name T48
Test name
Test status
Simulation time 191367284 ps
CPU time 1.35 seconds
Started Nov 22 12:30:26 PM PST 23
Finished Nov 22 12:30:29 PM PST 23
Peak memory 195672 kb
Host smart-5cf75744-a321-45d7-a582-6a344046e40d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59938619339011140653866809279492841511771965136026023813695001217763038800440 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.59938619339011140653866809279492841511771965136026023813695001217763038800440
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.81175959480885864362976968374851474301503068752138842929897115396107840513243
Short name T194
Test name
Test status
Simulation time 50082700 ps
CPU time 0.82 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 197080 kb
Host smart-722fbfa1-7e62-45ba-8a9a-48c433653673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8117595948088586436297696837485147430150306
8752138842929897115396107840513243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.811759594808
85864362976968374851474301503068752138842929897115396107840513243
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.39380755968530605920184702603758701460316346062329863276292844732460465484998
Short name T47
Test name
Test status
Simulation time 24154336 ps
CPU time 0.56 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 183164 kb
Host smart-0f432d2c-37ed-4070-974e-6a5ac3ec6580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380755968530605920184702603758701460316346062329863276292844732460465484998 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.39380755968530605920184702603758701460316346062329863276292844732460465484998
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.38835139193106478676704232584843977113475969181555454867862998273608190030354
Short name T105
Test name
Test status
Simulation time 27797164 ps
CPU time 0.67 seconds
Started Nov 22 12:30:29 PM PST 23
Finished Nov 22 12:30:32 PM PST 23
Peak memory 182864 kb
Host smart-1efb1580-7e9d-44b1-99b9-dccc5de6c86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835139193106478676704232584843977113475969181555454867862998273608190030354 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.38835139193106478676704232584843977113475969181555454867862998273608190030354
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.18972368859016735831883443785090922533467051160938718401928490704250354088020
Short name T163
Test name
Test status
Simulation time 261313153 ps
CPU time 2.63 seconds
Started Nov 22 12:30:24 PM PST 23
Finished Nov 22 12:30:30 PM PST 23
Peak memory 197956 kb
Host smart-531ad096-2e44-4c7e-956e-0cdf9b7cf4f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18972368859016735831883443785090922533467051160938718401928490704250354088020 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.18972368859016735831883443785090922533467051160938718401928490704250354088020
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.48334578456683524524207862833384963168893722746456046931785319935526380095162
Short name T192
Test name
Test status
Simulation time 191367284 ps
CPU time 1.37 seconds
Started Nov 22 12:30:27 PM PST 23
Finished Nov 22 12:30:30 PM PST 23
Peak memory 195688 kb
Host smart-51f1c806-c811-4fe7-8a15-c2cc362205d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48334578456683524524207862833384963168893722746456046931785319935526380095162 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.48334578456683524524207862833384963168893722746456046931785319935526380095162
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.20768436939993766414575457491399614622913924308443139849199180214586448404749
Short name T113
Test name
Test status
Simulation time 50082700 ps
CPU time 0.84 seconds
Started Nov 22 12:30:35 PM PST 23
Finished Nov 22 12:30:38 PM PST 23
Peak memory 197128 kb
Host smart-0e0cd92b-2016-45c2-802d-a0474505a8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076843693999376641457545749139961462291392
4308443139849199180214586448404749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.207684369399
93766414575457491399614622913924308443139849199180214586448404749
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.82784160814184991955476730457944268035499213753541811642302206938134327946108
Short name T44
Test name
Test status
Simulation time 24154336 ps
CPU time 0.6 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 183152 kb
Host smart-bf16560e-eb73-4012-a850-9ec704ab1fe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82784160814184991955476730457944268035499213753541811642302206938134327946108 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.82784160814184991955476730457944268035499213753541811642302206938134327946108
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.38340645793016746316848664423524648110333096624320495975394828315002756273637
Short name T97
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:46 PM PST 23
Finished Nov 22 12:30:47 PM PST 23
Peak memory 182828 kb
Host smart-15a2940a-2077-4701-9100-b6215cb7b4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340645793016746316848664423524648110333096624320495975394828315002756273637 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.38340645793016746316848664423524648110333096624320495975394828315002756273637
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.105607105131887318226574192470412590157200824333780829636008237104559740597430
Short name T54
Test name
Test status
Simulation time 63082596 ps
CPU time 0.83 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 192228 kb
Host smart-62e4b2dd-81a8-4b7a-938a-e6ba9c7711c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105607105131887318226574192470412590157200824333780829636008237104559740597430
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.1056071051318873182265741924704125901572008243337808
29636008237104559740597430
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.55764901381899340402959172038308983385963438808592965253271575522775926983763
Short name T155
Test name
Test status
Simulation time 261313153 ps
CPU time 2.63 seconds
Started Nov 22 12:30:23 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 197924 kb
Host smart-f3d49fca-c462-4e96-8724-c5d12f5678a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55764901381899340402959172038308983385963438808592965253271575522775926983763 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.55764901381899340402959172038308983385963438808592965253271575522775926983763
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.10559859387263382547537491782265171291505091846307514838004025691350860043775
Short name T134
Test name
Test status
Simulation time 191367284 ps
CPU time 1.34 seconds
Started Nov 22 12:30:22 PM PST 23
Finished Nov 22 12:30:26 PM PST 23
Peak memory 195584 kb
Host smart-c6cc4c5a-a0a5-40fb-9de7-62c9f65c39a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10559859387263382547537491782265171291505091846307514838004025691350860043775 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.10559859387263382547537491782265171291505091846307514838004025691350860043775
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.78682580645205182023853065136667377086780369894247005358227175353092691201754
Short name T177
Test name
Test status
Simulation time 50082700 ps
CPU time 0.83 seconds
Started Nov 22 12:30:34 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 197076 kb
Host smart-e3c2b98e-d87e-4fb5-a6e7-fb305a6d77ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7868258064520518202385306513666737708678036
9894247005358227175353092691201754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.786825806452
05182023853065136667377086780369894247005358227175353092691201754
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.12434489971649446297566594305196014633093540928912213609541011305827572181571
Short name T139
Test name
Test status
Simulation time 24154336 ps
CPU time 0.58 seconds
Started Nov 22 12:30:28 PM PST 23
Finished Nov 22 12:30:31 PM PST 23
Peak memory 183152 kb
Host smart-a14d4e76-4aa2-404b-9558-81b6914da795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434489971649446297566594305196014633093540928912213609541011305827572181571 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.12434489971649446297566594305196014633093540928912213609541011305827572181571
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.104680991188815733319448527840875901850891533272841223315998631030692014814794
Short name T230
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 182824 kb
Host smart-7c9c631d-9a8d-4aa5-929f-7a20383b24e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104680991188815733319448527840875901850891533272841223315998631030692014814794 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.104680991188815733319448527840875901850891533272841223315998631030692014814794
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.55281193158885989007440144596414594753170928818973282272695672151552089432987
Short name T182
Test name
Test status
Simulation time 63082596 ps
CPU time 0.78 seconds
Started Nov 22 12:30:35 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 192296 kb
Host smart-b607a18c-95ac-402e-9dcf-3e40e379f169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55281193158885989007440144596414594753170928818973282272695672151552089432987
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.55281193158885989007440144596414594753170928818973282
272695672151552089432987
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.66925779268430662096109353753557576270358872505544186918499681419927495639237
Short name T152
Test name
Test status
Simulation time 261313153 ps
CPU time 2.67 seconds
Started Nov 22 12:30:30 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 197968 kb
Host smart-30abf7c2-da52-474f-89bb-228606ddb477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66925779268430662096109353753557576270358872505544186918499681419927495639237 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.66925779268430662096109353753557576270358872505544186918499681419927495639237
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.38629494300276246364645833013737823510195326238633510371350173069246179383671
Short name T160
Test name
Test status
Simulation time 191367284 ps
CPU time 1.39 seconds
Started Nov 22 12:30:30 PM PST 23
Finished Nov 22 12:30:33 PM PST 23
Peak memory 195720 kb
Host smart-9b4cd3db-2105-4908-8f39-3a80a1ccf37a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629494300276246364645833013737823510195326238633510371350173069246179383671 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.38629494300276246364645833013737823510195326238633510371350173069246179383671
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.51265756501199135780434739170431599878969806380942908889563786249419433837941
Short name T13
Test name
Test status
Simulation time 50082700 ps
CPU time 0.89 seconds
Started Nov 22 12:30:35 PM PST 23
Finished Nov 22 12:30:38 PM PST 23
Peak memory 197128 kb
Host smart-0ae142ca-80cd-4841-9a1a-69c74eb0bf3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5126575650119913578043473917043159987896980
6380942908889563786249419433837941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.512657565011
99135780434739170431599878969806380942908889563786249419433837941
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.86656378995649757741138559943763937363734833937147831811013188027866924576596
Short name T130
Test name
Test status
Simulation time 24154336 ps
CPU time 0.61 seconds
Started Nov 22 12:30:54 PM PST 23
Finished Nov 22 12:30:56 PM PST 23
Peak memory 183184 kb
Host smart-5ba090c9-c5d2-47b6-9fe3-1e8c60ce1ede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86656378995649757741138559943763937363734833937147831811013188027866924576596 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.86656378995649757741138559943763937363734833937147831811013188027866924576596
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.49963047501388698077045985165342298975602054794020906130078437206365313494523
Short name T141
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:27 PM PST 23
Finished Nov 22 12:30:29 PM PST 23
Peak memory 182848 kb
Host smart-668ae489-5932-400b-b857-c8fa72134393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49963047501388698077045985165342298975602054794020906130078437206365313494523 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.49963047501388698077045985165342298975602054794020906130078437206365313494523
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.14172494886845602135638828764867109395254816859312443234650167058896968470436
Short name T196
Test name
Test status
Simulation time 63082596 ps
CPU time 0.77 seconds
Started Nov 22 12:30:49 PM PST 23
Finished Nov 22 12:30:50 PM PST 23
Peak memory 192236 kb
Host smart-3caaca26-066a-4d16-a2bd-fe6a5b430016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14172494886845602135638828764867109395254816859312443234650167058896968470436
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.14172494886845602135638828764867109395254816859312443
234650167058896968470436
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.6727225377060335381238691061482495792762134868690581521659297167221045089885
Short name T100
Test name
Test status
Simulation time 261313153 ps
CPU time 2.64 seconds
Started Nov 22 12:30:35 PM PST 23
Finished Nov 22 12:30:40 PM PST 23
Peak memory 197972 kb
Host smart-9a2dda78-376e-4736-a02a-282e71b38f19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6727225377060335381238691061482495792762134868690581521659297167221045089885 -assert nopostproc +UV
M_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.6727225377060335381238691061482495792762134868690581521659297167221045089885
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.47275672185806984177074360719801189077587173199269066007637505903818624232845
Short name T146
Test name
Test status
Simulation time 191367284 ps
CPU time 1.3 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 195648 kb
Host smart-f1e6d904-cd43-46d1-839b-eda574490c50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47275672185806984177074360719801189077587173199269066007637505903818624232845 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.47275672185806984177074360719801189077587173199269066007637505903818624232845
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.5604166400619774046669899684620597928570168492455042964269464725584827410242
Short name T174
Test name
Test status
Simulation time 50082700 ps
CPU time 0.86 seconds
Started Nov 22 12:30:29 PM PST 23
Finished Nov 22 12:30:33 PM PST 23
Peak memory 197084 kb
Host smart-f30ce2c7-2352-4b8d-863b-5a57e88f6879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5604166400619774046669899684620597928570168
492455042964269464725584827410242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.5604166400619
774046669899684620597928570168492455042964269464725584827410242
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.81842621979376589375052950532397817326221257332001803511218732727194969975816
Short name T142
Test name
Test status
Simulation time 24154336 ps
CPU time 0.59 seconds
Started Nov 22 12:30:50 PM PST 23
Finished Nov 22 12:30:51 PM PST 23
Peak memory 183168 kb
Host smart-7aad2221-120b-49e8-98a3-ba58bc98413d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81842621979376589375052950532397817326221257332001803511218732727194969975816 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.81842621979376589375052950532397817326221257332001803511218732727194969975816
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.37967905086033305260290837379524535798230401339565617722907805099279885416489
Short name T205
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 182808 kb
Host smart-6f1eebce-2a0e-460d-a059-b86e2c6239c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967905086033305260290837379524535798230401339565617722907805099279885416489 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.37967905086033305260290837379524535798230401339565617722907805099279885416489
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.57718397425722219649115877449174217059319495402624905852553215591612492404878
Short name T233
Test name
Test status
Simulation time 63082596 ps
CPU time 0.8 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 192200 kb
Host smart-fcdc7b14-b23b-4c8d-a855-387da16fc762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57718397425722219649115877449174217059319495402624905852553215591612492404878
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.57718397425722219649115877449174217059319495402624905
852553215591612492404878
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.89234032310313382966466384787805681599123446762473851857376165889741232728908
Short name T119
Test name
Test status
Simulation time 261313153 ps
CPU time 2.63 seconds
Started Nov 22 12:30:27 PM PST 23
Finished Nov 22 12:30:32 PM PST 23
Peak memory 197956 kb
Host smart-13c41ee4-daa5-4fde-a05a-49721d0cdd82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89234032310313382966466384787805681599123446762473851857376165889741232728908 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.89234032310313382966466384787805681599123446762473851857376165889741232728908
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.85202080355574837871180553641954186962935676799739477610812366124745980039924
Short name T170
Test name
Test status
Simulation time 191367284 ps
CPU time 1.37 seconds
Started Nov 22 12:30:28 PM PST 23
Finished Nov 22 12:30:31 PM PST 23
Peak memory 195684 kb
Host smart-954970a1-6af3-4ebe-8be3-538784a56722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85202080355574837871180553641954186962935676799739477610812366124745980039924 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.85202080355574837871180553641954186962935676799739477610812366124745980039924
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.28031860032116406432108776401542062929543262014169739132370031595425373338965
Short name T211
Test name
Test status
Simulation time 50082700 ps
CPU time 0.84 seconds
Started Nov 22 12:30:42 PM PST 23
Finished Nov 22 12:30:44 PM PST 23
Peak memory 197056 kb
Host smart-24342e57-7e27-4563-850b-05d5121dc621
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803186003211640643210877640154206292954326
2014169739132370031595425373338965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.280318600321
16406432108776401542062929543262014169739132370031595425373338965
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.75657003182063196703591873367160351081711455873555256303068509858519901490117
Short name T232
Test name
Test status
Simulation time 24154336 ps
CPU time 0.58 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:39 PM PST 23
Peak memory 183164 kb
Host smart-d543fb8e-7e31-43b1-b283-9cec8961f339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75657003182063196703591873367160351081711455873555256303068509858519901490117 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.75657003182063196703591873367160351081711455873555256303068509858519901490117
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.29069832312908312524830163759640598399532980511137845684690729496285390438998
Short name T150
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:31:06 PM PST 23
Finished Nov 22 12:31:07 PM PST 23
Peak memory 182820 kb
Host smart-be799af5-14ca-4f7c-9b0e-f950c8cf6a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29069832312908312524830163759640598399532980511137845684690729496285390438998 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.29069832312908312524830163759640598399532980511137845684690729496285390438998
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.44079606018638910175550163470713733720966858750761323052436782152622014201644
Short name T57
Test name
Test status
Simulation time 63082596 ps
CPU time 0.78 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 192200 kb
Host smart-e52c4a94-40b0-48c3-8243-60885de31eab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44079606018638910175550163470713733720966858750761323052436782152622014201644
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.44079606018638910175550163470713733720966858750761323
052436782152622014201644
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3252907671344232500028358903450322573327488021358083227228897241984419255024
Short name T167
Test name
Test status
Simulation time 261313153 ps
CPU time 2.7 seconds
Started Nov 22 12:30:57 PM PST 23
Finished Nov 22 12:31:01 PM PST 23
Peak memory 197956 kb
Host smart-e02cf50c-f4f2-491a-84a1-c1a1300a8243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252907671344232500028358903450322573327488021358083227228897241984419255024 -assert nopostproc +UV
M_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3252907671344232500028358903450322573327488021358083227228897241984419255024
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.78591719444491166007209538412146161060672609146463027303503042725641174023270
Short name T34
Test name
Test status
Simulation time 191367284 ps
CPU time 1.35 seconds
Started Nov 22 12:30:44 PM PST 23
Finished Nov 22 12:30:46 PM PST 23
Peak memory 195672 kb
Host smart-6c8c64c0-0fa8-41fb-b0d6-df0dc2d771e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78591719444491166007209538412146161060672609146463027303503042725641174023270 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.78591719444491166007209538412146161060672609146463027303503042725641174023270
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.42704690579236167725696812899259260331349618184001033480523716401910761962415
Short name T140
Test name
Test status
Simulation time 50082700 ps
CPU time 0.79 seconds
Started Nov 22 12:30:27 PM PST 23
Finished Nov 22 12:30:29 PM PST 23
Peak memory 197068 kb
Host smart-1bebba6d-5ab4-49bc-a66d-ce872a522513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270469057923616772569681289925926033134961
8184001033480523716401910761962415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.427046905792
36167725696812899259260331349618184001033480523716401910761962415
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.114625945271395373779309419245221256051190862334279823877327890168619646369891
Short name T108
Test name
Test status
Simulation time 24154336 ps
CPU time 0.58 seconds
Started Nov 22 12:30:55 PM PST 23
Finished Nov 22 12:30:56 PM PST 23
Peak memory 183176 kb
Host smart-fcf67948-4100-49cb-a76c-5372a68aa9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114625945271395373779309419245221256051190862334279823877327890168619646369891 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.114625945271395373779309419245221256051190862334279823877327890168619646369891
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.58232189072588688529103963693608892894415248501338964080149269042878930040204
Short name T195
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:31:06 PM PST 23
Finished Nov 22 12:31:08 PM PST 23
Peak memory 182820 kb
Host smart-bd671124-49dc-4bfd-afd8-69cbfb2509ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58232189072588688529103963693608892894415248501338964080149269042878930040204 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.58232189072588688529103963693608892894415248501338964080149269042878930040204
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.10230146823720026591390751293134696733074371232030869688696823321499709504934
Short name T228
Test name
Test status
Simulation time 63082596 ps
CPU time 0.76 seconds
Started Nov 22 12:30:48 PM PST 23
Finished Nov 22 12:30:50 PM PST 23
Peak memory 192236 kb
Host smart-54903011-0aa6-4102-a5c0-85a4803e2cfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10230146823720026591390751293134696733074371232030869688696823321499709504934
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.10230146823720026591390751293134696733074371232030869
688696823321499709504934
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.44494493678910769971384594221733897945540710475496501824720719359674900035363
Short name T189
Test name
Test status
Simulation time 261313153 ps
CPU time 2.65 seconds
Started Nov 22 12:30:50 PM PST 23
Finished Nov 22 12:30:54 PM PST 23
Peak memory 197956 kb
Host smart-48030584-e10e-4d24-81ae-093d64c55b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44494493678910769971384594221733897945540710475496501824720719359674900035363 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.44494493678910769971384594221733897945540710475496501824720719359674900035363
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.52490398166215034582925756754183639753155839225590596481577134425246405513948
Short name T197
Test name
Test status
Simulation time 191367284 ps
CPU time 1.35 seconds
Started Nov 22 12:30:46 PM PST 23
Finished Nov 22 12:30:48 PM PST 23
Peak memory 195672 kb
Host smart-77867197-07b9-4281-b786-d0e1e031574e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52490398166215034582925756754183639753155839225590596481577134425246405513948 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.52490398166215034582925756754183639753155839225590596481577134425246405513948
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.52837637622401345657927635822603635089688837876076321263848272565861892034964
Short name T193
Test name
Test status
Simulation time 50082700 ps
CPU time 0.81 seconds
Started Nov 22 12:30:50 PM PST 23
Finished Nov 22 12:30:51 PM PST 23
Peak memory 197012 kb
Host smart-aaf0a8f1-7244-4a60-945d-3191469c28a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5283763762240134565792763582260363508968883
7876076321263848272565861892034964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.528376376224
01345657927635822603635089688837876076321263848272565861892034964
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.63828625009677594573978322905898189007676224146877712830444403510822063758977
Short name T165
Test name
Test status
Simulation time 24154336 ps
CPU time 0.56 seconds
Started Nov 22 12:30:36 PM PST 23
Finished Nov 22 12:30:38 PM PST 23
Peak memory 183192 kb
Host smart-3d162823-85c3-4f2c-8957-d71a4e96efa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63828625009677594573978322905898189007676224146877712830444403510822063758977 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.63828625009677594573978322905898189007676224146877712830444403510822063758977
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.75393865726217746075480202543297559597680886726263489584770630264714305749329
Short name T145
Test name
Test status
Simulation time 27797164 ps
CPU time 0.54 seconds
Started Nov 22 12:30:45 PM PST 23
Finished Nov 22 12:30:46 PM PST 23
Peak memory 182828 kb
Host smart-f22a0779-1ebe-4ec7-b6d4-53779822fd3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75393865726217746075480202543297559597680886726263489584770630264714305749329 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.75393865726217746075480202543297559597680886726263489584770630264714305749329
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.18526061875817864946630439766546000968021515584777879828904905224638015366041
Short name T179
Test name
Test status
Simulation time 63082596 ps
CPU time 0.8 seconds
Started Nov 22 12:30:36 PM PST 23
Finished Nov 22 12:30:39 PM PST 23
Peak memory 192276 kb
Host smart-bd91acdf-1c1f-4987-a77b-1e3a1fbee3ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526061875817864946630439766546000968021515584777879828904905224638015366041
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.18526061875817864946630439766546000968021515584777879
828904905224638015366041
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.80012632406548361373881739729205884175344227918882399688595298807755188694619
Short name T212
Test name
Test status
Simulation time 261313153 ps
CPU time 2.62 seconds
Started Nov 22 12:31:05 PM PST 23
Finished Nov 22 12:31:09 PM PST 23
Peak memory 197904 kb
Host smart-07604a34-9c73-4d89-8236-f5af364eeb50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80012632406548361373881739729205884175344227918882399688595298807755188694619 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.80012632406548361373881739729205884175344227918882399688595298807755188694619
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.85887517754952724371077717137941967985300256457164143899078473822897424031573
Short name T33
Test name
Test status
Simulation time 191367284 ps
CPU time 1.35 seconds
Started Nov 22 12:30:59 PM PST 23
Finished Nov 22 12:31:01 PM PST 23
Peak memory 195692 kb
Host smart-eb337e90-3cb6-48a1-8a20-e318352ef1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85887517754952724371077717137941967985300256457164143899078473822897424031573 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.85887517754952724371077717137941967985300256457164143899078473822897424031573
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.35653140684781022278462773916935049513669191681226570006203972337495885369800
Short name T198
Test name
Test status
Simulation time 50082700 ps
CPU time 0.79 seconds
Started Nov 22 12:31:06 PM PST 23
Finished Nov 22 12:31:08 PM PST 23
Peak memory 197040 kb
Host smart-057bd6e8-ce4b-41b7-a298-291e458bc44c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565314068478102227846277391693504951366919
1681226570006203972337495885369800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.356531406847
81022278462773916935049513669191681226570006203972337495885369800
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.16432341052101254416716614385602388074709114043911756937826529395691917289640
Short name T124
Test name
Test status
Simulation time 24154336 ps
CPU time 0.59 seconds
Started Nov 22 12:30:49 PM PST 23
Finished Nov 22 12:30:50 PM PST 23
Peak memory 183236 kb
Host smart-a2777cd9-11fd-4eda-8678-c5628839b877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16432341052101254416716614385602388074709114043911756937826529395691917289640 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.16432341052101254416716614385602388074709114043911756937826529395691917289640
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.31659036858108608712704497590827723754008978048387918545753315138465289653288
Short name T143
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:44 PM PST 23
Finished Nov 22 12:30:46 PM PST 23
Peak memory 182812 kb
Host smart-48f11412-b0b8-4d72-bca4-a78e4d7e45c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659036858108608712704497590827723754008978048387918545753315138465289653288 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.31659036858108608712704497590827723754008978048387918545753315138465289653288
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.115467199838379081694972305850907654357607295153902490260694299338015256189778
Short name T158
Test name
Test status
Simulation time 63082596 ps
CPU time 0.82 seconds
Started Nov 22 12:30:41 PM PST 23
Finished Nov 22 12:30:43 PM PST 23
Peak memory 192312 kb
Host smart-8954b00d-ad28-424f-8581-f39014e576fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115467199838379081694972305850907654357607295153902490260694299338015256189778
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.1154671998383790816949723058509076543576072951539024
90260694299338015256189778
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.113060215912834122407388644144369753882849730734218500793209214811041352120205
Short name T136
Test name
Test status
Simulation time 261313153 ps
CPU time 2.57 seconds
Started Nov 22 12:30:53 PM PST 23
Finished Nov 22 12:30:57 PM PST 23
Peak memory 197924 kb
Host smart-d109fb3a-5db2-43dc-ab04-ed4b53f168f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113060215912834122407388644144369753882849730734218500793209214811041352120205 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.113060215912834122407388644144369753882849730734218500793209214811041352120205
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.58938330123738264169265096971481560635130505008505778912416738385210336448019
Short name T203
Test name
Test status
Simulation time 191367284 ps
CPU time 1.3 seconds
Started Nov 22 12:30:51 PM PST 23
Finished Nov 22 12:30:54 PM PST 23
Peak memory 195656 kb
Host smart-7cdd5a65-8088-4319-83d5-de9da5a8b0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58938330123738264169265096971481560635130505008505778912416738385210336448019 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.58938330123738264169265096971481560635130505008505778912416738385210336448019
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.29264747482949400999315914081120919412157949185687439392883037701439609221722
Short name T49
Test name
Test status
Simulation time 61136183 ps
CPU time 0.86 seconds
Started Nov 22 12:30:34 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 182980 kb
Host smart-f8c431a4-0ab5-41cf-9473-9e4fac48361e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29264747482949400999315914081120919412157949185687439392883037701439609221722 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.29264747482949400999315914081120919412157949185687439392883037701439609221722
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.50617065833839371543950542204296309865816070931822182541974681708770650594915
Short name T191
Test name
Test status
Simulation time 639238701 ps
CPU time 3.77 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 192812 kb
Host smart-95c34970-2fa6-4420-8766-7a5a69777a1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50617065833839371543950542204296309865816070931822182541974681708770650594915 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.50617065833839371543950542204296309865816070931822182541974681708770650594915
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.83065196401100141574077840527329879229482381580852529901212804124442732945868
Short name T132
Test name
Test status
Simulation time 29618578 ps
CPU time 0.58 seconds
Started Nov 22 12:30:29 PM PST 23
Finished Nov 22 12:30:31 PM PST 23
Peak memory 183176 kb
Host smart-dd01d87f-dfa3-4c4c-bdab-fb2e6da11671
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83065196401100141574077840527329879229482381580852529901212804124442732945868 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.83065196401100141574077840527329879229482381580852529901212804124442732945868
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.93333798758735377656331811678690582609000202219252189392817537197881713010280
Short name T220
Test name
Test status
Simulation time 50082700 ps
CPU time 0.81 seconds
Started Nov 22 12:30:34 PM PST 23
Finished Nov 22 12:30:37 PM PST 23
Peak memory 197032 kb
Host smart-3b9e3b1c-3fda-45a1-a680-80e1e9a9b343
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9333379875873537765633181167869058260900020
2219252189392817537197881713010280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.9333379875873
5377656331811678690582609000202219252189392817537197881713010280
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.77031172536105802445231054960648061174290140052850653147897046833176067795596
Short name T131
Test name
Test status
Simulation time 24154336 ps
CPU time 0.59 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:21 PM PST 23
Peak memory 183120 kb
Host smart-29ff9647-8453-4541-8dbe-6dfdc07350de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77031172536105802445231054960648061174290140052850653147897046833176067795596 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.77031172536105802445231054960648061174290140052850653147897046833176067795596
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.104956824166500666862957952334471894081355646396892054442513048214344133712375
Short name T164
Test name
Test status
Simulation time 27797164 ps
CPU time 0.61 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 182868 kb
Host smart-83529068-2bb6-4fd7-a06c-c9999de0f44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104956824166500666862957952334471894081355646396892054442513048214344133712375 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.104956824166500666862957952334471894081355646396892054442513048214344133712375
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3384952144706192814327783910561101057982178994704581388272391172324619379261
Short name T43
Test name
Test status
Simulation time 63082596 ps
CPU time 0.77 seconds
Started Nov 22 12:30:24 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 193640 kb
Host smart-f18370a9-bff7-42cc-8c2a-f77b2e94f5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384952144706192814327783910561101057982178994704581388272391172324619379261 -
assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.3384952144706192814327783910561101057982178994704581388
272391172324619379261
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.104197854084776741786215555414946144542395074121242089139152266718972876140188
Short name T169
Test name
Test status
Simulation time 261313153 ps
CPU time 2.67 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:30 PM PST 23
Peak memory 197960 kb
Host smart-f3837bcc-527f-40e0-8ae8-24620595ad80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104197854084776741786215555414946144542395074121242089139152266718972876140188 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.104197854084776741786215555414946144542395074121242089139152266718972876140188
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.83305533637205159332155796400849067519312069405543120239164981339316435508386
Short name T200
Test name
Test status
Simulation time 191367284 ps
CPU time 1.38 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 195624 kb
Host smart-dfeaff90-5d20-4993-826d-33656127bf91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83305533637205159332155796400849067519312069405543120239164981339316435508386 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.83305533637205159332155796400849067519312069405543120239164981339316435508386
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.47521527047342388077728251458708416627903684865717853541089394882819356740677
Short name T101
Test name
Test status
Simulation time 27797164 ps
CPU time 0.58 seconds
Started Nov 22 12:30:40 PM PST 23
Finished Nov 22 12:30:41 PM PST 23
Peak memory 182928 kb
Host smart-135d7997-24a5-4258-993a-6f4006f02244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47521527047342388077728251458708416627903684865717853541089394882819356740677 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.47521527047342388077728251458708416627903684865717853541089394882819356740677
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.111167698642709757453101863306237229999479148335761615914366533734690060054987
Short name T107
Test name
Test status
Simulation time 27797164 ps
CPU time 0.54 seconds
Started Nov 22 12:30:53 PM PST 23
Finished Nov 22 12:30:54 PM PST 23
Peak memory 182832 kb
Host smart-283a5afd-0f1c-4d94-ab34-08c9daba95aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111167698642709757453101863306237229999479148335761615914366533734690060054987 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.111167698642709757453101863306237229999479148335761615914366533734690060054987
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.20817891238079565668075098834118594281504904624450597920492941314309958214185
Short name T219
Test name
Test status
Simulation time 27797164 ps
CPU time 0.54 seconds
Started Nov 22 12:31:07 PM PST 23
Finished Nov 22 12:31:08 PM PST 23
Peak memory 182836 kb
Host smart-97cb9c4c-e022-4525-aaaf-1c2d196dbf61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20817891238079565668075098834118594281504904624450597920492941314309958214185 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.20817891238079565668075098834118594281504904624450597920492941314309958214185
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.87859807607580681193739791339429185265224800801684448493861333834285432504679
Short name T106
Test name
Test status
Simulation time 27797164 ps
CPU time 0.57 seconds
Started Nov 22 12:30:44 PM PST 23
Finished Nov 22 12:30:45 PM PST 23
Peak memory 182836 kb
Host smart-a91f3ed8-9cad-43a7-9805-0df02d9c35fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87859807607580681193739791339429185265224800801684448493861333834285432504679 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.87859807607580681193739791339429185265224800801684448493861333834285432504679
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.82264250198001422198006529313368463990232079580958510475153268047210088207407
Short name T52
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:38 PM PST 23
Finished Nov 22 12:30:40 PM PST 23
Peak memory 182864 kb
Host smart-2d856fe9-7300-4290-982e-66cc1bc424e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82264250198001422198006529313368463990232079580958510475153268047210088207407 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.82264250198001422198006529313368463990232079580958510475153268047210088207407
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.48430902183981177419871899388271852253173099969574675813375347635443647091212
Short name T149
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:30 PM PST 23
Finished Nov 22 12:30:33 PM PST 23
Peak memory 182844 kb
Host smart-3683e6bd-15bf-463d-be57-f278b607fd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48430902183981177419871899388271852253173099969574675813375347635443647091212 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.48430902183981177419871899388271852253173099969574675813375347635443647091212
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.80202672305638460464753893689325130917911930625390387720080132027708902675550
Short name T190
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:31:10 PM PST 23
Finished Nov 22 12:31:12 PM PST 23
Peak memory 182824 kb
Host smart-468717e9-56fa-4da7-9c61-105a62786c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80202672305638460464753893689325130917911930625390387720080132027708902675550 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.80202672305638460464753893689325130917911930625390387720080132027708902675550
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.98028839311660250655347067648318531928772731583847597341437827127936199321309
Short name T144
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:40 PM PST 23
Finished Nov 22 12:30:41 PM PST 23
Peak memory 182928 kb
Host smart-64eb5532-308a-4c65-89cd-bd2e643bdbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98028839311660250655347067648318531928772731583847597341437827127936199321309 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.98028839311660250655347067648318531928772731583847597341437827127936199321309
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.57542407190359048366207562605515193418079007654238574699692453606683277638028
Short name T188
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:31:10 PM PST 23
Finished Nov 22 12:31:12 PM PST 23
Peak memory 182824 kb
Host smart-facacbc9-00d8-40ce-8fef-6cbb7f6f8fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57542407190359048366207562605515193418079007654238574699692453606683277638028 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.57542407190359048366207562605515193418079007654238574699692453606683277638028
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.6805730673900993747655600441459116553036274087692787181347414404094831125985
Short name T225
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:40 PM PST 23
Finished Nov 22 12:30:41 PM PST 23
Peak memory 182928 kb
Host smart-e9856aac-58f7-4dbf-9be2-6436ea529200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6805730673900993747655600441459116553036274087692787181347414404094831125985 -assert nopostproc +UV
M_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.6805730673900993747655600441459116553036274087692787181347414404094831125985
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.46585753871610868616407958651482398113292918210379793063964420278344541865293
Short name T39
Test name
Test status
Simulation time 61136183 ps
CPU time 0.82 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:23 PM PST 23
Peak memory 183068 kb
Host smart-5bccc2ed-d6de-4644-ae8e-6036d6a1998c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46585753871610868616407958651482398113292918210379793063964420278344541865293 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.46585753871610868616407958651482398113292918210379793063964420278344541865293
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.30978938644113742485409373732764903822415820730657226738268421649271583953072
Short name T123
Test name
Test status
Simulation time 639238701 ps
CPU time 3.9 seconds
Started Nov 22 12:30:28 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 192548 kb
Host smart-e7a4d05b-37ed-4636-9fbf-5bec4164270b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30978938644113742485409373732764903822415820730657226738268421649271583953072 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.30978938644113742485409373732764903822415820730657226738268421649271583953072
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.73670478089615148036243328739889333587592190199754192238762447581595353311019
Short name T214
Test name
Test status
Simulation time 29618578 ps
CPU time 0.61 seconds
Started Nov 22 12:30:23 PM PST 23
Finished Nov 22 12:30:27 PM PST 23
Peak memory 183180 kb
Host smart-812236ca-ce7a-4705-9fc4-d70f59b8325d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73670478089615148036243328739889333587592190199754192238762447581595353311019 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.73670478089615148036243328739889333587592190199754192238762447581595353311019
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.70209706418088863597369303361209739490542918962691291550462049671981807295389
Short name T216
Test name
Test status
Simulation time 50082700 ps
CPU time 0.93 seconds
Started Nov 22 12:30:29 PM PST 23
Finished Nov 22 12:30:32 PM PST 23
Peak memory 197084 kb
Host smart-3ece684e-b8c5-48e0-ab7c-e3f4a8884fb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7020970641808886359736930336120973949054291
8962691291550462049671981807295389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.7020970641808
8863597369303361209739490542918962691291550462049671981807295389
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.67148154647842266063022588832714848000070425264565244273747154335851425722583
Short name T185
Test name
Test status
Simulation time 24154336 ps
CPU time 0.6 seconds
Started Nov 22 12:30:28 PM PST 23
Finished Nov 22 12:30:31 PM PST 23
Peak memory 182888 kb
Host smart-6a471468-e7c1-4610-8996-0ff9adb39cf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67148154647842266063022588832714848000070425264565244273747154335851425722583 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.67148154647842266063022588832714848000070425264565244273747154335851425722583
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.66670325059051290924811840020340756294897789495000036504890448714580619475679
Short name T109
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:22 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 182772 kb
Host smart-27dbb7a6-0f84-4da2-9501-844eac9019ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66670325059051290924811840020340756294897789495000036504890448714580619475679 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.66670325059051290924811840020340756294897789495000036504890448714580619475679
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.27120441250898624981951624354801686207571614285766002035747961881039781982322
Short name T14
Test name
Test status
Simulation time 63082596 ps
CPU time 0.82 seconds
Started Nov 22 12:30:18 PM PST 23
Finished Nov 22 12:30:20 PM PST 23
Peak memory 193688 kb
Host smart-944608a8-4303-417a-b145-5b8b3bfc64d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27120441250898624981951624354801686207571614285766002035747961881039781982322
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.271204412508986249819516243548016862075716142857660020
35747961881039781982322
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2814325948383130710047547763228664415243566312399791455842414495365227335485
Short name T172
Test name
Test status
Simulation time 261313153 ps
CPU time 2.7 seconds
Started Nov 22 12:30:17 PM PST 23
Finished Nov 22 12:30:21 PM PST 23
Peak memory 197916 kb
Host smart-5f66d81e-5347-4cbb-8e0e-9cef1b4d55bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814325948383130710047547763228664415243566312399791455842414495365227335485 -assert nopostproc +UV
M_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2814325948383130710047547763228664415243566312399791455842414495365227335485
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.542330788882932260902981982052214235175655962341023104334416874909720926125
Short name T115
Test name
Test status
Simulation time 191367284 ps
CPU time 1.34 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 195692 kb
Host smart-9b89fbf4-ef20-4b04-84d9-bf8e610897c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542330788882932260902981982052214235175655962341023104334416874909720926125 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.542330788882932260902981982052214235175655962341023104334416874909720926125
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.60262006386352354229611702584454289933549864688874532142099950739222721579739
Short name T180
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:52 PM PST 23
Finished Nov 22 12:30:54 PM PST 23
Peak memory 182856 kb
Host smart-86c65bf3-87cc-43c4-a19c-07fde04fe3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60262006386352354229611702584454289933549864688874532142099950739222721579739 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.60262006386352354229611702584454289933549864688874532142099950739222721579739
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.33180598618266784341631602583138162487720196201683918311725535748927289612469
Short name T217
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:31:11 PM PST 23
Finished Nov 22 12:31:12 PM PST 23
Peak memory 182824 kb
Host smart-f48e7e4a-9880-4bb6-9722-d00e332c469e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33180598618266784341631602583138162487720196201683918311725535748927289612469 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.33180598618266784341631602583138162487720196201683918311725535748927289612469
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.107297772646332152353189561850490780809737220491689766655132069891757188992711
Short name T207
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:54 PM PST 23
Finished Nov 22 12:30:56 PM PST 23
Peak memory 182824 kb
Host smart-3cc886d5-2da5-42ab-acf0-3fa888d19e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107297772646332152353189561850490780809737220491689766655132069891757188992711 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.107297772646332152353189561850490780809737220491689766655132069891757188992711
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3031807895983452825894232514783501203513205900601584681687287154066237428662
Short name T120
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:52 PM PST 23
Finished Nov 22 12:30:54 PM PST 23
Peak memory 182856 kb
Host smart-37c449fc-074d-4139-9b80-16e638f8c4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031807895983452825894232514783501203513205900601584681687287154066237428662 -assert nopostproc +UV
M_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3031807895983452825894232514783501203513205900601584681687287154066237428662
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.24068449134206822442134904716780321761181911983069015411695221429592655767218
Short name T175
Test name
Test status
Simulation time 27797164 ps
CPU time 0.58 seconds
Started Nov 22 12:30:53 PM PST 23
Finished Nov 22 12:30:55 PM PST 23
Peak memory 182856 kb
Host smart-bda14c2e-64df-4eed-b415-d0af41e111ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068449134206822442134904716780321761181911983069015411695221429592655767218 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.24068449134206822442134904716780321761181911983069015411695221429592655767218
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.72531088356515819359505669314975381105528499499024523836060267033466517566936
Short name T110
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:51 PM PST 23
Finished Nov 22 12:30:53 PM PST 23
Peak memory 182776 kb
Host smart-47d3abfa-322a-4892-9adb-baed98104c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72531088356515819359505669314975381105528499499024523836060267033466517566936 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.72531088356515819359505669314975381105528499499024523836060267033466517566936
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.72766843770071758247803832759007831706295509163562930534194080166953225522655
Short name T168
Test name
Test status
Simulation time 27797164 ps
CPU time 0.57 seconds
Started Nov 22 12:30:37 PM PST 23
Finished Nov 22 12:30:39 PM PST 23
Peak memory 182828 kb
Host smart-53ecf87b-0179-4ccf-97b4-4b8b7eec7d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72766843770071758247803832759007831706295509163562930534194080166953225522655 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.72766843770071758247803832759007831706295509163562930534194080166953225522655
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.13622374321737563569583468873566735072229508728982078099629713240371374946624
Short name T173
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:49 PM PST 23
Finished Nov 22 12:30:50 PM PST 23
Peak memory 182908 kb
Host smart-7d281df6-bf4e-480a-9dd0-8ffc294fbf57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622374321737563569583468873566735072229508728982078099629713240371374946624 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.13622374321737563569583468873566735072229508728982078099629713240371374946624
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.32127439359618048213082909752764483753723533050399947302370210929172040578261
Short name T204
Test name
Test status
Simulation time 27797164 ps
CPU time 0.54 seconds
Started Nov 22 12:30:44 PM PST 23
Finished Nov 22 12:30:45 PM PST 23
Peak memory 182832 kb
Host smart-9a36e66e-ec4e-46dd-bc44-1bbd58d87f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32127439359618048213082909752764483753723533050399947302370210929172040578261 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.32127439359618048213082909752764483753723533050399947302370210929172040578261
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.6302309757895332315382280979760877282148524723494001887664727848016723538340
Short name T98
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:48 PM PST 23
Finished Nov 22 12:30:49 PM PST 23
Peak memory 182908 kb
Host smart-f44b0ad3-ba35-4161-95f6-00b197f1bfb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6302309757895332315382280979760877282148524723494001887664727848016723538340 -assert nopostproc +UV
M_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.6302309757895332315382280979760877282148524723494001887664727848016723538340
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.81682621164262973788995979809169388310217487832296050950055499300043494315206
Short name T50
Test name
Test status
Simulation time 61136183 ps
CPU time 0.84 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 183152 kb
Host smart-704313f4-cbf8-4918-9dcd-70b31fa1ee93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81682621164262973788995979809169388310217487832296050950055499300043494315206 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.81682621164262973788995979809169388310217487832296050950055499300043494315206
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.81020482435308130258890659528958915017852365597341360955901031992187044076393
Short name T166
Test name
Test status
Simulation time 639238701 ps
CPU time 3.84 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:38 PM PST 23
Peak memory 192860 kb
Host smart-f922cafe-5480-4327-9df3-36871490df3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81020482435308130258890659528958915017852365597341360955901031992187044076393 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.81020482435308130258890659528958915017852365597341360955901031992187044076393
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.45396380521896041840612209617976577580325577491624762657043894954985091426985
Short name T46
Test name
Test status
Simulation time 29618578 ps
CPU time 0.58 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 183168 kb
Host smart-94fa3fe6-3849-4fac-a1fe-147314fc052d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45396380521896041840612209617976577580325577491624762657043894954985091426985 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.45396380521896041840612209617976577580325577491624762657043894954985091426985
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.109087232285753767146624959520299466771314709441034030583481783126149906924549
Short name T187
Test name
Test status
Simulation time 50082700 ps
CPU time 0.85 seconds
Started Nov 22 12:30:22 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 197076 kb
Host smart-b0078eea-7ff5-422a-b5ae-f017e7938112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090872322857537671466249595202994667713147
09441034030583481783126149906924549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.109087232285
753767146624959520299466771314709441034030583481783126149906924549
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.13274350446318852425102403793734532083141224735806589939221881253117757610074
Short name T171
Test name
Test status
Simulation time 24154336 ps
CPU time 0.61 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 183164 kb
Host smart-f210453b-17be-4e79-9d55-88f022dd690a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13274350446318852425102403793734532083141224735806589939221881253117757610074 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.13274350446318852425102403793734532083141224735806589939221881253117757610074
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.106594060664290680688838625885973976455945277196072740082263589431629044591775
Short name T117
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:32 PM PST 23
Finished Nov 22 12:30:36 PM PST 23
Peak memory 182848 kb
Host smart-32662b6f-de3d-44bd-b98f-da5ecd577e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106594060664290680688838625885973976455945277196072740082263589431629044591775 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.106594060664290680688838625885973976455945277196072740082263589431629044591775
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.17396528913013284528068257666988620580395937314245490246497211807391108217055
Short name T45
Test name
Test status
Simulation time 63082596 ps
CPU time 0.8 seconds
Started Nov 22 12:30:22 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 193620 kb
Host smart-2aa60158-c969-4b3d-afaa-be7b06ce4f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17396528913013284528068257666988620580395937314245490246497211807391108217055
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.173965289130132845280682576669886205803959373142454902
46497211807391108217055
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.56082914195682641477641727532573450461325003925596209952941338554079303172080
Short name T118
Test name
Test status
Simulation time 261313153 ps
CPU time 2.59 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 197952 kb
Host smart-ebd12f04-ff5a-40f6-b7ec-abdc22826d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56082914195682641477641727532573450461325003925596209952941338554079303172080 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.56082914195682641477641727532573450461325003925596209952941338554079303172080
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.58868997195282453526441448989499369200874327557673256571619645875798427370861
Short name T199
Test name
Test status
Simulation time 191367284 ps
CPU time 1.36 seconds
Started Nov 22 12:30:30 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 195676 kb
Host smart-30f29260-6734-41b5-adb2-d9e64f67b9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58868997195282453526441448989499369200874327557673256571619645875798427370861 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.58868997195282453526441448989499369200874327557673256571619645875798427370861
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.14087955397938560443598227572080324222284990782893780018073124685198672903127
Short name T151
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:31:08 PM PST 23
Finished Nov 22 12:31:09 PM PST 23
Peak memory 182776 kb
Host smart-77fb624a-9859-485b-80fa-7c40d45ed21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087955397938560443598227572080324222284990782893780018073124685198672903127 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.14087955397938560443598227572080324222284990782893780018073124685198672903127
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.27320595514502422536578410012305722267545908191906658368376320943429563036161
Short name T209
Test name
Test status
Simulation time 27797164 ps
CPU time 0.57 seconds
Started Nov 22 12:31:23 PM PST 23
Finished Nov 22 12:31:25 PM PST 23
Peak memory 182856 kb
Host smart-572a2c3c-2cbd-45ce-b9fa-c71524bb32a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27320595514502422536578410012305722267545908191906658368376320943429563036161 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.27320595514502422536578410012305722267545908191906658368376320943429563036161
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.57410235998982335724076536240726298227574206036282755889885294356344184620654
Short name T116
Test name
Test status
Simulation time 27797164 ps
CPU time 0.54 seconds
Started Nov 22 12:31:31 PM PST 23
Finished Nov 22 12:31:33 PM PST 23
Peak memory 182808 kb
Host smart-c39baee4-4f2f-4e61-a135-0c83355d4206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57410235998982335724076536240726298227574206036282755889885294356344184620654 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.57410235998982335724076536240726298227574206036282755889885294356344184620654
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.89444627917151419393245472815786143457558883025656243083206415978414155695777
Short name T103
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:31:30 PM PST 23
Finished Nov 22 12:31:32 PM PST 23
Peak memory 182808 kb
Host smart-03f0ab12-17b2-43c9-9bf5-41dbd2d8c893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89444627917151419393245472815786143457558883025656243083206415978414155695777 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.89444627917151419393245472815786143457558883025656243083206415978414155695777
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.59961275195004142348728209616970032337617339436611788580927644449963635427866
Short name T40
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:31:43 PM PST 23
Finished Nov 22 12:31:46 PM PST 23
Peak memory 182868 kb
Host smart-7e74b092-c1a0-423e-aa7e-c27e08fcc801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59961275195004142348728209616970032337617339436611788580927644449963635427866 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.59961275195004142348728209616970032337617339436611788580927644449963635427866
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.103745785268315302112233790862462991146600230496655293088560947038825231657735
Short name T227
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:31:48 PM PST 23
Finished Nov 22 12:31:51 PM PST 23
Peak memory 182856 kb
Host smart-a0eb5f45-d893-40c2-b3aa-23726156bce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103745785268315302112233790862462991146600230496655293088560947038825231657735 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.103745785268315302112233790862462991146600230496655293088560947038825231657735
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.68162771278839970752776066578541799725365939659523830547348314432302444787374
Short name T153
Test name
Test status
Simulation time 27797164 ps
CPU time 0.59 seconds
Started Nov 22 12:31:49 PM PST 23
Finished Nov 22 12:31:51 PM PST 23
Peak memory 182868 kb
Host smart-42029316-d586-403e-bc97-741f03ed6183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68162771278839970752776066578541799725365939659523830547348314432302444787374 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.68162771278839970752776066578541799725365939659523830547348314432302444787374
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.90790238916036098503997424563250754083061341218925352168407779806053427679104
Short name T111
Test name
Test status
Simulation time 27797164 ps
CPU time 0.58 seconds
Started Nov 22 12:31:25 PM PST 23
Finished Nov 22 12:31:27 PM PST 23
Peak memory 182844 kb
Host smart-ed3df79f-1ad8-46c4-8654-f46e6fdf1f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90790238916036098503997424563250754083061341218925352168407779806053427679104 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.90790238916036098503997424563250754083061341218925352168407779806053427679104
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.62182993905315705868921762145223459372669684222429505179365425612028090017287
Short name T99
Test name
Test status
Simulation time 27797164 ps
CPU time 0.61 seconds
Started Nov 22 12:31:25 PM PST 23
Finished Nov 22 12:31:26 PM PST 23
Peak memory 182904 kb
Host smart-d5387aab-a027-47f7-93cc-b8917ad9400f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62182993905315705868921762145223459372669684222429505179365425612028090017287 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.62182993905315705868921762145223459372669684222429505179365425612028090017287
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.82256708396903939411766516336956848578692689402321356074311455973900564252615
Short name T102
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:31:28 PM PST 23
Finished Nov 22 12:31:29 PM PST 23
Peak memory 183060 kb
Host smart-0b15a965-9857-4659-b091-0bef0502d850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82256708396903939411766516336956848578692689402321356074311455973900564252615 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.82256708396903939411766516336956848578692689402321356074311455973900564252615
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.100913129256976195674499350426142569535188063605899026310524006151472545338914
Short name T104
Test name
Test status
Simulation time 50082700 ps
CPU time 0.83 seconds
Started Nov 22 12:30:24 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 197072 kb
Host smart-05be3950-3d9b-4580-9db7-fdbd2543b535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009131292569761956744993504261425695351880
63605899026310524006151472545338914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.100913129256
976195674499350426142569535188063605899026310524006151472545338914
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.111514304843199286190606828773460294327867147625260918004994754450548139010338
Short name T121
Test name
Test status
Simulation time 24154336 ps
CPU time 0.6 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:20 PM PST 23
Peak memory 183112 kb
Host smart-c59c5683-c6b7-44ed-94fe-6dc2a8ca895a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111514304843199286190606828773460294327867147625260918004994754450548139010338 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.111514304843199286190606828773460294327867147625260918004994754450548139010338
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.111882990625697063896530271576474144661055821425877005357535537250191898230352
Short name T137
Test name
Test status
Simulation time 27797164 ps
CPU time 0.55 seconds
Started Nov 22 12:30:16 PM PST 23
Finished Nov 22 12:30:18 PM PST 23
Peak memory 182808 kb
Host smart-ce0a56b7-72f6-4c80-bcd3-2001f06ba9f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111882990625697063896530271576474144661055821425877005357535537250191898230352 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.111882990625697063896530271576474144661055821425877005357535537250191898230352
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.70713696782032460800920925178898417001783871418023891116305346538710379434187
Short name T53
Test name
Test status
Simulation time 63082596 ps
CPU time 0.79 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 193648 kb
Host smart-aae3e5d7-5314-46d4-bac6-71de746caa20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70713696782032460800920925178898417001783871418023891116305346538710379434187
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.707136967820324608009209251788984170017838714180238911
16305346538710379434187
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.44148024589557008459263673921118366677142453550429668945512004293970666410495
Short name T213
Test name
Test status
Simulation time 261313153 ps
CPU time 2.58 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:26 PM PST 23
Peak memory 197908 kb
Host smart-a5e1f0ab-67a2-4633-a06d-1402896888b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44148024589557008459263673921118366677142453550429668945512004293970666410495 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.44148024589557008459263673921118366677142453550429668945512004293970666410495
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.23107046140886952710226174822291388886880376245799440249268134365267215221848
Short name T181
Test name
Test status
Simulation time 191367284 ps
CPU time 1.35 seconds
Started Nov 22 12:30:23 PM PST 23
Finished Nov 22 12:30:27 PM PST 23
Peak memory 195664 kb
Host smart-6a0c525c-aab8-431c-b92a-cc8ac1ec455e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23107046140886952710226174822291388886880376245799440249268134365267215221848 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.23107046140886952710226174822291388886880376245799440249268134365267215221848
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.38900122568915362269815738244087040805504051975804262723167351111864038316957
Short name T147
Test name
Test status
Simulation time 50082700 ps
CPU time 0.8 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 197040 kb
Host smart-b6c7f036-5509-4236-aa22-c61fcbbcd4b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890012256891536226981573824408704080550405
1975804262723167351111864038316957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3890012256891
5362269815738244087040805504051975804262723167351111864038316957
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.36481562237933774193579341234954261954538731662725236185619188068503511771933
Short name T129
Test name
Test status
Simulation time 24154336 ps
CPU time 0.58 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 183180 kb
Host smart-4368f0d7-ce24-4873-8635-3c208cbb8a6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36481562237933774193579341234954261954538731662725236185619188068503511771933 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.36481562237933774193579341234954261954538731662725236185619188068503511771933
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.101539098312722961868281190212286831231750547337379018802286591743560032994671
Short name T202
Test name
Test status
Simulation time 27797164 ps
CPU time 0.57 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:22 PM PST 23
Peak memory 182868 kb
Host smart-13b0e03a-ae72-4a05-bb30-e3410dc679e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101539098312722961868281190212286831231750547337379018802286591743560032994671 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.101539098312722961868281190212286831231750547337379018802286591743560032994671
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.101347376062393154612924630980489225065509903311201008602935448171457599022653
Short name T56
Test name
Test status
Simulation time 63082596 ps
CPU time 0.78 seconds
Started Nov 22 12:30:19 PM PST 23
Finished Nov 22 12:30:21 PM PST 23
Peak memory 192232 kb
Host smart-7f39ebb2-6e95-4c76-adfa-c91a24aab282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101347376062393154612924630980489225065509903311201008602935448171457599022653
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.10134737606239315461292463098048922506550990331120100
8602935448171457599022653
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.110797731355886004787967367013257457083677338328819570498475852034153569192241
Short name T122
Test name
Test status
Simulation time 261313153 ps
CPU time 2.51 seconds
Started Nov 22 12:30:18 PM PST 23
Finished Nov 22 12:30:21 PM PST 23
Peak memory 197936 kb
Host smart-4a6d1108-ed49-4d3c-a1ad-fd543edee4be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110797731355886004787967367013257457083677338328819570498475852034153569192241 -assert nopostproc +
UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.110797731355886004787967367013257457083677338328819570498475852034153569192241
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.56032089794050382310099268549245822599956925717214047878478152004571417495081
Short name T148
Test name
Test status
Simulation time 191367284 ps
CPU time 1.39 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:25 PM PST 23
Peak memory 195656 kb
Host smart-5dfce85a-eea6-47e5-97ba-7573083314e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56032089794050382310099268549245822599956925717214047878478152004571417495081 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.56032089794050382310099268549245822599956925717214047878478152004571417495081
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.109551263549075957677423155356511072472026343724133263126647968933837723637181
Short name T208
Test name
Test status
Simulation time 50082700 ps
CPU time 0.82 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 197076 kb
Host smart-6198d29b-58f6-4394-b4e5-16ae0a6360ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095512635490759576774231553565110724720263
43724133263126647968933837723637181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.109551263549
075957677423155356511072472026343724133263126647968933837723637181
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.100674142889382823987704709672605423397993871439329455397457208193951715706624
Short name T133
Test name
Test status
Simulation time 24154336 ps
CPU time 0.58 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 183192 kb
Host smart-fb1be3c4-f985-475a-b5dd-100c1c42884d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100674142889382823987704709672605423397993871439329455397457208193951715706624 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.100674142889382823987704709672605423397993871439329455397457208193951715706624
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.45182906529791936066254371142035075868774337331362536641069168916861120017858
Short name T176
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:23 PM PST 23
Finished Nov 22 12:30:26 PM PST 23
Peak memory 182848 kb
Host smart-6736382e-ad44-4184-9d41-5f8b5f9bd8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45182906529791936066254371142035075868774337331362536641069168916861120017858 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.45182906529791936066254371142035075868774337331362536641069168916861120017858
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.4122647082959968835119557349657476126718724583214711876191839778422434451922
Short name T161
Test name
Test status
Simulation time 63082596 ps
CPU time 0.81 seconds
Started Nov 22 12:30:27 PM PST 23
Finished Nov 22 12:30:30 PM PST 23
Peak memory 193640 kb
Host smart-9be97f47-8399-49a1-a18a-4d500861e06f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122647082959968835119557349657476126718724583214711876191839778422434451922 -
assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.4122647082959968835119557349657476126718724583214711876
191839778422434451922
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.14454647495587998291800015417869219005432963404006965295352581372675234424563
Short name T183
Test name
Test status
Simulation time 261313153 ps
CPU time 2.65 seconds
Started Nov 22 12:30:17 PM PST 23
Finished Nov 22 12:30:21 PM PST 23
Peak memory 197936 kb
Host smart-0c7fd35b-d70c-44bd-aa50-9e098cfd2181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454647495587998291800015417869219005432963404006965295352581372675234424563 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.14454647495587998291800015417869219005432963404006965295352581372675234424563
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.10845832595356626080630285349582353554724534062759533235956624626626388286533
Short name T218
Test name
Test status
Simulation time 191367284 ps
CPU time 1.33 seconds
Started Nov 22 12:30:41 PM PST 23
Finished Nov 22 12:30:43 PM PST 23
Peak memory 195716 kb
Host smart-49c11436-9474-4dd8-bc03-3f7123d7170d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10845832595356626080630285349582353554724534062759533235956624626626388286533 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.10845832595356626080630285349582353554724534062759533235956624626626388286533
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.66303336477408140148221014178575538904530270873263393441688731829734149400084
Short name T138
Test name
Test status
Simulation time 50082700 ps
CPU time 0.81 seconds
Started Nov 22 12:30:37 PM PST 23
Finished Nov 22 12:30:39 PM PST 23
Peak memory 197080 kb
Host smart-e1fddef0-d18d-46a6-8cfe-9b2a7e0da633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6630333647740814014822101417857553890453027
0873263393441688731829734149400084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.6630333647740
8140148221014178575538904530270873263393441688731829734149400084
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.88305743436029066845604879298039884317660894550374577678175758398635287896489
Short name T125
Test name
Test status
Simulation time 24154336 ps
CPU time 0.6 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 182792 kb
Host smart-bdd3addb-cf45-4098-8535-753472835529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88305743436029066845604879298039884317660894550374577678175758398635287896489 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.88305743436029066845604879298039884317660894550374577678175758398635287896489
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.64314675503048047155888025442309581324383435999354388772772386171960725436005
Short name T112
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:20 PM PST 23
Finished Nov 22 12:30:23 PM PST 23
Peak memory 182804 kb
Host smart-ef73bd3b-c185-422b-869a-8ba639b9a7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64314675503048047155888025442309581324383435999354388772772386171960725436005 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.64314675503048047155888025442309581324383435999354388772772386171960725436005
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.63740092344746018401461320349906063113753547332978735273124561302708483265618
Short name T55
Test name
Test status
Simulation time 63082596 ps
CPU time 0.79 seconds
Started Nov 22 12:30:31 PM PST 23
Finished Nov 22 12:30:34 PM PST 23
Peak memory 193644 kb
Host smart-b0af0454-03bb-4c71-a51e-5dfc2bc2e12a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63740092344746018401461320349906063113753547332978735273124561302708483265618
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.637400923447460184014613203499060631137535473329787352
73124561302708483265618
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.58248696842370191946988219124797124126114303396849394924087622223694199777080
Short name T184
Test name
Test status
Simulation time 261313153 ps
CPU time 2.77 seconds
Started Nov 22 12:30:27 PM PST 23
Finished Nov 22 12:30:32 PM PST 23
Peak memory 197948 kb
Host smart-0d17edda-4cdd-404c-951e-44a9205beafa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58248696842370191946988219124797124126114303396849394924087622223694199777080 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.58248696842370191946988219124797124126114303396849394924087622223694199777080
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4099034414401545462292168092338348936064875672162803367740071666354203823236
Short name T157
Test name
Test status
Simulation time 191367284 ps
CPU time 1.38 seconds
Started Nov 22 12:30:24 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 195700 kb
Host smart-9f924c60-58de-4ea3-a651-1d3935580ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099034414401545462292168092338348936064875672162803367740071666354203823236 -assert no
postproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.4099034414401545462292168092338348936064875672162803367740071666354203823236
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.66749641419901526050587445019566893973681088180267494273952083724358615594637
Short name T127
Test name
Test status
Simulation time 50082700 ps
CPU time 0.81 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 197080 kb
Host smart-9bf7e040-24b9-47f9-8e3a-08de26cc0e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6674964141990152605058744501956689397368108
8180267494273952083724358615594637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.6674964141990
1526050587445019566893973681088180267494273952083724358615594637
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.98522785514389557785982842197703066882238169935468942525880359734311254796189
Short name T223
Test name
Test status
Simulation time 24154336 ps
CPU time 0.57 seconds
Started Nov 22 12:30:25 PM PST 23
Finished Nov 22 12:30:28 PM PST 23
Peak memory 183192 kb
Host smart-bebea998-00a9-47b2-9386-db395c157c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98522785514389557785982842197703066882238169935468942525880359734311254796189 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.98522785514389557785982842197703066882238169935468942525880359734311254796189
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.89447647086348214876603901569651545620576089546948943637286593808753353106179
Short name T128
Test name
Test status
Simulation time 27797164 ps
CPU time 0.56 seconds
Started Nov 22 12:30:21 PM PST 23
Finished Nov 22 12:30:24 PM PST 23
Peak memory 182512 kb
Host smart-2598f8ab-f968-4209-8e65-79d4c41f3aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89447647086348214876603901569651545620576089546948943637286593808753353106179 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.89447647086348214876603901569651545620576089546948943637286593808753353106179
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.103918801796491255524122015052869711588542355578286679750549479469271151345134
Short name T41
Test name
Test status
Simulation time 63082596 ps
CPU time 0.81 seconds
Started Nov 22 12:30:30 PM PST 23
Finished Nov 22 12:30:33 PM PST 23
Peak memory 192220 kb
Host smart-d86cde7a-fc8e-45a0-9a2d-d72ebbce5d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103918801796491255524122015052869711588542355578286679750549479469271151345134
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.10391880179649125552412201505286971158854235557828667
9750549479469271151345134
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.13629027479429562399651869409229933405455761716264145700410793958892576105329
Short name T32
Test name
Test status
Simulation time 261313153 ps
CPU time 2.75 seconds
Started Nov 22 12:30:29 PM PST 23
Finished Nov 22 12:30:33 PM PST 23
Peak memory 197948 kb
Host smart-4f759451-4fc5-46c2-9523-fe6a2a350701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629027479429562399651869409229933405455761716264145700410793958892576105329 -assert nopostproc +U
VM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.13629027479429562399651869409229933405455761716264145700410793958892576105329
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.33247252428234993254599287464188869562780066049337683564441930160631422052075
Short name T201
Test name
Test status
Simulation time 191367284 ps
CPU time 1.38 seconds
Started Nov 22 12:30:35 PM PST 23
Finished Nov 22 12:30:38 PM PST 23
Peak memory 195744 kb
Host smart-267ff99d-7431-4242-9a96-d762415dfb8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33247252428234993254599287464188869562780066049337683564441930160631422052075 -assert n
opostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.33247252428234993254599287464188869562780066049337683564441930160631422052075
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.55764704666791986468154758155186033231083764054581130433211312695684649823728
Short name T38
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.57 seconds
Started Nov 22 01:04:00 PM PST 23
Finished Nov 22 01:04:38 PM PST 23
Peak memory 183064 kb
Host smart-7e278480-e53b-4b2a-bbdd-1f048e81ccdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55764704666791986468154758155186033231083764054581130433211312695684649823728 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.rv_timer_disabled.55764704666791986468154758155186033231083764054581130433211312695684649823728
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.70227875274758451451135558500696795719518406263835286059438652799970949262335
Short name T606
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.83 seconds
Started Nov 22 01:03:52 PM PST 23
Finished Nov 22 01:05:06 PM PST 23
Peak memory 182984 kb
Host smart-b55188fc-bad6-4851-9166-1f39d536cfe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70227875274758451451135558500696795719518406263835286059438652799970949262335 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.70227875274758451451135558500696795719518406263835286059438652799970949262335
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.30255977258028700177097062451081151301494307406862535231236216528891330703333
Short name T524
Test name
Test status
Simulation time 60703901037 ps
CPU time 289.43 seconds
Started Nov 22 01:03:56 PM PST 23
Finished Nov 22 01:08:47 PM PST 23
Peak memory 191288 kb
Host smart-bf978fc0-cd4e-4d6e-a800-d8fcf90a7ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30255977258028700177097062451081151301494307406862535231236216528891330703333 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.rv_timer_random_reset.30255977258028700177097062451081151301494307406862535231236216528891330703333
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.8146282001962530659325192260607590981018978535461658588240650357353417948060
Short name T495
Test name
Test status
Simulation time 207522994332 ps
CPU time 814.87 seconds
Started Nov 22 01:04:07 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 199012 kb
Host smart-6c1bdbb2-b721-4acc-8e03-80b4ba27199d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8146282001962530659325
192260607590981018978535461658588240650357353417948060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset
.8146282001962530659325192260607590981018978535461658588240650357353417948060
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.66433434551296613350993466791574532818775350861946203038888587238042134555908
Short name T269
Test name
Test status
Simulation time 544575976458 ps
CPU time 616.06 seconds
Started Nov 22 01:03:56 PM PST 23
Finished Nov 22 01:14:13 PM PST 23
Peak memory 183052 kb
Host smart-45eaf15c-6321-4134-81cb-da5d1fcc3f00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6643343455129661335099346679157453281877535086194620303888858723804213455590
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.66433434551296613350993466791574532818775350861946
203038888587238042134555908
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.105983638379959731179068668724598023340193095459226271371349006200927889779313
Short name T83
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.11 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:04:44 PM PST 23
Peak memory 183080 kb
Host smart-e5d15e2e-df63-4d3e-8d2e-640caef4e7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105983638379959731179068668724598023340193095459226271371349006200927889779313 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.rv_timer_disabled.105983638379959731179068668724598023340193095459226271371349006200927889779313
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.103190175752804972969174137364100121240214794741437936224467677795351649840036
Short name T501
Test name
Test status
Simulation time 60703901037 ps
CPU time 290.1 seconds
Started Nov 22 01:03:59 PM PST 23
Finished Nov 22 01:08:57 PM PST 23
Peak memory 191168 kb
Host smart-8c0feede-4c8d-4040-9302-eb7deff85ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103190175752804972969174137364100121240214794741437936224467677795351649840036 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.rv_timer_random_reset.103190175752804972969174137364100121240214794741437936224467677795351649840036
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.5195091565333682329062057906693010694741287463173863507943518084851209480571
Short name T19
Test name
Test status
Simulation time 135135591 ps
CPU time 0.96 seconds
Started Nov 22 01:04:03 PM PST 23
Finished Nov 22 01:04:09 PM PST 23
Peak memory 214136 kb
Host smart-53e63df6-9134-492e-9955-a31d3e0d719a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5195091565333682329062057906693010694741287463173863507943518084851209480571 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.5195091565333682329062057906693010694741287463173863507943518084851209480571
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.75167646712085686415665819876260524838648651164980395638702742307830724603027
Short name T391
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1604 seconds
Started Nov 22 01:04:03 PM PST 23
Finished Nov 22 01:30:52 PM PST 23
Peak memory 191124 kb
Host smart-14f67106-9802-4883-8138-9e4d09e4d925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75167646712085686415665819876260524838648651164980395638702742307830724603027 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.75167646712085686415665819876260524838648651164980395638702742307830724603027
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.109950031853314015837318779252555019457577564502108879324003302353164281020336
Short name T311
Test name
Test status
Simulation time 207522994332 ps
CPU time 833.95 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:18:00 PM PST 23
Peak memory 199088 kb
Host smart-16c3e5d3-fc03-4369-894d-66b831ee9f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099500318533140158373
18779252555019457577564502108879324003302353164281020336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_res
et.109950031853314015837318779252555019457577564502108879324003302353164281020336
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.79793236595623709964776432729227356724716600029113038859560448847594942452260
Short name T328
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.15 seconds
Started Nov 22 01:04:06 PM PST 23
Finished Nov 22 01:14:23 PM PST 23
Peak memory 183016 kb
Host smart-1c4b4865-b1ee-4617-a881-48f6899b05bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7979323659562370996477643272922735672471660002911303885956044884759494245226
0 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.7979323659562370996477643272922735672471660002911
3038859560448847594942452260
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.79115726875229975017533463946540386872544011355171335912559945402148007615910
Short name T282
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.51 seconds
Started Nov 22 01:04:05 PM PST 23
Finished Nov 22 01:04:43 PM PST 23
Peak memory 182956 kb
Host smart-89dd76c2-2386-498c-ab16-e0785b850941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79115726875229975017533463946540386872544011355171335912559945402148007615910 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.rv_timer_disabled.79115726875229975017533463946540386872544011355171335912559945402148007615910
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.9877435501538650799252006846142494261251521056396453091500436301173488590317
Short name T464
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.33 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:05:30 PM PST 23
Peak memory 183044 kb
Host smart-dd1eea63-681a-481b-a7e7-00fc7cf02ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9877435501538650799252006846142494261251521056396453091500436301173488590317 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.9877435501538650799252006846142494261251521056396453091500436301173488590317
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.68412723693221769072086919193327658116721804776927197306642012330671288311547
Short name T512
Test name
Test status
Simulation time 60703901037 ps
CPU time 302.83 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:09:18 PM PST 23
Peak memory 191156 kb
Host smart-2dbdc73c-83d6-451e-bdab-0278ed70d4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68412723693221769072086919193327658116721804776927197306642012330671288311547 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.rv_timer_random_reset.68412723693221769072086919193327658116721804776927197306642012330671288311547
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.49310025370672143895243596323084408640262436378275951309012861160279239961299
Short name T457
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1618.04 seconds
Started Nov 22 01:04:14 PM PST 23
Finished Nov 22 01:31:13 PM PST 23
Peak memory 191152 kb
Host smart-9da96152-6d47-45e9-baf4-19496d33226d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49310025370672143895243596323084408640262436378275951309012861160279239961299 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.49310025370672143895243596323084408640262436378275951309012861160279239961299
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.8279987846478308030122584595812037921637820301433330594712785498363255586020
Short name T255
Test name
Test status
Simulation time 207522994332 ps
CPU time 846.86 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 199088 kb
Host smart-a8401999-f766-43b8-af97-b48cb30fcfbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8279987846478308030122
584595812037921637820301433330594712785498363255586020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_rese
t.8279987846478308030122584595812037921637820301433330594712785498363255586020
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.37438836791801672729875515999119276279780537404462622235478272872196972352638
Short name T74
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.69 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183116 kb
Host smart-5f980c4e-2fc6-46d7-bc28-9e6bef00bab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438836791801672729875515999119276279780537404462622235478272872196972352638 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.37438836791801672729875515999119276279780537404462622235478272872196972352638
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.97812074901983114143672342487928944747557951903987365579023223936455343653539
Short name T390
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.52 seconds
Started Nov 22 01:05:52 PM PST 23
Finished Nov 22 01:07:06 PM PST 23
Peak memory 183068 kb
Host smart-3611d5b4-2f7e-489a-a2f2-ed8758e57dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97812074901983114143672342487928944747557951903987365579023223936455343653539 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.97812074901983114143672342487928944747557951903987365579023223936455343653539
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.36564561106464517711386797784499167367547924356305396534272577607518527842174
Short name T73
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.12 seconds
Started Nov 22 01:06:07 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 182976 kb
Host smart-88fd7392-29fb-4a06-be68-73178f2cf1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36564561106464517711386797784499167367547924356305396534272577607518527842174 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.36564561106464517711386797784499167367547924356305396534272577607518527842174
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.68210629622683799631305169651825764098434530995758315017348481952848644920575
Short name T377
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.52 seconds
Started Nov 22 01:06:06 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 182996 kb
Host smart-e5553d06-3bae-4d61-811e-cdff6a119b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68210629622683799631305169651825764098434530995758315017348481952848644920575 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.68210629622683799631305169651825764098434530995758315017348481952848644920575
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3475609711747525955615833312824290568974462337665840719381921944102446228664
Short name T517
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.05 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 183052 kb
Host smart-0322589f-05c5-4125-a08c-0e8c5ebb4d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475609711747525955615833312824290568974462337665840719381921944102446228664 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3475609711747525955615833312824290568974462337665840719381921944102446228664
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.60110736258719205011154490096058147751216458420508918665798773197031771177749
Short name T615
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.99 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:26 PM PST 23
Peak memory 183036 kb
Host smart-f688363d-4ec1-49b7-a6eb-29198d8f7abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60110736258719205011154490096058147751216458420508918665798773197031771177749 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.60110736258719205011154490096058147751216458420508918665798773197031771177749
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.105831896471103909648084586592972692238787723006363677245640609071458527190148
Short name T469
Test name
Test status
Simulation time 70917337186 ps
CPU time 71.8 seconds
Started Nov 22 01:06:07 PM PST 23
Finished Nov 22 01:07:19 PM PST 23
Peak memory 182988 kb
Host smart-b41bf6ce-7d22-41cc-83a5-595a72f973b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105831896471103909648084586592972692238787723006363677245640609071458527190148 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.105831896471103909648084586592972692238787723006363677245640609071458527190148
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.15999579413013973623380734688473902627724204970376420986044030738921449561262
Short name T538
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.26 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183088 kb
Host smart-d8093e3a-b2f8-42d9-8f63-974518c3600a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999579413013973623380734688473902627724204970376420986044030738921449561262 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.15999579413013973623380734688473902627724204970376420986044030738921449561262
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.97881706254223813475455305176133568016477192720951169992792240701384071459933
Short name T518
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.1 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183080 kb
Host smart-149a1819-b922-4cf1-99f1-d6a08aef6d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97881706254223813475455305176133568016477192720951169992792240701384071459933 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.97881706254223813475455305176133568016477192720951169992792240701384071459933
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.7293943400813043973598493145078391715141537088565957821237799685381972807766
Short name T588
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.44 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:24 PM PST 23
Peak memory 182952 kb
Host smart-779d1ac6-0868-49ba-9523-fb7f623576bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7293943400813043973598493145078391715141537088565957821237799685381972807766 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.7293943400813043973598493145078391715141537088565957821237799685381972807766
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.24234424709055045485184163386586218795924698786797320880193690771097459226340
Short name T406
Test name
Test status
Simulation time 544575976458 ps
CPU time 609.91 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:14:23 PM PST 23
Peak memory 183068 kb
Host smart-e26cd90e-31ce-4ead-a2c4-37bb33ad30a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423442470905504548518416338658621879592469878679732088019369077109745922634
0 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2423442470905504548518416338658621879592469878679
7320880193690771097459226340
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.39700249741889297400646037207926383871922257912533914132742346065087548090344
Short name T76
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.96 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:04:45 PM PST 23
Peak memory 183104 kb
Host smart-9b644f74-9ecb-4005-9ed1-32bb8054471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39700249741889297400646037207926383871922257912533914132742346065087548090344 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.rv_timer_disabled.39700249741889297400646037207926383871922257912533914132742346065087548090344
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.64830738934937055538692902569606767054008070255701058262810590643011892288035
Short name T581
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.81 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:05:28 PM PST 23
Peak memory 183040 kb
Host smart-66cbcc0b-5b5c-47b9-80bc-168875030eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64830738934937055538692902569606767054008070255701058262810590643011892288035 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.64830738934937055538692902569606767054008070255701058262810590643011892288035
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.44396010764088350182413547478996818290026747448725656482068961407392545849415
Short name T273
Test name
Test status
Simulation time 60703901037 ps
CPU time 289.16 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:09:04 PM PST 23
Peak memory 191208 kb
Host smart-93af5b0f-06a8-4e13-87e3-86d6f08c58da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44396010764088350182413547478996818290026747448725656482068961407392545849415 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.rv_timer_random_reset.44396010764088350182413547478996818290026747448725656482068961407392545849415
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.102806860624084435747578060481213089764638523726319563713214083117802305857439
Short name T460
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1606.71 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:31:00 PM PST 23
Peak memory 191152 kb
Host smart-752d5dd1-7067-4d18-a3ca-18d5bf6f463c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102806860624084435747578060481213089764638523726319563713214083117802305857439 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.102806860624084435747578060481213089764638523726319563713214083117802305857439
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.45800346936133538978306960093241833574690348715326333876572625810300625335844
Short name T589
Test name
Test status
Simulation time 207522994332 ps
CPU time 827.48 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:18:03 PM PST 23
Peak memory 198976 kb
Host smart-2e68d591-8dfd-40a3-8698-6cf30ce6a308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4580034693613353897830
6960093241833574690348715326333876572625810300625335844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_res
et.45800346936133538978306960093241833574690348715326333876572625810300625335844
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.78432749696138599617000201793091493518621796525764859241734013123791058183565
Short name T591
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.52 seconds
Started Nov 22 01:06:09 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 182996 kb
Host smart-99ae0459-85e9-4a1d-aaa9-c6c155692fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78432749696138599617000201793091493518621796525764859241734013123791058183565 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.78432749696138599617000201793091493518621796525764859241734013123791058183565
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.65942819410352476799305477403574142081935167045419748520511931533935118932266
Short name T400
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.4 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183084 kb
Host smart-96b9da30-55cb-488a-8f46-8a79b8df3b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65942819410352476799305477403574142081935167045419748520511931533935118932266 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.65942819410352476799305477403574142081935167045419748520511931533935118932266
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.68009724493011051868311233337006023418263250793960654946628710735287210324806
Short name T327
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.45 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183088 kb
Host smart-fb2f0164-5346-41ba-a822-fbff95594e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68009724493011051868311233337006023418263250793960654946628710735287210324806 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.68009724493011051868311233337006023418263250793960654946628710735287210324806
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.93133323951685605799494624651791891675248939902506343965059045876917788557239
Short name T415
Test name
Test status
Simulation time 70917337186 ps
CPU time 73 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183060 kb
Host smart-7d25111f-d3f1-436e-86f4-b31062da2352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93133323951685605799494624651791891675248939902506343965059045876917788557239 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.93133323951685605799494624651791891675248939902506343965059045876917788557239
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.63490808042742080188888043589638834820701671847697131860257419905061833229130
Short name T444
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.41 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:24 PM PST 23
Peak memory 183036 kb
Host smart-4dd7ad7d-ba7a-4d31-a321-81adacfd68e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63490808042742080188888043589638834820701671847697131860257419905061833229130 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.63490808042742080188888043589638834820701671847697131860257419905061833229130
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.110446553325447549986217127024586101185409039197813927519232773626668055362337
Short name T271
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.2 seconds
Started Nov 22 01:06:07 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183100 kb
Host smart-2ee6b776-78ac-4205-bfb0-96b4f331b239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110446553325447549986217127024586101185409039197813927519232773626668055362337 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.110446553325447549986217127024586101185409039197813927519232773626668055362337
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.76543039792139256170050399065635234851689307962058350769456720341900070185824
Short name T22
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.71 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183092 kb
Host smart-550feafb-a1ce-4cf4-9c16-72a726fbad29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76543039792139256170050399065635234851689307962058350769456720341900070185824 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.76543039792139256170050399065635234851689307962058350769456720341900070185824
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.98294657847189858156551208191874345601484750187979129498851651212207292416026
Short name T290
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.3 seconds
Started Nov 22 01:06:07 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 183008 kb
Host smart-5ba26b35-6292-4ac5-839f-381994000b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98294657847189858156551208191874345601484750187979129498851651212207292416026 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.98294657847189858156551208191874345601484750187979129498851651212207292416026
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2724707928970931216910481586600240883905753739155393033120571897028257068756
Short name T535
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.32 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183080 kb
Host smart-9e3afece-abea-491b-9c5f-6077831f8102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724707928970931216910481586600240883905753739155393033120571897028257068756 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2724707928970931216910481586600240883905753739155393033120571897028257068756
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.52832641476423795650793383677837125896776648758669930856996027532708043212830
Short name T510
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.65 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183052 kb
Host smart-1107f799-788e-4b58-ad7d-5d757305919a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52832641476423795650793383677837125896776648758669930856996027532708043212830 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.52832641476423795650793383677837125896776648758669930856996027532708043212830
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.75248853072641051096639957873589652729352770896009242925902282587695462769276
Short name T544
Test name
Test status
Simulation time 544575976458 ps
CPU time 609.83 seconds
Started Nov 22 01:04:14 PM PST 23
Finished Nov 22 01:14:25 PM PST 23
Peak memory 182968 kb
Host smart-b17fe060-f4cd-48da-8dfb-c027521e98e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7524885307264105109663995787358965272935277089600924292590228258769546276927
6 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.7524885307264105109663995787358965272935277089600
9242925902282587695462769276
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.75992994184634961492693650264852347282233436032314643946525600490267117580897
Short name T428
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.39 seconds
Started Nov 22 01:04:17 PM PST 23
Finished Nov 22 01:04:48 PM PST 23
Peak memory 183044 kb
Host smart-1cc86bf4-1f05-43f8-8616-a0b15f905bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75992994184634961492693650264852347282233436032314643946525600490267117580897 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.rv_timer_disabled.75992994184634961492693650264852347282233436032314643946525600490267117580897
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.55491898798014167172169411689822777653875462923968340944456638046538835232478
Short name T603
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.29 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:05:29 PM PST 23
Peak memory 182992 kb
Host smart-de6c8df3-f18c-4dd9-ba7c-a3eadb5bb40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55491898798014167172169411689822777653875462923968340944456638046538835232478 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.55491898798014167172169411689822777653875462923968340944456638046538835232478
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.80583977999006614462583778287921414171602217871077494927606014836768496261374
Short name T315
Test name
Test status
Simulation time 60703901037 ps
CPU time 304.93 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:09:19 PM PST 23
Peak memory 191184 kb
Host smart-3e75f920-7f8b-4b29-a010-8103105ac272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80583977999006614462583778287921414171602217871077494927606014836768496261374 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rv_timer_random_reset.80583977999006614462583778287921414171602217871077494927606014836768496261374
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.86116683519676484052764729431078668276490183432037987105601333880648782017974
Short name T26
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1596.2 seconds
Started Nov 22 01:04:19 PM PST 23
Finished Nov 22 01:30:56 PM PST 23
Peak memory 191256 kb
Host smart-d1c25c3b-dfe9-4480-a352-d5545402ae64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86116683519676484052764729431078668276490183432037987105601333880648782017974 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.86116683519676484052764729431078668276490183432037987105601333880648782017974
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.208315005270238517314181921979941820875988813313700619703971490769575170215
Short name T370
Test name
Test status
Simulation time 207522994332 ps
CPU time 831.57 seconds
Started Nov 22 01:04:16 PM PST 23
Finished Nov 22 01:18:09 PM PST 23
Peak memory 199064 kb
Host smart-06d58b09-dc03-417c-8b66-cd66e8b04f1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083150052702385173141
81921979941820875988813313700619703971490769575170215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset
.208315005270238517314181921979941820875988813313700619703971490769575170215
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.46345671896758972924556079542198052223255810665622415941550168402470646521487
Short name T304
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.73 seconds
Started Nov 22 01:06:06 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183080 kb
Host smart-1e6b0b43-f120-46bf-8bbe-3a90f3b48de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46345671896758972924556079542198052223255810665622415941550168402470646521487 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.46345671896758972924556079542198052223255810665622415941550168402470646521487
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.76834991614563448568018190335308623597389286522815502199416664689756378511790
Short name T360
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.94 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183036 kb
Host smart-c7525030-cea9-4402-a510-de03eeb92b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76834991614563448568018190335308623597389286522815502199416664689756378511790 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.76834991614563448568018190335308623597389286522815502199416664689756378511790
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.41156528929577784968776751229354818491162293882684140658825282362834555361573
Short name T339
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.94 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:21 PM PST 23
Peak memory 183060 kb
Host smart-81272c1b-3a72-4a4c-9e0e-5b7f4ee9f349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156528929577784968776751229354818491162293882684140658825282362834555361573 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.41156528929577784968776751229354818491162293882684140658825282362834555361573
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.26211281910559707193583145962776690944473962736259192475229620676093212454079
Short name T254
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.4 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:26 PM PST 23
Peak memory 182952 kb
Host smart-2f5a8cd5-499f-43e8-9fc1-6ae2488d182d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211281910559707193583145962776690944473962736259192475229620676093212454079 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.26211281910559707193583145962776690944473962736259192475229620676093212454079
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.97517453707154537809969318861588614720486194052573487773460284493623889135586
Short name T500
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.11 seconds
Started Nov 22 01:06:07 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183072 kb
Host smart-3e6d0323-6bfb-4ede-a719-97d5b2e7b1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97517453707154537809969318861588614720486194052573487773460284493623889135586 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.97517453707154537809969318861588614720486194052573487773460284493623889135586
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.76122859224984460854660998363906143171684440122050610326616630031288730450818
Short name T476
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.32 seconds
Started Nov 22 01:06:05 PM PST 23
Finished Nov 22 01:07:19 PM PST 23
Peak memory 182960 kb
Host smart-0a201bed-4859-46fd-b781-f727cbfeb198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76122859224984460854660998363906143171684440122050610326616630031288730450818 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.76122859224984460854660998363906143171684440122050610326616630031288730450818
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.61324959380009189637304383533334767674327362807124494873855488796557420388138
Short name T243
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.48 seconds
Started Nov 22 01:06:09 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183048 kb
Host smart-b40b294f-a6e5-41a5-9b1a-e3123d92094d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61324959380009189637304383533334767674327362807124494873855488796557420388138 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.61324959380009189637304383533334767674327362807124494873855488796557420388138
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.27496232851401522847529238999036856269793347703952330333288724481441224678706
Short name T294
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.43 seconds
Started Nov 22 01:06:07 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 183008 kb
Host smart-eee3cf8e-66cc-4e54-a802-d5526bc4a272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27496232851401522847529238999036856269793347703952330333288724481441224678706 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.27496232851401522847529238999036856269793347703952330333288724481441224678706
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.63823415036974132636463589769445124122903064428475125348831386204167810404486
Short name T539
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.62 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:24 PM PST 23
Peak memory 183088 kb
Host smart-3194f869-d13d-44bf-b439-8813f6557f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63823415036974132636463589769445124122903064428475125348831386204167810404486 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.63823415036974132636463589769445124122903064428475125348831386204167810404486
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.12737977741546464174051786056365889274416187617568626164634110955977891392243
Short name T547
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.01 seconds
Started Nov 22 01:06:06 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 183060 kb
Host smart-9eaa4787-4642-4db8-bfdb-a3917eb87170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737977741546464174051786056365889274416187617568626164634110955977891392243 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.12737977741546464174051786056365889274416187617568626164634110955977891392243
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.101379019293008606076311607305349023445654919278871746367812132750727512236532
Short name T385
Test name
Test status
Simulation time 544575976458 ps
CPU time 608.83 seconds
Started Nov 22 01:04:47 PM PST 23
Finished Nov 22 01:14:58 PM PST 23
Peak memory 183052 kb
Host smart-bd9f7b27-152a-4312-9962-597cc3da2562
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013790192930086060763116073053490234456549192788717463678121327507275122365
32 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.101379019293008606076311607305349023445654919278
871746367812132750727512236532
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.52082163939835642885290158776234099918241293798341056422246418529186948282728
Short name T442
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.16 seconds
Started Nov 22 01:04:49 PM PST 23
Finished Nov 22 01:05:20 PM PST 23
Peak memory 183012 kb
Host smart-c1a9116d-f43a-4af9-b53b-66215ac8d6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52082163939835642885290158776234099918241293798341056422246418529186948282728 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.rv_timer_disabled.52082163939835642885290158776234099918241293798341056422246418529186948282728
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.108336229779683410890753568993380382458831661428136979701987383144563867989430
Short name T308
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.37 seconds
Started Nov 22 01:04:16 PM PST 23
Finished Nov 22 01:05:31 PM PST 23
Peak memory 183028 kb
Host smart-c5eb04fe-19d9-401e-9cb8-cd0cc78ba71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108336229779683410890753568993380382458831661428136979701987383144563867989430 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.108336229779683410890753568993380382458831661428136979701987383144563867989430
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.43989960950361187266636195347864513840100541033890829421719889400848367342584
Short name T566
Test name
Test status
Simulation time 60703901037 ps
CPU time 294.8 seconds
Started Nov 22 01:04:43 PM PST 23
Finished Nov 22 01:09:39 PM PST 23
Peak memory 191288 kb
Host smart-37d9c632-d3d9-4ff2-ac62-f394ab5eb90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43989960950361187266636195347864513840100541033890829421719889400848367342584 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.rv_timer_random_reset.43989960950361187266636195347864513840100541033890829421719889400848367342584
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.77475856139677758927652421104890813275737258224604372993698690203319965637967
Short name T554
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1599.05 seconds
Started Nov 22 01:04:42 PM PST 23
Finished Nov 22 01:31:22 PM PST 23
Peak memory 191276 kb
Host smart-d54fdbfb-b97e-492d-b0ac-f440acda251c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77475856139677758927652421104890813275737258224604372993698690203319965637967 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.77475856139677758927652421104890813275737258224604372993698690203319965637967
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3781521362335356165647188718730948350249192115082419981623310589608585995789
Short name T439
Test name
Test status
Simulation time 207522994332 ps
CPU time 836.7 seconds
Started Nov 22 01:04:55 PM PST 23
Finished Nov 22 01:18:55 PM PST 23
Peak memory 199100 kb
Host smart-40741fac-17b2-4141-af6f-48bf8aaef1d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781521362335356165647
188718730948350249192115082419981623310589608585995789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_rese
t.3781521362335356165647188718730948350249192115082419981623310589608585995789
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.50245478749138774165946086560821953420679485437556123630445407505636982563185
Short name T236
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.08 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:24 PM PST 23
Peak memory 182952 kb
Host smart-5424bddf-42ed-4d49-89ed-5578f575cada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50245478749138774165946086560821953420679485437556123630445407505636982563185 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.50245478749138774165946086560821953420679485437556123630445407505636982563185
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.77391158401453090085595495378736889022256870516097511302762716835140554888833
Short name T288
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.21 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 182976 kb
Host smart-6d2286bc-6020-4351-a077-e86ae8121794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77391158401453090085595495378736889022256870516097511302762716835140554888833 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.77391158401453090085595495378736889022256870516097511302762716835140554888833
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.102895805076121814626428965843514999157079782248253144803344432542119755220064
Short name T241
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.81 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183056 kb
Host smart-630cd0f6-8074-4786-99a6-dcf1bbbf56ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102895805076121814626428965843514999157079782248253144803344432542119755220064 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.102895805076121814626428965843514999157079782248253144803344432542119755220064
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.78652035425073399239384497006270212817958366609503777303919467200170838817212
Short name T75
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.31 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183088 kb
Host smart-51a47d37-97af-4cf0-a0f0-da5b1f528a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78652035425073399239384497006270212817958366609503777303919467200170838817212 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.78652035425073399239384497006270212817958366609503777303919467200170838817212
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2154810759256403438045551707992444254561675442002002959431611204785187314435
Short name T461
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.32 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183084 kb
Host smart-90f2459c-4e91-4f0b-ba12-55b1d3e57965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154810759256403438045551707992444254561675442002002959431611204785187314435 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2154810759256403438045551707992444254561675442002002959431611204785187314435
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.94153950790693192748010599322851769016224960616201677280397971332853768292575
Short name T71
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.01 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183048 kb
Host smart-54c15924-95f9-47d0-b86c-2d0af572d350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94153950790693192748010599322851769016224960616201677280397971332853768292575 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.94153950790693192748010599322851769016224960616201677280397971332853768292575
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.30583094867158236436609696647911793455261428150675887310082470075213572296431
Short name T467
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.76 seconds
Started Nov 22 01:06:06 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 183044 kb
Host smart-33fde95b-95a9-418f-89c4-3e7f6738cd39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30583094867158236436609696647911793455261428150675887310082470075213572296431 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.30583094867158236436609696647911793455261428150675887310082470075213572296431
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.57768130358620224608116785678245709094017621518189259781424104760071815711966
Short name T490
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.8 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183080 kb
Host smart-dd643d11-0a92-4a8c-b15d-04d7bf92635d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57768130358620224608116785678245709094017621518189259781424104760071815711966 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.57768130358620224608116785678245709094017621518189259781424104760071815711966
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.6617492722431118591318571637827665212783091584392291819132897091689164653039
Short name T519
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.36 seconds
Started Nov 22 01:06:06 PM PST 23
Finished Nov 22 01:07:20 PM PST 23
Peak memory 183064 kb
Host smart-35609e4d-2c05-422e-85a7-a7e234f16147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6617492722431118591318571637827665212783091584392291819132897091689164653039 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.6617492722431118591318571637827665212783091584392291819132897091689164653039
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.10745816900174043547480378174056295582887468668230288973899452189369931845245
Short name T323
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.15 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183060 kb
Host smart-936ffdbb-7cef-483d-9206-5ad963c4c574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10745816900174043547480378174056295582887468668230288973899452189369931845245 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.10745816900174043547480378174056295582887468668230288973899452189369931845245
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.74516744643250739958273624685374524522269691328016971871106001164813166745742
Short name T532
Test name
Test status
Simulation time 544575976458 ps
CPU time 603.5 seconds
Started Nov 22 01:04:52 PM PST 23
Finished Nov 22 01:14:57 PM PST 23
Peak memory 183020 kb
Host smart-31e602f9-54e9-4d45-997c-7421c08d4cd6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7451674464325073995827362468537452452226969132801697187110600116481316674574
2 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.7451674464325073995827362468537452452226969132801
6971871106001164813166745742
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.81818949803355285600953604785154997455325752958257853635180786829457630909741
Short name T337
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.48 seconds
Started Nov 22 01:04:50 PM PST 23
Finished Nov 22 01:05:21 PM PST 23
Peak memory 182976 kb
Host smart-7e8966ad-f49c-44f0-aee3-c0b453368bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81818949803355285600953604785154997455325752958257853635180786829457630909741 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.rv_timer_disabled.81818949803355285600953604785154997455325752958257853635180786829457630909741
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.19775360864754938358563627271029598019504395154832103832946445872158148456061
Short name T534
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.68 seconds
Started Nov 22 01:04:56 PM PST 23
Finished Nov 22 01:06:14 PM PST 23
Peak memory 182908 kb
Host smart-c19d6b9a-9e70-49be-9abd-14564f20b0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775360864754938358563627271029598019504395154832103832946445872158148456061 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.19775360864754938358563627271029598019504395154832103832946445872158148456061
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.441878550856398910024321979156231217948421196530682612599543286146023580775
Short name T413
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.56 seconds
Started Nov 22 01:04:47 PM PST 23
Finished Nov 22 01:09:44 PM PST 23
Peak memory 191272 kb
Host smart-1fe5e789-7537-4ecf-8907-6bd2196056b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441878550856398910024321979156231217948421196530682612599543286146023580775 -assert nopostproc +UVM_TESTNAME=rv_timer_ba
se_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.rv_timer_random_reset.441878550856398910024321979156231217948421196530682612599543286146023580775
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.69172716865309687100712106184038688736844712534681162139647637632750693579329
Short name T611
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1605.56 seconds
Started Nov 22 01:04:47 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 191236 kb
Host smart-510fd209-ae04-49dc-95f2-9171aa97a97f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69172716865309687100712106184038688736844712534681162139647637632750693579329 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.69172716865309687100712106184038688736844712534681162139647637632750693579329
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.111363856555058419317971313263644999165693171791767377264710574560315445333561
Short name T249
Test name
Test status
Simulation time 207522994332 ps
CPU time 817.71 seconds
Started Nov 22 01:04:42 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 199120 kb
Host smart-43b60006-54c0-4ad0-b090-aa92aeb85965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113638565550584193179
71313263644999165693171791767377264710574560315445333561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_re
set.111363856555058419317971313263644999165693171791767377264710574560315445333561
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.101014518329150434252449551067869175149848020914138198676914554694317882905066
Short name T557
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.95 seconds
Started Nov 22 01:06:04 PM PST 23
Finished Nov 22 01:07:18 PM PST 23
Peak memory 182948 kb
Host smart-30c68b91-44d5-4aeb-a03e-cbb17937d2b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101014518329150434252449551067869175149848020914138198676914554694317882905066 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.101014518329150434252449551067869175149848020914138198676914554694317882905066
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.48691961246067755944458280993877586651371432386067323409054367797123456060069
Short name T552
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.33 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183052 kb
Host smart-bfbe42ed-089d-482c-9c02-54c9a4367a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48691961246067755944458280993877586651371432386067323409054367797123456060069 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.48691961246067755944458280993877586651371432386067323409054367797123456060069
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.78217694793522799653023507634957284246554358419679529816079836424094229007798
Short name T459
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.49 seconds
Started Nov 22 01:06:08 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183052 kb
Host smart-bdc40fa3-62a8-4909-9119-155e7a64fee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78217694793522799653023507634957284246554358419679529816079836424094229007798 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.78217694793522799653023507634957284246554358419679529816079836424094229007798
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.105560860927193430067742500222734190876349076174793992732201344553075147194582
Short name T478
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.13 seconds
Started Nov 22 01:06:09 PM PST 23
Finished Nov 22 01:07:24 PM PST 23
Peak memory 183100 kb
Host smart-53748899-f14f-414b-ba99-393035f447bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105560860927193430067742500222734190876349076174793992732201344553075147194582 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.105560860927193430067742500222734190876349076174793992732201344553075147194582
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.50363193601476195030645781704559360652968750393011500000160787782113167124768
Short name T260
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.62 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:27 PM PST 23
Peak memory 182988 kb
Host smart-4b0c1f1c-e414-4826-8d30-7f1cdae0519e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50363193601476195030645781704559360652968750393011500000160787782113167124768 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.50363193601476195030645781704559360652968750393011500000160787782113167124768
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.9169509550235776136559686418979408677687541339693205054517067880846913254684
Short name T470
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.87 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:26 PM PST 23
Peak memory 182988 kb
Host smart-4af4cc87-dbcb-4e80-9eed-d340f74c8dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9169509550235776136559686418979408677687541339693205054517067880846913254684 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.9169509550235776136559686418979408677687541339693205054517067880846913254684
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.52700053783987629026078204253678401924753074392292338797039747629047186390831
Short name T451
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.4 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:07:41 PM PST 23
Peak memory 182976 kb
Host smart-15c43b4b-b263-463d-a7cd-f8bfd1df814a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52700053783987629026078204253678401924753074392292338797039747629047186390831 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.52700053783987629026078204253678401924753074392292338797039747629047186390831
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.94953733698974689233269217634965268232316866819542630792747477571268127781730
Short name T68
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.7 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:26 PM PST 23
Peak memory 183036 kb
Host smart-249383ca-88cb-48e0-b598-d3cd4d8b2148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94953733698974689233269217634965268232316866819542630792747477571268127781730 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.94953733698974689233269217634965268232316866819542630792747477571268127781730
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.78431451086966491962569366219110949397551029636432012388115206961884008412102
Short name T250
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.6 seconds
Started Nov 22 01:06:21 PM PST 23
Finished Nov 22 01:07:35 PM PST 23
Peak memory 183060 kb
Host smart-81486821-ec86-46ea-8aba-656a21cf68d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78431451086966491962569366219110949397551029636432012388115206961884008412102 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.78431451086966491962569366219110949397551029636432012388115206961884008412102
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.114148291986325346194924696469403747265707012156632623249482455339846311316742
Short name T481
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.4 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:23 PM PST 23
Peak memory 183052 kb
Host smart-2d1f41a0-2db3-49c2-8ea2-b0d3a742d73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114148291986325346194924696469403747265707012156632623249482455339846311316742 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.114148291986325346194924696469403747265707012156632623249482455339846311316742
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.28232006366415879774280303223080512613115421986228173650206467922356931441355
Short name T453
Test name
Test status
Simulation time 544575976458 ps
CPU time 615.12 seconds
Started Nov 22 01:04:50 PM PST 23
Finished Nov 22 01:15:06 PM PST 23
Peak memory 182936 kb
Host smart-df2d2a63-d0b7-4982-bad6-8359c34f79dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823200636641587977428030322308051261311542198622817365020646792235693144135
5 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.2823200636641587977428030322308051261311542198622
8173650206467922356931441355
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.62057085416662232746588561797258378154848184340061518715710969936039537965160
Short name T253
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.59 seconds
Started Nov 22 01:04:47 PM PST 23
Finished Nov 22 01:05:19 PM PST 23
Peak memory 183044 kb
Host smart-443eb6fa-5c3e-4a26-b4f6-173a0bbab867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62057085416662232746588561797258378154848184340061518715710969936039537965160 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.rv_timer_disabled.62057085416662232746588561797258378154848184340061518715710969936039537965160
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.13635388903197897255128943343744499773530471362534199100451760630745591141591
Short name T9
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.09 seconds
Started Nov 22 01:04:49 PM PST 23
Finished Nov 22 01:06:04 PM PST 23
Peak memory 183056 kb
Host smart-aa801d6b-04a5-48b6-b824-8395b07d8378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13635388903197897255128943343744499773530471362534199100451760630745591141591 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.13635388903197897255128943343744499773530471362534199100451760630745591141591
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2051539192058342058605593487468524515141146761353592684634989415294725798308
Short name T272
Test name
Test status
Simulation time 60703901037 ps
CPU time 291.95 seconds
Started Nov 22 01:04:50 PM PST 23
Finished Nov 22 01:09:43 PM PST 23
Peak memory 191252 kb
Host smart-c5f240e7-46e3-4b20-b56e-8683fd3d4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051539192058342058605593487468524515141146761353592684634989415294725798308 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.rv_timer_random_reset.2051539192058342058605593487468524515141146761353592684634989415294725798308
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.78868300704406402181842877849823294906053120084069523975745180821800021950168
Short name T441
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1617.69 seconds
Started Nov 22 01:04:46 PM PST 23
Finished Nov 22 01:31:46 PM PST 23
Peak memory 191224 kb
Host smart-65ca0dff-ca15-418a-be47-04a78435b085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78868300704406402181842877849823294906053120084069523975745180821800021950168 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.78868300704406402181842877849823294906053120084069523975745180821800021950168
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.25591231598208034249904712065783597143379635885773729441227002595033981436664
Short name T302
Test name
Test status
Simulation time 207522994332 ps
CPU time 815.07 seconds
Started Nov 22 01:04:51 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 199112 kb
Host smart-19336b90-bc30-4756-a1a1-bb336d8b7d2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559123159820803424990
4712065783597143379635885773729441227002595033981436664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_res
et.25591231598208034249904712065783597143379635885773729441227002595033981436664
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.106779776151270784143133661684996829081419930690358249614955121863148180021717
Short name T568
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.78 seconds
Started Nov 22 01:06:24 PM PST 23
Finished Nov 22 01:07:38 PM PST 23
Peak memory 182968 kb
Host smart-d0e8f4b9-f8e5-489b-926f-76fab756ebc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106779776151270784143133661684996829081419930690358249614955121863148180021717 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.106779776151270784143133661684996829081419930690358249614955121863148180021717
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.29171636211400931523771728455677751102021050720849895274005298853626320519075
Short name T279
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.37 seconds
Started Nov 22 01:06:18 PM PST 23
Finished Nov 22 01:07:34 PM PST 23
Peak memory 183036 kb
Host smart-773fc823-a717-491d-a406-c443fe97329d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29171636211400931523771728455677751102021050720849895274005298853626320519075 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.29171636211400931523771728455677751102021050720849895274005298853626320519075
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.33521288788442413477799471338979612888883677041755334249805439600179082488449
Short name T278
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.49 seconds
Started Nov 22 01:06:15 PM PST 23
Finished Nov 22 01:07:29 PM PST 23
Peak memory 183008 kb
Host smart-91787992-1f1c-4f3b-8805-212cb182a099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521288788442413477799471338979612888883677041755334249805439600179082488449 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.33521288788442413477799471338979612888883677041755334249805439600179082488449
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.88191252454348288392951843822241841234800031099988622951282975457099884147740
Short name T286
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.33 seconds
Started Nov 22 01:06:23 PM PST 23
Finished Nov 22 01:07:36 PM PST 23
Peak memory 182972 kb
Host smart-370bdbce-9d6d-499a-80bb-97277bc17efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88191252454348288392951843822241841234800031099988622951282975457099884147740 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.88191252454348288392951843822241841234800031099988622951282975457099884147740
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.74849923745490199020171414561820990100052804036670838147749879357289778252476
Short name T82
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.03 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:28 PM PST 23
Peak memory 183028 kb
Host smart-074df71b-9481-48ee-b707-f488ef5842b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74849923745490199020171414561820990100052804036670838147749879357289778252476 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.74849923745490199020171414561820990100052804036670838147749879357289778252476
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.109641254075376956006371362926905595462509613872061971806738093712076271389038
Short name T395
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.98 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:31 PM PST 23
Peak memory 182964 kb
Host smart-beea5e58-180c-47d6-80e5-85db87179112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109641254075376956006371362926905595462509613872061971806738093712076271389038 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.109641254075376956006371362926905595462509613872061971806738093712076271389038
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.52451704400710066149094063643341511127294789828123237495538961911638585636568
Short name T549
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.09 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:31 PM PST 23
Peak memory 183080 kb
Host smart-b1f8c31b-f79f-4c34-95d0-a7509807761e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52451704400710066149094063643341511127294789828123237495538961911638585636568 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.52451704400710066149094063643341511127294789828123237495538961911638585636568
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.28053496132427858431036006302470019287911115206495701952460637689281131872513
Short name T438
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.42 seconds
Started Nov 22 01:06:21 PM PST 23
Finished Nov 22 01:07:35 PM PST 23
Peak memory 183080 kb
Host smart-d1ca8c48-a72d-4cc6-b440-fe5f7131b992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053496132427858431036006302470019287911115206495701952460637689281131872513 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.28053496132427858431036006302470019287911115206495701952460637689281131872513
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.74913459660731092314736996890900936391719405965814872857394883757662265437030
Short name T474
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.69 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:30 PM PST 23
Peak memory 182616 kb
Host smart-bd3d3ace-fee1-4f1a-92fa-cc6c5e913ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74913459660731092314736996890900936391719405965814872857394883757662265437030 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.74913459660731092314736996890900936391719405965814872857394883757662265437030
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.80822076577351299311693742902871162152227702123922799188260220042777251436020
Short name T344
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.81 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:30 PM PST 23
Peak memory 183040 kb
Host smart-5b3db124-7287-48a3-8ac9-f45ded608bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80822076577351299311693742902871162152227702123922799188260220042777251436020 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.80822076577351299311693742902871162152227702123922799188260220042777251436020
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.71552984890735679185676786077561964097148679937285686113368656286298977383713
Short name T65
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.41 seconds
Started Nov 22 01:04:44 PM PST 23
Finished Nov 22 01:14:56 PM PST 23
Peak memory 183028 kb
Host smart-4ab31af1-e1a4-4127-958d-e783ec521209
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7155298489073567918567678607756196409714867993728568611336865628629897738371
3 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.7155298489073567918567678607756196409714867993728
5686113368656286298977383713
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.69162910066980685666669271359690250613873605110162141262019156525137041331841
Short name T322
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.5 seconds
Started Nov 22 01:04:51 PM PST 23
Finished Nov 22 01:05:22 PM PST 23
Peak memory 183076 kb
Host smart-6f56a8d4-d22d-4299-9c38-0c89c64834f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69162910066980685666669271359690250613873605110162141262019156525137041331841 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.rv_timer_disabled.69162910066980685666669271359690250613873605110162141262019156525137041331841
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.73089983741630369969733613810949755064531866870335730178705672379184592808109
Short name T394
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.01 seconds
Started Nov 22 01:04:42 PM PST 23
Finished Nov 22 01:05:57 PM PST 23
Peak memory 183084 kb
Host smart-d9dd2145-886b-4a73-a823-0c5a04e9ea34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73089983741630369969733613810949755064531866870335730178705672379184592808109 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.73089983741630369969733613810949755064531866870335730178705672379184592808109
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.91678203113377815133451307689398043319134355126241708148678354556148117191431
Short name T617
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1610.09 seconds
Started Nov 22 01:04:56 PM PST 23
Finished Nov 22 01:31:50 PM PST 23
Peak memory 191120 kb
Host smart-49e384f0-aa88-4fbd-a1c8-3ce5e84405ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91678203113377815133451307689398043319134355126241708148678354556148117191431 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.91678203113377815133451307689398043319134355126241708148678354556148117191431
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.67221900130657335541450453770569773890445344971602235267034853551366878070082
Short name T492
Test name
Test status
Simulation time 207522994332 ps
CPU time 812.8 seconds
Started Nov 22 01:04:45 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 199092 kb
Host smart-041600e3-b2bf-42b0-bc22-72d158e9dcbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6722190013065733554145
0453770569773890445344971602235267034853551366878070082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_res
et.67221900130657335541450453770569773890445344971602235267034853551366878070082
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.42114687826880482533724033595221855591253269858769541811327769435612257432689
Short name T261
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.08 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:25 PM PST 23
Peak memory 183040 kb
Host smart-e3fe09b3-630a-4327-8ec9-30b70d9b0e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42114687826880482533724033595221855591253269858769541811327769435612257432689 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.42114687826880482533724033595221855591253269858769541811327769435612257432689
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2832407757689653660259809151547537737805947816409361383968806132218626803577
Short name T498
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.75 seconds
Started Nov 22 01:06:18 PM PST 23
Finished Nov 22 01:07:31 PM PST 23
Peak memory 183084 kb
Host smart-95674ba4-8efc-4c62-9f01-f38cd487153f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832407757689653660259809151547537737805947816409361383968806132218626803577 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2832407757689653660259809151547537737805947816409361383968806132218626803577
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.71991524111962690604720501548514529990299038716998978144483886562348723537320
Short name T480
Test name
Test status
Simulation time 70917337186 ps
CPU time 71.9 seconds
Started Nov 22 01:06:10 PM PST 23
Finished Nov 22 01:07:22 PM PST 23
Peak memory 183044 kb
Host smart-a815a286-7669-42ec-9c9c-b9041c5d7076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71991524111962690604720501548514529990299038716998978144483886562348723537320 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.71991524111962690604720501548514529990299038716998978144483886562348723537320
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.5502089681705562811826248544493254472723457235585737651707872024679645034474
Short name T28
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.33 seconds
Started Nov 22 01:06:11 PM PST 23
Finished Nov 22 01:07:24 PM PST 23
Peak memory 183040 kb
Host smart-65215299-0c25-4103-a7f1-2ac2db6dd3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5502089681705562811826248544493254472723457235585737651707872024679645034474 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.5502089681705562811826248544493254472723457235585737651707872024679645034474
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.32199874595412411445690233323408566301794845646882914313313301856863044619930
Short name T423
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.78 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:30 PM PST 23
Peak memory 183060 kb
Host smart-efd97657-69ad-4a2f-b882-563e5d023f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199874595412411445690233323408566301794845646882914313313301856863044619930 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.32199874595412411445690233323408566301794845646882914313313301856863044619930
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.59869975049824842653638697254524976375777908695868161442415815691796124264300
Short name T472
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.95 seconds
Started Nov 22 01:06:19 PM PST 23
Finished Nov 22 01:07:33 PM PST 23
Peak memory 183088 kb
Host smart-253f4fbd-1ed2-4a6f-84bf-ee123898d641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59869975049824842653638697254524976375777908695868161442415815691796124264300 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.59869975049824842653638697254524976375777908695868161442415815691796124264300
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.27915392828588860040663031204834865271286032223418570658913206344952924080350
Short name T36
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.43 seconds
Started Nov 22 01:06:20 PM PST 23
Finished Nov 22 01:07:35 PM PST 23
Peak memory 183088 kb
Host smart-cbcbbdf3-a693-4a50-a077-f6b69f0f2ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915392828588860040663031204834865271286032223418570658913206344952924080350 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.27915392828588860040663031204834865271286032223418570658913206344952924080350
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.57624150615402722768532338141641480751526784854120186871635843228950298239353
Short name T2
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.44 seconds
Started Nov 22 01:06:23 PM PST 23
Finished Nov 22 01:07:37 PM PST 23
Peak memory 182972 kb
Host smart-a433ab36-1688-488a-968e-5d9a3afed95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57624150615402722768532338141641480751526784854120186871635843228950298239353 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.57624150615402722768532338141641480751526784854120186871635843228950298239353
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.38731630907237715413803098239632250410356856333706280214711362985864092735262
Short name T429
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.64 seconds
Started Nov 22 01:06:19 PM PST 23
Finished Nov 22 01:07:34 PM PST 23
Peak memory 183088 kb
Host smart-039abf73-95ba-4138-a1b9-33b24c877fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38731630907237715413803098239632250410356856333706280214711362985864092735262 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.38731630907237715413803098239632250410356856333706280214711362985864092735262
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.59734738463915508805468513730470117299349487620882359046117877638545820390528
Short name T78
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.59 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:31 PM PST 23
Peak memory 182956 kb
Host smart-1ca4043d-72d8-4fca-b268-8252263760a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59734738463915508805468513730470117299349487620882359046117877638545820390528 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.59734738463915508805468513730470117299349487620882359046117877638545820390528
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.15472817191693922761338103555915805345121601857608587355405403940248279029069
Short name T577
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.23 seconds
Started Nov 22 01:04:50 PM PST 23
Finished Nov 22 01:15:01 PM PST 23
Peak memory 183056 kb
Host smart-c3044b60-e11a-435e-9a4b-7a8b471ab018
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547281719169392276133810355591580534512160185760858735540540394024827902906
9 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1547281719169392276133810355591580534512160185760
8587355405403940248279029069
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.83606643592765293891230872964205336001042564190174398943887425998810584309978
Short name T401
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.42 seconds
Started Nov 22 01:04:44 PM PST 23
Finished Nov 22 01:05:16 PM PST 23
Peak memory 183056 kb
Host smart-844c288c-c67a-495c-b055-7567d8fbccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83606643592765293891230872964205336001042564190174398943887425998810584309978 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.rv_timer_disabled.83606643592765293891230872964205336001042564190174398943887425998810584309978
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.98160861659178921551157342186153619619528939929896292703752273966639277831964
Short name T386
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.41 seconds
Started Nov 22 01:04:47 PM PST 23
Finished Nov 22 01:06:02 PM PST 23
Peak memory 183044 kb
Host smart-70d61469-e5f7-4e35-82a9-367c5267e21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98160861659178921551157342186153619619528939929896292703752273966639277831964 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.98160861659178921551157342186153619619528939929896292703752273966639277831964
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.17144843493698544774286538745089104357654362549996237891896678372224592232158
Short name T298
Test name
Test status
Simulation time 60703901037 ps
CPU time 294.87 seconds
Started Nov 22 01:04:58 PM PST 23
Finished Nov 22 01:09:56 PM PST 23
Peak memory 191176 kb
Host smart-f8e3456b-2507-44f0-be26-7ff1e77ecd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17144843493698544774286538745089104357654362549996237891896678372224592232158 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.rv_timer_random_reset.17144843493698544774286538745089104357654362549996237891896678372224592232158
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.50834435881131521935731021925078584900885713557806456264726042230593535394891
Short name T276
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1629.41 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:32:16 PM PST 23
Peak memory 191276 kb
Host smart-97db7930-9818-4649-a5da-7ee574d0cad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50834435881131521935731021925078584900885713557806456264726042230593535394891 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.50834435881131521935731021925078584900885713557806456264726042230593535394891
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.18211520054660328890175790987942960986654420772023706677215206835895925992198
Short name T362
Test name
Test status
Simulation time 207522994332 ps
CPU time 824.62 seconds
Started Nov 22 01:05:00 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 199040 kb
Host smart-ba177bbd-f09a-4f28-b3ff-6f66fd38902c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821152005466032889017
5790987942960986654420772023706677215206835895925992198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_res
et.18211520054660328890175790987942960986654420772023706677215206835895925992198
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.53132288097531742060529803347945176861133954198021384897761539011488545996646
Short name T270
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.58 seconds
Started Nov 22 01:06:13 PM PST 23
Finished Nov 22 01:07:27 PM PST 23
Peak memory 183036 kb
Host smart-11d50eb7-1a4e-4d38-ac6b-ae675b0ba9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53132288097531742060529803347945176861133954198021384897761539011488545996646 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.53132288097531742060529803347945176861133954198021384897761539011488545996646
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.101016105074338291311848469984665007018896245980276946413456504742224742556413
Short name T347
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.58 seconds
Started Nov 22 01:06:14 PM PST 23
Finished Nov 22 01:07:27 PM PST 23
Peak memory 183044 kb
Host smart-e1ab3587-69ba-49c2-8633-d43b0fa19820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101016105074338291311848469984665007018896245980276946413456504742224742556413 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.101016105074338291311848469984665007018896245980276946413456504742224742556413
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.66614652535002319266983213190663469825823092640334724589688772458414222390984
Short name T77
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.1 seconds
Started Nov 22 01:06:19 PM PST 23
Finished Nov 22 01:07:32 PM PST 23
Peak memory 183080 kb
Host smart-53a44ba7-f075-4e5e-b7b5-208c2ee17a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66614652535002319266983213190663469825823092640334724589688772458414222390984 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.66614652535002319266983213190663469825823092640334724589688772458414222390984
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.58818689914102989196777188313368665118948708489267497387711943564110133460633
Short name T564
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.14 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:07:41 PM PST 23
Peak memory 182976 kb
Host smart-b0618395-b425-4aaf-a821-a0b2e450da20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58818689914102989196777188313368665118948708489267497387711943564110133460633 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.58818689914102989196777188313368665118948708489267497387711943564110133460633
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.58063061575832787256075899758236845822822031616688906117567410175459439499787
Short name T375
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.43 seconds
Started Nov 22 01:06:14 PM PST 23
Finished Nov 22 01:07:28 PM PST 23
Peak memory 183036 kb
Host smart-ab589a3c-c8ae-4179-b333-d12981b64f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58063061575832787256075899758236845822822031616688906117567410175459439499787 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.58063061575832787256075899758236845822822031616688906117567410175459439499787
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.108112224762853973737388607213037016398599176658740885088437858813583832712012
Short name T514
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.86 seconds
Started Nov 22 01:06:21 PM PST 23
Finished Nov 22 01:07:35 PM PST 23
Peak memory 183056 kb
Host smart-8d9fcb8f-3cd4-4e7f-ab8e-f0260a0f3cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108112224762853973737388607213037016398599176658740885088437858813583832712012 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.108112224762853973737388607213037016398599176658740885088437858813583832712012
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.98420169282617792978419492139434359749945709705909123340608168578095102220627
Short name T458
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.87 seconds
Started Nov 22 01:06:20 PM PST 23
Finished Nov 22 01:07:33 PM PST 23
Peak memory 183080 kb
Host smart-d72c7ba3-8ef6-4ff1-8cc2-3de595de0660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98420169282617792978419492139434359749945709705909123340608168578095102220627 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.98420169282617792978419492139434359749945709705909123340608168578095102220627
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.83791482348480445282824021107974816861665455223144409773953300224343913467986
Short name T353
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.22 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:27 PM PST 23
Peak memory 183000 kb
Host smart-95b1d92e-5806-4717-bc88-f0d5f8f958f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83791482348480445282824021107974816861665455223144409773953300224343913467986 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.83791482348480445282824021107974816861665455223144409773953300224343913467986
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.91386979883830497847806322724606912827468006698174291810490063612348384963827
Short name T244
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.08 seconds
Started Nov 22 01:06:16 PM PST 23
Finished Nov 22 01:07:31 PM PST 23
Peak memory 182532 kb
Host smart-da10cf15-1fb8-47d0-b1e5-12f2abbaae29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91386979883830497847806322724606912827468006698174291810490063612348384963827 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.91386979883830497847806322724606912827468006698174291810490063612348384963827
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1884206058119560386422719439327533450577945854397355215886681543256633739925
Short name T366
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.01 seconds
Started Nov 22 01:06:28 PM PST 23
Finished Nov 22 01:07:42 PM PST 23
Peak memory 183056 kb
Host smart-7ce1e757-de36-4c39-92b6-66359ec24f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884206058119560386422719439327533450577945854397355215886681543256633739925 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1884206058119560386422719439327533450577945854397355215886681543256633739925
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.102167039929782133249990016275383061523277172136680219790893354432464156105284
Short name T92
Test name
Test status
Simulation time 544575976458 ps
CPU time 606.93 seconds
Started Nov 22 01:04:58 PM PST 23
Finished Nov 22 01:15:08 PM PST 23
Peak memory 183020 kb
Host smart-c846a1a6-1cd9-4dfd-a3dd-0fa407224a4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021670399297821332499900162753830615232771721366802197908933544324641561052
84 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.102167039929782133249990016275383061523277172136
680219790893354432464156105284
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.84458410119080975122671233832090958955816325773660802466455560072862920929189
Short name T525
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.16 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:05:33 PM PST 23
Peak memory 183016 kb
Host smart-e6dbcc29-1380-46a0-8b0d-064f75fbd959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84458410119080975122671233832090958955816325773660802466455560072862920929189 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.rv_timer_disabled.84458410119080975122671233832090958955816325773660802466455560072862920929189
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.53488408234759242971397658430986493211426406468620858552149093316080703413332
Short name T267
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.02 seconds
Started Nov 22 01:04:57 PM PST 23
Finished Nov 22 01:06:13 PM PST 23
Peak memory 182960 kb
Host smart-66b157d2-22df-41ff-8997-357b93b0598a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53488408234759242971397658430986493211426406468620858552149093316080703413332 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.53488408234759242971397658430986493211426406468620858552149093316080703413332
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.22536380756608888748852038298862624178058033794071952461613308870402508208383
Short name T393
Test name
Test status
Simulation time 60703901037 ps
CPU time 296.45 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:10:02 PM PST 23
Peak memory 191284 kb
Host smart-08e2f74e-b6b3-49c4-ba3a-48d5f8b7b050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22536380756608888748852038298862624178058033794071952461613308870402508208383 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rv_timer_random_reset.22536380756608888748852038298862624178058033794071952461613308870402508208383
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.97107882792431185596887472409808786966142967400630849141384136053156528782033
Short name T473
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1614.17 seconds
Started Nov 22 01:05:05 PM PST 23
Finished Nov 22 01:32:01 PM PST 23
Peak memory 191276 kb
Host smart-0a84968d-1329-4d3e-a400-6d428630fd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97107882792431185596887472409808786966142967400630849141384136053156528782033 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.97107882792431185596887472409808786966142967400630849141384136053156528782033
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.69015178326856487852452926360370616757091248744036454213543698875502777401316
Short name T515
Test name
Test status
Simulation time 207522994332 ps
CPU time 803.35 seconds
Started Nov 22 01:05:00 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 199000 kb
Host smart-e52c7f2c-ce58-441f-b1d4-2b1976020aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6901517832685648785245
2926360370616757091248744036454213543698875502777401316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_res
et.69015178326856487852452926360370616757091248744036454213543698875502777401316
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.20176889129983109686283747124310581901762157196041793903960604150709837125147
Short name T505
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.52 seconds
Started Nov 22 01:06:26 PM PST 23
Finished Nov 22 01:07:40 PM PST 23
Peak memory 182976 kb
Host smart-ec52d580-8556-4c9f-b05b-b625f5310d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20176889129983109686283747124310581901762157196041793903960604150709837125147 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.20176889129983109686283747124310581901762157196041793903960604150709837125147
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.84742720112790459254242895584982964576427282089399530931834970348661844660540
Short name T341
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.38 seconds
Started Nov 22 01:06:17 PM PST 23
Finished Nov 22 01:07:30 PM PST 23
Peak memory 183072 kb
Host smart-57e21343-8719-4af2-8148-3e0ecbf7fe18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84742720112790459254242895584982964576427282089399530931834970348661844660540 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.84742720112790459254242895584982964576427282089399530931834970348661844660540
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.95394508229814075259904073568339301227442846829603696954810190508490395927260
Short name T598
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.41 seconds
Started Nov 22 01:06:19 PM PST 23
Finished Nov 22 01:07:35 PM PST 23
Peak memory 183064 kb
Host smart-8d8f0e39-6779-4476-8190-98c4c46ee241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95394508229814075259904073568339301227442846829603696954810190508490395927260 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.95394508229814075259904073568339301227442846829603696954810190508490395927260
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.98374179917869027466405255964219543917037735185634542191537861759211291580466
Short name T354
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.89 seconds
Started Nov 22 01:06:20 PM PST 23
Finished Nov 22 01:07:34 PM PST 23
Peak memory 183080 kb
Host smart-7e1df7aa-310a-4f51-87c4-39e355b7ec24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98374179917869027466405255964219543917037735185634542191537861759211291580466 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.98374179917869027466405255964219543917037735185634542191537861759211291580466
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.40412042125738778694834752602150201260556815345085719923138495896617519308561
Short name T404
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.55 seconds
Started Nov 22 01:06:22 PM PST 23
Finished Nov 22 01:07:37 PM PST 23
Peak memory 183060 kb
Host smart-7fce7cfb-6813-48c4-bf02-5cfd64945a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40412042125738778694834752602150201260556815345085719923138495896617519308561 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.40412042125738778694834752602150201260556815345085719923138495896617519308561
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.78772038314869954980203411390819721482994370498699427420932467768150128143804
Short name T587
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.1 seconds
Started Nov 22 01:06:27 PM PST 23
Finished Nov 22 01:07:42 PM PST 23
Peak memory 182976 kb
Host smart-8135ee3c-02be-4c92-b045-cb8c3080f2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78772038314869954980203411390819721482994370498699427420932467768150128143804 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.78772038314869954980203411390819721482994370498699427420932467768150128143804
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.57655968688075310191477074635777475420824222026366148177412168369579251119894
Short name T3
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.71 seconds
Started Nov 22 01:06:29 PM PST 23
Finished Nov 22 01:07:44 PM PST 23
Peak memory 183060 kb
Host smart-cd7135df-9d15-4a56-b936-c523d8053fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57655968688075310191477074635777475420824222026366148177412168369579251119894 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.57655968688075310191477074635777475420824222026366148177412168369579251119894
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.70472912477863757799644760804047292816925093475610865560636687199884390293668
Short name T356
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.07 seconds
Started Nov 22 01:06:19 PM PST 23
Finished Nov 22 01:07:34 PM PST 23
Peak memory 183064 kb
Host smart-0fc631cb-628f-4b69-86c9-7b8b8230ea31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70472912477863757799644760804047292816925093475610865560636687199884390293668 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.70472912477863757799644760804047292816925093475610865560636687199884390293668
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.78391881714486678467089651783129670138746919286241722461855238902534396086837
Short name T528
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.61 seconds
Started Nov 22 01:06:15 PM PST 23
Finished Nov 22 01:07:29 PM PST 23
Peak memory 183052 kb
Host smart-a579ce10-24ff-413d-9d26-4a6e3e89b0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78391881714486678467089651783129670138746919286241722461855238902534396086837 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.78391881714486678467089651783129670138746919286241722461855238902534396086837
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.61530973446691816897320801621885417028489410529533365296238344875961252239304
Short name T306
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.03 seconds
Started Nov 22 01:06:12 PM PST 23
Finished Nov 22 01:07:27 PM PST 23
Peak memory 183000 kb
Host smart-9f335eea-ffb4-4497-8a27-06c3c4699239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61530973446691816897320801621885417028489410529533365296238344875961252239304 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.61530973446691816897320801621885417028489410529533365296238344875961252239304
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.46806148551658755905482899540027301742165759696044725652459908798301258371333
Short name T293
Test name
Test status
Simulation time 544575976458 ps
CPU time 611 seconds
Started Nov 22 01:05:16 PM PST 23
Finished Nov 22 01:15:28 PM PST 23
Peak memory 183052 kb
Host smart-04d0aebd-f13d-4284-8e29-307464ead1fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4680614855165875590548289954002730174216575969604472565245990879830125837133
3 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.4680614855165875590548289954002730174216575969604
4725652459908798301258371333
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.49352880233366182192833637123001992186759356977701160853698632506205530694607
Short name T570
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.7 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:05:37 PM PST 23
Peak memory 183084 kb
Host smart-e45db122-3f43-4610-9cb2-a75a920775ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49352880233366182192833637123001992186759356977701160853698632506205530694607 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.rv_timer_disabled.49352880233366182192833637123001992186759356977701160853698632506205530694607
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.85296113403374149053157150152931327760418646745891430221561746342461808429139
Short name T291
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.14 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:06:18 PM PST 23
Peak memory 182952 kb
Host smart-f4868832-af73-4a2d-827b-aafad7c87f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85296113403374149053157150152931327760418646745891430221561746342461808429139 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.85296113403374149053157150152931327760418646745891430221561746342461808429139
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.106733760241112106204573593881825734936931122740465914905560961663395609578528
Short name T86
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.5 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:10:01 PM PST 23
Peak memory 191304 kb
Host smart-e1df00f0-efe9-49a1-bcef-1146714b3384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106733760241112106204573593881825734936931122740465914905560961663395609578528 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.rv_timer_random_reset.106733760241112106204573593881825734936931122740465914905560961663395609578528
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.91554304703489604089633494079017762815827413388241083900418706928004068432064
Short name T597
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1590.75 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:31:35 PM PST 23
Peak memory 191236 kb
Host smart-28fa7228-5ee2-4aa1-9092-3b544133865e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91554304703489604089633494079017762815827413388241083900418706928004068432064 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.91554304703489604089633494079017762815827413388241083900418706928004068432064
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.94760036491850175179769881235746065860140598065742453546239700439243647370933
Short name T247
Test name
Test status
Simulation time 207522994332 ps
CPU time 802.65 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:18:26 PM PST 23
Peak memory 199060 kb
Host smart-440d916c-901c-4bf9-b584-914b42b0efb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9476003649185017517976
9881235746065860140598065742453546239700439243647370933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_res
et.94760036491850175179769881235746065860140598065742453546239700439243647370933
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.348270725316686689688203905653399659039488981018284492412163360236412289683
Short name T371
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.28 seconds
Started Nov 22 01:06:21 PM PST 23
Finished Nov 22 01:07:36 PM PST 23
Peak memory 183088 kb
Host smart-00296b1c-b631-47b9-80ab-cee84ab8f1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348270725316686689688203905653399659039488981018284492412163360236412289683 -assert nopostp
roc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.348270725316686689688203905653399659039488981018284492412163360236412289683
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.108777362309049780273516992291111055175990364271809758390484490699931663813281
Short name T593
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.95 seconds
Started Nov 22 01:06:20 PM PST 23
Finished Nov 22 01:07:34 PM PST 23
Peak memory 183076 kb
Host smart-de708a13-60e0-4592-a4df-f31b5040f0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108777362309049780273516992291111055175990364271809758390484490699931663813281 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.108777362309049780273516992291111055175990364271809758390484490699931663813281
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.71470470741488115845743635866594931938408294289341415097411919282070965931180
Short name T292
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.65 seconds
Started Nov 22 01:06:23 PM PST 23
Finished Nov 22 01:07:37 PM PST 23
Peak memory 182972 kb
Host smart-3172dc80-8f5c-4fca-a9cb-7e54b8de294d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71470470741488115845743635866594931938408294289341415097411919282070965931180 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.71470470741488115845743635866594931938408294289341415097411919282070965931180
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.22872954660674497496750261674763830131324990190155816239474665184533642374483
Short name T264
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.97 seconds
Started Nov 22 01:06:18 PM PST 23
Finished Nov 22 01:07:32 PM PST 23
Peak memory 183088 kb
Host smart-f46cb313-17cc-46de-8142-93a20dc1a089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22872954660674497496750261674763830131324990190155816239474665184533642374483 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.22872954660674497496750261674763830131324990190155816239474665184533642374483
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.108635000132896458678408863554275261857227712816195818337766726995127028021328
Short name T72
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.76 seconds
Started Nov 22 01:06:18 PM PST 23
Finished Nov 22 01:07:32 PM PST 23
Peak memory 182948 kb
Host smart-56d8ad98-2e79-49f9-ac1b-dfbb7b2155f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108635000132896458678408863554275261857227712816195818337766726995127028021328 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.108635000132896458678408863554275261857227712816195818337766726995127028021328
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.226390106300479953574594552888265073285599924717544712946922590633167127527
Short name T342
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.71 seconds
Started Nov 22 01:06:23 PM PST 23
Finished Nov 22 01:07:37 PM PST 23
Peak memory 182968 kb
Host smart-23cef585-c5b3-4ede-9af6-8c1f5cac43fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226390106300479953574594552888265073285599924717544712946922590633167127527 -assert nopostp
roc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.226390106300479953574594552888265073285599924717544712946922590633167127527
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.64215199438449227656110078588397679065234371912448993352836260972816381625039
Short name T91
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.39 seconds
Started Nov 22 01:06:29 PM PST 23
Finished Nov 22 01:07:43 PM PST 23
Peak memory 183060 kb
Host smart-5b186264-84d0-41ad-a190-2534a2608878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64215199438449227656110078588397679065234371912448993352836260972816381625039 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.64215199438449227656110078588397679065234371912448993352836260972816381625039
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.108891047423678162196443280192387909840189042360466540946017156420735065540249
Short name T384
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.28 seconds
Started Nov 22 01:06:22 PM PST 23
Finished Nov 22 01:07:37 PM PST 23
Peak memory 183080 kb
Host smart-2e357b51-deaf-4967-b070-ac2240032af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108891047423678162196443280192387909840189042360466540946017156420735065540249 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.108891047423678162196443280192387909840189042360466540946017156420735065540249
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.33747598573224749714071230618236339883319295244380922625805637350034378225007
Short name T351
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.89 seconds
Started Nov 22 01:06:20 PM PST 23
Finished Nov 22 01:07:34 PM PST 23
Peak memory 183060 kb
Host smart-649e355e-9b3c-4def-8e25-4fc71d692628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33747598573224749714071230618236339883319295244380922625805637350034378225007 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.33747598573224749714071230618236339883319295244380922625805637350034378225007
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.56340503943514460530785129059989965065402818260349943311962168564101460949820
Short name T422
Test name
Test status
Simulation time 70917337186 ps
CPU time 71.94 seconds
Started Nov 22 01:06:29 PM PST 23
Finished Nov 22 01:07:42 PM PST 23
Peak memory 183060 kb
Host smart-641a9398-a0c6-4fde-9f43-4d4a41c2ae6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56340503943514460530785129059989965065402818260349943311962168564101460949820 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.56340503943514460530785129059989965065402818260349943311962168564101460949820
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.28747995354622907733260567725935567603185975210073073435932687570116878950363
Short name T343
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.22 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:14:24 PM PST 23
Peak memory 183012 kb
Host smart-a13940fe-7eb8-48e9-8439-02f2fcd2174f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874799535462290773326056772593556760318597521007307343593268757011687895036
3 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.28747995354622907733260567725935567603185975210073
073435932687570116878950363
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2568262003406812240840694949116043371969194403829858404925621109496176495312
Short name T324
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.7 seconds
Started Nov 22 01:04:00 PM PST 23
Finished Nov 22 01:04:38 PM PST 23
Peak memory 183060 kb
Host smart-92155255-4865-4009-a1f6-868f7a00ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568262003406812240840694949116043371969194403829858404925621109496176495312 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.rv_timer_disabled.2568262003406812240840694949116043371969194403829858404925621109496176495312
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.25956822278325454375569672582477671148212871477942157817297399504643532943870
Short name T352
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.35 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:05:14 PM PST 23
Peak memory 183084 kb
Host smart-e62c6ee3-3573-4efe-a0eb-7ba9c695c579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25956822278325454375569672582477671148212871477942157817297399504643532943870 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.25956822278325454375569672582477671148212871477942157817297399504643532943870
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.110118010420773699183105130308721427465502212772321347238881060291652635690403
Short name T503
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.77 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:09:09 PM PST 23
Peak memory 191252 kb
Host smart-d92d4d67-f1f9-4994-b7b1-aab2c837ff2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110118010420773699183105130308721427465502212772321347238881060291652635690403 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rv_timer_random_reset.110118010420773699183105130308721427465502212772321347238881060291652635690403
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.434910611681601195857196589382841741142768905535226603550977068722215273672
Short name T15
Test name
Test status
Simulation time 135135591 ps
CPU time 0.9 seconds
Started Nov 22 01:03:53 PM PST 23
Finished Nov 22 01:03:55 PM PST 23
Peak memory 214344 kb
Host smart-7d1b43fd-f2f4-4a4c-a398-ad6f06ceae72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434910611681601195857196589382841741142768905535226603550977068722215273672 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.434910611681601195857196589382841741142768905535226603550977068722215273672
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.63483835829594408999934594111157206400776270459071247404594787377208809039524
Short name T425
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1602.56 seconds
Started Nov 22 01:04:05 PM PST 23
Finished Nov 22 01:30:55 PM PST 23
Peak memory 191236 kb
Host smart-5070d0bf-172c-4044-b15d-eae96405a0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63483835829594408999934594111157206400776270459071247404594787377208809039524 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.63483835829594408999934594111157206400776270459071247404594787377208809039524
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.97637516864325868024455852022325295841298455190050627073469784010534752426401
Short name T595
Test name
Test status
Simulation time 207522994332 ps
CPU time 812.17 seconds
Started Nov 22 01:04:05 PM PST 23
Finished Nov 22 01:17:44 PM PST 23
Peak memory 199120 kb
Host smart-86105288-8ec3-4ece-b41a-92ada1ce7ff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9763751686432586802445
5852022325295841298455190050627073469784010534752426401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_rese
t.97637516864325868024455852022325295841298455190050627073469784010534752426401
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.12981705237760678607991723728780841197982157916795825497257430937553934339122
Short name T319
Test name
Test status
Simulation time 544575976458 ps
CPU time 601.09 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:15:07 PM PST 23
Peak memory 183056 kb
Host smart-4f1adda5-245f-4fa1-8ec9-623e57cdfeef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298170523776067860799172372878084119798215791679582549725743093755393433912
2 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.1298170523776067860799172372878084119798215791679
5825497257430937553934339122
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.45402805838038410843593325907890643500151326470193844949403546661072860647194
Short name T268
Test name
Test status
Simulation time 32101379859 ps
CPU time 30 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:05:36 PM PST 23
Peak memory 182508 kb
Host smart-69044308-51d3-4372-b17f-e2ac039451b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45402805838038410843593325907890643500151326470193844949403546661072860647194 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.rv_timer_disabled.45402805838038410843593325907890643500151326470193844949403546661072860647194
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.80941514356091250323574026303440826227017721292047697253950714991060905042763
Short name T477
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.49 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:06:18 PM PST 23
Peak memory 183036 kb
Host smart-7060a13c-cd19-46ba-a2f4-fb293d141aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80941514356091250323574026303440826227017721292047697253950714991060905042763 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.80941514356091250323574026303440826227017721292047697253950714991060905042763
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.72771596161135299495769564745902407832552766089877147581988469641045422569966
Short name T388
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.95 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:10:04 PM PST 23
Peak memory 191268 kb
Host smart-dc0d9637-cb15-462a-af80-1364fafbb30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72771596161135299495769564745902407832552766089877147581988469641045422569966 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.rv_timer_random_reset.72771596161135299495769564745902407832552766089877147581988469641045422569966
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.32878329994347553779776151317638294917882129452137904932848704424837053175715
Short name T62
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1609.48 seconds
Started Nov 22 01:05:10 PM PST 23
Finished Nov 22 01:32:00 PM PST 23
Peak memory 191220 kb
Host smart-258737a6-f1c2-46e3-9db6-7c888decf962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878329994347553779776151317638294917882129452137904932848704424837053175715 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.32878329994347553779776151317638294917882129452137904932848704424837053175715
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.104730289196770162431868017901147597343745673181521194550472722364262117077143
Short name T447
Test name
Test status
Simulation time 207522994332 ps
CPU time 808.33 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 198348 kb
Host smart-28a6cb08-e7ec-4791-a3b0-b919ad7f080f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047302891967701624318
68017901147597343745673181521194550472722364262117077143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_re
set.104730289196770162431868017901147597343745673181521194550472722364262117077143
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.13179009764150677696020784180342189980055875682778544119654699582889935719347
Short name T355
Test name
Test status
Simulation time 544575976458 ps
CPU time 617.98 seconds
Started Nov 22 01:05:07 PM PST 23
Finished Nov 22 01:15:26 PM PST 23
Peak memory 183028 kb
Host smart-4686b57b-b517-4b3c-9958-a65927b8b45f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317900976415067769602078418034218998005587568277854411965469958288993571934
7 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1317900976415067769602078418034218998005587568277
8544119654699582889935719347
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.5036551198456958454894531821008613279429104654583903562864905721755812860942
Short name T578
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.79 seconds
Started Nov 22 01:05:07 PM PST 23
Finished Nov 22 01:05:39 PM PST 23
Peak memory 183052 kb
Host smart-d4a48254-f241-46b2-a633-c71af4aede18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5036551198456958454894531821008613279429104654583903562864905721755812860942 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.rv_timer_disabled.5036551198456958454894531821008613279429104654583903562864905721755812860942
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.92192650114835355544984870689069834229823027293085942608303347920580871644425
Short name T489
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.22 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:06:21 PM PST 23
Peak memory 182960 kb
Host smart-cc6b7289-f611-4cec-863d-a905256f58dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92192650114835355544984870689069834229823027293085942608303347920580871644425 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.92192650114835355544984870689069834229823027293085942608303347920580871644425
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.64405218788161452945055131248033033099830558148499081600397445800665212443115
Short name T27
Test name
Test status
Simulation time 60703901037 ps
CPU time 300.97 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:10:09 PM PST 23
Peak memory 191268 kb
Host smart-f84ff8d6-b911-49c6-8d06-2d01d17f7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64405218788161452945055131248033033099830558148499081600397445800665212443115 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.rv_timer_random_reset.64405218788161452945055131248033033099830558148499081600397445800665212443115
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.44126986742829250631305113172449934311145201964468160128293230822544579464518
Short name T59
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1580.79 seconds
Started Nov 22 01:05:19 PM PST 23
Finished Nov 22 01:31:42 PM PST 23
Peak memory 191248 kb
Host smart-50713c50-0a15-4358-8789-a1e16f93a95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44126986742829250631305113172449934311145201964468160128293230822544579464518 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.44126986742829250631305113172449934311145201964468160128293230822544579464518
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.103011688567663725027814869246702341467770497804460224361156376958867349457127
Short name T506
Test name
Test status
Simulation time 544575976458 ps
CPU time 611.8 seconds
Started Nov 22 01:05:14 PM PST 23
Finished Nov 22 01:15:27 PM PST 23
Peak memory 183068 kb
Host smart-9a268f0d-1b25-4ff8-806c-d0188467bb91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030116885676637250278148692467023414677704978044602243611563769588673494571
27 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.103011688567663725027814869246702341467770497804
460224361156376958867349457127
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.59992634050988222472928743686107647124528672273458158036744605514421622088794
Short name T382
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.41 seconds
Started Nov 22 01:05:29 PM PST 23
Finished Nov 22 01:06:01 PM PST 23
Peak memory 183064 kb
Host smart-341ade4b-b192-4bb1-895d-defc0bd09a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59992634050988222472928743686107647124528672273458158036744605514421622088794 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.rv_timer_disabled.59992634050988222472928743686107647124528672273458158036744605514421622088794
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.22792401269616661951248961942286898944016524927063484700318996541325469320462
Short name T299
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.43 seconds
Started Nov 22 01:05:31 PM PST 23
Finished Nov 22 01:06:46 PM PST 23
Peak memory 182960 kb
Host smart-67274321-8bb3-4942-b4ab-8a577af0b843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792401269616661951248961942286898944016524927063484700318996541325469320462 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.22792401269616661951248961942286898944016524927063484700318996541325469320462
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.58308800208214544775882076718687561394198131409446708037959510281796194311051
Short name T521
Test name
Test status
Simulation time 60703901037 ps
CPU time 296.47 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:10:01 PM PST 23
Peak memory 191224 kb
Host smart-a9fbd8cf-1aac-4e1c-8390-a4165dbd8a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58308800208214544775882076718687561394198131409446708037959510281796194311051 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.rv_timer_random_reset.58308800208214544775882076718687561394198131409446708037959510281796194311051
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.67630596883641064395826089786339028346792244014083629496360717269433848375551
Short name T381
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1604.59 seconds
Started Nov 22 01:05:19 PM PST 23
Finished Nov 22 01:32:05 PM PST 23
Peak memory 191224 kb
Host smart-f562e71d-94e9-4a82-bcec-91d600e36057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67630596883641064395826089786339028346792244014083629496360717269433848375551 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.67630596883641064395826089786339028346792244014083629496360717269433848375551
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.40793350934290692937707240711367392417866006809220303217197269367945685632806
Short name T530
Test name
Test status
Simulation time 207522994332 ps
CPU time 812.75 seconds
Started Nov 22 01:05:12 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 199100 kb
Host smart-9c479d6d-2444-4b14-92c3-2e3b2bf6cfe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079335093429069293770
7240711367392417866006809220303217197269367945685632806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_res
et.40793350934290692937707240711367392417866006809220303217197269367945685632806
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.96854248586719901152090641153183413866534366233452909054763107829074587617751
Short name T604
Test name
Test status
Simulation time 544575976458 ps
CPU time 615.09 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:15:20 PM PST 23
Peak memory 182980 kb
Host smart-abab3aec-aed2-4d92-b120-dd9fc016de05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9685424858671990115209064115318341386653436623345290905476310782907458761775
1 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.9685424858671990115209064115318341386653436623345
2909054763107829074587617751
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.17758580381246442016842522947077900137113675522421795609960380485208824379699
Short name T431
Test name
Test status
Simulation time 32101379859 ps
CPU time 29.93 seconds
Started Nov 22 01:05:18 PM PST 23
Finished Nov 22 01:05:48 PM PST 23
Peak memory 183008 kb
Host smart-5d0bb6d9-e455-418f-b785-843629c98ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17758580381246442016842522947077900137113675522421795609960380485208824379699 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.rv_timer_disabled.17758580381246442016842522947077900137113675522421795609960380485208824379699
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.58822868362204184792123333543518997855605347867558915063108310144986530761762
Short name T471
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.79 seconds
Started Nov 22 01:05:30 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 182856 kb
Host smart-28447330-a043-434c-9608-8c331d06724e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58822868362204184792123333543518997855605347867558915063108310144986530761762 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.58822868362204184792123333543518997855605347867558915063108310144986530761762
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.103361717380024425865883757970861433028406984151322307878492826859219388443898
Short name T561
Test name
Test status
Simulation time 60703901037 ps
CPU time 301.23 seconds
Started Nov 22 01:04:53 PM PST 23
Finished Nov 22 01:09:55 PM PST 23
Peak memory 191256 kb
Host smart-990e8ef0-16ce-4237-a5ae-ac57ca133310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103361717380024425865883757970861433028406984151322307878492826859219388443898 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.rv_timer_random_reset.103361717380024425865883757970861433028406984151322307878492826859219388443898
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.13705667970145174927355313053591645782231750201371543130220102682572141766751
Short name T60
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1595.02 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 191212 kb
Host smart-68426008-5a49-4ddf-932b-df4170ec08a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13705667970145174927355313053591645782231750201371543130220102682572141766751 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.13705667970145174927355313053591645782231750201371543130220102682572141766751
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.13867514923822135790133767522820647791998272262787272811259204689931808425194
Short name T373
Test name
Test status
Simulation time 207522994332 ps
CPU time 806.25 seconds
Started Nov 22 01:04:55 PM PST 23
Finished Nov 22 01:18:23 PM PST 23
Peak memory 199100 kb
Host smart-dddce62c-ecad-4503-9657-332520ad0c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386751492382213579013
3767522820647791998272262787272811259204689931808425194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_res
et.13867514923822135790133767522820647791998272262787272811259204689931808425194
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.20224173088284050881018410830979406894852423972252361827260546857841039859044
Short name T560
Test name
Test status
Simulation time 544575976458 ps
CPU time 611.2 seconds
Started Nov 22 01:04:57 PM PST 23
Finished Nov 22 01:15:12 PM PST 23
Peak memory 183016 kb
Host smart-907699ad-5dfe-4c5b-b087-84f6a6cc4cf7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022417308828405088101841083097940689485242397225236182726054685784103985904
4 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2022417308828405088101841083097940689485242397225
2361827260546857841039859044
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.97173303450002860031947333954727979015774420373846395455864297626911537894417
Short name T348
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.07 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:05:38 PM PST 23
Peak memory 183088 kb
Host smart-8e5034d0-c888-4d57-8a99-42155a732fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97173303450002860031947333954727979015774420373846395455864297626911537894417 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.rv_timer_disabled.97173303450002860031947333954727979015774420373846395455864297626911537894417
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.29642736483270527697419766790110048148440626724332442325535372154234855388314
Short name T556
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.49 seconds
Started Nov 22 01:04:48 PM PST 23
Finished Nov 22 01:06:02 PM PST 23
Peak memory 183064 kb
Host smart-9105ccbe-f300-45d1-87a9-305a12ae5f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642736483270527697419766790110048148440626724332442325535372154234855388314 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.29642736483270527697419766790110048148440626724332442325535372154234855388314
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.45812963261798304811913645785344301329662104929336208104734297087390143099682
Short name T374
Test name
Test status
Simulation time 60703901037 ps
CPU time 294.21 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:09:56 PM PST 23
Peak memory 191212 kb
Host smart-8c49e9b2-11a6-4c7f-981f-b034999ca66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45812963261798304811913645785344301329662104929336208104734297087390143099682 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.rv_timer_random_reset.45812963261798304811913645785344301329662104929336208104734297087390143099682
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.47279144027171833370051327695553171753386089275085057930835354370280543911753
Short name T580
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1610.87 seconds
Started Nov 22 01:05:05 PM PST 23
Finished Nov 22 01:31:58 PM PST 23
Peak memory 191268 kb
Host smart-9730b4b6-7a0e-432e-a68d-1815f50b6640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47279144027171833370051327695553171753386089275085057930835354370280543911753 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.47279144027171833370051327695553171753386089275085057930835354370280543911753
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.54649468588748521772840230834034192899206687392257352851120988490295265722745
Short name T397
Test name
Test status
Simulation time 207522994332 ps
CPU time 816.72 seconds
Started Nov 22 01:05:07 PM PST 23
Finished Nov 22 01:18:45 PM PST 23
Peak memory 199080 kb
Host smart-d6080f27-9a46-4649-a4ce-c2cf834ce64d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5464946858874852177284
0230834034192899206687392257352851120988490295265722745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_res
et.54649468588748521772840230834034192899206687392257352851120988490295265722745
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.87642837199995154814397455589708694159796964623943463290985480060896411262724
Short name T446
Test name
Test status
Simulation time 544575976458 ps
CPU time 604.68 seconds
Started Nov 22 01:05:04 PM PST 23
Finished Nov 22 01:15:11 PM PST 23
Peak memory 183048 kb
Host smart-a042610c-87dd-4f75-a3e3-531e3d7d5e76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8764283719999515481439745558970869415979696462394346329098548006089641126272
4 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.8764283719999515481439745558970869415979696462394
3463290985480060896411262724
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.89475870649114510081928144025909080152156867240758856785203645220629903802840
Short name T332
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.81 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:05:35 PM PST 23
Peak memory 183024 kb
Host smart-5ef06b5e-299a-458d-9270-d6a8c423279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89475870649114510081928144025909080152156867240758856785203645220629903802840 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.rv_timer_disabled.89475870649114510081928144025909080152156867240758856785203645220629903802840
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.94911641367267039705417638134828019558758654254454781603359947663457734257240
Short name T6
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.22 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:06:18 PM PST 23
Peak memory 182952 kb
Host smart-5ae3e901-3fec-4ab7-9852-96dc1e655d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94911641367267039705417638134828019558758654254454781603359947663457734257240 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.94911641367267039705417638134828019558758654254454781603359947663457734257240
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.79988412873497937113161722427175736745108495426465681868415832006471144570464
Short name T318
Test name
Test status
Simulation time 60703901037 ps
CPU time 294.35 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:10:00 PM PST 23
Peak memory 191284 kb
Host smart-4fbb9546-fb62-469f-b833-4601550ea0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79988412873497937113161722427175736745108495426465681868415832006471144570464 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.rv_timer_random_reset.79988412873497937113161722427175736745108495426465681868415832006471144570464
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.48928192523806050202634105676942211879770037368121644923967109889338429272830
Short name T61
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1606.45 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:31:50 PM PST 23
Peak memory 191184 kb
Host smart-f8421188-14c8-4f55-b921-d77c2becb9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48928192523806050202634105676942211879770037368121644923967109889338429272830 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.48928192523806050202634105676942211879770037368121644923967109889338429272830
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.42174300011673890679892589493951350150001866453695773827683399419019429103949
Short name T418
Test name
Test status
Simulation time 207522994332 ps
CPU time 844.33 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 199120 kb
Host smart-9bca6b68-37a4-4ab1-9512-7d08e58ad7c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217430001167389067989
2589493951350150001866453695773827683399419019429103949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_res
et.42174300011673890679892589493951350150001866453695773827683399419019429103949
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.34160119797637386861790375401496498024859880547273361204902226210113851504794
Short name T527
Test name
Test status
Simulation time 544575976458 ps
CPU time 606.51 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:15:09 PM PST 23
Peak memory 182916 kb
Host smart-a7a63657-990a-473d-9e20-6f95d3060ccc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416011979763738686179037540149649802485988054727336120490222621011385150479
4 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3416011979763738686179037540149649802485988054727
3361204902226210113851504794
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.61153857260583983200635020670590911112494603227038218681886997106330555031394
Short name T257
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.44 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:05:38 PM PST 23
Peak memory 183088 kb
Host smart-3f2658cf-bc81-4856-94ae-c89ec0b937fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61153857260583983200635020670590911112494603227038218681886997106330555031394 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.rv_timer_disabled.61153857260583983200635020670590911112494603227038218681886997106330555031394
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.61467243991818861390774998566908069546453569325691880720760049530471810689616
Short name T313
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.4 seconds
Started Nov 22 01:05:00 PM PST 23
Finished Nov 22 01:06:16 PM PST 23
Peak memory 182980 kb
Host smart-e2ecda49-ef2d-4696-a046-1c6b358003b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61467243991818861390774998566908069546453569325691880720760049530471810689616 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.61467243991818861390774998566908069546453569325691880720760049530471810689616
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.41853258261255730759742037690980550429241555898504583907022502671015698920506
Short name T584
Test name
Test status
Simulation time 60703901037 ps
CPU time 301.61 seconds
Started Nov 22 01:05:05 PM PST 23
Finished Nov 22 01:10:08 PM PST 23
Peak memory 191288 kb
Host smart-fcc167ec-dd39-436b-8ded-7c3a6d53597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41853258261255730759742037690980550429241555898504583907022502671015698920506 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rv_timer_random_reset.41853258261255730759742037690980550429241555898504583907022502671015698920506
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.86314929345436968836081582978058713440332777420988479130822608246428775228219
Short name T274
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1592.93 seconds
Started Nov 22 01:05:08 PM PST 23
Finished Nov 22 01:31:42 PM PST 23
Peak memory 191256 kb
Host smart-bb00e84e-aaf1-4a42-9ac3-b653c5500dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86314929345436968836081582978058713440332777420988479130822608246428775228219 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.86314929345436968836081582978058713440332777420988479130822608246428775228219
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.40290955154350586543662807515052123817205491295499611444076935066339572868824
Short name T600
Test name
Test status
Simulation time 207522994332 ps
CPU time 828.29 seconds
Started Nov 22 01:04:57 PM PST 23
Finished Nov 22 01:18:49 PM PST 23
Peak memory 199124 kb
Host smart-0bff6ae7-f996-4d06-b26b-bfdf66c46f3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029095515435058654366
2807515052123817205491295499611444076935066339572868824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_res
et.40290955154350586543662807515052123817205491295499611444076935066339572868824
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.88346252552616835838522101354125345062824788314295683679940933091160113794478
Short name T508
Test name
Test status
Simulation time 544575976458 ps
CPU time 603.74 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:15:08 PM PST 23
Peak memory 182984 kb
Host smart-a8b61549-cb6e-4520-8f48-0df5e6084d53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8834625255261683583852210135412534506282478831429568367994093309116011379447
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.8834625255261683583852210135412534506282478831429
5683679940933091160113794478
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.58817926120417243523265060069420328726484751185315407132755190864363538699858
Short name T456
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.38 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:05:33 PM PST 23
Peak memory 183060 kb
Host smart-fd42aaef-cd0d-4593-94dc-3e3120ecba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58817926120417243523265060069420328726484751185315407132755190864363538699858 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.rv_timer_disabled.58817926120417243523265060069420328726484751185315407132755190864363538699858
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.24642852939738502578327066359141782367844048771451997149214064375403196807944
Short name T449
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.32 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:06:16 PM PST 23
Peak memory 183032 kb
Host smart-b51e7563-2803-4075-80c7-961db18c665c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642852939738502578327066359141782367844048771451997149214064375403196807944 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.24642852939738502578327066359141782367844048771451997149214064375403196807944
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.16394500422010969521396463507435321207776858392074376208276834504144959656792
Short name T335
Test name
Test status
Simulation time 60703901037 ps
CPU time 300.3 seconds
Started Nov 22 01:05:00 PM PST 23
Finished Nov 22 01:10:02 PM PST 23
Peak memory 191252 kb
Host smart-c1db9405-dc21-45f0-9b7b-3b5a6b9ce923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16394500422010969521396463507435321207776858392074376208276834504144959656792 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.rv_timer_random_reset.16394500422010969521396463507435321207776858392074376208276834504144959656792
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.100638317088816954590064185968571173988204548185020061602387292784587555222644
Short name T607
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1636.95 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:32:19 PM PST 23
Peak memory 191272 kb
Host smart-c8a3b65d-cb40-44eb-9b23-05a9133dfcc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100638317088816954590064185968571173988204548185020061602387292784587555222644 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.100638317088816954590064185968571173988204548185020061602387292784587555222644
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.43552003165841291298744160957688866640650926732767230265096031119779800415832
Short name T542
Test name
Test status
Simulation time 207522994332 ps
CPU time 809.75 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 199132 kb
Host smart-d13e9017-24f5-498c-89d4-a20af9038687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4355200316584129129874
4160957688866640650926732767230265096031119779800415832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_res
et.43552003165841291298744160957688866640650926732767230265096031119779800415832
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.63987518821606041052171539781177140946531480923070542588908886344695923493195
Short name T258
Test name
Test status
Simulation time 544575976458 ps
CPU time 605.78 seconds
Started Nov 22 01:04:58 PM PST 23
Finished Nov 22 01:15:07 PM PST 23
Peak memory 183016 kb
Host smart-b75e9f7c-4e6e-40e6-9664-15e9534c74e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6398751882160604105217153978117714094653148092307054258890888634469592349319
5 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.6398751882160604105217153978117714094653148092307
0542588908886344695923493195
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.6699577135134273477616921083240804510848871777699648013815120306833065767796
Short name T349
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.34 seconds
Started Nov 22 01:05:06 PM PST 23
Finished Nov 22 01:05:38 PM PST 23
Peak memory 183072 kb
Host smart-31b77d61-12b3-41fe-892b-c22a396dee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6699577135134273477616921083240804510848871777699648013815120306833065767796 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.rv_timer_disabled.6699577135134273477616921083240804510848871777699648013815120306833065767796
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.32165289084919410861502177377509556758759245354563271130720583536157514192359
Short name T513
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.46 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:06:17 PM PST 23
Peak memory 183044 kb
Host smart-9d6bc0ab-cb6a-459e-9a84-a2a86d027603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165289084919410861502177377509556758759245354563271130720583536157514192359 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.32165289084919410861502177377509556758759245354563271130720583536157514192359
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.76379299121609986838770203979377967568717935266365500157041802311375769504911
Short name T245
Test name
Test status
Simulation time 60703901037 ps
CPU time 300.01 seconds
Started Nov 22 01:05:00 PM PST 23
Finished Nov 22 01:10:02 PM PST 23
Peak memory 191196 kb
Host smart-eaf24b39-13a5-4815-9a67-80774a978a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76379299121609986838770203979377967568717935266365500157041802311375769504911 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.rv_timer_random_reset.76379299121609986838770203979377967568717935266365500157041802311375769504911
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.60192694331868875570626720262296817559854230404812717098148401415397650784181
Short name T468
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1608.39 seconds
Started Nov 22 01:05:05 PM PST 23
Finished Nov 22 01:31:56 PM PST 23
Peak memory 191276 kb
Host smart-38a026ff-f922-4e75-93e2-12e16d5aeaef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60192694331868875570626720262296817559854230404812717098148401415397650784181 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.60192694331868875570626720262296817559854230404812717098148401415397650784181
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.27898261708195226730600451201217360078736973656506475041993450557566008447416
Short name T455
Test name
Test status
Simulation time 207522994332 ps
CPU time 828.94 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 199068 kb
Host smart-ecac1a96-703f-445d-be78-9b4b6a6764a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789826170819522673060
0451201217360078736973656506475041993450557566008447416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_res
et.27898261708195226730600451201217360078736973656506475041993450557566008447416
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.55317191471324096349233180370490269089921408746014169586228859559154836651190
Short name T496
Test name
Test status
Simulation time 544575976458 ps
CPU time 604.48 seconds
Started Nov 22 01:05:00 PM PST 23
Finished Nov 22 01:15:07 PM PST 23
Peak memory 182972 kb
Host smart-4fe7c742-6de7-4c9d-a180-af8b6152e841
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5531719147132409634923318037049026908992140874601416958622885955915483665119
0 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.5531719147132409634923318037049026908992140874601
4169586228859559154836651190
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.47050752018967376018089910963158362200622278982227083090873665884991765316449
Short name T569
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.75 seconds
Started Nov 22 01:05:01 PM PST 23
Finished Nov 22 01:05:33 PM PST 23
Peak memory 182956 kb
Host smart-0a1cc9f3-f9ac-42bf-a62c-988494aa6cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47050752018967376018089910963158362200622278982227083090873665884991765316449 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.rv_timer_disabled.47050752018967376018089910963158362200622278982227083090873665884991765316449
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.75424426841873256884477521750842457675077406600509598680110566751082245536379
Short name T239
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.31 seconds
Started Nov 22 01:05:08 PM PST 23
Finished Nov 22 01:06:23 PM PST 23
Peak memory 183064 kb
Host smart-c3e8c95a-0211-467c-8e89-0a100c6f6e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75424426841873256884477521750842457675077406600509598680110566751082245536379 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.75424426841873256884477521750842457675077406600509598680110566751082245536379
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.109798490407149535528117593852928333487962308346057559559584670680024836702836
Short name T520
Test name
Test status
Simulation time 60703901037 ps
CPU time 293.53 seconds
Started Nov 22 01:05:08 PM PST 23
Finished Nov 22 01:10:03 PM PST 23
Peak memory 191268 kb
Host smart-fb50aea1-dfab-4b78-8b9c-6ca19f6ebffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109798490407149535528117593852928333487962308346057559559584670680024836702836 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.rv_timer_random_reset.109798490407149535528117593852928333487962308346057559559584670680024836702836
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.68189409898352602816128981959264108461585509722277849434693754439387812588506
Short name T379
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1583.24 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:31:27 PM PST 23
Peak memory 191252 kb
Host smart-a10378be-a250-446b-9f75-6372d4310d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68189409898352602816128981959264108461585509722277849434693754439387812588506 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.68189409898352602816128981959264108461585509722277849434693754439387812588506
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.83388266880783248442243065868808536417478247744606358435611000587365396692162
Short name T409
Test name
Test status
Simulation time 207522994332 ps
CPU time 813.28 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 199068 kb
Host smart-ade66f91-e6ee-4795-b4fa-7927095a66d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8338826688078324844224
3065868808536417478247744606358435611000587365396692162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_res
et.83388266880783248442243065868808536417478247744606358435611000587365396692162
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.88641922739440272681319208267900673010610934466199574522137416439665710632956
Short name T297
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.67 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:14:24 PM PST 23
Peak memory 183044 kb
Host smart-7430efdd-5483-4661-8566-5ff1373885ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8864192273944027268131920826790067301061093446619957452213741643966571063295
6 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.88641922739440272681319208267900673010610934466199
574522137416439665710632956
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.30747919053540604936966973426466024839969753558356040852760436366204188167955
Short name T357
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.25 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:04:44 PM PST 23
Peak memory 183012 kb
Host smart-48076a42-3282-4bc1-ae71-348d7246f0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30747919053540604936966973426466024839969753558356040852760436366204188167955 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.rv_timer_disabled.30747919053540604936966973426466024839969753558356040852760436366204188167955
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.29187949299035870543655971429783679249059076442744760747557071879602799552825
Short name T548
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.81 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:05:27 PM PST 23
Peak memory 183048 kb
Host smart-a20072e4-f69b-449a-9209-0390a2d8fb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29187949299035870543655971429783679249059076442744760747557071879602799552825 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.29187949299035870543655971429783679249059076442744760747557071879602799552825
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.81986594105740494546976080999357925642589302924501785871428458195435359409500
Short name T289
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.55 seconds
Started Nov 22 01:04:07 PM PST 23
Finished Nov 22 01:09:08 PM PST 23
Peak memory 191160 kb
Host smart-0eb2f200-e51e-4719-b122-957246cb2f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81986594105740494546976080999357925642589302924501785871428458195435359409500 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rv_timer_random_reset.81986594105740494546976080999357925642589302924501785871428458195435359409500
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.20012505435203632025274790622068016458987664454337029800234180484584780707159
Short name T18
Test name
Test status
Simulation time 135135591 ps
CPU time 0.9 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:04:04 PM PST 23
Peak memory 214324 kb
Host smart-c91ae14e-0587-456c-b8d9-44ab697d699e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20012505435203632025274790622068016458987664454337029800234180484584780707159 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.20012505435203632025274790622068016458987664454337029800234180484584780707159
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.45747558130143678095980528736019777736307743501696608370886051254646550043995
Short name T307
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1605.97 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:31:00 PM PST 23
Peak memory 191260 kb
Host smart-ae50af8d-fa13-400b-9b9f-c0694e6aac1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45747558130143678095980528736019777736307743501696608370886051254646550043995 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.45747558130143678095980528736019777736307743501696608370886051254646550043995
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.49523755030432447822712863104898085110493017257717357466997837210470525294016
Short name T333
Test name
Test status
Simulation time 207522994332 ps
CPU time 828.18 seconds
Started Nov 22 01:04:10 PM PST 23
Finished Nov 22 01:18:02 PM PST 23
Peak memory 199048 kb
Host smart-2819bedf-fc52-4504-8421-95a1d81e9b21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4952375503043244782271
2863104898085110493017257717357466997837210470525294016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_rese
t.49523755030432447822712863104898085110493017257717357466997837210470525294016
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.16406392096140227039735820738546392158617377556710964512053690957321684094829
Short name T502
Test name
Test status
Simulation time 544575976458 ps
CPU time 603.19 seconds
Started Nov 22 01:05:08 PM PST 23
Finished Nov 22 01:15:12 PM PST 23
Peak memory 183036 kb
Host smart-9a08c21c-cc24-4e53-9d7d-15f0679116c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640639209614022703973582073854639215861737755671096451205369095732168409482
9 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.1640639209614022703973582073854639215861737755671
0964512053690957321684094829
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.70293010019893890742253007341159415132466065688955336757247224426371070545014
Short name T440
Test name
Test status
Simulation time 32101379859 ps
CPU time 29.96 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:05:34 PM PST 23
Peak memory 183068 kb
Host smart-6d9ffb16-671b-460f-91a0-7ba4d42d0d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70293010019893890742253007341159415132466065688955336757247224426371070545014 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.rv_timer_disabled.70293010019893890742253007341159415132466065688955336757247224426371070545014
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.58763099390920131175224382366559130269142941805227435115846943680626161716874
Short name T550
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.16 seconds
Started Nov 22 01:05:02 PM PST 23
Finished Nov 22 01:06:16 PM PST 23
Peak memory 183052 kb
Host smart-cc88d232-9b7f-437b-a617-a6e8ae29fcc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58763099390920131175224382366559130269142941805227435115846943680626161716874 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.58763099390920131175224382366559130269142941805227435115846943680626161716874
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2697139342059689310093361528445946087253490906235244985701361336192610184688
Short name T594
Test name
Test status
Simulation time 60703901037 ps
CPU time 292.09 seconds
Started Nov 22 01:05:03 PM PST 23
Finished Nov 22 01:09:57 PM PST 23
Peak memory 191316 kb
Host smart-3e846183-5fa5-4a62-ad53-1915f88cc75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697139342059689310093361528445946087253490906235244985701361336192610184688 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.rv_timer_random_reset.2697139342059689310093361528445946087253490906235244985701361336192610184688
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.74637861169792867208833160669047693444250652091629208936272540061838143989050
Short name T555
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1611.87 seconds
Started Nov 22 01:05:10 PM PST 23
Finished Nov 22 01:32:03 PM PST 23
Peak memory 191220 kb
Host smart-31c3f1f6-2ad7-4257-9536-53ae3c0cc326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74637861169792867208833160669047693444250652091629208936272540061838143989050 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.74637861169792867208833160669047693444250652091629208936272540061838143989050
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.36429938646711636476940788094618992877453996351904969505079564458724153228236
Short name T497
Test name
Test status
Simulation time 207522994332 ps
CPU time 820.59 seconds
Started Nov 22 01:05:10 PM PST 23
Finished Nov 22 01:18:51 PM PST 23
Peak memory 199096 kb
Host smart-2c289959-b7c5-4f55-aeb3-e6f47640aee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642993864671163647694
0788094618992877453996351904969505079564458724153228236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_res
et.36429938646711636476940788094618992877453996351904969505079564458724153228236
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.61809217313623661307897561070451220761216894927117868997327379924865807396569
Short name T284
Test name
Test status
Simulation time 544575976458 ps
CPU time 618.18 seconds
Started Nov 22 01:05:07 PM PST 23
Finished Nov 22 01:15:27 PM PST 23
Peak memory 183028 kb
Host smart-310025fb-8f23-4766-940d-daeebb2aef86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6180921731362366130789756107045122076121689492711786899732737992486580739656
9 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.6180921731362366130789756107045122076121689492711
7868997327379924865807396569
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.79311930508034191797068971792467845293177370257385137213022163323371887738115
Short name T420
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.85 seconds
Started Nov 22 01:05:10 PM PST 23
Finished Nov 22 01:05:42 PM PST 23
Peak memory 183052 kb
Host smart-55a53e70-b811-46e1-9faf-d330e2f0f7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79311930508034191797068971792467845293177370257385137213022163323371887738115 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.rv_timer_disabled.79311930508034191797068971792467845293177370257385137213022163323371887738115
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.75030606669002988095901122134427354385565508466708272326333780411386113259508
Short name T592
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.85 seconds
Started Nov 22 01:05:07 PM PST 23
Finished Nov 22 01:06:23 PM PST 23
Peak memory 183052 kb
Host smart-5809ef8b-2f5d-4ec1-a2f2-cab397188323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75030606669002988095901122134427354385565508466708272326333780411386113259508 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.75030606669002988095901122134427354385565508466708272326333780411386113259508
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.28875040941006434010619303922817585699069744082726072794694482167562045415499
Short name T412
Test name
Test status
Simulation time 60703901037 ps
CPU time 296.8 seconds
Started Nov 22 01:05:16 PM PST 23
Finished Nov 22 01:10:14 PM PST 23
Peak memory 191300 kb
Host smart-b8194e03-ea53-49b0-8567-16338601a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28875040941006434010619303922817585699069744082726072794694482167562045415499 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.rv_timer_random_reset.28875040941006434010619303922817585699069744082726072794694482167562045415499
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.27219381037744061109813046989190538118540790274943501860877759731310916659272
Short name T567
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1601.19 seconds
Started Nov 22 01:05:09 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 191276 kb
Host smart-820633b3-f509-4e01-8ad7-f6284f7dca06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27219381037744061109813046989190538118540790274943501860877759731310916659272 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.27219381037744061109813046989190538118540790274943501860877759731310916659272
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.72227129833345931349333824850488800083713159854414617968714614510851899137420
Short name T277
Test name
Test status
Simulation time 207522994332 ps
CPU time 820.24 seconds
Started Nov 22 01:05:25 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 199100 kb
Host smart-e708f4db-9079-41db-b8cf-6c405fb4f13f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7222712983334593134933
3824850488800083713159854414617968714614510851899137420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_res
et.72227129833345931349333824850488800083713159854414617968714614510851899137420
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.38983684077535946592463799800133065118920928586487634734886833179179433545520
Short name T533
Test name
Test status
Simulation time 544575976458 ps
CPU time 612.57 seconds
Started Nov 22 01:05:29 PM PST 23
Finished Nov 22 01:15:43 PM PST 23
Peak memory 183056 kb
Host smart-60bc1eea-7eaf-4386-83e8-9dd6465cc701
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898368407753594659246379980013306511892092858648763473488683317917943354552
0 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3898368407753594659246379980013306511892092858648
7634734886833179179433545520
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.67488188834782145973609049213606374538392774524250941327421739676666116323479
Short name T20
Test name
Test status
Simulation time 32101379859 ps
CPU time 30 seconds
Started Nov 22 01:05:18 PM PST 23
Finished Nov 22 01:05:49 PM PST 23
Peak memory 183044 kb
Host smart-09f09e14-5904-4c3e-b4d7-67f6cd961c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67488188834782145973609049213606374538392774524250941327421739676666116323479 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.rv_timer_disabled.67488188834782145973609049213606374538392774524250941327421739676666116323479
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.62199462592458326006826347412755635377263606869189212882160332592356495834267
Short name T325
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.43 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 183088 kb
Host smart-82b9fdb0-050e-441b-b297-37926d0e156f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62199462592458326006826347412755635377263606869189212882160332592356495834267 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.62199462592458326006826347412755635377263606869189212882160332592356495834267
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.7787328235608367119366492894086244295697063823659209100629658287438724619313
Short name T340
Test name
Test status
Simulation time 60703901037 ps
CPU time 297.53 seconds
Started Nov 22 01:05:16 PM PST 23
Finished Nov 22 01:10:15 PM PST 23
Peak memory 191264 kb
Host smart-f46c27bc-e5eb-4fc9-8c4b-7ddddc821a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7787328235608367119366492894086244295697063823659209100629658287438724619313 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.rv_timer_random_reset.7787328235608367119366492894086244295697063823659209100629658287438724619313
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.72011350246853069186763239294469467261019830138706248919461174063580492921122
Short name T443
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1606.61 seconds
Started Nov 22 01:05:16 PM PST 23
Finished Nov 22 01:32:04 PM PST 23
Peak memory 191276 kb
Host smart-5baf8e50-1d9d-43ea-9d0b-970bbdd7d372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72011350246853069186763239294469467261019830138706248919461174063580492921122 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.72011350246853069186763239294469467261019830138706248919461174063580492921122
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.25066873469842810417588413068353011389163222254480756315416657526395718463428
Short name T610
Test name
Test status
Simulation time 207522994332 ps
CPU time 811.21 seconds
Started Nov 22 01:05:17 PM PST 23
Finished Nov 22 01:18:49 PM PST 23
Peak memory 199060 kb
Host smart-bcda20ca-f808-4769-820b-3b5dc68145a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506687346984281041758
8413068353011389163222254480756315416657526395718463428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_res
et.25066873469842810417588413068353011389163222254480756315416657526395718463428
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.71680212358520646774923794836743035575306918710436106021721287781177134049039
Short name T511
Test name
Test status
Simulation time 544575976458 ps
CPU time 622.32 seconds
Started Nov 22 01:05:26 PM PST 23
Finished Nov 22 01:15:50 PM PST 23
Peak memory 183028 kb
Host smart-c01a3db1-a5c4-4e0f-a982-3f98ec7e0828
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7168021235852064677492379483674303557530691871043610602172128778117713404903
9 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.7168021235852064677492379483674303557530691871043
6106021721287781177134049039
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.64085982991304514871521425284861173206454830560225344147195339969685234822440
Short name T565
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.5 seconds
Started Nov 22 01:05:29 PM PST 23
Finished Nov 22 01:06:01 PM PST 23
Peak memory 183084 kb
Host smart-16c3fdd1-debf-4930-a1ae-5ef7fef16e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64085982991304514871521425284861173206454830560225344147195339969685234822440 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.rv_timer_disabled.64085982991304514871521425284861173206454830560225344147195339969685234822440
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.104023928662571160115121148353636567648982201344721886106923036095961914328440
Short name T540
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.52 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 183060 kb
Host smart-2333a2de-7cb7-4674-b61d-99fd9b170602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104023928662571160115121148353636567648982201344721886106923036095961914328440 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.104023928662571160115121148353636567648982201344721886106923036095961914328440
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.99109632508074960987564407383991233052840088954735267250109864702009298065235
Short name T303
Test name
Test status
Simulation time 60703901037 ps
CPU time 291.71 seconds
Started Nov 22 01:05:30 PM PST 23
Finished Nov 22 01:10:23 PM PST 23
Peak memory 191048 kb
Host smart-2e8dfe95-14c4-4e34-948b-d33c09779b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99109632508074960987564407383991233052840088954735267250109864702009298065235 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.rv_timer_random_reset.99109632508074960987564407383991233052840088954735267250109864702009298065235
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.37861716835700069229338697148344370977947851294754312615402771453706683457247
Short name T235
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1605.32 seconds
Started Nov 22 01:05:29 PM PST 23
Finished Nov 22 01:32:16 PM PST 23
Peak memory 191280 kb
Host smart-8752e436-ea13-4eed-aa61-80ec6f979215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861716835700069229338697148344370977947851294754312615402771453706683457247 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.37861716835700069229338697148344370977947851294754312615402771453706683457247
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.81450995397083788543164731550647631331688689036753420930032326455142337331078
Short name T553
Test name
Test status
Simulation time 207522994332 ps
CPU time 821.86 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 199124 kb
Host smart-73285fa0-4df2-4d8f-836c-ff904588015f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8145099539708378854316
4731550647631331688689036753420930032326455142337331078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_res
et.81450995397083788543164731550647631331688689036753420930032326455142337331078
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.89393507665765874640311576615212379822130653688665002755816340997523559311088
Short name T620
Test name
Test status
Simulation time 544575976458 ps
CPU time 612.46 seconds
Started Nov 22 01:05:21 PM PST 23
Finished Nov 22 01:15:35 PM PST 23
Peak memory 183020 kb
Host smart-dabbe1b7-c01c-4b6a-924f-e2bde80bb86d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8939350766576587464031157661521237982213065368866500275581634099752355931108
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.8939350766576587464031157661521237982213065368866
5002755816340997523559311088
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.100452715811251995673150143980499515422943220848803161659445700344451238879358
Short name T484
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.32 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:06:07 PM PST 23
Peak memory 183056 kb
Host smart-8e43fea8-cbee-4f4a-8686-22bc7f6ff1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100452715811251995673150143980499515422943220848803161659445700344451238879358 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.rv_timer_disabled.100452715811251995673150143980499515422943220848803161659445700344451238879358
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.97147238825444524742425149474588340599520757881086994309369858446307750559231
Short name T285
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.6 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 183056 kb
Host smart-7fd8acfe-00ed-4666-807b-a81523392e27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97147238825444524742425149474588340599520757881086994309369858446307750559231 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.97147238825444524742425149474588340599520757881086994309369858446307750559231
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.32084135690771913631336672051732619228905809932423675857576104046574295484264
Short name T546
Test name
Test status
Simulation time 60703901037 ps
CPU time 299.41 seconds
Started Nov 22 01:05:12 PM PST 23
Finished Nov 22 01:10:13 PM PST 23
Peak memory 191268 kb
Host smart-ea2a8775-ae75-48c2-a64c-788d844683db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32084135690771913631336672051732619228905809932423675857576104046574295484264 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.rv_timer_random_reset.32084135690771913631336672051732619228905809932423675857576104046574295484264
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.28425698472543046765334529889922567529410164196365747065869772076062532592776
Short name T572
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1623.55 seconds
Started Nov 22 01:05:27 PM PST 23
Finished Nov 22 01:32:32 PM PST 23
Peak memory 191276 kb
Host smart-1a9e9bcf-dae8-43df-b244-91d2e846c463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425698472543046765334529889922567529410164196365747065869772076062532592776 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.28425698472543046765334529889922567529410164196365747065869772076062532592776
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.9598365911351578302612582945639770915036922690098475793853790933800774665454
Short name T509
Test name
Test status
Simulation time 207522994332 ps
CPU time 818.89 seconds
Started Nov 22 01:05:27 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 199084 kb
Host smart-facab678-3b9c-4cfd-9a92-135388a6eebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9598365911351578302612
582945639770915036922690098475793853790933800774665454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_rese
t.9598365911351578302612582945639770915036922690098475793853790933800774665454
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.32744390211312195984297595312088012501608835214231794344193208862746822730342
Short name T317
Test name
Test status
Simulation time 544575976458 ps
CPU time 619.28 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:15:56 PM PST 23
Peak memory 182944 kb
Host smart-495a7e8a-07b4-44a3-a3a9-a48a4d482694
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274439021131219598429759531208801250160883521423179434419320886274682273034
2 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3274439021131219598429759531208801250160883521423
1794344193208862746822730342
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.88059344394533289859034788409374173677712927114953144776482868717049014732226
Short name T487
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.11 seconds
Started Nov 22 01:05:19 PM PST 23
Finished Nov 22 01:05:52 PM PST 23
Peak memory 183084 kb
Host smart-1384c559-31c1-48ce-b057-91b931375c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88059344394533289859034788409374173677712927114953144776482868717049014732226 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.rv_timer_disabled.88059344394533289859034788409374173677712927114953144776482868717049014732226
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.31584787037799080036210404382689263592526194384788706806339208641923093411117
Short name T499
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.95 seconds
Started Nov 22 01:05:08 PM PST 23
Finished Nov 22 01:06:23 PM PST 23
Peak memory 182956 kb
Host smart-fc4eaff9-322d-4bb8-8ea7-a351ad65b2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31584787037799080036210404382689263592526194384788706806339208641923093411117 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.31584787037799080036210404382689263592526194384788706806339208641923093411117
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.51419569769699616812624443731499030707660731799349412149656445186484426688105
Short name T426
Test name
Test status
Simulation time 60703901037 ps
CPU time 299.57 seconds
Started Nov 22 01:05:21 PM PST 23
Finished Nov 22 01:10:22 PM PST 23
Peak memory 191260 kb
Host smart-b86078b4-8364-49e3-9578-1fcb43db3fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51419569769699616812624443731499030707660731799349412149656445186484426688105 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.rv_timer_random_reset.51419569769699616812624443731499030707660731799349412149656445186484426688105
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.68080472262566061270841832542502404550335060363503919884524814793015280815541
Short name T240
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1629.99 seconds
Started Nov 22 01:05:29 PM PST 23
Finished Nov 22 01:32:41 PM PST 23
Peak memory 191256 kb
Host smart-440867af-b6f2-437a-84b9-9134b3b93ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68080472262566061270841832542502404550335060363503919884524814793015280815541 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.68080472262566061270841832542502404550335060363503919884524814793015280815541
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.62036388730380558274576488681516164828476567530090249617283225957465919566554
Short name T399
Test name
Test status
Simulation time 207522994332 ps
CPU time 813.4 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:19:04 PM PST 23
Peak memory 199092 kb
Host smart-d032fd81-1707-4453-a7cb-58aae0ae3139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6203638873038055827457
6488681516164828476567530090249617283225957465919566554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_res
et.62036388730380558274576488681516164828476567530090249617283225957465919566554
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.105268868830464180464056516651697821571975514083689321727798980069238341707065
Short name T616
Test name
Test status
Simulation time 544575976458 ps
CPU time 617.83 seconds
Started Nov 22 01:05:16 PM PST 23
Finished Nov 22 01:15:35 PM PST 23
Peak memory 183068 kb
Host smart-3f4e1de7-b721-4232-8b6b-e4f81e43605c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052688688304641804640565166516978215719755140836893217277989800692383417070
65 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.105268868830464180464056516651697821571975514083
689321727798980069238341707065
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.6672104031256455135400126273394674579825127877881114027467381891811735098270
Short name T559
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.07 seconds
Started Nov 22 01:05:21 PM PST 23
Finished Nov 22 01:05:53 PM PST 23
Peak memory 183080 kb
Host smart-51a4be98-9dcd-411b-9d3d-6eb5b26c8a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6672104031256455135400126273394674579825127877881114027467381891811735098270 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.rv_timer_disabled.6672104031256455135400126273394674579825127877881114027467381891811735098270
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.82249114777060357941603719025705277539472889855801272504864940772284709588637
Short name T403
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.15 seconds
Started Nov 22 01:05:18 PM PST 23
Finished Nov 22 01:06:31 PM PST 23
Peak memory 182992 kb
Host smart-92fa371a-411c-457d-8094-24d4d30e9fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82249114777060357941603719025705277539472889855801272504864940772284709588637 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.82249114777060357941603719025705277539472889855801272504864940772284709588637
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.6161157553115937328722538477533440698251758472138663099195132017737518406791
Short name T66
Test name
Test status
Simulation time 60703901037 ps
CPU time 298.78 seconds
Started Nov 22 01:05:27 PM PST 23
Finished Nov 22 01:10:28 PM PST 23
Peak memory 191288 kb
Host smart-6cdff1fa-eb4e-49b7-a776-1f2389b6fae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6161157553115937328722538477533440698251758472138663099195132017737518406791 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.rv_timer_random_reset.6161157553115937328722538477533440698251758472138663099195132017737518406791
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.50821909185828201937144083126465346956904829302492617364693927147796736635866
Short name T411
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1606.07 seconds
Started Nov 22 01:05:05 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 191144 kb
Host smart-20ed0cc6-e2af-4760-ab66-5a813f4c5bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50821909185828201937144083126465346956904829302492617364693927147796736635866 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.50821909185828201937144083126465346956904829302492617364693927147796736635866
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.18618599331092393917440908110602420814689160440587828254144084359368410410341
Short name T30
Test name
Test status
Simulation time 207522994332 ps
CPU time 804.75 seconds
Started Nov 22 01:05:24 PM PST 23
Finished Nov 22 01:18:51 PM PST 23
Peak memory 199100 kb
Host smart-7fd44e25-5338-422d-9d39-022e34f5bd19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861859933109239391744
0908110602420814689160440587828254144084359368410410341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_res
et.18618599331092393917440908110602420814689160440587828254144084359368410410341
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.41567320192802749789579189464861485780695687016558569028743350514544907913409
Short name T590
Test name
Test status
Simulation time 544575976458 ps
CPU time 619.74 seconds
Started Nov 22 01:05:33 PM PST 23
Finished Nov 22 01:15:55 PM PST 23
Peak memory 183052 kb
Host smart-f938e573-ce13-4838-a9c4-1120bfff6a23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156732019280274978957918946486148578069568701655856902874335051454490791340
9 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.4156732019280274978957918946486148578069568701655
8569028743350514544907913409
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2429415269750410467849470992684546442534288665277025679741195339285823748849
Short name T338
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.43 seconds
Started Nov 22 01:05:31 PM PST 23
Finished Nov 22 01:06:04 PM PST 23
Peak memory 183064 kb
Host smart-f705d0d1-08b6-4407-8479-a453828c3e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429415269750410467849470992684546442534288665277025679741195339285823748849 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.rv_timer_disabled.2429415269750410467849470992684546442534288665277025679741195339285823748849
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.104004586854640467400169722650593274260408649746048875339529902449441791223484
Short name T309
Test name
Test status
Simulation time 70917337186 ps
CPU time 74 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:06:51 PM PST 23
Peak memory 183064 kb
Host smart-aa572cb7-5979-4b45-93f0-d7b2e4a06a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104004586854640467400169722650593274260408649746048875339529902449441791223484 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.104004586854640467400169722650593274260408649746048875339529902449441791223484
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.16346490097903977560324996141503695967747871498530285354359623572177280443817
Short name T246
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.78 seconds
Started Nov 22 01:05:29 PM PST 23
Finished Nov 22 01:10:26 PM PST 23
Peak memory 191280 kb
Host smart-b7c88198-14b6-42d2-902a-3fb1d14cbe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16346490097903977560324996141503695967747871498530285354359623572177280443817 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rv_timer_random_reset.16346490097903977560324996141503695967747871498530285354359623572177280443817
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.27650641275368114709868385663967405345326886515980158459066403689040710739161
Short name T372
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1630.34 seconds
Started Nov 22 01:05:27 PM PST 23
Finished Nov 22 01:32:40 PM PST 23
Peak memory 191220 kb
Host smart-142c8f8b-6cef-4f48-a4f8-a03398e709f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650641275368114709868385663967405345326886515980158459066403689040710739161 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.27650641275368114709868385663967405345326886515980158459066403689040710739161
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.87175888246875717314130036138684490022020105388658327153390217682124168947275
Short name T562
Test name
Test status
Simulation time 207522994332 ps
CPU time 803.25 seconds
Started Nov 22 01:05:32 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 199120 kb
Host smart-3e3e9f2b-91eb-4953-8fb2-95391c76cc38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8717588824687571731413
0036138684490022020105388658327153390217682124168947275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_res
et.87175888246875717314130036138684490022020105388658327153390217682124168947275
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.62562255130854315051457320199243754411263236479466170060528439160177994123061
Short name T485
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.49 seconds
Started Nov 22 01:05:49 PM PST 23
Finished Nov 22 01:16:01 PM PST 23
Peak memory 183056 kb
Host smart-a9258ad5-89f9-465d-88e3-9a3deaf0e9ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6256225513085431505145732019924375441126323647946617006052843916017799412306
1 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.6256225513085431505145732019924375441126323647946
6170060528439160177994123061
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.71242363917340236410861739198984231933369381128628689166424620544321595528397
Short name T320
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.43 seconds
Started Nov 22 01:05:32 PM PST 23
Finished Nov 22 01:06:04 PM PST 23
Peak memory 183068 kb
Host smart-13e83e5a-8a40-4f55-8ba1-7130c44c23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71242363917340236410861739198984231933369381128628689166424620544321595528397 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.rv_timer_disabled.71242363917340236410861739198984231933369381128628689166424620544321595528397
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.22564363635291107411241672944936276472160062409960315393724414676688905135125
Short name T586
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.02 seconds
Started Nov 22 01:05:27 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 183012 kb
Host smart-1fc4905a-53b4-4b2f-8e02-eb4a07467dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22564363635291107411241672944936276472160062409960315393724414676688905135125 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.22564363635291107411241672944936276472160062409960315393724414676688905135125
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.35162550107603575860816215289557632518734665037065892382561020952950798240570
Short name T88
Test name
Test status
Simulation time 60703901037 ps
CPU time 308.29 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:10:38 PM PST 23
Peak memory 191220 kb
Host smart-948ceb8a-7e9c-4885-8c4c-70d2e00b5ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35162550107603575860816215289557632518734665037065892382561020952950798240570 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.rv_timer_random_reset.35162550107603575860816215289557632518734665037065892382561020952950798240570
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.51197138067263761321248753867563201158560129023703536816739917520506049452227
Short name T330
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1600.1 seconds
Started Nov 22 01:05:18 PM PST 23
Finished Nov 22 01:31:59 PM PST 23
Peak memory 191228 kb
Host smart-ac1344c8-f463-438f-ba5f-904e83fc744e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51197138067263761321248753867563201158560129023703536816739917520506049452227 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.51197138067263761321248753867563201158560129023703536816739917520506049452227
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.14551496948661608238829417743151324780068960490693313023556353668681695859931
Short name T275
Test name
Test status
Simulation time 207522994332 ps
CPU time 819.18 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:19:15 PM PST 23
Peak memory 199116 kb
Host smart-af91afa7-d7a9-4bb2-b96b-28c5f7ed0c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455149694866160823882
9417743151324780068960490693313023556353668681695859931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_res
et.14551496948661608238829417743151324780068960490693313023556353668681695859931
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.68721424879641789564317336544527287252520167631231344448487212026449868306079
Short name T378
Test name
Test status
Simulation time 544575976458 ps
CPU time 612.67 seconds
Started Nov 22 01:05:31 PM PST 23
Finished Nov 22 01:15:46 PM PST 23
Peak memory 183068 kb
Host smart-fec6aec7-a50e-4db8-9fe3-33afc4ad6c8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6872142487964178956431733654452728725252016763123134444848721202644986830607
9 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.6872142487964178956431733654452728725252016763123
1344448487212026449868306079
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.87788686134702182509223773488887657088705560962351073373798913980977976696599
Short name T329
Test name
Test status
Simulation time 32101379859 ps
CPU time 29.96 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:06:00 PM PST 23
Peak memory 183068 kb
Host smart-535e0f32-c949-4d42-9a86-ff21b55169ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87788686134702182509223773488887657088705560962351073373798913980977976696599 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.rv_timer_disabled.87788686134702182509223773488887657088705560962351073373798913980977976696599
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.112044217474904276559769160088829699372210948563251482095602240683184605490793
Short name T575
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.95 seconds
Started Nov 22 01:05:28 PM PST 23
Finished Nov 22 01:06:44 PM PST 23
Peak memory 183052 kb
Host smart-4b3da8f8-a65a-4306-b494-b4a6443d3bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112044217474904276559769160088829699372210948563251482095602240683184605490793 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.112044217474904276559769160088829699372210948563251482095602240683184605490793
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.110945700978294428153577911486784597801716093653788954661640586366317178755150
Short name T8
Test name
Test status
Simulation time 60703901037 ps
CPU time 292.76 seconds
Started Nov 22 01:05:42 PM PST 23
Finished Nov 22 01:10:37 PM PST 23
Peak memory 191280 kb
Host smart-19821575-0bd3-4b0a-81e8-9d645df51d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110945700978294428153577911486784597801716093653788954661640586366317178755150 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.rv_timer_random_reset.110945700978294428153577911486784597801716093653788954661640586366317178755150
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.83000769839657582656060345705547556915696214016647667443301106871422882747726
Short name T491
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1605.62 seconds
Started Nov 22 01:05:37 PM PST 23
Finished Nov 22 01:32:25 PM PST 23
Peak memory 191156 kb
Host smart-f6553635-1848-43d3-81e9-5abbf3775de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83000769839657582656060345705547556915696214016647667443301106871422882747726 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.83000769839657582656060345705547556915696214016647667443301106871422882747726
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.107792032376474134167417595249818901233267949932895039743967744653229979543727
Short name T618
Test name
Test status
Simulation time 207522994332 ps
CPU time 819.39 seconds
Started Nov 22 01:05:23 PM PST 23
Finished Nov 22 01:19:04 PM PST 23
Peak memory 199024 kb
Host smart-b02babb5-d8e2-4afb-be0e-603c0d7ed6f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077920323764741341674
17595249818901233267949932895039743967744653229979543727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_re
set.107792032376474134167417595249818901233267949932895039743967744653229979543727
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.31595678015400270932507792437564284362631417075469776787103579972417885221968
Short name T465
Test name
Test status
Simulation time 544575976458 ps
CPU time 613 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:14:27 PM PST 23
Peak memory 183028 kb
Host smart-1b37dca4-1914-488f-8edc-8ff3bb4a3af3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159567801540027093250779243756428436263141707546977678710357997241788522196
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.31595678015400270932507792437564284362631417075469
776787103579972417885221968
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.54325308601822090617090958240860702280788052135974668263877011530187444698136
Short name T537
Test name
Test status
Simulation time 32101379859 ps
CPU time 29.93 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:04:35 PM PST 23
Peak memory 183080 kb
Host smart-56f84f9c-5007-4099-9d69-04da446fc9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54325308601822090617090958240860702280788052135974668263877011530187444698136 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.rv_timer_disabled.54325308601822090617090958240860702280788052135974668263877011530187444698136
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.40634695021044474208863229408910961146970068433724261789043388889945021423771
Short name T602
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.11 seconds
Started Nov 22 01:04:05 PM PST 23
Finished Nov 22 01:05:27 PM PST 23
Peak memory 183056 kb
Host smart-1208c8b4-2644-4f71-afca-23ffeda7ab16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40634695021044474208863229408910961146970068433724261789043388889945021423771 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.40634695021044474208863229408910961146970068433724261789043388889945021423771
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.63568702776426960842857558993416643559456645439894058848866426814361974831056
Short name T79
Test name
Test status
Simulation time 60703901037 ps
CPU time 299.77 seconds
Started Nov 22 01:03:59 PM PST 23
Finished Nov 22 01:09:07 PM PST 23
Peak memory 191292 kb
Host smart-820750f1-64ca-49c6-bb65-60509b9b2a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63568702776426960842857558993416643559456645439894058848866426814361974831056 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rv_timer_random_reset.63568702776426960842857558993416643559456645439894058848866426814361974831056
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.78852657633052171693578894188798217248384070634986946818439541340692828825892
Short name T16
Test name
Test status
Simulation time 135135591 ps
CPU time 0.88 seconds
Started Nov 22 01:04:08 PM PST 23
Finished Nov 22 01:04:14 PM PST 23
Peak memory 214348 kb
Host smart-a4cce412-b19f-456d-9c0a-a6aba29a2b5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78852657633052171693578894188798217248384070634986946818439541340692828825892 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.78852657633052171693578894188798217248384070634986946818439541340692828825892
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.25621458552390459022728811465725241741701519423765423895550194140788727909677
Short name T543
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1590.1 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:30:46 PM PST 23
Peak memory 191224 kb
Host smart-e8f7f40f-99e4-4e3b-b68f-51375aedfa1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25621458552390459022728811465725241741701519423765423895550194140788727909677 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.25621458552390459022728811465725241741701519423765423895550194140788727909677
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.5166471088199315368101236880902604949103132606988251372806710432913399525532
Short name T331
Test name
Test status
Simulation time 207522994332 ps
CPU time 819.73 seconds
Started Nov 22 01:04:11 PM PST 23
Finished Nov 22 01:17:54 PM PST 23
Peak memory 199064 kb
Host smart-ec2417be-5784-4379-919a-1dd79d48fb7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5166471088199315368101
236880902604949103132606988251372806710432913399525532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset
.5166471088199315368101236880902604949103132606988251372806710432913399525532
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.92422494833251873333052480108958071514590411220911059988367268989413872742062
Short name T486
Test name
Test status
Simulation time 544575976458 ps
CPU time 618.73 seconds
Started Nov 22 01:05:42 PM PST 23
Finished Nov 22 01:16:02 PM PST 23
Peak memory 183048 kb
Host smart-7c4f2040-5396-4c7a-afcf-2a32bc0c61bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9242249483325187333305248010895807151459041122091105998836726898941387274206
2 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.9242249483325187333305248010895807151459041122091
1059988367268989413872742062
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.109157106908326100766768082631560327607819069399941506041856904191610406676708
Short name T316
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.91 seconds
Started Nov 22 01:05:37 PM PST 23
Finished Nov 22 01:06:10 PM PST 23
Peak memory 183040 kb
Host smart-99225d79-26cc-4b9e-99b2-5e9ed522905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109157106908326100766768082631560327607819069399941506041856904191610406676708 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.rv_timer_disabled.109157106908326100766768082631560327607819069399941506041856904191610406676708
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.9435019619621849518460540173417910872691222695325043058754490495623998151854
Short name T280
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.89 seconds
Started Nov 22 01:05:30 PM PST 23
Finished Nov 22 01:06:45 PM PST 23
Peak memory 182960 kb
Host smart-c4fdd3d1-13e1-4c67-af02-9f8bb70cd52a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9435019619621849518460540173417910872691222695325043058754490495623998151854 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.9435019619621849518460540173417910872691222695325043058754490495623998151854
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.83152657469795064479395520031555354951841503942663090035123961804983254478458
Short name T25
Test name
Test status
Simulation time 60703901037 ps
CPU time 300.95 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:10:38 PM PST 23
Peak memory 191264 kb
Host smart-c582692d-13fe-45bc-8c58-fb18a164a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83152657469795064479395520031555354951841503942663090035123961804983254478458 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.rv_timer_random_reset.83152657469795064479395520031555354951841503942663090035123961804983254478458
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.107059671639935816047767602219684003606466071451846214331093394365687977616592
Short name T482
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1595.24 seconds
Started Nov 22 01:05:23 PM PST 23
Finished Nov 22 01:32:00 PM PST 23
Peak memory 191172 kb
Host smart-e71283be-67d3-4269-921c-3d418cf0b31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107059671639935816047767602219684003606466071451846214331093394365687977616592 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.107059671639935816047767602219684003606466071451846214331093394365687977616592
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.87989109848041157219891595906356844025048410898849417082688786035480518965043
Short name T11
Test name
Test status
Simulation time 207522994332 ps
CPU time 804.44 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 199120 kb
Host smart-c1b9e7c3-4a1d-492e-9d58-4a10d5ef8339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8798910984804115721989
1595906356844025048410898849417082688786035480518965043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_res
et.87989109848041157219891595906356844025048410898849417082688786035480518965043
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.30889768192952839940455347521301690488877093350020395438224507935985939975635
Short name T96
Test name
Test status
Simulation time 544575976458 ps
CPU time 607.73 seconds
Started Nov 22 01:05:39 PM PST 23
Finished Nov 22 01:15:49 PM PST 23
Peak memory 183068 kb
Host smart-083f9598-110d-4516-a7e0-f2ef9c3294aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088976819295283994045534752130169048887709335002039543822450793598593997563
5 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3088976819295283994045534752130169048887709335002
0395438224507935985939975635
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.67144452387479019714906757292296806835909796839495480412365190229803601526159
Short name T494
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.77 seconds
Started Nov 22 01:05:40 PM PST 23
Finished Nov 22 01:06:12 PM PST 23
Peak memory 182996 kb
Host smart-0769fed0-c521-441a-9b15-b3380b58fa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67144452387479019714906757292296806835909796839495480412365190229803601526159 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.rv_timer_disabled.67144452387479019714906757292296806835909796839495480412365190229803601526159
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.94672047073018751848034463502511246101192374053234014715542772490056076525273
Short name T80
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.35 seconds
Started Nov 22 01:05:42 PM PST 23
Finished Nov 22 01:06:57 PM PST 23
Peak memory 183076 kb
Host smart-b4051f13-7c50-466b-b00c-11ef620f07ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94672047073018751848034463502511246101192374053234014715542772490056076525273 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.94672047073018751848034463502511246101192374053234014715542772490056076525273
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.50719852864578391168572986152180799290789379372492681090872780796046085242188
Short name T242
Test name
Test status
Simulation time 60703901037 ps
CPU time 293.07 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:10:40 PM PST 23
Peak memory 191264 kb
Host smart-0ba470b9-0284-4b00-b4fd-1ce6c74dc3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50719852864578391168572986152180799290789379372492681090872780796046085242188 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.rv_timer_random_reset.50719852864578391168572986152180799290789379372492681090872780796046085242188
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.12848241738773652325870553803107665417577883635712866282638266937823896923340
Short name T516
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1609.25 seconds
Started Nov 22 01:05:36 PM PST 23
Finished Nov 22 01:32:27 PM PST 23
Peak memory 191164 kb
Host smart-ad9f0f17-7927-470f-80f2-4f96f3271722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12848241738773652325870553803107665417577883635712866282638266937823896923340 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.12848241738773652325870553803107665417577883635712866282638266937823896923340
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.69750405173190379834026846691905592909899718483480616049584383646421386400455
Short name T392
Test name
Test status
Simulation time 207522994332 ps
CPU time 798.16 seconds
Started Nov 22 01:05:40 PM PST 23
Finished Nov 22 01:19:00 PM PST 23
Peak memory 199032 kb
Host smart-5304f17d-79df-479d-901b-cf9e0d1e1fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6975040517319037983402
6846691905592909899718483480616049584383646421386400455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_res
et.69750405173190379834026846691905592909899718483480616049584383646421386400455
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.105453087901733330661653719296009378322611027672384853958995690001724007202397
Short name T376
Test name
Test status
Simulation time 544575976458 ps
CPU time 604.43 seconds
Started Nov 22 01:05:43 PM PST 23
Finished Nov 22 01:15:50 PM PST 23
Peak memory 183036 kb
Host smart-07b3217b-dd56-45b9-83d3-67aebbf5671b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054530879017333306616537192960093783226110276723848539589956900017240072023
97 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.105453087901733330661653719296009378322611027672
384853958995690001724007202397
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.64636607453135196442109278632559507533254600573371937823738962137070700508180
Short name T336
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.58 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:06:08 PM PST 23
Peak memory 182968 kb
Host smart-b8812922-a572-465d-b9c9-5f320c1548c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64636607453135196442109278632559507533254600573371937823738962137070700508180 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.rv_timer_disabled.64636607453135196442109278632559507533254600573371937823738962137070700508180
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.87990533700185163156212925633296570981403089910620082330058757148164805953183
Short name T523
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.01 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 183060 kb
Host smart-ac84b56b-2f28-485e-9dd5-cb288f3a16c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87990533700185163156212925633296570981403089910620082330058757148164805953183 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.87990533700185163156212925633296570981403089910620082330058757148164805953183
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.55138222159562438487880874653874084636905517343330118514805896469247346989724
Short name T605
Test name
Test status
Simulation time 60703901037 ps
CPU time 298.27 seconds
Started Nov 22 01:05:41 PM PST 23
Finished Nov 22 01:10:40 PM PST 23
Peak memory 191204 kb
Host smart-5d58d5b9-44dd-431d-930e-0e3d2a28ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55138222159562438487880874653874084636905517343330118514805896469247346989724 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.rv_timer_random_reset.55138222159562438487880874653874084636905517343330118514805896469247346989724
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.41089386299271328819328350204323652456701790564575737793336109861311272012879
Short name T414
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1601.88 seconds
Started Nov 22 01:05:37 PM PST 23
Finished Nov 22 01:32:21 PM PST 23
Peak memory 191212 kb
Host smart-96cc0b62-2765-4fcc-8e10-35932f9ac242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089386299271328819328350204323652456701790564575737793336109861311272012879 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.41089386299271328819328350204323652456701790564575737793336109861311272012879
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.54257680490645003710524396022877873026040370007197203794998571787203977033367
Short name T402
Test name
Test status
Simulation time 207522994332 ps
CPU time 814.5 seconds
Started Nov 22 01:05:34 PM PST 23
Finished Nov 22 01:19:10 PM PST 23
Peak memory 199088 kb
Host smart-13d9c0e7-d562-4819-bf1e-41280deae003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5425768049064500371052
4396022877873026040370007197203794998571787203977033367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_res
et.54257680490645003710524396022877873026040370007197203794998571787203977033367
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.8902641005234337315333751565522290946152419295416639881006513172145690198163
Short name T367
Test name
Test status
Simulation time 544575976458 ps
CPU time 624.36 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:16:02 PM PST 23
Peak memory 183044 kb
Host smart-09a6b677-bc35-49ff-8e6e-d4a2c86ab564
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8902641005234337315333751565522290946152419295416639881006513172145690198163
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.89026410052343373153337515655222909461524192954166
39881006513172145690198163
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.30969766168310943974218993979044471164129056251886799592923713648609089445631
Short name T283
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.2 seconds
Started Nov 22 01:05:32 PM PST 23
Finished Nov 22 01:06:04 PM PST 23
Peak memory 183032 kb
Host smart-4494cc12-7221-44dd-a22d-4d94022c5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30969766168310943974218993979044471164129056251886799592923713648609089445631 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.rv_timer_disabled.30969766168310943974218993979044471164129056251886799592923713648609089445631
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.43845094845888103894666785707738246254193641272464311420627137025388346356995
Short name T574
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.86 seconds
Started Nov 22 01:05:34 PM PST 23
Finished Nov 22 01:06:49 PM PST 23
Peak memory 183056 kb
Host smart-3d304968-862e-49b8-9b97-0182399910ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43845094845888103894666785707738246254193641272464311420627137025388346356995 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.43845094845888103894666785707738246254193641272464311420627137025388346356995
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.71468593515924484186675310616712674479397094305794936481894717386037676592511
Short name T576
Test name
Test status
Simulation time 60703901037 ps
CPU time 299.43 seconds
Started Nov 22 01:05:32 PM PST 23
Finished Nov 22 01:10:33 PM PST 23
Peak memory 191260 kb
Host smart-f99374c2-a126-4a91-9add-4ca0f766c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71468593515924484186675310616712674479397094305794936481894717386037676592511 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rv_timer_random_reset.71468593515924484186675310616712674479397094305794936481894717386037676592511
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.47793492803230528098520756683219390839590817277001661784209258407996334797238
Short name T265
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1572.17 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:32:00 PM PST 23
Peak memory 191252 kb
Host smart-b79857d4-a19d-44b1-bef6-541f4cd8efb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47793492803230528098520756683219390839590817277001661784209258407996334797238 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.47793492803230528098520756683219390839590817277001661784209258407996334797238
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.49483360006412310664535862589610553704923067398794974251683597039553623560363
Short name T387
Test name
Test status
Simulation time 207522994332 ps
CPU time 812.86 seconds
Started Nov 22 01:05:40 PM PST 23
Finished Nov 22 01:19:15 PM PST 23
Peak memory 199048 kb
Host smart-f48d7687-346a-42fa-879e-a779ccd50bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4948336000641231066453
5862589610553704923067398794974251683597039553623560363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_res
et.49483360006412310664535862589610553704923067398794974251683597039553623560363
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.760421205024075484305612381158893089753784389682769659425575313773754736020
Short name T369
Test name
Test status
Simulation time 544575976458 ps
CPU time 615.9 seconds
Started Nov 22 01:05:35 PM PST 23
Finished Nov 22 01:15:53 PM PST 23
Peak memory 182948 kb
Host smart-2e979c6d-551f-44fc-acf5-0baffd5ba209
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760421205024075484305612381158893089753784389682769659425575313773754736020
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.760421205024075484305612381158893089753784389682769
659425575313773754736020
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.28093395453204825652991295767792673547993183460607315033550049145126308818161
Short name T310
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.16 seconds
Started Nov 22 01:05:44 PM PST 23
Finished Nov 22 01:06:16 PM PST 23
Peak memory 182436 kb
Host smart-5b69cc11-b693-4ed6-9e64-6654398078cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28093395453204825652991295767792673547993183460607315033550049145126308818161 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.rv_timer_disabled.28093395453204825652991295767792673547993183460607315033550049145126308818161
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.93165741833598470882946021759042411768415902909107959707695983431771792885243
Short name T433
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.08 seconds
Started Nov 22 01:05:44 PM PST 23
Finished Nov 22 01:06:59 PM PST 23
Peak memory 182216 kb
Host smart-223cb1aa-9c78-411b-ba5c-956e55d908f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93165741833598470882946021759042411768415902909107959707695983431771792885243 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.93165741833598470882946021759042411768415902909107959707695983431771792885243
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.29032165355023834488789635297205546665731443612270612992851792448520497428397
Short name T295
Test name
Test status
Simulation time 60703901037 ps
CPU time 302.45 seconds
Started Nov 22 01:05:36 PM PST 23
Finished Nov 22 01:10:41 PM PST 23
Peak memory 191196 kb
Host smart-0c24f056-325b-4ebc-bae9-951ef859188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29032165355023834488789635297205546665731443612270612992851792448520497428397 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rv_timer_random_reset.29032165355023834488789635297205546665731443612270612992851792448520497428397
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.25218002663129396864648331526258748925122681132590528797155039418747131101865
Short name T93
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1604.43 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:32:34 PM PST 23
Peak memory 191204 kb
Host smart-a5e0232e-1a72-4213-913a-3c8e9b77a47d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25218002663129396864648331526258748925122681132590528797155039418747131101865 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.25218002663129396864648331526258748925122681132590528797155039418747131101865
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.31377390290083118769632805775817106360695822474542866977576294006390636837974
Short name T454
Test name
Test status
Simulation time 207522994332 ps
CPU time 789.22 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 199104 kb
Host smart-1ca56fe1-d9d0-45b2-89da-86946d6fa33d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137739029008311876963
2805775817106360695822474542866977576294006390636837974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_res
et.31377390290083118769632805775817106360695822474542866977576294006390636837974
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.635856403138967615005323689725626156671310547042639762661035929424462089023
Short name T583
Test name
Test status
Simulation time 544575976458 ps
CPU time 611.37 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:15:59 PM PST 23
Peak memory 183036 kb
Host smart-09142fd5-e2ef-40fe-8edd-045b86898bdf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635856403138967615005323689725626156671310547042639762661035929424462089023
-assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.635856403138967615005323689725626156671310547042639
762661035929424462089023
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.100197975357743740735720446928577847847650213050652291323136928342630370620472
Short name T579
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.61 seconds
Started Nov 22 01:05:44 PM PST 23
Finished Nov 22 01:06:17 PM PST 23
Peak memory 183080 kb
Host smart-38899171-9e6c-43b8-b9c9-608d6b5fbd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100197975357743740735720446928577847847650213050652291323136928342630370620472 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.rv_timer_disabled.100197975357743740735720446928577847847650213050652291323136928342630370620472
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.13267039632761231883657937423580563389086611791126779706018647432716996077370
Short name T70
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.59 seconds
Started Nov 22 01:05:40 PM PST 23
Finished Nov 22 01:06:54 PM PST 23
Peak memory 183044 kb
Host smart-02e25e8b-d956-45c4-9560-e69d150ebd67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267039632761231883657937423580563389086611791126779706018647432716996077370 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.13267039632761231883657937423580563389086611791126779706018647432716996077370
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.70130736792453383504250601600669345219512389640979431429789844976961807034787
Short name T368
Test name
Test status
Simulation time 60703901037 ps
CPU time 297.05 seconds
Started Nov 22 01:05:43 PM PST 23
Finished Nov 22 01:10:43 PM PST 23
Peak memory 191280 kb
Host smart-4e32d0bb-7ad4-4bef-b768-b18a0a279072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70130736792453383504250601600669345219512389640979431429789844976961807034787 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rv_timer_random_reset.70130736792453383504250601600669345219512389640979431429789844976961807034787
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.10629727474276598700109537121028374612759473051355543282732221043595462076784
Short name T380
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1606.78 seconds
Started Nov 22 01:05:40 PM PST 23
Finished Nov 22 01:32:28 PM PST 23
Peak memory 191180 kb
Host smart-1f9fd833-3678-47f8-8fa4-7855451531f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629727474276598700109537121028374612759473051355543282732221043595462076784 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.10629727474276598700109537121028374612759473051355543282732221043595462076784
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.32389987661533321643167573381878917418413769072727236343328263727578170632783
Short name T448
Test name
Test status
Simulation time 207522994332 ps
CPU time 793.71 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 199104 kb
Host smart-f1294ba5-28cd-45b9-a93c-7338ba96de6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238998766153332164316
7573381878917418413769072727236343328263727578170632783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_res
et.32389987661533321643167573381878917418413769072727236343328263727578170632783
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.44869418873638167403144241219228771379806008333644770479540353242894561080821
Short name T619
Test name
Test status
Simulation time 544575976458 ps
CPU time 596.43 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:15:53 PM PST 23
Peak memory 183020 kb
Host smart-450547f8-82c4-4a04-839b-516e00b54524
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4486941887363816740314424121922877137980600833364477047954035324289456108082
1 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.4486941887363816740314424121922877137980600833364
4770479540353242894561080821
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.41362603363701037972729580913251723041065852666436143280905794666136575540735
Short name T522
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.44 seconds
Started Nov 22 01:05:39 PM PST 23
Finished Nov 22 01:06:11 PM PST 23
Peak memory 183084 kb
Host smart-5e537bc6-b304-4d0a-b457-e328fac149a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41362603363701037972729580913251723041065852666436143280905794666136575540735 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.rv_timer_disabled.41362603363701037972729580913251723041065852666436143280905794666136575540735
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.111751341633627676082283185978009680211614736956274993305366013081367068397474
Short name T462
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.71 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:07:09 PM PST 23
Peak memory 183044 kb
Host smart-132c59b4-7a4b-4177-adb0-f976678c9afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111751341633627676082283185978009680211614736956274993305366013081367068397474 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.111751341633627676082283185978009680211614736956274993305366013081367068397474
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.51305756730354867391790737232069375509784693377961379211067391567845289642414
Short name T363
Test name
Test status
Simulation time 60703901037 ps
CPU time 286.25 seconds
Started Nov 22 01:05:46 PM PST 23
Finished Nov 22 01:10:36 PM PST 23
Peak memory 191264 kb
Host smart-1fa2dc25-4b5f-4773-942b-b5e67b14011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51305756730354867391790737232069375509784693377961379211067391567845289642414 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rv_timer_random_reset.51305756730354867391790737232069375509784693377961379211067391567845289642414
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.66464252247717918295700213652037953444244228572556092997051103767404763163296
Short name T529
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1569.82 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:32:06 PM PST 23
Peak memory 191228 kb
Host smart-00288073-97a2-4849-a61e-ce3bef0c8915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66464252247717918295700213652037953444244228572556092997051103767404763163296 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.66464252247717918295700213652037953444244228572556092997051103767404763163296
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.60686492757581923838074195550795346599908201338843667189549640636901169605353
Short name T573
Test name
Test status
Simulation time 207522994332 ps
CPU time 816.53 seconds
Started Nov 22 01:05:42 PM PST 23
Finished Nov 22 01:19:21 PM PST 23
Peak memory 199104 kb
Host smart-9d514325-ea2a-4cf3-a4fa-2cdefaf3f09b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6068649275758192383807
4195550795346599908201338843667189549640636901169605353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_res
et.60686492757581923838074195550795346599908201338843667189549640636901169605353
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.102698018965774985761468075662717454413547757214644368324567312611193084444659
Short name T452
Test name
Test status
Simulation time 544575976458 ps
CPU time 614.26 seconds
Started Nov 22 01:05:48 PM PST 23
Finished Nov 22 01:16:05 PM PST 23
Peak memory 183032 kb
Host smart-3d98fa0a-6adf-46a2-a370-04ddff755520
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026980189657749857614680756627174544135477572146443683245673126111930844446
59 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.102698018965774985761468075662717454413547757214
644368324567312611193084444659
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.54908156638853760651287419101994482342008212742582589133178128047472178249621
Short name T398
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.22 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:06:26 PM PST 23
Peak memory 183060 kb
Host smart-336f5f59-19d6-452e-a38b-85f34b1255cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54908156638853760651287419101994482342008212742582589133178128047472178249621 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.rv_timer_disabled.54908156638853760651287419101994482342008212742582589133178128047472178249621
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.16482727883070227975452900668823706141957439413433673472754383540006664470508
Short name T94
Test name
Test status
Simulation time 70917337186 ps
CPU time 71.96 seconds
Started Nov 22 01:05:54 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 183068 kb
Host smart-345cbe68-5867-49c9-bce4-3d1131a87248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16482727883070227975452900668823706141957439413433673472754383540006664470508 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.16482727883070227975452900668823706141957439413433673472754383540006664470508
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.24661839177148828472808850922229438779238421795427965936028435280427968375571
Short name T419
Test name
Test status
Simulation time 60703901037 ps
CPU time 304.49 seconds
Started Nov 22 01:05:42 PM PST 23
Finished Nov 22 01:10:49 PM PST 23
Peak memory 191256 kb
Host smart-85562b78-190a-4248-b5e7-35245690ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24661839177148828472808850922229438779238421795427965936028435280427968375571 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rv_timer_random_reset.24661839177148828472808850922229438779238421795427965936028435280427968375571
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.94978808170825070860636318631111470492372931990754511328171551455975404085288
Short name T350
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1614.86 seconds
Started Nov 22 01:05:42 PM PST 23
Finished Nov 22 01:32:39 PM PST 23
Peak memory 191164 kb
Host smart-6e555a44-94ec-4652-9247-8a88657a9846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94978808170825070860636318631111470492372931990754511328171551455975404085288 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.94978808170825070860636318631111470492372931990754511328171551455975404085288
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.129573044899106645673991670474242649666980024718027164409033410426574930521
Short name T551
Test name
Test status
Simulation time 207522994332 ps
CPU time 822.98 seconds
Started Nov 22 01:05:49 PM PST 23
Finished Nov 22 01:19:33 PM PST 23
Peak memory 199076 kb
Host smart-6d27be03-0353-4aa8-910d-37e34c5c8d0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295730448991066456739
91670474242649666980024718027164409033410426574930521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset
.129573044899106645673991670474242649666980024718027164409033410426574930521
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.95631040139368526594617567094202448540434505503279516492070383161624371498306
Short name T300
Test name
Test status
Simulation time 544575976458 ps
CPU time 601.59 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:15:58 PM PST 23
Peak memory 183020 kb
Host smart-7402a514-f882-4320-a6db-3b54cca1b2ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9563104013936852659461756709420244854043450550327951649207038316162437149830
6 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.9563104013936852659461756709420244854043450550327
9516492070383161624371498306
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2746307858959224217111877759035030011757248842713795161273961583695249497809
Short name T263
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.08 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:06:26 PM PST 23
Peak memory 183052 kb
Host smart-05b8c4c1-cecc-42b1-b956-34cda0eddd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746307858959224217111877759035030011757248842713795161273961583695249497809 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.rv_timer_disabled.2746307858959224217111877759035030011757248842713795161273961583695249497809
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.33584505200128866937993038600228481228347455839652804637023599306907702159584
Short name T69
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.66 seconds
Started Nov 22 01:05:41 PM PST 23
Finished Nov 22 01:06:55 PM PST 23
Peak memory 182960 kb
Host smart-bf7544af-d7cc-463b-a209-e76cd3f461c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584505200128866937993038600228481228347455839652804637023599306907702159584 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.33584505200128866937993038600228481228347455839652804637023599306907702159584
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.86762265870222028002282848336644088424624621038747202063521833654596559732723
Short name T361
Test name
Test status
Simulation time 60703901037 ps
CPU time 301.31 seconds
Started Nov 22 01:05:43 PM PST 23
Finished Nov 22 01:10:47 PM PST 23
Peak memory 191288 kb
Host smart-8bc76238-51d5-473d-a5f2-eade8fb0d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86762265870222028002282848336644088424624621038747202063521833654596559732723 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rv_timer_random_reset.86762265870222028002282848336644088424624621038747202063521833654596559732723
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.52282969230953951146404564614228878675231690751308259053304919135017901280004
Short name T346
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1611.8 seconds
Started Nov 22 01:05:46 PM PST 23
Finished Nov 22 01:32:41 PM PST 23
Peak memory 191264 kb
Host smart-dd05b2cd-9f4b-40a2-a951-b3d33b3d8949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52282969230953951146404564614228878675231690751308259053304919135017901280004 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.52282969230953951146404564614228878675231690751308259053304919135017901280004
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.79060262738434031853134440583356837479124439715116754480563664051679350473045
Short name T408
Test name
Test status
Simulation time 207522994332 ps
CPU time 802.58 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:19:21 PM PST 23
Peak memory 199104 kb
Host smart-99094ff6-edfa-4130-842c-af9e0ad0f467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7906026273843403185313
4440583356837479124439715116754480563664051679350473045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_res
et.79060262738434031853134440583356837479124439715116754480563664051679350473045
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.35573708120264951581927828868943234803939802572612557256491279119934581168778
Short name T301
Test name
Test status
Simulation time 544575976458 ps
CPU time 609.05 seconds
Started Nov 22 01:05:41 PM PST 23
Finished Nov 22 01:15:51 PM PST 23
Peak memory 183056 kb
Host smart-1e604cf7-c46b-4d55-b797-f2c8ac2bdf05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557370812026495158192782886894323480393980257261255725649127911993458116877
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3557370812026495158192782886894323480393980257261
2557256491279119934581168778
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.85518948666817673207879801683900837304410741374185584844182960653792190001935
Short name T585
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.14 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:06:17 PM PST 23
Peak memory 183084 kb
Host smart-6b757637-de5d-4415-ad62-a939e05cd856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85518948666817673207879801683900837304410741374185584844182960653792190001935 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.rv_timer_disabled.85518948666817673207879801683900837304410741374185584844182960653792190001935
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.61733430438837214119058419183389940027245882928894036940272736187077098928550
Short name T281
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.01 seconds
Started Nov 22 01:05:46 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183020 kb
Host smart-4f356373-dcd8-4d84-86a7-7e07f3abcbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61733430438837214119058419183389940027245882928894036940272736187077098928550 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.61733430438837214119058419183389940027245882928894036940272736187077098928550
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.37113369252886520555042652768852920972434043773650281388119364271749207311036
Short name T417
Test name
Test status
Simulation time 60703901037 ps
CPU time 295.36 seconds
Started Nov 22 01:05:46 PM PST 23
Finished Nov 22 01:10:44 PM PST 23
Peak memory 191288 kb
Host smart-e120d76d-0a25-4e25-88cf-b9980508e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37113369252886520555042652768852920972434043773650281388119364271749207311036 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.rv_timer_random_reset.37113369252886520555042652768852920972434043773650281388119364271749207311036
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.101624339331439001793612312112312989246984014664288082647329258890891977109105
Short name T389
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1578.91 seconds
Started Nov 22 01:05:54 PM PST 23
Finished Nov 22 01:32:14 PM PST 23
Peak memory 191228 kb
Host smart-a0eaa88f-bb84-437a-bee3-7c47521a8e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101624339331439001793612312112312989246984014664288082647329258890891977109105 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.101624339331439001793612312112312989246984014664288082647329258890891977109105
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.35553666629790290994647475514207958111445358017365553954552906604756905369940
Short name T31
Test name
Test status
Simulation time 207522994332 ps
CPU time 811.22 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:19:20 PM PST 23
Peak memory 199096 kb
Host smart-6fbbc253-4c57-433d-a5b1-7635aa957fa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555366662979029099464
7475514207958111445358017365553954552906604756905369940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_res
et.35553666629790290994647475514207958111445358017365553954552906604756905369940
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.63249944833120064599578298212169519061317761558041797646544237493903032510188
Short name T287
Test name
Test status
Simulation time 544575976458 ps
CPU time 616.26 seconds
Started Nov 22 01:04:08 PM PST 23
Finished Nov 22 01:14:29 PM PST 23
Peak memory 183040 kb
Host smart-7cf5993d-8c7a-44c8-ad45-f2fa06763a86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6324994483312006459957829821216951906131776155804179764654423749390303251018
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.63249944833120064599578298212169519061317761558041
797646544237493903032510188
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.9499526920029605979793664782833603670497144964060960845263074124143334103594
Short name T334
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.17 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:04:44 PM PST 23
Peak memory 183064 kb
Host smart-770ea447-e33a-4645-8794-a5f89c62ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9499526920029605979793664782833603670497144964060960845263074124143334103594 -assert nopostproc +UVM_TESTNAME=rv_timer_b
ase_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.rv_timer_disabled.9499526920029605979793664782833603670497144964060960845263074124143334103594
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.22476574258151353114219271940852333647903107151940902149735964263942529516091
Short name T450
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.53 seconds
Started Nov 22 01:03:58 PM PST 23
Finished Nov 22 01:05:21 PM PST 23
Peak memory 183032 kb
Host smart-e7f62d45-5331-4d88-99d3-9c8d3db58a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22476574258151353114219271940852333647903107151940902149735964263942529516091 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.22476574258151353114219271940852333647903107151940902149735964263942529516091
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.105953923034553025511471145481763992567329162747741968207478662339507345568060
Short name T358
Test name
Test status
Simulation time 60703901037 ps
CPU time 297.82 seconds
Started Nov 22 01:04:08 PM PST 23
Finished Nov 22 01:09:11 PM PST 23
Peak memory 191280 kb
Host smart-45b21ce0-8125-41b3-8ab0-301dded667a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105953923034553025511471145481763992567329162747741968207478662339507345568060 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.rv_timer_random_reset.105953923034553025511471145481763992567329162747741968207478662339507345568060
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.37442026726149531899661431463895669900666424610271622038161391622086778774108
Short name T563
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1625.52 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:31:19 PM PST 23
Peak memory 191188 kb
Host smart-959cf0d2-ca1a-4d2e-a715-684b6a5c51bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37442026726149531899661431463895669900666424610271622038161391622086778774108 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.37442026726149531899661431463895669900666424610271622038161391622086778774108
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.7939991363574425641887057445199741763808507491918064012551324350186605658335
Short name T435
Test name
Test status
Simulation time 207522994332 ps
CPU time 807.52 seconds
Started Nov 22 01:04:15 PM PST 23
Finished Nov 22 01:17:43 PM PST 23
Peak memory 199096 kb
Host smart-48a7ff4e-1fa8-4775-86e7-929555c5aaa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7939991363574425641887
057445199741763808507491918064012551324350186605658335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset
.7939991363574425641887057445199741763808507491918064012551324350186605658335
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.64311870945116293190572539141020651220579387679416454124671879308474826782000
Short name T90
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.65 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 183068 kb
Host smart-10d0b749-73ec-4fe3-91af-6c00b197f354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64311870945116293190572539141020651220579387679416454124671879308474826782000 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.64311870945116293190572539141020651220579387679416454124671879308474826782000
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.18669055653096774261152931543157138610770053968458199744124684946496531729838
Short name T608
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.68 seconds
Started Nov 22 01:05:48 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183056 kb
Host smart-240e62ac-aac0-49fd-8481-543e557e51c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669055653096774261152931543157138610770053968458199744124684946496531729838 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.18669055653096774261152931543157138610770053968458199744124684946496531729838
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.112926951400824422659463368013038161549083348401781896447169769910301846584746
Short name T314
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.82 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:07:00 PM PST 23
Peak memory 183088 kb
Host smart-a94665b5-28dd-43f5-850b-3f156c51e850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112926951400824422659463368013038161549083348401781896447169769910301846584746 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.112926951400824422659463368013038161549083348401781896447169769910301846584746
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.7519626880121830571910889888538770063125314879981213997289226959445033815063
Short name T256
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.1 seconds
Started Nov 22 01:05:54 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 183068 kb
Host smart-14cf0e67-6c9a-4d86-97c3-ba6b72053f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7519626880121830571910889888538770063125314879981213997289226959445033815063 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.7519626880121830571910889888538770063125314879981213997289226959445033815063
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.21159552183019069251297768947216062207446532500961220841772608733406011624056
Short name T558
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.99 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:07:03 PM PST 23
Peak memory 183008 kb
Host smart-e3409e19-1935-48b7-8957-f9ba3badf8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21159552183019069251297768947216062207446532500961220841772608733406011624056 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.21159552183019069251297768947216062207446532500961220841772608733406011624056
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.26820164996525976038254130998071263924106126374841739001275286409250757526362
Short name T305
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.09 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183068 kb
Host smart-3fb5d5a2-d09f-4458-87e6-23af491d6c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26820164996525976038254130998071263924106126374841739001275286409250757526362 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.26820164996525976038254130998071263924106126374841739001275286409250757526362
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.30555364625241139863036071657631714881677696612885805377258101641874113304402
Short name T237
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.14 seconds
Started Nov 22 01:05:49 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183056 kb
Host smart-50ea1fb4-fef6-4a6e-975f-904e93744bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555364625241139863036071657631714881677696612885805377258101641874113304402 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.30555364625241139863036071657631714881677696612885805377258101641874113304402
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.89103808155966387919290368658634351054322870218629496447227769768920410919703
Short name T95
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.71 seconds
Started Nov 22 01:05:49 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 182992 kb
Host smart-b55b779f-4ded-4621-8372-222583070c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89103808155966387919290368658634351054322870218629496447227769768920410919703 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.89103808155966387919290368658634351054322870218629496447227769768920410919703
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.76761846604403686606128000734048614059632808138859211771964641807315643580743
Short name T424
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.06 seconds
Started Nov 22 01:05:49 PM PST 23
Finished Nov 22 01:07:05 PM PST 23
Peak memory 183000 kb
Host smart-459a844b-1628-451a-a741-19c8bc007ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76761846604403686606128000734048614059632808138859211771964641807315643580743 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.76761846604403686606128000734048614059632808138859211771964641807315643580743
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.108505740752255188028145402901064531321452341846630603779503952020288128105015
Short name T259
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.26 seconds
Started Nov 22 01:05:57 PM PST 23
Finished Nov 22 01:07:12 PM PST 23
Peak memory 183064 kb
Host smart-7e8b3660-6c3a-449b-b8ea-f5086d28f9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108505740752255188028145402901064531321452341846630603779503952020288128105015 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.108505740752255188028145402901064531321452341846630603779503952020288128105015
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.101915876919071451825538162117569546081650392334728520129776577599821099430760
Short name T64
Test name
Test status
Simulation time 544575976458 ps
CPU time 610.9 seconds
Started Nov 22 01:04:12 PM PST 23
Finished Nov 22 01:14:25 PM PST 23
Peak memory 183008 kb
Host smart-0d6c1541-acee-4e59-9313-3594abc792fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019158769190714518255381621175695460816503923347285201297765775998210994307
60 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.1019158769190714518255381621175695460816503923347
28520129776577599821099430760
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.32721469496909431790679416241223700366377855298739572977203173318078887294499
Short name T601
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.58 seconds
Started Nov 22 01:03:56 PM PST 23
Finished Nov 22 01:04:28 PM PST 23
Peak memory 183056 kb
Host smart-44561afa-9814-467a-8af2-a2bc706b7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32721469496909431790679416241223700366377855298739572977203173318078887294499 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.rv_timer_disabled.32721469496909431790679416241223700366377855298739572977203173318078887294499
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.90962642616842428676202077637068113258039823700643931980190749830715106409802
Short name T21
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.46 seconds
Started Nov 22 01:04:03 PM PST 23
Finished Nov 22 01:05:22 PM PST 23
Peak memory 182772 kb
Host smart-22f300e6-24c7-412e-adff-a2839e8ecd87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90962642616842428676202077637068113258039823700643931980190749830715106409802 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.90962642616842428676202077637068113258039823700643931980190749830715106409802
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.78036578626683630433559478925892034166514304976290641972307161816806250195043
Short name T609
Test name
Test status
Simulation time 60703901037 ps
CPU time 296.3 seconds
Started Nov 22 01:04:07 PM PST 23
Finished Nov 22 01:09:09 PM PST 23
Peak memory 191276 kb
Host smart-51ac7ca1-ad55-40f7-befa-890924fb8f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78036578626683630433559478925892034166514304976290641972307161816806250195043 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.rv_timer_random_reset.78036578626683630433559478925892034166514304976290641972307161816806250195043
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.107580562912892503129439472253476951997342276493337242218683746862360204941617
Short name T365
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1604.99 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:30:59 PM PST 23
Peak memory 191176 kb
Host smart-a346a7ca-8e79-4346-ae0c-cb86f119b030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107580562912892503129439472253476951997342276493337242218683746862360204941617 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.107580562912892503129439472253476951997342276493337242218683746862360204941617
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.31111811833552315170823928900555156193004565521306238547429748903045015058232
Short name T29
Test name
Test status
Simulation time 207522994332 ps
CPU time 805.84 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:17:39 PM PST 23
Peak memory 199140 kb
Host smart-1ab3f550-5aa5-43f6-b8bf-8c066f2e1730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111181183355231517082
3928900555156193004565521306238547429748903045015058232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_rese
t.31111811833552315170823928900555156193004565521306238547429748903045015058232
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.12132247417441703254727535005789773483415524642161853144537009429586413079609
Short name T613
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.09 seconds
Started Nov 22 01:05:50 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183036 kb
Host smart-d9ff109a-0d90-4654-8101-22a6cc43b280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132247417441703254727535005789773483415524642161853144537009429586413079609 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.12132247417441703254727535005789773483415524642161853144537009429586413079609
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.101917232043451460589689157339932300727134910180606610439716839239386247737868
Short name T345
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.15 seconds
Started Nov 22 01:05:50 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183060 kb
Host smart-9af0ff6b-33c4-4456-ae07-635207516d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101917232043451460589689157339932300727134910180606610439716839239386247737868 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.101917232043451460589689157339932300727134910180606610439716839239386247737868
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.29809983144309547225485055638693767114147694152930826687983323712949665402382
Short name T445
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.46 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:07:02 PM PST 23
Peak memory 183084 kb
Host smart-ebc49830-1d7f-43ee-8b7f-715f6fca6b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809983144309547225485055638693767114147694152930826687983323712949665402382 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.29809983144309547225485055638693767114147694152930826687983323712949665402382
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.37082294828696046826450862816008181030759463170943200980699629172368490672960
Short name T67
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.41 seconds
Started Nov 22 01:05:44 PM PST 23
Finished Nov 22 01:06:58 PM PST 23
Peak memory 183044 kb
Host smart-06bf9ecd-604a-461d-adde-a9941e541f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082294828696046826450862816008181030759463170943200980699629172368490672960 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.37082294828696046826450862816008181030759463170943200980699629172368490672960
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.24996298408697498343911126864234990278479369569547294711060323554576580146551
Short name T410
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.12 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 182960 kb
Host smart-da6ad92b-d5c1-4c27-bf45-8081c72c7bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24996298408697498343911126864234990278479369569547294711060323554576580146551 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.24996298408697498343911126864234990278479369569547294711060323554576580146551
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.44545881650626909920530105487128656440183674363983556445961017119581066533215
Short name T407
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.67 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:07:02 PM PST 23
Peak memory 182980 kb
Host smart-959cbc2c-9051-40d2-99ab-196015eb4c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44545881650626909920530105487128656440183674363983556445961017119581066533215 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.44545881650626909920530105487128656440183674363983556445961017119581066533215
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.19791138183926175074922909814766226801689536786252487225465964912591209581289
Short name T571
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.92 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:07:03 PM PST 23
Peak memory 182940 kb
Host smart-ccb7f2e8-c33c-4592-a995-070ab62bbf63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19791138183926175074922909814766226801689536786252487225465964912591209581289 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.19791138183926175074922909814766226801689536786252487225465964912591209581289
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.106646122947304410268884898872488641242977054423638919122344574065440100008883
Short name T437
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.12 seconds
Started Nov 22 01:05:49 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 182952 kb
Host smart-fda65a29-d036-436f-9635-cd8ed6017bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106646122947304410268884898872488641242977054423638919122344574065440100008883 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.106646122947304410268884898872488641242977054423638919122344574065440100008883
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.92653883532016850449638095172504891571359742299106812750406072260092826090527
Short name T475
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.21 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:05 PM PST 23
Peak memory 182960 kb
Host smart-d996353d-65c7-4f2d-b0e3-f846be9ff53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92653883532016850449638095172504891571359742299106812750406072260092826090527 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.92653883532016850449638095172504891571359742299106812750406072260092826090527
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.90072450194066846446206734688657144221726547452328548886813179655300696827314
Short name T507
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.87 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183020 kb
Host smart-f2d305f9-d223-4e90-a29d-d6201f5d288f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90072450194066846446206734688657144221726547452328548886813179655300696827314 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.90072450194066846446206734688657144221726547452328548886813179655300696827314
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.103920662027624710642209258733966022624502312673975667145995765394256730933070
Short name T526
Test name
Test status
Simulation time 544575976458 ps
CPU time 601.57 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:14:15 PM PST 23
Peak memory 182972 kb
Host smart-08b8bdba-9551-4410-82ab-1c42072b91c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039206620276247106422092587339660226245023126739756671459957653942567309330
70 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.1039206620276247106422092587339660226245023126739
75667145995765394256730933070
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.87059281799524585545638864429461879467044386596435490348334088314902741296333
Short name T493
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.3 seconds
Started Nov 22 01:04:11 PM PST 23
Finished Nov 22 01:04:44 PM PST 23
Peak memory 183032 kb
Host smart-f1ee5d36-379d-4bc0-bab3-5c549e470497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87059281799524585545638864429461879467044386596435490348334088314902741296333 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.rv_timer_disabled.87059281799524585545638864429461879467044386596435490348334088314902741296333
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.76210142208159639744243142892048560221441793670200649300753046476012435686087
Short name T531
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.24 seconds
Started Nov 22 01:04:03 PM PST 23
Finished Nov 22 01:05:21 PM PST 23
Peak memory 182944 kb
Host smart-9c06c357-6fef-40e9-ba9d-70c1af563fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76210142208159639744243142892048560221441793670200649300753046476012435686087 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.76210142208159639744243142892048560221441793670200649300753046476012435686087
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.61523199449899146415779342360935719197946577416478114686214642760311089369062
Short name T545
Test name
Test status
Simulation time 60703901037 ps
CPU time 290.22 seconds
Started Nov 22 01:04:11 PM PST 23
Finished Nov 22 01:09:04 PM PST 23
Peak memory 191264 kb
Host smart-557e9c2b-d5d2-41c3-ae1e-67255291ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61523199449899146415779342360935719197946577416478114686214642760311089369062 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.rv_timer_random_reset.61523199449899146415779342360935719197946577416478114686214642760311089369062
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.80510557071706069594285963129591063640788021993437014259394423447536405599579
Short name T536
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1586.29 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:30:40 PM PST 23
Peak memory 191180 kb
Host smart-2feb0e3b-0874-4e28-b36b-addd20aebeae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80510557071706069594285963129591063640788021993437014259394423447536405599579 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.80510557071706069594285963129591063640788021993437014259394423447536405599579
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.9339223042869557901507016256718273683062156811018305372056028007365431676697
Short name T479
Test name
Test status
Simulation time 207522994332 ps
CPU time 819.5 seconds
Started Nov 22 01:04:07 PM PST 23
Finished Nov 22 01:17:52 PM PST 23
Peak memory 199120 kb
Host smart-ae13b610-470d-4ae9-97ef-fde7e6ce1f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9339223042869557901507
016256718273683062156811018305372056028007365431676697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset
.9339223042869557901507016256718273683062156811018305372056028007365431676697
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.63858518974780765669681859969854595156346832710495902047336674144814913069307
Short name T359
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.41 seconds
Started Nov 22 01:05:45 PM PST 23
Finished Nov 22 01:07:01 PM PST 23
Peak memory 183084 kb
Host smart-d5005d29-3731-488b-8d02-c5d584105d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63858518974780765669681859969854595156346832710495902047336674144814913069307 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.63858518974780765669681859969854595156346832710495902047336674144814913069307
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.75515878107678388772852037136276910773610712073013351217375699351584021330600
Short name T84
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.59 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:07:09 PM PST 23
Peak memory 182984 kb
Host smart-bd3b1520-60c4-4b73-8170-a4b53e9e31c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75515878107678388772852037136276910773610712073013351217375699351584021330600 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.75515878107678388772852037136276910773610712073013351217375699351584021330600
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.22906538134088112221044998231151248827519955246585146359730447519361087625832
Short name T599
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.52 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:07:03 PM PST 23
Peak memory 183072 kb
Host smart-3d14e9e5-3e9d-48a8-8479-5fca0c168938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22906538134088112221044998231151248827519955246585146359730447519361087625832 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.22906538134088112221044998231151248827519955246585146359730447519361087625832
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.110354865233618640077563581653042172831136260110436677166062914676618013878889
Short name T24
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.19 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 183064 kb
Host smart-71ac35f7-4be5-48f5-bd9f-93151a283534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110354865233618640077563581653042172831136260110436677166062914676618013878889 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.110354865233618640077563581653042172831136260110436677166062914676618013878889
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.304837802819745252690640973331355158479769792821501290951314153900546258494
Short name T596
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.29 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:06 PM PST 23
Peak memory 183068 kb
Host smart-18a36b3e-27b1-443e-8c4b-f0460fc6b527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304837802819745252690640973331355158479769792821501290951314153900546258494 -assert nopostp
roc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.304837802819745252690640973331355158479769792821501290951314153900546258494
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.109514215387785951463861078243560607733961674401917777882963756800391259912891
Short name T436
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.1 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:06 PM PST 23
Peak memory 183064 kb
Host smart-a1c52a39-2122-4fa0-8dde-0d83b3e0916d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109514215387785951463861078243560607733961674401917777882963756800391259912891 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.109514215387785951463861078243560607733961674401917777882963756800391259912891
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.55095220533298635710507509520814548857572151055115297984050945460384745722681
Short name T488
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.24 seconds
Started Nov 22 01:05:47 PM PST 23
Finished Nov 22 01:07:04 PM PST 23
Peak memory 183020 kb
Host smart-448d27d9-c6bd-4405-9185-3918d63ab8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55095220533298635710507509520814548857572151055115297984050945460384745722681 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.55095220533298635710507509520814548857572151055115297984050945460384745722681
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.24986159694799212374083996290302570454091634694638691888260428701723830478217
Short name T23
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.04 seconds
Started Nov 22 01:05:46 PM PST 23
Finished Nov 22 01:07:03 PM PST 23
Peak memory 183020 kb
Host smart-bbb68397-fac1-432d-842e-dfc01bc59d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24986159694799212374083996290302570454091634694638691888260428701723830478217 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.24986159694799212374083996290302570454091634694638691888260428701723830478217
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.11922012856612057677047007774322203534034078285906242497937917744673195293330
Short name T364
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.45 seconds
Started Nov 22 01:05:50 PM PST 23
Finished Nov 22 01:07:03 PM PST 23
Peak memory 183056 kb
Host smart-42d3a747-a5e2-43c8-86c5-39b182edd070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11922012856612057677047007774322203534034078285906242497937917744673195293330 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.11922012856612057677047007774322203534034078285906242497937917744673195293330
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.88816741894182977748048618000419711752642354013939985564612295877394285721091
Short name T614
Test name
Test status
Simulation time 70917337186 ps
CPU time 71.76 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183068 kb
Host smart-a37a2cc0-f695-4a85-ab77-397e1383c2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88816741894182977748048618000419711752642354013939985564612295877394285721091 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.88816741894182977748048618000419711752642354013939985564612295877394285721091
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.66643562437336592226879333344492062512057494335818179211734159226372171048277
Short name T63
Test name
Test status
Simulation time 544575976458 ps
CPU time 614.33 seconds
Started Nov 22 01:04:07 PM PST 23
Finished Nov 22 01:14:27 PM PST 23
Peak memory 183024 kb
Host smart-c04cf6d3-79a7-4526-b90a-b84e13cb6638
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6664356243733659222687933334449206251205749433581817921173415922637217104827
7 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.66643562437336592226879333344492062512057494335818
179211734159226372171048277
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.84015864866541492559609612690717319790991122312866220410470189704029090250959
Short name T296
Test name
Test status
Simulation time 32101379859 ps
CPU time 29.89 seconds
Started Nov 22 01:03:58 PM PST 23
Finished Nov 22 01:04:37 PM PST 23
Peak memory 183044 kb
Host smart-27bd97f0-9c90-45c6-a703-904b0e19f9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84015864866541492559609612690717319790991122312866220410470189704029090250959 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.rv_timer_disabled.84015864866541492559609612690717319790991122312866220410470189704029090250959
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.98900748135775025025057852301645678242121806597442194374743829765710611843603
Short name T427
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.41 seconds
Started Nov 22 01:04:01 PM PST 23
Finished Nov 22 01:05:22 PM PST 23
Peak memory 183060 kb
Host smart-3455c0cb-f81d-49e4-88ec-7be30eb1d6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98900748135775025025057852301645678242121806597442194374743829765710611843603 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.98900748135775025025057852301645678242121806597442194374743829765710611843603
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.43628665046323571936015071513643321928041845297623521583567991950745835089748
Short name T430
Test name
Test status
Simulation time 60703901037 ps
CPU time 297.53 seconds
Started Nov 22 01:04:07 PM PST 23
Finished Nov 22 01:09:10 PM PST 23
Peak memory 191276 kb
Host smart-b7eef216-bdf1-4fff-9a3a-4d5d0083d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43628665046323571936015071513643321928041845297623521583567991950745835089748 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rv_timer_random_reset.43628665046323571936015071513643321928041845297623521583567991950745835089748
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.89302482124641921661770907274089075177617922352636916780700270906867304045699
Short name T248
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1614.58 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:31:08 PM PST 23
Peak memory 191228 kb
Host smart-d7b6d305-0cc9-40ba-8ef6-2ec3bd13e73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89302482124641921661770907274089075177617922352636916780700270906867304045699 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.89302482124641921661770907274089075177617922352636916780700270906867304045699
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.10650238042012215872644750987825154931947170511352122961123831885154960764007
Short name T405
Test name
Test status
Simulation time 207522994332 ps
CPU time 824.08 seconds
Started Nov 22 01:04:08 PM PST 23
Finished Nov 22 01:17:58 PM PST 23
Peak memory 199104 kb
Host smart-62992956-5693-40ba-ba09-a002f68c604a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065023804201221587264
4750987825154931947170511352122961123831885154960764007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_rese
t.10650238042012215872644750987825154931947170511352122961123831885154960764007
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.15034803434759688867106826926577897508690045603367891442055246036263460523327
Short name T251
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.04 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183068 kb
Host smart-fcbc13e1-44b6-441c-baae-1bc7c44113c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15034803434759688867106826926577897508690045603367891442055246036263460523327 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.15034803434759688867106826926577897508690045603367891442055246036263460523327
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.80385598082223253292631270271523375753075380067993441138434640645207814918799
Short name T87
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.76 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:05 PM PST 23
Peak memory 183056 kb
Host smart-761e346d-1d80-4cde-a672-7c7292be088c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80385598082223253292631270271523375753075380067993441138434640645207814918799 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.80385598082223253292631270271523375753075380067993441138434640645207814918799
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.25737263508621374411092431712611503101465330450173951547101006421842113285776
Short name T432
Test name
Test status
Simulation time 70917337186 ps
CPU time 71.79 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 183068 kb
Host smart-bd72d69b-9dae-47b8-882b-73ab73e29b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737263508621374411092431712611503101465330450173951547101006421842113285776 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.25737263508621374411092431712611503101465330450173951547101006421842113285776
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.37618330165527658162964579822650771299300657093806829888761864548098383530783
Short name T85
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.42 seconds
Started Nov 22 01:05:50 PM PST 23
Finished Nov 22 01:07:05 PM PST 23
Peak memory 183056 kb
Host smart-5d1d5c2b-18d5-43a7-b5d0-bfaf838b637a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37618330165527658162964579822650771299300657093806829888761864548098383530783 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.37618330165527658162964579822650771299300657093806829888761864548098383530783
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.26266795673106845263779101107577300484288581810545150281632310457679837576476
Short name T238
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.84 seconds
Started Nov 22 01:05:46 PM PST 23
Finished Nov 22 01:07:02 PM PST 23
Peak memory 183068 kb
Host smart-db58f306-cdee-4933-819a-7fab4787c314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26266795673106845263779101107577300484288581810545150281632310457679837576476 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.26266795673106845263779101107577300484288581810545150281632310457679837576476
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.36839873151363678732296168617545508664948056754595017691407635534436316639812
Short name T321
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.01 seconds
Started Nov 22 01:05:55 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 183068 kb
Host smart-4565e9b5-a6bc-4362-90c7-7f5e66424138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36839873151363678732296168617545508664948056754595017691407635534436316639812 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.36839873151363678732296168617545508664948056754595017691407635534436316639812
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.104436237258731280741522437603447281222935398135909659205931607695815218801607
Short name T396
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.16 seconds
Started Nov 22 01:05:56 PM PST 23
Finished Nov 22 01:07:09 PM PST 23
Peak memory 183016 kb
Host smart-e725fa5b-7636-430c-af79-0dacac0a8198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104436237258731280741522437603447281222935398135909659205931607695815218801607 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.104436237258731280741522437603447281222935398135909659205931607695815218801607
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.30882583958213119399064849357602955911710317219988253982035234996248012146419
Short name T312
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.69 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183036 kb
Host smart-870524f5-7445-4eba-baa1-23c60c2c843f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30882583958213119399064849357602955911710317219988253982035234996248012146419 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.30882583958213119399064849357602955911710317219988253982035234996248012146419
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.56287641986140714741493827412849727302036212714251228546030694158846074945487
Short name T582
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.08 seconds
Started Nov 22 01:05:57 PM PST 23
Finished Nov 22 01:07:12 PM PST 23
Peak memory 183028 kb
Host smart-65cbc9e9-3932-4af4-a4d9-2e2271de7a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56287641986140714741493827412849727302036212714251228546030694158846074945487 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.56287641986140714741493827412849727302036212714251228546030694158846074945487
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.110952987411629259451781030735180358344549680456605268132499430741181297987868
Short name T252
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.28 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183060 kb
Host smart-9c63324e-f821-4679-b663-85a5e996fcc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110952987411629259451781030735180358344549680456605268132499430741181297987868 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.110952987411629259451781030735180358344549680456605268132499430741181297987868
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.34349430127502161769588956638693036877461898003542557950682428654787174039148
Short name T463
Test name
Test status
Simulation time 544575976458 ps
CPU time 615.36 seconds
Started Nov 22 01:04:11 PM PST 23
Finished Nov 22 01:14:29 PM PST 23
Peak memory 182956 kb
Host smart-840251e6-e5ce-438f-9a47-ff4dfaffe150
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434943012750216176958895663869303687746189800354255795068242865478717403914
8 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.34349430127502161769588956638693036877461898003542
557950682428654787174039148
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.53568071819219757302464313528565814718090335329336649883067083377563244324912
Short name T1
Test name
Test status
Simulation time 32101379859 ps
CPU time 30.17 seconds
Started Nov 22 01:04:14 PM PST 23
Finished Nov 22 01:04:45 PM PST 23
Peak memory 183060 kb
Host smart-22afddd9-a77d-4a1b-9b2d-a3014bc27c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53568071819219757302464313528565814718090335329336649883067083377563244324912 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.rv_timer_disabled.53568071819219757302464313528565814718090335329336649883067083377563244324912
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.36368062641192243036022225688320458436812331848119940183002587141098112312024
Short name T541
Test name
Test status
Simulation time 70917337186 ps
CPU time 75.11 seconds
Started Nov 22 01:04:09 PM PST 23
Finished Nov 22 01:05:29 PM PST 23
Peak memory 183040 kb
Host smart-5b746517-4841-42f0-8657-44f88760d7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368062641192243036022225688320458436812331848119940183002587141098112312024 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.36368062641192243036022225688320458436812331848119940183002587141098112312024
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.17955451810268320717564781703981239423243575744475768805073976403033903097970
Short name T37
Test name
Test status
Simulation time 60703901037 ps
CPU time 305.21 seconds
Started Nov 22 01:04:04 PM PST 23
Finished Nov 22 01:09:16 PM PST 23
Peak memory 191292 kb
Host smart-8e13903b-442b-4f9e-b325-d6586d3d8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17955451810268320717564781703981239423243575744475768805073976403033903097970 -assert nopostproc +UVM_TESTNAME=rv_timer_
base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.rv_timer_random_reset.17955451810268320717564781703981239423243575744475768805073976403033903097970
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.53007676655960790105290799861387658065538856125717212985087662562414456692436
Short name T383
Test name
Test status
Simulation time 1048433034855 ps
CPU time 1586.52 seconds
Started Nov 22 01:04:02 PM PST 23
Finished Nov 22 01:30:34 PM PST 23
Peak memory 191212 kb
Host smart-cf643426-e3cf-4f18-b433-d724c92777ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53007676655960790105290799861387658065538856125717212985087662562414456692436 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.53007676655960790105290799861387658065538856125717212985087662562414456692436
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.64053049082654455541446810262037564501291693920442831089530906124847088807879
Short name T4
Test name
Test status
Simulation time 207522994332 ps
CPU time 824.64 seconds
Started Nov 22 01:04:18 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 199104 kb
Host smart-83571e7d-4548-4d08-b2f4-c93aa174d561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6405304908265445554144
6810262037564501291693920442831089530906124847088807879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_rese
t.64053049082654455541446810262037564501291693920442831089530906124847088807879
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.28310121128625994781358054170161944543114099365278398857410916750964070268906
Short name T504
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.08 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:06 PM PST 23
Peak memory 183044 kb
Host smart-f173ae09-20c4-49e3-ade9-4797529d7a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28310121128625994781358054170161944543114099365278398857410916750964070268906 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.28310121128625994781358054170161944543114099365278398857410916750964070268906
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.75745190278010779657540517424007067474671526510699930807093114063164140461960
Short name T434
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.02 seconds
Started Nov 22 01:05:54 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183044 kb
Host smart-bf72fb04-2806-4218-9bac-480709b963f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75745190278010779657540517424007067474671526510699930807093114063164140461960 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.75745190278010779657540517424007067474671526510699930807093114063164140461960
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.64821107293678211386560641240264332442828145303102137851402563948638718868038
Short name T612
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.52 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:06 PM PST 23
Peak memory 183052 kb
Host smart-1756f20e-a5d1-47bd-a683-7425330e1cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64821107293678211386560641240264332442828145303102137851402563948638718868038 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.64821107293678211386560641240264332442828145303102137851402563948638718868038
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.33462660142538579627722092086162828729654980072307573858498651475948809493888
Short name T466
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.4 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:07 PM PST 23
Peak memory 182964 kb
Host smart-9000da0e-1e59-4c24-91f9-623efcf327be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33462660142538579627722092086162828729654980072307573858498651475948809493888 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.33462660142538579627722092086162828729654980072307573858498651475948809493888
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.86581203240493538479544944528561151328143000635870607306553193262019930414255
Short name T483
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.88 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:09 PM PST 23
Peak memory 183072 kb
Host smart-e39873c9-b0f5-4445-b037-3aa873cc7e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86581203240493538479544944528561151328143000635870607306553193262019930414255 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.86581203240493538479544944528561151328143000635870607306553193262019930414255
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.94437103538342008216942045395985603770395543208686470424741583989318815940795
Short name T326
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.45 seconds
Started Nov 22 01:05:53 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 183036 kb
Host smart-a4e513a5-379c-4c4e-993f-ca9e123bdb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94437103538342008216942045395985603770395543208686470424741583989318815940795 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.94437103538342008216942045395985603770395543208686470424741583989318815940795
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.96219091463027751061017673967862485613459110931355482224610390282376793844264
Short name T416
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.97 seconds
Started Nov 22 01:05:51 PM PST 23
Finished Nov 22 01:07:06 PM PST 23
Peak memory 183000 kb
Host smart-f8550ce6-77a3-4eef-a727-114e489dcf79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96219091463027751061017673967862485613459110931355482224610390282376793844264 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.96219091463027751061017673967862485613459110931355482224610390282376793844264
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.101032984899948219260434294290165680140687774570816406268912016257097712044746
Short name T266
Test name
Test status
Simulation time 70917337186 ps
CPU time 72.96 seconds
Started Nov 22 01:05:54 PM PST 23
Finished Nov 22 01:07:08 PM PST 23
Peak memory 182996 kb
Host smart-e6fec59f-2b39-45e9-a49a-57ebf549782c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101032984899948219260434294290165680140687774570816406268912016257097712044746 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.101032984899948219260434294290165680140687774570816406268912016257097712044746
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.5045635656510105437934631012932845782386600420915196983551486471679881064841
Short name T421
Test name
Test status
Simulation time 70917337186 ps
CPU time 74.47 seconds
Started Nov 22 01:06:01 PM PST 23
Finished Nov 22 01:07:16 PM PST 23
Peak memory 183084 kb
Host smart-135c42ac-462d-45cd-9d14-c7b36af5bd70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5045635656510105437934631012932845782386600420915196983551486471679881064841 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.5045635656510105437934631012932845782386600420915196983551486471679881064841
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.46258644699290225063816072183531015026718357852646058608000051298201370333779
Short name T89
Test name
Test status
Simulation time 70917337186 ps
CPU time 73.53 seconds
Started Nov 22 01:06:00 PM PST 23
Finished Nov 22 01:07:15 PM PST 23
Peak memory 183084 kb
Host smart-11226808-2d01-4877-af4a-4535f3974c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46258644699290225063816072183531015026718357852646058608000051298201370333779 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.46258644699290225063816072183531015026718357852646058608000051298201370333779
Directory /workspace/99.rv_timer_random/latest
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