Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 614
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T568 /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.210809334 Dec 20 12:39:46 PM PST 23 Dec 20 12:45:09 PM PST 23 211225850251 ps
T379 /workspace/coverage/default/31.rv_timer_random.3264914175 Dec 20 12:40:00 PM PST 23 Dec 20 12:42:41 PM PST 23 68262338871 ps
T569 /workspace/coverage/default/39.rv_timer_random_reset.1208014158 Dec 20 12:39:46 PM PST 23 Dec 20 12:41:09 PM PST 23 11730244585 ps
T337 /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1241775285 Dec 20 12:39:36 PM PST 23 Dec 20 12:44:05 PM PST 23 37231479886 ps
T253 /workspace/coverage/default/144.rv_timer_random.1703557935 Dec 20 12:40:02 PM PST 23 Dec 20 12:45:35 PM PST 23 819270738744 ps
T570 /workspace/coverage/default/48.rv_timer_disabled.248491134 Dec 20 12:39:59 PM PST 23 Dec 20 12:42:29 PM PST 23 220172632102 ps
T200 /workspace/coverage/default/198.rv_timer_random.2011725505 Dec 20 12:40:40 PM PST 23 Dec 20 12:43:48 PM PST 23 72124213693 ps
T571 /workspace/coverage/default/45.rv_timer_stress_all.1218118739 Dec 20 12:39:53 PM PST 23 Dec 20 12:43:07 PM PST 23 322368193950 ps
T368 /workspace/coverage/default/2.rv_timer_random_reset.3427814275 Dec 20 12:39:20 PM PST 23 Dec 20 12:42:52 PM PST 23 51320835172 ps
T363 /workspace/coverage/default/7.rv_timer_random_reset.3928528254 Dec 20 12:39:19 PM PST 23 Dec 20 12:43:27 PM PST 23 333791496401 ps
T284 /workspace/coverage/default/38.rv_timer_random_reset.795927181 Dec 20 12:40:05 PM PST 23 Dec 20 12:46:41 PM PST 23 107846576796 ps
T572 /workspace/coverage/default/21.rv_timer_stress_all.1320300160 Dec 20 12:39:46 PM PST 23 Dec 20 12:45:33 PM PST 23 322427341970 ps
T146 /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1265204333 Dec 20 12:39:08 PM PST 23 Dec 20 01:00:43 PM PST 23 120917205009 ps
T573 /workspace/coverage/default/27.rv_timer_random.2813002133 Dec 20 12:39:47 PM PST 23 Dec 20 12:41:09 PM PST 23 38172929632 ps
T574 /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2367675032 Dec 20 12:39:31 PM PST 23 Dec 20 12:50:44 PM PST 23 86073091410 ps
T222 /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3209191281 Dec 20 12:39:38 PM PST 23 Dec 20 12:41:06 PM PST 23 67129591395 ps
T373 /workspace/coverage/default/142.rv_timer_random.352009877 Dec 20 12:40:05 PM PST 23 Dec 20 12:45:13 PM PST 23 135254476989 ps
T575 /workspace/coverage/default/78.rv_timer_random.4091287624 Dec 20 12:39:57 PM PST 23 Dec 20 12:41:17 PM PST 23 9931928806 ps
T576 /workspace/coverage/default/19.rv_timer_disabled.3048236 Dec 20 12:39:33 PM PST 23 Dec 20 12:43:07 PM PST 23 208217732523 ps
T577 /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3827845292 Dec 20 12:39:29 PM PST 23 Dec 20 12:47:57 PM PST 23 65340515069 ps
T578 /workspace/coverage/default/34.rv_timer_disabled.1809792987 Dec 20 12:39:35 PM PST 23 Dec 20 12:44:42 PM PST 23 501754492332 ps
T262 /workspace/coverage/default/44.rv_timer_random.3188050401 Dec 20 12:39:34 PM PST 23 Dec 20 12:40:57 PM PST 23 8724808030 ps
T318 /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2651543125 Dec 20 12:39:51 PM PST 23 Dec 20 12:42:35 PM PST 23 108386260660 ps
T362 /workspace/coverage/default/3.rv_timer_random_reset.1518721293 Dec 20 12:40:05 PM PST 23 Dec 20 12:45:11 PM PST 23 327243268897 ps
T375 /workspace/coverage/default/99.rv_timer_random.2904098693 Dec 20 12:40:14 PM PST 23 Dec 20 12:45:03 PM PST 23 260292238405 ps
T233 /workspace/coverage/default/177.rv_timer_random.558529497 Dec 20 12:40:32 PM PST 23 Dec 20 12:47:34 PM PST 23 795034159681 ps
T191 /workspace/coverage/default/190.rv_timer_random.1096443822 Dec 20 12:39:57 PM PST 23 Dec 20 12:56:21 PM PST 23 353420936831 ps
T323 /workspace/coverage/default/137.rv_timer_random.4256789561 Dec 20 12:40:10 PM PST 23 Dec 20 12:59:28 PM PST 23 234144791701 ps
T579 /workspace/coverage/default/172.rv_timer_random.77381075 Dec 20 12:40:16 PM PST 23 Dec 20 12:41:52 PM PST 23 36403526861 ps
T336 /workspace/coverage/default/88.rv_timer_random.3759268673 Dec 20 12:40:09 PM PST 23 Dec 20 12:58:59 PM PST 23 409976370449 ps
T344 /workspace/coverage/default/81.rv_timer_random.1866588465 Dec 20 12:40:08 PM PST 23 Dec 20 12:44:40 PM PST 23 116602319665 ps
T333 /workspace/coverage/default/154.rv_timer_random.1388035911 Dec 20 12:40:02 PM PST 23 Dec 20 12:45:21 PM PST 23 505973094113 ps
T306 /workspace/coverage/default/126.rv_timer_random.480748991 Dec 20 12:39:55 PM PST 23 Dec 20 12:52:04 PM PST 23 215387678154 ps
T352 /workspace/coverage/default/180.rv_timer_random.3305861635 Dec 20 12:40:08 PM PST 23 Dec 20 12:54:01 PM PST 23 161412334416 ps
T580 /workspace/coverage/default/42.rv_timer_random.947916768 Dec 20 12:39:43 PM PST 23 Dec 20 12:44:12 PM PST 23 101206940063 ps
T350 /workspace/coverage/default/128.rv_timer_random.4102833570 Dec 20 12:40:02 PM PST 23 Dec 20 12:44:23 PM PST 23 339950791512 ps
T249 /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.915046103 Dec 20 12:39:46 PM PST 23 Dec 20 12:59:28 PM PST 23 1091983373652 ps
T303 /workspace/coverage/default/4.rv_timer_random.1831737441 Dec 20 12:39:27 PM PST 23 Dec 20 12:42:03 PM PST 23 92621535571 ps
T209 /workspace/coverage/default/31.rv_timer_stress_all.2711208463 Dec 20 12:39:57 PM PST 23 Dec 20 12:55:00 PM PST 23 246115117630 ps
T581 /workspace/coverage/default/42.rv_timer_random_reset.3116831890 Dec 20 12:39:51 PM PST 23 Dec 20 12:41:00 PM PST 23 8088134022 ps
T192 /workspace/coverage/default/43.rv_timer_random.2485574032 Dec 20 12:40:03 PM PST 23 Dec 20 12:43:16 PM PST 23 397106059231 ps
T582 /workspace/coverage/default/12.rv_timer_random_reset.3266138554 Dec 20 12:40:00 PM PST 23 Dec 20 12:42:38 PM PST 23 253343437291 ps
T214 /workspace/coverage/default/25.rv_timer_stress_all.1138536615 Dec 20 12:39:35 PM PST 23 Dec 20 12:58:12 PM PST 23 1477114609583 ps
T279 /workspace/coverage/default/197.rv_timer_random.2936746820 Dec 20 12:40:11 PM PST 23 Dec 20 12:42:55 PM PST 23 180421302418 ps
T140 /workspace/coverage/default/97.rv_timer_random.4283121724 Dec 20 12:39:48 PM PST 23 Dec 20 12:55:12 PM PST 23 173700707629 ps
T314 /workspace/coverage/default/39.rv_timer_stress_all.3180226906 Dec 20 12:39:33 PM PST 23 Dec 20 01:09:18 PM PST 23 2317218402312 ps
T282 /workspace/coverage/default/179.rv_timer_random.1864297973 Dec 20 12:40:30 PM PST 23 Dec 20 12:49:47 PM PST 23 608277396521 ps
T583 /workspace/coverage/default/98.rv_timer_random.706890709 Dec 20 12:40:17 PM PST 23 Dec 20 12:46:37 PM PST 23 147482003960 ps
T326 /workspace/coverage/default/16.rv_timer_random_reset.1828838072 Dec 20 12:39:28 PM PST 23 Dec 20 12:41:56 PM PST 23 55077183629 ps
T584 /workspace/coverage/default/63.rv_timer_random.3347146700 Dec 20 12:39:56 PM PST 23 Dec 20 12:42:51 PM PST 23 77145254832 ps
T374 /workspace/coverage/default/121.rv_timer_random.2883858443 Dec 20 12:40:02 PM PST 23 Dec 20 12:42:36 PM PST 23 112475352033 ps
T585 /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.693284523 Dec 20 12:39:26 PM PST 23 Dec 20 12:56:22 PM PST 23 1667816084269 ps
T586 /workspace/coverage/default/32.rv_timer_disabled.1103899650 Dec 20 12:39:48 PM PST 23 Dec 20 12:41:36 PM PST 23 75388085345 ps
T587 /workspace/coverage/default/29.rv_timer_disabled.870914458 Dec 20 12:39:56 PM PST 23 Dec 20 12:44:27 PM PST 23 175704942456 ps
T588 /workspace/coverage/default/14.rv_timer_disabled.3214746959 Dec 20 12:39:25 PM PST 23 Dec 20 12:41:17 PM PST 23 26907011300 ps
T589 /workspace/coverage/default/13.rv_timer_random_reset.3988776230 Dec 20 12:39:28 PM PST 23 Dec 20 12:40:54 PM PST 23 7163464228 ps
T307 /workspace/coverage/default/80.rv_timer_random.3875612293 Dec 20 12:39:53 PM PST 23 Dec 20 12:44:58 PM PST 23 367239059550 ps
T201 /workspace/coverage/default/55.rv_timer_random.3016744704 Dec 20 12:39:41 PM PST 23 Dec 20 01:00:09 PM PST 23 133399563278 ps
T162 /workspace/coverage/default/171.rv_timer_random.1668986023 Dec 20 12:40:00 PM PST 23 Dec 20 12:54:29 PM PST 23 833033457509 ps
T590 /workspace/coverage/default/122.rv_timer_random.3626153930 Dec 20 12:40:02 PM PST 23 Dec 20 12:42:12 PM PST 23 103145978389 ps
T170 /workspace/coverage/default/85.rv_timer_random.1531660206 Dec 20 12:39:53 PM PST 23 Dec 20 12:52:57 PM PST 23 402923602148 ps
T591 /workspace/coverage/default/43.rv_timer_disabled.1673289515 Dec 20 12:39:54 PM PST 23 Dec 20 12:41:05 PM PST 23 2382525981 ps
T592 /workspace/coverage/default/0.rv_timer_random_reset.1754163045 Dec 20 12:38:53 PM PST 23 Dec 20 12:52:32 PM PST 23 142099898806 ps
T342 /workspace/coverage/default/101.rv_timer_random.1817818427 Dec 20 12:39:58 PM PST 23 Dec 20 12:48:57 PM PST 23 191668788197 ps
T319 /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.915832529 Dec 20 12:39:12 PM PST 23 Dec 20 12:53:41 PM PST 23 855953571166 ps
T295 /workspace/coverage/default/53.rv_timer_random.22145761 Dec 20 12:39:40 PM PST 23 Dec 20 12:47:36 PM PST 23 253890110301 ps
T593 /workspace/coverage/default/19.rv_timer_random_reset.4100589031 Dec 20 12:39:16 PM PST 23 Dec 20 12:42:24 PM PST 23 22489357557 ps
T311 /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1641718965 Dec 20 12:39:16 PM PST 23 Dec 20 12:52:34 PM PST 23 442159260812 ps
T160 /workspace/coverage/default/184.rv_timer_random.3518468059 Dec 20 12:40:00 PM PST 23 Dec 20 01:14:22 PM PST 23 570689017944 ps
T355 /workspace/coverage/default/35.rv_timer_stress_all.2987851427 Dec 20 12:39:53 PM PST 23 Dec 20 01:01:42 PM PST 23 585118079316 ps
T594 /workspace/coverage/default/17.rv_timer_stress_all.3677257479 Dec 20 12:39:45 PM PST 23 Dec 20 12:48:50 PM PST 23 588188635954 ps
T595 /workspace/coverage/default/26.rv_timer_disabled.1377577699 Dec 20 12:40:20 PM PST 23 Dec 20 12:42:29 PM PST 23 47485665647 ps
T596 /workspace/coverage/default/36.rv_timer_disabled.3321872277 Dec 20 12:39:54 PM PST 23 Dec 20 12:42:51 PM PST 23 143558915159 ps
T597 /workspace/coverage/default/38.rv_timer_disabled.3721872887 Dec 20 12:39:33 PM PST 23 Dec 20 12:47:10 PM PST 23 939382514843 ps
T598 /workspace/coverage/default/44.rv_timer_random_reset.3214030191 Dec 20 12:40:06 PM PST 23 Dec 20 12:42:08 PM PST 23 35770552720 ps
T599 /workspace/coverage/default/20.rv_timer_disabled.4014692357 Dec 20 12:39:33 PM PST 23 Dec 20 12:41:43 PM PST 23 44917939944 ps
T600 /workspace/coverage/default/15.rv_timer_random_reset.1667279565 Dec 20 12:39:29 PM PST 23 Dec 20 01:00:21 PM PST 23 380880413034 ps
T364 /workspace/coverage/default/69.rv_timer_random.3544347097 Dec 20 12:40:15 PM PST 23 Dec 20 12:41:49 PM PST 23 17929019229 ps
T601 /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.283486058 Dec 20 12:39:15 PM PST 23 Dec 20 12:57:32 PM PST 23 105785100496 ps
T602 /workspace/coverage/default/5.rv_timer_disabled.1475867227 Dec 20 12:39:33 PM PST 23 Dec 20 12:42:21 PM PST 23 64894937264 ps
T268 /workspace/coverage/default/153.rv_timer_random.1348676678 Dec 20 12:40:01 PM PST 23 Dec 20 01:12:54 PM PST 23 805667417854 ps
T17 /workspace/coverage/default/0.rv_timer_sec_cm.2112654945 Dec 20 12:39:12 PM PST 23 Dec 20 12:40:26 PM PST 23 130629375 ps
T603 /workspace/coverage/default/23.rv_timer_random.2120012403 Dec 20 12:39:47 PM PST 23 Dec 20 12:47:20 PM PST 23 121286754578 ps
T357 /workspace/coverage/default/130.rv_timer_random.2259516699 Dec 20 12:40:02 PM PST 23 Dec 20 12:50:08 PM PST 23 503529950658 ps
T223 /workspace/coverage/default/132.rv_timer_random.2334677675 Dec 20 12:40:02 PM PST 23 Dec 20 12:43:16 PM PST 23 42210760646 ps
T289 /workspace/coverage/default/65.rv_timer_random.4982416 Dec 20 12:39:54 PM PST 23 Dec 20 12:55:04 PM PST 23 748960677425 ps
T371 /workspace/coverage/default/49.rv_timer_stress_all.3127824711 Dec 20 12:39:45 PM PST 23 Dec 20 01:02:39 PM PST 23 515676026628 ps
T308 /workspace/coverage/default/111.rv_timer_random.835156924 Dec 20 12:40:09 PM PST 23 Dec 20 12:42:43 PM PST 23 238002550795 ps
T195 /workspace/coverage/default/36.rv_timer_stress_all.1645907248 Dec 20 12:39:30 PM PST 23 Dec 20 12:48:57 PM PST 23 259464346560 ps
T304 /workspace/coverage/default/110.rv_timer_random.1713451656 Dec 20 12:39:58 PM PST 23 Dec 20 12:54:38 PM PST 23 379679140924 ps
T372 /workspace/coverage/default/199.rv_timer_random.2524504626 Dec 20 12:40:20 PM PST 23 Dec 20 12:49:12 PM PST 23 183094144294 ps
T237 /workspace/coverage/default/30.rv_timer_random.4112472364 Dec 20 12:39:49 PM PST 23 Dec 20 12:42:35 PM PST 23 196948013440 ps
T604 /workspace/coverage/default/124.rv_timer_random.2401707795 Dec 20 12:40:04 PM PST 23 Dec 20 12:44:36 PM PST 23 63868285591 ps
T338 /workspace/coverage/default/29.rv_timer_stress_all.1680884406 Dec 20 12:39:41 PM PST 23 Dec 20 12:53:53 PM PST 23 393396448016 ps
T232 /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1029578094 Dec 20 12:39:54 PM PST 23 Dec 20 12:46:59 PM PST 23 781384750964 ps
T210 /workspace/coverage/default/139.rv_timer_random.3422691016 Dec 20 12:39:58 PM PST 23 Dec 20 12:46:40 PM PST 23 339576692636 ps
T378 /workspace/coverage/default/60.rv_timer_random.105156224 Dec 20 12:40:12 PM PST 23 Dec 20 12:46:31 PM PST 23 185257512523 ps
T605 /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.460631592 Dec 20 12:39:34 PM PST 23 Dec 20 12:43:58 PM PST 23 55619634465 ps
T312 /workspace/coverage/default/105.rv_timer_random.8488033 Dec 20 12:39:54 PM PST 23 Dec 20 12:42:53 PM PST 23 66897561636 ps
T606 /workspace/coverage/default/7.rv_timer_disabled.2165260076 Dec 20 12:39:16 PM PST 23 Dec 20 12:41:11 PM PST 23 29140454001 ps
T358 /workspace/coverage/default/191.rv_timer_random.2348085984 Dec 20 12:40:26 PM PST 23 Dec 20 12:45:19 PM PST 23 75156116527 ps
T607 /workspace/coverage/default/38.rv_timer_stress_all.1017897222 Dec 20 12:39:55 PM PST 23 Dec 20 12:41:04 PM PST 23 55183679 ps
T608 /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4046116805 Dec 20 12:39:48 PM PST 23 Dec 20 12:43:14 PM PST 23 168925747554 ps
T609 /workspace/coverage/default/21.rv_timer_disabled.1141656036 Dec 20 12:39:18 PM PST 23 Dec 20 12:43:48 PM PST 23 251400705785 ps
T610 /workspace/coverage/default/71.rv_timer_random.831216535 Dec 20 12:39:51 PM PST 23 Dec 20 12:42:07 PM PST 23 353814801089 ps
T611 /workspace/coverage/default/16.rv_timer_stress_all.1035581434 Dec 20 12:39:43 PM PST 23 Dec 20 12:48:17 PM PST 23 255644353414 ps
T354 /workspace/coverage/default/56.rv_timer_random.2561841693 Dec 20 12:39:36 PM PST 23 Dec 20 12:54:38 PM PST 23 227489227643 ps
T242 /workspace/coverage/default/70.rv_timer_random.3142915130 Dec 20 12:40:08 PM PST 23 Dec 20 12:47:22 PM PST 23 661484463923 ps
T612 /workspace/coverage/default/176.rv_timer_random.969435405 Dec 20 12:40:05 PM PST 23 Dec 20 12:41:45 PM PST 23 80600776044 ps
T613 /workspace/coverage/default/92.rv_timer_random.684719267 Dec 20 12:39:51 PM PST 23 Dec 20 12:41:52 PM PST 23 42731221474 ps
T148 /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2079447535 Dec 20 12:39:48 PM PST 23 Dec 20 12:50:28 PM PST 23 601377234050 ps
T164 /workspace/coverage/default/2.rv_timer_stress_all.3474223879 Dec 20 12:39:09 PM PST 23 Dec 20 01:17:42 PM PST 23 338268571180 ps
T165 /workspace/coverage/default/10.rv_timer_random_reset.1307019945 Dec 20 12:39:40 PM PST 23 Dec 20 12:49:48 PM PST 23 272851004513 ps
T614 /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1883885868 Dec 20 12:39:31 PM PST 23 Dec 20 12:46:22 PM PST 23 98128991541 ps

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2522081176
Short name T5
Test name
Test status
Simulation time 151711700049 ps
CPU time 562.72 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:50:00 PM PST 23
Peak memory 206976 kb
Host smart-8c56d9d7-9407-402f-85fb-a4cf843c924a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522081176 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2522081176
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2324525957
Short name T104
Test name
Test status
Simulation time 2624186158210 ps
CPU time 1814.74 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 01:10:44 PM PST 23
Peak memory 191248 kb
Host smart-fa8700c2-e36a-4d2a-aebf-ddaca1f9ce95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324525957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2324525957
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.5533827
Short name T91
Test name
Test status
Simulation time 832923758105 ps
CPU time 4920.66 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 02:02:22 PM PST 23
Peak memory 195160 kb
Host smart-e6d6b490-cced-4faa-adef-c1917df540cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5533827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.5533827
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.681874530
Short name T27
Test name
Test status
Simulation time 173134756 ps
CPU time 1.28 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 183584 kb
Host smart-ac5c7aa2-7de6-428e-ba7c-c8423f526050
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681874530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.681874530
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2128421356
Short name T152
Test name
Test status
Simulation time 3339549648532 ps
CPU time 3066.89 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 01:31:56 PM PST 23
Peak memory 191036 kb
Host smart-78fcc288-47cf-48d8-bd47-9ab54244e87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128421356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2128421356
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2944685884
Short name T163
Test name
Test status
Simulation time 668703439109 ps
CPU time 1936.93 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 01:12:48 PM PST 23
Peak memory 195112 kb
Host smart-fa099ba6-f7de-4a46-9228-4fc669030f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944685884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2944685884
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.303084435
Short name T175
Test name
Test status
Simulation time 764495440596 ps
CPU time 3244.79 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 01:34:41 PM PST 23
Peak memory 190984 kb
Host smart-24f812dd-bf6a-4267-bef2-c43d52bfde20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303084435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.303084435
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.838210846
Short name T8
Test name
Test status
Simulation time 950571811662 ps
CPU time 2367.59 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 01:20:08 PM PST 23
Peak memory 191232 kb
Host smart-e68794ca-3e5d-491b-b30f-c27a9932f244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838210846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
838210846
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1581585358
Short name T112
Test name
Test status
Simulation time 1613836777548 ps
CPU time 1618.42 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 01:07:34 PM PST 23
Peak memory 191100 kb
Host smart-2a45225a-a1e5-457e-8371-40ca1d0500c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581585358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1581585358
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1505965605
Short name T39
Test name
Test status
Simulation time 56201637 ps
CPU time 0.58 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 183356 kb
Host smart-b47647b9-d67a-4ff7-ad61-bb164e3e54a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505965605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1505965605
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1138536615
Short name T214
Test name
Test status
Simulation time 1477114609583 ps
CPU time 1049.38 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:58:12 PM PST 23
Peak memory 191176 kb
Host smart-8b93e31b-2392-484d-81ee-fd5e24773322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138536615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1138536615
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1728407421
Short name T108
Test name
Test status
Simulation time 7767490193838 ps
CPU time 1682.78 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 01:08:43 PM PST 23
Peak memory 191240 kb
Host smart-3b5b69a0-ee77-4f01-a4b9-068887cf0d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728407421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1728407421
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2091873992
Short name T101
Test name
Test status
Simulation time 3344322541975 ps
CPU time 921.12 seconds
Started Dec 20 12:39:22 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 195444 kb
Host smart-a012208f-c67a-4464-b2c8-4c2942689435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091873992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2091873992
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3001007243
Short name T153
Test name
Test status
Simulation time 618451388744 ps
CPU time 1686.41 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 01:08:52 PM PST 23
Peak memory 191240 kb
Host smart-425bd7a7-fb78-4bfb-880a-8a6911ad7fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001007243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3001007243
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2112654945
Short name T17
Test name
Test status
Simulation time 130629375 ps
CPU time 0.7 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:40:26 PM PST 23
Peak memory 212676 kb
Host smart-17cf5f56-3bf4-4811-bae6-fc02894ab6fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112654945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2112654945
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/89.rv_timer_random.3262690278
Short name T89
Test name
Test status
Simulation time 137950065862 ps
CPU time 245.18 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:45:10 PM PST 23
Peak memory 191208 kb
Host smart-65b5e082-71f2-4275-9c20-6028cfc0d052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262690278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3262690278
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.915556792
Short name T236
Test name
Test status
Simulation time 1677244029402 ps
CPU time 1411.75 seconds
Started Dec 20 12:39:52 PM PST 23
Finished Dec 20 01:04:27 PM PST 23
Peak memory 191248 kb
Host smart-2087cb7f-120d-404c-b67e-e889451cff80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915556792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
915556792
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1680884406
Short name T338
Test name
Test status
Simulation time 393396448016 ps
CPU time 782.13 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 191236 kb
Host smart-5480dc02-adc4-41fc-916d-69179f5b2289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680884406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1680884406
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2711208463
Short name T209
Test name
Test status
Simulation time 246115117630 ps
CPU time 837.75 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 191228 kb
Host smart-58239afe-1765-4885-b73d-62c9220883dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711208463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2711208463
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.740256491
Short name T100
Test name
Test status
Simulation time 452813423084 ps
CPU time 206.24 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:44:31 PM PST 23
Peak memory 191164 kb
Host smart-d4400952-b9b4-46c7-b19a-49274a285da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740256491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.740256491
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1668986023
Short name T162
Test name
Test status
Simulation time 833033457509 ps
CPU time 794.38 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:54:29 PM PST 23
Peak memory 193256 kb
Host smart-669a8d97-c518-4e1e-ac42-f762cef875c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668986023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1668986023
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2987851427
Short name T355
Test name
Test status
Simulation time 585118079316 ps
CPU time 1242.83 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 01:01:42 PM PST 23
Peak memory 191208 kb
Host smart-1c369de5-8777-40c1-82f0-14896fb511b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987851427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2987851427
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.352009877
Short name T373
Test name
Test status
Simulation time 135254476989 ps
CPU time 244.31 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:45:13 PM PST 23
Peak memory 191208 kb
Host smart-b9153723-8f0a-4588-9831-69b6036f3ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352009877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.352009877
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.2322324311
Short name T241
Test name
Test status
Simulation time 139138301644 ps
CPU time 161.25 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:43:11 PM PST 23
Peak memory 191156 kb
Host smart-356e2f13-9c01-47ab-bbed-b1e37e7e6bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322324311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2322324311
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4283121724
Short name T140
Test name
Test status
Simulation time 173700707629 ps
CPU time 858.31 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 191032 kb
Host smart-bac9dba0-8c88-41d7-bd2d-047aa28b2e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283121724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4283121724
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1864297973
Short name T282
Test name
Test status
Simulation time 608277396521 ps
CPU time 497.26 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:49:47 PM PST 23
Peak memory 193964 kb
Host smart-d7c4547c-501c-4467-bb7f-fd5cee5c1d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864297973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1864297973
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.3930727712
Short name T215
Test name
Test status
Simulation time 160903436292 ps
CPU time 285.45 seconds
Started Dec 20 12:39:52 PM PST 23
Finished Dec 20 12:45:47 PM PST 23
Peak memory 191224 kb
Host smart-1338a991-494a-416d-bd57-11a1ed8cd23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930727712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3930727712
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3180226906
Short name T314
Test name
Test status
Simulation time 2317218402312 ps
CPU time 1716.62 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 01:09:18 PM PST 23
Peak memory 194860 kb
Host smart-bc5c7536-9838-4254-9e51-369e5f8ec597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180226906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3180226906
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3779652124
Short name T294
Test name
Test status
Simulation time 1417511570840 ps
CPU time 1129.37 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:59:47 PM PST 23
Peak memory 191252 kb
Host smart-bdf7cf64-9ff6-48e1-99a4-28f89c84e8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779652124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3779652124
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/55.rv_timer_random.3016744704
Short name T201
Test name
Test status
Simulation time 133399563278 ps
CPU time 1161.28 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 01:00:09 PM PST 23
Peak memory 195232 kb
Host smart-c8cc0d96-55ca-4960-aaf2-7fd93207aa03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016744704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3016744704
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4000336921
Short name T24
Test name
Test status
Simulation time 333342689416 ps
CPU time 517.17 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:49:28 PM PST 23
Peak memory 191060 kb
Host smart-3ef8a038-1cf1-4b08-b0bf-aea2cd8be854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000336921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4000336921
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.4071699408
Short name T247
Test name
Test status
Simulation time 135581812354 ps
CPU time 239.42 seconds
Started Dec 20 12:39:21 PM PST 23
Finished Dec 20 12:44:28 PM PST 23
Peak memory 191064 kb
Host smart-db730b0d-0704-4d23-bac0-cd14cfa67f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071699408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4071699408
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.1608892918
Short name T229
Test name
Test status
Simulation time 218221059071 ps
CPU time 357.2 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:46:57 PM PST 23
Peak memory 191004 kb
Host smart-af0d6a0a-805e-4a2f-9089-606b605b92f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608892918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1608892918
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3127824711
Short name T371
Test name
Test status
Simulation time 515676026628 ps
CPU time 1309.73 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 01:02:39 PM PST 23
Peak memory 191240 kb
Host smart-30ff5d0c-9bc5-42b4-aca3-63f89ace9f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127824711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3127824711
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.4982416
Short name T289
Test name
Test status
Simulation time 748960677425 ps
CPU time 844.76 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 193156 kb
Host smart-a47eee66-df96-452d-a412-552e483eed25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4982416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.4982416
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3645307626
Short name T119
Test name
Test status
Simulation time 402559865557 ps
CPU time 531.08 seconds
Started Dec 20 12:39:21 PM PST 23
Finished Dec 20 12:49:25 PM PST 23
Peak memory 183180 kb
Host smart-b7cb5d52-80be-46c6-9a1c-4a10be5b21b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645307626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3645307626
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/139.rv_timer_random.3422691016
Short name T210
Test name
Test status
Simulation time 339576692636 ps
CPU time 335.36 seconds
Started Dec 20 12:39:58 PM PST 23
Finished Dec 20 12:46:40 PM PST 23
Peak memory 194460 kb
Host smart-e1b8bf45-a0c7-4308-b445-bd42aecea4ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422691016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3422691016
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1641718965
Short name T311
Test name
Test status
Simulation time 442159260812 ps
CPU time 729.17 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:52:34 PM PST 23
Peak memory 183060 kb
Host smart-95d86770-cb6f-4348-824c-c3e52b980064
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641718965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1641718965
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/188.rv_timer_random.3600720454
Short name T216
Test name
Test status
Simulation time 399391801209 ps
CPU time 1060.76 seconds
Started Dec 20 12:40:11 PM PST 23
Finished Dec 20 12:58:52 PM PST 23
Peak memory 195336 kb
Host smart-e0b0d3d9-1d6a-47d4-928e-deb44fb8db68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600720454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3600720454
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.3451078951
Short name T155
Test name
Test status
Simulation time 174787033247 ps
CPU time 170.15 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:43:23 PM PST 23
Peak memory 191264 kb
Host smart-665e19a8-293e-4773-bc19-8bfc8669746a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451078951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3451078951
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.678925773
Short name T345
Test name
Test status
Simulation time 1632744989730 ps
CPU time 828.73 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:54:45 PM PST 23
Peak memory 182784 kb
Host smart-756174c4-90e8-4dd4-a2ed-fa36800e1882
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678925773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.678925773
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.12499507
Short name T180
Test name
Test status
Simulation time 1090020085888 ps
CPU time 766.79 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:53:33 PM PST 23
Peak memory 191228 kb
Host smart-073649bc-729f-4736-a249-ec4a22db378f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12499507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.12499507
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/64.rv_timer_random.2212171323
Short name T114
Test name
Test status
Simulation time 127015445925 ps
CPU time 293.67 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:45:42 PM PST 23
Peak memory 193832 kb
Host smart-7306acb9-f396-4fc7-891c-71b62091828a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212171323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2212171323
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.3289412370
Short name T221
Test name
Test status
Simulation time 655356874061 ps
CPU time 859.43 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 193536 kb
Host smart-1eda9a8d-b656-41df-8861-628ab7351425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289412370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3289412370
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3501254503
Short name T179
Test name
Test status
Simulation time 237188374582 ps
CPU time 644.52 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:51:48 PM PST 23
Peak memory 191172 kb
Host smart-a11a4ea0-03db-4de6-895a-a4cf234a4ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501254503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3501254503
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.889608412
Short name T189
Test name
Test status
Simulation time 138565983425 ps
CPU time 422.77 seconds
Started Dec 20 12:39:43 PM PST 23
Finished Dec 20 12:47:49 PM PST 23
Peak memory 191048 kb
Host smart-22accf02-5f67-454a-a2dc-1ce09d6c67ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889608412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.889608412
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1713451656
Short name T304
Test name
Test status
Simulation time 379679140924 ps
CPU time 816.1 seconds
Started Dec 20 12:39:58 PM PST 23
Finished Dec 20 12:54:38 PM PST 23
Peak memory 193768 kb
Host smart-8b08ac3f-c5ae-42f8-8f09-7c5badc2ef3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713451656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1713451656
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.835156924
Short name T308
Test name
Test status
Simulation time 238002550795 ps
CPU time 93.15 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 194020 kb
Host smart-34d183d5-c5e8-412f-bf7e-c7bab5507964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835156924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.835156924
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.480748991
Short name T306
Test name
Test status
Simulation time 215387678154 ps
CPU time 660.51 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:52:04 PM PST 23
Peak memory 193240 kb
Host smart-eb38de38-7393-4bb2-aa10-4841a5c01f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480748991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.480748991
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.14506793
Short name T144
Test name
Test status
Simulation time 119057203453 ps
CPU time 205.02 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:44:44 PM PST 23
Peak memory 183068 kb
Host smart-48c53583-5192-4c11-acaf-4f51353ef464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.14506793
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1295700939
Short name T272
Test name
Test status
Simulation time 88765482719 ps
CPU time 53.6 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 182988 kb
Host smart-9e4b5c88-03a8-4ebd-8f9d-e560d7032d42
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295700939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1295700939
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3003451426
Short name T158
Test name
Test status
Simulation time 315804275097 ps
CPU time 914.2 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 191208 kb
Host smart-1a613bae-11ff-4199-98de-135afb8ad46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003451426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3003451426
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.22145761
Short name T295
Test name
Test status
Simulation time 253890110301 ps
CPU time 405.15 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:47:36 PM PST 23
Peak memory 195448 kb
Host smart-837071d5-c9ec-4913-a24f-84a6b76167d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22145761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.22145761
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3071714935
Short name T67
Test name
Test status
Simulation time 954043437 ps
CPU time 1.57 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:14 PM PST 23
Peak memory 191716 kb
Host smart-738add18-9e7e-4f97-9ee0-9a949d0e0f8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071714935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3071714935
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4041040373
Short name T55
Test name
Test status
Simulation time 135453645 ps
CPU time 0.68 seconds
Started Dec 20 12:20:00 PM PST 23
Finished Dec 20 12:20:01 PM PST 23
Peak memory 192396 kb
Host smart-79caae03-6b94-4caa-a009-01328c22a7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041040373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4041040373
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1292201292
Short name T285
Test name
Test status
Simulation time 62364338017 ps
CPU time 98.37 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 191256 kb
Host smart-4aefd96c-7d28-403d-9a44-037b5ff77ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292201292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1292201292
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1307019945
Short name T165
Test name
Test status
Simulation time 272851004513 ps
CPU time 536.73 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:49:48 PM PST 23
Peak memory 182972 kb
Host smart-7ded008b-6565-48a2-9ea5-995e5435aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307019945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1307019945
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/113.rv_timer_random.1706761160
Short name T199
Test name
Test status
Simulation time 245913338233 ps
CPU time 730.43 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 191188 kb
Host smart-2d6cc9aa-8884-4249-a2bf-1b27fc50280a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706761160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1706761160
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1988478270
Short name T240
Test name
Test status
Simulation time 598951909503 ps
CPU time 443.42 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:47:49 PM PST 23
Peak memory 191192 kb
Host smart-66492b08-fc91-452c-8c98-b380aea31027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988478270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1988478270
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.2127559816
Short name T239
Test name
Test status
Simulation time 406626079305 ps
CPU time 1070.19 seconds
Started Dec 20 12:40:41 PM PST 23
Finished Dec 20 12:59:33 PM PST 23
Peak memory 191296 kb
Host smart-78945f3e-4318-4b14-ba0e-34858a0ec7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127559816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2127559816
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.202508291
Short name T316
Test name
Test status
Simulation time 217098280319 ps
CPU time 508.53 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:49:38 PM PST 23
Peak memory 191272 kb
Host smart-4504870c-33ab-47ee-b2cf-6b42147d0c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202508291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.202508291
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3019438231
Short name T151
Test name
Test status
Simulation time 137444575755 ps
CPU time 694.66 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 193112 kb
Host smart-30504ca1-b925-4fe5-9698-25c62a8de86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019438231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3019438231
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.558529497
Short name T233
Test name
Test status
Simulation time 795034159681 ps
CPU time 359.11 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:47:34 PM PST 23
Peak memory 191308 kb
Host smart-63eee519-32cc-418e-99a3-f0ecd4c9bce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558529497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.558529497
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2823377266
Short name T154
Test name
Test status
Simulation time 105069694149 ps
CPU time 205.22 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:44:36 PM PST 23
Peak memory 190976 kb
Host smart-e20d2854-d096-47f3-af01-c5b791b412fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823377266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2823377266
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1212568209
Short name T138
Test name
Test status
Simulation time 801877011652 ps
CPU time 756.57 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:53:36 PM PST 23
Peak memory 183000 kb
Host smart-56f97860-1052-4f33-a6b4-5771a249c6c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212568209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1212568209
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.3094084227
Short name T227
Test name
Test status
Simulation time 419089433781 ps
CPU time 445.19 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:48:27 PM PST 23
Peak memory 191104 kb
Host smart-6b4893b3-e760-438f-952e-93cb1c7aab35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094084227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3094084227
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.278176626
Short name T168
Test name
Test status
Simulation time 174229940564 ps
CPU time 790.69 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:54:13 PM PST 23
Peak memory 191168 kb
Host smart-493d26c9-5ad6-426b-94ff-162e4754d8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278176626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
278176626
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1645907248
Short name T195
Test name
Test status
Simulation time 259464346560 ps
CPU time 489.1 seconds
Started Dec 20 12:39:30 PM PST 23
Finished Dec 20 12:48:57 PM PST 23
Peak memory 191008 kb
Host smart-28dec2ef-e256-43d2-a1dc-fa16c5134637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645907248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1645907248
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3194868867
Short name T92
Test name
Test status
Simulation time 392423980666 ps
CPU time 209.28 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:44:22 PM PST 23
Peak memory 182856 kb
Host smart-db4fc82c-5df7-4f1b-9387-339b8ce5b599
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194868867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3194868867
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/59.rv_timer_random.2736108865
Short name T335
Test name
Test status
Simulation time 582581560639 ps
CPU time 494.98 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:49:14 PM PST 23
Peak memory 191228 kb
Host smart-65b56b79-a021-4ec4-8498-8a1ff59243d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736108865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2736108865
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1091717118
Short name T87
Test name
Test status
Simulation time 865137828 ps
CPU time 1.27 seconds
Started Dec 20 12:21:27 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 183720 kb
Host smart-e34bb440-3bf6-4b84-95b2-c9a3936b3190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091717118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1091717118
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.210957870
Short name T207
Test name
Test status
Simulation time 104999586632 ps
CPU time 179.75 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:43:09 PM PST 23
Peak memory 191272 kb
Host smart-dae911af-beb9-4a30-892a-d4e94d963d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210957870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.210957870
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.852284777
Short name T186
Test name
Test status
Simulation time 191375495297 ps
CPU time 625.23 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 12:50:41 PM PST 23
Peak memory 191204 kb
Host smart-0bb09d9f-8df0-4cd7-84b7-c078a0c347bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852284777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.852284777
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1817818427
Short name T342
Test name
Test status
Simulation time 191668788197 ps
CPU time 476.1 seconds
Started Dec 20 12:39:58 PM PST 23
Finished Dec 20 12:48:57 PM PST 23
Peak memory 193660 kb
Host smart-2c985ca6-cdf7-4572-8869-484b2bf77a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817818427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1817818427
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.270606687
Short name T543
Test name
Test status
Simulation time 3962193728 ps
CPU time 4.39 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:33 PM PST 23
Peak memory 182988 kb
Host smart-4fdeaa09-c47e-4c60-801f-4b457f3ce576
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270606687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.270606687
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random.3183357144
Short name T339
Test name
Test status
Simulation time 66275535590 ps
CPU time 370.74 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:46:32 PM PST 23
Peak memory 191140 kb
Host smart-d2f10f01-bca4-4824-88c9-0de629be3c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183357144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3183357144
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.779074731
Short name T159
Test name
Test status
Simulation time 206783424607 ps
CPU time 312.93 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:46:22 PM PST 23
Peak memory 191224 kb
Host smart-41e5310c-8e5b-4687-a9d6-ee05bffd2c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779074731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.779074731
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4102833570
Short name T350
Test name
Test status
Simulation time 339950791512 ps
CPU time 199.34 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:44:23 PM PST 23
Peak memory 190684 kb
Host smart-5bc9f266-5ec1-4fad-b79f-54635ddfc1a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102833570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4102833570
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2471262283
Short name T212
Test name
Test status
Simulation time 55569039724 ps
CPU time 415.08 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:47:38 PM PST 23
Peak memory 197520 kb
Host smart-da5c8c61-dc80-4211-a434-bf2628bd0bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471262283 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2471262283
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1619575509
Short name T141
Test name
Test status
Simulation time 110304865752 ps
CPU time 117.57 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 191176 kb
Host smart-30165af1-c91e-4e14-b574-0ddc421a47f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619575509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1619575509
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1039035771
Short name T124
Test name
Test status
Simulation time 838820447809 ps
CPU time 605.14 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:51:16 PM PST 23
Peak memory 191212 kb
Host smart-a1eb02a2-33dc-4323-bcf2-9ba4d9b4eaef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039035771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1039035771
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2402162117
Short name T127
Test name
Test status
Simulation time 520539240301 ps
CPU time 397.28 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:47:40 PM PST 23
Peak memory 193356 kb
Host smart-f27c9b13-061e-437f-a002-337d3c55b8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402162117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2402162117
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2730879313
Short name T230
Test name
Test status
Simulation time 35185673019 ps
CPU time 58.61 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:41:57 PM PST 23
Peak memory 191248 kb
Host smart-f13a3546-1363-4187-9363-668b48542192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730879313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2730879313
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3811122539
Short name T198
Test name
Test status
Simulation time 240589405697 ps
CPU time 512.12 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:49:55 PM PST 23
Peak memory 191136 kb
Host smart-921fd3b3-a568-4475-9a9c-22d7da81f40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811122539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3811122539
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.265068517
Short name T193
Test name
Test status
Simulation time 364177142206 ps
CPU time 189.78 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:44:33 PM PST 23
Peak memory 193348 kb
Host smart-37b04a8f-2c19-4da4-8380-24b2016fb9e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265068517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.265068517
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3120851627
Short name T20
Test name
Test status
Simulation time 573056236575 ps
CPU time 1134.14 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:59:57 PM PST 23
Peak memory 191176 kb
Host smart-3c81bc98-1592-4c90-a670-42c9a7bb1aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120851627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3120851627
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4110250299
Short name T190
Test name
Test status
Simulation time 230209378665 ps
CPU time 484.49 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:49:19 PM PST 23
Peak memory 191200 kb
Host smart-6fe0d2ea-a3d9-4506-a535-a8f24bcacc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110250299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4110250299
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.262114838
Short name T106
Test name
Test status
Simulation time 93116334712 ps
CPU time 236.27 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:45:24 PM PST 23
Peak memory 191064 kb
Host smart-13913643-d1e8-4d33-b746-f3eda39c9d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262114838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.262114838
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.999847290
Short name T252
Test name
Test status
Simulation time 449419213289 ps
CPU time 251.02 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:46:28 PM PST 23
Peak memory 191184 kb
Host smart-cc368866-1c68-494d-8334-956c3df96d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999847290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.999847290
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1045950440
Short name T102
Test name
Test status
Simulation time 68982577064 ps
CPU time 903.64 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 183028 kb
Host smart-48e28556-5b0c-43cd-bd4c-42d7097ac3f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045950440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1045950440
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3702828385
Short name T97
Test name
Test status
Simulation time 119130634865 ps
CPU time 348.24 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:47:04 PM PST 23
Peak memory 191028 kb
Host smart-ad8f0799-661b-4554-ae8c-dd77c7cf806e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702828385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3702828385
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2380440965
Short name T377
Test name
Test status
Simulation time 137719030986 ps
CPU time 47.02 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:41:05 PM PST 23
Peak memory 183020 kb
Host smart-d93ad79e-753e-4b64-9400-e324e60284a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380440965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2380440965
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3209191281
Short name T222
Test name
Test status
Simulation time 67129591395 ps
CPU time 17.76 seconds
Started Dec 20 12:39:38 PM PST 23
Finished Dec 20 12:41:06 PM PST 23
Peak memory 183052 kb
Host smart-e836d8a2-0010-4d05-b6d9-4a0604b2f206
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209191281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3209191281
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2079447535
Short name T148
Test name
Test status
Simulation time 601377234050 ps
CPU time 575.04 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:50:28 PM PST 23
Peak memory 183076 kb
Host smart-621e11a6-f33c-42d2-b80f-7663ea355bd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079447535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2079447535
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.2749976930
Short name T238
Test name
Test status
Simulation time 88746335792 ps
CPU time 144.67 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:43:33 PM PST 23
Peak memory 191124 kb
Host smart-0c3a7ea9-0466-4d07-9cc7-1c951f0eabe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749976930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2749976930
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3882189854
Short name T196
Test name
Test status
Simulation time 405905243509 ps
CPU time 2596.06 seconds
Started Dec 20 12:39:38 PM PST 23
Finished Dec 20 01:24:05 PM PST 23
Peak memory 191396 kb
Host smart-a5e4b133-b8be-40c6-98ad-5fe516fd0d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882189854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3882189854
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1210822374
Short name T275
Test name
Test status
Simulation time 677885966703 ps
CPU time 550.71 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:50:10 PM PST 23
Peak memory 191288 kb
Host smart-cbab263f-d9b5-4aba-b71f-91ef6cac9abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210822374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1210822374
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/79.rv_timer_random.1417723367
Short name T288
Test name
Test status
Simulation time 499651846830 ps
CPU time 217.63 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:44:35 PM PST 23
Peak memory 191212 kb
Host smart-e99a5894-ef8a-4694-b519-8484d01877bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417723367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1417723367
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1063704638
Short name T313
Test name
Test status
Simulation time 152325397474 ps
CPU time 125.91 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:43:18 PM PST 23
Peak memory 193764 kb
Host smart-531ea425-217c-4283-9551-0866971a6aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063704638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1063704638
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.951384772
Short name T261
Test name
Test status
Simulation time 107411496065 ps
CPU time 89.89 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:41:58 PM PST 23
Peak memory 192552 kb
Host smart-3565abfd-0af9-4610-9876-9e5ba1735de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951384772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.951384772
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3506611932
Short name T69
Test name
Test status
Simulation time 57295271 ps
CPU time 0.74 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 192920 kb
Host smart-96891e0d-3a90-4c0e-8589-4d5e3b82cc5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506611932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3506611932
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2599166813
Short name T61
Test name
Test status
Simulation time 26579533 ps
CPU time 0.55 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:37 PM PST 23
Peak memory 183320 kb
Host smart-e999f6a7-fe74-4014-8046-6d367e99c785
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599166813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2599166813
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.473566673
Short name T13
Test name
Test status
Simulation time 48095495 ps
CPU time 1.49 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 198080 kb
Host smart-251e046e-0f65-4944-ba98-965a59c5b5c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473566673 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.473566673
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2911190017
Short name T71
Test name
Test status
Simulation time 23218410 ps
CPU time 0.56 seconds
Started Dec 20 12:21:36 PM PST 23
Finished Dec 20 12:21:51 PM PST 23
Peak memory 183208 kb
Host smart-d06b18ef-e592-41f5-8b52-eed8b4c46f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911190017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2911190017
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3578568272
Short name T438
Test name
Test status
Simulation time 70866760 ps
CPU time 0.52 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 182152 kb
Host smart-42791090-ba31-4d78-9a4a-f24b2876d8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578568272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3578568272
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1258575714
Short name T35
Test name
Test status
Simulation time 206566500 ps
CPU time 1.25 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 198064 kb
Host smart-bc87145c-967e-49d3-a1ef-a0b5ec8712ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258575714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1258575714
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3061002897
Short name T485
Test name
Test status
Simulation time 122707841 ps
CPU time 1.42 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:41 PM PST 23
Peak memory 183900 kb
Host smart-730c4e19-d2be-4bfc-8e4e-f8890a10cb60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061002897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3061002897
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4049310546
Short name T456
Test name
Test status
Simulation time 97285328 ps
CPU time 0.69 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:19 PM PST 23
Peak memory 192592 kb
Host smart-75eb9ec8-31e1-49e1-8bba-513279af386b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049310546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.4049310546
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2457440864
Short name T44
Test name
Test status
Simulation time 663136652 ps
CPU time 2.63 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 191652 kb
Host smart-70d344d3-2893-4455-a1dc-a36de39d264e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457440864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2457440864
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4196463259
Short name T76
Test name
Test status
Simulation time 18310099 ps
CPU time 0.58 seconds
Started Dec 20 12:20:31 PM PST 23
Finished Dec 20 12:20:36 PM PST 23
Peak memory 183348 kb
Host smart-5d4cf135-1094-4155-bece-0ca31ef2ef9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196463259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4196463259
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3053155564
Short name T31
Test name
Test status
Simulation time 17191207 ps
CPU time 0.62 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 194456 kb
Host smart-76973e68-6c63-4899-be5d-1d04eed77694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053155564 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3053155564
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3476665200
Short name T43
Test name
Test status
Simulation time 40863525 ps
CPU time 0.54 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 183264 kb
Host smart-1c1ed25d-1220-4fa4-9b40-86de4ebccab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476665200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3476665200
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3910974744
Short name T483
Test name
Test status
Simulation time 27293051 ps
CPU time 0.54 seconds
Started Dec 20 12:20:12 PM PST 23
Finished Dec 20 12:20:14 PM PST 23
Peak memory 182948 kb
Host smart-2cc00837-ad4f-4e4a-b269-b5713fd8f8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910974744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3910974744
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2882888561
Short name T475
Test name
Test status
Simulation time 55111342 ps
CPU time 0.65 seconds
Started Dec 20 12:20:31 PM PST 23
Finished Dec 20 12:20:36 PM PST 23
Peak memory 192588 kb
Host smart-68c5c163-f427-4587-9b30-cee95de534a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882888561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2882888561
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1995325926
Short name T36
Test name
Test status
Simulation time 118250557 ps
CPU time 0.91 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 197492 kb
Host smart-c572e05f-f2e4-49b1-bcba-6e9657a098c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995325926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1995325926
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.721534385
Short name T28
Test name
Test status
Simulation time 536459542 ps
CPU time 0.87 seconds
Started Dec 20 12:20:13 PM PST 23
Finished Dec 20 12:20:15 PM PST 23
Peak memory 193936 kb
Host smart-b2f162f2-cb40-4732-9a6f-1ebc34b70b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721534385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.721534385
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.864925000
Short name T474
Test name
Test status
Simulation time 122487186 ps
CPU time 0.72 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 195864 kb
Host smart-06a45baa-5630-4b4e-841b-a86a428b1a1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864925000 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.864925000
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.557806667
Short name T395
Test name
Test status
Simulation time 40993348 ps
CPU time 0.56 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:21:26 PM PST 23
Peak memory 192584 kb
Host smart-720c8747-e87c-4a91-96c2-9db6bbc95c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557806667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.557806667
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3686454860
Short name T439
Test name
Test status
Simulation time 148646003 ps
CPU time 0.56 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 183048 kb
Host smart-0ef80de9-6b72-4dfb-9d00-93c047c4b2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686454860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3686454860
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1414625293
Short name T42
Test name
Test status
Simulation time 121885082 ps
CPU time 0.75 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 193792 kb
Host smart-61c91f87-d6be-4975-9ed8-b56aafe5dd52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414625293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1414625293
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1745833868
Short name T486
Test name
Test status
Simulation time 125141351 ps
CPU time 2.47 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 197900 kb
Host smart-cc380b88-fdf7-47be-835e-962e039f7aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745833868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1745833868
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1747575702
Short name T416
Test name
Test status
Simulation time 124312704 ps
CPU time 0.77 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:19 PM PST 23
Peak memory 193864 kb
Host smart-de6419d9-f3d7-4c63-a155-c7d3f58143bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747575702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1747575702
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3735853224
Short name T430
Test name
Test status
Simulation time 72881398 ps
CPU time 0.99 seconds
Started Dec 20 12:20:10 PM PST 23
Finished Dec 20 12:20:13 PM PST 23
Peak memory 197624 kb
Host smart-ecdc5d4e-5aec-4025-b196-e0632ca0c6b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735853224 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3735853224
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.446951984
Short name T78
Test name
Test status
Simulation time 40873009 ps
CPU time 0.54 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:32 PM PST 23
Peak memory 183352 kb
Host smart-84d43adb-274d-4985-9687-391b94001a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446951984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.446951984
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2380785541
Short name T58
Test name
Test status
Simulation time 93348796 ps
CPU time 0.57 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:34 PM PST 23
Peak memory 183076 kb
Host smart-a7b89588-0304-428f-8f53-671817d3780d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380785541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2380785541
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3477024174
Short name T83
Test name
Test status
Simulation time 120514311 ps
CPU time 0.67 seconds
Started Dec 20 12:21:18 PM PST 23
Finished Dec 20 12:21:39 PM PST 23
Peak memory 193644 kb
Host smart-6ce10f92-c381-4f98-b89e-72056cf84534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477024174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3477024174
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.838854182
Short name T45
Test name
Test status
Simulation time 532041000 ps
CPU time 1.59 seconds
Started Dec 20 12:21:38 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 197332 kb
Host smart-3210eca9-5517-478a-a5e9-8a474b4fce30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838854182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.838854182
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1924866472
Short name T74
Test name
Test status
Simulation time 63756396 ps
CPU time 0.81 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 193900 kb
Host smart-29d23c1a-bc1f-417a-9591-bc994a64c51b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924866472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1924866472
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1485799278
Short name T46
Test name
Test status
Simulation time 133766071 ps
CPU time 0.75 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 196312 kb
Host smart-ce869f67-de29-45f1-8c9e-90affeb56745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485799278 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1485799278
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3112437770
Short name T460
Test name
Test status
Simulation time 13075261 ps
CPU time 0.52 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 182172 kb
Host smart-a22025ab-ee26-4b25-b28d-ae3c23d8fe0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112437770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3112437770
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2744041993
Short name T458
Test name
Test status
Simulation time 13543100 ps
CPU time 0.59 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 192168 kb
Host smart-29cb15c5-6975-4358-a859-6a81f9b39729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744041993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2744041993
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.798178161
Short name T405
Test name
Test status
Simulation time 377113524 ps
CPU time 3.47 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:40 PM PST 23
Peak memory 198100 kb
Host smart-0d5840da-749c-43c5-8164-2671fd2006c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798178161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.798178161
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.896334920
Short name T426
Test name
Test status
Simulation time 186584795 ps
CPU time 0.88 seconds
Started Dec 20 12:20:38 PM PST 23
Finished Dec 20 12:20:45 PM PST 23
Peak memory 194240 kb
Host smart-7dd4fcaa-86c1-4ebf-bea4-364a3c71ac32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896334920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.896334920
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.96238866
Short name T30
Test name
Test status
Simulation time 170759274 ps
CPU time 0.62 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 193188 kb
Host smart-fbf0abd4-b42d-4e99-9fc9-39872b850eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96238866 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.96238866
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1424669589
Short name T428
Test name
Test status
Simulation time 118758438 ps
CPU time 0.55 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:31 PM PST 23
Peak memory 183392 kb
Host smart-3042479f-5a09-44df-865c-d81da79c250a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424669589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1424669589
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1299089051
Short name T437
Test name
Test status
Simulation time 34805793 ps
CPU time 0.53 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 182992 kb
Host smart-ab3f7d85-fffa-44c2-9c75-f464663ed8fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299089051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1299089051
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3700047653
Short name T38
Test name
Test status
Simulation time 85389940 ps
CPU time 0.59 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 192640 kb
Host smart-6853bcca-32a4-472c-a22d-d2245260566c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700047653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3700047653
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2759915524
Short name T482
Test name
Test status
Simulation time 60907440 ps
CPU time 1.49 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:33 PM PST 23
Peak memory 198108 kb
Host smart-c61110cb-4adc-4986-b0ec-cc828cd1b3be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759915524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2759915524
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.461444559
Short name T472
Test name
Test status
Simulation time 938145399 ps
CPU time 1.3 seconds
Started Dec 20 12:21:16 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 195760 kb
Host smart-ca8696cc-e1f6-42e1-a9d1-c0dc79a05b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461444559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.461444559
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.856900226
Short name T411
Test name
Test status
Simulation time 26372594 ps
CPU time 1.07 seconds
Started Dec 20 12:20:41 PM PST 23
Finished Dec 20 12:20:47 PM PST 23
Peak memory 198100 kb
Host smart-ebb4ee23-60d3-4cf8-a4d4-bbb53569748a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856900226 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.856900226
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.187822606
Short name T392
Test name
Test status
Simulation time 32020226 ps
CPU time 0.51 seconds
Started Dec 20 12:20:31 PM PST 23
Finished Dec 20 12:20:36 PM PST 23
Peak memory 183316 kb
Host smart-52892f3b-a30a-4274-b703-4fc4642432c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187822606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.187822606
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.102077352
Short name T479
Test name
Test status
Simulation time 21102038 ps
CPU time 0.57 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 183124 kb
Host smart-b568f080-54f2-4b0d-a034-ee46cadd901f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102077352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.102077352
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1388127647
Short name T457
Test name
Test status
Simulation time 45901812 ps
CPU time 0.57 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:31 PM PST 23
Peak memory 192544 kb
Host smart-937e78a4-a637-4d6a-bcc2-4c679c7e248a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388127647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1388127647
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2631583945
Short name T450
Test name
Test status
Simulation time 165789638 ps
CPU time 2.43 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 198072 kb
Host smart-cb6c06b1-e524-4a67-9c58-eef4167c2593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631583945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2631583945
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4203813389
Short name T465
Test name
Test status
Simulation time 17011118 ps
CPU time 0.61 seconds
Started Dec 20 12:22:01 PM PST 23
Finished Dec 20 12:22:05 PM PST 23
Peak memory 194376 kb
Host smart-c87aff55-0319-4a11-8e87-644a01e62e2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203813389 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4203813389
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1724706692
Short name T12
Test name
Test status
Simulation time 24358474 ps
CPU time 0.59 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:37 PM PST 23
Peak memory 183500 kb
Host smart-588cda55-4de1-4903-8769-3708150d7356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724706692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1724706692
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2865860709
Short name T464
Test name
Test status
Simulation time 43955681 ps
CPU time 0.53 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:36 PM PST 23
Peak memory 182160 kb
Host smart-22d7b9fb-d988-463c-9ccb-e453ffdd081b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865860709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2865860709
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2103760530
Short name T80
Test name
Test status
Simulation time 257331784 ps
CPU time 0.75 seconds
Started Dec 20 12:20:31 PM PST 23
Finished Dec 20 12:20:37 PM PST 23
Peak memory 192304 kb
Host smart-31d7794a-eb28-4b00-9afd-08153f88855c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103760530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2103760530
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4257135345
Short name T476
Test name
Test status
Simulation time 101603591 ps
CPU time 1.99 seconds
Started Dec 20 12:21:28 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 197932 kb
Host smart-28c2e7ca-6d04-480b-a2c0-7fa0f1c750a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257135345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4257135345
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4251712648
Short name T429
Test name
Test status
Simulation time 157324129 ps
CPU time 0.88 seconds
Started Dec 20 12:20:05 PM PST 23
Finished Dec 20 12:20:07 PM PST 23
Peak memory 194232 kb
Host smart-cade130f-70e3-4e6f-9ced-4985a4b2c7e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251712648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4251712648
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1674629984
Short name T41
Test name
Test status
Simulation time 216270748 ps
CPU time 0.63 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 194404 kb
Host smart-0de4a05b-45fc-4191-ad55-9a99d682ea0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674629984 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1674629984
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1630333567
Short name T51
Test name
Test status
Simulation time 22429869 ps
CPU time 0.56 seconds
Started Dec 20 12:20:27 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 183328 kb
Host smart-f85947ff-2933-4d7b-aed7-375bee6c3118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630333567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1630333567
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.92918641
Short name T396
Test name
Test status
Simulation time 31614514 ps
CPU time 0.53 seconds
Started Dec 20 12:20:38 PM PST 23
Finished Dec 20 12:20:44 PM PST 23
Peak memory 182968 kb
Host smart-310a3295-563f-42a5-8894-5a817aa853de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92918641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.92918641
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1716991177
Short name T84
Test name
Test status
Simulation time 35649443 ps
CPU time 0.73 seconds
Started Dec 20 12:21:46 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 193736 kb
Host smart-aad04731-bbfc-4c39-b538-b659ce334754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716991177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1716991177
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2270960534
Short name T387
Test name
Test status
Simulation time 70051535 ps
CPU time 1.07 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 197828 kb
Host smart-341bfb2a-ab08-45bc-92de-8f5932ff6a74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270960534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2270960534
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4003920883
Short name T412
Test name
Test status
Simulation time 46905005 ps
CPU time 0.81 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 196632 kb
Host smart-f127715e-1b2d-4eef-b04c-fb395a572a00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003920883 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4003920883
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4150944639
Short name T397
Test name
Test status
Simulation time 47243802 ps
CPU time 0.53 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 182732 kb
Host smart-aa3c56e9-c63c-42a0-bb1b-03e260a6c53b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150944639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4150944639
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2686486923
Short name T73
Test name
Test status
Simulation time 12714264 ps
CPU time 0.5 seconds
Started Dec 20 12:21:49 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 182600 kb
Host smart-ba0ae561-ba4c-4ade-8c4b-b2c459007074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686486923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2686486923
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3675591370
Short name T37
Test name
Test status
Simulation time 31038967 ps
CPU time 0.7 seconds
Started Dec 20 12:21:45 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 192064 kb
Host smart-dcbe5bd2-df2b-46e9-90cc-0b0b41700b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675591370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3675591370
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2538763030
Short name T415
Test name
Test status
Simulation time 274305796 ps
CPU time 1.75 seconds
Started Dec 20 12:21:18 PM PST 23
Finished Dec 20 12:21:40 PM PST 23
Peak memory 198064 kb
Host smart-96d248de-9722-4f33-9012-a3b4ebdd3c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538763030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2538763030
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1048521172
Short name T399
Test name
Test status
Simulation time 175405451 ps
CPU time 1.12 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:39 PM PST 23
Peak memory 195584 kb
Host smart-d7174197-d6d2-46d4-8f87-bcabe189bb1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048521172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1048521172
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.661523384
Short name T72
Test name
Test status
Simulation time 144200997 ps
CPU time 0.82 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:39 PM PST 23
Peak memory 197196 kb
Host smart-eb5c675c-bd0a-42df-baec-d12d65ea2066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661523384 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.661523384
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.212006328
Short name T68
Test name
Test status
Simulation time 65343187 ps
CPU time 0.52 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 183160 kb
Host smart-32b118d4-b857-4429-8fac-23099f157b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212006328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.212006328
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3213501630
Short name T388
Test name
Test status
Simulation time 62784837 ps
CPU time 0.53 seconds
Started Dec 20 12:21:33 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 183096 kb
Host smart-e92709b4-bab9-467c-b4bb-a3246e8924a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213501630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3213501630
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.710494285
Short name T487
Test name
Test status
Simulation time 124339011 ps
CPU time 0.74 seconds
Started Dec 20 12:21:48 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 192300 kb
Host smart-e5a70bba-148b-45db-a6af-4bb619943c16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710494285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.710494285
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1318584652
Short name T33
Test name
Test status
Simulation time 62704567 ps
CPU time 2.78 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 198048 kb
Host smart-f0c939d0-4dac-497c-bba4-953d7d89d3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318584652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1318584652
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2764581733
Short name T473
Test name
Test status
Simulation time 68706615 ps
CPU time 1.02 seconds
Started Dec 20 12:21:19 PM PST 23
Finished Dec 20 12:21:40 PM PST 23
Peak memory 183572 kb
Host smart-92b1a5c4-ee34-4072-83d3-9dae89cdc482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764581733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2764581733
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4118853454
Short name T478
Test name
Test status
Simulation time 75394532 ps
CPU time 0.64 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:34 PM PST 23
Peak memory 194988 kb
Host smart-a6070ce4-4c44-425a-be29-3bfd10667ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118853454 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4118853454
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2546420637
Short name T444
Test name
Test status
Simulation time 49606819 ps
CPU time 0.55 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:34 PM PST 23
Peak memory 183420 kb
Host smart-fec7a7e2-abcd-4a5e-a188-1069ea2e93fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546420637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2546420637
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4198008483
Short name T54
Test name
Test status
Simulation time 27113879 ps
CPU time 0.53 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:22 PM PST 23
Peak memory 182688 kb
Host smart-34841a3e-a9d3-4684-affe-5d71127372be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198008483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4198008483
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3841080384
Short name T436
Test name
Test status
Simulation time 66831582 ps
CPU time 0.74 seconds
Started Dec 20 12:21:46 PM PST 23
Finished Dec 20 12:22:01 PM PST 23
Peak memory 193712 kb
Host smart-f6e47880-e350-4025-a694-0dc41d74ee90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841080384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3841080384
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2427507295
Short name T433
Test name
Test status
Simulation time 311427024 ps
CPU time 1.45 seconds
Started Dec 20 12:21:45 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 198104 kb
Host smart-6a200d3e-84ca-4fe6-bd94-9a23e6df79aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427507295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2427507295
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1156436647
Short name T86
Test name
Test status
Simulation time 431628622 ps
CPU time 1.28 seconds
Started Dec 20 12:21:15 PM PST 23
Finished Dec 20 12:21:36 PM PST 23
Peak memory 195880 kb
Host smart-1101c064-4044-4182-980f-9dfaa498cae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156436647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1156436647
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.684237050
Short name T77
Test name
Test status
Simulation time 32958822 ps
CPU time 0.79 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 193032 kb
Host smart-0000fd37-c6ce-4ea3-8a79-942ff9e0d8be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684237050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.684237050
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1396002973
Short name T477
Test name
Test status
Simulation time 245551470 ps
CPU time 2.28 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:21:27 PM PST 23
Peak memory 183696 kb
Host smart-9753310b-f901-4363-96dc-a7393f432079
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396002973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1396002973
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3222872428
Short name T65
Test name
Test status
Simulation time 15873620 ps
CPU time 0.53 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:19 PM PST 23
Peak memory 183372 kb
Host smart-d1da3992-602f-424f-88f6-c3cb3b4d0a98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222872428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3222872428
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.36289543
Short name T59
Test name
Test status
Simulation time 17937281 ps
CPU time 0.65 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 195080 kb
Host smart-f219f15d-4ec9-484f-92f0-e325cc7cf185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289543 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.36289543
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2501943633
Short name T446
Test name
Test status
Simulation time 33449640 ps
CPU time 0.56 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 183356 kb
Host smart-1ecc337c-6bb5-47d2-ac65-e2b12cf81db0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501943633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2501943633
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2012528694
Short name T406
Test name
Test status
Simulation time 11880074 ps
CPU time 0.62 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182968 kb
Host smart-22cd5a0f-a99a-4cc2-b4ff-37809ca3ef9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012528694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2012528694
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.241556767
Short name T431
Test name
Test status
Simulation time 20663469 ps
CPU time 0.79 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 192348 kb
Host smart-b5bbc22d-733c-4a38-a8cf-ee9dd09ca49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241556767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.241556767
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1303740540
Short name T389
Test name
Test status
Simulation time 292740106 ps
CPU time 2.1 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:49 PM PST 23
Peak memory 191812 kb
Host smart-8838a906-44b8-4ab6-b3ff-0297fcf4bc07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303740540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1303740540
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1278016013
Short name T462
Test name
Test status
Simulation time 77872383 ps
CPU time 0.83 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 183596 kb
Host smart-b5b9ce04-33d6-47ea-a667-de7ee44cc158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278016013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1278016013
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4161501496
Short name T49
Test name
Test status
Simulation time 22472401 ps
CPU time 0.52 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 183040 kb
Host smart-d4c3ea1b-f3ff-4fd9-a542-bc4e66fae21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161501496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4161501496
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1568441788
Short name T425
Test name
Test status
Simulation time 35430281 ps
CPU time 0.54 seconds
Started Dec 20 12:21:48 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 183020 kb
Host smart-6dc733f8-3414-4bff-84bc-3812cf330fea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568441788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1568441788
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.943735640
Short name T385
Test name
Test status
Simulation time 11985987 ps
CPU time 0.53 seconds
Started Dec 20 12:21:48 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 183044 kb
Host smart-ee2f9667-e995-4239-ad7a-9b865f077d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943735640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.943735640
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.910406875
Short name T47
Test name
Test status
Simulation time 17551838 ps
CPU time 0.54 seconds
Started Dec 20 12:21:35 PM PST 23
Finished Dec 20 12:21:50 PM PST 23
Peak memory 183048 kb
Host smart-54ec597a-1741-42cd-8eb4-7b564c615195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910406875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.910406875
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3511450330
Short name T417
Test name
Test status
Simulation time 80639194 ps
CPU time 0.54 seconds
Started Dec 20 12:21:47 PM PST 23
Finished Dec 20 12:22:01 PM PST 23
Peak memory 182956 kb
Host smart-4ae9e281-f683-4229-8159-e6e46548cb36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511450330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3511450330
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2368513400
Short name T435
Test name
Test status
Simulation time 15146536 ps
CPU time 0.53 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 182176 kb
Host smart-8ce94bf0-4363-43dd-a73b-bc0875af67cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368513400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2368513400
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2213848651
Short name T410
Test name
Test status
Simulation time 11961309 ps
CPU time 0.51 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:21:59 PM PST 23
Peak memory 182560 kb
Host smart-e2284037-4ffc-4451-bf53-5314a951cba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213848651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2213848651
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1284447021
Short name T408
Test name
Test status
Simulation time 17178555 ps
CPU time 0.58 seconds
Started Dec 20 12:21:51 PM PST 23
Finished Dec 20 12:22:03 PM PST 23
Peak memory 182956 kb
Host smart-909cb0e1-aa0d-46f6-a9fb-9e70a8da61ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284447021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1284447021
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.272357597
Short name T471
Test name
Test status
Simulation time 24163288 ps
CPU time 0.53 seconds
Started Dec 20 12:20:26 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 182100 kb
Host smart-4e28fd25-b0ed-450d-a241-2bc217ae88b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272357597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.272357597
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2365815789
Short name T451
Test name
Test status
Simulation time 23300981 ps
CPU time 0.53 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 182944 kb
Host smart-d17e80bc-4553-411d-8f74-737435917fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365815789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2365815789
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2699232431
Short name T56
Test name
Test status
Simulation time 85293855 ps
CPU time 0.61 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:32 PM PST 23
Peak memory 192436 kb
Host smart-ad84a7d3-575f-498d-a058-ae0f67ecf116
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699232431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2699232431
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.897643978
Short name T469
Test name
Test status
Simulation time 1448507403 ps
CPU time 3.49 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:37 PM PST 23
Peak memory 193192 kb
Host smart-049f0b57-7bac-4e31-a8ae-6d26bb8c399b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897643978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.897643978
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3004713181
Short name T40
Test name
Test status
Simulation time 15873474 ps
CPU time 0.55 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 183424 kb
Host smart-7e32462c-a6ea-49f0-bb8c-f1bbd385e162
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004713181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3004713181
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3886851091
Short name T391
Test name
Test status
Simulation time 21419536 ps
CPU time 0.98 seconds
Started Dec 20 12:21:36 PM PST 23
Finished Dec 20 12:21:51 PM PST 23
Peak memory 198116 kb
Host smart-141cd7ba-7471-447e-9305-aef5f108abaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886851091 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3886851091
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3497981839
Short name T448
Test name
Test status
Simulation time 13148567 ps
CPU time 0.58 seconds
Started Dec 20 12:21:38 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 183416 kb
Host smart-5d85a998-7efa-4fdd-bf81-4d5bd1f0b515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497981839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3497981839
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1806117040
Short name T384
Test name
Test status
Simulation time 54988208 ps
CPU time 0.53 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 183032 kb
Host smart-ec0f5b1c-6d60-4fb2-8dc4-02a7084677c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806117040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1806117040
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1931488101
Short name T449
Test name
Test status
Simulation time 125766315 ps
CPU time 0.76 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:32 PM PST 23
Peak memory 193888 kb
Host smart-fd67eba1-00f7-48a8-99ea-5a130771d473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931488101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1931488101
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3441932834
Short name T413
Test name
Test status
Simulation time 167192892 ps
CPU time 1.99 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 198216 kb
Host smart-cb39ddde-90a1-4070-881d-083902a75e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441932834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3441932834
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.57404628
Short name T454
Test name
Test status
Simulation time 214790296 ps
CPU time 1 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 195452 kb
Host smart-ab2d079c-a9a4-4bd1-be34-611ab9be9791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57404628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg
_err.57404628
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1802419396
Short name T386
Test name
Test status
Simulation time 27170668 ps
CPU time 0.54 seconds
Started Dec 20 12:21:27 PM PST 23
Finished Dec 20 12:21:45 PM PST 23
Peak memory 182916 kb
Host smart-4b78a6d7-0456-461f-b670-465a32047913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802419396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1802419396
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2049261562
Short name T484
Test name
Test status
Simulation time 14622580 ps
CPU time 0.53 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:33 PM PST 23
Peak memory 182184 kb
Host smart-b30c98aa-0640-4bcf-8e86-88555e0308d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049261562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2049261562
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4250152131
Short name T443
Test name
Test status
Simulation time 13138307 ps
CPU time 0.56 seconds
Started Dec 20 12:21:19 PM PST 23
Finished Dec 20 12:21:40 PM PST 23
Peak memory 182976 kb
Host smart-5a8e7e57-a40b-4a5e-985f-469ee91325c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250152131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4250152131
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3296864364
Short name T461
Test name
Test status
Simulation time 79360965 ps
CPU time 0.51 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 182668 kb
Host smart-463153c7-23dc-47af-980a-b94666fdd0d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296864364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3296864364
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.418585210
Short name T48
Test name
Test status
Simulation time 42657208 ps
CPU time 0.54 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 182988 kb
Host smart-90b5b4cb-85cd-4eea-972b-9f17c21ef831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418585210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.418585210
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.593531954
Short name T427
Test name
Test status
Simulation time 10806662 ps
CPU time 0.51 seconds
Started Dec 20 12:21:46 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 182580 kb
Host smart-9932e4e1-9a22-4930-a886-47796a0e4e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593531954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.593531954
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4011942159
Short name T432
Test name
Test status
Simulation time 41974870 ps
CPU time 0.51 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:17 PM PST 23
Peak memory 182632 kb
Host smart-e8239baa-e687-4a97-9522-51008cf89db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011942159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4011942159
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.140313740
Short name T452
Test name
Test status
Simulation time 11508252 ps
CPU time 0.52 seconds
Started Dec 20 12:21:35 PM PST 23
Finished Dec 20 12:21:50 PM PST 23
Peak memory 182976 kb
Host smart-50edf2b7-9417-41a2-b141-d2ab1d9a4294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140313740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.140313740
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2302152247
Short name T52
Test name
Test status
Simulation time 35460202 ps
CPU time 0.54 seconds
Started Dec 20 12:20:13 PM PST 23
Finished Dec 20 12:20:15 PM PST 23
Peak memory 182244 kb
Host smart-34d14dfe-e248-497a-8166-8722cc1c448f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302152247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2302152247
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.914825365
Short name T470
Test name
Test status
Simulation time 53054801 ps
CPU time 0.52 seconds
Started Dec 20 12:21:32 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 183032 kb
Host smart-ebd328f8-8065-4003-a4f9-8a0c1ed5693d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914825365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.914825365
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1372868924
Short name T57
Test name
Test status
Simulation time 89955422 ps
CPU time 0.72 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 183260 kb
Host smart-a9a097fb-4d57-4d38-a963-261a5f955bc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372868924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1372868924
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.142665910
Short name T402
Test name
Test status
Simulation time 199174277 ps
CPU time 1.48 seconds
Started Dec 20 12:21:33 PM PST 23
Finished Dec 20 12:21:49 PM PST 23
Peak memory 183728 kb
Host smart-3f1e67a1-b54d-47e0-bdef-c28ff7b5029a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142665910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.142665910
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3451423959
Short name T66
Test name
Test status
Simulation time 28536756 ps
CPU time 0.55 seconds
Started Dec 20 12:21:36 PM PST 23
Finished Dec 20 12:21:51 PM PST 23
Peak memory 183484 kb
Host smart-cc2e84e0-5b27-49c6-ae9b-551cec72d421
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451423959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3451423959
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3098466464
Short name T409
Test name
Test status
Simulation time 179912570 ps
CPU time 1.59 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 198316 kb
Host smart-aef1bb30-6ab5-4958-9df7-e6520b04ffd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098466464 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3098466464
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3148035506
Short name T403
Test name
Test status
Simulation time 23346409 ps
CPU time 0.52 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:27 PM PST 23
Peak memory 182960 kb
Host smart-c3dab0e1-8334-4a4f-a2ce-967850e8cfe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148035506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3148035506
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.4274233430
Short name T453
Test name
Test status
Simulation time 13854416 ps
CPU time 0.54 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:31 PM PST 23
Peak memory 182144 kb
Host smart-a0cdac7e-6987-46a3-8672-4ff7501ba6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274233430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.4274233430
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.776824802
Short name T434
Test name
Test status
Simulation time 21222051 ps
CPU time 0.76 seconds
Started Dec 20 12:21:42 PM PST 23
Finished Dec 20 12:21:55 PM PST 23
Peak memory 193928 kb
Host smart-3fddf30b-4e5f-43a6-a24a-e7cbbc8d832b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776824802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.776824802
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3822597497
Short name T34
Test name
Test status
Simulation time 100668945 ps
CPU time 2.39 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 197992 kb
Host smart-8e971e01-d91a-4548-b420-10f8a3a1b918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822597497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3822597497
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1802933410
Short name T85
Test name
Test status
Simulation time 266415483 ps
CPU time 0.77 seconds
Started Dec 20 12:21:15 PM PST 23
Finished Dec 20 12:21:36 PM PST 23
Peak memory 194276 kb
Host smart-41e5d2fa-21be-4f36-9133-f7d27a8e5945
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802933410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1802933410
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3086549568
Short name T393
Test name
Test status
Simulation time 39180439 ps
CPU time 0.54 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:28 PM PST 23
Peak memory 182148 kb
Host smart-07acc0a3-0930-491e-accb-d1fb493dc206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086549568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3086549568
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.696658452
Short name T407
Test name
Test status
Simulation time 37625192 ps
CPU time 0.52 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 182532 kb
Host smart-e77e9550-eec1-4913-9c0b-b6ab940007e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696658452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.696658452
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3914686954
Short name T75
Test name
Test status
Simulation time 94784918 ps
CPU time 0.51 seconds
Started Dec 20 12:21:18 PM PST 23
Finished Dec 20 12:21:39 PM PST 23
Peak memory 182900 kb
Host smart-3d6544bc-2927-4437-85ba-3acaeac8518d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914686954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3914686954
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4274305241
Short name T390
Test name
Test status
Simulation time 24320131 ps
CPU time 0.54 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 182140 kb
Host smart-b5108438-94d8-4638-a9ec-baa350813d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274305241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4274305241
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3654935761
Short name T480
Test name
Test status
Simulation time 48066933 ps
CPU time 0.55 seconds
Started Dec 20 12:20:47 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 182968 kb
Host smart-9d3f65d7-18d5-4479-b1f5-5fac3ea89ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654935761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3654935761
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3913266137
Short name T398
Test name
Test status
Simulation time 12901678 ps
CPU time 0.52 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:26 PM PST 23
Peak memory 182100 kb
Host smart-4efb9302-5ff2-4186-8136-768c56bcc57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913266137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3913266137
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1242878045
Short name T414
Test name
Test status
Simulation time 15872718 ps
CPU time 0.6 seconds
Started Dec 20 12:21:39 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 183072 kb
Host smart-960ff0e1-8510-4714-be8b-4ab123226bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242878045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1242878045
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4045189848
Short name T418
Test name
Test status
Simulation time 94975612 ps
CPU time 0.55 seconds
Started Dec 20 12:20:18 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 183096 kb
Host smart-2164ece9-a235-4a04-8ace-4a79c6bb51e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045189848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4045189848
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3375526016
Short name T481
Test name
Test status
Simulation time 22703307 ps
CPU time 0.57 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 183012 kb
Host smart-d50c5cf4-0a91-4f0c-ba17-5ee9f7af036c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375526016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3375526016
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.944749500
Short name T419
Test name
Test status
Simulation time 55465263 ps
CPU time 0.53 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 182976 kb
Host smart-8c2749dd-5013-4f34-8a6f-a85b2de54627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944749500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.944749500
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3326297221
Short name T440
Test name
Test status
Simulation time 33936318 ps
CPU time 0.67 seconds
Started Dec 20 12:20:15 PM PST 23
Finished Dec 20 12:20:17 PM PST 23
Peak memory 196200 kb
Host smart-c9f73a7b-7ca2-4d25-8ac0-a4b158b6558e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326297221 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3326297221
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2148582812
Short name T64
Test name
Test status
Simulation time 22405452 ps
CPU time 0.52 seconds
Started Dec 20 12:20:09 PM PST 23
Finished Dec 20 12:20:10 PM PST 23
Peak memory 182928 kb
Host smart-66c7fbb1-de14-4359-ace5-4bcdccf1ac50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148582812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2148582812
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.32582391
Short name T466
Test name
Test status
Simulation time 43486767 ps
CPU time 0.55 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:37 PM PST 23
Peak memory 183028 kb
Host smart-1593ec11-2f91-4886-bcac-2a04860cdf9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32582391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.32582391
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2470487324
Short name T81
Test name
Test status
Simulation time 21337657 ps
CPU time 0.69 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:21:15 PM PST 23
Peak memory 191828 kb
Host smart-6ec84fb8-d00b-4fad-bba4-719fd75fb359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470487324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2470487324
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4120277919
Short name T441
Test name
Test status
Simulation time 567524530 ps
CPU time 1.48 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 198096 kb
Host smart-b2691547-6aa3-42cb-861a-eae1910a7426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120277919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4120277919
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1689706398
Short name T442
Test name
Test status
Simulation time 43227087 ps
CPU time 0.78 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 193916 kb
Host smart-bc3412ea-72d7-4980-b8f8-c2dbf34bbf6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689706398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1689706398
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3067600509
Short name T394
Test name
Test status
Simulation time 24211772 ps
CPU time 1.09 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 198184 kb
Host smart-1dd7c95a-c131-4692-a456-8f9d67d196f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067600509 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3067600509
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.643156922
Short name T62
Test name
Test status
Simulation time 27188897 ps
CPU time 0.54 seconds
Started Dec 20 12:20:27 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 183336 kb
Host smart-308cceac-7d93-40c9-a17b-eac52c485c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643156922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.643156922
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4023820232
Short name T421
Test name
Test status
Simulation time 110560581 ps
CPU time 0.52 seconds
Started Dec 20 12:21:43 PM PST 23
Finished Dec 20 12:21:58 PM PST 23
Peak memory 182580 kb
Host smart-fcec00e0-c7a4-4f92-9391-3d40eefc48a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023820232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4023820232
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1980740324
Short name T82
Test name
Test status
Simulation time 109629650 ps
CPU time 0.75 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 192256 kb
Host smart-880d580e-cc81-488f-b5b2-9162bce7c50c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980740324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1980740324
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2758744264
Short name T60
Test name
Test status
Simulation time 79776211 ps
CPU time 0.95 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 191532 kb
Host smart-83c58e08-e5ca-4b86-9401-8ac5e2248b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758744264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2758744264
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2937311057
Short name T404
Test name
Test status
Simulation time 158902696 ps
CPU time 1.06 seconds
Started Dec 20 12:20:11 PM PST 23
Finished Dec 20 12:20:14 PM PST 23
Peak memory 195556 kb
Host smart-97d67281-19eb-4571-af9c-843d3c56752a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937311057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2937311057
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.938699739
Short name T447
Test name
Test status
Simulation time 62438113 ps
CPU time 0.63 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:40 PM PST 23
Peak memory 195000 kb
Host smart-a31c3772-2e50-4eec-ac18-90d7b6dc9db7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938699739 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.938699739
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1413003467
Short name T63
Test name
Test status
Simulation time 13025108 ps
CPU time 0.56 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 183204 kb
Host smart-b9332590-5b22-4287-9dd7-f3831288f9a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413003467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1413003467
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.474485556
Short name T459
Test name
Test status
Simulation time 15330335 ps
CPU time 0.54 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 182152 kb
Host smart-c2b0e8c2-9b9a-46f2-8726-afab6ca2170b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474485556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.474485556
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2857153403
Short name T463
Test name
Test status
Simulation time 15760252 ps
CPU time 0.66 seconds
Started Dec 20 12:20:13 PM PST 23
Finished Dec 20 12:20:15 PM PST 23
Peak memory 192568 kb
Host smart-29c895c3-9ce8-41f1-b0b6-cb99f0e3cebf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857153403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2857153403
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.351057413
Short name T400
Test name
Test status
Simulation time 461837642 ps
CPU time 2.32 seconds
Started Dec 20 12:20:40 PM PST 23
Finished Dec 20 12:20:48 PM PST 23
Peak memory 198200 kb
Host smart-49b4a35a-1471-4ce2-b58d-84154862293c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351057413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.351057413
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2587890750
Short name T29
Test name
Test status
Simulation time 158219683 ps
CPU time 0.78 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 193780 kb
Host smart-ad28a77b-31bd-48d3-b499-6643fabf0bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587890750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2587890750
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1411129742
Short name T468
Test name
Test status
Simulation time 19710282 ps
CPU time 0.85 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 191772 kb
Host smart-875a9d07-966c-4b59-999b-ccb66a6295f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411129742 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1411129742
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.305502709
Short name T455
Test name
Test status
Simulation time 32969895 ps
CPU time 0.51 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:32 PM PST 23
Peak memory 182648 kb
Host smart-0209920d-148d-4a45-b095-668bd6f20605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305502709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.305502709
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.418534852
Short name T420
Test name
Test status
Simulation time 32203233 ps
CPU time 0.54 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 183004 kb
Host smart-0c43c1ca-8feb-446f-82f8-4953cab6513e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418534852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.418534852
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2184134999
Short name T445
Test name
Test status
Simulation time 51769977 ps
CPU time 0.66 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 192280 kb
Host smart-6547b2db-1639-4d39-9c6d-57814a5df0cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184134999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2184134999
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1883940237
Short name T401
Test name
Test status
Simulation time 401156224 ps
CPU time 1.45 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:41 PM PST 23
Peak memory 198092 kb
Host smart-1256b030-0676-4d4d-a9b5-19a4dbe33cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883940237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1883940237
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.327970193
Short name T424
Test name
Test status
Simulation time 83020399 ps
CPU time 0.79 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 183480 kb
Host smart-db4af139-7cee-46cb-981d-4e4543d5a82b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327970193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.327970193
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.736911850
Short name T50
Test name
Test status
Simulation time 40910160 ps
CPU time 0.75 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 196256 kb
Host smart-b35713d0-fc83-4885-9b9b-2901a8b46f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736911850 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.736911850
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.240988060
Short name T422
Test name
Test status
Simulation time 12393501 ps
CPU time 0.56 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 183316 kb
Host smart-63b98817-2ba4-44b5-a6e5-d5ac693c60cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240988060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.240988060
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.915792078
Short name T423
Test name
Test status
Simulation time 13516983 ps
CPU time 0.52 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 182572 kb
Host smart-23af903c-944a-4b3c-91e6-0179581179a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915792078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.915792078
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1679717699
Short name T53
Test name
Test status
Simulation time 81570146 ps
CPU time 0.79 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 193928 kb
Host smart-2e97ae10-da01-48a9-87ca-5865d9ef3511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679717699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1679717699
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1819294063
Short name T467
Test name
Test status
Simulation time 183148472 ps
CPU time 1.14 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:31 PM PST 23
Peak memory 197876 kb
Host smart-48eea49f-7f83-4a38-9eb0-2932b512debc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819294063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1819294063
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1783294594
Short name T70
Test name
Test status
Simulation time 45157158 ps
CPU time 0.84 seconds
Started Dec 20 12:21:34 PM PST 23
Finished Dec 20 12:21:49 PM PST 23
Peak memory 183444 kb
Host smart-d900adf1-b2c8-4e84-8753-1a648140bebd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783294594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1783294594
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.915832529
Short name T319
Test name
Test status
Simulation time 855953571166 ps
CPU time 795.4 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:53:41 PM PST 23
Peak memory 183020 kb
Host smart-a7b12f04-695b-4b27-9cc0-46727d9c7a60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915832529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.915832529
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3612561968
Short name T522
Test name
Test status
Simulation time 184537476314 ps
CPU time 292.3 seconds
Started Dec 20 12:39:01 PM PST 23
Finished Dec 20 12:44:55 PM PST 23
Peak memory 183040 kb
Host smart-24600e15-dd14-4fc0-99f8-a52f44927799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612561968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3612561968
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1754163045
Short name T592
Test name
Test status
Simulation time 142099898806 ps
CPU time 757.87 seconds
Started Dec 20 12:38:53 PM PST 23
Finished Dec 20 12:52:32 PM PST 23
Peak memory 182992 kb
Host smart-6406a249-2887-4743-973e-046fcc186690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754163045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1754163045
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3626087263
Short name T566
Test name
Test status
Simulation time 198609711581 ps
CPU time 868.13 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 206904 kb
Host smart-53138aec-f093-41f7-981a-cea2ba462477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626087263 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3626087263
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2294517142
Short name T329
Test name
Test status
Simulation time 5534846915 ps
CPU time 10.09 seconds
Started Dec 20 12:39:17 PM PST 23
Finished Dec 20 12:40:37 PM PST 23
Peak memory 182872 kb
Host smart-3cb96874-2693-4f80-91c1-22d6472e50a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294517142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2294517142
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1420060976
Short name T529
Test name
Test status
Simulation time 324700900205 ps
CPU time 118.24 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 183036 kb
Host smart-2c492e87-5560-441a-ad8e-1b611f964069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420060976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1420060976
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.526953087
Short name T15
Test name
Test status
Simulation time 214676296 ps
CPU time 0.86 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:40:30 PM PST 23
Peak memory 212804 kb
Host smart-44a20bfc-ee4b-46f8-ac17-baacbdf7898d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526953087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.526953087
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1334659170
Short name T360
Test name
Test status
Simulation time 350109455746 ps
CPU time 320.28 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:46:11 PM PST 23
Peak memory 183064 kb
Host smart-d59fef51-2aa4-4ca8-bbe8-3f124d9123b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334659170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1334659170
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.536322966
Short name T501
Test name
Test status
Simulation time 399452459290 ps
CPU time 91.61 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 183020 kb
Host smart-67bf87df-bdac-4eff-92f2-43016d67161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536322966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.536322966
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1692623514
Short name T539
Test name
Test status
Simulation time 171350282887 ps
CPU time 229.93 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:44:30 PM PST 23
Peak memory 205764 kb
Host smart-341b0a8e-9f68-4649-a8fa-9b709b81c497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692623514 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1692623514
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2655281309
Short name T187
Test name
Test status
Simulation time 50629834716 ps
CPU time 87.53 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:42:31 PM PST 23
Peak memory 183060 kb
Host smart-c2f59998-5676-4ad1-a811-7832e09b9658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655281309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2655281309
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1847742882
Short name T263
Test name
Test status
Simulation time 246623094424 ps
CPU time 102.63 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 191224 kb
Host smart-1f311cca-a259-4189-9978-ecebc6a7a757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847742882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1847742882
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.8488033
Short name T312
Test name
Test status
Simulation time 66897561636 ps
CPU time 114.45 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:42:53 PM PST 23
Peak memory 191076 kb
Host smart-4ade38ec-e7d1-452e-b789-4f704cc5468f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8488033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.8488033
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3890708486
Short name T292
Test name
Test status
Simulation time 90446115152 ps
CPU time 152.73 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:43:43 PM PST 23
Peak memory 191124 kb
Host smart-3efb4b2f-1991-43e7-9669-1b18b21c51c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890708486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3890708486
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1986057433
Short name T324
Test name
Test status
Simulation time 78936769262 ps
CPU time 62.79 seconds
Started Dec 20 12:39:58 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 182976 kb
Host smart-8a770682-5d8f-43a7-a75d-8d3b48b8dd0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986057433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1986057433
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.140793069
Short name T211
Test name
Test status
Simulation time 379983623084 ps
CPU time 127.93 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:43:05 PM PST 23
Peak memory 191236 kb
Host smart-c34adfd4-f1b1-4996-846b-8e8360c620ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140793069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.140793069
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4169426651
Short name T493
Test name
Test status
Simulation time 78800368272 ps
CPU time 109.7 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:42:30 PM PST 23
Peak memory 183000 kb
Host smart-136d9479-7276-4d46-bf3f-7e8e2d8e77c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169426651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4169426651
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1597444337
Short name T380
Test name
Test status
Simulation time 359505027 ps
CPU time 0.72 seconds
Started Dec 20 12:39:11 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 191108 kb
Host smart-a58562fb-a6a9-4cc2-a3fc-17489c046259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597444337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1597444337
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2572691460
Short name T497
Test name
Test status
Simulation time 75631901510 ps
CPU time 99.59 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:42:31 PM PST 23
Peak memory 182784 kb
Host smart-10b081bc-da52-4097-8aa4-e19db939e9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572691460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2572691460
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.947871373
Short name T498
Test name
Test status
Simulation time 77869756348 ps
CPU time 409.38 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:47:43 PM PST 23
Peak memory 197556 kb
Host smart-06c12684-10df-4064-b595-141a182125dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947871373 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.947871373
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.1519142816
Short name T250
Test name
Test status
Simulation time 601245795328 ps
CPU time 1215.86 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 01:01:24 PM PST 23
Peak memory 193792 kb
Host smart-2a633229-de00-46ff-9166-7c7d351afe73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519142816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1519142816
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1931387923
Short name T266
Test name
Test status
Simulation time 11532577430 ps
CPU time 15.6 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 183036 kb
Host smart-2d7b9a86-8d12-4d64-8e5a-53adc0b68e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931387923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1931387923
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.170063905
Short name T107
Test name
Test status
Simulation time 289736348007 ps
CPU time 275.99 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:45:41 PM PST 23
Peak memory 191136 kb
Host smart-22011c31-ffea-442a-b71e-52862916a88f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170063905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.170063905
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3164231052
Short name T118
Test name
Test status
Simulation time 233504984940 ps
CPU time 103.53 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 191140 kb
Host smart-f2c66acd-16f8-47de-b9bc-6ca1ef178532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164231052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3164231052
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3510993871
Short name T225
Test name
Test status
Simulation time 176402393658 ps
CPU time 365.55 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:47:09 PM PST 23
Peak memory 191140 kb
Host smart-59b90800-3510-4f01-82e0-63b6d7c6f271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510993871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3510993871
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3246242871
Short name T157
Test name
Test status
Simulation time 1323603244099 ps
CPU time 473.84 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:48:14 PM PST 23
Peak memory 183056 kb
Host smart-cb95ff90-ab12-4aea-9202-d746ca2a8833
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246242871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3246242871
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random.3896084561
Short name T257
Test name
Test status
Simulation time 590665542562 ps
CPU time 636.51 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:51:10 PM PST 23
Peak memory 191088 kb
Host smart-0fd19378-7384-48c9-907c-615f2de09e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896084561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3896084561
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3266138554
Short name T582
Test name
Test status
Simulation time 253343437291 ps
CPU time 79.74 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 191184 kb
Host smart-d126c2b2-b4b3-412d-b2fa-da3bdbb34cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266138554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3266138554
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3337941056
Short name T137
Test name
Test status
Simulation time 56485725469 ps
CPU time 451.55 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:48:16 PM PST 23
Peak memory 197644 kb
Host smart-97de12d0-6a50-4e42-85ca-4956b2023076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337941056 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3337941056
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.436071227
Short name T161
Test name
Test status
Simulation time 170982394743 ps
CPU time 654.68 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:51:57 PM PST 23
Peak memory 191176 kb
Host smart-68483f8d-c096-455e-80bf-40eaac38891b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436071227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.436071227
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2883858443
Short name T374
Test name
Test status
Simulation time 112475352033 ps
CPU time 93.39 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:42:36 PM PST 23
Peak memory 193264 kb
Host smart-27383312-42cb-44c2-bb4b-d977f53b4b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883858443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2883858443
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3626153930
Short name T590
Test name
Test status
Simulation time 103145978389 ps
CPU time 68.78 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 182884 kb
Host smart-5eee008a-4eed-47d9-a6fb-5ca57dac69db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626153930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3626153930
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.54512390
Short name T135
Test name
Test status
Simulation time 337485688795 ps
CPU time 160.83 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:43:54 PM PST 23
Peak memory 191220 kb
Host smart-68f13365-5260-482f-92eb-4e10a1a3d2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54512390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.54512390
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2401707795
Short name T604
Test name
Test status
Simulation time 63868285591 ps
CPU time 209.27 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:44:36 PM PST 23
Peak memory 191216 kb
Host smart-87c3453b-e193-487b-bce3-67dc5c1fd796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401707795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2401707795
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.80138481
Short name T280
Test name
Test status
Simulation time 1471936080655 ps
CPU time 630.59 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:51:33 PM PST 23
Peak memory 194368 kb
Host smart-d4e47874-4032-4ead-8d89-f14adb48effa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80138481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.80138481
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1729267097
Short name T347
Test name
Test status
Simulation time 131754698888 ps
CPU time 549.81 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 191212 kb
Host smart-5ef2c588-fb63-435f-b607-c2783b2441b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729267097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1729267097
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3143541005
Short name T206
Test name
Test status
Simulation time 51331580967 ps
CPU time 52.71 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 182868 kb
Host smart-109f54e4-7bd8-4873-ad1a-ce760868aee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143541005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3143541005
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.964594105
Short name T134
Test name
Test status
Simulation time 267751131241 ps
CPU time 1192.11 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 01:00:23 PM PST 23
Peak memory 191220 kb
Host smart-88b6e8f0-7665-4a5f-be91-6955246fb946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964594105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.964594105
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3988776230
Short name T589
Test name
Test status
Simulation time 7163464228 ps
CPU time 8.84 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:40:54 PM PST 23
Peak memory 191088 kb
Host smart-33a4dfca-5fd0-4e5b-993b-d5f2d901e6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988776230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3988776230
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2259516699
Short name T357
Test name
Test status
Simulation time 503529950658 ps
CPU time 545.13 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:50:08 PM PST 23
Peak memory 191220 kb
Host smart-fae8ff3c-ad42-4a3c-ab4e-0e942e3988bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259516699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2259516699
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2334677675
Short name T223
Test name
Test status
Simulation time 42210760646 ps
CPU time 132.58 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:43:16 PM PST 23
Peak memory 190708 kb
Host smart-169b9a08-f05c-4cca-bc73-3c07e18224d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334677675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2334677675
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1218050818
Short name T130
Test name
Test status
Simulation time 334582327003 ps
CPU time 1061.04 seconds
Started Dec 20 12:40:34 PM PST 23
Finished Dec 20 12:59:21 PM PST 23
Peak memory 191212 kb
Host smart-ef775bdc-ceee-4356-9aa6-00e4e0a480b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218050818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1218050818
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1648195306
Short name T320
Test name
Test status
Simulation time 497430665649 ps
CPU time 111.79 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 191252 kb
Host smart-8564d503-0c64-452d-b294-6292ced77421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648195306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1648195306
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.749399199
Short name T564
Test name
Test status
Simulation time 63088297182 ps
CPU time 1774.87 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 01:10:44 PM PST 23
Peak memory 191120 kb
Host smart-3aaf4a7f-7c5a-462f-bd4c-3e95510f2700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749399199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.749399199
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.4256789561
Short name T323
Test name
Test status
Simulation time 234144791701 ps
CPU time 1096.57 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:59:28 PM PST 23
Peak memory 191144 kb
Host smart-caa4e04c-7f81-4776-a136-6c2ca6c3ae74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256789561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.4256789561
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4167971357
Short name T120
Test name
Test status
Simulation time 1307836758692 ps
CPU time 257.28 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:45:29 PM PST 23
Peak memory 191268 kb
Host smart-ef0bdda4-ad48-4277-9809-d6bd1d42cdbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167971357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4167971357
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3234583538
Short name T110
Test name
Test status
Simulation time 1186250136342 ps
CPU time 727.06 seconds
Started Dec 20 12:39:30 PM PST 23
Finished Dec 20 12:52:49 PM PST 23
Peak memory 182888 kb
Host smart-d2615843-5caa-4200-8822-d1a8c25d3464
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234583538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3234583538
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3214746959
Short name T588
Test name
Test status
Simulation time 26907011300 ps
CPU time 42.48 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 183064 kb
Host smart-ae1e7fa3-6483-41ae-8ec7-cf307e3ee78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214746959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3214746959
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2786411344
Short name T202
Test name
Test status
Simulation time 236773091652 ps
CPU time 293.14 seconds
Started Dec 20 12:39:17 PM PST 23
Finished Dec 20 12:45:20 PM PST 23
Peak memory 193928 kb
Host smart-48054753-239d-4abd-bb46-24beb2007659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786411344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2786411344
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3176057583
Short name T297
Test name
Test status
Simulation time 133546024486 ps
CPU time 193.32 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:44:04 PM PST 23
Peak memory 194772 kb
Host smart-672fed7a-15f5-4316-a55b-c20059a1c5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176057583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3176057583
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.4226797029
Short name T503
Test name
Test status
Simulation time 23171581996 ps
CPU time 248.85 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:45:15 PM PST 23
Peak memory 197700 kb
Host smart-5e75c5c2-a937-45ea-8895-b4b5edef3331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226797029 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.4226797029
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.4149907116
Short name T248
Test name
Test status
Simulation time 62443054094 ps
CPU time 110.21 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:43:00 PM PST 23
Peak memory 182988 kb
Host smart-1dcdb0f2-e3c8-4455-bdc3-624ed84da968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149907116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4149907116
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1703557935
Short name T253
Test name
Test status
Simulation time 819270738744 ps
CPU time 272.21 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:45:35 PM PST 23
Peak memory 194292 kb
Host smart-3a9a89e7-4973-426b-bce5-03927cbae1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703557935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1703557935
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.151389826
Short name T6
Test name
Test status
Simulation time 51158228258 ps
CPU time 212.24 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:44:25 PM PST 23
Peak memory 194440 kb
Host smart-fb514118-46dd-4370-a23e-04c15cd06e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151389826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.151389826
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.4114422695
Short name T123
Test name
Test status
Simulation time 22677839489 ps
CPU time 40.75 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 191056 kb
Host smart-374a790d-0cf0-401f-8572-173d2b7170c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114422695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4114422695
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4267609186
Short name T310
Test name
Test status
Simulation time 199908045309 ps
CPU time 1541.91 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 01:06:47 PM PST 23
Peak memory 182896 kb
Host smart-02781639-6b6f-4e10-aaec-4510b280e309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267609186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4267609186
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2496023102
Short name T545
Test name
Test status
Simulation time 159208955533 ps
CPU time 280.48 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:45:12 PM PST 23
Peak memory 182912 kb
Host smart-bd1d937d-2a46-4d0d-82b8-2283e276544f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496023102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2496023102
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2534066066
Short name T524
Test name
Test status
Simulation time 49314580478 ps
CPU time 54.3 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:41:48 PM PST 23
Peak memory 183008 kb
Host smart-f9738b9f-90e4-4606-b8a2-224c7facf51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534066066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2534066066
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1667279565
Short name T600
Test name
Test status
Simulation time 380880413034 ps
CPU time 1185.81 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 01:00:21 PM PST 23
Peak memory 183020 kb
Host smart-976c52cc-954a-4537-9ad7-b4ef7c530186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667279565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1667279565
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.16068285
Short name T301
Test name
Test status
Simulation time 582877877709 ps
CPU time 1805.25 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 01:10:57 PM PST 23
Peak memory 214036 kb
Host smart-60254ce5-407d-4a8c-9320-6c89665e07cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16068285 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.16068285
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1236452790
Short name T219
Test name
Test status
Simulation time 175250690735 ps
CPU time 43.54 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 182888 kb
Host smart-83c9ab17-bcbf-4b4f-9d6c-7685f984437c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236452790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1236452790
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2088050357
Short name T228
Test name
Test status
Simulation time 174702155235 ps
CPU time 200.69 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:44:17 PM PST 23
Peak memory 191164 kb
Host smart-9bedb856-c69f-477d-852a-091bd7d5e069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088050357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2088050357
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1286506372
Short name T290
Test name
Test status
Simulation time 304112500355 ps
CPU time 149.95 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:43:39 PM PST 23
Peak memory 193636 kb
Host smart-bcdfa570-2698-4b16-849d-990a454dfa8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286506372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1286506372
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1348676678
Short name T268
Test name
Test status
Simulation time 805667417854 ps
CPU time 1911.19 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 01:12:54 PM PST 23
Peak memory 191128 kb
Host smart-b8921237-ec8d-468a-a3a8-63e2675fc82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348676678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1348676678
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1388035911
Short name T333
Test name
Test status
Simulation time 505973094113 ps
CPU time 257 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:45:21 PM PST 23
Peak memory 191140 kb
Host smart-2d546a7e-f47a-4d76-855e-2fe387e03845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388035911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1388035911
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3202845603
Short name T143
Test name
Test status
Simulation time 13315307634 ps
CPU time 92.05 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:42:30 PM PST 23
Peak memory 191204 kb
Host smart-a86424e5-99f6-48b7-b30d-09625556ccca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202845603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3202845603
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.920782386
Short name T234
Test name
Test status
Simulation time 60407382735 ps
CPU time 70.2 seconds
Started Dec 20 12:40:33 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 191168 kb
Host smart-65b60c0a-a7f3-419c-8918-66e426355e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920782386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.920782386
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.920889498
Short name T208
Test name
Test status
Simulation time 908248641310 ps
CPU time 1539.19 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 01:06:38 PM PST 23
Peak memory 191240 kb
Host smart-e11da1f6-2216-41f0-a2a6-d2894d4dd8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920889498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.920889498
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.267310214
Short name T88
Test name
Test status
Simulation time 88812111077 ps
CPU time 340.52 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:46:43 PM PST 23
Peak memory 193216 kb
Host smart-16ac8e79-f362-4b4c-8022-2c9e45316cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267310214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.267310214
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3892772600
Short name T330
Test name
Test status
Simulation time 42668139210 ps
CPU time 80.1 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 192556 kb
Host smart-73f890fb-32bd-4fd0-a51f-b1f28aa6ad8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892772600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3892772600
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.693284523
Short name T585
Test name
Test status
Simulation time 1667816084269 ps
CPU time 947.36 seconds
Started Dec 20 12:39:26 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 183000 kb
Host smart-8e27b788-ead8-4a8d-a00b-7851d98cdaa0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693284523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.693284523
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2391327117
Short name T542
Test name
Test status
Simulation time 63928851617 ps
CPU time 60.96 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 183004 kb
Host smart-9510fea2-c125-4c6e-a4c7-7cc9cf29917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391327117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2391327117
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3275016477
Short name T177
Test name
Test status
Simulation time 82577864273 ps
CPU time 210.46 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:44:06 PM PST 23
Peak memory 193560 kb
Host smart-cfdfc5d1-3d55-45b5-9b7e-7d089b8b49d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275016477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3275016477
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1828838072
Short name T326
Test name
Test status
Simulation time 55077183629 ps
CPU time 79.54 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 191272 kb
Host smart-679d5562-d98a-423e-a69f-012908df3a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828838072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1828838072
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1035581434
Short name T611
Test name
Test status
Simulation time 255644353414 ps
CPU time 441.9 seconds
Started Dec 20 12:39:43 PM PST 23
Finished Dec 20 12:48:17 PM PST 23
Peak memory 191272 kb
Host smart-2898b9a6-4d1f-4644-8a28-bfc5aa5455ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035581434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1035581434
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3713333127
Short name T340
Test name
Test status
Simulation time 244686987207 ps
CPU time 480.01 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:48:29 PM PST 23
Peak memory 206024 kb
Host smart-54bfe021-2e2f-48bb-88ff-a50c426d875f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713333127 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3713333127
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.51462320
Short name T260
Test name
Test status
Simulation time 113835909819 ps
CPU time 54.11 seconds
Started Dec 20 12:40:07 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 191208 kb
Host smart-0953575e-6957-4342-a10d-142582d7653c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51462320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.51462320
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1895020221
Short name T122
Test name
Test status
Simulation time 294454071764 ps
CPU time 481.63 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:49:12 PM PST 23
Peak memory 191332 kb
Host smart-40239072-bee2-4334-a339-9f2cb5c392a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895020221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1895020221
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2944152838
Short name T194
Test name
Test status
Simulation time 259917728347 ps
CPU time 263.75 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:45:50 PM PST 23
Peak memory 191072 kb
Host smart-88e152ac-1bf0-41aa-8b90-7d1b66ab0c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944152838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2944152838
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2893443551
Short name T150
Test name
Test status
Simulation time 82356622035 ps
CPU time 72.69 seconds
Started Dec 20 12:40:29 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 191020 kb
Host smart-1e53093f-449b-47f6-8a7d-1ddb55f32797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893443551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2893443551
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2404513179
Short name T231
Test name
Test status
Simulation time 1758532332782 ps
CPU time 704.03 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 193664 kb
Host smart-56e2f7c4-9c20-486f-b5f1-28a691c9cdfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404513179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2404513179
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.82186350
Short name T203
Test name
Test status
Simulation time 235003453520 ps
CPU time 1791.81 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 01:10:51 PM PST 23
Peak memory 193264 kb
Host smart-3b446527-7bcd-4c15-87e9-7c2345dc4bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82186350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.82186350
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2854413495
Short name T121
Test name
Test status
Simulation time 103240262604 ps
CPU time 107.46 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:43:11 PM PST 23
Peak memory 191012 kb
Host smart-587b11cc-1d04-4d1c-8a2e-9513b410ecde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854413495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2854413495
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3629482939
Short name T536
Test name
Test status
Simulation time 130806696434 ps
CPU time 60.85 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 183020 kb
Host smart-01bdb0b1-cfae-4f77-889f-2ec792cf383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629482939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3629482939
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.187152281
Short name T328
Test name
Test status
Simulation time 22256341064 ps
CPU time 268.57 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:44:59 PM PST 23
Peak memory 183012 kb
Host smart-8841ea5c-ba1f-48a8-b784-53bf88b89ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187152281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.187152281
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4271599821
Short name T351
Test name
Test status
Simulation time 50923440932 ps
CPU time 326.35 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:46:02 PM PST 23
Peak memory 183028 kb
Host smart-68a2c0f7-5ee4-4727-9caf-9706b25eeb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271599821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4271599821
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3677257479
Short name T594
Test name
Test status
Simulation time 588188635954 ps
CPU time 481.09 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:48:50 PM PST 23
Peak memory 191228 kb
Host smart-47121351-e8ab-4418-88f9-b26c3d3c3554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677257479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3677257479
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.333300630
Short name T533
Test name
Test status
Simulation time 44227511824 ps
CPU time 221.71 seconds
Started Dec 20 12:39:21 PM PST 23
Finished Dec 20 12:44:16 PM PST 23
Peak memory 197588 kb
Host smart-5fafafb6-898e-4279-a5fc-8d3d649cecef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333300630 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.333300630
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2909004617
Short name T348
Test name
Test status
Simulation time 45379306958 ps
CPU time 76.12 seconds
Started Dec 20 12:40:03 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 191212 kb
Host smart-3878d6ab-c1a4-48e0-945a-da39357af427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909004617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2909004617
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.77381075
Short name T579
Test name
Test status
Simulation time 36403526861 ps
CPU time 36.28 seconds
Started Dec 20 12:40:16 PM PST 23
Finished Dec 20 12:41:52 PM PST 23
Peak memory 182972 kb
Host smart-23362bb3-721c-4237-84c5-a3ca7f3b94de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77381075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.77381075
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.350419284
Short name T245
Test name
Test status
Simulation time 54515694310 ps
CPU time 76.5 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 191236 kb
Host smart-e2583a12-f9d8-45e5-be23-00ec33763b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350419284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.350419284
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.969435405
Short name T612
Test name
Test status
Simulation time 80600776044 ps
CPU time 35.57 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:41:45 PM PST 23
Peak memory 194524 kb
Host smart-351f6cb5-029c-490a-bec8-95e5eb658904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969435405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.969435405
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1473277683
Short name T176
Test name
Test status
Simulation time 323219014566 ps
CPU time 348.92 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:47:24 PM PST 23
Peak memory 191236 kb
Host smart-0c5b022e-9b5b-421f-8eaf-f5605ca19f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473277683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1473277683
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2285300997
Short name T293
Test name
Test status
Simulation time 27658195616 ps
CPU time 47.32 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 182868 kb
Host smart-c00c0df9-b36d-4934-9ce8-e22bc04ab478
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285300997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2285300997
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.746353015
Short name T488
Test name
Test status
Simulation time 222204904420 ps
CPU time 90.22 seconds
Started Dec 20 12:39:52 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 182988 kb
Host smart-a0cf3f59-683e-489e-9b78-9b43eda4d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746353015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.746353015
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1152743923
Short name T166
Test name
Test status
Simulation time 49747676887 ps
CPU time 77.61 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 191264 kb
Host smart-545dba45-3905-4131-beac-a85a2d82adba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152743923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1152743923
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4089494424
Short name T22
Test name
Test status
Simulation time 109434829071 ps
CPU time 331.81 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:46:03 PM PST 23
Peak memory 191260 kb
Host smart-ce7e7eb2-73f8-41b1-944b-53deb6e3c5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089494424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4089494424
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.512585487
Short name T535
Test name
Test status
Simulation time 1198369027794 ps
CPU time 413.61 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:47:55 PM PST 23
Peak memory 191156 kb
Host smart-73ba9fbc-7a56-4e69-b682-b04406a1dd58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512585487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
512585487
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.520127647
Short name T172
Test name
Test status
Simulation time 177901715475 ps
CPU time 641.23 seconds
Started Dec 20 12:39:24 PM PST 23
Finished Dec 20 12:51:16 PM PST 23
Peak memory 206656 kb
Host smart-68ed0dac-8702-4f09-8905-3564ea88c0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520127647 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.520127647
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3305861635
Short name T352
Test name
Test status
Simulation time 161412334416 ps
CPU time 772.07 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 191164 kb
Host smart-aa66b77b-04f6-4cf4-afd9-5e64aa882f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305861635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3305861635
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1287486059
Short name T95
Test name
Test status
Simulation time 405881627652 ps
CPU time 104.45 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:42:56 PM PST 23
Peak memory 191628 kb
Host smart-2f4ea0d3-3b3b-40ed-b39d-6ba986a82831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287486059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1287486059
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3921146239
Short name T167
Test name
Test status
Simulation time 1549501907783 ps
CPU time 422.99 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:48:19 PM PST 23
Peak memory 194064 kb
Host smart-c02fc47b-784e-448e-9aa8-ca00d9f33b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921146239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3921146239
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3518468059
Short name T160
Test name
Test status
Simulation time 570689017944 ps
CPU time 1997.98 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 01:14:22 PM PST 23
Peak memory 190992 kb
Host smart-64d82e89-acf8-4e89-adba-9a872bb86365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518468059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3518468059
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3143193888
Short name T18
Test name
Test status
Simulation time 972583356926 ps
CPU time 367.53 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:47:08 PM PST 23
Peak memory 191028 kb
Host smart-57cc5d3b-fc1c-4c74-a352-e14461004314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143193888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3143193888
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1109842814
Short name T273
Test name
Test status
Simulation time 45208736122 ps
CPU time 71.65 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 183012 kb
Host smart-0e384df9-200b-4750-ae6e-7a6ea2859d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109842814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1109842814
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3048236
Short name T576
Test name
Test status
Simulation time 208217732523 ps
CPU time 147.13 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 12:43:07 PM PST 23
Peak memory 183032 kb
Host smart-a6715e43-92ad-4401-92aa-0448b4933e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3048236
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.4100589031
Short name T593
Test name
Test status
Simulation time 22489357557 ps
CPU time 117.23 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 191156 kb
Host smart-a59c7339-4b98-4095-a1dc-b7cedec00e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100589031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4100589031
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3324251875
Short name T537
Test name
Test status
Simulation time 1058556781212 ps
CPU time 349.87 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:46:21 PM PST 23
Peak memory 191280 kb
Host smart-c996e9f0-efec-493a-9eff-ad8574fef363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324251875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3324251875
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1225345987
Short name T544
Test name
Test status
Simulation time 75866134623 ps
CPU time 106.47 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 197748 kb
Host smart-b9d91088-866b-488d-8b42-77f15a32bfc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225345987 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1225345987
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1096443822
Short name T191
Test name
Test status
Simulation time 353420936831 ps
CPU time 912.24 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 191164 kb
Host smart-22821847-0318-41f0-ad10-20523585bbee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096443822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1096443822
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2348085984
Short name T358
Test name
Test status
Simulation time 75156116527 ps
CPU time 232.81 seconds
Started Dec 20 12:40:26 PM PST 23
Finished Dec 20 12:45:19 PM PST 23
Peak memory 193596 kb
Host smart-b3f253c4-553d-4719-80be-1ae020691fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348085984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2348085984
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1301972451
Short name T103
Test name
Test status
Simulation time 82146924003 ps
CPU time 125.31 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:43:12 PM PST 23
Peak memory 191200 kb
Host smart-1a16ca91-a8f1-4fea-87bc-d0a37a9c4893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301972451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1301972451
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2853405923
Short name T349
Test name
Test status
Simulation time 61962978863 ps
CPU time 376.81 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:47:31 PM PST 23
Peak memory 194388 kb
Host smart-431b1d2d-85f6-487b-b652-d10830ffc3fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853405923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2853405923
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2684044530
Short name T109
Test name
Test status
Simulation time 45644558013 ps
CPU time 228.35 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:45:13 PM PST 23
Peak memory 191016 kb
Host smart-0154732b-f02c-4f42-9371-c60e4d3b9b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684044530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2684044530
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2936746820
Short name T279
Test name
Test status
Simulation time 180421302418 ps
CPU time 103.96 seconds
Started Dec 20 12:40:11 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 191200 kb
Host smart-03898759-e397-4671-954b-1eebe484ffa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936746820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2936746820
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2011725505
Short name T200
Test name
Test status
Simulation time 72124213693 ps
CPU time 125.32 seconds
Started Dec 20 12:40:40 PM PST 23
Finished Dec 20 12:43:48 PM PST 23
Peak memory 191168 kb
Host smart-e3b34560-184b-4a93-b17d-9c4bebbc32d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011725505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2011725505
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2524504626
Short name T372
Test name
Test status
Simulation time 183094144294 ps
CPU time 472.29 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:49:12 PM PST 23
Peak memory 191072 kb
Host smart-5ae73358-8cc4-4f3b-aa60-125b1779a140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524504626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2524504626
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1058368887
Short name T525
Test name
Test status
Simulation time 37758003311 ps
CPU time 52.73 seconds
Started Dec 20 12:39:07 PM PST 23
Finished Dec 20 12:41:04 PM PST 23
Peak memory 183056 kb
Host smart-8f257240-43e0-4893-849d-53a0aa6b8f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058368887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1058368887
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.727281252
Short name T4
Test name
Test status
Simulation time 666678086979 ps
CPU time 952.62 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 193260 kb
Host smart-08f48207-bcbc-4170-9025-35f66080698a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727281252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.727281252
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3427814275
Short name T368
Test name
Test status
Simulation time 51320835172 ps
CPU time 129.11 seconds
Started Dec 20 12:39:20 PM PST 23
Finished Dec 20 12:42:52 PM PST 23
Peak memory 191192 kb
Host smart-d8ec10ab-c955-4e71-ab39-5ef2723c20cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427814275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3427814275
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2295893570
Short name T10
Test name
Test status
Simulation time 131805775 ps
CPU time 0.7 seconds
Started Dec 20 12:39:26 PM PST 23
Finished Dec 20 12:40:37 PM PST 23
Peak memory 212932 kb
Host smart-efd5aabc-a20d-4a46-a6e8-af4593458e52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295893570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2295893570
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3474223879
Short name T164
Test name
Test status
Simulation time 338268571180 ps
CPU time 2248.67 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 01:17:42 PM PST 23
Peak memory 191180 kb
Host smart-a29d9705-4dc3-4b9d-8b8c-d31337ed0913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474223879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3474223879
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3845680948
Short name T370
Test name
Test status
Simulation time 102585985332 ps
CPU time 1025.58 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:57:51 PM PST 23
Peak memory 214132 kb
Host smart-76228427-e3d3-49c9-9a9a-5c77c0be5588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845680948 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3845680948
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2594626908
Short name T139
Test name
Test status
Simulation time 6264363307 ps
CPU time 11.86 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:40:43 PM PST 23
Peak memory 183072 kb
Host smart-3904733b-2ad0-4ef7-8623-145b9d075d04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594626908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2594626908
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4014692357
Short name T599
Test name
Test status
Simulation time 44917939944 ps
CPU time 61.29 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 12:41:43 PM PST 23
Peak memory 183116 kb
Host smart-730b6b88-4aa3-4ddb-b394-32a4a559ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014692357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4014692357
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2195528777
Short name T113
Test name
Test status
Simulation time 189132540277 ps
CPU time 96.15 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 183068 kb
Host smart-391bb06d-dad6-4d5e-bee5-e78f7ad11abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195528777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2195528777
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3463085237
Short name T267
Test name
Test status
Simulation time 176830394446 ps
CPU time 143.3 seconds
Started Dec 20 12:39:22 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 194416 kb
Host smart-f3624326-0c82-47bb-a0ff-97278826a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463085237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3463085237
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1855829980
Short name T271
Test name
Test status
Simulation time 1015205560761 ps
CPU time 1635.61 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 01:08:03 PM PST 23
Peak memory 191104 kb
Host smart-4d19416a-24d7-4bbe-badd-4d1b6fd481b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855829980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1855829980
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1241775285
Short name T337
Test name
Test status
Simulation time 37231479886 ps
CPU time 202.77 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:44:05 PM PST 23
Peak memory 206012 kb
Host smart-1033a126-f7d2-468e-8253-b6aee6ddbd92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241775285 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1241775285
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2311937720
Short name T204
Test name
Test status
Simulation time 854943246281 ps
CPU time 424.42 seconds
Started Dec 20 12:39:44 PM PST 23
Finished Dec 20 12:48:10 PM PST 23
Peak memory 182936 kb
Host smart-484f1fa0-f41a-4746-9287-52e16e196906
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311937720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2311937720
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1141656036
Short name T609
Test name
Test status
Simulation time 251400705785 ps
CPU time 194.47 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:43:48 PM PST 23
Peak memory 182920 kb
Host smart-8f3ceb6e-3403-4ef5-9045-9cbbd5da080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141656036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1141656036
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1872513168
Short name T555
Test name
Test status
Simulation time 675831800 ps
CPU time 2.07 seconds
Started Dec 20 12:39:20 PM PST 23
Finished Dec 20 12:40:30 PM PST 23
Peak memory 191348 kb
Host smart-c12e8c1e-62fa-404d-ab27-e9b0b023ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872513168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1872513168
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1320300160
Short name T572
Test name
Test status
Simulation time 322427341970 ps
CPU time 278.28 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:45:33 PM PST 23
Peak memory 191176 kb
Host smart-0eb66527-039b-4152-98d7-5b11c2c9723c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320300160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1320300160
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.283486058
Short name T601
Test name
Test status
Simulation time 105785100496 ps
CPU time 1021.3 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 212068 kb
Host smart-946cc5ca-c29c-4604-847d-4b0f1e04cde7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283486058 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.283486058
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.210809334
Short name T568
Test name
Test status
Simulation time 211225850251 ps
CPU time 257.49 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:45:09 PM PST 23
Peak memory 182916 kb
Host smart-b367dc03-00f7-4be2-bce8-58048c0eb3b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210809334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.210809334
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3925839050
Short name T508
Test name
Test status
Simulation time 42664262888 ps
CPU time 37.8 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:41:07 PM PST 23
Peak memory 182864 kb
Host smart-a9b77e9d-d981-474c-96fa-0f45bbf39a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925839050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3925839050
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2609830217
Short name T315
Test name
Test status
Simulation time 38883079216 ps
CPU time 15.31 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:41:20 PM PST 23
Peak memory 182776 kb
Host smart-a35e835d-8d36-46a9-9600-5fe82d2b556d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609830217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2609830217
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3498962736
Short name T235
Test name
Test status
Simulation time 137033884715 ps
CPU time 716.53 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:52:51 PM PST 23
Peak memory 194176 kb
Host smart-959cfd3d-bcbc-4777-8805-0a5f55c94faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498962736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3498962736
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1278466509
Short name T513
Test name
Test status
Simulation time 637934018006 ps
CPU time 182.77 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:43:54 PM PST 23
Peak memory 182920 kb
Host smart-bd16fa6a-907b-4d7b-b918-46ab7eea9060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278466509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1278466509
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.4127233754
Short name T32
Test name
Test status
Simulation time 137315640291 ps
CPU time 832.48 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:54:30 PM PST 23
Peak memory 207928 kb
Host smart-98ab0d0b-0016-4427-816c-de1443796585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127233754 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.4127233754
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4046116805
Short name T608
Test name
Test status
Simulation time 168925747554 ps
CPU time 143.09 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:43:14 PM PST 23
Peak memory 183060 kb
Host smart-9ea2f431-8103-488c-977a-b90e5858eb90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046116805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4046116805
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1008193888
Short name T383
Test name
Test status
Simulation time 81960381020 ps
CPU time 35.26 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:41:12 PM PST 23
Peak memory 182880 kb
Host smart-251e4f4b-a46b-4239-bfc9-2b8c5a339f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008193888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1008193888
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2120012403
Short name T603
Test name
Test status
Simulation time 121286754578 ps
CPU time 389.61 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:47:20 PM PST 23
Peak memory 191216 kb
Host smart-c82d02d5-92d7-44f3-a02a-1aa4766733e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120012403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2120012403
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2657249100
Short name T527
Test name
Test status
Simulation time 682077863 ps
CPU time 1 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 193580 kb
Host smart-726d8293-0343-47dc-9bbc-8e328be41f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657249100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2657249100
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2096408733
Short name T506
Test name
Test status
Simulation time 370389937001 ps
CPU time 302.79 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:45:41 PM PST 23
Peak memory 205972 kb
Host smart-44cd26d9-3dee-4663-8bdc-eb3a1ac02d79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096408733 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2096408733
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3691799869
Short name T218
Test name
Test status
Simulation time 407587543776 ps
CPU time 207.34 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:44:21 PM PST 23
Peak memory 182864 kb
Host smart-1d2be1b7-8aee-4c0c-bcae-3545fb11d745
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691799869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3691799869
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2462897125
Short name T381
Test name
Test status
Simulation time 693363796400 ps
CPU time 292.43 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:45:41 PM PST 23
Peak memory 183060 kb
Host smart-7bb44913-4c72-4a61-962c-ee069b320ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462897125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2462897125
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.132084291
Short name T277
Test name
Test status
Simulation time 38571142074 ps
CPU time 147.12 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 191204 kb
Host smart-d12d7f42-7ee6-434a-8961-f0d903000851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132084291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.132084291
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3042002497
Short name T366
Test name
Test status
Simulation time 74775486606 ps
CPU time 89.68 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 182980 kb
Host smart-da277673-8eb7-41d1-9b3a-db914b162583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042002497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3042002497
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3019738593
Short name T93
Test name
Test status
Simulation time 300616386738 ps
CPU time 1920.34 seconds
Started Dec 20 12:39:30 PM PST 23
Finished Dec 20 01:12:39 PM PST 23
Peak memory 191020 kb
Host smart-6e6985da-45f5-4416-b5d5-acea338f9f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019738593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3019738593
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3053826261
Short name T514
Test name
Test status
Simulation time 78021900148 ps
CPU time 838.3 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:54:49 PM PST 23
Peak memory 209816 kb
Host smart-76a655b0-7db8-4589-acd7-95c7a8dc1548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053826261 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3053826261
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3637265119
Short name T269
Test name
Test status
Simulation time 481099801522 ps
CPU time 308.76 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:46:17 PM PST 23
Peak memory 182936 kb
Host smart-c78c7934-4a63-4de9-9d3a-333bcfd0aab7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637265119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3637265119
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2882101959
Short name T500
Test name
Test status
Simulation time 345714552209 ps
CPU time 144.68 seconds
Started Dec 20 12:39:42 PM PST 23
Finished Dec 20 12:43:11 PM PST 23
Peak memory 182852 kb
Host smart-a39fbfe5-b33c-4107-a7a3-b6558bbde800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882101959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2882101959
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3268224658
Short name T286
Test name
Test status
Simulation time 247561082676 ps
CPU time 250.89 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:45:12 PM PST 23
Peak memory 191036 kb
Host smart-ecc0b383-1658-496e-9c93-4514885040e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268224658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3268224658
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.337901816
Short name T550
Test name
Test status
Simulation time 52647913331 ps
CPU time 88.47 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 182968 kb
Host smart-fdeee4b2-e6b1-485f-aab1-494044535b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337901816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.337901816
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3212842820
Short name T565
Test name
Test status
Simulation time 32557132968 ps
CPU time 250.63 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:45:03 PM PST 23
Peak memory 197736 kb
Host smart-03dccabc-28a7-47cf-9f68-51b3e43545ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212842820 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3212842820
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3928182425
Short name T276
Test name
Test status
Simulation time 156252708407 ps
CPU time 238.97 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:45:11 PM PST 23
Peak memory 183000 kb
Host smart-e0406b95-8c77-484b-a8d6-f81a954237c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928182425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3928182425
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1377577699
Short name T595
Test name
Test status
Simulation time 47485665647 ps
CPU time 70.53 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 183068 kb
Host smart-81584efc-f3bd-4785-8e91-2cfc5adf1505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377577699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1377577699
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.4106477408
Short name T490
Test name
Test status
Simulation time 78168429383 ps
CPU time 64.19 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 191284 kb
Host smart-90f98a8f-ea83-42ad-af1e-3185752b3783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106477408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.4106477408
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.4052320456
Short name T220
Test name
Test status
Simulation time 506368070609 ps
CPU time 768.48 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:53:36 PM PST 23
Peak memory 191032 kb
Host smart-13bea576-06a3-4b3b-9df2-a3b3cfe519d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052320456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.4052320456
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3529828975
Short name T541
Test name
Test status
Simulation time 71929652135 ps
CPU time 110.85 seconds
Started Dec 20 12:39:42 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 197572 kb
Host smart-9daafa5b-56b1-4da5-bbf0-e7ac05f84630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529828975 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3529828975
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2948849520
Short name T145
Test name
Test status
Simulation time 664988077059 ps
CPU time 199.53 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:44:22 PM PST 23
Peak memory 182920 kb
Host smart-460c1316-9dc2-4875-b311-b3f84a043dd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948849520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2948849520
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.772488989
Short name T515
Test name
Test status
Simulation time 67233597447 ps
CPU time 98.74 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 182868 kb
Host smart-bf3e702e-2230-4b94-942c-8dfc4735b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772488989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.772488989
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2813002133
Short name T573
Test name
Test status
Simulation time 38172929632 ps
CPU time 19.26 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:41:09 PM PST 23
Peak memory 183052 kb
Host smart-4f32cfaa-e8c2-46fd-90a1-f01f10f03902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813002133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2813002133
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2099271039
Short name T504
Test name
Test status
Simulation time 1230579605 ps
CPU time 1.6 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:40:47 PM PST 23
Peak memory 182804 kb
Host smart-a2115dbc-839e-4f5c-8152-88f268d27055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099271039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2099271039
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.296825694
Short name T1
Test name
Test status
Simulation time 301799185203 ps
CPU time 389.55 seconds
Started Dec 20 12:40:07 PM PST 23
Finished Dec 20 12:47:38 PM PST 23
Peak memory 207100 kb
Host smart-49df470a-bf81-4294-99eb-4bfc4171650f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296825694 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.296825694
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.968797024
Short name T278
Test name
Test status
Simulation time 337160158376 ps
CPU time 500.56 seconds
Started Dec 20 12:40:07 PM PST 23
Finished Dec 20 12:49:29 PM PST 23
Peak memory 182860 kb
Host smart-a3adcaf5-2fe1-4e53-973e-9617801c957b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968797024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.968797024
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3487499971
Short name T563
Test name
Test status
Simulation time 27014267433 ps
CPU time 43.25 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:41:34 PM PST 23
Peak memory 182964 kb
Host smart-a1691d6f-6168-40aa-a44e-c61706f44f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487499971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3487499971
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2118612630
Short name T185
Test name
Test status
Simulation time 16898094294 ps
CPU time 24.19 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 182836 kb
Host smart-adc9951f-0056-4da6-b25d-29fffad32419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118612630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2118612630
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3054586392
Short name T553
Test name
Test status
Simulation time 25237687408 ps
CPU time 314.96 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:46:21 PM PST 23
Peak memory 205152 kb
Host smart-29a52352-b1c0-497f-9a0b-ec7a150cea32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054586392 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3054586392
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4025770395
Short name T173
Test name
Test status
Simulation time 61841725663 ps
CPU time 108.75 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 182960 kb
Host smart-19d5cfee-6f6c-4074-b2bc-072e24f76c85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025770395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4025770395
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.870914458
Short name T587
Test name
Test status
Simulation time 175704942456 ps
CPU time 209.34 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:44:27 PM PST 23
Peak memory 182848 kb
Host smart-a58e7d70-68d7-4271-bddb-3fc191a386c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870914458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.870914458
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1502619229
Short name T255
Test name
Test status
Simulation time 263872330146 ps
CPU time 301.49 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:45:42 PM PST 23
Peak memory 191312 kb
Host smart-9d4c656b-ac07-4fed-b08e-cad1c25e1544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502619229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1502619229
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2253745042
Short name T128
Test name
Test status
Simulation time 76078270365 ps
CPU time 80.14 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 182824 kb
Host smart-246ab45a-76e6-49b5-ad72-6f89e0c3bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253745042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2253745042
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2367675032
Short name T574
Test name
Test status
Simulation time 86073091410 ps
CPU time 598.5 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:50:44 PM PST 23
Peak memory 207100 kb
Host smart-f155c755-18bd-4e4c-a1f2-038063a0ade9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367675032 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2367675032
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4278840384
Short name T334
Test name
Test status
Simulation time 1123522271879 ps
CPU time 882.72 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:55:20 PM PST 23
Peak memory 183008 kb
Host smart-381722b0-db65-4d42-9916-ae9230356d73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278840384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4278840384
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random.13489913
Short name T188
Test name
Test status
Simulation time 669391029120 ps
CPU time 532.15 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:49:39 PM PST 23
Peak memory 191332 kb
Host smart-828d16fc-56c1-41b3-9df3-77deeb9b62d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.13489913
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1518721293
Short name T362
Test name
Test status
Simulation time 327243268897 ps
CPU time 241.89 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:45:11 PM PST 23
Peak memory 191064 kb
Host smart-a0899bc0-f39a-4551-9b2a-ae505e3a2ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518721293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1518721293
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1051551118
Short name T16
Test name
Test status
Simulation time 267111542 ps
CPU time 0.79 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:40:17 PM PST 23
Peak memory 212628 kb
Host smart-8a2088c5-b566-4947-81d8-aaf7ff55972b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051551118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1051551118
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2950909244
Short name T567
Test name
Test status
Simulation time 22174718 ps
CPU time 0.58 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:40:37 PM PST 23
Peak memory 182632 kb
Host smart-ac435794-fb0f-4e7b-8c9f-91d5a45765c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950909244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2950909244
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3827845292
Short name T577
Test name
Test status
Simulation time 65340515069 ps
CPU time 432.52 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:47:57 PM PST 23
Peak memory 205916 kb
Host smart-e5a56db4-8103-4234-bc6a-461ec8931c17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827845292 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3827845292
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.557957492
Short name T560
Test name
Test status
Simulation time 24590354048 ps
CPU time 34.42 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 183128 kb
Host smart-1aa8b2b2-b33b-45f9-9629-04d50eb9859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557957492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.557957492
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4112472364
Short name T237
Test name
Test status
Simulation time 196948013440 ps
CPU time 100.61 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:42:35 PM PST 23
Peak memory 182912 kb
Host smart-b9184a26-a81d-4182-b6d8-9095d8f33a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112472364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4112472364
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1215850080
Short name T7
Test name
Test status
Simulation time 495120858 ps
CPU time 1.27 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 182648 kb
Host smart-55614059-bd06-4e7a-b279-da1f38cddced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215850080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1215850080
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2027651386
Short name T367
Test name
Test status
Simulation time 705879383304 ps
CPU time 316.01 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:46:05 PM PST 23
Peak memory 191136 kb
Host smart-9acd2435-0cc1-46e8-a7d3-5ac792998654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027651386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2027651386
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.3382487793
Short name T79
Test name
Test status
Simulation time 444600474268 ps
CPU time 780.58 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:53:26 PM PST 23
Peak memory 209696 kb
Host smart-35e1f85c-5fcd-48d9-90ae-34bc9fe94ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382487793 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.3382487793
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2658109118
Short name T25
Test name
Test status
Simulation time 334885461982 ps
CPU time 180.87 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:44:04 PM PST 23
Peak memory 182924 kb
Host smart-cf5fa72e-424e-462f-a75b-b8ac97e79d38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658109118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2658109118
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1386476156
Short name T23
Test name
Test status
Simulation time 397287118470 ps
CPU time 161.14 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:43:10 PM PST 23
Peak memory 183176 kb
Host smart-4ca4f450-9097-4c61-9de1-46af880b0b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386476156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1386476156
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3264914175
Short name T379
Test name
Test status
Simulation time 68262338871 ps
CPU time 96.62 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:42:41 PM PST 23
Peak memory 194536 kb
Host smart-37a0ac3c-20ef-41c9-a10b-7f767255dbc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264914175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3264914175
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2982626384
Short name T332
Test name
Test status
Simulation time 340221687591 ps
CPU time 96.47 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 182884 kb
Host smart-2633301a-6ee9-4b69-b6d0-f60f4f979540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982626384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2982626384
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.319863759
Short name T548
Test name
Test status
Simulation time 215828338698 ps
CPU time 925.56 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:55:59 PM PST 23
Peak memory 213508 kb
Host smart-0c52dee3-ab8c-4ee4-a5ff-3785a64cffdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319863759 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.319863759
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1103899650
Short name T586
Test name
Test status
Simulation time 75388085345 ps
CPU time 45.39 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:41:36 PM PST 23
Peak memory 182816 kb
Host smart-1d699e1d-e3c9-4751-980c-b55a21bd395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103899650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1103899650
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1442966088
Short name T136
Test name
Test status
Simulation time 115479908999 ps
CPU time 180.53 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:43:44 PM PST 23
Peak memory 191248 kb
Host smart-363996e0-bc71-449b-aaf9-d051cf1c0643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442966088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1442966088
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1569754309
Short name T183
Test name
Test status
Simulation time 45138603807 ps
CPU time 59.96 seconds
Started Dec 20 12:39:44 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 183056 kb
Host smart-bf73279e-c48b-4aea-b757-92f72ea1a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569754309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1569754309
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.100008897
Short name T492
Test name
Test status
Simulation time 467620157939 ps
CPU time 131.8 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 183020 kb
Host smart-6f1ef45f-0229-4e8b-af55-62a9a4c8a608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100008897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
100008897
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2542845593
Short name T523
Test name
Test status
Simulation time 59325760744 ps
CPU time 109.08 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:43:03 PM PST 23
Peak memory 205912 kb
Host smart-6012e1cd-6e45-4dae-9636-46f8aceb8def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542845593 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2542845593
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2947713260
Short name T516
Test name
Test status
Simulation time 91953822545 ps
CPU time 134.33 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 183060 kb
Host smart-894a25a2-6c62-4047-b4a7-0334340132a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947713260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2947713260
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.634356638
Short name T365
Test name
Test status
Simulation time 272277711495 ps
CPU time 147.04 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:43:26 PM PST 23
Peak memory 190644 kb
Host smart-2b6bcd68-19f6-40de-ad2d-398d46e07e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634356638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.634356638
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.932108316
Short name T244
Test name
Test status
Simulation time 51890158499 ps
CPU time 77.53 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 182856 kb
Host smart-99cc42b6-7e1a-4361-94f1-fab7bf3553bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932108316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.932108316
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3427088073
Short name T254
Test name
Test status
Simulation time 614631975764 ps
CPU time 1305.33 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 01:02:56 PM PST 23
Peak memory 213952 kb
Host smart-3d407e6d-99f6-426e-8c7f-3849da561b80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427088073 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3427088073
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3816609965
Short name T302
Test name
Test status
Simulation time 709482201895 ps
CPU time 1237.1 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 01:01:28 PM PST 23
Peak memory 182868 kb
Host smart-6d19a73c-651f-40b6-b5f6-1521e76c1b44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816609965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3816609965
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1809792987
Short name T578
Test name
Test status
Simulation time 501754492332 ps
CPU time 239.2 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:44:42 PM PST 23
Peak memory 183060 kb
Host smart-2496fb05-d115-489d-b98e-db0a24011761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809792987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1809792987
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.4189339180
Short name T258
Test name
Test status
Simulation time 172232373610 ps
CPU time 56.44 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 182692 kb
Host smart-fd14f90e-160c-449b-9a16-371c9120567a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189339180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4189339180
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.4234467373
Short name T353
Test name
Test status
Simulation time 151924961258 ps
CPU time 232.25 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:44:35 PM PST 23
Peak memory 191164 kb
Host smart-c90f779d-10fd-40cb-b2cb-559dbb975e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234467373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.4234467373
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.1855831211
Short name T518
Test name
Test status
Simulation time 33928050861 ps
CPU time 380.92 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:47:08 PM PST 23
Peak memory 197708 kb
Host smart-af2d3a0d-dac2-48a0-aac0-198ede4ba7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855831211 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.1855831211
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2707895512
Short name T298
Test name
Test status
Simulation time 1044380766919 ps
CPU time 1001.74 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:57:27 PM PST 23
Peak memory 183056 kb
Host smart-7bc59f48-3336-44f9-9613-2515ba495513
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707895512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2707895512
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.4103830757
Short name T322
Test name
Test status
Simulation time 88403971056 ps
CPU time 156.25 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:43:16 PM PST 23
Peak memory 191032 kb
Host smart-0e10861f-5c8c-4f40-94c5-2c8e93593815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103830757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4103830757
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.251172066
Short name T251
Test name
Test status
Simulation time 40538200850 ps
CPU time 36.16 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 191284 kb
Host smart-4bd35f45-fd26-48f7-bc1a-5624c9bf8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251172066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.251172066
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2592535470
Short name T346
Test name
Test status
Simulation time 72471184019 ps
CPU time 303.65 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:46:10 PM PST 23
Peak memory 205764 kb
Host smart-63956b9b-ffaf-4a0f-96e0-59f72d5e095c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592535470 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2592535470
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1452852021
Short name T115
Test name
Test status
Simulation time 11136354355 ps
CPU time 9.24 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:41:03 PM PST 23
Peak memory 182936 kb
Host smart-2eeed69e-f9f3-447a-b317-30bf64f8f412
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452852021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1452852021
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3321872277
Short name T596
Test name
Test status
Simulation time 143558915159 ps
CPU time 96.47 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:42:51 PM PST 23
Peak memory 182820 kb
Host smart-440ee83e-a6cb-455a-b305-ea97a8c790ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321872277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3321872277
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2711170038
Short name T376
Test name
Test status
Simulation time 23807572487 ps
CPU time 77.58 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 182876 kb
Host smart-9ec2ab48-5559-4600-a84f-94e49812b1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711170038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2711170038
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3148910216
Short name T517
Test name
Test status
Simulation time 453424764 ps
CPU time 0.68 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:40:47 PM PST 23
Peak memory 182776 kb
Host smart-2a33e474-393b-4d5c-b375-e137f02a4d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148910216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3148910216
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1046322905
Short name T557
Test name
Test status
Simulation time 98123216731 ps
CPU time 741.04 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 205912 kb
Host smart-bf35a728-603c-4be0-b6f8-ec98bcd47573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046322905 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1046322905
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2423994546
Short name T327
Test name
Test status
Simulation time 309484150018 ps
CPU time 553.38 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 182840 kb
Host smart-efe8c4a5-4777-4159-830d-eac8f854f6e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423994546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2423994546
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.2677734634
Short name T274
Test name
Test status
Simulation time 11014796444 ps
CPU time 10.2 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:40:47 PM PST 23
Peak memory 183108 kb
Host smart-0cfd9ff7-e4eb-4fcc-86da-cac18b743bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677734634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2677734634
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2980273228
Short name T559
Test name
Test status
Simulation time 339804681 ps
CPU time 1.22 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:40:44 PM PST 23
Peak memory 182940 kb
Host smart-24ffabad-ccb3-428f-8b39-d1bb7ec16c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980273228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2980273228
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.821125799
Short name T382
Test name
Test status
Simulation time 288821934460 ps
CPU time 407.51 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:47:23 PM PST 23
Peak memory 191328 kb
Host smart-518e43a4-a12d-4739-9302-5df1f5911306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821125799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
821125799
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.334150092
Short name T556
Test name
Test status
Simulation time 66500447909 ps
CPU time 712.07 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:53:01 PM PST 23
Peak memory 207148 kb
Host smart-76bae934-387e-4172-b030-a9bccabf3e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334150092 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.334150092
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1029578094
Short name T232
Test name
Test status
Simulation time 781384750964 ps
CPU time 358.22 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:46:59 PM PST 23
Peak memory 182908 kb
Host smart-ebdc95ea-a4ee-4129-b97b-3b157cc3518d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029578094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1029578094
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3721872887
Short name T597
Test name
Test status
Simulation time 939382514843 ps
CPU time 388.79 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 182960 kb
Host smart-b6c109cb-8bcc-4f25-a1e2-3ca1672ba958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721872887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3721872887
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2929791430
Short name T129
Test name
Test status
Simulation time 33039963706 ps
CPU time 16.72 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:41:08 PM PST 23
Peak memory 182876 kb
Host smart-d066e101-6b80-4231-a7be-ad5b102676d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929791430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2929791430
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.795927181
Short name T284
Test name
Test status
Simulation time 107846576796 ps
CPU time 331.56 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:46:41 PM PST 23
Peak memory 191100 kb
Host smart-55fc3275-85c8-4285-bb8f-3fdf325e7d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795927181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.795927181
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1017897222
Short name T607
Test name
Test status
Simulation time 55183679 ps
CPU time 0.54 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:41:04 PM PST 23
Peak memory 182640 kb
Host smart-9d7db826-7ee2-4cf9-bbfe-3b8bc093b89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017897222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1017897222
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2172657532
Short name T526
Test name
Test status
Simulation time 221357837606 ps
CPU time 1132.66 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:59:52 PM PST 23
Peak memory 212740 kb
Host smart-eb17a472-3ce8-454f-984e-5a0c2b738f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172657532 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2172657532
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3343872486
Short name T505
Test name
Test status
Simulation time 242671171315 ps
CPU time 89.46 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 183060 kb
Host smart-5fc97c7a-3410-40c5-8b0f-8b526498e01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343872486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3343872486
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3050515551
Short name T126
Test name
Test status
Simulation time 79346849484 ps
CPU time 70.51 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 182968 kb
Host smart-68910cd5-9982-4563-bd1d-0a23e0d4f1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050515551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3050515551
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1208014158
Short name T569
Test name
Test status
Simulation time 11730244585 ps
CPU time 17.44 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:41:09 PM PST 23
Peak memory 182692 kb
Host smart-248ebcdf-9db4-4fef-a226-6629125152bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208014158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1208014158
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2301503409
Short name T547
Test name
Test status
Simulation time 97866336025 ps
CPU time 272.24 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:45:25 PM PST 23
Peak memory 205928 kb
Host smart-f6ca4957-fb63-472c-ab39-22fe8465f602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301503409 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2301503409
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.33811659
Short name T131
Test name
Test status
Simulation time 74432579071 ps
CPU time 24.82 seconds
Started Dec 20 12:39:20 PM PST 23
Finished Dec 20 12:41:03 PM PST 23
Peak memory 182996 kb
Host smart-4e0c6628-4466-4823-ac9a-2a83d1de51e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33811659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
rv_timer_cfg_update_on_fly.33811659
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2381536557
Short name T546
Test name
Test status
Simulation time 393477450174 ps
CPU time 153.78 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:43:32 PM PST 23
Peak memory 183076 kb
Host smart-484e734c-8f25-471c-8fbf-d2802b15f624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381536557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2381536557
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1831737441
Short name T303
Test name
Test status
Simulation time 92621535571 ps
CPU time 86.4 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:42:03 PM PST 23
Peak memory 183128 kb
Host smart-3a6193bd-d894-463f-af51-b686ab0be416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831737441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1831737441
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.447984761
Short name T356
Test name
Test status
Simulation time 471211279398 ps
CPU time 224.57 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:44:41 PM PST 23
Peak memory 191224 kb
Host smart-cb8f4ec4-4d17-4bc4-a949-f50860e1b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447984761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.447984761
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4250016574
Short name T14
Test name
Test status
Simulation time 94080706 ps
CPU time 0.84 seconds
Started Dec 20 12:39:17 PM PST 23
Finished Dec 20 12:40:25 PM PST 23
Peak memory 212960 kb
Host smart-2776cccb-a9d5-42bd-8f57-8c7bbec27c3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250016574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4250016574
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.192777749
Short name T540
Test name
Test status
Simulation time 135006074683 ps
CPU time 176.43 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:43:55 PM PST 23
Peak memory 182608 kb
Host smart-a0ced646-0874-4162-a79b-69eb9059d1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192777749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.192777749
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1301330522
Short name T519
Test name
Test status
Simulation time 61518542710 ps
CPU time 136.5 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:44:05 PM PST 23
Peak memory 197760 kb
Host smart-c649abb8-130b-458e-8bed-7725289350a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301330522 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1301330522
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1746678852
Short name T224
Test name
Test status
Simulation time 1511519502060 ps
CPU time 855.04 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 183072 kb
Host smart-f339c731-6eef-49d6-8bec-f87f7db12619
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746678852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1746678852
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1614302344
Short name T495
Test name
Test status
Simulation time 54695943575 ps
CPU time 74 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 182764 kb
Host smart-a8c588ad-a51f-40e7-86f0-9ff7d6f3f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614302344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1614302344
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.311228526
Short name T270
Test name
Test status
Simulation time 412913140025 ps
CPU time 882.34 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 191212 kb
Host smart-ab105891-c2fa-4a26-8aad-652978505d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311228526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.311228526
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3867140466
Short name T552
Test name
Test status
Simulation time 7826817313 ps
CPU time 14.14 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 183008 kb
Host smart-11fb8df4-60f3-4861-8268-cbc609cd9566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867140466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3867140466
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.969264505
Short name T309
Test name
Test status
Simulation time 246671547793 ps
CPU time 1010.44 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 209332 kb
Host smart-547f990c-73b7-4cfc-bf9f-3f536b4e546a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969264505 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.969264505
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.915046103
Short name T249
Test name
Test status
Simulation time 1091983373652 ps
CPU time 1116.58 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:59:28 PM PST 23
Peak memory 182992 kb
Host smart-fc8a41ac-ed05-4e91-af58-83ce58ab64f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915046103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.915046103
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2229963512
Short name T530
Test name
Test status
Simulation time 16205734146 ps
CPU time 27.13 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:41:43 PM PST 23
Peak memory 183020 kb
Host smart-3e44937d-3c80-4a8b-b834-92b0b2c339f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229963512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2229963512
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3507922179
Short name T132
Test name
Test status
Simulation time 39224121185 ps
CPU time 66.25 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 183016 kb
Host smart-afa08b4c-bcc0-44c3-bfae-e433c2668428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507922179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3507922179
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1709504208
Short name T509
Test name
Test status
Simulation time 589295060 ps
CPU time 1.4 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:40:46 PM PST 23
Peak memory 182820 kb
Host smart-708e9211-7b3b-453b-95b4-8e4df4ce19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709504208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1709504208
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2062378760
Short name T551
Test name
Test status
Simulation time 251042250480 ps
CPU time 198.57 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:44:18 PM PST 23
Peak memory 183012 kb
Host smart-be347060-10ce-46f2-b2c1-a92f2cce9d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062378760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2062378760
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.4139548956
Short name T554
Test name
Test status
Simulation time 196878779736 ps
CPU time 633.78 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:51:46 PM PST 23
Peak memory 205892 kb
Host smart-4b032fb1-825e-43b4-b41c-74e8388bbc37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139548956 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.4139548956
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1292746290
Short name T181
Test name
Test status
Simulation time 218949505075 ps
CPU time 185.25 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:43:59 PM PST 23
Peak memory 182816 kb
Host smart-54e4ef8e-bd54-4eed-a980-cb319444a838
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292746290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1292746290
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1403149285
Short name T538
Test name
Test status
Simulation time 500073135454 ps
CPU time 195.36 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:43:57 PM PST 23
Peak memory 182852 kb
Host smart-4dc1ea47-5cf0-4182-87d8-692d78eccd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403149285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1403149285
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.947916768
Short name T580
Test name
Test status
Simulation time 101206940063 ps
CPU time 193.28 seconds
Started Dec 20 12:39:43 PM PST 23
Finished Dec 20 12:44:12 PM PST 23
Peak memory 193328 kb
Host smart-974d2025-2f3e-43db-86ce-4beb311accc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947916768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.947916768
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3116831890
Short name T581
Test name
Test status
Simulation time 8088134022 ps
CPU time 7.85 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:41:00 PM PST 23
Peak memory 194308 kb
Host smart-51c15745-808a-4014-ba5f-d686bb170226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116831890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3116831890
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.76314992
Short name T174
Test name
Test status
Simulation time 232717677346 ps
CPU time 336.35 seconds
Started Dec 20 12:39:43 PM PST 23
Finished Dec 20 12:46:31 PM PST 23
Peak memory 191284 kb
Host smart-1872cc0a-34af-47b0-aaa6-4999c924cbb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76314992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.76314992
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1883885868
Short name T614
Test name
Test status
Simulation time 98128991541 ps
CPU time 342.12 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:46:22 PM PST 23
Peak memory 205788 kb
Host smart-6299ecc8-0d9d-43f4-b7ed-9105edae1c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883885868 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1883885868
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2551836083
Short name T359
Test name
Test status
Simulation time 369301176046 ps
CPU time 271.43 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:45:22 PM PST 23
Peak memory 182844 kb
Host smart-f0be77bb-0502-4635-a9db-d986ea50d064
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551836083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2551836083
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1673289515
Short name T591
Test name
Test status
Simulation time 2382525981 ps
CPU time 2.42 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:41:05 PM PST 23
Peak memory 182860 kb
Host smart-ff5dc3fe-8c1f-4ff5-bb3b-b8deec59ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673289515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1673289515
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2485574032
Short name T192
Test name
Test status
Simulation time 397106059231 ps
CPU time 122.29 seconds
Started Dec 20 12:40:03 PM PST 23
Finished Dec 20 12:43:16 PM PST 23
Peak memory 191188 kb
Host smart-a26c41c2-eb08-405d-b56f-b76e1de7e844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485574032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2485574032
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3041910053
Short name T116
Test name
Test status
Simulation time 258790431403 ps
CPU time 156.02 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 194312 kb
Host smart-5fcdce2c-05d0-4e9e-a1e3-ac0710c101bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041910053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3041910053
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.3831498213
Short name T532
Test name
Test status
Simulation time 863304942019 ps
CPU time 387.73 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 205828 kb
Host smart-a5863fa6-2b58-4427-b46f-8609bdd45c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831498213 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.3831498213
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.554754629
Short name T281
Test name
Test status
Simulation time 94347177869 ps
CPU time 163 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:43:28 PM PST 23
Peak memory 182844 kb
Host smart-39a340d6-31d6-44a9-bbc2-d13bf21196cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554754629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.554754629
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.39727710
Short name T502
Test name
Test status
Simulation time 80728411390 ps
CPU time 32.17 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:41:09 PM PST 23
Peak memory 183040 kb
Host smart-1383e9f6-d250-4651-aa12-41128cd57d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39727710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.39727710
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3188050401
Short name T262
Test name
Test status
Simulation time 8724808030 ps
CPU time 16.47 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:40:57 PM PST 23
Peak memory 183040 kb
Host smart-7eff2764-e772-419d-a3bb-0ea7ad9d5699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188050401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3188050401
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3214030191
Short name T598
Test name
Test status
Simulation time 35770552720 ps
CPU time 54.88 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 183032 kb
Host smart-ec73fa1d-322f-4800-8bf4-dfac9659168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214030191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3214030191
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4266175730
Short name T287
Test name
Test status
Simulation time 191165688468 ps
CPU time 674.47 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:52:23 PM PST 23
Peak memory 182924 kb
Host smart-d121aa18-e14e-4238-b172-37b702081860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266175730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4266175730
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.363663746
Short name T510
Test name
Test status
Simulation time 46484103553 ps
CPU time 435.94 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:48:15 PM PST 23
Peak memory 197552 kb
Host smart-00804b55-7813-4847-b6a6-2353415bdbce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363663746 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.363663746
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2651543125
Short name T318
Test name
Test status
Simulation time 108386260660 ps
CPU time 102.3 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:42:35 PM PST 23
Peak memory 182816 kb
Host smart-5d2e9dd9-e91b-4150-9691-e1ca6750fdbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651543125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2651543125
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1649564026
Short name T3
Test name
Test status
Simulation time 56557515804 ps
CPU time 79.25 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 182268 kb
Host smart-77284da1-1197-4c36-bedd-473d2dd99165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649564026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1649564026
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4134946548
Short name T521
Test name
Test status
Simulation time 730312324 ps
CPU time 2.3 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:41:01 PM PST 23
Peak memory 191000 kb
Host smart-a85d623c-ee1c-449d-b94d-55f7fb76fae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134946548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4134946548
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1218118739
Short name T571
Test name
Test status
Simulation time 322368193950 ps
CPU time 132 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:43:07 PM PST 23
Peak memory 182936 kb
Host smart-727cb3c6-e9da-472f-b9b4-a2188c52dcd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218118739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1218118739
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2357602217
Short name T117
Test name
Test status
Simulation time 138766249276 ps
CPU time 576.75 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:50:39 PM PST 23
Peak memory 205672 kb
Host smart-06bd9edd-e11f-4775-a43e-0e005b9d72a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357602217 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2357602217
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2382912160
Short name T2
Test name
Test status
Simulation time 579907594075 ps
CPU time 337.56 seconds
Started Dec 20 12:39:58 PM PST 23
Finished Dec 20 12:46:38 PM PST 23
Peak memory 182980 kb
Host smart-595deb70-25f6-46ec-9030-97073ea0a220
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382912160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2382912160
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1357554358
Short name T562
Test name
Test status
Simulation time 440274400100 ps
CPU time 171.46 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:44:02 PM PST 23
Peak memory 182912 kb
Host smart-ccd2eee8-819e-4705-828b-ebd0bdb9b0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357554358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1357554358
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2428514127
Short name T105
Test name
Test status
Simulation time 141181451427 ps
CPU time 261.51 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:45:16 PM PST 23
Peak memory 191008 kb
Host smart-92d4a12c-15fb-4b55-9d57-36c56c309796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428514127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2428514127
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1574870797
Short name T507
Test name
Test status
Simulation time 210660741 ps
CPU time 0.6 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:40:57 PM PST 23
Peak memory 182792 kb
Host smart-55d8bfd0-bb51-459a-9a28-a415fa2f0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574870797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1574870797
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.485214157
Short name T512
Test name
Test status
Simulation time 334486007857 ps
CPU time 674.78 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:52:19 PM PST 23
Peak memory 207324 kb
Host smart-79f573d5-b102-4bbd-8eed-cc43ba828299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485214157 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.485214157
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2917232566
Short name T99
Test name
Test status
Simulation time 23707803476 ps
CPU time 20.15 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 182776 kb
Host smart-c67e8982-3575-4815-ab81-7d4aae4dfed4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917232566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2917232566
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1708069589
Short name T528
Test name
Test status
Simulation time 102746949318 ps
CPU time 82.14 seconds
Started Dec 20 12:40:17 PM PST 23
Finished Dec 20 12:42:41 PM PST 23
Peak memory 182992 kb
Host smart-4ab88ef4-3552-4426-b81b-3f50c6383810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708069589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1708069589
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2893489399
Short name T197
Test name
Test status
Simulation time 73966452460 ps
CPU time 592.3 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:50:34 PM PST 23
Peak memory 183156 kb
Host smart-49a09637-18bd-4081-996c-4febc5913ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893489399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2893489399
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3934255318
Short name T133
Test name
Test status
Simulation time 35669112105 ps
CPU time 334.38 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:46:46 PM PST 23
Peak memory 194028 kb
Host smart-68148fc8-5d3d-4cea-956c-2bb39e36b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934255318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3934255318
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3391888900
Short name T561
Test name
Test status
Simulation time 61546569 ps
CPU time 0.55 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:40:53 PM PST 23
Peak memory 182608 kb
Host smart-8d865b33-1c58-427a-812d-cf5ec1fb2ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391888900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3391888900
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3867554969
Short name T182
Test name
Test status
Simulation time 1016634951449 ps
CPU time 884.74 seconds
Started Dec 20 12:40:11 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 213360 kb
Host smart-29f6ffc0-5421-4064-b3b9-0b5ae9fe7cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867554969 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3867554969
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.427176642
Short name T265
Test name
Test status
Simulation time 933652999414 ps
CPU time 883.95 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 182884 kb
Host smart-127b4126-c54e-42b8-9932-e65e24993379
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427176642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.427176642
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.248491134
Short name T570
Test name
Test status
Simulation time 220172632102 ps
CPU time 88.42 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 183052 kb
Host smart-15dc7006-2bb2-48a2-9d36-38b073e03f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248491134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.248491134
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.301795183
Short name T156
Test name
Test status
Simulation time 83317664519 ps
CPU time 136.61 seconds
Started Dec 20 12:40:01 PM PST 23
Finished Dec 20 12:43:20 PM PST 23
Peak memory 191284 kb
Host smart-585913be-d0dd-43c5-9105-3d886d3c0f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301795183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.301795183
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.352690019
Short name T94
Test name
Test status
Simulation time 220896592735 ps
CPU time 130.2 seconds
Started Dec 20 12:39:38 PM PST 23
Finished Dec 20 12:42:58 PM PST 23
Peak memory 183164 kb
Host smart-f2cdc75a-7b74-4776-9337-4ec85bf147c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352690019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.352690019
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.156225603
Short name T511
Test name
Test status
Simulation time 101731603092 ps
CPU time 200.65 seconds
Started Dec 20 12:39:38 PM PST 23
Finished Dec 20 12:44:05 PM PST 23
Peak memory 205952 kb
Host smart-d96a6470-4ef9-4d48-bc07-891c8446a4ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156225603 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.156225603
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3138964
Short name T264
Test name
Test status
Simulation time 391291590965 ps
CPU time 673.6 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:51:53 PM PST 23
Peak memory 183064 kb
Host smart-a01a67ae-65ea-41b4-ad5a-bef4b43082cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
rv_timer_cfg_update_on_fly.3138964
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1401176558
Short name T9
Test name
Test status
Simulation time 341262636741 ps
CPU time 265.9 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:45:16 PM PST 23
Peak memory 183040 kb
Host smart-5172b91c-51af-49b4-9113-fe8bae085b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401176558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1401176558
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3143084434
Short name T217
Test name
Test status
Simulation time 193591267749 ps
CPU time 532.04 seconds
Started Dec 20 12:39:52 PM PST 23
Finished Dec 20 12:49:53 PM PST 23
Peak memory 192136 kb
Host smart-eded0f78-f79d-497b-bd00-5ca4ff4d81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143084434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3143084434
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3040236889
Short name T491
Test name
Test status
Simulation time 118722030959 ps
CPU time 553.22 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:50:12 PM PST 23
Peak memory 207328 kb
Host smart-fedc7fd3-e86e-4cb5-b8d3-1bb57c3f68c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040236889 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3040236889
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1475867227
Short name T602
Test name
Test status
Simulation time 64894937264 ps
CPU time 99.66 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 182904 kb
Host smart-edd381af-a92d-4bf2-964c-1f7f55018c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475867227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1475867227
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1950747758
Short name T184
Test name
Test status
Simulation time 63178149366 ps
CPU time 507.97 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:49:13 PM PST 23
Peak memory 191016 kb
Host smart-4490b3db-6c33-484f-8a1d-afe8c9a0120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950747758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1950747758
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.460631592
Short name T605
Test name
Test status
Simulation time 55619634465 ps
CPU time 198.13 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:43:58 PM PST 23
Peak memory 197752 kb
Host smart-6662bcff-b83f-4bdb-bb33-3b4642143b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460631592 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.460631592
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.4205788707
Short name T171
Test name
Test status
Simulation time 356919981080 ps
CPU time 468.63 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:48:59 PM PST 23
Peak memory 194504 kb
Host smart-ae7d8d1d-0269-4d9a-b11e-71672b448fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205788707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4205788707
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.633498207
Short name T19
Test name
Test status
Simulation time 56638699677 ps
CPU time 74.25 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 191112 kb
Host smart-1d8ee19b-b042-4d5c-9882-0ca1cea66a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633498207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.633498207
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2237813269
Short name T256
Test name
Test status
Simulation time 29240468810 ps
CPU time 52.04 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:41:38 PM PST 23
Peak memory 191224 kb
Host smart-347d4eaf-3aa6-423f-8667-0d7f82402624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237813269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2237813269
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1022512197
Short name T299
Test name
Test status
Simulation time 18573986652 ps
CPU time 28.57 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 183060 kb
Host smart-0cd654f1-09a5-4fb6-8ec6-9fb80d09bdf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022512197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1022512197
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2561841693
Short name T354
Test name
Test status
Simulation time 227489227643 ps
CPU time 832.73 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:54:38 PM PST 23
Peak memory 191220 kb
Host smart-3eefc84e-9309-4bbb-a29d-2462316133cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561841693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2561841693
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1925333717
Short name T142
Test name
Test status
Simulation time 54328344377 ps
CPU time 90.66 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:42:20 PM PST 23
Peak memory 191204 kb
Host smart-3c5a8559-54f4-4efb-932d-bd565be085ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925333717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1925333717
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2336214744
Short name T98
Test name
Test status
Simulation time 109709618268 ps
CPU time 1798.43 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 01:11:13 PM PST 23
Peak memory 191136 kb
Host smart-6a8f5052-739a-4590-a5a5-78b78ca6fcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336214744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2336214744
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.384218814
Short name T558
Test name
Test status
Simulation time 1424019567 ps
CPU time 2.73 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:40:36 PM PST 23
Peak memory 182776 kb
Host smart-af2a79e6-c7ab-4ca1-9fed-f313f6d9d488
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384218814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.384218814
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.58451757
Short name T534
Test name
Test status
Simulation time 43025553956 ps
CPU time 55.54 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:41:54 PM PST 23
Peak memory 183116 kb
Host smart-898f5fb4-0091-407f-9615-d062a5ca8061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58451757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.58451757
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2574534110
Short name T300
Test name
Test status
Simulation time 66977771188 ps
CPU time 36.58 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:41:24 PM PST 23
Peak memory 183016 kb
Host smart-18653f71-2e7c-437f-9da4-7083fb2cb1ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574534110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2574534110
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3916344212
Short name T226
Test name
Test status
Simulation time 53414253538 ps
CPU time 88.19 seconds
Started Dec 20 12:39:17 PM PST 23
Finished Dec 20 12:41:52 PM PST 23
Peak memory 191212 kb
Host smart-f3001a57-f144-45e2-ace7-6871d4502e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916344212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3916344212
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.4250810042
Short name T499
Test name
Test status
Simulation time 92021586771 ps
CPU time 633.55 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:51:04 PM PST 23
Peak memory 205960 kb
Host smart-411b7bd0-1615-4c7a-b414-55806ebf9663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250810042 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.4250810042
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.105156224
Short name T378
Test name
Test status
Simulation time 185257512523 ps
CPU time 318.28 seconds
Started Dec 20 12:40:12 PM PST 23
Finished Dec 20 12:46:31 PM PST 23
Peak memory 182872 kb
Host smart-ef5e4824-6e6f-439b-b7f4-553b9a9424c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105156224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.105156224
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1463278072
Short name T213
Test name
Test status
Simulation time 23443964378 ps
CPU time 44.9 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 12:41:32 PM PST 23
Peak memory 183072 kb
Host smart-fb581fc3-aff1-484e-bdb8-d730bc1eded3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463278072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1463278072
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4100869545
Short name T369
Test name
Test status
Simulation time 116053384208 ps
CPU time 192.82 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:43:56 PM PST 23
Peak memory 191240 kb
Host smart-d35c8aa9-fb07-49fe-bcbb-29c3e092ddd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100869545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4100869545
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3347146700
Short name T584
Test name
Test status
Simulation time 77145254832 ps
CPU time 111.85 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:42:51 PM PST 23
Peak memory 183040 kb
Host smart-a09b037c-bcf8-4806-8c28-14bdbd8c0a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347146700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3347146700
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.740716940
Short name T291
Test name
Test status
Simulation time 184039788641 ps
CPU time 91.32 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:42:28 PM PST 23
Peak memory 194144 kb
Host smart-ef118534-4105-4612-89b2-d435ebfecc7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740716940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.740716940
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2726420174
Short name T90
Test name
Test status
Simulation time 851164898545 ps
CPU time 1523.78 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 01:06:45 PM PST 23
Peak memory 193132 kb
Host smart-df41df1e-4d18-4e48-bb56-84bcc8bfd531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726420174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2726420174
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1802629538
Short name T149
Test name
Test status
Simulation time 110681429542 ps
CPU time 305.75 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:46:26 PM PST 23
Peak memory 193508 kb
Host smart-17e11899-9f3e-44aa-aa3d-145ceb68d0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802629538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1802629538
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3544347097
Short name T364
Test name
Test status
Simulation time 17929019229 ps
CPU time 34.65 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 183108 kb
Host smart-1540e280-0008-4c8b-8c91-baf23822b618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544347097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3544347097
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.854664792
Short name T283
Test name
Test status
Simulation time 976525834598 ps
CPU time 395.06 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:47:32 PM PST 23
Peak memory 182944 kb
Host smart-d7bd5168-6ce6-4478-9568-ea52e73090c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854664792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.854664792
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2165260076
Short name T606
Test name
Test status
Simulation time 29140454001 ps
CPU time 45.86 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:41:11 PM PST 23
Peak memory 183000 kb
Host smart-f6f62799-9c11-42bf-a0ec-8d462abd0e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165260076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2165260076
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.155183661
Short name T178
Test name
Test status
Simulation time 94223234252 ps
CPU time 1410.06 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 01:04:19 PM PST 23
Peak memory 191056 kb
Host smart-1b257e9f-5a3a-4850-ab31-a3b4439f954c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155183661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.155183661
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3928528254
Short name T363
Test name
Test status
Simulation time 333791496401 ps
CPU time 178.71 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:43:27 PM PST 23
Peak memory 194180 kb
Host smart-e478e7ee-213f-4fe0-90e9-a94042970d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928528254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3928528254
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1888284443
Short name T11
Test name
Test status
Simulation time 78886991904 ps
CPU time 681.78 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:51:54 PM PST 23
Peak memory 206928 kb
Host smart-4de3c6a7-5f0c-4a14-8e15-c9340d24a389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888284443 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1888284443
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3142915130
Short name T242
Test name
Test status
Simulation time 661484463923 ps
CPU time 373.12 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:47:22 PM PST 23
Peak memory 193992 kb
Host smart-c0af88c8-1026-4b30-ae9f-d555d8cdba53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142915130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3142915130
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.831216535
Short name T610
Test name
Test status
Simulation time 353814801089 ps
CPU time 61.38 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 183004 kb
Host smart-6fdba7a8-e8e0-4e61-a507-6232eeb58e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831216535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.831216535
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1138891499
Short name T96
Test name
Test status
Simulation time 56945925937 ps
CPU time 147.09 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:43:38 PM PST 23
Peak memory 191136 kb
Host smart-1c4c14a1-bb54-4fed-a9be-e44a72956ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138891499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1138891499
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.365618408
Short name T343
Test name
Test status
Simulation time 119972864498 ps
CPU time 1026.54 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 183020 kb
Host smart-d40b14e0-37e1-48ce-973a-a00ed9a50329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365618408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.365618408
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1779841943
Short name T169
Test name
Test status
Simulation time 174399058687 ps
CPU time 265.52 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:45:34 PM PST 23
Peak memory 191116 kb
Host smart-bb47834e-b7f7-460a-809d-737bc835bfad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779841943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1779841943
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3472615117
Short name T321
Test name
Test status
Simulation time 398202785007 ps
CPU time 357.56 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:47:00 PM PST 23
Peak memory 182968 kb
Host smart-58216f28-c001-47cf-b5f6-5b952f0a0ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472615117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3472615117
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3381444275
Short name T26
Test name
Test status
Simulation time 19399579958 ps
CPU time 30.42 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 182828 kb
Host smart-1141225e-bbd5-4f8b-a660-52e3b1527fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381444275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3381444275
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2597752662
Short name T125
Test name
Test status
Simulation time 97406346127 ps
CPU time 146.85 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:43:48 PM PST 23
Peak memory 191216 kb
Host smart-17bb46b1-dab9-46c3-9828-0b588c0b1a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597752662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2597752662
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4091287624
Short name T575
Test name
Test status
Simulation time 9931928806 ps
CPU time 14.93 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 182648 kb
Host smart-df73429e-7a2b-4488-b80a-eac376964c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091287624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4091287624
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3616921045
Short name T325
Test name
Test status
Simulation time 54150046178 ps
CPU time 20.86 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 183020 kb
Host smart-50c1e84f-19cd-4c80-a32f-0d19a31d040f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616921045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3616921045
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3551374204
Short name T494
Test name
Test status
Simulation time 387072388604 ps
CPU time 170.86 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:43:27 PM PST 23
Peak memory 182864 kb
Host smart-62a1ccce-0969-44bf-ae20-461b0bf60737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551374204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3551374204
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.235977960
Short name T305
Test name
Test status
Simulation time 235747367211 ps
CPU time 98.45 seconds
Started Dec 20 12:40:03 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 191124 kb
Host smart-cd69b94c-042e-499a-9301-6f3ce2e2e591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235977960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.235977960
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1352579468
Short name T489
Test name
Test status
Simulation time 426264008 ps
CPU time 0.69 seconds
Started Dec 20 12:39:42 PM PST 23
Finished Dec 20 12:40:46 PM PST 23
Peak memory 182812 kb
Host smart-a238934a-d520-4aa7-85d2-a60027fb093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352579468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1352579468
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.744628220
Short name T259
Test name
Test status
Simulation time 1811079229228 ps
CPU time 1151.62 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 01:00:24 PM PST 23
Peak memory 191416 kb
Host smart-5973781b-a90c-4342-b62d-6a6064252107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744628220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.744628220
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3170995032
Short name T520
Test name
Test status
Simulation time 26698381658 ps
CPU time 514.81 seconds
Started Dec 20 12:39:33 PM PST 23
Finished Dec 20 12:49:16 PM PST 23
Peak memory 197576 kb
Host smart-7919e38b-37de-47ba-b242-d8609c56b34f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170995032 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3170995032
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3875612293
Short name T307
Test name
Test status
Simulation time 367239059550 ps
CPU time 239.85 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:44:58 PM PST 23
Peak memory 194320 kb
Host smart-eb9af07f-46ac-49f9-b83a-2f9720f06338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875612293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3875612293
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1866588465
Short name T344
Test name
Test status
Simulation time 116602319665 ps
CPU time 210.45 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:44:40 PM PST 23
Peak memory 194084 kb
Host smart-e3750dd7-0e11-49bf-b01f-0a61ba6f26f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866588465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1866588465
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1320040049
Short name T296
Test name
Test status
Simulation time 380090411129 ps
CPU time 957.16 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 191196 kb
Host smart-3d1425a6-ebbd-4d69-870d-e95ffb5dc0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320040049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1320040049
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3844879840
Short name T549
Test name
Test status
Simulation time 23399426472 ps
CPU time 31.1 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 182696 kb
Host smart-31efb845-f2c0-4a9d-8140-dcdfa888ad04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844879840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3844879840
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1531660206
Short name T170
Test name
Test status
Simulation time 402923602148 ps
CPU time 719.36 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:52:57 PM PST 23
Peak memory 191240 kb
Host smart-ca3596e1-f7d5-4381-851f-f3eb647ce6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531660206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1531660206
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.928624079
Short name T331
Test name
Test status
Simulation time 94861839434 ps
CPU time 515.67 seconds
Started Dec 20 12:39:43 PM PST 23
Finished Dec 20 12:49:34 PM PST 23
Peak memory 191264 kb
Host smart-9fefdf98-817f-4e3c-b8f0-9ed659ea335c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928624079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.928624079
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1301832253
Short name T341
Test name
Test status
Simulation time 54680360812 ps
CPU time 29.88 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:41:27 PM PST 23
Peak memory 183060 kb
Host smart-e4016fdc-68fb-4987-ba93-9f27135e926a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301832253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1301832253
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3759268673
Short name T336
Test name
Test status
Simulation time 409976370449 ps
CPU time 1062.87 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:58:59 PM PST 23
Peak memory 182840 kb
Host smart-7f3bf0fc-8df2-4173-9147-93df6e3fba58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759268673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3759268673
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3816240667
Short name T21
Test name
Test status
Simulation time 173510908146 ps
CPU time 90.63 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 183072 kb
Host smart-dc69919d-6359-4931-b0c2-f6b17d065d0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816240667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3816240667
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.418643368
Short name T531
Test name
Test status
Simulation time 58034828749 ps
CPU time 45.45 seconds
Started Dec 20 12:39:38 PM PST 23
Finished Dec 20 12:41:33 PM PST 23
Peak memory 182868 kb
Host smart-a029a6fe-1bb1-4169-be44-1ddf51e467ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418643368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.418643368
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1137863186
Short name T317
Test name
Test status
Simulation time 71100742558 ps
CPU time 33.69 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:40:42 PM PST 23
Peak memory 191160 kb
Host smart-de881640-f341-4549-ae08-a024b14f4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137863186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1137863186
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2420052240
Short name T496
Test name
Test status
Simulation time 817073728068 ps
CPU time 324.63 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 12:46:07 PM PST 23
Peak memory 191216 kb
Host smart-c6806e7a-77a8-4e23-9b49-d3903bdfd07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420052240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2420052240
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1265204333
Short name T146
Test name
Test status
Simulation time 120917205009 ps
CPU time 1214.01 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 01:00:43 PM PST 23
Peak memory 206764 kb
Host smart-45319617-b27f-4923-bf33-434a5a9a6edf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265204333 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1265204333
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1112914404
Short name T205
Test name
Test status
Simulation time 166022665739 ps
CPU time 166.26 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:43:52 PM PST 23
Peak memory 191236 kb
Host smart-edd70f17-b119-4260-a089-102f488712fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112914404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1112914404
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.610016372
Short name T147
Test name
Test status
Simulation time 209640305245 ps
CPU time 197.05 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:44:23 PM PST 23
Peak memory 194096 kb
Host smart-2c6e74c0-b440-4a51-b17c-02c3af831737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610016372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.610016372
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.684719267
Short name T613
Test name
Test status
Simulation time 42731221474 ps
CPU time 55.34 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:41:52 PM PST 23
Peak memory 182928 kb
Host smart-b2f8ca41-6dfa-46eb-83ae-ac5f33a211ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684719267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.684719267
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2459174239
Short name T246
Test name
Test status
Simulation time 192633452504 ps
CPU time 147 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:44:07 PM PST 23
Peak memory 191136 kb
Host smart-0e9308f0-4cc3-4cb9-8ae8-5ee8691aad32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459174239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2459174239
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2200828377
Short name T361
Test name
Test status
Simulation time 358048934037 ps
CPU time 177.7 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:43:56 PM PST 23
Peak memory 191240 kb
Host smart-6e4f3116-426a-4486-9804-c2e7e87cdaff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200828377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2200828377
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2209148712
Short name T243
Test name
Test status
Simulation time 75042047396 ps
CPU time 264.34 seconds
Started Dec 20 12:39:52 PM PST 23
Finished Dec 20 12:45:25 PM PST 23
Peak memory 191128 kb
Host smart-8bf55b08-0e93-41c6-a359-6584159c1896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209148712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2209148712
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3452141648
Short name T111
Test name
Test status
Simulation time 13292619509 ps
CPU time 11.51 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 191300 kb
Host smart-95ad284a-ff1f-4cf0-8cad-b7fb1f128d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452141648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3452141648
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.706890709
Short name T583
Test name
Test status
Simulation time 147482003960 ps
CPU time 310.28 seconds
Started Dec 20 12:40:17 PM PST 23
Finished Dec 20 12:46:37 PM PST 23
Peak memory 191164 kb
Host smart-d1000baf-7774-4f96-baf5-91c13beb4f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706890709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.706890709
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2904098693
Short name T375
Test name
Test status
Simulation time 260292238405 ps
CPU time 218.57 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:45:03 PM PST 23
Peak memory 191164 kb
Host smart-31536aa0-3ff4-407d-9349-8f5385325a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904098693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2904098693
Directory /workspace/99.rv_timer_random/latest
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