Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 618
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T558 /workspace/coverage/default/48.rv_timer_disabled.3497855853 Dec 24 12:38:41 PM PST 23 Dec 24 12:41:48 PM PST 23 339329286059 ps
T368 /workspace/coverage/default/198.rv_timer_random.2093112227 Dec 24 12:39:37 PM PST 23 Dec 24 12:52:41 PM PST 23 765735451223 ps
T376 /workspace/coverage/default/14.rv_timer_random_reset.3357866270 Dec 24 12:38:07 PM PST 23 Dec 24 12:45:29 PM PST 23 53918045327 ps
T337 /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1406557621 Dec 24 12:38:02 PM PST 23 Dec 24 12:47:35 PM PST 23 652588720090 ps
T290 /workspace/coverage/default/65.rv_timer_random.2740252644 Dec 24 12:38:57 PM PST 23 Dec 24 12:45:39 PM PST 23 646025596769 ps
T559 /workspace/coverage/default/10.rv_timer_random_reset.201821103 Dec 24 12:37:47 PM PST 23 Dec 24 12:38:19 PM PST 23 49065542001 ps
T176 /workspace/coverage/default/11.rv_timer_stress_all.3134646301 Dec 24 12:37:53 PM PST 23 Dec 24 12:52:09 PM PST 23 552927446685 ps
T324 /workspace/coverage/default/109.rv_timer_random.2332827662 Dec 24 12:39:10 PM PST 23 Dec 24 12:40:32 PM PST 23 56019921381 ps
T560 /workspace/coverage/default/5.rv_timer_disabled.2748485490 Dec 24 12:37:42 PM PST 23 Dec 24 12:39:12 PM PST 23 192645522982 ps
T355 /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.516730992 Dec 24 12:38:25 PM PST 23 Dec 24 12:42:48 PM PST 23 299145459362 ps
T183 /workspace/coverage/default/15.rv_timer_random.2701250426 Dec 24 12:38:09 PM PST 23 Dec 24 12:39:55 PM PST 23 46611197083 ps
T561 /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2811638623 Dec 24 12:38:54 PM PST 23 Dec 24 12:40:44 PM PST 23 96857228367 ps
T261 /workspace/coverage/default/134.rv_timer_random.973192932 Dec 24 12:39:10 PM PST 23 Dec 24 12:45:29 PM PST 23 211595388147 ps
T562 /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.95802716 Dec 24 12:38:13 PM PST 23 Dec 24 12:57:51 PM PST 23 709307550543 ps
T378 /workspace/coverage/default/55.rv_timer_random.2047937581 Dec 24 12:39:04 PM PST 23 Dec 24 12:41:34 PM PST 23 185455877126 ps
T563 /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3884306760 Dec 24 12:38:45 PM PST 23 Dec 24 12:53:26 PM PST 23 704586459594 ps
T564 /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2408214690 Dec 24 12:38:11 PM PST 23 Dec 24 12:41:51 PM PST 23 200237039219 ps
T565 /workspace/coverage/default/27.rv_timer_disabled.3043364200 Dec 24 12:38:16 PM PST 23 Dec 24 12:38:29 PM PST 23 13586331134 ps
T566 /workspace/coverage/default/32.rv_timer_disabled.2608039070 Dec 24 12:38:10 PM PST 23 Dec 24 12:38:46 PM PST 23 19596229393 ps
T18 /workspace/coverage/default/2.rv_timer_sec_cm.3723967409 Dec 24 12:37:52 PM PST 23 Dec 24 12:37:56 PM PST 23 83911158 ps
T379 /workspace/coverage/default/108.rv_timer_random.3357979513 Dec 24 12:39:06 PM PST 23 Dec 24 12:46:59 PM PST 23 565675300880 ps
T567 /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.4102569705 Dec 24 12:39:00 PM PST 23 Dec 24 12:48:23 PM PST 23 76313597559 ps
T341 /workspace/coverage/default/5.rv_timer_random.975376349 Dec 24 12:37:41 PM PST 23 Dec 24 12:39:46 PM PST 23 211675729528 ps
T234 /workspace/coverage/default/139.rv_timer_random.765591798 Dec 24 12:39:39 PM PST 23 Dec 24 12:52:21 PM PST 23 363281994830 ps
T568 /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.609739665 Dec 24 12:38:39 PM PST 23 Dec 24 12:42:06 PM PST 23 43538904660 ps
T346 /workspace/coverage/default/6.rv_timer_random.3907531683 Dec 24 12:37:51 PM PST 23 Dec 24 12:52:28 PM PST 23 551943623029 ps
T220 /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2717393227 Dec 24 12:38:40 PM PST 23 Dec 24 12:41:32 PM PST 23 148760491106 ps
T569 /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1482275061 Dec 24 12:38:41 PM PST 23 Dec 24 12:47:15 PM PST 23 97864272157 ps
T570 /workspace/coverage/default/30.rv_timer_disabled.1858730945 Dec 24 12:38:27 PM PST 23 Dec 24 12:41:44 PM PST 23 247474714066 ps
T213 /workspace/coverage/default/49.rv_timer_stress_all.3111965128 Dec 24 12:39:05 PM PST 23 Dec 24 01:09:44 PM PST 23 945917430225 ps
T571 /workspace/coverage/default/0.rv_timer_disabled.2316366019 Dec 24 12:38:00 PM PST 23 Dec 24 12:39:16 PM PST 23 47450579817 ps
T195 /workspace/coverage/default/20.rv_timer_stress_all.4131352580 Dec 24 12:38:11 PM PST 23 Dec 24 12:56:16 PM PST 23 721461563606 ps
T235 /workspace/coverage/default/45.rv_timer_stress_all.310416991 Dec 24 12:38:37 PM PST 23 Dec 24 12:55:27 PM PST 23 281208389439 ps
T207 /workspace/coverage/default/24.rv_timer_random.2158269463 Dec 24 12:38:25 PM PST 23 Dec 24 12:42:02 PM PST 23 377024200695 ps
T338 /workspace/coverage/default/42.rv_timer_random.4229859300 Dec 24 12:38:44 PM PST 23 Dec 24 12:39:28 PM PST 23 16701934350 ps
T572 /workspace/coverage/default/110.rv_timer_random.1364746776 Dec 24 12:39:08 PM PST 23 Dec 24 12:40:38 PM PST 23 115260412774 ps
T365 /workspace/coverage/default/142.rv_timer_random.4226576701 Dec 24 12:39:41 PM PST 23 Dec 24 01:17:52 PM PST 23 337589999990 ps
T573 /workspace/coverage/default/33.rv_timer_disabled.1455459873 Dec 24 12:38:36 PM PST 23 Dec 24 12:41:08 PM PST 23 170186900483 ps
T214 /workspace/coverage/default/177.rv_timer_random.406475146 Dec 24 12:39:42 PM PST 23 Dec 24 12:44:26 PM PST 23 385890338989 ps
T205 /workspace/coverage/default/153.rv_timer_random.627658028 Dec 24 12:39:36 PM PST 23 Dec 24 12:47:29 PM PST 23 948480416936 ps
T375 /workspace/coverage/default/27.rv_timer_random_reset.1156253590 Dec 24 12:38:18 PM PST 23 Dec 24 12:39:47 PM PST 23 244247153744 ps
T574 /workspace/coverage/default/35.rv_timer_random_reset.2289174392 Dec 24 12:38:29 PM PST 23 Dec 24 12:38:47 PM PST 23 2522043937 ps
T575 /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1180868498 Dec 24 12:38:52 PM PST 23 Dec 24 12:44:52 PM PST 23 690904640140 ps
T291 /workspace/coverage/default/47.rv_timer_random.663680086 Dec 24 12:38:55 PM PST 23 Dec 24 12:42:53 PM PST 23 154162418189 ps
T576 /workspace/coverage/default/136.rv_timer_random.3726819525 Dec 24 12:39:08 PM PST 23 Dec 24 12:42:03 PM PST 23 171159501880 ps
T147 /workspace/coverage/default/47.rv_timer_stress_all.3645819762 Dec 24 12:38:42 PM PST 23 Dec 24 01:10:30 PM PST 23 2696819321189 ps
T163 /workspace/coverage/default/145.rv_timer_random.3696850299 Dec 24 12:39:41 PM PST 23 Dec 24 12:48:37 PM PST 23 150548832272 ps
T349 /workspace/coverage/default/154.rv_timer_random.2810210821 Dec 24 12:39:39 PM PST 23 Dec 24 12:41:28 PM PST 23 64097673376 ps
T577 /workspace/coverage/default/22.rv_timer_disabled.3552157223 Dec 24 12:38:11 PM PST 23 Dec 24 12:43:21 PM PST 23 701560768805 ps
T262 /workspace/coverage/default/118.rv_timer_random.2477971435 Dec 24 12:39:02 PM PST 23 Dec 24 12:52:28 PM PST 23 206002393227 ps
T578 /workspace/coverage/default/179.rv_timer_random.3703319662 Dec 24 12:39:36 PM PST 23 Dec 24 12:48:00 PM PST 23 358754561063 ps
T579 /workspace/coverage/default/28.rv_timer_random_reset.2245291401 Dec 24 12:38:11 PM PST 23 Dec 24 12:38:13 PM PST 23 244096193 ps
T344 /workspace/coverage/default/193.rv_timer_random.2054575129 Dec 24 12:39:42 PM PST 23 Dec 24 12:41:41 PM PST 23 67317023216 ps
T580 /workspace/coverage/default/42.rv_timer_random_reset.563273159 Dec 24 12:38:41 PM PST 23 Dec 24 12:46:11 PM PST 23 87883813135 ps
T581 /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.39031849 Dec 24 12:38:38 PM PST 23 Dec 24 12:39:02 PM PST 23 5067086694 ps
T582 /workspace/coverage/default/94.rv_timer_random.3056120084 Dec 24 12:39:01 PM PST 23 Dec 24 12:40:28 PM PST 23 39747547276 ps
T583 /workspace/coverage/default/41.rv_timer_random_reset.1888100317 Dec 24 12:38:28 PM PST 23 Dec 24 12:38:30 PM PST 23 211934586 ps
T584 /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.72265515 Dec 24 12:38:38 PM PST 23 Dec 24 12:54:51 PM PST 23 232217628185 ps
T585 /workspace/coverage/default/8.rv_timer_stress_all.4113677337 Dec 24 12:37:59 PM PST 23 Dec 24 12:40:11 PM PST 23 74854195022 ps
T373 /workspace/coverage/default/36.rv_timer_random.398539341 Dec 24 12:38:25 PM PST 23 Dec 24 12:43:43 PM PST 23 601450617061 ps
T380 /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2207443040 Dec 24 12:38:11 PM PST 23 Dec 24 12:38:55 PM PST 23 74508564203 ps
T586 /workspace/coverage/default/26.rv_timer_disabled.4203851620 Dec 24 12:38:12 PM PST 23 Dec 24 12:42:40 PM PST 23 171893143265 ps
T361 /workspace/coverage/default/10.rv_timer_stress_all.2827393462 Dec 24 12:37:54 PM PST 23 Dec 24 12:55:59 PM PST 23 607862458866 ps
T311 /workspace/coverage/default/169.rv_timer_random.565225437 Dec 24 12:39:39 PM PST 23 Dec 24 12:50:29 PM PST 23 525783267493 ps
T169 /workspace/coverage/default/26.rv_timer_stress_all.1567978289 Dec 24 12:38:15 PM PST 23 Dec 24 12:59:17 PM PST 23 1794914434243 ps
T587 /workspace/coverage/default/31.rv_timer_disabled.1443480997 Dec 24 12:38:34 PM PST 23 Dec 24 12:41:10 PM PST 23 203603897991 ps
T588 /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3530611068 Dec 24 12:38:01 PM PST 23 Dec 24 12:48:25 PM PST 23 307440117121 ps
T322 /workspace/coverage/default/6.rv_timer_random_reset.1551107989 Dec 24 12:38:03 PM PST 23 Dec 24 12:41:34 PM PST 23 95852841553 ps
T589 /workspace/coverage/default/22.rv_timer_random_reset.464517734 Dec 24 12:38:27 PM PST 23 Dec 24 12:38:31 PM PST 23 852384218 ps
T590 /workspace/coverage/default/41.rv_timer_disabled.1429267584 Dec 24 12:38:28 PM PST 23 Dec 24 12:40:17 PM PST 23 240070688091 ps
T591 /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.311143277 Dec 24 12:38:11 PM PST 23 Dec 24 12:50:35 PM PST 23 350849516947 ps
T592 /workspace/coverage/default/165.rv_timer_random.3513383904 Dec 24 12:39:39 PM PST 23 Dec 24 12:45:14 PM PST 23 182065613595 ps
T593 /workspace/coverage/default/28.rv_timer_disabled.2276834801 Dec 24 12:38:07 PM PST 23 Dec 24 12:40:18 PM PST 23 295995058086 ps
T594 /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1972414380 Dec 24 12:38:31 PM PST 23 Dec 24 12:43:39 PM PST 23 518314536767 ps
T595 /workspace/coverage/default/30.rv_timer_random.1522399185 Dec 24 12:38:09 PM PST 23 Dec 24 12:39:34 PM PST 23 46697275384 ps
T596 /workspace/coverage/default/20.rv_timer_random_reset.3438417716 Dec 24 12:38:09 PM PST 23 Dec 24 12:38:12 PM PST 23 2123636584 ps
T330 /workspace/coverage/default/116.rv_timer_random.1064523550 Dec 24 12:39:03 PM PST 23 Dec 24 12:53:07 PM PST 23 257921627218 ps
T360 /workspace/coverage/default/81.rv_timer_random.4115458636 Dec 24 12:38:57 PM PST 23 Dec 24 12:45:49 PM PST 23 124592433581 ps
T198 /workspace/coverage/default/44.rv_timer_stress_all.331717071 Dec 24 12:38:46 PM PST 23 Dec 24 01:06:30 PM PST 23 820629296199 ps
T258 /workspace/coverage/default/21.rv_timer_stress_all.693896177 Dec 24 12:38:08 PM PST 23 Dec 24 12:45:38 PM PST 23 465241978693 ps
T597 /workspace/coverage/default/175.rv_timer_random.1167884380 Dec 24 12:39:38 PM PST 23 Dec 24 12:43:53 PM PST 23 1496390807324 ps
T299 /workspace/coverage/default/170.rv_timer_random.4082165088 Dec 24 12:39:36 PM PST 23 Dec 24 12:50:56 PM PST 23 328310918947 ps
T358 /workspace/coverage/default/20.rv_timer_random.4062781971 Dec 24 12:37:50 PM PST 23 Dec 24 12:39:19 PM PST 23 136218773573 ps
T598 /workspace/coverage/default/25.rv_timer_random.1981391963 Dec 24 12:38:18 PM PST 23 Dec 24 12:38:38 PM PST 23 11844172770 ps
T599 /workspace/coverage/default/12.rv_timer_disabled.52891619 Dec 24 12:38:02 PM PST 23 Dec 24 12:40:20 PM PST 23 90443118849 ps
T600 /workspace/coverage/default/11.rv_timer_random_reset.3852116852 Dec 24 12:37:50 PM PST 23 Dec 24 12:37:55 PM PST 23 1029266044 ps
T601 /workspace/coverage/default/23.rv_timer_random_reset.2983698152 Dec 24 12:38:25 PM PST 23 Dec 24 12:39:19 PM PST 23 90206350077 ps
T374 /workspace/coverage/default/194.rv_timer_random.1580050494 Dec 24 12:39:44 PM PST 23 Dec 24 12:44:30 PM PST 23 650519204653 ps
T602 /workspace/coverage/default/37.rv_timer_disabled.154635447 Dec 24 12:38:27 PM PST 23 Dec 24 12:41:22 PM PST 23 418398733226 ps
T319 /workspace/coverage/default/82.rv_timer_random.2559811002 Dec 24 12:38:58 PM PST 23 Dec 24 12:42:51 PM PST 23 441013937074 ps
T364 /workspace/coverage/default/172.rv_timer_random.4181948867 Dec 24 12:39:37 PM PST 23 Dec 24 12:43:34 PM PST 23 206844519655 ps
T359 /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3698945496 Dec 24 12:37:57 PM PST 23 Dec 24 12:52:36 PM PST 23 416332714203 ps
T369 /workspace/coverage/default/4.rv_timer_stress_all.3493351356 Dec 24 12:38:03 PM PST 23 Dec 24 12:44:30 PM PST 23 655923437179 ps
T603 /workspace/coverage/default/21.rv_timer_random_reset.3597365151 Dec 24 12:38:15 PM PST 23 Dec 24 12:45:12 PM PST 23 101551019948 ps
T353 /workspace/coverage/default/160.rv_timer_random.3484476440 Dec 24 12:39:37 PM PST 23 Dec 24 12:51:53 PM PST 23 320964437559 ps
T371 /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2851054871 Dec 24 12:37:48 PM PST 23 Dec 24 01:01:15 PM PST 23 1328024657028 ps
T604 /workspace/coverage/default/152.rv_timer_random.3049222733 Dec 24 12:39:38 PM PST 23 Dec 24 12:40:17 PM PST 23 76107910021 ps
T605 /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2431558076 Dec 24 12:38:08 PM PST 23 Dec 24 12:48:27 PM PST 23 109636716784 ps
T347 /workspace/coverage/default/191.rv_timer_random.3552205631 Dec 24 12:39:43 PM PST 23 Dec 24 12:50:54 PM PST 23 159474623731 ps
T606 /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2575333353 Dec 24 12:38:31 PM PST 23 Dec 24 12:48:27 PM PST 23 32917185560 ps
T350 /workspace/coverage/default/147.rv_timer_random.292823688 Dec 24 12:39:37 PM PST 23 Dec 24 12:41:09 PM PST 23 214049037691 ps
T377 /workspace/coverage/default/162.rv_timer_random.1158577374 Dec 24 12:39:37 PM PST 23 Dec 24 12:41:00 PM PST 23 51006656567 ps
T607 /workspace/coverage/default/35.rv_timer_random.3555448189 Dec 24 12:38:47 PM PST 23 Dec 24 12:43:32 PM PST 23 164562413722 ps
T608 /workspace/coverage/default/26.rv_timer_random.2681382009 Dec 24 12:38:15 PM PST 23 Dec 24 12:39:30 PM PST 23 17229657828 ps
T609 /workspace/coverage/default/183.rv_timer_random.3817101075 Dec 24 12:39:56 PM PST 23 Dec 24 12:40:56 PM PST 23 127782655168 ps
T305 /workspace/coverage/default/36.rv_timer_random_reset.741547154 Dec 24 12:38:31 PM PST 23 Dec 24 12:42:02 PM PST 23 487161351368 ps
T610 /workspace/coverage/default/121.rv_timer_random.3430874393 Dec 24 12:39:01 PM PST 23 Dec 24 12:47:08 PM PST 23 82720389484 ps
T611 /workspace/coverage/default/95.rv_timer_random.533987194 Dec 24 12:39:14 PM PST 23 Dec 24 12:40:58 PM PST 23 37357796862 ps
T612 /workspace/coverage/default/23.rv_timer_random.3837982396 Dec 24 12:38:10 PM PST 23 Dec 24 12:39:42 PM PST 23 238147953994 ps
T189 /workspace/coverage/default/43.rv_timer_random_reset.2976535493 Dec 24 12:38:40 PM PST 23 Dec 24 01:01:26 PM PST 23 319865621691 ps
T351 /workspace/coverage/default/199.rv_timer_random.2912093004 Dec 24 12:39:46 PM PST 23 Dec 24 12:51:56 PM PST 23 228166116407 ps
T613 /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.646773232 Dec 24 12:38:08 PM PST 23 Dec 24 12:51:15 PM PST 23 806635001887 ps
T614 /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.789691518 Dec 24 12:38:08 PM PST 23 Dec 24 12:51:51 PM PST 23 80351439208 ps
T615 /workspace/coverage/default/19.rv_timer_disabled.196279461 Dec 24 12:37:47 PM PST 23 Dec 24 12:39:31 PM PST 23 68564135536 ps
T616 /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.807936667 Dec 24 12:38:12 PM PST 23 Dec 24 12:42:52 PM PST 23 116822461330 ps
T170 /workspace/coverage/default/31.rv_timer_stress_all.3058349058 Dec 24 12:38:13 PM PST 23 Dec 24 01:44:44 PM PST 23 3312602482866 ps
T617 /workspace/coverage/default/85.rv_timer_random.452214130 Dec 24 12:39:09 PM PST 23 Dec 24 12:41:22 PM PST 23 174073287658 ps
T618 /workspace/coverage/default/38.rv_timer_disabled.722078900 Dec 24 12:38:32 PM PST 23 Dec 24 12:39:58 PM PST 23 196746892239 ps

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1697231104
Short name T2
Test name
Test status
Simulation time 85920794950 ps
CPU time 199.54 seconds
Started Dec 24 12:37:56 PM PST 23
Finished Dec 24 12:41:21 PM PST 23
Peak memory 197632 kb
Host smart-131b4a0e-4b82-4f04-9b52-fbb04e40d7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697231104 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1697231104
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2272349551
Short name T30
Test name
Test status
Simulation time 2367187108258 ps
CPU time 6316.62 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 02:23:32 PM PST 23
Peak memory 191012 kb
Host smart-cdc81270-46ae-4aa3-9caf-5f4a6725a202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272349551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2272349551
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.722016819
Short name T14
Test name
Test status
Simulation time 452585355 ps
CPU time 0.78 seconds
Started Dec 24 12:37:45 PM PST 23
Finished Dec 24 12:37:49 PM PST 23
Peak memory 212852 kb
Host smart-68fc9e4b-0d6d-4948-8d09-747ee98dbea6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722016819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.722016819
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4286167108
Short name T84
Test name
Test status
Simulation time 1231820728917 ps
CPU time 1674.82 seconds
Started Dec 24 12:37:44 PM PST 23
Finished Dec 24 01:05:43 PM PST 23
Peak memory 191016 kb
Host smart-4e2803a7-568a-4b38-a32b-e05df30ecf26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286167108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4286167108
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4136764947
Short name T153
Test name
Test status
Simulation time 766033228357 ps
CPU time 1347.89 seconds
Started Dec 24 12:38:28 PM PST 23
Finished Dec 24 01:00:58 PM PST 23
Peak memory 190984 kb
Host smart-467ebc69-2a40-4e12-9233-1d5945e02b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136764947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4136764947
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3398896599
Short name T37
Test name
Test status
Simulation time 18254259 ps
CPU time 0.59 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 183268 kb
Host smart-c4793ca8-d530-46ae-a245-e0d9ea1cf0e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398896599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3398896599
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.331717071
Short name T198
Test name
Test status
Simulation time 820629296199 ps
CPU time 1651.41 seconds
Started Dec 24 12:38:46 PM PST 23
Finished Dec 24 01:06:30 PM PST 23
Peak memory 191168 kb
Host smart-8d695f04-c198-483b-9335-3fd9fe7da0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331717071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
331717071
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3645819762
Short name T147
Test name
Test status
Simulation time 2696819321189 ps
CPU time 1892.65 seconds
Started Dec 24 12:38:42 PM PST 23
Finished Dec 24 01:10:30 PM PST 23
Peak memory 191108 kb
Host smart-579d641c-4add-4702-8805-d2affe4e63a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645819762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3645819762
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3643500750
Short name T252
Test name
Test status
Simulation time 1544125166074 ps
CPU time 2819.07 seconds
Started Dec 24 12:37:56 PM PST 23
Finished Dec 24 01:25:01 PM PST 23
Peak memory 191172 kb
Host smart-eda61d67-acb9-459e-8e09-5932069c5395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643500750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3643500750
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2826855720
Short name T28
Test name
Test status
Simulation time 282486674 ps
CPU time 1.13 seconds
Started Dec 24 01:41:27 PM PST 23
Finished Dec 24 01:41:30 PM PST 23
Peak memory 195272 kb
Host smart-bbf57172-e19c-41f4-ba6e-228db7328ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826855720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2826855720
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3406865154
Short name T123
Test name
Test status
Simulation time 431800148162 ps
CPU time 494.31 seconds
Started Dec 24 12:37:58 PM PST 23
Finished Dec 24 12:46:16 PM PST 23
Peak memory 191148 kb
Host smart-3b5102ee-9d3c-400c-a96d-511cb9fa3848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406865154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3406865154
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2448184120
Short name T219
Test name
Test status
Simulation time 435641611871 ps
CPU time 958.57 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 12:54:56 PM PST 23
Peak memory 191152 kb
Host smart-965d6738-b33e-4def-933a-f61bcfaf37a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448184120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2448184120
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3134646301
Short name T176
Test name
Test status
Simulation time 552927446685 ps
CPU time 852.98 seconds
Started Dec 24 12:37:53 PM PST 23
Finished Dec 24 12:52:09 PM PST 23
Peak memory 191212 kb
Host smart-ceb4319e-d8e1-42eb-a846-ce3149e21e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134646301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3134646301
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2960252316
Short name T187
Test name
Test status
Simulation time 558637158315 ps
CPU time 770.96 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:51:24 PM PST 23
Peak memory 191148 kb
Host smart-6e556274-703c-4d24-950c-842fb943afb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960252316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2960252316
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.1363513892
Short name T148
Test name
Test status
Simulation time 534923655509 ps
CPU time 336.13 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:45:17 PM PST 23
Peak memory 191028 kb
Host smart-b30b2219-98ed-4774-8291-a3d4a25c640d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363513892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1363513892
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1570502433
Short name T134
Test name
Test status
Simulation time 505024904059 ps
CPU time 544.99 seconds
Started Dec 24 12:37:42 PM PST 23
Finished Dec 24 12:46:52 PM PST 23
Peak memory 191084 kb
Host smart-16ad805f-16a7-4fae-8387-c228de41fc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570502433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1570502433
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3171540322
Short name T209
Test name
Test status
Simulation time 269872613828 ps
CPU time 463.01 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:45:37 PM PST 23
Peak memory 191152 kb
Host smart-a0d0aa03-7ee3-4476-af41-f0af281f4ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171540322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3171540322
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2700574469
Short name T277
Test name
Test status
Simulation time 1129813997223 ps
CPU time 2055.86 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 01:12:49 PM PST 23
Peak memory 195628 kb
Host smart-427fe2c5-e91e-4c1d-a2bd-78652e940dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700574469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2700574469
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.1482937546
Short name T119
Test name
Test status
Simulation time 266657017878 ps
CPU time 498.79 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:47:26 PM PST 23
Peak memory 190996 kb
Host smart-8bf4abdc-5bcf-4760-a299-62303e36e8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482937546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1482937546
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2675266312
Short name T126
Test name
Test status
Simulation time 670009616559 ps
CPU time 403.75 seconds
Started Dec 24 12:39:13 PM PST 23
Finished Dec 24 12:45:58 PM PST 23
Peak memory 191156 kb
Host smart-9668f9c4-90bb-4cad-b6d3-4acd94bfae0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675266312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2675266312
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1372966996
Short name T11
Test name
Test status
Simulation time 125153851404 ps
CPU time 881.22 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:52:53 PM PST 23
Peak memory 214032 kb
Host smart-ac1d59ca-8827-4d6b-8aff-414fd90c33bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372966996 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1372966996
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3141179799
Short name T136
Test name
Test status
Simulation time 272676648381 ps
CPU time 481.08 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:46:13 PM PST 23
Peak memory 191148 kb
Host smart-7ca2218f-ae74-4455-9e66-b55eb630a921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141179799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3141179799
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3764948370
Short name T91
Test name
Test status
Simulation time 398469204667 ps
CPU time 3816.17 seconds
Started Dec 24 12:38:14 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 191080 kb
Host smart-061053ca-e648-4857-b83f-ebb4437deaab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764948370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3764948370
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.627658028
Short name T205
Test name
Test status
Simulation time 948480416936 ps
CPU time 469.13 seconds
Started Dec 24 12:39:36 PM PST 23
Finished Dec 24 12:47:29 PM PST 23
Peak memory 191048 kb
Host smart-828c5ed5-58fd-4b94-8943-9aaf6e729c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627658028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.627658028
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3552205631
Short name T347
Test name
Test status
Simulation time 159474623731 ps
CPU time 667.7 seconds
Started Dec 24 12:39:43 PM PST 23
Finished Dec 24 12:50:54 PM PST 23
Peak memory 194620 kb
Host smart-303ef588-c4b1-43e0-b171-8b117f010241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552205631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3552205631
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.2596312866
Short name T184
Test name
Test status
Simulation time 244335154590 ps
CPU time 228.58 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:42:56 PM PST 23
Peak memory 191176 kb
Host smart-b3a025ba-8bfd-4db4-830b-4bccbc4555eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596312866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2596312866
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2245383993
Short name T296
Test name
Test status
Simulation time 634388965487 ps
CPU time 568.08 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:49:08 PM PST 23
Peak memory 191192 kb
Host smart-b4731e93-41f1-41e4-8abd-853d034aa0ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245383993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2245383993
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.4082165088
Short name T299
Test name
Test status
Simulation time 328310918947 ps
CPU time 675.82 seconds
Started Dec 24 12:39:36 PM PST 23
Finished Dec 24 12:50:56 PM PST 23
Peak memory 191180 kb
Host smart-b1ba08eb-82c6-4c8a-9283-64807b2e2be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082165088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4082165088
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2854678562
Short name T225
Test name
Test status
Simulation time 1151837765986 ps
CPU time 989 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:55:03 PM PST 23
Peak memory 182840 kb
Host smart-b26863d3-63b0-4e68-898c-28fd89047166
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854678562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2854678562
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/88.rv_timer_random.2523237282
Short name T309
Test name
Test status
Simulation time 594563205832 ps
CPU time 631.69 seconds
Started Dec 24 12:39:05 PM PST 23
Finished Dec 24 12:49:40 PM PST 23
Peak memory 191048 kb
Host smart-3749a6f6-d4a9-49aa-840a-c3b869d9d094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523237282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2523237282
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.104981649
Short name T255
Test name
Test status
Simulation time 3164986938370 ps
CPU time 804.98 seconds
Started Dec 24 12:39:36 PM PST 23
Finished Dec 24 12:53:05 PM PST 23
Peak memory 191048 kb
Host smart-9b29cee9-f438-4a4f-8203-432946dd3a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104981649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.104981649
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3876083140
Short name T157
Test name
Test status
Simulation time 418563145257 ps
CPU time 432.19 seconds
Started Dec 24 12:38:05 PM PST 23
Finished Dec 24 12:45:17 PM PST 23
Peak memory 191144 kb
Host smart-1cccabbc-97da-4e96-9770-3ea971beb0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876083140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3876083140
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3246227
Short name T150
Test name
Test status
Simulation time 120885182692 ps
CPU time 437.52 seconds
Started Dec 24 12:37:50 PM PST 23
Finished Dec 24 12:45:11 PM PST 23
Peak memory 191160 kb
Host smart-e7709795-618a-4b08-a510-04cae6161f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3246227
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1406810420
Short name T1
Test name
Test status
Simulation time 824748674008 ps
CPU time 325.43 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:45:06 PM PST 23
Peak memory 194032 kb
Host smart-ed5a10a3-2d2a-44dc-bda5-aacfbcf1caa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406810420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1406810420
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1692944494
Short name T199
Test name
Test status
Simulation time 713809123035 ps
CPU time 435.74 seconds
Started Dec 24 12:38:07 PM PST 23
Finished Dec 24 12:45:25 PM PST 23
Peak memory 182788 kb
Host smart-34583aba-1cfd-49d8-abed-0fa69c96fa94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692944494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1692944494
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random.3214468048
Short name T193
Test name
Test status
Simulation time 149467201778 ps
CPU time 264.02 seconds
Started Dec 24 12:37:48 PM PST 23
Finished Dec 24 12:42:16 PM PST 23
Peak memory 191172 kb
Host smart-bef480b1-e53e-4a67-af56-eff554467914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214468048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3214468048
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3357979513
Short name T379
Test name
Test status
Simulation time 565675300880 ps
CPU time 469.23 seconds
Started Dec 24 12:39:06 PM PST 23
Finished Dec 24 12:46:59 PM PST 23
Peak memory 193952 kb
Host smart-e88f316f-4ba1-49e6-8fff-94641a7649c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357979513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3357979513
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3598097016
Short name T268
Test name
Test status
Simulation time 481105239122 ps
CPU time 1535.23 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 01:03:48 PM PST 23
Peak memory 194056 kb
Host smart-e4ce9962-9805-4f0e-86c8-6d3b818cbbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598097016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3598097016
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2868754674
Short name T141
Test name
Test status
Simulation time 528675655168 ps
CPU time 1112.77 seconds
Started Dec 24 12:39:23 PM PST 23
Finished Dec 24 12:57:59 PM PST 23
Peak memory 191072 kb
Host smart-4c8361b9-64c0-4315-962f-49e1fe22afeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868754674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2868754674
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1713466713
Short name T257
Test name
Test status
Simulation time 160978068862 ps
CPU time 193.35 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:42:56 PM PST 23
Peak memory 191072 kb
Host smart-86e3f611-882c-4c02-ac68-2f21ccb5400e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713466713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1713466713
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2912093004
Short name T351
Test name
Test status
Simulation time 228166116407 ps
CPU time 727.89 seconds
Started Dec 24 12:39:46 PM PST 23
Finished Dec 24 12:51:56 PM PST 23
Peak memory 194244 kb
Host smart-7459e9ca-8ed2-4d34-aa27-a7e966faee3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912093004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2912093004
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1730292756
Short name T8
Test name
Test status
Simulation time 232368774073 ps
CPU time 516.5 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 12:46:55 PM PST 23
Peak memory 191056 kb
Host smart-c6d33ca1-9cb3-42a6-aa27-a3898b33921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730292756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1730292756
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_random.2486488979
Short name T161
Test name
Test status
Simulation time 45332237723 ps
CPU time 81.63 seconds
Started Dec 24 12:37:55 PM PST 23
Finished Dec 24 12:39:20 PM PST 23
Peak memory 191056 kb
Host smart-afc29b7c-3ab2-43ad-8432-6dc4f4e9ae12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486488979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2486488979
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2546354683
Short name T106
Test name
Test status
Simulation time 2775182057198 ps
CPU time 871.69 seconds
Started Dec 24 12:37:20 PM PST 23
Finished Dec 24 12:52:03 PM PST 23
Peak memory 191244 kb
Host smart-4cc3b5d3-7401-42b4-b004-75384dc52913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546354683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2546354683
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/138.rv_timer_random.524793336
Short name T320
Test name
Test status
Simulation time 595549289437 ps
CPU time 335.25 seconds
Started Dec 24 12:39:24 PM PST 23
Finished Dec 24 12:45:02 PM PST 23
Peak memory 190968 kb
Host smart-5bf91051-5fc8-4c04-bde9-dbec5cab24d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524793336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.524793336
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.569671996
Short name T162
Test name
Test status
Simulation time 958217865412 ps
CPU time 613.88 seconds
Started Dec 24 12:38:03 PM PST 23
Finished Dec 24 12:48:19 PM PST 23
Peak memory 182944 kb
Host smart-565cbd41-82b4-44b0-b0e5-3da350f6f577
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569671996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.569671996
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.693942057
Short name T274
Test name
Test status
Simulation time 70583865796 ps
CPU time 119.7 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:39:58 PM PST 23
Peak memory 191132 kb
Host smart-71d9f37c-5288-411e-a9ce-e5785d5fec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693942057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.693942057
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/177.rv_timer_random.406475146
Short name T214
Test name
Test status
Simulation time 385890338989 ps
CPU time 281.53 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:44:26 PM PST 23
Peak memory 194300 kb
Host smart-63c7f5c8-59a9-4a81-9d79-1300ad31cf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406475146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.406475146
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.764632065
Short name T159
Test name
Test status
Simulation time 293210054855 ps
CPU time 367.55 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:45:47 PM PST 23
Peak memory 193364 kb
Host smart-cc418252-1d18-420c-b374-476f93ec5b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764632065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.764632065
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3757386534
Short name T281
Test name
Test status
Simulation time 113125926460 ps
CPU time 193.63 seconds
Started Dec 24 12:38:13 PM PST 23
Finished Dec 24 12:41:30 PM PST 23
Peak memory 182936 kb
Host smart-428b4450-ade5-4448-b83b-cddb8405002a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757386534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3757386534
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3793789767
Short name T178
Test name
Test status
Simulation time 245891744541 ps
CPU time 175.39 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 12:42:00 PM PST 23
Peak memory 191064 kb
Host smart-aae89d69-1bb3-4df6-8a8f-8f3ca17a2ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793789767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3793789767
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2546030640
Short name T55
Test name
Test status
Simulation time 1377513586736 ps
CPU time 391.26 seconds
Started Dec 24 12:38:39 PM PST 23
Finished Dec 24 12:45:22 PM PST 23
Peak memory 182880 kb
Host smart-767ab315-7eb8-4ade-b00c-91446e320046
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546030640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2546030640
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.3907531683
Short name T346
Test name
Test status
Simulation time 551943623029 ps
CPU time 873.7 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:52:28 PM PST 23
Peak memory 191156 kb
Host smart-6d06628d-bc81-491d-b491-bb6637230d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907531683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3907531683
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3090484227
Short name T303
Test name
Test status
Simulation time 113091265144 ps
CPU time 271.96 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:43:37 PM PST 23
Peak memory 191140 kb
Host smart-c0d50148-d7ea-410e-88b1-e5ce7664b5a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090484227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3090484227
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3336660199
Short name T83
Test name
Test status
Simulation time 273492308289 ps
CPU time 274.97 seconds
Started Dec 24 12:39:02 PM PST 23
Finished Dec 24 12:43:42 PM PST 23
Peak memory 191112 kb
Host smart-d0101494-ff18-4c45-914e-fc15cd198999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336660199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3336660199
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.799289166
Short name T82
Test name
Test status
Simulation time 68903350 ps
CPU time 0.61 seconds
Started Dec 24 01:40:40 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 191796 kb
Host smart-84385f31-d3f6-4bf4-918c-feea432e8989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799289166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.799289166
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1290833664
Short name T42
Test name
Test status
Simulation time 135292328 ps
CPU time 0.58 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:51 PM PST 23
Peak memory 183308 kb
Host smart-7f4199e4-7ee6-4249-b960-76126b79b776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290833664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1290833664
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/118.rv_timer_random.2477971435
Short name T262
Test name
Test status
Simulation time 206002393227 ps
CPU time 800.95 seconds
Started Dec 24 12:39:02 PM PST 23
Finished Dec 24 12:52:28 PM PST 23
Peak memory 191000 kb
Host smart-8a999e3e-852c-4712-9539-dc202ab553f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477971435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2477971435
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.3733070209
Short name T314
Test name
Test status
Simulation time 270705607289 ps
CPU time 358.79 seconds
Started Dec 24 12:39:10 PM PST 23
Finished Dec 24 12:45:10 PM PST 23
Peak memory 191040 kb
Host smart-a12d4549-0598-44da-86fd-b8600f9bb589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733070209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3733070209
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1700584740
Short name T202
Test name
Test status
Simulation time 1645430466249 ps
CPU time 1183.12 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:57:40 PM PST 23
Peak memory 191240 kb
Host smart-ee3e9168-4d77-4424-8553-0a40a95b6964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700584740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1700584740
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_random.3255824924
Short name T124
Test name
Test status
Simulation time 105754690272 ps
CPU time 1157.59 seconds
Started Dec 24 12:37:53 PM PST 23
Finished Dec 24 12:57:14 PM PST 23
Peak memory 191124 kb
Host smart-a2c1dcfe-8436-40a4-ba99-921ea1112eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255824924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3255824924
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3287935794
Short name T264
Test name
Test status
Simulation time 8964714715181 ps
CPU time 2236.01 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 01:15:29 PM PST 23
Peak memory 182808 kb
Host smart-f4f5aafd-6ff6-481c-9313-a6b399ba5775
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287935794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3287935794
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.1160954455
Short name T127
Test name
Test status
Simulation time 282027245693 ps
CPU time 699.22 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:49:50 PM PST 23
Peak memory 191176 kb
Host smart-21cbb209-9c59-4d65-82bc-68b0f9abbe01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160954455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1160954455
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.752223055
Short name T19
Test name
Test status
Simulation time 133302780936 ps
CPU time 122.1 seconds
Started Dec 24 12:38:14 PM PST 23
Finished Dec 24 12:40:19 PM PST 23
Peak memory 191128 kb
Host smart-478364fa-7c8c-4342-ab5d-197de08da8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752223055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.752223055
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.2246979866
Short name T191
Test name
Test status
Simulation time 338675512191 ps
CPU time 490.73 seconds
Started Dec 24 12:38:26 PM PST 23
Finished Dec 24 12:46:39 PM PST 23
Peak memory 191176 kb
Host smart-ca6af3eb-b655-4aa1-841d-d776e8172baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246979866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2246979866
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.171465138
Short name T7
Test name
Test status
Simulation time 394950835989 ps
CPU time 172.47 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:41:58 PM PST 23
Peak memory 193872 kb
Host smart-93fecb4d-405f-4b4a-b922-e4c319cda925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171465138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.171465138
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3251672791
Short name T215
Test name
Test status
Simulation time 373625020093 ps
CPU time 660.64 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 12:50:05 PM PST 23
Peak memory 191136 kb
Host smart-08cafc0e-4e63-4663-9e2f-6ec66255a89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251672791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3251672791
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3943479987
Short name T293
Test name
Test status
Simulation time 1509716938587 ps
CPU time 1069.4 seconds
Started Dec 24 12:37:52 PM PST 23
Finished Dec 24 12:55:44 PM PST 23
Peak memory 182820 kb
Host smart-8d5e4de2-720a-4ac4-87b3-47cc9e6b4c26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943479987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3943479987
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.627195250
Short name T439
Test name
Test status
Simulation time 438920902 ps
CPU time 1.4 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:51 PM PST 23
Peak memory 195596 kb
Host smart-88bb1d35-e7a9-4cf1-adaf-2b01d8ea5feb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627195250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.627195250
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.1794615888
Short name T232
Test name
Test status
Simulation time 1257417617599 ps
CPU time 1574.17 seconds
Started Dec 24 12:37:21 PM PST 23
Finished Dec 24 01:03:47 PM PST 23
Peak memory 207416 kb
Host smart-0c1a1684-1e38-420a-889b-cbfb252826de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794615888 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.1794615888
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2173530566
Short name T356
Test name
Test status
Simulation time 6566743518 ps
CPU time 26.03 seconds
Started Dec 24 12:37:58 PM PST 23
Finished Dec 24 12:38:28 PM PST 23
Peak memory 182936 kb
Host smart-a9622758-1e9f-42a3-8b35-9acd5e275a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173530566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2173530566
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/105.rv_timer_random.3384420742
Short name T151
Test name
Test status
Simulation time 109832463329 ps
CPU time 40.41 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:39:47 PM PST 23
Peak memory 182936 kb
Host smart-b68c9ce1-d205-4eca-adc1-8efc371456fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384420742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3384420742
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.679985156
Short name T156
Test name
Test status
Simulation time 328031756714 ps
CPU time 1981.84 seconds
Started Dec 24 12:37:36 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 213524 kb
Host smart-b213acf7-5495-495b-b912-bf0478edcbb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679985156 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.679985156
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.rv_timer_random.621029628
Short name T102
Test name
Test status
Simulation time 47189629720 ps
CPU time 117.68 seconds
Started Dec 24 12:39:10 PM PST 23
Finished Dec 24 12:41:09 PM PST 23
Peak memory 191040 kb
Host smart-d039262a-2a42-4ae1-966e-3f5fe1b21703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621029628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.621029628
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1064523550
Short name T330
Test name
Test status
Simulation time 257921627218 ps
CPU time 838.36 seconds
Started Dec 24 12:39:03 PM PST 23
Finished Dec 24 12:53:07 PM PST 23
Peak memory 191052 kb
Host smart-f7be404e-5898-477f-a356-5df833859311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064523550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1064523550
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2023646871
Short name T181
Test name
Test status
Simulation time 44718169979 ps
CPU time 162.93 seconds
Started Dec 24 12:37:52 PM PST 23
Finished Dec 24 12:40:38 PM PST 23
Peak memory 191020 kb
Host smart-0940c191-38ee-448d-ae07-6e8e273de881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023646871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2023646871
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/127.rv_timer_random.3237939644
Short name T339
Test name
Test status
Simulation time 142088147120 ps
CPU time 79.98 seconds
Started Dec 24 12:39:10 PM PST 23
Finished Dec 24 12:40:31 PM PST 23
Peak memory 182840 kb
Host smart-974830ef-43a7-4e85-b25e-0ba6de008101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237939644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3237939644
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.4242631777
Short name T245
Test name
Test status
Simulation time 65493746530 ps
CPU time 606.56 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:48:01 PM PST 23
Peak memory 205728 kb
Host smart-b2fa6081-0baf-4139-ae40-293d0a2d82a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242631777 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.4242631777
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3357866270
Short name T376
Test name
Test status
Simulation time 53918045327 ps
CPU time 438.37 seconds
Started Dec 24 12:38:07 PM PST 23
Finished Dec 24 12:45:29 PM PST 23
Peak memory 182808 kb
Host smart-cd4cec51-6b58-4df1-8215-263b6cbb36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357866270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3357866270
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.611435868
Short name T36
Test name
Test status
Simulation time 109875790160 ps
CPU time 222.75 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:43:25 PM PST 23
Peak memory 191172 kb
Host smart-79ee2fbd-3871-4780-a908-05dd8c04176e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611435868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.611435868
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3049222733
Short name T604
Test name
Test status
Simulation time 76107910021 ps
CPU time 36.67 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:40:17 PM PST 23
Peak memory 191004 kb
Host smart-5205aaf9-112c-4667-9802-a174ec86c4e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049222733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3049222733
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3874735138
Short name T56
Test name
Test status
Simulation time 10737040586 ps
CPU time 19.34 seconds
Started Dec 24 12:39:36 PM PST 23
Finished Dec 24 12:39:59 PM PST 23
Peak memory 182872 kb
Host smart-168660e2-26ce-4663-a7da-4a4fb07d31b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874735138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3874735138
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2667682653
Short name T310
Test name
Test status
Simulation time 243528113253 ps
CPU time 463.05 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:47:25 PM PST 23
Peak memory 191032 kb
Host smart-b2a1d23a-0a1a-4cbe-bc93-9d65143d0238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667682653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2667682653
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.565225437
Short name T311
Test name
Test status
Simulation time 525783267493 ps
CPU time 645.95 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:50:29 PM PST 23
Peak memory 191012 kb
Host smart-fb66b407-a118-4af0-ae43-a4ae6f62c53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565225437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.565225437
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1167884380
Short name T597
Test name
Test status
Simulation time 1496390807324 ps
CPU time 252.86 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:43:53 PM PST 23
Peak memory 191072 kb
Host smart-7143a6f2-f1a1-4911-a573-3b937b578ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167884380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1167884380
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2726113830
Short name T211
Test name
Test status
Simulation time 86795876763 ps
CPU time 114.35 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:40:09 PM PST 23
Peak memory 191172 kb
Host smart-d809c394-5a4d-49ba-b775-81d7e079a969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726113830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2726113830
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1414086584
Short name T240
Test name
Test status
Simulation time 258409122233 ps
CPU time 292.22 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:44:37 PM PST 23
Peak memory 191028 kb
Host smart-6931b18c-84ac-406f-8ad9-00bf0065654f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414086584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1414086584
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2054575129
Short name T344
Test name
Test status
Simulation time 67317023216 ps
CPU time 115.73 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:41:41 PM PST 23
Peak memory 191140 kb
Host smart-05b84fa4-9b61-4c6d-9a97-654d4d45afad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054575129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2054575129
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1580050494
Short name T374
Test name
Test status
Simulation time 650519204653 ps
CPU time 283.56 seconds
Started Dec 24 12:39:44 PM PST 23
Finished Dec 24 12:44:30 PM PST 23
Peak memory 191076 kb
Host smart-4a27415a-ce3d-4226-ac2f-c46377874eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580050494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1580050494
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4131352580
Short name T195
Test name
Test status
Simulation time 721461563606 ps
CPU time 1082.64 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 191140 kb
Host smart-c14215a4-66ab-4d42-a31d-891d65064972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131352580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4131352580
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_random.2158269463
Short name T207
Test name
Test status
Simulation time 377024200695 ps
CPU time 214.04 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:42:02 PM PST 23
Peak memory 191132 kb
Host smart-a4734a82-9359-44fe-83e5-cc52c2cd1974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158269463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2158269463
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1567978289
Short name T169
Test name
Test status
Simulation time 1794914434243 ps
CPU time 1258.76 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 12:59:17 PM PST 23
Peak memory 191132 kb
Host smart-54c955cb-dc17-4ffc-8c33-e37d9fcc3433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567978289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1567978289
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random.2776446087
Short name T325
Test name
Test status
Simulation time 176751974268 ps
CPU time 83.26 seconds
Started Dec 24 12:38:23 PM PST 23
Finished Dec 24 12:39:47 PM PST 23
Peak memory 191044 kb
Host smart-30fca7f7-fdff-43a7-80ca-82236beff208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776446087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2776446087
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.132497459
Short name T197
Test name
Test status
Simulation time 569461885527 ps
CPU time 252.64 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:42:10 PM PST 23
Peak memory 191128 kb
Host smart-edef4df9-f93c-4083-aa41-12eb18a104cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132497459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.132497459
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1266030084
Short name T31
Test name
Test status
Simulation time 259306500349 ps
CPU time 1621.21 seconds
Started Dec 24 12:37:44 PM PST 23
Finished Dec 24 01:04:49 PM PST 23
Peak memory 214056 kb
Host smart-d83f6023-b61d-452e-ae09-b09b01c2ea9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266030084 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1266030084
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.497586535
Short name T192
Test name
Test status
Simulation time 231286713698 ps
CPU time 344.95 seconds
Started Dec 24 12:38:24 PM PST 23
Finished Dec 24 12:44:11 PM PST 23
Peak memory 195048 kb
Host smart-e1ce069f-d55f-4429-861b-59b7754ad79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497586535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
497586535
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.741547154
Short name T305
Test name
Test status
Simulation time 487161351368 ps
CPU time 209.56 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 12:42:02 PM PST 23
Peak memory 182924 kb
Host smart-be9c363a-578a-4de2-b643-a11109bfb389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741547154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.741547154
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.776363125
Short name T166
Test name
Test status
Simulation time 1118572190247 ps
CPU time 903.59 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:54:09 PM PST 23
Peak memory 191188 kb
Host smart-214039e1-11c6-4dae-85ce-231b3d905824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776363125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.776363125
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.905929286
Short name T239
Test name
Test status
Simulation time 104071512367 ps
CPU time 368.28 seconds
Started Dec 24 12:38:59 PM PST 23
Finished Dec 24 12:45:15 PM PST 23
Peak memory 194240 kb
Host smart-f352a96d-d932-4e54-b679-d6373bad0d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905929286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.905929286
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2910445269
Short name T69
Test name
Test status
Simulation time 13426960 ps
CPU time 0.62 seconds
Started Dec 24 01:40:43 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 192528 kb
Host smart-fb70a40a-8fca-4120-b381-c279c3d7dbc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910445269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2910445269
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2713657940
Short name T475
Test name
Test status
Simulation time 191180700 ps
CPU time 2.56 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 183584 kb
Host smart-4daabbb5-8bef-47ba-b337-94466c40ec7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713657940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2713657940
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3083818810
Short name T407
Test name
Test status
Simulation time 47786487 ps
CPU time 0.54 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 183228 kb
Host smart-42ed369d-96c3-40e4-a502-3a7cb045ff43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083818810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3083818810
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2310196615
Short name T395
Test name
Test status
Simulation time 157828503 ps
CPU time 0.83 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 196540 kb
Host smart-9719630a-60ab-4883-8627-cd4fbb769664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310196615 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2310196615
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3376548780
Short name T71
Test name
Test status
Simulation time 14900820 ps
CPU time 0.61 seconds
Started Dec 24 01:40:43 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 183292 kb
Host smart-61556c18-27e8-4791-87c3-5446bada2c0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376548780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3376548780
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3938094128
Short name T392
Test name
Test status
Simulation time 33868752 ps
CPU time 0.57 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 182876 kb
Host smart-c9bb285e-341c-4f34-9a20-d11be96c4d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938094128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3938094128
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2681677066
Short name T462
Test name
Test status
Simulation time 115943356 ps
CPU time 0.81 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 193840 kb
Host smart-e9eb85fc-f68d-4b32-b1ca-b3762464438f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681677066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2681677066
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2217265437
Short name T484
Test name
Test status
Simulation time 226817407 ps
CPU time 2.38 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 198068 kb
Host smart-d87cea3a-006e-4a99-93d2-596ec36bedc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217265437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2217265437
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3263068414
Short name T26
Test name
Test status
Simulation time 47103998 ps
CPU time 0.83 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 193912 kb
Host smart-33026151-69e9-473f-96bd-de9e9806d00b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263068414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3263068414
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1991589163
Short name T393
Test name
Test status
Simulation time 29439019 ps
CPU time 0.74 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 183236 kb
Host smart-60ec074e-88b7-4d19-92d9-62b6387d9f15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991589163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1991589163
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4018939544
Short name T61
Test name
Test status
Simulation time 63528510 ps
CPU time 2.46 seconds
Started Dec 24 01:40:37 PM PST 23
Finished Dec 24 01:40:41 PM PST 23
Peak memory 192928 kb
Host smart-079580dc-3f75-4420-ac44-6bf3415abbf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018939544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4018939544
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.926346208
Short name T59
Test name
Test status
Simulation time 253605622 ps
CPU time 0.56 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 183312 kb
Host smart-8c0fafb8-548b-4eef-a184-1a427682b47c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926346208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.926346208
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.658155259
Short name T418
Test name
Test status
Simulation time 98672704 ps
CPU time 1.26 seconds
Started Dec 24 01:40:42 PM PST 23
Finished Dec 24 01:40:48 PM PST 23
Peak memory 198104 kb
Host smart-f0ef2d1f-b15a-4544-9ef3-c613d4127e7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658155259 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.658155259
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1598019598
Short name T448
Test name
Test status
Simulation time 18336521 ps
CPU time 0.57 seconds
Started Dec 24 01:40:37 PM PST 23
Finished Dec 24 01:40:40 PM PST 23
Peak memory 183232 kb
Host smart-9cf46923-ea38-4730-97f0-3baf7c30959f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598019598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1598019598
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.539533928
Short name T48
Test name
Test status
Simulation time 42766740 ps
CPU time 0.52 seconds
Started Dec 24 01:40:37 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 182540 kb
Host smart-ae6ba2bb-e24b-42c4-b588-418bda8c0d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539533928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.539533928
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3775855295
Short name T464
Test name
Test status
Simulation time 63294695 ps
CPU time 1.73 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:42 PM PST 23
Peak memory 197828 kb
Host smart-ba8d840c-e058-4a20-8743-5db5c562495f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775855295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3775855295
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3176776291
Short name T384
Test name
Test status
Simulation time 119546148 ps
CPU time 0.91 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 197896 kb
Host smart-927f528a-c842-4d6c-b53f-3221922515ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176776291 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3176776291
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1569861737
Short name T489
Test name
Test status
Simulation time 20806092 ps
CPU time 0.56 seconds
Started Dec 24 01:41:24 PM PST 23
Finished Dec 24 01:41:26 PM PST 23
Peak memory 183308 kb
Host smart-3336585b-f717-4010-9b24-bcefb1c209ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569861737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1569861737
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4024668760
Short name T451
Test name
Test status
Simulation time 11241614 ps
CPU time 0.56 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:31 PM PST 23
Peak memory 182124 kb
Host smart-9cf3f722-8e34-42a8-b5ac-4c941fa9f4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024668760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4024668760
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.772904798
Short name T15
Test name
Test status
Simulation time 16983939 ps
CPU time 0.72 seconds
Started Dec 24 01:41:24 PM PST 23
Finished Dec 24 01:41:26 PM PST 23
Peak memory 193248 kb
Host smart-683a4dbc-bb95-4972-bdb1-b41067f668c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772904798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.772904798
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1970339086
Short name T434
Test name
Test status
Simulation time 26929777 ps
CPU time 1.16 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 198116 kb
Host smart-121e33ff-158b-4b99-9dec-c09bbd04e3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970339086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1970339086
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3010345477
Short name T490
Test name
Test status
Simulation time 156541075 ps
CPU time 1.29 seconds
Started Dec 24 01:41:26 PM PST 23
Finished Dec 24 01:41:29 PM PST 23
Peak memory 195600 kb
Host smart-017ea92c-74f2-4000-b3f4-5f73584bb0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010345477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3010345477
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.819607969
Short name T40
Test name
Test status
Simulation time 92951529 ps
CPU time 0.65 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 193672 kb
Host smart-0b2e3bd9-9958-437d-91ee-334225e7527b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819607969 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.819607969
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1433075571
Short name T424
Test name
Test status
Simulation time 44661957 ps
CPU time 0.54 seconds
Started Dec 24 01:41:35 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 182724 kb
Host smart-8d047af5-9660-4149-831e-e0033a8da224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433075571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1433075571
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3737437269
Short name T456
Test name
Test status
Simulation time 16180764 ps
CPU time 0.62 seconds
Started Dec 24 01:40:56 PM PST 23
Finished Dec 24 01:40:58 PM PST 23
Peak memory 183012 kb
Host smart-6876036f-a413-4876-b25a-3746cde1bcc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737437269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3737437269
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3647725780
Short name T413
Test name
Test status
Simulation time 41375520 ps
CPU time 0.81 seconds
Started Dec 24 01:41:28 PM PST 23
Finished Dec 24 01:41:30 PM PST 23
Peak memory 193708 kb
Host smart-d6bb7d9c-7e29-435c-8fe5-e0f997f6915d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647725780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3647725780
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.647454821
Short name T47
Test name
Test status
Simulation time 111874736 ps
CPU time 1.6 seconds
Started Dec 24 01:41:31 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 198084 kb
Host smart-d7144bd1-d31d-45fb-87a5-556bf60ca35d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647454821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.647454821
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1307121747
Short name T458
Test name
Test status
Simulation time 16161717 ps
CPU time 0.92 seconds
Started Dec 24 01:42:07 PM PST 23
Finished Dec 24 01:42:09 PM PST 23
Peak memory 196088 kb
Host smart-29a066f0-623a-4a05-a97f-870c10d6ff5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307121747 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1307121747
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3263720635
Short name T409
Test name
Test status
Simulation time 47790518 ps
CPU time 0.62 seconds
Started Dec 24 01:41:23 PM PST 23
Finished Dec 24 01:41:25 PM PST 23
Peak memory 183176 kb
Host smart-0f75fd7c-3697-4034-9b5e-d83e97561c91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263720635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3263720635
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1826315012
Short name T383
Test name
Test status
Simulation time 25219151 ps
CPU time 0.59 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:58 PM PST 23
Peak memory 182960 kb
Host smart-77075eac-c005-4a6a-916f-a230b596b7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826315012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1826315012
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3741800534
Short name T46
Test name
Test status
Simulation time 52049701 ps
CPU time 0.78 seconds
Started Dec 24 01:41:25 PM PST 23
Finished Dec 24 01:41:27 PM PST 23
Peak memory 193588 kb
Host smart-ce4b91a5-cd90-4c78-9479-e47f8fa8d420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741800534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3741800534
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.783985870
Short name T463
Test name
Test status
Simulation time 138550626 ps
CPU time 2.96 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:34 PM PST 23
Peak memory 197080 kb
Host smart-e62adcdd-0382-400a-ba78-c1932ca87673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783985870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.783985870
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1745324794
Short name T412
Test name
Test status
Simulation time 294825784 ps
CPU time 1.11 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 195196 kb
Host smart-b5064e59-8b22-4958-b061-d03d69d95f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745324794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1745324794
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3726568354
Short name T482
Test name
Test status
Simulation time 71291966 ps
CPU time 0.71 seconds
Started Dec 24 01:41:26 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 191572 kb
Host smart-b65678e3-4ecd-4c67-8729-900243043569
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726568354 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3726568354
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3111465356
Short name T396
Test name
Test status
Simulation time 14406454 ps
CPU time 0.59 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 182420 kb
Host smart-b3cc23f2-4b91-419f-9bd6-7d46da8243f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111465356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3111465356
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2756701130
Short name T51
Test name
Test status
Simulation time 54850144 ps
CPU time 0.53 seconds
Started Dec 24 01:41:25 PM PST 23
Finished Dec 24 01:41:27 PM PST 23
Peak memory 182736 kb
Host smart-07e0a83a-e66d-477d-b0a4-c603c637d177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756701130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2756701130
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1358468350
Short name T38
Test name
Test status
Simulation time 45210712 ps
CPU time 0.81 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 192400 kb
Host smart-99bce304-8bc6-4865-b698-53f41764189a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358468350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1358468350
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1858690080
Short name T398
Test name
Test status
Simulation time 507524873 ps
CPU time 2.09 seconds
Started Dec 24 01:42:07 PM PST 23
Finished Dec 24 01:42:10 PM PST 23
Peak memory 196260 kb
Host smart-b8dd5931-fe59-44b1-834a-8b12152618cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858690080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1858690080
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3193952804
Short name T483
Test name
Test status
Simulation time 219556931 ps
CPU time 1.48 seconds
Started Dec 24 01:41:25 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 195724 kb
Host smart-d29a3be8-3f7f-4658-8b2e-6186f7bb7765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193952804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3193952804
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4273525196
Short name T449
Test name
Test status
Simulation time 29590346 ps
CPU time 0.94 seconds
Started Dec 24 01:41:33 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 196404 kb
Host smart-dafe9825-d08e-4930-9086-f9f0f72db339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273525196 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4273525196
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.400473661
Short name T428
Test name
Test status
Simulation time 43650399 ps
CPU time 0.55 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 183368 kb
Host smart-3e7b7ad9-a6c6-41b7-a88e-2ff99e408ccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400473661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.400473661
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.376697584
Short name T467
Test name
Test status
Simulation time 120087780 ps
CPU time 0.55 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 182996 kb
Host smart-1564d90d-eff3-4e28-a794-afc141466b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376697584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.376697584
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.314483746
Short name T29
Test name
Test status
Simulation time 15520536 ps
CPU time 0.7 seconds
Started Dec 24 01:41:35 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 193004 kb
Host smart-2c192761-558a-4dc2-b140-1072a17b1819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314483746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.314483746
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2852831472
Short name T420
Test name
Test status
Simulation time 50369121 ps
CPU time 0.81 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 195964 kb
Host smart-d409ee06-884c-4c8d-b5d3-640ef0072ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852831472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2852831472
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2176345596
Short name T472
Test name
Test status
Simulation time 512113579 ps
CPU time 1.44 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 195888 kb
Host smart-c225b757-fb37-43b7-a3ca-d51205df1f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176345596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2176345596
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.465196341
Short name T394
Test name
Test status
Simulation time 62025052 ps
CPU time 0.77 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 196848 kb
Host smart-47c165fc-111b-4acc-a98f-81416ef2520c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465196341 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.465196341
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1581653070
Short name T389
Test name
Test status
Simulation time 15840887 ps
CPU time 0.57 seconds
Started Dec 24 01:41:33 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 182980 kb
Host smart-fc9c5eb4-c4c2-4ef0-8234-82c8a57ddf6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581653070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1581653070
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.221292661
Short name T440
Test name
Test status
Simulation time 20538588 ps
CPU time 0.8 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:31 PM PST 23
Peak memory 193860 kb
Host smart-60d48e7f-e48a-4be2-a62c-9efeda2d7e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221292661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.221292661
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.676179551
Short name T492
Test name
Test status
Simulation time 47599715 ps
CPU time 1.04 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 197608 kb
Host smart-dbff7245-a28d-4ab9-9efa-72b34179e773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676179551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.676179551
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2002476542
Short name T95
Test name
Test status
Simulation time 1731088307 ps
CPU time 1.42 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 183776 kb
Host smart-dce164f3-f86f-4c5f-b1c9-5a75dccc8fee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002476542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2002476542
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.41225079
Short name T35
Test name
Test status
Simulation time 23793447 ps
CPU time 0.78 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 196340 kb
Host smart-c76a3b08-e70b-4340-9492-7467a7ddfc80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41225079 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.41225079
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1567054758
Short name T455
Test name
Test status
Simulation time 28681626 ps
CPU time 0.52 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 182812 kb
Host smart-dfa2f19e-67c2-4c6e-bb76-2c8aa6d67d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567054758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1567054758
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1415673995
Short name T400
Test name
Test status
Simulation time 14169715 ps
CPU time 0.6 seconds
Started Dec 24 01:41:26 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 182512 kb
Host smart-1a02d530-4f8c-4487-8eee-c54a1fd54e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415673995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1415673995
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3636252610
Short name T486
Test name
Test status
Simulation time 21375101 ps
CPU time 0.81 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 192268 kb
Host smart-7905f48c-7ea7-46b2-96a8-4ef08beb9481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636252610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3636252610
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.586365704
Short name T493
Test name
Test status
Simulation time 100069351 ps
CPU time 2.12 seconds
Started Dec 24 01:41:28 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 198000 kb
Host smart-0713be9d-7404-4287-8c7f-71c8c144a862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586365704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.586365704
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3178059184
Short name T387
Test name
Test status
Simulation time 164873946 ps
CPU time 0.81 seconds
Started Dec 24 01:41:26 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 193716 kb
Host smart-1df47fc0-f678-41e4-a7ec-ea72b4d5c7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178059184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3178059184
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1602704922
Short name T34
Test name
Test status
Simulation time 26178400 ps
CPU time 1.22 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 197556 kb
Host smart-184fe357-a851-467d-8609-0420da20f32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602704922 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1602704922
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1966200271
Short name T386
Test name
Test status
Simulation time 37980310 ps
CPU time 0.52 seconds
Started Dec 24 01:41:28 PM PST 23
Finished Dec 24 01:41:30 PM PST 23
Peak memory 183256 kb
Host smart-d9bec742-2007-4684-9c78-cf836c154c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966200271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1966200271
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3488547569
Short name T471
Test name
Test status
Simulation time 55182197 ps
CPU time 0.56 seconds
Started Dec 24 01:41:25 PM PST 23
Finished Dec 24 01:41:27 PM PST 23
Peak memory 182956 kb
Host smart-b5c777ab-dc19-4689-a27a-68cd7bac48a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488547569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3488547569
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2310926710
Short name T487
Test name
Test status
Simulation time 63463871 ps
CPU time 0.71 seconds
Started Dec 24 01:41:33 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 193472 kb
Host smart-1104c39a-a95b-4f68-82ed-5dfcc591b42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310926710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2310926710
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.921399099
Short name T401
Test name
Test status
Simulation time 203909947 ps
CPU time 2.43 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:38 PM PST 23
Peak memory 198168 kb
Host smart-f6542cd3-4970-485b-a655-550085011a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921399099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.921399099
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.821074154
Short name T457
Test name
Test status
Simulation time 82238923 ps
CPU time 0.86 seconds
Started Dec 24 01:41:26 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 183692 kb
Host smart-e0fb3184-9e03-4c1d-8b78-25f6bacc8d88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821074154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.821074154
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1748159380
Short name T447
Test name
Test status
Simulation time 85677995 ps
CPU time 0.67 seconds
Started Dec 24 01:41:31 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 194932 kb
Host smart-3e2367b5-6425-4d1c-a027-adceadbb6126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748159380 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1748159380
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2803210227
Short name T399
Test name
Test status
Simulation time 40882958 ps
CPU time 0.55 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 183280 kb
Host smart-1bd74ab0-a479-465c-857a-effbbe8392bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803210227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2803210227
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2179933715
Short name T433
Test name
Test status
Simulation time 15241702 ps
CPU time 0.56 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:51 PM PST 23
Peak memory 182876 kb
Host smart-4b934691-ab28-4ef3-b830-5e6d50434be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179933715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2179933715
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2031567782
Short name T80
Test name
Test status
Simulation time 37233847 ps
CPU time 0.77 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:53 PM PST 23
Peak memory 193572 kb
Host smart-0803f50d-7395-481e-adb9-25d19653420b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031567782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2031567782
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1689691552
Short name T444
Test name
Test status
Simulation time 34291570 ps
CPU time 1.64 seconds
Started Dec 24 01:41:35 PM PST 23
Finished Dec 24 01:41:38 PM PST 23
Peak memory 197964 kb
Host smart-ef0083b5-3891-413c-aab2-f4ff23f857ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689691552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1689691552
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2860581633
Short name T92
Test name
Test status
Simulation time 174170763 ps
CPU time 0.8 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 193756 kb
Host smart-34ae8533-8f8f-4e16-9969-130a00301eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860581633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2860581633
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3392763222
Short name T422
Test name
Test status
Simulation time 32804768 ps
CPU time 1.74 seconds
Started Dec 24 01:41:48 PM PST 23
Finished Dec 24 01:41:51 PM PST 23
Peak memory 198060 kb
Host smart-5752441f-7963-40f1-8c92-d09e9e838a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392763222 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3392763222
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4169796917
Short name T67
Test name
Test status
Simulation time 14151184 ps
CPU time 0.54 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 183288 kb
Host smart-58b9fc27-14cf-4068-9c6b-7c804815935d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169796917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4169796917
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3730940306
Short name T480
Test name
Test status
Simulation time 16462186 ps
CPU time 0.56 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 182900 kb
Host smart-89a56712-d486-4570-8bec-07d2abaf190b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730940306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3730940306
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3332081006
Short name T443
Test name
Test status
Simulation time 62920641 ps
CPU time 0.81 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:33 PM PST 23
Peak memory 193876 kb
Host smart-89548665-a410-4451-87d3-a7e8901530e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332081006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3332081006
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1091592325
Short name T33
Test name
Test status
Simulation time 100020264 ps
CPU time 2.05 seconds
Started Dec 24 01:41:25 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 197956 kb
Host smart-69aacb4f-36a9-4977-beb6-7e9792b73815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091592325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1091592325
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1013795049
Short name T465
Test name
Test status
Simulation time 100439709 ps
CPU time 0.83 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:36 PM PST 23
Peak memory 193764 kb
Host smart-283de77e-50fe-493f-b54b-092645f64433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013795049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1013795049
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3300751240
Short name T58
Test name
Test status
Simulation time 17138108 ps
CPU time 0.72 seconds
Started Dec 24 01:40:47 PM PST 23
Finished Dec 24 01:40:52 PM PST 23
Peak memory 183100 kb
Host smart-902c398a-d697-4284-8149-01f16085913c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300751240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3300751240
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3737322575
Short name T385
Test name
Test status
Simulation time 747379054 ps
CPU time 2.66 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 191680 kb
Host smart-afdda6bf-41e3-47ac-bade-e56b5886e361
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737322575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3737322575
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3391436122
Short name T68
Test name
Test status
Simulation time 57368324 ps
CPU time 0.56 seconds
Started Dec 24 01:40:47 PM PST 23
Finished Dec 24 01:40:52 PM PST 23
Peak memory 183100 kb
Host smart-fd6b1b00-af3e-4c3d-ae89-de00f772a66e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391436122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3391436122
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1625521228
Short name T397
Test name
Test status
Simulation time 31370404 ps
CPU time 1.49 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:42 PM PST 23
Peak memory 198164 kb
Host smart-8c758eb5-8e31-46de-9de9-d2fce20d7af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625521228 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1625521228
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2165452130
Short name T70
Test name
Test status
Simulation time 42169801 ps
CPU time 0.57 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 183192 kb
Host smart-7022ce33-345d-422d-acd8-c53f0999b497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165452130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2165452130
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2279564574
Short name T403
Test name
Test status
Simulation time 10902261 ps
CPU time 0.51 seconds
Started Dec 24 01:40:46 PM PST 23
Finished Dec 24 01:40:51 PM PST 23
Peak memory 182336 kb
Host smart-e2df59bf-07af-4b43-a2e9-769d1e7405d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279564574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2279564574
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1353018552
Short name T415
Test name
Test status
Simulation time 74790962 ps
CPU time 0.59 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:42 PM PST 23
Peak memory 191556 kb
Host smart-b60399f5-560b-46a2-8d5c-a2c7d7d329bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353018552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1353018552
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1653541420
Short name T441
Test name
Test status
Simulation time 38155420 ps
CPU time 1.12 seconds
Started Dec 24 01:40:40 PM PST 23
Finished Dec 24 01:40:46 PM PST 23
Peak memory 197884 kb
Host smart-42f8e4c7-68f6-480e-88b5-17c73e344386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653541420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1653541420
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2922222087
Short name T93
Test name
Test status
Simulation time 99053068 ps
CPU time 1.34 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 195632 kb
Host smart-71dd4fae-65a1-430d-ae94-4e275c4de9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922222087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2922222087
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2184366788
Short name T414
Test name
Test status
Simulation time 49576437 ps
CPU time 0.53 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:58 PM PST 23
Peak memory 182084 kb
Host smart-5583dbc7-2853-481f-b85a-2c99430d4f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184366788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2184366788
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3832414225
Short name T481
Test name
Test status
Simulation time 11519752 ps
CPU time 0.57 seconds
Started Dec 24 01:42:18 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 182968 kb
Host smart-83bb9ed2-8c1f-43ea-a41c-1e8d9f035bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832414225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3832414225
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2751903348
Short name T391
Test name
Test status
Simulation time 44251852 ps
CPU time 0.54 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:17 PM PST 23
Peak memory 182528 kb
Host smart-5f2fc015-9e8f-41ca-b8fe-5327b17ba7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751903348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2751903348
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3856764292
Short name T390
Test name
Test status
Simulation time 45809648 ps
CPU time 0.53 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 182944 kb
Host smart-ff1ff7fc-04d7-4ca7-bccf-2fcdc53d1df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856764292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3856764292
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1189520539
Short name T437
Test name
Test status
Simulation time 54155941 ps
CPU time 0.55 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 182108 kb
Host smart-dc3508f4-5089-40f3-a998-fabb5b6be00f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189520539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1189520539
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4236102560
Short name T421
Test name
Test status
Simulation time 14193628 ps
CPU time 0.54 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 182172 kb
Host smart-aa8a640d-9681-455d-a14d-6881800dd717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236102560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4236102560
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4161397255
Short name T445
Test name
Test status
Simulation time 14394276 ps
CPU time 0.57 seconds
Started Dec 24 01:41:47 PM PST 23
Finished Dec 24 01:41:48 PM PST 23
Peak memory 182924 kb
Host smart-25c20446-defb-481d-b3f9-ce784242f7cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161397255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4161397255
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2833610601
Short name T459
Test name
Test status
Simulation time 17745313 ps
CPU time 0.52 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 182128 kb
Host smart-7bce8c99-2e7b-4474-889b-63fa473af795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833610601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2833610601
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2302720463
Short name T430
Test name
Test status
Simulation time 114058968 ps
CPU time 0.54 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:58 PM PST 23
Peak memory 182976 kb
Host smart-90f34422-cf13-4e5e-8bea-f6934360c785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302720463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2302720463
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.347624865
Short name T406
Test name
Test status
Simulation time 26171607 ps
CPU time 0.52 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 182696 kb
Host smart-c7dd2c92-8bde-452c-a1ba-afa09c18496e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347624865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.347624865
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2042986870
Short name T60
Test name
Test status
Simulation time 49002560 ps
CPU time 0.61 seconds
Started Dec 24 01:40:43 PM PST 23
Finished Dec 24 01:40:49 PM PST 23
Peak memory 183152 kb
Host smart-c306a1ab-514b-4a72-9e83-92ede4234313
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042986870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2042986870
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.791894929
Short name T408
Test name
Test status
Simulation time 197351005 ps
CPU time 1.53 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:44 PM PST 23
Peak memory 192424 kb
Host smart-24526b11-9459-4be2-84c9-e0e6a05d0161
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791894929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.791894929
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1690644473
Short name T76
Test name
Test status
Simulation time 64314280 ps
CPU time 0.55 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:58 PM PST 23
Peak memory 183244 kb
Host smart-725efe3b-b2f1-4c5e-b9e8-01052a2fda55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690644473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1690644473
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2310156281
Short name T426
Test name
Test status
Simulation time 83645101 ps
CPU time 0.76 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 193420 kb
Host smart-1c9ac4af-108a-40c3-913c-ff07d6f7e587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310156281 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2310156281
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3834351580
Short name T65
Test name
Test status
Simulation time 55772250 ps
CPU time 0.62 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 182996 kb
Host smart-404e36f2-648e-48ac-91db-90bf2ea1ffe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834351580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3834351580
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.153343138
Short name T432
Test name
Test status
Simulation time 64586856 ps
CPU time 0.56 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 182816 kb
Host smart-e3d9183b-fa49-4c73-9739-98c70c42eee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153343138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.153343138
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3650382808
Short name T81
Test name
Test status
Simulation time 18212571 ps
CPU time 0.78 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 193520 kb
Host smart-7fae209a-7b30-4fed-ba68-ac691e0d87a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650382808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3650382808
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2977754109
Short name T453
Test name
Test status
Simulation time 37008465 ps
CPU time 1.67 seconds
Started Dec 24 01:40:40 PM PST 23
Finished Dec 24 01:40:46 PM PST 23
Peak memory 197972 kb
Host smart-2ddf16a1-4979-4569-9487-4716eb1b6f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977754109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2977754109
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2971619488
Short name T410
Test name
Test status
Simulation time 614073629 ps
CPU time 0.78 seconds
Started Dec 24 01:40:46 PM PST 23
Finished Dec 24 01:40:51 PM PST 23
Peak memory 193616 kb
Host smart-e54f7f8a-eda3-4541-bd11-dc0eb88c7a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971619488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2971619488
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.4135479461
Short name T405
Test name
Test status
Simulation time 33892874 ps
CPU time 0.54 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 183036 kb
Host smart-7cd56d8e-5898-4c8d-9e5b-a3f04d77cf73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135479461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.4135479461
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2222653765
Short name T479
Test name
Test status
Simulation time 12784284 ps
CPU time 0.55 seconds
Started Dec 24 01:42:01 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 182140 kb
Host smart-7511c82a-42b3-43f9-945a-d12cee51e90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222653765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2222653765
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1535899328
Short name T45
Test name
Test status
Simulation time 14871939 ps
CPU time 0.6 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 182904 kb
Host smart-adc814be-651d-44da-8a5a-e8261a936f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535899328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1535899328
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1770921212
Short name T450
Test name
Test status
Simulation time 13869965 ps
CPU time 0.55 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 182944 kb
Host smart-39ed38ec-9d89-41d0-a40a-52a2757d5c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770921212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1770921212
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3725435102
Short name T388
Test name
Test status
Simulation time 53825306 ps
CPU time 0.53 seconds
Started Dec 24 01:42:01 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 182156 kb
Host smart-143b0a98-2357-42b0-a9f6-0d0d5130f7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725435102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3725435102
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3728525608
Short name T54
Test name
Test status
Simulation time 14283078 ps
CPU time 0.52 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:03 PM PST 23
Peak memory 182120 kb
Host smart-be00595e-80e3-462f-9d85-f0a1cf4f146d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728525608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3728525608
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2837050328
Short name T469
Test name
Test status
Simulation time 14398729 ps
CPU time 0.59 seconds
Started Dec 24 01:42:21 PM PST 23
Finished Dec 24 01:42:23 PM PST 23
Peak memory 182552 kb
Host smart-1a0de17c-3fce-4573-a6ba-7297a73c2eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837050328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2837050328
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.571295914
Short name T491
Test name
Test status
Simulation time 40618887 ps
CPU time 0.55 seconds
Started Dec 24 01:42:02 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 182592 kb
Host smart-826256d4-aff4-42ba-b447-3509e0dc7928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571295914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.571295914
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.985906403
Short name T427
Test name
Test status
Simulation time 58006122 ps
CPU time 0.52 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 182108 kb
Host smart-5e7477e2-924c-4614-951d-515a56b1d2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985906403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.985906403
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.482508630
Short name T73
Test name
Test status
Simulation time 75351540 ps
CPU time 0.56 seconds
Started Dec 24 01:42:02 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 182536 kb
Host smart-2b91ff89-9986-4882-8ade-5d95d1c47cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482508630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.482508630
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1758199580
Short name T75
Test name
Test status
Simulation time 120305319 ps
CPU time 0.84 seconds
Started Dec 24 01:41:11 PM PST 23
Finished Dec 24 01:41:13 PM PST 23
Peak memory 193020 kb
Host smart-3702bddc-142b-4d5d-ba27-5728859c7a95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758199580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1758199580
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3401081947
Short name T66
Test name
Test status
Simulation time 1699105997 ps
CPU time 3.6 seconds
Started Dec 24 01:40:56 PM PST 23
Finished Dec 24 01:41:01 PM PST 23
Peak memory 193000 kb
Host smart-07f3ab8c-6734-457a-b596-ada84e5b2be9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401081947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3401081947
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.462280973
Short name T64
Test name
Test status
Simulation time 74510747 ps
CPU time 0.6 seconds
Started Dec 24 01:41:28 PM PST 23
Finished Dec 24 01:41:30 PM PST 23
Peak memory 192520 kb
Host smart-eedd3eab-00ae-45a8-bfa6-d6a88e8080a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462280973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.462280973
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2777038608
Short name T436
Test name
Test status
Simulation time 19297346 ps
CPU time 0.68 seconds
Started Dec 24 01:41:31 PM PST 23
Finished Dec 24 01:41:33 PM PST 23
Peak memory 194692 kb
Host smart-ffbca3c0-bdcc-4aa8-b274-73337ba318f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777038608 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2777038608
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2947443446
Short name T423
Test name
Test status
Simulation time 49891951 ps
CPU time 0.6 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:58 PM PST 23
Peak memory 183308 kb
Host smart-33d0c257-1342-46e8-bac5-b3437a328d62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947443446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2947443446
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1518023084
Short name T404
Test name
Test status
Simulation time 13038751 ps
CPU time 0.51 seconds
Started Dec 24 01:41:31 PM PST 23
Finished Dec 24 01:41:33 PM PST 23
Peak memory 182124 kb
Host smart-67c02764-4253-4771-bf30-4b28657d227b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518023084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1518023084
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3193975023
Short name T477
Test name
Test status
Simulation time 128457443 ps
CPU time 0.83 seconds
Started Dec 24 01:41:11 PM PST 23
Finished Dec 24 01:41:13 PM PST 23
Peak memory 193724 kb
Host smart-7499b979-cc81-4ea7-b9ad-c2f5f88e0441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193975023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3193975023
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3810314888
Short name T466
Test name
Test status
Simulation time 51217218 ps
CPU time 1.46 seconds
Started Dec 24 01:40:57 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 198044 kb
Host smart-d9a7a116-a44c-4a90-9f53-5406414d44b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810314888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3810314888
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2886879787
Short name T468
Test name
Test status
Simulation time 429732169 ps
CPU time 1.36 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 195436 kb
Host smart-c9ee9d30-f1e5-4921-a33f-893bc1e67b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886879787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2886879787
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4061755512
Short name T416
Test name
Test status
Simulation time 17988415 ps
CPU time 0.56 seconds
Started Dec 24 01:42:01 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 182948 kb
Host smart-1df2cd49-ebe4-4e06-ba07-d55f2c4efc9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061755512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4061755512
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1411852524
Short name T417
Test name
Test status
Simulation time 19828670 ps
CPU time 0.53 seconds
Started Dec 24 01:41:35 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 181888 kb
Host smart-7e426e1a-5c77-41d5-a07f-d99041411ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411852524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1411852524
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.427368844
Short name T402
Test name
Test status
Simulation time 15685394 ps
CPU time 0.55 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:16 PM PST 23
Peak memory 182144 kb
Host smart-5ed91adf-7a58-44f3-a6dc-24b6f409152e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427368844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.427368844
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4033071202
Short name T485
Test name
Test status
Simulation time 61942592 ps
CPU time 0.56 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:19 PM PST 23
Peak memory 182016 kb
Host smart-edf1c904-59d6-478c-be91-7b9a659b6f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033071202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4033071202
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3981975811
Short name T53
Test name
Test status
Simulation time 14463173 ps
CPU time 0.55 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 182896 kb
Host smart-85650543-6b4e-4dfc-83d7-2d9e42e6358e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981975811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3981975811
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3392173035
Short name T72
Test name
Test status
Simulation time 13239477 ps
CPU time 0.53 seconds
Started Dec 24 01:41:24 PM PST 23
Finished Dec 24 01:41:25 PM PST 23
Peak memory 183088 kb
Host smart-a89966f8-b443-4cf4-b20e-5cdf10bc734e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392173035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3392173035
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.208637358
Short name T474
Test name
Test status
Simulation time 13117222 ps
CPU time 0.55 seconds
Started Dec 24 01:41:26 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 182964 kb
Host smart-8dd66b74-bc8c-4546-9c56-f848e0752280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208637358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.208637358
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4152096289
Short name T74
Test name
Test status
Simulation time 12120104 ps
CPU time 0.53 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 182084 kb
Host smart-3b4361e9-8e5d-4320-bacc-3edf335fcf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152096289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4152096289
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2968571636
Short name T478
Test name
Test status
Simulation time 14258063 ps
CPU time 0.55 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 182908 kb
Host smart-560dc998-1747-4e2f-bbe4-0b856a45b8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968571636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2968571636
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3457319570
Short name T460
Test name
Test status
Simulation time 18403635 ps
CPU time 0.61 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 182832 kb
Host smart-e47bf496-bc26-4f02-82cf-e259327c4ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457319570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3457319570
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2550812966
Short name T442
Test name
Test status
Simulation time 20567407 ps
CPU time 0.73 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 195684 kb
Host smart-76c72198-07c2-4adf-abc8-bb754d20a9c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550812966 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2550812966
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3140893619
Short name T63
Test name
Test status
Simulation time 53846041 ps
CPU time 0.57 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 183092 kb
Host smart-5862d1b9-e4df-488c-86af-c9b8105c599c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140893619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3140893619
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.216047066
Short name T470
Test name
Test status
Simulation time 35567348 ps
CPU time 0.54 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:57 PM PST 23
Peak memory 182832 kb
Host smart-d9c1f1fe-2096-4e3c-a920-d76c38a88b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216047066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.216047066
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1085565600
Short name T79
Test name
Test status
Simulation time 192015840 ps
CPU time 0.74 seconds
Started Dec 24 01:41:11 PM PST 23
Finished Dec 24 01:41:13 PM PST 23
Peak memory 193544 kb
Host smart-ad562bab-04c4-4657-b2fe-dc7037b99bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085565600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1085565600
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2401274406
Short name T488
Test name
Test status
Simulation time 43826947 ps
CPU time 2.18 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:33 PM PST 23
Peak memory 197852 kb
Host smart-e7ef4891-9bac-4fff-876e-b5edf48e1309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401274406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2401274406
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4276182951
Short name T419
Test name
Test status
Simulation time 160972547 ps
CPU time 1.09 seconds
Started Dec 24 01:41:33 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 183536 kb
Host smart-41822082-6cf1-4b59-a6b0-05d9122fc86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276182951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4276182951
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1718399768
Short name T57
Test name
Test status
Simulation time 65010474 ps
CPU time 0.92 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 197428 kb
Host smart-1b6970f5-029f-4bb3-a065-613ac4805b9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718399768 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1718399768
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1741988731
Short name T62
Test name
Test status
Simulation time 22923557 ps
CPU time 0.59 seconds
Started Dec 24 01:41:11 PM PST 23
Finished Dec 24 01:41:12 PM PST 23
Peak memory 192408 kb
Host smart-7dfca787-8ebf-4977-bc6d-58033582a34b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741988731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1741988731
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3636918759
Short name T454
Test name
Test status
Simulation time 52578273 ps
CPU time 0.54 seconds
Started Dec 24 01:40:57 PM PST 23
Finished Dec 24 01:40:59 PM PST 23
Peak memory 182604 kb
Host smart-19b10136-f128-4306-b215-0009e1aa40c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636918759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3636918759
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.523403311
Short name T49
Test name
Test status
Simulation time 41159958 ps
CPU time 0.66 seconds
Started Dec 24 01:41:33 PM PST 23
Finished Dec 24 01:41:35 PM PST 23
Peak memory 192164 kb
Host smart-e49cead5-0169-43d1-8715-ae68edd4d34d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523403311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.523403311
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2243583665
Short name T429
Test name
Test status
Simulation time 65517017 ps
CPU time 1.86 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:37 PM PST 23
Peak memory 197992 kb
Host smart-a089552e-8160-4312-9623-41e276f5c9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243583665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2243583665
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.340127914
Short name T27
Test name
Test status
Simulation time 159141771 ps
CPU time 0.83 seconds
Started Dec 24 01:40:57 PM PST 23
Finished Dec 24 01:40:59 PM PST 23
Peak memory 183572 kb
Host smart-0dd864d9-01e8-4d46-addb-f8bb647357eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340127914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.340127914
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3373709790
Short name T446
Test name
Test status
Simulation time 47191434 ps
CPU time 0.65 seconds
Started Dec 24 01:40:54 PM PST 23
Finished Dec 24 01:40:56 PM PST 23
Peak memory 193792 kb
Host smart-c0949b91-9c6b-4008-989f-c89607af9bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373709790 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3373709790
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3636716392
Short name T435
Test name
Test status
Simulation time 27984481 ps
CPU time 0.55 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:57 PM PST 23
Peak memory 182748 kb
Host smart-f12e04fb-f07e-4456-b8fc-d7787ec58410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636716392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3636716392
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2162492710
Short name T438
Test name
Test status
Simulation time 18915926 ps
CPU time 0.55 seconds
Started Dec 24 01:40:57 PM PST 23
Finished Dec 24 01:40:59 PM PST 23
Peak memory 182968 kb
Host smart-6c6bb194-1dc3-414a-88f1-b0e6401bba8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162492710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2162492710
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1806552315
Short name T44
Test name
Test status
Simulation time 76812963 ps
CPU time 0.78 seconds
Started Dec 24 01:40:54 PM PST 23
Finished Dec 24 01:40:56 PM PST 23
Peak memory 192164 kb
Host smart-aab2124d-f239-4a4a-b82b-b18d3dcf2a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806552315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1806552315
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1858926655
Short name T425
Test name
Test status
Simulation time 636550329 ps
CPU time 2.43 seconds
Started Dec 24 01:41:10 PM PST 23
Finished Dec 24 01:41:13 PM PST 23
Peak memory 198020 kb
Host smart-6b9bd4c7-b779-451a-bcbf-46e0b800f299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858926655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1858926655
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.633767112
Short name T50
Test name
Test status
Simulation time 104690974 ps
CPU time 1.13 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:58 PM PST 23
Peak memory 195272 kb
Host smart-3a558598-8f34-4260-a558-e3d5f219e1e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633767112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.633767112
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1098415112
Short name T43
Test name
Test status
Simulation time 67165858 ps
CPU time 0.71 seconds
Started Dec 24 01:40:58 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 195356 kb
Host smart-3a27c9ef-9cd7-4b19-9980-1e6e991c0e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098415112 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1098415112
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3558089028
Short name T382
Test name
Test status
Simulation time 16542615 ps
CPU time 0.61 seconds
Started Dec 24 01:41:23 PM PST 23
Finished Dec 24 01:41:24 PM PST 23
Peak memory 182996 kb
Host smart-7761e5ab-38c1-413d-bfaf-53ac0b2d1019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558089028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3558089028
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1240013493
Short name T452
Test name
Test status
Simulation time 185258024 ps
CPU time 0.81 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 192208 kb
Host smart-433bfb01-aee6-48f8-a4cd-a2caf4b19b82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240013493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1240013493
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.109860665
Short name T473
Test name
Test status
Simulation time 49910233 ps
CPU time 1.39 seconds
Started Dec 24 01:41:35 PM PST 23
Finished Dec 24 01:41:38 PM PST 23
Peak memory 198004 kb
Host smart-55169727-da38-4a92-a5a8-b1ffc71acd45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109860665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.109860665
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2577483541
Short name T476
Test name
Test status
Simulation time 126027633 ps
CPU time 1.4 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 195696 kb
Host smart-cc3205b5-d0cc-4017-b5a6-d9aebbf85228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577483541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2577483541
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3465421926
Short name T39
Test name
Test status
Simulation time 48565442 ps
CPU time 0.8 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 196220 kb
Host smart-8c397a22-60c7-4d95-857b-d729df7142bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465421926 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3465421926
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2445630639
Short name T41
Test name
Test status
Simulation time 17803377 ps
CPU time 0.59 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 183280 kb
Host smart-8c90821a-e1f3-4d2f-ab36-a00355cedce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445630639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2445630639
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3907014031
Short name T431
Test name
Test status
Simulation time 20649972 ps
CPU time 0.54 seconds
Started Dec 24 01:41:32 PM PST 23
Finished Dec 24 01:41:34 PM PST 23
Peak memory 182084 kb
Host smart-ff5b7b1a-adb0-4222-b7a7-835af89d34ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907014031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3907014031
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.588940736
Short name T411
Test name
Test status
Simulation time 142534678 ps
CPU time 0.83 seconds
Started Dec 24 01:41:25 PM PST 23
Finished Dec 24 01:41:27 PM PST 23
Peak memory 192272 kb
Host smart-bd5c2669-5948-4b56-aa2f-78f43d790077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588940736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.588940736
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4172841773
Short name T461
Test name
Test status
Simulation time 224217038 ps
CPU time 2.84 seconds
Started Dec 24 01:40:56 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 198068 kb
Host smart-ba40b44a-6254-4b4e-9e00-c4d3bc6bc954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172841773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4172841773
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4038725375
Short name T94
Test name
Test status
Simulation time 112843164 ps
CPU time 1.42 seconds
Started Dec 24 01:41:33 PM PST 23
Finished Dec 24 01:41:36 PM PST 23
Peak memory 195572 kb
Host smart-bee499eb-2b9d-47a9-9e98-dae1ec3c00e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038725375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4038725375
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1406557621
Short name T337
Test name
Test status
Simulation time 652588720090 ps
CPU time 571.37 seconds
Started Dec 24 12:38:02 PM PST 23
Finished Dec 24 12:47:35 PM PST 23
Peak memory 182772 kb
Host smart-72fe2651-495b-46f1-8f3e-7444ca8bb32c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406557621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1406557621
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2316366019
Short name T571
Test name
Test status
Simulation time 47450579817 ps
CPU time 73.32 seconds
Started Dec 24 12:38:00 PM PST 23
Finished Dec 24 12:39:16 PM PST 23
Peak memory 182772 kb
Host smart-234745fc-8d20-4dc4-806f-0bff1f0135d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316366019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2316366019
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.917404033
Short name T154
Test name
Test status
Simulation time 410256813906 ps
CPU time 1155.07 seconds
Started Dec 24 12:37:58 PM PST 23
Finished Dec 24 12:57:17 PM PST 23
Peak memory 190980 kb
Host smart-fc5a204d-7226-4c35-ad1a-d7d5898ce50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917404033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.917404033
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.83585750
Short name T128
Test name
Test status
Simulation time 87807954505 ps
CPU time 51.45 seconds
Started Dec 24 12:38:00 PM PST 23
Finished Dec 24 12:38:54 PM PST 23
Peak memory 182788 kb
Host smart-5a186205-1e21-468b-bbf4-126205b268ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83585750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.83585750
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1825591740
Short name T13
Test name
Test status
Simulation time 126642397 ps
CPU time 0.83 seconds
Started Dec 24 12:37:55 PM PST 23
Finished Dec 24 12:37:59 PM PST 23
Peak memory 212824 kb
Host smart-ba30e41b-b379-420d-bfbe-696c46115709
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825591740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1825591740
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1702221845
Short name T139
Test name
Test status
Simulation time 191062677549 ps
CPU time 344.75 seconds
Started Dec 24 12:38:02 PM PST 23
Finished Dec 24 12:43:48 PM PST 23
Peak memory 182896 kb
Host smart-6243c9fe-2868-4099-b3cc-babef2ba9a49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702221845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1702221845
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3807251797
Short name T547
Test name
Test status
Simulation time 113459345852 ps
CPU time 55.97 seconds
Started Dec 24 12:37:59 PM PST 23
Finished Dec 24 12:38:58 PM PST 23
Peak memory 182936 kb
Host smart-ba6ebe07-dcfd-4aed-ae67-3f1bcabe8140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807251797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3807251797
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1390674305
Short name T301
Test name
Test status
Simulation time 283288096939 ps
CPU time 179.78 seconds
Started Dec 24 12:38:03 PM PST 23
Finished Dec 24 12:41:04 PM PST 23
Peak memory 182864 kb
Host smart-31df3edf-78c1-4e14-85c8-6b53e8527cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390674305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1390674305
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1220734520
Short name T16
Test name
Test status
Simulation time 153378091 ps
CPU time 0.89 seconds
Started Dec 24 12:38:04 PM PST 23
Finished Dec 24 12:38:06 PM PST 23
Peak memory 213852 kb
Host smart-15f05027-fd40-4ddf-b82f-536b7954954b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220734520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1220734520
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.776999256
Short name T133
Test name
Test status
Simulation time 941650225265 ps
CPU time 386.67 seconds
Started Dec 24 12:37:59 PM PST 23
Finished Dec 24 12:44:29 PM PST 23
Peak memory 190992 kb
Host smart-c1b9b49c-f3a3-43df-892a-4d3ae6a5e22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776999256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.776999256
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.411063127
Short name T525
Test name
Test status
Simulation time 106673963422 ps
CPU time 387.98 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:44:25 PM PST 23
Peak memory 205716 kb
Host smart-04ecab44-a122-4745-9b12-2a83feadb7b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411063127 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.411063127
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.308267090
Short name T171
Test name
Test status
Simulation time 94448381979 ps
CPU time 95.85 seconds
Started Dec 24 12:37:46 PM PST 23
Finished Dec 24 12:39:24 PM PST 23
Peak memory 182784 kb
Host smart-0c703283-dbe6-4023-a99b-35dc8b08362c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308267090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.308267090
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.239576987
Short name T536
Test name
Test status
Simulation time 85229530846 ps
CPU time 75.33 seconds
Started Dec 24 12:37:46 PM PST 23
Finished Dec 24 12:39:04 PM PST 23
Peak memory 182808 kb
Host smart-67c59c1a-fccb-44ac-ac05-3801605736af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239576987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.239576987
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3453040670
Short name T287
Test name
Test status
Simulation time 122849661151 ps
CPU time 111.34 seconds
Started Dec 24 12:37:41 PM PST 23
Finished Dec 24 12:39:38 PM PST 23
Peak memory 191016 kb
Host smart-5f47875c-4ada-4131-ac6b-367310cc1862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453040670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3453040670
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.201821103
Short name T559
Test name
Test status
Simulation time 49065542001 ps
CPU time 30.33 seconds
Started Dec 24 12:37:47 PM PST 23
Finished Dec 24 12:38:19 PM PST 23
Peak memory 194824 kb
Host smart-2f40f6ae-e18f-4f1e-a754-c59a7fbd6f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201821103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.201821103
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2827393462
Short name T361
Test name
Test status
Simulation time 607862458866 ps
CPU time 1081.24 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:55:59 PM PST 23
Peak memory 190992 kb
Host smart-cd810926-c3af-4024-bc79-bb74b12479ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827393462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2827393462
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2003133962
Short name T145
Test name
Test status
Simulation time 259493034825 ps
CPU time 914.64 seconds
Started Dec 24 12:37:49 PM PST 23
Finished Dec 24 12:53:07 PM PST 23
Peak memory 205724 kb
Host smart-1ffa16d4-4f0f-462c-873d-8871b381914d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003133962 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2003133962
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2010285724
Short name T256
Test name
Test status
Simulation time 235279461255 ps
CPU time 632.59 seconds
Started Dec 24 12:39:04 PM PST 23
Finished Dec 24 12:49:41 PM PST 23
Peak memory 191188 kb
Host smart-871cbe2b-0738-41d3-a1f5-7f54def68d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010285724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2010285724
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1067768833
Short name T149
Test name
Test status
Simulation time 445741454039 ps
CPU time 175.41 seconds
Started Dec 24 12:39:07 PM PST 23
Finished Dec 24 12:42:05 PM PST 23
Peak memory 191072 kb
Host smart-e33ba379-7f2b-459f-a75d-847bff126ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067768833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1067768833
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2433490553
Short name T143
Test name
Test status
Simulation time 530681159773 ps
CPU time 131.35 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:41:18 PM PST 23
Peak memory 191132 kb
Host smart-83ba94de-5434-4218-95ac-e0a5d0a7e8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433490553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2433490553
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.4129819736
Short name T210
Test name
Test status
Simulation time 403890966153 ps
CPU time 415.04 seconds
Started Dec 24 12:39:04 PM PST 23
Finished Dec 24 12:46:04 PM PST 23
Peak memory 194452 kb
Host smart-a5299470-ea13-4f14-90e9-bebfb4decf03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129819736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4129819736
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3060835237
Short name T116
Test name
Test status
Simulation time 757558749928 ps
CPU time 322.94 seconds
Started Dec 24 12:39:02 PM PST 23
Finished Dec 24 12:44:30 PM PST 23
Peak memory 191172 kb
Host smart-9b87dcca-7964-42d1-b14d-e9b8f650cf11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060835237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3060835237
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2137718350
Short name T316
Test name
Test status
Simulation time 145977097764 ps
CPU time 128.9 seconds
Started Dec 24 12:39:05 PM PST 23
Finished Dec 24 12:41:18 PM PST 23
Peak memory 191172 kb
Host smart-48a584b8-ed07-40c0-9bc7-01f0abd09d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137718350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2137718350
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1564122544
Short name T24
Test name
Test status
Simulation time 102367965697 ps
CPU time 177.62 seconds
Started Dec 24 12:39:14 PM PST 23
Finished Dec 24 12:42:13 PM PST 23
Peak memory 191120 kb
Host smart-824b0d52-d487-4d34-8fac-dc6e15bc3554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564122544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1564122544
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2332827662
Short name T324
Test name
Test status
Simulation time 56019921381 ps
CPU time 80.37 seconds
Started Dec 24 12:39:10 PM PST 23
Finished Dec 24 12:40:32 PM PST 23
Peak memory 194236 kb
Host smart-d8131fd4-eb28-486b-aa61-fa87e43878b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332827662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2332827662
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2851054871
Short name T371
Test name
Test status
Simulation time 1328024657028 ps
CPU time 1403.95 seconds
Started Dec 24 12:37:48 PM PST 23
Finished Dec 24 01:01:15 PM PST 23
Peak memory 182896 kb
Host smart-cbc4744d-05c1-407e-aebf-92e7aadd959a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851054871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2851054871
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3214523645
Short name T522
Test name
Test status
Simulation time 185660432897 ps
CPU time 96.42 seconds
Started Dec 24 12:37:53 PM PST 23
Finished Dec 24 12:39:33 PM PST 23
Peak memory 182968 kb
Host smart-854d6405-533d-4a5b-a937-65c152f87bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214523645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3214523645
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3852116852
Short name T600
Test name
Test status
Simulation time 1029266044 ps
CPU time 1.46 seconds
Started Dec 24 12:37:50 PM PST 23
Finished Dec 24 12:37:55 PM PST 23
Peak memory 182880 kb
Host smart-d1c305e7-2668-40ff-ab52-a2243016666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852116852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3852116852
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1364746776
Short name T572
Test name
Test status
Simulation time 115260412774 ps
CPU time 88.16 seconds
Started Dec 24 12:39:08 PM PST 23
Finished Dec 24 12:40:38 PM PST 23
Peak memory 182840 kb
Host smart-b1bcc8f9-6280-4454-a5c6-08172e1ea212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364746776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1364746776
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2973136608
Short name T251
Test name
Test status
Simulation time 127598493942 ps
CPU time 196.32 seconds
Started Dec 24 12:39:06 PM PST 23
Finished Dec 24 12:42:26 PM PST 23
Peak memory 194584 kb
Host smart-63018836-466b-4dcc-954c-f5fb6104b033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973136608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2973136608
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2147207290
Short name T300
Test name
Test status
Simulation time 31066323288 ps
CPU time 219.74 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:42:46 PM PST 23
Peak memory 191028 kb
Host smart-2853210b-af00-461c-8c3f-7080b4016e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147207290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2147207290
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.878900593
Short name T212
Test name
Test status
Simulation time 79182239753 ps
CPU time 129.58 seconds
Started Dec 24 12:39:05 PM PST 23
Finished Dec 24 12:41:18 PM PST 23
Peak memory 191072 kb
Host smart-ae9114aa-b8b3-4a58-9e42-8783c7e3cb57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878900593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.878900593
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3880491057
Short name T107
Test name
Test status
Simulation time 102260264364 ps
CPU time 491.52 seconds
Started Dec 24 12:39:05 PM PST 23
Finished Dec 24 12:47:20 PM PST 23
Peak memory 191036 kb
Host smart-9406a355-6dd4-4f00-9dd6-1143bc872630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880491057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3880491057
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2232559605
Short name T321
Test name
Test status
Simulation time 282532146991 ps
CPU time 126.94 seconds
Started Dec 24 12:39:10 PM PST 23
Finished Dec 24 12:41:18 PM PST 23
Peak memory 191036 kb
Host smart-6ba9f914-fdb7-4d29-8a67-e6ed287eec06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232559605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2232559605
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3932667452
Short name T247
Test name
Test status
Simulation time 100681350601 ps
CPU time 202.04 seconds
Started Dec 24 12:39:06 PM PST 23
Finished Dec 24 12:42:32 PM PST 23
Peak memory 191076 kb
Host smart-82cfaa39-0a96-4715-bd1c-4f416f616404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932667452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3932667452
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2716055646
Short name T331
Test name
Test status
Simulation time 59472679166 ps
CPU time 93.54 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:39:28 PM PST 23
Peak memory 182804 kb
Host smart-73232c75-31ca-44bc-af57-fe86e054e07f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716055646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2716055646
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.52891619
Short name T599
Test name
Test status
Simulation time 90443118849 ps
CPU time 135.56 seconds
Started Dec 24 12:38:02 PM PST 23
Finished Dec 24 12:40:20 PM PST 23
Peak memory 182948 kb
Host smart-ec4fca91-42c1-4d82-8e46-b8a1f7d1ce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52891619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.52891619
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2826870184
Short name T272
Test name
Test status
Simulation time 254444008187 ps
CPU time 249.73 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:42:03 PM PST 23
Peak memory 191076 kb
Host smart-4af76feb-786d-4b14-93c6-760d0d58aac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826870184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2826870184
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2141791581
Short name T164
Test name
Test status
Simulation time 21887717825 ps
CPU time 39.97 seconds
Started Dec 24 12:37:56 PM PST 23
Finished Dec 24 12:38:41 PM PST 23
Peak memory 182804 kb
Host smart-fe6f7e78-a832-4015-8fe4-94bf3c474b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141791581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2141791581
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3990016755
Short name T253
Test name
Test status
Simulation time 170790514601 ps
CPU time 654.35 seconds
Started Dec 24 12:38:01 PM PST 23
Finished Dec 24 12:48:58 PM PST 23
Peak memory 205840 kb
Host smart-e3626e2c-4294-42cb-83d5-0fc019029a40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990016755 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3990016755
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.3430874393
Short name T610
Test name
Test status
Simulation time 82720389484 ps
CPU time 480.81 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:47:08 PM PST 23
Peak memory 182976 kb
Host smart-626c86b9-37ac-48c0-929e-be26864a6d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430874393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3430874393
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3772210303
Short name T267
Test name
Test status
Simulation time 306965712733 ps
CPU time 269.46 seconds
Started Dec 24 12:39:02 PM PST 23
Finished Dec 24 12:43:37 PM PST 23
Peak memory 191052 kb
Host smart-f92c386e-26a3-4860-958e-b49f9ccf7dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772210303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3772210303
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1787773089
Short name T307
Test name
Test status
Simulation time 82576890011 ps
CPU time 142.98 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:41:30 PM PST 23
Peak memory 191112 kb
Host smart-b2780016-f586-49e8-9fb6-a7f1c370faac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787773089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1787773089
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.545586927
Short name T271
Test name
Test status
Simulation time 137953736915 ps
CPU time 537.93 seconds
Started Dec 24 12:39:07 PM PST 23
Finished Dec 24 12:48:08 PM PST 23
Peak memory 191040 kb
Host smart-1a9295f5-fb8f-4a89-854e-d7a1c48f93ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545586927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.545586927
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.514513001
Short name T248
Test name
Test status
Simulation time 110683009882 ps
CPU time 476.76 seconds
Started Dec 24 12:39:03 PM PST 23
Finished Dec 24 12:47:05 PM PST 23
Peak memory 191176 kb
Host smart-ea3826e2-ae8c-4314-93ec-63f317b32fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514513001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.514513001
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2072981406
Short name T222
Test name
Test status
Simulation time 85078556611 ps
CPU time 424.19 seconds
Started Dec 24 12:39:05 PM PST 23
Finished Dec 24 12:46:13 PM PST 23
Peak memory 191076 kb
Host smart-8b5751fa-fbdc-4d9b-9010-ff817d5380c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072981406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2072981406
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1682094038
Short name T216
Test name
Test status
Simulation time 333582816236 ps
CPU time 1511.44 seconds
Started Dec 24 12:39:08 PM PST 23
Finished Dec 24 01:04:22 PM PST 23
Peak memory 191048 kb
Host smart-d1ca527d-2ebc-4104-80d5-0e8a18b99a39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682094038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1682094038
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2293821902
Short name T352
Test name
Test status
Simulation time 557727245105 ps
CPU time 524.28 seconds
Started Dec 24 12:37:52 PM PST 23
Finished Dec 24 12:46:39 PM PST 23
Peak memory 182812 kb
Host smart-7ec01157-3faa-487b-b45a-e27a35a08350
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293821902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2293821902
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2901154245
Short name T555
Test name
Test status
Simulation time 61677544997 ps
CPU time 73.44 seconds
Started Dec 24 12:37:55 PM PST 23
Finished Dec 24 12:39:12 PM PST 23
Peak memory 182872 kb
Host smart-e964bfcd-54b6-44b5-8f43-da555eaf8e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901154245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2901154245
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.66494012
Short name T513
Test name
Test status
Simulation time 54800204 ps
CPU time 0.56 seconds
Started Dec 24 12:37:56 PM PST 23
Finished Dec 24 12:38:01 PM PST 23
Peak memory 182252 kb
Host smart-5f604f4a-4800-41ce-b59a-fbd1519b5af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66494012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.66494012
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3279445959
Short name T130
Test name
Test status
Simulation time 140469840946 ps
CPU time 130.92 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:40:23 PM PST 23
Peak memory 191236 kb
Host smart-7ffd8155-831a-4d32-90a3-390b606c2b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279445959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3279445959
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.1518886961
Short name T327
Test name
Test status
Simulation time 32024087800 ps
CPU time 250.6 seconds
Started Dec 24 12:39:07 PM PST 23
Finished Dec 24 12:43:21 PM PST 23
Peak memory 191184 kb
Host smart-1b407bcc-5f38-4430-96a9-4c9ec288e907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518886961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1518886961
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3223005314
Short name T110
Test name
Test status
Simulation time 478698758320 ps
CPU time 1264.54 seconds
Started Dec 24 12:39:12 PM PST 23
Finished Dec 24 01:00:17 PM PST 23
Peak memory 191120 kb
Host smart-aa4865bd-576a-4f5c-8a6c-97a38f29c775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223005314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3223005314
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.973192932
Short name T261
Test name
Test status
Simulation time 211595388147 ps
CPU time 378.01 seconds
Started Dec 24 12:39:10 PM PST 23
Finished Dec 24 12:45:29 PM PST 23
Peak memory 191040 kb
Host smart-304d30dd-7e6e-4bca-95a8-45337c9dd796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973192932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.973192932
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3289998936
Short name T557
Test name
Test status
Simulation time 149566603188 ps
CPU time 52.26 seconds
Started Dec 24 12:39:24 PM PST 23
Finished Dec 24 12:40:19 PM PST 23
Peak memory 182768 kb
Host smart-186fd937-4386-489d-b7dc-2ce9f45c660f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289998936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3289998936
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3726819525
Short name T576
Test name
Test status
Simulation time 171159501880 ps
CPU time 172.59 seconds
Started Dec 24 12:39:08 PM PST 23
Finished Dec 24 12:42:03 PM PST 23
Peak memory 193192 kb
Host smart-decfd1d7-2c72-42a4-953a-324580d3ff80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726819525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3726819525
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1995593879
Short name T103
Test name
Test status
Simulation time 367229556773 ps
CPU time 178.57 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:42:05 PM PST 23
Peak memory 191068 kb
Host smart-8d6ea185-0c7d-41d8-a896-b7792fbf5f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995593879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1995593879
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.765591798
Short name T234
Test name
Test status
Simulation time 363281994830 ps
CPU time 758.14 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:52:21 PM PST 23
Peak memory 193948 kb
Host smart-46efb36a-87bd-4344-8f15-647f66476694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765591798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.765591798
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1899583783
Short name T545
Test name
Test status
Simulation time 126171571584 ps
CPU time 97.74 seconds
Started Dec 24 12:37:48 PM PST 23
Finished Dec 24 12:39:30 PM PST 23
Peak memory 182888 kb
Host smart-382b3d29-1e8b-4412-9089-1945062772b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899583783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1899583783
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2105554533
Short name T286
Test name
Test status
Simulation time 298491265836 ps
CPU time 721.69 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:50:12 PM PST 23
Peak memory 191164 kb
Host smart-0ba30af3-74f3-41a7-8216-89c240423458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105554533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2105554533
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.306777379
Short name T152
Test name
Test status
Simulation time 248034637293 ps
CPU time 605.38 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:48:19 PM PST 23
Peak memory 191076 kb
Host smart-8dbd02c9-0fc5-4677-a5f1-5bbe3e9e4a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306777379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
306777379
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3530611068
Short name T588
Test name
Test status
Simulation time 307440117121 ps
CPU time 621.6 seconds
Started Dec 24 12:38:01 PM PST 23
Finished Dec 24 12:48:25 PM PST 23
Peak memory 208832 kb
Host smart-248f4a08-c9e7-44e1-be7c-10e61eff35b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530611068 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3530611068
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1901792981
Short name T108
Test name
Test status
Simulation time 142874370816 ps
CPU time 479.44 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 191028 kb
Host smart-ac9c8e8a-dc9d-4c08-8f08-ad2db246980a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901792981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1901792981
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.229190916
Short name T105
Test name
Test status
Simulation time 1578902519456 ps
CPU time 644.44 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:50:25 PM PST 23
Peak memory 191068 kb
Host smart-477f9637-0040-4568-b536-ed640cabe58b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229190916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.229190916
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4226576701
Short name T365
Test name
Test status
Simulation time 337589999990 ps
CPU time 2288.57 seconds
Started Dec 24 12:39:41 PM PST 23
Finished Dec 24 01:17:52 PM PST 23
Peak memory 194192 kb
Host smart-3c9f2c29-1295-4d1b-a7cf-fa0813054ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226576701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4226576701
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3713186813
Short name T4
Test name
Test status
Simulation time 233387519956 ps
CPU time 898.19 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:54:39 PM PST 23
Peak memory 191224 kb
Host smart-7121a8d6-75d7-4c22-a336-25ae1d210f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713186813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3713186813
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3696850299
Short name T163
Test name
Test status
Simulation time 150548832272 ps
CPU time 533.3 seconds
Started Dec 24 12:39:41 PM PST 23
Finished Dec 24 12:48:37 PM PST 23
Peak memory 191140 kb
Host smart-7357c08f-bd5a-4248-aa77-82d7ff2466a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696850299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3696850299
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3348928644
Short name T556
Test name
Test status
Simulation time 252495483721 ps
CPU time 74.4 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:40:55 PM PST 23
Peak memory 182904 kb
Host smart-5ba3e815-3478-49a6-a797-79d1b2ccb2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348928644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3348928644
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.292823688
Short name T350
Test name
Test status
Simulation time 214049037691 ps
CPU time 88.38 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:41:09 PM PST 23
Peak memory 191124 kb
Host smart-71548ec2-29ce-4e39-8349-58bf66f1845e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292823688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.292823688
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2051695433
Short name T117
Test name
Test status
Simulation time 242574432067 ps
CPU time 188.52 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:42:53 PM PST 23
Peak memory 191096 kb
Host smart-2709cc64-eeec-416b-ab3b-c26e11de7cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051695433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2051695433
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.871547258
Short name T294
Test name
Test status
Simulation time 13959771801 ps
CPU time 24.77 seconds
Started Dec 24 12:38:03 PM PST 23
Finished Dec 24 12:38:29 PM PST 23
Peak memory 182784 kb
Host smart-6f26f871-cf55-4ed4-8515-3f87e7c222ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871547258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.871547258
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.149912061
Short name T502
Test name
Test status
Simulation time 586834186607 ps
CPU time 267.47 seconds
Started Dec 24 12:37:47 PM PST 23
Finished Dec 24 12:42:18 PM PST 23
Peak memory 182916 kb
Host smart-1c4efce6-bde3-425f-82e2-9b6ac9eaac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149912061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.149912061
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2701250426
Short name T183
Test name
Test status
Simulation time 46611197083 ps
CPU time 104.11 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:39:55 PM PST 23
Peak memory 191100 kb
Host smart-5306118f-1af0-4ee5-8b8f-41c1a7175e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701250426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2701250426
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.312334277
Short name T540
Test name
Test status
Simulation time 2292176278582 ps
CPU time 382.59 seconds
Started Dec 24 12:37:49 PM PST 23
Finished Dec 24 12:44:16 PM PST 23
Peak memory 191080 kb
Host smart-eeeb1ab3-843e-4030-9b69-61728b15bf01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312334277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
312334277
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.789691518
Short name T614
Test name
Test status
Simulation time 80351439208 ps
CPU time 820.41 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:51:51 PM PST 23
Peak memory 197524 kb
Host smart-d60367b0-7cad-4f36-8abe-35f0a6e6b481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789691518 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.789691518
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.rv_timer_random.2810210821
Short name T349
Test name
Test status
Simulation time 64097673376 ps
CPU time 105.51 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:41:28 PM PST 23
Peak memory 192192 kb
Host smart-b82eddbe-9203-44d7-b926-266edb60ad96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810210821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2810210821
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2700971644
Short name T306
Test name
Test status
Simulation time 36312207595 ps
CPU time 100.91 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:41:26 PM PST 23
Peak memory 191176 kb
Host smart-7a31307a-6b8a-4a7f-b465-ccb4054f11c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700971644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2700971644
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.393999552
Short name T221
Test name
Test status
Simulation time 51572594533 ps
CPU time 77.7 seconds
Started Dec 24 12:39:40 PM PST 23
Finished Dec 24 12:41:01 PM PST 23
Peak memory 192376 kb
Host smart-d3441c95-ccfe-4ffd-b1bb-0ed02fa1440e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393999552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.393999552
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.753217973
Short name T155
Test name
Test status
Simulation time 64982890362 ps
CPU time 377.59 seconds
Started Dec 24 12:39:40 PM PST 23
Finished Dec 24 12:46:01 PM PST 23
Peak memory 193812 kb
Host smart-097e458f-257d-4487-92cc-098d96d1a98a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753217973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.753217973
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4242284638
Short name T340
Test name
Test status
Simulation time 54238465230 ps
CPU time 63.35 seconds
Started Dec 24 12:39:40 PM PST 23
Finished Dec 24 12:40:46 PM PST 23
Peak memory 191212 kb
Host smart-e1cfaf08-ce4a-4dd2-8c78-89e612afce37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242284638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4242284638
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2100600453
Short name T328
Test name
Test status
Simulation time 60264769610 ps
CPU time 28.15 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:40:09 PM PST 23
Peak memory 182836 kb
Host smart-5749e406-3f25-4b44-aa64-00d083384b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100600453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2100600453
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2640936194
Short name T326
Test name
Test status
Simulation time 1376821042103 ps
CPU time 776.59 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:50:50 PM PST 23
Peak memory 182792 kb
Host smart-66ce289d-dd05-42c3-b1ff-d25dece3d10f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640936194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2640936194
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.188524798
Short name T514
Test name
Test status
Simulation time 329498245677 ps
CPU time 150.64 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:40:43 PM PST 23
Peak memory 182852 kb
Host smart-8b64da24-a64d-4e28-957b-96bb294a4f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188524798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.188524798
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2959208343
Short name T505
Test name
Test status
Simulation time 797601826 ps
CPU time 1.24 seconds
Started Dec 24 12:38:13 PM PST 23
Finished Dec 24 12:38:16 PM PST 23
Peak memory 182600 kb
Host smart-3cc0a759-ae59-4f25-9864-ae65027fc9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959208343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2959208343
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.845531329
Short name T538
Test name
Test status
Simulation time 33995502480 ps
CPU time 113.68 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:39:48 PM PST 23
Peak memory 197864 kb
Host smart-9a941391-2b94-4004-a150-94022d35022a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845531329 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.845531329
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3484476440
Short name T353
Test name
Test status
Simulation time 320964437559 ps
CPU time 733.63 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:51:53 PM PST 23
Peak memory 191064 kb
Host smart-1241dc11-e49c-4a3f-bb16-3406548716ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484476440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3484476440
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.332556831
Short name T362
Test name
Test status
Simulation time 298744772672 ps
CPU time 190.63 seconds
Started Dec 24 12:39:40 PM PST 23
Finished Dec 24 12:42:54 PM PST 23
Peak memory 190972 kb
Host smart-5ff91dc7-3d82-4020-9be1-94d8568609aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332556831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.332556831
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1158577374
Short name T377
Test name
Test status
Simulation time 51006656567 ps
CPU time 80.45 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:41:00 PM PST 23
Peak memory 191168 kb
Host smart-d3988d8c-27d8-4809-944e-658133f52b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158577374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1158577374
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2707160257
Short name T370
Test name
Test status
Simulation time 288202026428 ps
CPU time 62.71 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:40:43 PM PST 23
Peak memory 182580 kb
Host smart-0fc1142b-ecd2-4473-bd38-6771947ebbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707160257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2707160257
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3513383904
Short name T592
Test name
Test status
Simulation time 182065613595 ps
CPU time 332.1 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:45:14 PM PST 23
Peak memory 194696 kb
Host smart-e3966765-b786-4b5b-9839-e25df7ff32cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513383904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3513383904
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3360780016
Short name T22
Test name
Test status
Simulation time 117590896611 ps
CPU time 240.9 seconds
Started Dec 24 12:39:41 PM PST 23
Finished Dec 24 12:43:45 PM PST 23
Peak memory 191004 kb
Host smart-65445be7-b6f9-4ecb-9f5e-47f63d3a506e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360780016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3360780016
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4021544967
Short name T354
Test name
Test status
Simulation time 277568357611 ps
CPU time 341.29 seconds
Started Dec 24 12:39:38 PM PST 23
Finished Dec 24 12:45:22 PM PST 23
Peak memory 191132 kb
Host smart-5a9a8d89-2950-4ada-8941-c96f3bc2728e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021544967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4021544967
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.784429000
Short name T236
Test name
Test status
Simulation time 155946953477 ps
CPU time 275.3 seconds
Started Dec 24 12:38:04 PM PST 23
Finished Dec 24 12:42:41 PM PST 23
Peak memory 182960 kb
Host smart-74303d8b-2388-4ca5-83fa-5ed365aa4a8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784429000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.784429000
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3527375854
Short name T511
Test name
Test status
Simulation time 561736059874 ps
CPU time 232.43 seconds
Started Dec 24 12:38:07 PM PST 23
Finished Dec 24 12:42:03 PM PST 23
Peak memory 182872 kb
Host smart-ee84ec7f-33b7-4b1f-aab0-d038ca9ef07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527375854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3527375854
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1946518367
Short name T269
Test name
Test status
Simulation time 298247587105 ps
CPU time 72.97 seconds
Started Dec 24 12:37:55 PM PST 23
Finished Dec 24 12:39:11 PM PST 23
Peak memory 191140 kb
Host smart-9ef28ab6-78bc-4bda-9929-f173c70db00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946518367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1946518367
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1523159597
Short name T12
Test name
Test status
Simulation time 140416238585 ps
CPU time 571.81 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:47:30 PM PST 23
Peak memory 205788 kb
Host smart-08116b58-33bc-489e-85a0-325a9517ef09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523159597 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1523159597
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.3613208664
Short name T101
Test name
Test status
Simulation time 68461944575 ps
CPU time 61.47 seconds
Started Dec 24 12:39:36 PM PST 23
Finished Dec 24 12:40:41 PM PST 23
Peak memory 182840 kb
Host smart-ab6279f5-1b96-454d-a245-4f1ec5ca174a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613208664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3613208664
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.4181948867
Short name T364
Test name
Test status
Simulation time 206844519655 ps
CPU time 234.26 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:43:34 PM PST 23
Peak memory 190988 kb
Host smart-5b291f61-dfb0-453b-90e8-57155cb7f2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181948867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4181948867
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3924720896
Short name T549
Test name
Test status
Simulation time 83948485771 ps
CPU time 77 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:40:59 PM PST 23
Peak memory 182836 kb
Host smart-01aceff0-57fd-445d-abba-0ab523eeda54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924720896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3924720896
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3703319662
Short name T578
Test name
Test status
Simulation time 358754561063 ps
CPU time 500.39 seconds
Started Dec 24 12:39:36 PM PST 23
Finished Dec 24 12:48:00 PM PST 23
Peak memory 193960 kb
Host smart-ef018148-2840-42c9-b779-54866a489583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703319662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3703319662
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1581083720
Short name T542
Test name
Test status
Simulation time 515810328967 ps
CPU time 232.17 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:41:50 PM PST 23
Peak memory 182948 kb
Host smart-7fbb2163-878c-446f-83ec-8f9b2cb5e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581083720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1581083720
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.473937120
Short name T260
Test name
Test status
Simulation time 34370162291 ps
CPU time 372.07 seconds
Started Dec 24 12:38:07 PM PST 23
Finished Dec 24 12:44:23 PM PST 23
Peak memory 182816 kb
Host smart-c6b16e64-8200-4c08-b0a1-70f95dd923d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473937120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.473937120
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.107772864
Short name T109
Test name
Test status
Simulation time 433410652096 ps
CPU time 393.41 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:44:44 PM PST 23
Peak memory 191052 kb
Host smart-b0de4a37-a450-4ac8-89a7-af9fef65da02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107772864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
107772864
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2160295866
Short name T503
Test name
Test status
Simulation time 8543727368 ps
CPU time 83.27 seconds
Started Dec 24 12:38:04 PM PST 23
Finished Dec 24 12:39:28 PM PST 23
Peak memory 197632 kb
Host smart-eaae2950-a801-43a5-83eb-e5ba38a69a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160295866 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2160295866
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1730587846
Short name T282
Test name
Test status
Simulation time 38056166687 ps
CPU time 36.97 seconds
Started Dec 24 12:39:39 PM PST 23
Finished Dec 24 12:40:19 PM PST 23
Peak memory 182936 kb
Host smart-d6541d1f-bf7a-46e7-b0df-033c4a762420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730587846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1730587846
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.4086245529
Short name T275
Test name
Test status
Simulation time 2094114083557 ps
CPU time 463.62 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:47:24 PM PST 23
Peak memory 193800 kb
Host smart-6373b19a-4716-4b7c-b92d-50f714ac8fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086245529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4086245529
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3817101075
Short name T609
Test name
Test status
Simulation time 127782655168 ps
CPU time 59.96 seconds
Started Dec 24 12:39:56 PM PST 23
Finished Dec 24 12:40:56 PM PST 23
Peak memory 182952 kb
Host smart-80b0bd79-53b2-4b81-ad4f-eea46c8bfd65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817101075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3817101075
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1656790639
Short name T288
Test name
Test status
Simulation time 724302542051 ps
CPU time 136.2 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:42:01 PM PST 23
Peak memory 191028 kb
Host smart-ea6ba835-b91b-48ab-82af-96481207d078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656790639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1656790639
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.836663403
Short name T332
Test name
Test status
Simulation time 65170672810 ps
CPU time 77.83 seconds
Started Dec 24 12:39:41 PM PST 23
Finished Dec 24 12:41:01 PM PST 23
Peak memory 191132 kb
Host smart-71a4db9c-c8b1-4ba8-8d43-24e8e255087d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836663403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.836663403
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.214049890
Short name T279
Test name
Test status
Simulation time 53005375851 ps
CPU time 24.66 seconds
Started Dec 24 12:39:46 PM PST 23
Finished Dec 24 12:40:13 PM PST 23
Peak memory 191148 kb
Host smart-9c403dae-9b86-40f4-bdda-0463307380fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214049890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.214049890
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.4182962928
Short name T298
Test name
Test status
Simulation time 416994615210 ps
CPU time 1058.38 seconds
Started Dec 24 12:39:46 PM PST 23
Finished Dec 24 12:57:26 PM PST 23
Peak memory 191112 kb
Host smart-f262b327-a661-4ed6-8529-a1fd1f7f041c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182962928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4182962928
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.769114766
Short name T315
Test name
Test status
Simulation time 142646877364 ps
CPU time 84.86 seconds
Started Dec 24 12:39:42 PM PST 23
Finished Dec 24 12:41:10 PM PST 23
Peak memory 182820 kb
Host smart-2bde06a4-357a-4b02-a64f-6636195c7f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769114766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.769114766
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3083709623
Short name T158
Test name
Test status
Simulation time 116546509534 ps
CPU time 197.43 seconds
Started Dec 24 12:39:45 PM PST 23
Finished Dec 24 12:43:04 PM PST 23
Peak memory 191052 kb
Host smart-577ceea9-d0d4-448f-ae14-f52bb2e601fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083709623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3083709623
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1359174373
Short name T552
Test name
Test status
Simulation time 1358949538883 ps
CPU time 672.63 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:49:26 PM PST 23
Peak memory 182836 kb
Host smart-cb0a993b-74c0-4ff4-8917-74c8cc01743f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359174373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1359174373
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.196279461
Short name T615
Test name
Test status
Simulation time 68564135536 ps
CPU time 102.42 seconds
Started Dec 24 12:37:47 PM PST 23
Finished Dec 24 12:39:31 PM PST 23
Peak memory 182944 kb
Host smart-638db131-f1be-44e2-b0fb-41f607203900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196279461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.196279461
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1357432475
Short name T249
Test name
Test status
Simulation time 146270865286 ps
CPU time 249.9 seconds
Started Dec 24 12:37:52 PM PST 23
Finished Dec 24 12:42:05 PM PST 23
Peak memory 191044 kb
Host smart-9c29ee49-2f90-4fba-9304-53d843e501e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357432475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1357432475
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1450743343
Short name T304
Test name
Test status
Simulation time 193023264785 ps
CPU time 215.42 seconds
Started Dec 24 12:38:02 PM PST 23
Finished Dec 24 12:41:39 PM PST 23
Peak memory 191116 kb
Host smart-ad130c94-32fa-497b-b33b-1aa13556bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450743343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1450743343
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.311143277
Short name T591
Test name
Test status
Simulation time 350849516947 ps
CPU time 742.14 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:50:35 PM PST 23
Peak memory 209164 kb
Host smart-1b70e855-3348-494a-9bf3-d1a8f090f850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311143277 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.311143277
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.116451234
Short name T99
Test name
Test status
Simulation time 310024951859 ps
CPU time 1000.02 seconds
Started Dec 24 12:39:40 PM PST 23
Finished Dec 24 12:56:23 PM PST 23
Peak memory 191992 kb
Host smart-4727a1e9-fce2-4922-92c2-1996142e0bf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116451234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.116451234
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1033773223
Short name T190
Test name
Test status
Simulation time 652558787212 ps
CPU time 406.19 seconds
Started Dec 24 12:39:40 PM PST 23
Finished Dec 24 12:46:30 PM PST 23
Peak memory 191176 kb
Host smart-8615580f-2573-4397-862e-f9136a31e30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033773223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1033773223
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2791340310
Short name T266
Test name
Test status
Simulation time 525271042989 ps
CPU time 227.28 seconds
Started Dec 24 12:39:43 PM PST 23
Finished Dec 24 12:43:33 PM PST 23
Peak memory 191032 kb
Host smart-013b6851-f339-4b9d-870f-ddba89a5e26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791340310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2791340310
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4104292378
Short name T204
Test name
Test status
Simulation time 403449254149 ps
CPU time 222.91 seconds
Started Dec 24 12:39:44 PM PST 23
Finished Dec 24 12:43:29 PM PST 23
Peak memory 193900 kb
Host smart-50e47b33-561f-4505-a8e5-214866d150c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104292378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4104292378
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2093112227
Short name T368
Test name
Test status
Simulation time 765735451223 ps
CPU time 780.37 seconds
Started Dec 24 12:39:37 PM PST 23
Finished Dec 24 12:52:41 PM PST 23
Peak memory 191116 kb
Host smart-aca903c8-0166-436d-9cff-b10012841db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093112227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2093112227
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1813000334
Short name T520
Test name
Test status
Simulation time 737246806311 ps
CPU time 404.53 seconds
Started Dec 24 12:38:00 PM PST 23
Finished Dec 24 12:44:47 PM PST 23
Peak memory 182804 kb
Host smart-ad3c511a-7cd1-4c99-b6d1-8ec8de1fb5ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813000334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1813000334
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1300703948
Short name T501
Test name
Test status
Simulation time 716621684898 ps
CPU time 271.4 seconds
Started Dec 24 12:37:55 PM PST 23
Finished Dec 24 12:42:31 PM PST 23
Peak memory 182788 kb
Host smart-e9f2206a-103e-480e-b5fb-61b782ba1ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300703948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1300703948
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2744146146
Short name T85
Test name
Test status
Simulation time 93456683102 ps
CPU time 3440.79 seconds
Started Dec 24 12:37:48 PM PST 23
Finished Dec 24 01:35:13 PM PST 23
Peak memory 182792 kb
Host smart-6b5e59e5-107d-404e-954e-a2f3e54fd802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744146146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2744146146
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3723967409
Short name T18
Test name
Test status
Simulation time 83911158 ps
CPU time 0.92 seconds
Started Dec 24 12:37:52 PM PST 23
Finished Dec 24 12:37:56 PM PST 23
Peak memory 213896 kb
Host smart-c7eae16c-ae2b-4e4d-908c-1034e9214673
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723967409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3723967409
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.646773232
Short name T613
Test name
Test status
Simulation time 806635001887 ps
CPU time 783.75 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:51:15 PM PST 23
Peak memory 182872 kb
Host smart-6d4ca3da-f97c-4a5b-a003-fff6ec6cc80d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646773232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.646773232
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1595055962
Short name T510
Test name
Test status
Simulation time 20693994619 ps
CPU time 29.96 seconds
Started Dec 24 12:37:52 PM PST 23
Finished Dec 24 12:38:24 PM PST 23
Peak memory 182988 kb
Host smart-9dd81a1e-9e9a-4be1-9207-27e2d0c2c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595055962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1595055962
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.4062781971
Short name T358
Test name
Test status
Simulation time 136218773573 ps
CPU time 85.9 seconds
Started Dec 24 12:37:50 PM PST 23
Finished Dec 24 12:39:19 PM PST 23
Peak memory 182876 kb
Host smart-6d2bfe78-709a-4f90-bd6f-ce453674ca7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062781971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.4062781971
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3438417716
Short name T596
Test name
Test status
Simulation time 2123636584 ps
CPU time 1.25 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:38:12 PM PST 23
Peak memory 182920 kb
Host smart-1e25feac-6a84-459e-a681-06b2b12936f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438417716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3438417716
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3307911217
Short name T312
Test name
Test status
Simulation time 128502486707 ps
CPU time 1071.15 seconds
Started Dec 24 12:38:13 PM PST 23
Finished Dec 24 12:56:07 PM PST 23
Peak memory 207268 kb
Host smart-b4cad186-2fa5-4029-95ca-fa4f0814421b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307911217 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3307911217
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3479997401
Short name T86
Test name
Test status
Simulation time 246352315205 ps
CPU time 198.9 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:41:30 PM PST 23
Peak memory 182860 kb
Host smart-27a28bbb-4c40-4e78-b7cd-623537dbe780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479997401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3479997401
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3818842451
Short name T177
Test name
Test status
Simulation time 38850346172 ps
CPU time 64.12 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:39:15 PM PST 23
Peak memory 191024 kb
Host smart-79be00a6-9ded-4718-9800-2d03254cee59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818842451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3818842451
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3597365151
Short name T603
Test name
Test status
Simulation time 101551019948 ps
CPU time 414.04 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 12:45:12 PM PST 23
Peak memory 191056 kb
Host smart-228a7ae5-4520-4134-a75a-2590a9ec7b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597365151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3597365151
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.693896177
Short name T258
Test name
Test status
Simulation time 465241978693 ps
CPU time 447.15 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:45:38 PM PST 23
Peak memory 191040 kb
Host smart-86d4da99-0c10-4e1a-a097-82b1ca1e85f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693896177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
693896177
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.1899011570
Short name T554
Test name
Test status
Simulation time 139723580223 ps
CPU time 695.54 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:49:49 PM PST 23
Peak memory 197552 kb
Host smart-cfe689bb-5884-4511-bc16-c8d5228f3777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899011570 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.1899011570
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3552157223
Short name T577
Test name
Test status
Simulation time 701560768805 ps
CPU time 308.41 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:43:21 PM PST 23
Peak memory 182868 kb
Host smart-958d2581-9d5f-49a8-856e-799f2debe42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552157223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3552157223
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.464517734
Short name T589
Test name
Test status
Simulation time 852384218 ps
CPU time 1.85 seconds
Started Dec 24 12:38:27 PM PST 23
Finished Dec 24 12:38:31 PM PST 23
Peak memory 182568 kb
Host smart-5c4ceb26-3b58-4531-adcb-0aedd82f5b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464517734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.464517734
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3648787784
Short name T173
Test name
Test status
Simulation time 164965847370 ps
CPU time 630.51 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:48:42 PM PST 23
Peak memory 195712 kb
Host smart-cf69e141-72c9-4109-9d90-1950e526d625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648787784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3648787784
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.198084525
Short name T329
Test name
Test status
Simulation time 107916669172 ps
CPU time 667.62 seconds
Started Dec 24 12:38:34 PM PST 23
Finished Dec 24 12:49:44 PM PST 23
Peak memory 197516 kb
Host smart-57ce80f0-52b7-4c08-acf4-1e4794a42594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198084525 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.198084525
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2408214690
Short name T564
Test name
Test status
Simulation time 200237039219 ps
CPU time 218.41 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:41:51 PM PST 23
Peak memory 183036 kb
Host smart-a56367e8-647c-4c4d-b116-7332abd033f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408214690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2408214690
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2815232201
Short name T523
Test name
Test status
Simulation time 49030025674 ps
CPU time 32.91 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:38:46 PM PST 23
Peak memory 182828 kb
Host smart-ae086869-3255-4eef-ac3d-e9b42a4609ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815232201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2815232201
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3837982396
Short name T612
Test name
Test status
Simulation time 238147953994 ps
CPU time 89.99 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:39:42 PM PST 23
Peak memory 182956 kb
Host smart-31427906-e58d-466e-9216-a3288b203d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837982396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3837982396
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2983698152
Short name T601
Test name
Test status
Simulation time 90206350077 ps
CPU time 52.06 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:39:19 PM PST 23
Peak memory 182804 kb
Host smart-cf885394-df2f-4eb7-b400-2b308baf86b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983698152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2983698152
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3420083885
Short name T292
Test name
Test status
Simulation time 640939565968 ps
CPU time 546.02 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 12:47:24 PM PST 23
Peak memory 191048 kb
Host smart-81df4f29-0e5a-4931-bdd8-84d0aac743fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420083885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3420083885
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2431558076
Short name T605
Test name
Test status
Simulation time 109636716784 ps
CPU time 616.3 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:48:27 PM PST 23
Peak memory 205948 kb
Host smart-3041687f-b5ba-4eba-aef7-6da54ca25c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431558076 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2431558076
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2699185871
Short name T160
Test name
Test status
Simulation time 124127208001 ps
CPU time 193.03 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 12:41:31 PM PST 23
Peak memory 182764 kb
Host smart-1378c0a4-6aec-479e-9468-92785a269a7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699185871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2699185871
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.130790022
Short name T515
Test name
Test status
Simulation time 58864025027 ps
CPU time 89.03 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:39:41 PM PST 23
Peak memory 182844 kb
Host smart-53e0da38-4680-43c7-aa34-56f068537bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130790022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.130790022
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2080887130
Short name T231
Test name
Test status
Simulation time 351846638007 ps
CPU time 290.97 seconds
Started Dec 24 12:38:20 PM PST 23
Finished Dec 24 12:43:13 PM PST 23
Peak memory 195600 kb
Host smart-586c3c10-196b-4832-bd05-5daf4bd76429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080887130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2080887130
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2901412114
Short name T129
Test name
Test status
Simulation time 111496269422 ps
CPU time 464.28 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 12:46:16 PM PST 23
Peak memory 210672 kb
Host smart-2fb12cd2-a438-4905-a204-eabf154dab7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901412114 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2901412114
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1100616926
Short name T295
Test name
Test status
Simulation time 113527909740 ps
CPU time 218.4 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:41:51 PM PST 23
Peak memory 182784 kb
Host smart-25dd928d-6282-4070-b3dc-04da62c6658f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100616926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1100616926
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.4050482218
Short name T548
Test name
Test status
Simulation time 535840699144 ps
CPU time 188.46 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:41:23 PM PST 23
Peak memory 182928 kb
Host smart-c4547125-844c-46ce-b3c7-628e4e9accc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050482218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4050482218
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1981391963
Short name T598
Test name
Test status
Simulation time 11844172770 ps
CPU time 18.16 seconds
Started Dec 24 12:38:18 PM PST 23
Finished Dec 24 12:38:38 PM PST 23
Peak memory 182972 kb
Host smart-17b5aeda-4c5d-4f9f-8360-9c40f5d18e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981391963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1981391963
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1205746393
Short name T25
Test name
Test status
Simulation time 102643011172 ps
CPU time 54.97 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:39:09 PM PST 23
Peak memory 182804 kb
Host smart-632b4d9e-6a6a-4ceb-a378-e481f93afb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205746393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1205746393
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3487978869
Short name T229
Test name
Test status
Simulation time 358667264952 ps
CPU time 760.24 seconds
Started Dec 24 12:38:20 PM PST 23
Finished Dec 24 12:51:02 PM PST 23
Peak memory 205852 kb
Host smart-6094b75f-0763-4964-be37-34d4db3183b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487978869 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3487978869
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2207443040
Short name T380
Test name
Test status
Simulation time 74508564203 ps
CPU time 41.72 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:38:55 PM PST 23
Peak memory 182796 kb
Host smart-8011e371-eb46-4dcd-a72e-d9416891ca67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207443040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2207443040
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.4203851620
Short name T586
Test name
Test status
Simulation time 171893143265 ps
CPU time 266.05 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:42:40 PM PST 23
Peak memory 182792 kb
Host smart-224e96f4-813f-4871-90f8-931666c411c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203851620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.4203851620
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2681382009
Short name T608
Test name
Test status
Simulation time 17229657828 ps
CPU time 71.94 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 12:39:30 PM PST 23
Peak memory 191156 kb
Host smart-97379a88-1a8e-4552-a87c-654c604a1649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681382009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2681382009
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1990744110
Short name T546
Test name
Test status
Simulation time 56532292131 ps
CPU time 15.96 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:38:30 PM PST 23
Peak memory 182988 kb
Host smart-e01a6c62-9cb3-4b3b-9b7e-aecd849ba8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990744110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1990744110
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.807936667
Short name T616
Test name
Test status
Simulation time 116822461330 ps
CPU time 278.16 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:42:52 PM PST 23
Peak memory 205788 kb
Host smart-a7f4f26a-a4ae-4f58-9562-3898e7cb2153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807936667 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.807936667
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2659277214
Short name T203
Test name
Test status
Simulation time 3357968889941 ps
CPU time 1416.1 seconds
Started Dec 24 12:38:15 PM PST 23
Finished Dec 24 01:01:55 PM PST 23
Peak memory 182760 kb
Host smart-3281d484-ed48-4fb7-af03-431c8a67b77f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659277214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2659277214
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3043364200
Short name T565
Test name
Test status
Simulation time 13586331134 ps
CPU time 10.22 seconds
Started Dec 24 12:38:16 PM PST 23
Finished Dec 24 12:38:29 PM PST 23
Peak memory 182872 kb
Host smart-c6bcc43b-9810-4505-966b-7ba4cd0c9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043364200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3043364200
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.4152780544
Short name T98
Test name
Test status
Simulation time 1289486994239 ps
CPU time 918.7 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:53:29 PM PST 23
Peak memory 193320 kb
Host smart-adb5a123-76dd-49f3-a4fd-27ebbdc5042d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152780544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4152780544
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1156253590
Short name T375
Test name
Test status
Simulation time 244247153744 ps
CPU time 87.46 seconds
Started Dec 24 12:38:18 PM PST 23
Finished Dec 24 12:39:47 PM PST 23
Peak memory 182936 kb
Host smart-84a4ddca-a534-4bd7-9b96-76c6cfe5ded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156253590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1156253590
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3986843957
Short name T551
Test name
Test status
Simulation time 846055514610 ps
CPU time 489.8 seconds
Started Dec 24 12:38:13 PM PST 23
Finished Dec 24 12:46:25 PM PST 23
Peak memory 191144 kb
Host smart-8a971c86-1685-4eff-ad82-4892d13a3414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986843957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3986843957
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4198560049
Short name T265
Test name
Test status
Simulation time 94774356611 ps
CPU time 163.32 seconds
Started Dec 24 12:38:14 PM PST 23
Finished Dec 24 12:41:00 PM PST 23
Peak memory 182824 kb
Host smart-84043336-2f55-4c77-8cb1-abecda2e4189
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198560049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4198560049
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2276834801
Short name T593
Test name
Test status
Simulation time 295995058086 ps
CPU time 128.11 seconds
Started Dec 24 12:38:07 PM PST 23
Finished Dec 24 12:40:18 PM PST 23
Peak memory 182828 kb
Host smart-b0877c43-b751-4804-bd3c-c1719f3de655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276834801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2276834801
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2245291401
Short name T579
Test name
Test status
Simulation time 244096193 ps
CPU time 0.65 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:38:13 PM PST 23
Peak memory 182588 kb
Host smart-b2dab253-0cca-4ce7-aea3-7fff9dcc20ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245291401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2245291401
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.95802716
Short name T562
Test name
Test status
Simulation time 709307550543 ps
CPU time 1175.5 seconds
Started Dec 24 12:38:13 PM PST 23
Finished Dec 24 12:57:51 PM PST 23
Peak memory 211632 kb
Host smart-25a5a5f2-575b-47db-b106-6d254402accc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95802716 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.95802716
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.343568093
Short name T237
Test name
Test status
Simulation time 1947873312757 ps
CPU time 1119.3 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:56:54 PM PST 23
Peak memory 182784 kb
Host smart-988357db-f4d2-4c93-8455-b4697350fcf0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343568093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.343568093
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.437085455
Short name T381
Test name
Test status
Simulation time 727576814561 ps
CPU time 160.86 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:40:55 PM PST 23
Peak memory 182984 kb
Host smart-0272b1af-fcfc-459d-8259-efbb2891b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437085455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.437085455
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3667943999
Short name T343
Test name
Test status
Simulation time 399604334066 ps
CPU time 980.98 seconds
Started Dec 24 12:38:39 PM PST 23
Finished Dec 24 12:55:11 PM PST 23
Peak memory 191040 kb
Host smart-3880abbb-f9f5-4df5-9055-768f80106fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667943999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3667943999
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3119244946
Short name T135
Test name
Test status
Simulation time 361279556962 ps
CPU time 241.93 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:42:17 PM PST 23
Peak memory 191024 kb
Host smart-aec3f98c-33ab-4bd0-9de9-930c33393bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119244946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3119244946
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3731549302
Short name T535
Test name
Test status
Simulation time 76291933608 ps
CPU time 201.85 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:41:49 PM PST 23
Peak memory 205744 kb
Host smart-0c0c494c-1890-476e-9c29-e0f8726723ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731549302 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3731549302
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1606776894
Short name T521
Test name
Test status
Simulation time 1231558554717 ps
CPU time 722.17 seconds
Started Dec 24 12:37:45 PM PST 23
Finished Dec 24 12:49:51 PM PST 23
Peak memory 182936 kb
Host smart-138a6580-36d6-4625-a529-805cd436eea3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606776894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1606776894
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.220720848
Short name T508
Test name
Test status
Simulation time 10452529240 ps
CPU time 16.48 seconds
Started Dec 24 12:37:50 PM PST 23
Finished Dec 24 12:38:10 PM PST 23
Peak memory 182752 kb
Host smart-947926a8-b4b2-418a-9e2e-4053f21a0f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220720848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.220720848
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2707742297
Short name T208
Test name
Test status
Simulation time 209439333659 ps
CPU time 110.63 seconds
Started Dec 24 12:38:08 PM PST 23
Finished Dec 24 12:40:01 PM PST 23
Peak memory 182792 kb
Host smart-ffb81304-4111-4679-a9e6-3fee47171ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707742297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2707742297
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2372831030
Short name T17
Test name
Test status
Simulation time 338046880 ps
CPU time 0.89 seconds
Started Dec 24 12:37:43 PM PST 23
Finished Dec 24 12:37:48 PM PST 23
Peak memory 212872 kb
Host smart-24e8b2d3-7221-4816-b0af-c77670b0fe88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372831030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2372831030
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.565175914
Short name T196
Test name
Test status
Simulation time 13206732148 ps
CPU time 12.03 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:38:26 PM PST 23
Peak memory 182928 kb
Host smart-89364606-aefd-4e05-9a6b-f79a9ae91d75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565175914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.565175914
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1858730945
Short name T570
Test name
Test status
Simulation time 247474714066 ps
CPU time 195.14 seconds
Started Dec 24 12:38:27 PM PST 23
Finished Dec 24 12:41:44 PM PST 23
Peak memory 182812 kb
Host smart-4bbdd175-8dc1-4e30-920f-98c037967b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858730945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1858730945
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1522399185
Short name T595
Test name
Test status
Simulation time 46697275384 ps
CPU time 82.47 seconds
Started Dec 24 12:38:09 PM PST 23
Finished Dec 24 12:39:34 PM PST 23
Peak memory 191176 kb
Host smart-587f46e7-9839-4a8a-a291-8d117531eb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522399185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1522399185
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.751879186
Short name T125
Test name
Test status
Simulation time 42208481808 ps
CPU time 25.38 seconds
Started Dec 24 12:38:33 PM PST 23
Finished Dec 24 12:39:00 PM PST 23
Peak memory 191016 kb
Host smart-871846b9-d017-4f3c-a8e5-bfbe1e193401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751879186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.751879186
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.681069832
Short name T77
Test name
Test status
Simulation time 2390823580611 ps
CPU time 1804.83 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 01:08:37 PM PST 23
Peak memory 213732 kb
Host smart-db66977d-1210-44a2-a53d-718ce78aeb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681069832 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.681069832
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1496134696
Short name T259
Test name
Test status
Simulation time 515406223252 ps
CPU time 247.47 seconds
Started Dec 24 12:38:14 PM PST 23
Finished Dec 24 12:42:24 PM PST 23
Peak memory 182888 kb
Host smart-5ee4bc09-e3e1-4e2c-81e7-5a65c67f8dbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496134696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1496134696
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1443480997
Short name T587
Test name
Test status
Simulation time 203603897991 ps
CPU time 154.08 seconds
Started Dec 24 12:38:34 PM PST 23
Finished Dec 24 12:41:10 PM PST 23
Peak memory 182920 kb
Host smart-ebd190e1-c4ee-4037-be61-71fa42f474b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443480997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1443480997
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3744639685
Short name T363
Test name
Test status
Simulation time 141950310803 ps
CPU time 83.6 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:39:38 PM PST 23
Peak memory 191004 kb
Host smart-25101a2f-3f2d-48a9-adb9-20ffa2d2b6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744639685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3744639685
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3058349058
Short name T170
Test name
Test status
Simulation time 3312602482866 ps
CPU time 3988.08 seconds
Started Dec 24 12:38:13 PM PST 23
Finished Dec 24 01:44:44 PM PST 23
Peak memory 190924 kb
Host smart-befc564a-1c1a-4ac1-b59f-4f3698083808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058349058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3058349058
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2949260582
Short name T168
Test name
Test status
Simulation time 72797169531 ps
CPU time 609.42 seconds
Started Dec 24 12:38:24 PM PST 23
Finished Dec 24 12:48:35 PM PST 23
Peak memory 205864 kb
Host smart-3e081daf-e138-43a1-b1e5-3156829ae097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949260582 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2949260582
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2791973226
Short name T263
Test name
Test status
Simulation time 304510200800 ps
CPU time 478.1 seconds
Started Dec 24 12:38:11 PM PST 23
Finished Dec 24 12:46:11 PM PST 23
Peak memory 182940 kb
Host smart-47190c87-9064-4a91-9f24-c07ea9d7fdb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791973226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2791973226
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2608039070
Short name T566
Test name
Test status
Simulation time 19596229393 ps
CPU time 33.87 seconds
Started Dec 24 12:38:10 PM PST 23
Finished Dec 24 12:38:46 PM PST 23
Peak memory 182968 kb
Host smart-fcd93a06-3342-43d0-b437-f3d8114b4992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608039070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2608039070
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1693865384
Short name T131
Test name
Test status
Simulation time 1417814116 ps
CPU time 1.24 seconds
Started Dec 24 12:38:12 PM PST 23
Finished Dec 24 12:38:15 PM PST 23
Peak memory 182560 kb
Host smart-57e46015-2cd0-4162-8580-264ea6c8cce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693865384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1693865384
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.644331222
Short name T357
Test name
Test status
Simulation time 68867121691 ps
CPU time 69.77 seconds
Started Dec 24 12:38:28 PM PST 23
Finished Dec 24 12:39:39 PM PST 23
Peak memory 182836 kb
Host smart-03400434-17c7-447e-b09b-a16818aabe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644331222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.644331222
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2511814572
Short name T276
Test name
Test status
Simulation time 290128629167 ps
CPU time 414.56 seconds
Started Dec 24 12:38:34 PM PST 23
Finished Dec 24 12:45:31 PM PST 23
Peak memory 191144 kb
Host smart-7ecfc08f-86f4-4f6f-ab56-6a2e7c9d6e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511814572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2511814572
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2575333353
Short name T606
Test name
Test status
Simulation time 32917185560 ps
CPU time 595.61 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 12:48:27 PM PST 23
Peak memory 205868 kb
Host smart-aea86f0e-01f8-42d9-8ac8-2c6485ec0e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575333353 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2575333353
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1820389847
Short name T270
Test name
Test status
Simulation time 9229092153 ps
CPU time 16.64 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 12:38:49 PM PST 23
Peak memory 182892 kb
Host smart-995d4af1-8874-46b8-99c1-d46c30724a77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820389847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1820389847
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1455459873
Short name T573
Test name
Test status
Simulation time 170186900483 ps
CPU time 148.65 seconds
Started Dec 24 12:38:36 PM PST 23
Finished Dec 24 12:41:08 PM PST 23
Peak memory 182952 kb
Host smart-df3a8bf9-02e1-4aea-8a0f-c54b9fa30bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455459873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1455459873
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2421638290
Short name T334
Test name
Test status
Simulation time 325135156627 ps
CPU time 175.36 seconds
Started Dec 24 12:38:30 PM PST 23
Finished Dec 24 12:41:27 PM PST 23
Peak memory 191156 kb
Host smart-5451875d-62a7-4944-a130-5d56c56e187f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421638290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2421638290
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2439403632
Short name T289
Test name
Test status
Simulation time 169843004987 ps
CPU time 142.06 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:40:56 PM PST 23
Peak memory 191060 kb
Host smart-9eccdb6d-d458-47a2-a00d-fedf1fd3d1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439403632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2439403632
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1753158842
Short name T32
Test name
Test status
Simulation time 27573253748 ps
CPU time 126.13 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:40:40 PM PST 23
Peak memory 197560 kb
Host smart-7369b598-7c26-4d67-80ca-7886cc7c92a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753158842 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1753158842
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1972414380
Short name T594
Test name
Test status
Simulation time 518314536767 ps
CPU time 306.53 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 12:43:39 PM PST 23
Peak memory 182956 kb
Host smart-b70f545e-12bb-4925-9c0f-63fcb1b9a894
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972414380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1972414380
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.166433714
Short name T519
Test name
Test status
Simulation time 691577342201 ps
CPU time 247.78 seconds
Started Dec 24 12:38:44 PM PST 23
Finished Dec 24 12:43:05 PM PST 23
Peak memory 182820 kb
Host smart-b17c17d8-dacd-4a76-a57c-5837505c3fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166433714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.166433714
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.955729832
Short name T273
Test name
Test status
Simulation time 57996811868 ps
CPU time 97.66 seconds
Started Dec 24 12:38:37 PM PST 23
Finished Dec 24 12:40:21 PM PST 23
Peak memory 191060 kb
Host smart-8b2105e2-6ea7-4e8c-aeb1-6e0f0fcabf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955729832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.955729832
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2961882312
Short name T87
Test name
Test status
Simulation time 97524391614 ps
CPU time 1425.64 seconds
Started Dec 24 12:38:30 PM PST 23
Finished Dec 24 01:02:17 PM PST 23
Peak memory 183164 kb
Host smart-5ff9db42-9e0d-420f-b9b6-48433d7e4e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961882312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2961882312
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2554998386
Short name T230
Test name
Test status
Simulation time 65118094933 ps
CPU time 435.62 seconds
Started Dec 24 12:38:39 PM PST 23
Finished Dec 24 12:46:07 PM PST 23
Peak memory 197612 kb
Host smart-746bd0eb-b355-4973-abab-3ab59d2636e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554998386 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2554998386
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3512158872
Short name T10
Test name
Test status
Simulation time 4404877181 ps
CPU time 4.51 seconds
Started Dec 24 12:38:38 PM PST 23
Finished Dec 24 12:38:53 PM PST 23
Peak memory 182816 kb
Host smart-de561367-a828-4807-a88d-5078e7132d7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512158872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3512158872
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2059554221
Short name T512
Test name
Test status
Simulation time 191522224689 ps
CPU time 148.76 seconds
Started Dec 24 12:38:26 PM PST 23
Finished Dec 24 12:40:57 PM PST 23
Peak memory 182864 kb
Host smart-e419608a-0740-45bc-9e89-fe4697cf86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059554221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2059554221
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3555448189
Short name T607
Test name
Test status
Simulation time 164562413722 ps
CPU time 274.93 seconds
Started Dec 24 12:38:47 PM PST 23
Finished Dec 24 12:43:32 PM PST 23
Peak memory 191120 kb
Host smart-22637a55-c30f-40ec-a163-10662c0c43ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555448189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3555448189
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2289174392
Short name T574
Test name
Test status
Simulation time 2522043937 ps
CPU time 15.91 seconds
Started Dec 24 12:38:29 PM PST 23
Finished Dec 24 12:38:47 PM PST 23
Peak memory 193220 kb
Host smart-0694b518-309a-4992-8fa7-0175cdd1d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289174392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2289174392
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3725793981
Short name T185
Test name
Test status
Simulation time 179166200325 ps
CPU time 652.3 seconds
Started Dec 24 12:38:33 PM PST 23
Finished Dec 24 12:49:27 PM PST 23
Peak memory 210948 kb
Host smart-59a11efc-a30e-4451-ad6e-6e9964ccb359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725793981 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3725793981
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.516730992
Short name T355
Test name
Test status
Simulation time 299145459362 ps
CPU time 261.69 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:42:48 PM PST 23
Peak memory 182792 kb
Host smart-e623b681-0adf-4497-90d1-21414b3d98b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516730992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.516730992
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.4253785198
Short name T524
Test name
Test status
Simulation time 10237051512 ps
CPU time 16.21 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:38:44 PM PST 23
Peak memory 182868 kb
Host smart-5cdbb3b3-c15e-4ea9-bdfb-94c41b9da6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253785198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.4253785198
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.398539341
Short name T373
Test name
Test status
Simulation time 601450617061 ps
CPU time 314.74 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:43:43 PM PST 23
Peak memory 191048 kb
Host smart-0be33210-6b6f-41fb-bede-392140c04e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398539341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.398539341
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3314593509
Short name T5
Test name
Test status
Simulation time 982010495294 ps
CPU time 384.82 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:44:53 PM PST 23
Peak memory 193704 kb
Host smart-17e0ccc0-2f62-4eeb-bbc8-b494f1371e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314593509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3314593509
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.72265515
Short name T584
Test name
Test status
Simulation time 232217628185 ps
CPU time 962.19 seconds
Started Dec 24 12:38:38 PM PST 23
Finished Dec 24 12:54:51 PM PST 23
Peak memory 209432 kb
Host smart-b96fc241-91e7-4f8a-9466-c3b7c53bfb4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72265515 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.72265515
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3570603866
Short name T182
Test name
Test status
Simulation time 65158183013 ps
CPU time 106.05 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:40:20 PM PST 23
Peak memory 182900 kb
Host smart-952ea4f7-f1e2-4346-8d88-176804f14cee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570603866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3570603866
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.154635447
Short name T602
Test name
Test status
Simulation time 418398733226 ps
CPU time 173.31 seconds
Started Dec 24 12:38:27 PM PST 23
Finished Dec 24 12:41:22 PM PST 23
Peak memory 182868 kb
Host smart-d9f0ab6a-41fc-4336-aef4-898160cd39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154635447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.154635447
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3343682238
Short name T89
Test name
Test status
Simulation time 9130434985 ps
CPU time 16.67 seconds
Started Dec 24 12:38:25 PM PST 23
Finished Dec 24 12:38:44 PM PST 23
Peak memory 182804 kb
Host smart-7870b14e-0372-4c68-8c7b-dbb881bc9b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343682238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3343682238
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1731479308
Short name T529
Test name
Test status
Simulation time 28442711404 ps
CPU time 52.08 seconds
Started Dec 24 12:38:49 PM PST 23
Finished Dec 24 12:39:51 PM PST 23
Peak memory 182804 kb
Host smart-4d41be10-7473-4687-a36d-0f1d6e3ce5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731479308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1731479308
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.4255201932
Short name T78
Test name
Test status
Simulation time 263543539046 ps
CPU time 778.65 seconds
Started Dec 24 12:38:26 PM PST 23
Finished Dec 24 12:51:27 PM PST 23
Peak memory 208144 kb
Host smart-f0184a1f-e082-4411-84e4-51e54ab3208d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255201932 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.4255201932
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1471553382
Short name T142
Test name
Test status
Simulation time 219808114183 ps
CPU time 128.42 seconds
Started Dec 24 12:38:38 PM PST 23
Finished Dec 24 12:40:57 PM PST 23
Peak memory 182792 kb
Host smart-a44be2c5-7449-41be-84ef-f77bc6c0db8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471553382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1471553382
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.722078900
Short name T618
Test name
Test status
Simulation time 196746892239 ps
CPU time 85.38 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:39:58 PM PST 23
Peak memory 182952 kb
Host smart-3b3a7908-2091-4598-be6d-6beb8b3f2701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722078900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.722078900
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1412604976
Short name T532
Test name
Test status
Simulation time 11050628119 ps
CPU time 19.17 seconds
Started Dec 24 12:38:27 PM PST 23
Finished Dec 24 12:38:48 PM PST 23
Peak memory 182832 kb
Host smart-b7d19351-f63e-46a4-9ea6-17bc091ea7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412604976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1412604976
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.701652375
Short name T115
Test name
Test status
Simulation time 316898013877 ps
CPU time 478.93 seconds
Started Dec 24 12:38:39 PM PST 23
Finished Dec 24 12:46:51 PM PST 23
Peak memory 191148 kb
Host smart-4e5c1640-eb82-49b9-aaf7-a45dc947f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701652375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.701652375
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2414765298
Short name T509
Test name
Test status
Simulation time 3149827003366 ps
CPU time 796.48 seconds
Started Dec 24 12:38:32 PM PST 23
Finished Dec 24 12:51:50 PM PST 23
Peak memory 191056 kb
Host smart-de3dad13-7218-41d1-a279-e7881e98b79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414765298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2414765298
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1482275061
Short name T569
Test name
Test status
Simulation time 97864272157 ps
CPU time 498.01 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 12:47:15 PM PST 23
Peak memory 197620 kb
Host smart-0d4abc80-3368-4fcc-af9b-0da3178c9fda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482275061 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1482275061
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.747495910
Short name T495
Test name
Test status
Simulation time 134753516456 ps
CPU time 231.76 seconds
Started Dec 24 12:38:30 PM PST 23
Finished Dec 24 12:42:23 PM PST 23
Peak memory 183152 kb
Host smart-2fdb8130-0e22-4803-93b4-b19e8c3de5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747495910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.747495910
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1929353598
Short name T233
Test name
Test status
Simulation time 124838849860 ps
CPU time 69.34 seconds
Started Dec 24 12:38:29 PM PST 23
Finished Dec 24 12:39:40 PM PST 23
Peak memory 191020 kb
Host smart-25f0ce19-8d1d-41a9-8b16-28d90fa07899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929353598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1929353598
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1021822145
Short name T280
Test name
Test status
Simulation time 139099334694 ps
CPU time 65.67 seconds
Started Dec 24 12:38:31 PM PST 23
Finished Dec 24 12:39:37 PM PST 23
Peak memory 183000 kb
Host smart-dfc30a4b-448b-4aa8-9b95-80f7deb63d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021822145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1021822145
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3884306760
Short name T563
Test name
Test status
Simulation time 704586459594 ps
CPU time 868.84 seconds
Started Dec 24 12:38:45 PM PST 23
Finished Dec 24 12:53:26 PM PST 23
Peak memory 209760 kb
Host smart-fd6a308c-a24b-48e0-9c6a-ac73548cd429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884306760 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3884306760
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1812844060
Short name T167
Test name
Test status
Simulation time 88704083769 ps
CPU time 149.28 seconds
Started Dec 24 12:37:46 PM PST 23
Finished Dec 24 12:40:18 PM PST 23
Peak memory 182828 kb
Host smart-2e617230-534e-4734-b20a-c5ab39083e5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812844060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1812844060
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3066779992
Short name T530
Test name
Test status
Simulation time 905838249758 ps
CPU time 163.18 seconds
Started Dec 24 12:37:40 PM PST 23
Finished Dec 24 12:40:30 PM PST 23
Peak memory 182792 kb
Host smart-48dcb69b-1506-4510-8457-fb9d0c67978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066779992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3066779992
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1443645630
Short name T242
Test name
Test status
Simulation time 218696172215 ps
CPU time 180.06 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:40:57 PM PST 23
Peak memory 182760 kb
Host smart-378a5012-19a4-4fcb-8af3-8ac00a221b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443645630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1443645630
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3493351356
Short name T369
Test name
Test status
Simulation time 655923437179 ps
CPU time 385.05 seconds
Started Dec 24 12:38:03 PM PST 23
Finished Dec 24 12:44:30 PM PST 23
Peak memory 191052 kb
Host smart-bd7a2038-cf43-4e2b-96c1-661d051bd1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493351356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3493351356
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.13961893
Short name T506
Test name
Test status
Simulation time 168455422953 ps
CPU time 292.43 seconds
Started Dec 24 12:37:59 PM PST 23
Finished Dec 24 12:42:55 PM PST 23
Peak memory 205832 kb
Host smart-120df0e5-2fb1-4eb2-8e01-fa58509f55ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961893 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.13961893
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4237373812
Short name T372
Test name
Test status
Simulation time 8360681477 ps
CPU time 5.09 seconds
Started Dec 24 12:38:37 PM PST 23
Finished Dec 24 12:38:48 PM PST 23
Peak memory 182900 kb
Host smart-35ad9c0e-e10c-41fc-ae47-257bcd42d148
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237373812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4237373812
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2113240535
Short name T517
Test name
Test status
Simulation time 295694898824 ps
CPU time 108.44 seconds
Started Dec 24 12:38:37 PM PST 23
Finished Dec 24 12:40:28 PM PST 23
Peak memory 182972 kb
Host smart-946a485f-d5df-4892-877b-a494ca7d81e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113240535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2113240535
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2484558535
Short name T217
Test name
Test status
Simulation time 43986953850 ps
CPU time 195.45 seconds
Started Dec 24 12:38:37 PM PST 23
Finished Dec 24 12:41:59 PM PST 23
Peak memory 191132 kb
Host smart-a89e7ee9-5deb-43cb-9c26-66cbdbdd0990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484558535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2484558535
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2386749794
Short name T516
Test name
Test status
Simulation time 859895162 ps
CPU time 0.74 seconds
Started Dec 24 12:38:27 PM PST 23
Finished Dec 24 12:38:30 PM PST 23
Peak memory 182684 kb
Host smart-64087604-98b6-4c43-aa76-2718c196e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386749794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2386749794
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.820014755
Short name T500
Test name
Test status
Simulation time 20841898 ps
CPU time 0.52 seconds
Started Dec 24 12:38:28 PM PST 23
Finished Dec 24 12:38:30 PM PST 23
Peak memory 182168 kb
Host smart-4779a62c-ccef-463d-b964-35055b563edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820014755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
820014755
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3413954072
Short name T104
Test name
Test status
Simulation time 255554761193 ps
CPU time 449.72 seconds
Started Dec 24 12:38:39 PM PST 23
Finished Dec 24 12:46:21 PM PST 23
Peak memory 207560 kb
Host smart-8e61a7d3-132d-4aff-b524-15d237f74216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413954072 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3413954072
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1429267584
Short name T590
Test name
Test status
Simulation time 240070688091 ps
CPU time 106.64 seconds
Started Dec 24 12:38:28 PM PST 23
Finished Dec 24 12:40:17 PM PST 23
Peak memory 182988 kb
Host smart-8ed5e07d-4930-4182-87c4-446428ee1b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429267584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1429267584
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2615683240
Short name T140
Test name
Test status
Simulation time 146397349770 ps
CPU time 310.21 seconds
Started Dec 24 12:38:28 PM PST 23
Finished Dec 24 12:43:40 PM PST 23
Peak memory 191172 kb
Host smart-109d6e81-9016-4dd9-926a-81be22892912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615683240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2615683240
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1888100317
Short name T583
Test name
Test status
Simulation time 211934586 ps
CPU time 0.56 seconds
Started Dec 24 12:38:28 PM PST 23
Finished Dec 24 12:38:30 PM PST 23
Peak memory 182684 kb
Host smart-1bed4173-2dd4-416e-8ac4-bc20bc36912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888100317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1888100317
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3517880263
Short name T52
Test name
Test status
Simulation time 142197875724 ps
CPU time 195.01 seconds
Started Dec 24 12:38:30 PM PST 23
Finished Dec 24 12:41:46 PM PST 23
Peak memory 182888 kb
Host smart-f85b3cda-ecef-4321-9af1-f67c5dad4344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517880263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3517880263
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1772318459
Short name T539
Test name
Test status
Simulation time 401324647884 ps
CPU time 981.49 seconds
Started Dec 24 12:38:36 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 211444 kb
Host smart-d5a538ab-a650-4087-a779-e924ba220906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772318459 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1772318459
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2246338890
Short name T283
Test name
Test status
Simulation time 620728332832 ps
CPU time 340.57 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 12:44:45 PM PST 23
Peak memory 182800 kb
Host smart-3e313c86-2ce9-4ea5-b54d-da995b51e62f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246338890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2246338890
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3840782537
Short name T518
Test name
Test status
Simulation time 47347450467 ps
CPU time 66.98 seconds
Started Dec 24 12:38:55 PM PST 23
Finished Dec 24 12:40:12 PM PST 23
Peak memory 182848 kb
Host smart-79cbc932-83bf-4e27-a6a4-b3fcd1f2d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840782537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3840782537
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4229859300
Short name T338
Test name
Test status
Simulation time 16701934350 ps
CPU time 30.62 seconds
Started Dec 24 12:38:44 PM PST 23
Finished Dec 24 12:39:28 PM PST 23
Peak memory 182940 kb
Host smart-2ad7bdcf-c7ee-449c-b7c4-00c6d3ef566e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229859300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4229859300
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.563273159
Short name T580
Test name
Test status
Simulation time 87883813135 ps
CPU time 434.16 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 12:46:11 PM PST 23
Peak memory 194612 kb
Host smart-b88a5b0a-0daf-446a-b15c-394834e6ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563273159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.563273159
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1187000484
Short name T537
Test name
Test status
Simulation time 95728753318 ps
CPU time 39.28 seconds
Started Dec 24 12:38:51 PM PST 23
Finished Dec 24 12:39:41 PM PST 23
Peak memory 182828 kb
Host smart-98e994ec-7aa6-4966-9019-926bad732eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187000484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1187000484
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3568517798
Short name T527
Test name
Test status
Simulation time 1106058729307 ps
CPU time 1225.61 seconds
Started Dec 24 12:38:40 PM PST 23
Finished Dec 24 12:59:19 PM PST 23
Peak memory 213936 kb
Host smart-3ce7e349-e5db-4135-b20e-8637d9549bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568517798 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3568517798
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2717393227
Short name T220
Test name
Test status
Simulation time 148760491106 ps
CPU time 157.09 seconds
Started Dec 24 12:38:40 PM PST 23
Finished Dec 24 12:41:32 PM PST 23
Peak memory 182944 kb
Host smart-d4c8f568-41fc-44b4-9ff2-a7d2b8a75f9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717393227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2717393227
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.51433032
Short name T223
Test name
Test status
Simulation time 477179247368 ps
CPU time 234.73 seconds
Started Dec 24 12:38:50 PM PST 23
Finished Dec 24 12:42:56 PM PST 23
Peak memory 193356 kb
Host smart-b0c2bcaf-d84e-4b35-b5d8-7d66d5fd1c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51433032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.51433032
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2976535493
Short name T189
Test name
Test status
Simulation time 319865621691 ps
CPU time 1348.54 seconds
Started Dec 24 12:38:40 PM PST 23
Finished Dec 24 01:01:26 PM PST 23
Peak memory 191032 kb
Host smart-8498168d-95a4-4828-a14f-f454b4b66c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976535493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2976535493
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.466665258
Short name T118
Test name
Test status
Simulation time 219819009497 ps
CPU time 369.37 seconds
Started Dec 24 12:38:56 PM PST 23
Finished Dec 24 12:45:15 PM PST 23
Peak memory 182788 kb
Host smart-73b6c191-5807-43a7-a6a4-390bd823ad2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466665258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
466665258
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.4253340951
Short name T186
Test name
Test status
Simulation time 170512432133 ps
CPU time 1281.39 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 01:00:26 PM PST 23
Peak memory 207764 kb
Host smart-87644b19-8c3b-41d6-b114-1239c6d0f638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253340951 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.4253340951
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2811638623
Short name T561
Test name
Test status
Simulation time 96857228367 ps
CPU time 98.97 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:40:44 PM PST 23
Peak memory 182792 kb
Host smart-2e94d9a2-87fe-4e4d-b956-e419a0a8bbe7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811638623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2811638623
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2734262613
Short name T531
Test name
Test status
Simulation time 732550785047 ps
CPU time 259.11 seconds
Started Dec 24 12:38:55 PM PST 23
Finished Dec 24 12:43:25 PM PST 23
Peak memory 182820 kb
Host smart-690fe544-f3b4-4405-a5f6-363c9dbc4c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734262613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2734262613
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1435173281
Short name T100
Test name
Test status
Simulation time 898787388804 ps
CPU time 193 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 12:42:17 PM PST 23
Peak memory 191076 kb
Host smart-5dddd6c4-3bbe-4214-b2a3-824300381be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435173281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1435173281
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1924704919
Short name T238
Test name
Test status
Simulation time 47032667701 ps
CPU time 66.63 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:40:12 PM PST 23
Peak memory 191076 kb
Host smart-b3411c33-af9e-458d-b3e1-d4c82443e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924704919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1924704919
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3875378506
Short name T498
Test name
Test status
Simulation time 72178579574 ps
CPU time 200.78 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:42:27 PM PST 23
Peak memory 205732 kb
Host smart-0b89df6e-45dd-4369-9e9c-db1587c9d99d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875378506 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3875378506
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1180868498
Short name T575
Test name
Test status
Simulation time 690904640140 ps
CPU time 349.37 seconds
Started Dec 24 12:38:52 PM PST 23
Finished Dec 24 12:44:52 PM PST 23
Peak memory 182780 kb
Host smart-23ed0260-ff22-4d04-9939-1dad1e1a6005
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180868498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1180868498
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2189879126
Short name T507
Test name
Test status
Simulation time 204649088011 ps
CPU time 82.58 seconds
Started Dec 24 12:38:49 PM PST 23
Finished Dec 24 12:40:22 PM PST 23
Peak memory 182772 kb
Host smart-5230517c-082b-4763-b428-c1f1ffe86f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189879126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2189879126
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2097097080
Short name T285
Test name
Test status
Simulation time 67912011208 ps
CPU time 205.07 seconds
Started Dec 24 12:38:55 PM PST 23
Finished Dec 24 12:42:30 PM PST 23
Peak memory 191164 kb
Host smart-63781275-990f-4cec-9e26-e40f049bdc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097097080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2097097080
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.547239196
Short name T553
Test name
Test status
Simulation time 65182369970 ps
CPU time 66.23 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 12:40:03 PM PST 23
Peak memory 191128 kb
Host smart-d62abbef-f2e5-4e09-a32a-474ac00643c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547239196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.547239196
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.310416991
Short name T235
Test name
Test status
Simulation time 281208389439 ps
CPU time 1003.48 seconds
Started Dec 24 12:38:37 PM PST 23
Finished Dec 24 12:55:27 PM PST 23
Peak memory 195368 kb
Host smart-764afbf1-a7de-418a-8ef5-e7cc7678477e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310416991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
310416991
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.39031849
Short name T581
Test name
Test status
Simulation time 5067086694 ps
CPU time 13.94 seconds
Started Dec 24 12:38:38 PM PST 23
Finished Dec 24 12:39:02 PM PST 23
Peak memory 197508 kb
Host smart-ba57adea-79b5-48bd-81c3-0cc2fae96ec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031849 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.39031849
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1974698931
Short name T137
Test name
Test status
Simulation time 467201194310 ps
CPU time 201.82 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 12:42:19 PM PST 23
Peak memory 182932 kb
Host smart-35e32c39-fcfd-4c31-8bf4-e1fc8eedbbaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974698931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1974698931
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1655873650
Short name T550
Test name
Test status
Simulation time 500304943625 ps
CPU time 152.92 seconds
Started Dec 24 12:38:52 PM PST 23
Finished Dec 24 12:41:36 PM PST 23
Peak memory 182824 kb
Host smart-375623e9-b085-4918-9f46-ceefda4fbafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655873650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1655873650
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1342909
Short name T302
Test name
Test status
Simulation time 181992547880 ps
CPU time 472.73 seconds
Started Dec 24 12:38:44 PM PST 23
Finished Dec 24 12:46:50 PM PST 23
Peak memory 191080 kb
Host smart-01a678cc-d852-416a-83a4-f9dfade83f5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1342909
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2072317483
Short name T496
Test name
Test status
Simulation time 235148807 ps
CPU time 0.66 seconds
Started Dec 24 12:38:40 PM PST 23
Finished Dec 24 12:38:54 PM PST 23
Peak memory 182264 kb
Host smart-fcac0f32-3456-4075-a800-987fb43f7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072317483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2072317483
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2418904684
Short name T243
Test name
Test status
Simulation time 79503332776 ps
CPU time 1227.19 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:59:33 PM PST 23
Peak memory 207148 kb
Host smart-c8b71fff-b697-4161-8c5a-6ea64d9fe385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418904684 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2418904684
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1612935334
Short name T188
Test name
Test status
Simulation time 21973276716 ps
CPU time 19.71 seconds
Started Dec 24 12:38:40 PM PST 23
Finished Dec 24 12:39:16 PM PST 23
Peak memory 182848 kb
Host smart-f7b4313e-ed1b-4ac9-b350-529016cfa235
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612935334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1612935334
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2211390041
Short name T544
Test name
Test status
Simulation time 183499532918 ps
CPU time 138.78 seconds
Started Dec 24 12:38:50 PM PST 23
Finished Dec 24 12:41:20 PM PST 23
Peak memory 182808 kb
Host smart-a6659304-e1df-426c-9fd9-e2ca40785f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211390041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2211390041
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.663680086
Short name T291
Test name
Test status
Simulation time 154162418189 ps
CPU time 227.96 seconds
Started Dec 24 12:38:55 PM PST 23
Finished Dec 24 12:42:53 PM PST 23
Peak memory 193052 kb
Host smart-2f6857e4-cfa6-47db-bcb5-15a010b9d080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663680086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.663680086
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.4036448644
Short name T497
Test name
Test status
Simulation time 817335513 ps
CPU time 1.71 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:39:07 PM PST 23
Peak memory 193304 kb
Host smart-a4addc53-ea87-4ce9-9008-0cb5e1f9b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036448644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4036448644
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.609739665
Short name T568
Test name
Test status
Simulation time 43538904660 ps
CPU time 195.29 seconds
Started Dec 24 12:38:39 PM PST 23
Finished Dec 24 12:42:06 PM PST 23
Peak memory 197548 kb
Host smart-1af98b62-c535-422c-bc31-ba45a45a7be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609739665 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.609739665
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1564589657
Short name T336
Test name
Test status
Simulation time 186773402935 ps
CPU time 180.02 seconds
Started Dec 24 12:38:42 PM PST 23
Finished Dec 24 12:41:57 PM PST 23
Peak memory 182932 kb
Host smart-64adc03d-cbca-4f73-83f2-821cad3bab25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564589657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1564589657
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3497855853
Short name T558
Test name
Test status
Simulation time 339329286059 ps
CPU time 170.75 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 12:41:48 PM PST 23
Peak memory 182988 kb
Host smart-c4801a3f-7fcf-407e-9338-f8b98bc2db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497855853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3497855853
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3141566294
Short name T174
Test name
Test status
Simulation time 129499127892 ps
CPU time 1356.11 seconds
Started Dec 24 12:38:41 PM PST 23
Finished Dec 24 01:01:33 PM PST 23
Peak memory 191000 kb
Host smart-345c0df6-85b8-4f16-8e24-56b565959d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141566294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3141566294
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.153624903
Short name T278
Test name
Test status
Simulation time 528004948131 ps
CPU time 208.04 seconds
Started Dec 24 12:38:49 PM PST 23
Finished Dec 24 12:42:27 PM PST 23
Peak memory 191040 kb
Host smart-fb6377ef-8a7f-450d-b3d7-381f52da3a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153624903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.153624903
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.994082097
Short name T90
Test name
Test status
Simulation time 25348311 ps
CPU time 0.59 seconds
Started Dec 24 12:38:51 PM PST 23
Finished Dec 24 12:39:03 PM PST 23
Peak memory 182628 kb
Host smart-fb04dd83-f701-45b8-895f-83040a12c7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994082097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
994082097
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.4102569705
Short name T567
Test name
Test status
Simulation time 76313597559 ps
CPU time 555.73 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:48:23 PM PST 23
Peak memory 205824 kb
Host smart-4c22c8c6-0094-423d-ac9d-f116ba55b8a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102569705 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.4102569705
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2773930154
Short name T246
Test name
Test status
Simulation time 150328696376 ps
CPU time 269.32 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:43:34 PM PST 23
Peak memory 182812 kb
Host smart-ba336528-cbcd-4009-856d-49894f270f54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773930154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2773930154
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.688291296
Short name T528
Test name
Test status
Simulation time 218249940474 ps
CPU time 49.99 seconds
Started Dec 24 12:38:58 PM PST 23
Finished Dec 24 12:39:56 PM PST 23
Peak memory 182864 kb
Host smart-d6a07423-0bd9-42ab-8c9d-0a21a4dab251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688291296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.688291296
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2645873644
Short name T132
Test name
Test status
Simulation time 141418985215 ps
CPU time 320.1 seconds
Started Dec 24 12:38:59 PM PST 23
Finished Dec 24 12:44:27 PM PST 23
Peak memory 191136 kb
Host smart-57d35dde-caf0-4c33-a60f-3a069948ddb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645873644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2645873644
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1733957744
Short name T308
Test name
Test status
Simulation time 71794686174 ps
CPU time 68.13 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:40:13 PM PST 23
Peak memory 182848 kb
Host smart-90ee1cf1-0a06-427b-a82e-5af035b7738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733957744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1733957744
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3111965128
Short name T213
Test name
Test status
Simulation time 945917430225 ps
CPU time 1835.12 seconds
Started Dec 24 12:39:05 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 191176 kb
Host smart-69e7926f-5642-433f-a323-11ac8154d26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111965128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3111965128
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1248673448
Short name T534
Test name
Test status
Simulation time 376204854582 ps
CPU time 538.45 seconds
Started Dec 24 12:38:55 PM PST 23
Finished Dec 24 12:48:04 PM PST 23
Peak memory 205772 kb
Host smart-e97218f2-71da-449d-bd25-d4cfda55d686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248673448 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1248673448
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1763452326
Short name T20
Test name
Test status
Simulation time 1761129141103 ps
CPU time 807.67 seconds
Started Dec 24 12:37:59 PM PST 23
Finished Dec 24 12:51:30 PM PST 23
Peak memory 182884 kb
Host smart-63e0cd38-1de3-4b47-8461-d0fb5cf5d8dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763452326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1763452326
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2748485490
Short name T560
Test name
Test status
Simulation time 192645522982 ps
CPU time 85.11 seconds
Started Dec 24 12:37:42 PM PST 23
Finished Dec 24 12:39:12 PM PST 23
Peak memory 182956 kb
Host smart-4326ce46-1238-470e-b794-83213730ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748485490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2748485490
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.975376349
Short name T341
Test name
Test status
Simulation time 211675729528 ps
CPU time 119.06 seconds
Started Dec 24 12:37:41 PM PST 23
Finished Dec 24 12:39:46 PM PST 23
Peak memory 182860 kb
Host smart-f688d1c8-575f-4353-a585-352bac3481cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975376349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.975376349
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3452813243
Short name T254
Test name
Test status
Simulation time 42513946944 ps
CPU time 39.32 seconds
Started Dec 24 12:37:56 PM PST 23
Finished Dec 24 12:38:40 PM PST 23
Peak memory 182796 kb
Host smart-8dd6df67-d9e4-41e9-bc25-4c4bb8553984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452813243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3452813243
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.315094347
Short name T504
Test name
Test status
Simulation time 408470519090 ps
CPU time 157.85 seconds
Started Dec 24 12:37:56 PM PST 23
Finished Dec 24 12:40:38 PM PST 23
Peak memory 182812 kb
Host smart-91838b3a-048b-43de-92bf-6b4aa5c14ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315094347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.315094347
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1437383853
Short name T494
Test name
Test status
Simulation time 114876986174 ps
CPU time 1469.23 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 01:02:23 PM PST 23
Peak memory 212556 kb
Host smart-8e69cff0-d872-4ab0-b5e3-e4da46677221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437383853 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1437383853
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.2792882678
Short name T21
Test name
Test status
Simulation time 565452021483 ps
CPU time 170.69 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 12:41:55 PM PST 23
Peak memory 193056 kb
Host smart-cf47659b-42e5-429b-b5d7-498e4923c6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792882678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2792882678
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.137891675
Short name T121
Test name
Test status
Simulation time 6227671737 ps
CPU time 32.16 seconds
Started Dec 24 12:38:53 PM PST 23
Finished Dec 24 12:39:36 PM PST 23
Peak memory 191396 kb
Host smart-87454e81-dfd0-480b-b7c8-7a543810b815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137891675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.137891675
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.277570689
Short name T112
Test name
Test status
Simulation time 23836759190 ps
CPU time 48.07 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:39:53 PM PST 23
Peak memory 191108 kb
Host smart-1c4a08d7-1a53-4015-b337-992b8f54b57d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277570689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.277570689
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.354155810
Short name T333
Test name
Test status
Simulation time 8250314904 ps
CPU time 8.46 seconds
Started Dec 24 12:38:59 PM PST 23
Finished Dec 24 12:39:15 PM PST 23
Peak memory 182808 kb
Host smart-6b7ffaec-7edb-463c-93a2-07e427e8432b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354155810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.354155810
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2047937581
Short name T378
Test name
Test status
Simulation time 185455877126 ps
CPU time 145.28 seconds
Started Dec 24 12:39:04 PM PST 23
Finished Dec 24 12:41:34 PM PST 23
Peak memory 182932 kb
Host smart-5580da6e-fd00-45d8-8988-47f7b9f472e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047937581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2047937581
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2235308902
Short name T200
Test name
Test status
Simulation time 2228319855939 ps
CPU time 400.46 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:45:48 PM PST 23
Peak memory 191024 kb
Host smart-6df42b69-e769-4396-8df3-dd4d0699cf7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235308902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2235308902
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1060971991
Short name T146
Test name
Test status
Simulation time 522430847338 ps
CPU time 583.87 seconds
Started Dec 24 12:38:59 PM PST 23
Finished Dec 24 12:48:51 PM PST 23
Peak memory 194644 kb
Host smart-e6996fde-c5d7-4155-acf3-0dadf3b2de12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060971991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1060971991
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.658041610
Short name T97
Test name
Test status
Simulation time 89574019904 ps
CPU time 331.24 seconds
Started Dec 24 12:38:56 PM PST 23
Finished Dec 24 12:44:37 PM PST 23
Peak memory 191136 kb
Host smart-451ab73d-7e98-4b96-9266-6ee66d6f4819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658041610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.658041610
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.130493813
Short name T194
Test name
Test status
Simulation time 419882801754 ps
CPU time 742.88 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:51:28 PM PST 23
Peak memory 191008 kb
Host smart-74360720-4e71-4c7c-9e45-d4151dc5aa9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130493813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.130493813
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1550226715
Short name T367
Test name
Test status
Simulation time 6740028680 ps
CPU time 12.14 seconds
Started Dec 24 12:37:48 PM PST 23
Finished Dec 24 12:38:03 PM PST 23
Peak memory 183020 kb
Host smart-bb3675bd-f61d-46ef-887f-4fd831d1af8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550226715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1550226715
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4081372746
Short name T499
Test name
Test status
Simulation time 227846187318 ps
CPU time 54.9 seconds
Started Dec 24 12:37:47 PM PST 23
Finished Dec 24 12:38:45 PM PST 23
Peak memory 182988 kb
Host smart-40c4bf57-6439-437f-8c9f-355e17d5e46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081372746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4081372746
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1551107989
Short name T322
Test name
Test status
Simulation time 95852841553 ps
CPU time 209.51 seconds
Started Dec 24 12:38:03 PM PST 23
Finished Dec 24 12:41:34 PM PST 23
Peak memory 182864 kb
Host smart-c98516da-7710-45ab-91d4-119e5d4cab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551107989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1551107989
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3010507085
Short name T201
Test name
Test status
Simulation time 1304564161057 ps
CPU time 1089.49 seconds
Started Dec 24 12:37:44 PM PST 23
Finished Dec 24 12:55:58 PM PST 23
Peak memory 191216 kb
Host smart-a0cb1964-0af6-4a7c-9abf-a4d7b70e9f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010507085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3010507085
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1405304939
Short name T224
Test name
Test status
Simulation time 286368101940 ps
CPU time 1174.19 seconds
Started Dec 24 12:37:53 PM PST 23
Finished Dec 24 12:57:30 PM PST 23
Peak memory 212304 kb
Host smart-91627fea-4aa2-4d2a-ac16-e80ee8c5d97b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405304939 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1405304939
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.2631883513
Short name T526
Test name
Test status
Simulation time 154663366420 ps
CPU time 43.6 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:39:51 PM PST 23
Peak memory 182756 kb
Host smart-38282edb-c898-482b-9a61-196db3c62794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631883513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2631883513
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2646316979
Short name T88
Test name
Test status
Simulation time 2674199156030 ps
CPU time 408.26 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:45:55 PM PST 23
Peak memory 191024 kb
Host smart-de134c75-7150-40c1-a9dc-b87f67c64f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646316979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2646316979
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2288004214
Short name T179
Test name
Test status
Simulation time 1035902083 ps
CPU time 2.15 seconds
Started Dec 24 12:39:00 PM PST 23
Finished Dec 24 12:39:09 PM PST 23
Peak memory 182192 kb
Host smart-156ae108-9589-4717-87ca-236f930c4440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288004214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2288004214
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2740252644
Short name T290
Test name
Test status
Simulation time 646025596769 ps
CPU time 393.43 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:45:39 PM PST 23
Peak memory 191168 kb
Host smart-cc5b4958-3b97-4edd-ba9b-2511ea6cc0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740252644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2740252644
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3503601758
Short name T96
Test name
Test status
Simulation time 215714876370 ps
CPU time 303.77 seconds
Started Dec 24 12:38:58 PM PST 23
Finished Dec 24 12:44:10 PM PST 23
Peak memory 191048 kb
Host smart-19c627ca-6acb-40a3-90ad-6d605073941b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503601758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3503601758
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1970190132
Short name T348
Test name
Test status
Simulation time 3948189756 ps
CPU time 4.29 seconds
Started Dec 24 12:39:08 PM PST 23
Finished Dec 24 12:39:15 PM PST 23
Peak memory 182936 kb
Host smart-fe8b61cb-1771-4b8a-88bd-f58275c2153b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970190132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1970190132
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1483106631
Short name T144
Test name
Test status
Simulation time 198267861397 ps
CPU time 410.92 seconds
Started Dec 24 12:38:56 PM PST 23
Finished Dec 24 12:45:57 PM PST 23
Peak memory 191072 kb
Host smart-d4f6fa4b-3d1b-4892-9e79-86f9e0b9beaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483106631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1483106631
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1970088670
Short name T543
Test name
Test status
Simulation time 6895116650 ps
CPU time 6.15 seconds
Started Dec 24 12:38:02 PM PST 23
Finished Dec 24 12:38:10 PM PST 23
Peak memory 182788 kb
Host smart-b883d5bf-5089-42b5-935b-3774b138b0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970088670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1970088670
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.345975048
Short name T122
Test name
Test status
Simulation time 415239190697 ps
CPU time 255.7 seconds
Started Dec 24 12:37:37 PM PST 23
Finished Dec 24 12:42:00 PM PST 23
Peak memory 191128 kb
Host smart-8d931d5d-c9ae-4e15-a64c-cdcf94a3b826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345975048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.345975048
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2636952882
Short name T226
Test name
Test status
Simulation time 81192421791 ps
CPU time 80.02 seconds
Started Dec 24 12:37:49 PM PST 23
Finished Dec 24 12:39:12 PM PST 23
Peak memory 192416 kb
Host smart-d4deaed4-9013-4ce2-9f7a-7724c0bab24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636952882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2636952882
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3803842094
Short name T206
Test name
Test status
Simulation time 1083594404765 ps
CPU time 805.89 seconds
Started Dec 24 12:37:51 PM PST 23
Finished Dec 24 12:51:20 PM PST 23
Peak memory 191152 kb
Host smart-8f483829-15d6-4ffc-8c82-fe5079e3b8f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803842094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3803842094
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3972522155
Short name T541
Test name
Test status
Simulation time 58573754671 ps
CPU time 297.64 seconds
Started Dec 24 12:37:47 PM PST 23
Finished Dec 24 12:42:47 PM PST 23
Peak memory 197532 kb
Host smart-7c57996a-a3ed-4e31-9a20-402d92d2c69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972522155 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3972522155
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3504226921
Short name T172
Test name
Test status
Simulation time 92011327055 ps
CPU time 160.44 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:41:45 PM PST 23
Peak memory 191068 kb
Host smart-f40acd64-273a-47f4-9729-65fcb1cddba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504226921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3504226921
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2987972884
Short name T342
Test name
Test status
Simulation time 437272281607 ps
CPU time 244.56 seconds
Started Dec 24 12:38:59 PM PST 23
Finished Dec 24 12:43:11 PM PST 23
Peak memory 193800 kb
Host smart-9a8a2b44-720a-4fd7-99b5-1dcf9e6c9982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987972884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2987972884
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.428576214
Short name T317
Test name
Test status
Simulation time 211101384900 ps
CPU time 204.06 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:42:30 PM PST 23
Peak memory 191132 kb
Host smart-19bcd71b-6902-4799-bc5e-2483d4d6381e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428576214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.428576214
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1517422567
Short name T228
Test name
Test status
Simulation time 136892591593 ps
CPU time 138.55 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:41:25 PM PST 23
Peak memory 191192 kb
Host smart-eafdf5f3-cd0c-48a1-bfa8-945dc0d18ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517422567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1517422567
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1909807964
Short name T180
Test name
Test status
Simulation time 183689870912 ps
CPU time 254.68 seconds
Started Dec 24 12:38:59 PM PST 23
Finished Dec 24 12:43:21 PM PST 23
Peak memory 191144 kb
Host smart-6f3854fd-99a8-408c-bb5d-2b1085426e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909807964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1909807964
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3340235569
Short name T23
Test name
Test status
Simulation time 494133944918 ps
CPU time 572.88 seconds
Started Dec 24 12:38:55 PM PST 23
Finished Dec 24 12:48:38 PM PST 23
Peak memory 191160 kb
Host smart-ed48638c-ef34-4938-8fe2-fe364c94c4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340235569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3340235569
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.507303570
Short name T284
Test name
Test status
Simulation time 27342878699 ps
CPU time 48.03 seconds
Started Dec 24 12:38:54 PM PST 23
Finished Dec 24 12:39:53 PM PST 23
Peak memory 191076 kb
Host smart-174a51e9-28d5-46cf-ad4c-5078e7d83918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507303570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.507303570
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3779608677
Short name T244
Test name
Test status
Simulation time 59844795746 ps
CPU time 131.7 seconds
Started Dec 24 12:39:03 PM PST 23
Finished Dec 24 12:41:20 PM PST 23
Peak memory 191156 kb
Host smart-c18c0bed-66e7-4c42-bdb9-05d032cfa5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779608677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3779608677
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.222038864
Short name T120
Test name
Test status
Simulation time 166321368694 ps
CPU time 173.53 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:42:00 PM PST 23
Peak memory 190996 kb
Host smart-220b6588-a307-4bed-b236-16c5d416744b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222038864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.222038864
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3926751488
Short name T9
Test name
Test status
Simulation time 151153645145 ps
CPU time 266.6 seconds
Started Dec 24 12:37:55 PM PST 23
Finished Dec 24 12:42:26 PM PST 23
Peak memory 182784 kb
Host smart-c4e8ea51-8471-4bba-acd1-8c58558a2ed3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926751488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3926751488
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1488632855
Short name T533
Test name
Test status
Simulation time 386912997213 ps
CPU time 168.42 seconds
Started Dec 24 12:37:46 PM PST 23
Finished Dec 24 12:40:37 PM PST 23
Peak memory 182904 kb
Host smart-96c8314b-d8fd-4b0d-ae6c-e8017339c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488632855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1488632855
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.885266350
Short name T250
Test name
Test status
Simulation time 625131721495 ps
CPU time 305.78 seconds
Started Dec 24 12:37:53 PM PST 23
Finished Dec 24 12:43:01 PM PST 23
Peak memory 191036 kb
Host smart-d46614c5-a10f-4e12-8048-d7a7b60e15cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885266350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.885266350
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1037790896
Short name T313
Test name
Test status
Simulation time 104018270941 ps
CPU time 366.16 seconds
Started Dec 24 12:38:07 PM PST 23
Finished Dec 24 12:44:16 PM PST 23
Peak memory 191032 kb
Host smart-73d8b1b1-c368-4e67-8a9d-bf281ef4090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037790896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1037790896
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4113677337
Short name T585
Test name
Test status
Simulation time 74854195022 ps
CPU time 128.64 seconds
Started Dec 24 12:37:59 PM PST 23
Finished Dec 24 12:40:11 PM PST 23
Peak memory 191088 kb
Host smart-a88dd301-0af9-412f-a8f5-81737298e696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113677337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4113677337
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3698945496
Short name T359
Test name
Test status
Simulation time 416332714203 ps
CPU time 873.96 seconds
Started Dec 24 12:37:57 PM PST 23
Finished Dec 24 12:52:36 PM PST 23
Peak memory 209372 kb
Host smart-7da50251-607d-4b70-8db0-bbbb02daaed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698945496 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3698945496
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2421000698
Short name T113
Test name
Test status
Simulation time 68303750886 ps
CPU time 441.48 seconds
Started Dec 24 12:39:03 PM PST 23
Finished Dec 24 12:46:30 PM PST 23
Peak memory 191172 kb
Host smart-297627b8-5a0e-4212-adaf-002f9e5baff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421000698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2421000698
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4115458636
Short name T360
Test name
Test status
Simulation time 124592433581 ps
CPU time 402.62 seconds
Started Dec 24 12:38:57 PM PST 23
Finished Dec 24 12:45:49 PM PST 23
Peak memory 191036 kb
Host smart-ab2ca929-3db2-4cbc-8ba0-a9bd2364ecb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115458636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4115458636
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2559811002
Short name T319
Test name
Test status
Simulation time 441013937074 ps
CPU time 224.41 seconds
Started Dec 24 12:38:58 PM PST 23
Finished Dec 24 12:42:51 PM PST 23
Peak memory 191052 kb
Host smart-013fde14-d171-4662-abb6-290ebaecad3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559811002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2559811002
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3473556008
Short name T138
Test name
Test status
Simulation time 78141951360 ps
CPU time 139.73 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:41:27 PM PST 23
Peak memory 191044 kb
Host smart-39939ce5-602a-4db2-8810-15b9e607c325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473556008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3473556008
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.452214130
Short name T617
Test name
Test status
Simulation time 174073287658 ps
CPU time 131.2 seconds
Started Dec 24 12:39:09 PM PST 23
Finished Dec 24 12:41:22 PM PST 23
Peak memory 182848 kb
Host smart-fadf7114-06ec-4c5e-9427-98e14472b962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452214130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.452214130
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3107664626
Short name T241
Test name
Test status
Simulation time 121394084336 ps
CPU time 261.67 seconds
Started Dec 24 12:39:09 PM PST 23
Finished Dec 24 12:43:32 PM PST 23
Peak memory 191176 kb
Host smart-a28f95bf-c58c-48e8-8be6-7b05a988a52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107664626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3107664626
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.536430875
Short name T297
Test name
Test status
Simulation time 203505534193 ps
CPU time 684.5 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:50:31 PM PST 23
Peak memory 191004 kb
Host smart-2001f9af-373b-4c5b-a867-076ce9b75df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536430875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.536430875
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.833604944
Short name T3
Test name
Test status
Simulation time 744877041436 ps
CPU time 518.02 seconds
Started Dec 24 12:39:09 PM PST 23
Finished Dec 24 12:47:49 PM PST 23
Peak memory 191164 kb
Host smart-59a2a938-6403-496a-8007-ee9694ee403b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833604944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.833604944
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2166922388
Short name T323
Test name
Test status
Simulation time 72714876666 ps
CPU time 138.56 seconds
Started Dec 24 12:37:46 PM PST 23
Finished Dec 24 12:40:07 PM PST 23
Peak memory 182728 kb
Host smart-fac4bf8b-726a-4c07-9531-315d0735f384
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166922388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2166922388
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2774758385
Short name T6
Test name
Test status
Simulation time 12417899875 ps
CPU time 19.75 seconds
Started Dec 24 12:37:54 PM PST 23
Finished Dec 24 12:38:16 PM PST 23
Peak memory 182972 kb
Host smart-e6b2382d-d256-47c9-9c3c-3d269eef3df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774758385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2774758385
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2584354142
Short name T114
Test name
Test status
Simulation time 204629807386 ps
CPU time 114.8 seconds
Started Dec 24 12:38:05 PM PST 23
Finished Dec 24 12:40:00 PM PST 23
Peak memory 191116 kb
Host smart-8ca9da6c-2af2-4720-a415-d1eff63ebe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584354142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2584354142
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3127230734
Short name T175
Test name
Test status
Simulation time 1086207917662 ps
CPU time 445.88 seconds
Started Dec 24 12:38:03 PM PST 23
Finished Dec 24 12:45:31 PM PST 23
Peak memory 193764 kb
Host smart-a01eb6e1-a005-4701-9bdd-de8e5a0515d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127230734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3127230734
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1981580021
Short name T318
Test name
Test status
Simulation time 223927713440 ps
CPU time 674.81 seconds
Started Dec 24 12:37:41 PM PST 23
Finished Dec 24 12:49:02 PM PST 23
Peak memory 207808 kb
Host smart-cb690bf7-a954-4167-a110-666fba6304cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981580021 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1981580021
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.4140806962
Short name T366
Test name
Test status
Simulation time 221910669807 ps
CPU time 220.34 seconds
Started Dec 24 12:39:06 PM PST 23
Finished Dec 24 12:42:49 PM PST 23
Peak memory 191052 kb
Host smart-3139e07a-4f63-4cad-83b7-029a567784f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140806962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4140806962
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1578691754
Short name T335
Test name
Test status
Simulation time 58912998802 ps
CPU time 110.32 seconds
Started Dec 24 12:39:07 PM PST 23
Finished Dec 24 12:41:01 PM PST 23
Peak memory 193048 kb
Host smart-05c48ebb-2a46-4380-9282-0513fecd929c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578691754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1578691754
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1634227011
Short name T227
Test name
Test status
Simulation time 169926774911 ps
CPU time 1615.65 seconds
Started Dec 24 12:39:02 PM PST 23
Finished Dec 24 01:06:04 PM PST 23
Peak memory 193368 kb
Host smart-dbe303f3-c31c-47a8-96ac-7973a52b5d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634227011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1634227011
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3056120084
Short name T582
Test name
Test status
Simulation time 39747547276 ps
CPU time 81.19 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:40:28 PM PST 23
Peak memory 190980 kb
Host smart-98eadbe4-b715-40cf-b9b8-d9cf1f6462a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056120084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3056120084
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.533987194
Short name T611
Test name
Test status
Simulation time 37357796862 ps
CPU time 102.87 seconds
Started Dec 24 12:39:14 PM PST 23
Finished Dec 24 12:40:58 PM PST 23
Peak memory 194860 kb
Host smart-16a3fd33-79d1-4700-9e18-cfbe867e13f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533987194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.533987194
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2778373128
Short name T111
Test name
Test status
Simulation time 153599668119 ps
CPU time 256.15 seconds
Started Dec 24 12:39:01 PM PST 23
Finished Dec 24 12:43:23 PM PST 23
Peak memory 191044 kb
Host smart-3cf1b8ab-47b6-45a7-83e8-2f18f5b4fcf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778373128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2778373128
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1532375149
Short name T218
Test name
Test status
Simulation time 265310894979 ps
CPU time 1122.29 seconds
Started Dec 24 12:39:02 PM PST 23
Finished Dec 24 12:57:50 PM PST 23
Peak memory 190980 kb
Host smart-37649bf6-c7e3-432e-ba1e-03a85ded0068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532375149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1532375149
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1592609004
Short name T165
Test name
Test status
Simulation time 82627325227 ps
CPU time 144.4 seconds
Started Dec 24 12:39:06 PM PST 23
Finished Dec 24 12:41:34 PM PST 23
Peak memory 191036 kb
Host smart-9969c441-d6d8-4bf0-b466-6ca703840592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592609004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1592609004
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2989392588
Short name T345
Test name
Test status
Simulation time 134088240344 ps
CPU time 58.17 seconds
Started Dec 24 12:39:06 PM PST 23
Finished Dec 24 12:40:08 PM PST 23
Peak memory 194232 kb
Host smart-570d0668-fad8-4f48-945b-cb64b8f29487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989392588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2989392588
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%