Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 618
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T299 /workspace/coverage/default/107.rv_timer_random.2861022462 Dec 27 12:35:19 PM PST 23 Dec 27 12:37:15 PM PST 23 57613977608 ps
T325 /workspace/coverage/default/29.rv_timer_random.1572254118 Dec 27 12:35:32 PM PST 23 Dec 27 12:41:34 PM PST 23 1101653133861 ps
T257 /workspace/coverage/default/31.rv_timer_stress_all.4271022769 Dec 27 12:35:19 PM PST 23 Dec 27 12:38:16 PM PST 23 144756609923 ps
T236 /workspace/coverage/default/17.rv_timer_random.267901272 Dec 27 12:35:14 PM PST 23 Dec 27 12:36:41 PM PST 23 48590118238 ps
T365 /workspace/coverage/default/37.rv_timer_stress_all.3050403468 Dec 27 12:35:47 PM PST 23 Dec 27 12:36:56 PM PST 23 33150666593 ps
T249 /workspace/coverage/default/183.rv_timer_random.3485828766 Dec 27 12:35:36 PM PST 23 Dec 27 12:38:17 PM PST 23 75795322178 ps
T203 /workspace/coverage/default/33.rv_timer_random.2787472068 Dec 27 12:35:03 PM PST 23 Dec 27 12:38:37 PM PST 23 471695833608 ps
T239 /workspace/coverage/default/15.rv_timer_random.1651888883 Dec 27 12:35:25 PM PST 23 Dec 27 12:40:57 PM PST 23 217533476413 ps
T566 /workspace/coverage/default/24.rv_timer_disabled.405019967 Dec 27 12:34:52 PM PST 23 Dec 27 12:37:36 PM PST 23 102792878996 ps
T567 /workspace/coverage/default/122.rv_timer_random.4146978319 Dec 27 12:35:17 PM PST 23 Dec 27 12:39:37 PM PST 23 119129865390 ps
T370 /workspace/coverage/default/26.rv_timer_random.683420595 Dec 27 12:35:10 PM PST 23 Dec 27 12:38:02 PM PST 23 553261399128 ps
T568 /workspace/coverage/default/38.rv_timer_disabled.454667085 Dec 27 12:36:34 PM PST 23 Dec 27 12:40:07 PM PST 23 528959644187 ps
T569 /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2178586285 Dec 27 12:35:10 PM PST 23 Dec 27 12:39:28 PM PST 23 66386210303 ps
T172 /workspace/coverage/default/21.rv_timer_stress_all.3958929277 Dec 27 12:34:55 PM PST 23 Dec 27 12:47:23 PM PST 23 911263597598 ps
T570 /workspace/coverage/default/2.rv_timer_random_reset.3356108129 Dec 27 12:36:26 PM PST 23 Dec 27 12:36:49 PM PST 23 149256445 ps
T269 /workspace/coverage/default/125.rv_timer_random.2463976879 Dec 27 12:35:19 PM PST 23 Dec 27 12:43:46 PM PST 23 521136183153 ps
T571 /workspace/coverage/default/44.rv_timer_disabled.3772827950 Dec 27 12:35:31 PM PST 23 Dec 27 12:38:29 PM PST 23 213129419933 ps
T216 /workspace/coverage/default/48.rv_timer_random_reset.100954547 Dec 27 12:35:18 PM PST 23 Dec 27 12:37:21 PM PST 23 122351339966 ps
T154 /workspace/coverage/default/32.rv_timer_stress_all.2728733081 Dec 27 12:35:19 PM PST 23 Dec 27 12:52:02 PM PST 23 193294709908 ps
T572 /workspace/coverage/default/26.rv_timer_random_reset.1859815119 Dec 27 12:35:20 PM PST 23 Dec 27 12:35:37 PM PST 23 394050785 ps
T207 /workspace/coverage/default/41.rv_timer_random.2930552449 Dec 27 12:35:05 PM PST 23 Dec 27 12:37:26 PM PST 23 68872398161 ps
T331 /workspace/coverage/default/62.rv_timer_random.4155681334 Dec 27 12:35:09 PM PST 23 Dec 27 12:41:06 PM PST 23 162855679403 ps
T285 /workspace/coverage/default/0.rv_timer_random.1933917499 Dec 27 12:34:39 PM PST 23 Dec 27 12:38:14 PM PST 23 574103321967 ps
T351 /workspace/coverage/default/41.rv_timer_random_reset.686960274 Dec 27 12:35:41 PM PST 23 Dec 27 12:36:47 PM PST 23 121512959122 ps
T573 /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2654570117 Dec 27 12:35:17 PM PST 23 Dec 27 12:49:48 PM PST 23 104776837847 ps
T237 /workspace/coverage/default/23.rv_timer_random.4072286572 Dec 27 12:36:06 PM PST 23 Dec 27 01:03:58 PM PST 23 304030746025 ps
T574 /workspace/coverage/default/0.rv_timer_disabled.1220475368 Dec 27 12:34:33 PM PST 23 Dec 27 12:36:26 PM PST 23 60573911048 ps
T575 /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2933698686 Dec 27 12:35:30 PM PST 23 Dec 27 12:47:39 PM PST 23 232920652994 ps
T250 /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4131300306 Dec 27 12:35:14 PM PST 23 Dec 27 12:35:52 PM PST 23 13066968064 ps
T576 /workspace/coverage/default/35.rv_timer_random_reset.2342000186 Dec 27 12:36:51 PM PST 23 Dec 27 12:39:10 PM PST 23 109411738740 ps
T361 /workspace/coverage/default/32.rv_timer_random.3978415311 Dec 27 12:36:09 PM PST 23 Dec 27 12:43:39 PM PST 23 86130827641 ps
T577 /workspace/coverage/default/65.rv_timer_random.407598743 Dec 27 12:35:52 PM PST 23 Dec 27 12:36:22 PM PST 23 21973335750 ps
T274 /workspace/coverage/default/104.rv_timer_random.1551482087 Dec 27 12:35:38 PM PST 23 Dec 27 12:51:12 PM PST 23 467198744453 ps
T312 /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3042195948 Dec 27 12:35:14 PM PST 23 Dec 27 12:42:50 PM PST 23 119771069993 ps
T363 /workspace/coverage/default/191.rv_timer_random.504547069 Dec 27 12:35:24 PM PST 23 Dec 27 12:43:15 PM PST 23 388568692807 ps
T578 /workspace/coverage/default/47.rv_timer_random_reset.3808194044 Dec 27 12:35:01 PM PST 23 Dec 27 12:35:37 PM PST 23 39043981368 ps
T579 /workspace/coverage/default/15.rv_timer_random_reset.2075422028 Dec 27 12:35:02 PM PST 23 Dec 27 12:36:16 PM PST 23 65378626846 ps
T308 /workspace/coverage/default/7.rv_timer_random_reset.700125210 Dec 27 12:35:22 PM PST 23 Dec 27 12:43:47 PM PST 23 583147320445 ps
T580 /workspace/coverage/default/117.rv_timer_random.3026448476 Dec 27 12:35:29 PM PST 23 Dec 27 12:47:47 PM PST 23 489663348995 ps
T581 /workspace/coverage/default/139.rv_timer_random.2004005400 Dec 27 12:36:21 PM PST 23 Dec 27 12:55:33 PM PST 23 159946773558 ps
T287 /workspace/coverage/default/14.rv_timer_stress_all.3553087803 Dec 27 12:35:24 PM PST 23 Dec 27 12:52:35 PM PST 23 1470356242009 ps
T582 /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3454246093 Dec 27 12:34:56 PM PST 23 Dec 27 12:46:26 PM PST 23 529946966710 ps
T583 /workspace/coverage/default/14.rv_timer_disabled.282115261 Dec 27 12:35:06 PM PST 23 Dec 27 12:37:56 PM PST 23 876451085339 ps
T182 /workspace/coverage/default/40.rv_timer_stress_all.4287588839 Dec 27 12:35:16 PM PST 23 Dec 27 01:11:46 PM PST 23 2004319375075 ps
T372 /workspace/coverage/default/5.rv_timer_random.518455638 Dec 27 12:34:52 PM PST 23 Dec 27 12:38:14 PM PST 23 78930740735 ps
T584 /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2771874125 Dec 27 12:34:52 PM PST 23 Dec 27 12:43:57 PM PST 23 47841014896 ps
T348 /workspace/coverage/default/6.rv_timer_random_reset.2652721844 Dec 27 12:34:41 PM PST 23 Dec 27 12:35:08 PM PST 23 5230656013 ps
T585 /workspace/coverage/default/118.rv_timer_random.86080220 Dec 27 12:35:16 PM PST 23 Dec 27 12:36:22 PM PST 23 53059577174 ps
T245 /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3798115710 Dec 27 12:34:58 PM PST 23 Dec 27 12:35:42 PM PST 23 14274436295 ps
T340 /workspace/coverage/default/174.rv_timer_random.670880346 Dec 27 12:35:36 PM PST 23 Dec 27 12:56:51 PM PST 23 361026865469 ps
T374 /workspace/coverage/default/34.rv_timer_stress_all.1472214552 Dec 27 12:36:41 PM PST 23 Dec 27 12:52:46 PM PST 23 283941675159 ps
T375 /workspace/coverage/default/17.rv_timer_stress_all.2353465629 Dec 27 12:35:17 PM PST 23 Dec 27 12:36:40 PM PST 23 159096807696 ps
T316 /workspace/coverage/default/164.rv_timer_random.3390963764 Dec 27 12:35:56 PM PST 23 Dec 27 12:49:44 PM PST 23 186353528729 ps
T276 /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3737936283 Dec 27 12:35:48 PM PST 23 Dec 27 12:36:15 PM PST 23 15564880256 ps
T586 /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2163444281 Dec 27 12:35:46 PM PST 23 Dec 27 12:38:50 PM PST 23 21032292491 ps
T587 /workspace/coverage/default/68.rv_timer_random.1009170653 Dec 27 12:35:15 PM PST 23 Dec 27 12:37:10 PM PST 23 59221567609 ps
T169 /workspace/coverage/default/38.rv_timer_stress_all.1134779059 Dec 27 12:35:22 PM PST 23 Dec 27 12:53:05 PM PST 23 1688497995338 ps
T246 /workspace/coverage/default/60.rv_timer_random.820178569 Dec 27 12:35:23 PM PST 23 Dec 27 12:40:16 PM PST 23 401672147681 ps
T588 /workspace/coverage/default/44.rv_timer_random_reset.1737713511 Dec 27 12:35:02 PM PST 23 Dec 27 01:04:18 PM PST 23 244626750976 ps
T589 /workspace/coverage/default/30.rv_timer_random_reset.920346355 Dec 27 12:37:12 PM PST 23 Dec 27 12:37:45 PM PST 23 9829513095 ps
T590 /workspace/coverage/default/93.rv_timer_random.3000447978 Dec 27 12:35:24 PM PST 23 Dec 27 12:40:06 PM PST 23 29183311244 ps
T591 /workspace/coverage/default/16.rv_timer_random_reset.2888596110 Dec 27 12:35:16 PM PST 23 Dec 27 12:35:33 PM PST 23 1558402485 ps
T343 /workspace/coverage/default/38.rv_timer_random_reset.3263110462 Dec 27 12:35:38 PM PST 23 Dec 27 12:43:02 PM PST 23 98275971185 ps
T592 /workspace/coverage/default/28.rv_timer_random.2007054882 Dec 27 12:34:48 PM PST 23 Dec 27 12:36:54 PM PST 23 133187928493 ps
T362 /workspace/coverage/default/5.rv_timer_random_reset.2907581124 Dec 27 12:35:12 PM PST 23 Dec 27 12:35:47 PM PST 23 24671972936 ps
T593 /workspace/coverage/default/24.rv_timer_random_reset.775691944 Dec 27 12:35:19 PM PST 23 Dec 27 12:35:40 PM PST 23 6439142463 ps
T352 /workspace/coverage/default/77.rv_timer_random.3406968648 Dec 27 12:35:17 PM PST 23 Dec 27 12:35:53 PM PST 23 119597088827 ps
T313 /workspace/coverage/default/30.rv_timer_stress_all.2422221984 Dec 27 12:35:44 PM PST 23 Dec 27 12:48:56 PM PST 23 516626293198 ps
T254 /workspace/coverage/default/35.rv_timer_random.4022886272 Dec 27 12:36:58 PM PST 23 Dec 27 12:46:36 PM PST 23 417848075525 ps
T594 /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2212277700 Dec 27 12:35:13 PM PST 23 Dec 27 12:40:13 PM PST 23 505620642943 ps
T339 /workspace/coverage/default/58.rv_timer_random.1209324238 Dec 27 12:35:21 PM PST 23 Dec 27 12:38:04 PM PST 23 89439155180 ps
T286 /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1357440878 Dec 27 12:35:08 PM PST 23 Dec 27 12:39:47 PM PST 23 496749810456 ps
T301 /workspace/coverage/default/0.rv_timer_stress_all.3117097302 Dec 27 12:34:40 PM PST 23 Dec 27 12:54:37 PM PST 23 461644267488 ps
T595 /workspace/coverage/default/154.rv_timer_random.3303009533 Dec 27 12:35:36 PM PST 23 Dec 27 12:39:11 PM PST 23 91090145624 ps
T596 /workspace/coverage/default/10.rv_timer_disabled.449801683 Dec 27 12:35:29 PM PST 23 Dec 27 12:36:41 PM PST 23 84285050155 ps
T597 /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3879298696 Dec 27 12:35:33 PM PST 23 Dec 27 12:43:35 PM PST 23 33676325203 ps
T598 /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2605828957 Dec 27 12:35:54 PM PST 23 Dec 27 12:36:43 PM PST 23 16208933455 ps
T228 /workspace/coverage/default/149.rv_timer_random.2982987848 Dec 27 12:35:27 PM PST 23 Dec 27 12:37:37 PM PST 23 49796337284 ps
T303 /workspace/coverage/default/8.rv_timer_random_reset.504418307 Dec 27 12:35:14 PM PST 23 Dec 27 12:58:46 PM PST 23 324161932444 ps
T300 /workspace/coverage/default/16.rv_timer_random.2116353638 Dec 27 12:35:52 PM PST 23 Dec 27 12:48:36 PM PST 23 714846035560 ps
T599 /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.134702892 Dec 27 12:35:29 PM PST 23 Dec 27 12:42:10 PM PST 23 55159056128 ps
T600 /workspace/coverage/default/47.rv_timer_disabled.2103483902 Dec 27 12:35:20 PM PST 23 Dec 27 12:39:45 PM PST 23 306337259798 ps
T304 /workspace/coverage/default/167.rv_timer_random.2475055177 Dec 27 12:36:04 PM PST 23 Dec 27 01:11:45 PM PST 23 679202046396 ps
T270 /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1807490731 Dec 27 12:36:48 PM PST 23 Dec 27 12:41:27 PM PST 23 679202516344 ps
T601 /workspace/coverage/default/26.rv_timer_stress_all.3904626367 Dec 27 12:35:09 PM PST 23 Dec 27 12:39:31 PM PST 23 166569811958 ps
T229 /workspace/coverage/default/70.rv_timer_random.941985348 Dec 27 12:35:51 PM PST 23 Dec 27 12:45:55 PM PST 23 138170390644 ps
T309 /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1018625445 Dec 27 12:35:12 PM PST 23 Dec 27 12:45:52 PM PST 23 247419066508 ps
T198 /workspace/coverage/default/35.rv_timer_stress_all.2518271242 Dec 27 12:35:14 PM PST 23 Dec 27 01:03:40 PM PST 23 709454262801 ps
T602 /workspace/coverage/default/71.rv_timer_random.1577822873 Dec 27 12:35:13 PM PST 23 Dec 27 12:45:10 PM PST 23 111333242637 ps
T231 /workspace/coverage/default/45.rv_timer_stress_all.865503997 Dec 27 12:35:12 PM PST 23 Dec 27 12:46:06 PM PST 23 381377490132 ps
T603 /workspace/coverage/default/21.rv_timer_disabled.1641889114 Dec 27 12:34:53 PM PST 23 Dec 27 12:37:31 PM PST 23 197972413553 ps
T290 /workspace/coverage/default/177.rv_timer_random.135772502 Dec 27 12:35:45 PM PST 23 Dec 27 12:42:32 PM PST 23 67769730268 ps
T604 /workspace/coverage/default/127.rv_timer_random.2167444428 Dec 27 12:35:44 PM PST 23 Dec 27 12:36:38 PM PST 23 18394946186 ps
T364 /workspace/coverage/default/136.rv_timer_random.869301744 Dec 27 12:35:47 PM PST 23 Dec 27 12:42:18 PM PST 23 213657106530 ps
T605 /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.831030378 Dec 27 12:35:13 PM PST 23 Dec 27 12:38:05 PM PST 23 21096390029 ps
T606 /workspace/coverage/default/113.rv_timer_random.1512594653 Dec 27 12:35:41 PM PST 23 Dec 27 12:39:00 PM PST 23 653033170319 ps
T193 /workspace/coverage/default/121.rv_timer_random.330762975 Dec 27 12:36:07 PM PST 23 Dec 27 12:38:54 PM PST 23 171614034442 ps
T319 /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2447466112 Dec 27 12:35:25 PM PST 23 Dec 27 12:36:19 PM PST 23 24051425127 ps
T607 /workspace/coverage/default/25.rv_timer_random.109458796 Dec 27 12:35:02 PM PST 23 Dec 27 12:40:53 PM PST 23 188019382612 ps
T608 /workspace/coverage/default/51.rv_timer_random.2970293102 Dec 27 12:35:00 PM PST 23 Dec 27 12:43:39 PM PST 23 119683943993 ps
T356 /workspace/coverage/default/12.rv_timer_random_reset.1424281892 Dec 27 12:35:05 PM PST 23 Dec 27 12:36:19 PM PST 23 38552394837 ps
T609 /workspace/coverage/default/84.rv_timer_random.3557566738 Dec 27 12:36:08 PM PST 23 Dec 27 12:37:48 PM PST 23 46333120069 ps
T332 /workspace/coverage/default/69.rv_timer_random.461453329 Dec 27 12:35:33 PM PST 23 Dec 27 12:50:00 PM PST 23 91385487819 ps
T610 /workspace/coverage/default/26.rv_timer_disabled.3991959641 Dec 27 12:35:08 PM PST 23 Dec 27 12:39:37 PM PST 23 622075867403 ps
T355 /workspace/coverage/default/196.rv_timer_random.1561199359 Dec 27 12:35:34 PM PST 23 Dec 27 12:49:05 PM PST 23 1206805729323 ps
T265 /workspace/coverage/default/188.rv_timer_random.867847418 Dec 27 12:36:07 PM PST 23 Dec 27 12:38:42 PM PST 23 196146288324 ps
T611 /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3152198260 Dec 27 12:35:11 PM PST 23 Dec 27 01:00:42 PM PST 23 297724078992 ps
T612 /workspace/coverage/default/57.rv_timer_random.168593091 Dec 27 12:35:05 PM PST 23 Dec 27 12:38:42 PM PST 23 83768248064 ps
T613 /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1233240516 Dec 27 12:35:32 PM PST 23 Dec 27 12:41:34 PM PST 23 47792917293 ps
T333 /workspace/coverage/default/55.rv_timer_random.1646363102 Dec 27 12:35:23 PM PST 23 Dec 27 12:40:27 PM PST 23 552179647854 ps
T614 /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2327674602 Dec 27 12:37:09 PM PST 23 Dec 27 12:46:25 PM PST 23 647099428370 ps
T354 /workspace/coverage/default/42.rv_timer_stress_all.4232140756 Dec 27 12:35:31 PM PST 23 Dec 27 12:46:38 PM PST 23 400073698530 ps
T615 /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1822752479 Dec 27 12:35:21 PM PST 23 Dec 27 12:51:33 PM PST 23 146060723670 ps
T616 /workspace/coverage/default/168.rv_timer_random.539077556 Dec 27 12:35:25 PM PST 23 Dec 27 12:36:12 PM PST 23 81545158306 ps
T271 /workspace/coverage/default/1.rv_timer_random.1730682296 Dec 27 12:36:33 PM PST 23 Dec 27 12:40:08 PM PST 23 430198572531 ps
T617 /workspace/coverage/default/43.rv_timer_disabled.3545359521 Dec 27 12:34:50 PM PST 23 Dec 27 12:38:00 PM PST 23 110646883662 ps
T618 /workspace/coverage/default/32.rv_timer_disabled.1143176928 Dec 27 12:36:47 PM PST 23 Dec 27 12:41:11 PM PST 23 655735138345 ps
T373 /workspace/coverage/default/66.rv_timer_random.1235715531 Dec 27 12:35:32 PM PST 23 Dec 27 12:36:23 PM PST 23 22863737136 ps

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2292260481
Short name T3
Test name
Test status
Simulation time 153890086527 ps
CPU time 101.21 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 197700 kb
Host smart-691ae5bf-39ef-4249-a0c2-f45c58404230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292260481 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2292260481
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.rv_timer_random.2733758857
Short name T8
Test name
Test status
Simulation time 593785762027 ps
CPU time 1137.56 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:54:54 PM PST 23
Peak memory 191156 kb
Host smart-116b6462-896d-4bba-8646-60fbabf23d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733758857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2733758857
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2893238867
Short name T166
Test name
Test status
Simulation time 794345717554 ps
CPU time 2129.71 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 01:11:14 PM PST 23
Peak memory 190988 kb
Host smart-6e912ca5-5b6d-4c39-9e4e-23336cf1250f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893238867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2893238867
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.434847622
Short name T30
Test name
Test status
Simulation time 708953338 ps
CPU time 1.1 seconds
Started Dec 27 01:09:25 PM PST 23
Finished Dec 27 01:09:35 PM PST 23
Peak memory 183572 kb
Host smart-eb1c6996-ce2d-4294-855c-d6661f44e02e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434847622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.434847622
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.982226196
Short name T109
Test name
Test status
Simulation time 503115893810 ps
CPU time 1605.08 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 195180 kb
Host smart-23c8882c-0189-472a-aafe-b14a7ec505b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982226196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
982226196
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.767109402
Short name T180
Test name
Test status
Simulation time 3941271291478 ps
CPU time 6893.06 seconds
Started Dec 27 12:35:58 PM PST 23
Finished Dec 27 02:31:11 PM PST 23
Peak memory 191020 kb
Host smart-8c48c018-1c03-4e67-88fa-196b87e65b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767109402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
767109402
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3251955951
Short name T101
Test name
Test status
Simulation time 6073008810004 ps
CPU time 2822.5 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 01:22:40 PM PST 23
Peak memory 191060 kb
Host smart-9bf040de-66c1-43d9-964b-f6ef7c7b6a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251955951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3251955951
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2612234903
Short name T110
Test name
Test status
Simulation time 1500406861392 ps
CPU time 2360.46 seconds
Started Dec 27 12:35:52 PM PST 23
Finished Dec 27 01:15:32 PM PST 23
Peak memory 195768 kb
Host smart-141146f1-3753-46bc-a372-00369799a814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612234903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2612234903
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1309607326
Short name T46
Test name
Test status
Simulation time 50708740 ps
CPU time 0.56 seconds
Started Dec 27 01:09:37 PM PST 23
Finished Dec 27 01:09:46 PM PST 23
Peak memory 183292 kb
Host smart-f199beba-00ef-4d0c-adf5-d095adc5d194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309607326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1309607326
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3755419188
Short name T103
Test name
Test status
Simulation time 1354964438853 ps
CPU time 1701.35 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 01:03:44 PM PST 23
Peak memory 191020 kb
Host smart-864ace10-ddb0-4f8d-92a5-a0d8bc43654a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755419188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3755419188
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3117097302
Short name T301
Test name
Test status
Simulation time 461644267488 ps
CPU time 1180.08 seconds
Started Dec 27 12:34:40 PM PST 23
Finished Dec 27 12:54:37 PM PST 23
Peak memory 191024 kb
Host smart-61497b51-4311-4904-9b8f-ed53efd1f0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117097302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3117097302
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1191146748
Short name T202
Test name
Test status
Simulation time 1422841076360 ps
CPU time 1667.57 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 190996 kb
Host smart-f24d1f2f-1f90-4cca-b4c2-db3425b03582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191146748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1191146748
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1812035060
Short name T15
Test name
Test status
Simulation time 41630050 ps
CPU time 0.72 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:03 PM PST 23
Peak memory 212652 kb
Host smart-e18f4564-4b4f-4470-a31a-44b770691302
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812035060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1812035060
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.235137187
Short name T212
Test name
Test status
Simulation time 478345677386 ps
CPU time 1193.68 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:55:35 PM PST 23
Peak memory 191156 kb
Host smart-f46f459e-d77f-4d83-8d24-3148f3c83a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235137187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
235137187
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.85032459
Short name T153
Test name
Test status
Simulation time 461289934723 ps
CPU time 1201.18 seconds
Started Dec 27 12:34:54 PM PST 23
Finished Dec 27 12:55:16 PM PST 23
Peak memory 191008 kb
Host smart-c88f6511-7abc-404c-90a5-1a79b8a618d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85032459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.85032459
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.80099826
Short name T214
Test name
Test status
Simulation time 1946035566960 ps
CPU time 1414.25 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 194672 kb
Host smart-e9405fbe-3980-41d1-8466-9c1580030fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80099826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.80099826
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3396399379
Short name T177
Test name
Test status
Simulation time 469980573577 ps
CPU time 2543.8 seconds
Started Dec 27 12:34:32 PM PST 23
Finished Dec 27 01:17:13 PM PST 23
Peak memory 191108 kb
Host smart-4e5a0322-e54b-4072-93f4-ff1427f0b122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396399379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3396399379
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/143.rv_timer_random.2648136955
Short name T135
Test name
Test status
Simulation time 99332409588 ps
CPU time 705.56 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 190964 kb
Host smart-e6a57a9b-2bc8-400d-a51f-cdeaf8c2683e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648136955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2648136955
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3840013772
Short name T26
Test name
Test status
Simulation time 2344763238178 ps
CPU time 1406.97 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 191176 kb
Host smart-2132260f-512c-4044-b0b7-ef4a0d8d7947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840013772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3840013772
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.4287588839
Short name T182
Test name
Test status
Simulation time 2004319375075 ps
CPU time 2173.69 seconds
Started Dec 27 12:35:16 PM PST 23
Finished Dec 27 01:11:46 PM PST 23
Peak memory 191156 kb
Host smart-63d2f554-3c79-442a-b793-28f25214eeb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287588839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.4287588839
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2518271242
Short name T198
Test name
Test status
Simulation time 709454262801 ps
CPU time 1688.54 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 01:03:40 PM PST 23
Peak memory 191096 kb
Host smart-00e201b0-6fa1-4676-ac4c-db1adf1917ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518271242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2518271242
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.4155681334
Short name T331
Test name
Test status
Simulation time 162855679403 ps
CPU time 339.23 seconds
Started Dec 27 12:35:09 PM PST 23
Finished Dec 27 12:41:06 PM PST 23
Peak memory 191068 kb
Host smart-8c4e858b-b647-4bb5-a127-293d249658d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155681334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4155681334
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.2116353638
Short name T300
Test name
Test status
Simulation time 714846035560 ps
CPU time 744.24 seconds
Started Dec 27 12:35:52 PM PST 23
Finished Dec 27 12:48:36 PM PST 23
Peak memory 191188 kb
Host smart-03464ddf-4c90-4d32-9d11-d1318ec2f924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116353638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2116353638
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3958929277
Short name T172
Test name
Test status
Simulation time 911263597598 ps
CPU time 727 seconds
Started Dec 27 12:34:55 PM PST 23
Finished Dec 27 12:47:23 PM PST 23
Peak memory 191060 kb
Host smart-b907556a-7c75-4360-a646-8b7b61d3c224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958929277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3958929277
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.325880306
Short name T34
Test name
Test status
Simulation time 462615834609 ps
CPU time 850.9 seconds
Started Dec 27 12:34:55 PM PST 23
Finished Dec 27 12:49:26 PM PST 23
Peak memory 191012 kb
Host smart-07a6a8a6-f8ef-4c64-bc11-9b11c07c9260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325880306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
325880306
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/195.rv_timer_random.3784924154
Short name T268
Test name
Test status
Simulation time 273549698773 ps
CPU time 638.27 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:46:52 PM PST 23
Peak memory 191164 kb
Host smart-646da9ec-bf32-4f02-83e6-49139475dbe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784924154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3784924154
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2649429481
Short name T296
Test name
Test status
Simulation time 854076108915 ps
CPU time 540.85 seconds
Started Dec 27 12:34:59 PM PST 23
Finished Dec 27 12:44:19 PM PST 23
Peak memory 191112 kb
Host smart-6f8d7d38-d5b1-4744-a6ac-e0eded9b1e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649429481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2649429481
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1152978537
Short name T114
Test name
Test status
Simulation time 2000819164789 ps
CPU time 1123.39 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:54:02 PM PST 23
Peak memory 191140 kb
Host smart-3bacba52-c3a0-4d0a-a17f-8f9918d8377e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152978537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1152978537
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/162.rv_timer_random.3618133888
Short name T127
Test name
Test status
Simulation time 423559253482 ps
CPU time 1653.38 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 190964 kb
Host smart-557145d4-bd11-4223-a998-7041ac699dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618133888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3618133888
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.670880346
Short name T340
Test name
Test status
Simulation time 361026865469 ps
CPU time 1262.91 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:56:51 PM PST 23
Peak memory 194364 kb
Host smart-33f40e4c-c1cb-49b8-a274-df2592182788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670880346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.670880346
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.2787472068
Short name T203
Test name
Test status
Simulation time 471695833608 ps
CPU time 195.69 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:38:37 PM PST 23
Peak memory 191084 kb
Host smart-fbe4bdad-eb26-45b2-987e-d87e6f3244cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787472068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2787472068
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.4217910452
Short name T218
Test name
Test status
Simulation time 89770766857 ps
CPU time 136.69 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 191068 kb
Host smart-e76a09b6-9775-443a-ad28-b0ec58c9a2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217910452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.4217910452
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3674608581
Short name T259
Test name
Test status
Simulation time 211753575183 ps
CPU time 374.4 seconds
Started Dec 27 12:35:50 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 191024 kb
Host smart-5a417df7-3edc-4226-a77c-8adbf40dbc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674608581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3674608581
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1357440878
Short name T286
Test name
Test status
Simulation time 496749810456 ps
CPU time 261.52 seconds
Started Dec 27 12:35:08 PM PST 23
Finished Dec 27 12:39:47 PM PST 23
Peak memory 182824 kb
Host smart-2f96a8c2-85f9-4fd1-9c4b-2a853d0d96f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357440878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1357440878
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2728733081
Short name T154
Test name
Test status
Simulation time 193294709908 ps
CPU time 984.1 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:52:02 PM PST 23
Peak memory 191132 kb
Host smart-6e7ebdc5-de7a-4a1f-97d5-927d2a9188a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728733081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2728733081
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3079876279
Short name T143
Test name
Test status
Simulation time 814068467678 ps
CPU time 1136.74 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:54:44 PM PST 23
Peak memory 190980 kb
Host smart-e869ce64-d0e8-4120-8fca-c08aa54ce553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079876279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3079876279
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.404293511
Short name T122
Test name
Test status
Simulation time 1047600235040 ps
CPU time 597.99 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:45:29 PM PST 23
Peak memory 191024 kb
Host smart-1b1a2f52-ca09-441f-84b7-98c1808bf500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404293511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.404293511
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1138364101
Short name T164
Test name
Test status
Simulation time 766547778027 ps
CPU time 1168.17 seconds
Started Dec 27 12:34:40 PM PST 23
Finished Dec 27 12:54:26 PM PST 23
Peak memory 194100 kb
Host smart-39a98a93-0b7f-4116-9615-329f131111f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138364101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1138364101
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.1510436170
Short name T263
Test name
Test status
Simulation time 23116884541 ps
CPU time 238.62 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:39:29 PM PST 23
Peak memory 191112 kb
Host smart-213eedac-5f1e-43a2-8dd5-5c2dca032c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510436170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1510436170
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1484616655
Short name T305
Test name
Test status
Simulation time 127156390396 ps
CPU time 302.95 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:40:57 PM PST 23
Peak memory 191024 kb
Host smart-b5589fa6-54de-4a5b-80a0-20f0cee4d573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484616655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1484616655
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.215170945
Short name T347
Test name
Test status
Simulation time 472336970800 ps
CPU time 389.28 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:42:48 PM PST 23
Peak memory 191068 kb
Host smart-ca1a3069-a29c-4e61-822b-efd986070d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215170945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.215170945
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.4022886272
Short name T254
Test name
Test status
Simulation time 417848075525 ps
CPU time 552.72 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:46:36 PM PST 23
Peak memory 190968 kb
Host smart-65b3c085-4de2-4dd1-bc73-438a9b4f02d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022886272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4022886272
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.2850435412
Short name T191
Test name
Test status
Simulation time 68284566251 ps
CPU time 257.41 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:39:51 PM PST 23
Peak memory 191124 kb
Host smart-b8a9590f-eab4-456d-b115-c6e851dab886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850435412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2850435412
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1730682296
Short name T271
Test name
Test status
Simulation time 430198572531 ps
CPU time 187.68 seconds
Started Dec 27 12:36:33 PM PST 23
Finished Dec 27 12:40:08 PM PST 23
Peak memory 193896 kb
Host smart-e4a41c36-cdfc-48e5-9d8e-7e919a94b054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730682296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1730682296
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.3686054338
Short name T107
Test name
Test status
Simulation time 82252022003 ps
CPU time 60.59 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 191200 kb
Host smart-05d1e96d-6561-4fb3-9a4b-54482b41efc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686054338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3686054338
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1312165437
Short name T105
Test name
Test status
Simulation time 591935382519 ps
CPU time 328.86 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 191076 kb
Host smart-214eb44e-7419-46d7-a45f-88b1c617c07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312165437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1312165437
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1753434937
Short name T28
Test name
Test status
Simulation time 459135530387 ps
CPU time 203.81 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:39:30 PM PST 23
Peak memory 194584 kb
Host smart-5bf7e948-8e39-4f41-be3b-cbd7c20c9554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753434937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1753434937
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.1572254118
Short name T325
Test name
Test status
Simulation time 1101653133861 ps
CPU time 348.9 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:41:34 PM PST 23
Peak memory 191032 kb
Host smart-29a3b01a-b63d-4576-8dc7-df8f7411808a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572254118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1572254118
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3544500506
Short name T342
Test name
Test status
Simulation time 932893886751 ps
CPU time 460.41 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:45:01 PM PST 23
Peak memory 182724 kb
Host smart-fc026e09-660e-40cc-bfda-5b22dae0418b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544500506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3544500506
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1018625445
Short name T309
Test name
Test status
Simulation time 247419066508 ps
CPU time 623.26 seconds
Started Dec 27 12:35:12 PM PST 23
Finished Dec 27 12:45:52 PM PST 23
Peak memory 205784 kb
Host smart-a850e791-f44f-4d16-8292-086cb215730c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018625445 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1018625445
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1134779059
Short name T169
Test name
Test status
Simulation time 1688497995338 ps
CPU time 1047.49 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:53:05 PM PST 23
Peak memory 191160 kb
Host smart-6144ff63-c061-4c78-ae08-c412b75b2636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134779059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1134779059
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1380196948
Short name T213
Test name
Test status
Simulation time 137600237900 ps
CPU time 239.46 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:39:52 PM PST 23
Peak memory 182936 kb
Host smart-58f03f24-7ad0-4779-9fd9-a3077cd0aa5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380196948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1380196948
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/76.rv_timer_random.3290828883
Short name T152
Test name
Test status
Simulation time 795672857149 ps
CPU time 1663.58 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 193664 kb
Host smart-a049b874-0509-4831-a852-42959eb458aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290828883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3290828883
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3305000433
Short name T93
Test name
Test status
Simulation time 53384397 ps
CPU time 0.79 seconds
Started Dec 27 01:09:18 PM PST 23
Finished Dec 27 01:09:26 PM PST 23
Peak memory 192192 kb
Host smart-4c351c2f-b975-4cf8-80b4-3792f7027c21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305000433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3305000433
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.508725510
Short name T97
Test name
Test status
Simulation time 126244333 ps
CPU time 1.33 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 183564 kb
Host smart-65ad03fe-35be-42f7-bced-c2ddd89c00a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508725510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.508725510
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/103.rv_timer_random.1697265997
Short name T302
Test name
Test status
Simulation time 205379829513 ps
CPU time 94.54 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:37:19 PM PST 23
Peak memory 191004 kb
Host smart-fd15b373-066b-44aa-9422-b78d0a9129cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697265997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1697265997
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1512594653
Short name T606
Test name
Test status
Simulation time 653033170319 ps
CPU time 184.07 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:39:00 PM PST 23
Peak memory 182808 kb
Host smart-b3b943c4-7f93-42cd-b8a3-8c4201c16210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512594653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1512594653
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2675896058
Short name T241
Test name
Test status
Simulation time 446601851229 ps
CPU time 324.32 seconds
Started Dec 27 12:35:12 PM PST 23
Finished Dec 27 12:40:54 PM PST 23
Peak memory 194244 kb
Host smart-6b564b5d-c90e-430a-bcff-c8e690557a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675896058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2675896058
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.782212178
Short name T111
Test name
Test status
Simulation time 107662156666 ps
CPU time 244.65 seconds
Started Dec 27 12:34:47 PM PST 23
Finished Dec 27 12:39:12 PM PST 23
Peak memory 191048 kb
Host smart-da5f1c4b-e80d-4c6d-9236-2998281df820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782212178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.782212178
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2094821387
Short name T142
Test name
Test status
Simulation time 170648582681 ps
CPU time 1552.19 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 01:01:37 PM PST 23
Peak memory 191028 kb
Host smart-89690281-ea8b-4a9d-a90c-5f29f9ce3994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094821387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2094821387
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.474304506
Short name T208
Test name
Test status
Simulation time 412309247000 ps
CPU time 166.94 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:38:36 PM PST 23
Peak memory 191028 kb
Host smart-e3c71fa6-012f-4dde-abf5-af2578e0bd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474304506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.474304506
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4102492482
Short name T9
Test name
Test status
Simulation time 102944982608 ps
CPU time 164.15 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:38:23 PM PST 23
Peak memory 191120 kb
Host smart-90b65edc-25f1-4dbe-a65d-5e61a9683d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102492482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4102492482
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3485828766
Short name T249
Test name
Test status
Simulation time 75795322178 ps
CPU time 148.27 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:38:17 PM PST 23
Peak memory 191008 kb
Host smart-c4d3f10a-4837-4876-a229-7bdbf79dd198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485828766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3485828766
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.504547069
Short name T363
Test name
Test status
Simulation time 388568692807 ps
CPU time 457.12 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:43:15 PM PST 23
Peak memory 191148 kb
Host smart-d243f9fa-402c-4a5d-88ee-b7ebe6d21230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504547069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.504547069
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.3978415311
Short name T361
Test name
Test status
Simulation time 86130827641 ps
CPU time 429.28 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:43:39 PM PST 23
Peak memory 190544 kb
Host smart-7ab2bca7-93aa-42a9-9edc-408e3e908b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978415311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3978415311
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.1148895330
Short name T155
Test name
Test status
Simulation time 425786449455 ps
CPU time 436.52 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 191032 kb
Host smart-ba633b95-1d13-4f8b-ae92-199880d16b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148895330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1148895330
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2970293102
Short name T608
Test name
Test status
Simulation time 119683943993 ps
CPU time 500.09 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:43:39 PM PST 23
Peak memory 191200 kb
Host smart-d61b5d6b-405b-40c4-8618-4540376ad9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970293102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2970293102
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3229414219
Short name T171
Test name
Test status
Simulation time 169992936719 ps
CPU time 2100.27 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 01:10:35 PM PST 23
Peak memory 191048 kb
Host smart-23c72afd-2493-45fa-83be-ae5554d44ca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229414219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3229414219
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.1933917499
Short name T285
Test name
Test status
Simulation time 574103321967 ps
CPU time 197.75 seconds
Started Dec 27 12:34:39 PM PST 23
Finished Dec 27 12:38:14 PM PST 23
Peak memory 191032 kb
Host smart-2031533e-3b30-4abf-b6b6-f6cd35aecb25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933917499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1933917499
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.2404391931
Short name T187
Test name
Test status
Simulation time 243365903026 ps
CPU time 368.92 seconds
Started Dec 27 12:35:52 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 193200 kb
Host smart-359a58fd-71e5-4d8a-9c62-74f8ad296af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404391931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2404391931
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1551482087
Short name T274
Test name
Test status
Simulation time 467198744453 ps
CPU time 921.07 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:51:12 PM PST 23
Peak memory 191036 kb
Host smart-4f1d7840-e24f-4391-822d-c0d636de598c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551482087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1551482087
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1696013006
Short name T190
Test name
Test status
Simulation time 2017075454120 ps
CPU time 788.18 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:48:57 PM PST 23
Peak memory 191036 kb
Host smart-9ae041fd-772a-402a-89d1-5ba22f3c6370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696013006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1696013006
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2861022462
Short name T299
Test name
Test status
Simulation time 57613977608 ps
CPU time 100.03 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 192072 kb
Host smart-3e10f6f6-5d15-49d2-af0d-e9db6e3c3ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861022462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2861022462
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2696314097
Short name T368
Test name
Test status
Simulation time 64240502631 ps
CPU time 25.95 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 182844 kb
Host smart-37bb8cc6-0957-43ac-a797-f16c54bed143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696314097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2696314097
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.4271066546
Short name T147
Test name
Test status
Simulation time 750000665926 ps
CPU time 526.1 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:44:32 PM PST 23
Peak memory 190992 kb
Host smart-2f6047b6-3c02-4371-955d-6aa241c87dab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271066546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4271066546
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3059739902
Short name T138
Test name
Test status
Simulation time 11140302641 ps
CPU time 64.73 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:37:12 PM PST 23
Peak memory 191068 kb
Host smart-c2901b8e-f0cc-4d7c-834b-1d7615345578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059739902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3059739902
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1651888883
Short name T239
Test name
Test status
Simulation time 217533476413 ps
CPU time 318.19 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:40:57 PM PST 23
Peak memory 191072 kb
Host smart-15c549da-f3fe-42fa-84b3-9396d28a5ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651888883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1651888883
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2247518778
Short name T329
Test name
Test status
Simulation time 63041581901 ps
CPU time 1470.07 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 01:00:16 PM PST 23
Peak memory 191040 kb
Host smart-3077d25e-aa6e-4f9b-8bae-0e66b2925095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247518778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2247518778
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.236988594
Short name T140
Test name
Test status
Simulation time 1815136879 ps
CPU time 3.83 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:35:48 PM PST 23
Peak memory 182824 kb
Host smart-204b1d32-b26e-4f5d-baac-36a5b6c2272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236988594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.236988594
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3396255203
Short name T205
Test name
Test status
Simulation time 120515052512 ps
CPU time 1241.54 seconds
Started Dec 27 12:36:22 PM PST 23
Finished Dec 27 12:57:25 PM PST 23
Peak memory 191944 kb
Host smart-0823aff1-464a-4a88-9c8e-c43683b041e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396255203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3396255203
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3723452149
Short name T120
Test name
Test status
Simulation time 139961420473 ps
CPU time 190.09 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 194272 kb
Host smart-5669be9d-ad37-494d-a54f-f306c40fbb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723452149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3723452149
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3722148369
Short name T232
Test name
Test status
Simulation time 392394627279 ps
CPU time 188.21 seconds
Started Dec 27 12:35:26 PM PST 23
Finished Dec 27 12:38:48 PM PST 23
Peak memory 191068 kb
Host smart-6f1afc22-e951-4fe3-9c04-fce7f4d2fe31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722148369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3722148369
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.135772502
Short name T290
Test name
Test status
Simulation time 67769730268 ps
CPU time 388.53 seconds
Started Dec 27 12:35:45 PM PST 23
Finished Dec 27 12:42:32 PM PST 23
Peak memory 190952 kb
Host smart-349f1937-233b-4ab1-953a-79e521d3ea88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135772502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.135772502
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.261660137
Short name T206
Test name
Test status
Simulation time 644510477311 ps
CPU time 518.37 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:44:20 PM PST 23
Peak memory 191068 kb
Host smart-678560fb-b173-4df5-8a21-dc98aa166246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261660137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.261660137
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2740235120
Short name T311
Test name
Test status
Simulation time 98003014179 ps
CPU time 89.26 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 191068 kb
Host smart-c9485cd6-abc7-4964-8bd6-1fe56ded13ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740235120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2740235120
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3077600199
Short name T262
Test name
Test status
Simulation time 137783679809 ps
CPU time 140.56 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:38:36 PM PST 23
Peak memory 193088 kb
Host smart-6a289327-5bb3-434f-b3d6-496769ce5da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077600199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3077600199
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3197537534
Short name T100
Test name
Test status
Simulation time 840434690582 ps
CPU time 662.02 seconds
Started Dec 27 12:35:43 PM PST 23
Finished Dec 27 12:47:03 PM PST 23
Peak memory 191164 kb
Host smart-ce6727c7-9617-4324-98ff-97d782e3aea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197537534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3197537534
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.494389946
Short name T280
Test name
Test status
Simulation time 249952975015 ps
CPU time 319.39 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:40:57 PM PST 23
Peak memory 191080 kb
Host smart-201ffa80-5387-4536-a11b-508a4794bf8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494389946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.494389946
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2597877170
Short name T349
Test name
Test status
Simulation time 131945524594 ps
CPU time 241.13 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:39:33 PM PST 23
Peak memory 182800 kb
Host smart-500494a1-d1e8-45dc-9538-1b6037974679
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597877170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2597877170
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4096203392
Short name T360
Test name
Test status
Simulation time 57269826512 ps
CPU time 31.45 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 182760 kb
Host smart-36d0bfba-25e5-4813-8816-1abf889f7558
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096203392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4096203392
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1442432277
Short name T139
Test name
Test status
Simulation time 82872003266 ps
CPU time 974.64 seconds
Started Dec 27 12:34:33 PM PST 23
Finished Dec 27 12:51:05 PM PST 23
Peak memory 191160 kb
Host smart-64b628a4-79d7-4b61-8164-6c5ead3bdb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442432277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1442432277
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1286365393
Short name T307
Test name
Test status
Simulation time 1073343344517 ps
CPU time 550.87 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:45:04 PM PST 23
Peak memory 182780 kb
Host smart-49688634-8c4f-4042-90eb-916d093aad45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286365393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1286365393
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1284522768
Short name T201
Test name
Test status
Simulation time 593671760192 ps
CPU time 148.74 seconds
Started Dec 27 12:37:04 PM PST 23
Finished Dec 27 12:39:57 PM PST 23
Peak memory 182732 kb
Host smart-fd717f53-6f61-4000-87bd-786920c3c683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284522768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1284522768
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_random.2169640032
Short name T175
Test name
Test status
Simulation time 67729111897 ps
CPU time 114.39 seconds
Started Dec 27 12:35:26 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 191144 kb
Host smart-33fcd792-31ec-42e0-bf05-b45e4983c13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169640032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2169640032
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.3283125553
Short name T273
Test name
Test status
Simulation time 72144657456 ps
CPU time 133.04 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:37:50 PM PST 23
Peak memory 191040 kb
Host smart-be95042a-bde9-4e3e-b023-c582192bc0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283125553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3283125553
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3050403468
Short name T365
Test name
Test status
Simulation time 33150666593 ps
CPU time 50.07 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:36:56 PM PST 23
Peak memory 191032 kb
Host smart-4005f138-ad3e-4a60-8e43-f8393869dbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050403468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3050403468
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.2617475611
Short name T261
Test name
Test status
Simulation time 21904855988 ps
CPU time 38.21 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:45 PM PST 23
Peak memory 191040 kb
Host smart-f83f7294-c4a1-4b54-bc09-d641f2b42819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617475611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2617475611
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.391165964
Short name T11
Test name
Test status
Simulation time 40791129494 ps
CPU time 267.77 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:40:15 PM PST 23
Peak memory 194032 kb
Host smart-d4b44faf-f8e7-4f6e-a850-44ea5e6ec79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391165964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.391165964
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2179012996
Short name T148
Test name
Test status
Simulation time 898964205587 ps
CPU time 476.12 seconds
Started Dec 27 12:34:53 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 182824 kb
Host smart-2fb4a722-0d06-402a-8936-a7a0105100fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179012996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2179012996
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/54.rv_timer_random.4094456419
Short name T338
Test name
Test status
Simulation time 150533916623 ps
CPU time 742.07 seconds
Started Dec 27 12:35:02 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 191032 kb
Host smart-04fc8363-f68d-43b5-b5c1-4eebd6b3487c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094456419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4094456419
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1646363102
Short name T333
Test name
Test status
Simulation time 552179647854 ps
CPU time 289.33 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:40:27 PM PST 23
Peak memory 191036 kb
Host smart-62aae81e-87e1-4fcf-8f7f-1db1ad585ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646363102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1646363102
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.820178569
Short name T246
Test name
Test status
Simulation time 401672147681 ps
CPU time 278.55 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:40:16 PM PST 23
Peak memory 190792 kb
Host smart-432b8867-31f9-4229-9605-cf8e26fcfa2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820178569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.820178569
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.1775424721
Short name T123
Test name
Test status
Simulation time 347419128122 ps
CPU time 110.6 seconds
Started Dec 27 12:34:34 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 194212 kb
Host smart-59d063f7-e259-46a2-897e-030b720dde17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775424721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1775424721
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2527966867
Short name T200
Test name
Test status
Simulation time 26872850789 ps
CPU time 16.21 seconds
Started Dec 27 12:34:54 PM PST 23
Finished Dec 27 12:35:31 PM PST 23
Peak memory 182828 kb
Host smart-b5ea109e-8f34-4484-96db-db824cff6b59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527966867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2527966867
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3269792353
Short name T58
Test name
Test status
Simulation time 19855570 ps
CPU time 0.72 seconds
Started Dec 27 01:09:30 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 192468 kb
Host smart-997f3a76-53be-4bad-9c10-c3238a145044
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269792353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3269792353
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.514239318
Short name T415
Test name
Test status
Simulation time 96203817 ps
CPU time 3.11 seconds
Started Dec 27 01:09:37 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 193972 kb
Host smart-e33c3b37-b223-4295-bf56-ed16b25ebaff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514239318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.514239318
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2197034902
Short name T67
Test name
Test status
Simulation time 15273710 ps
CPU time 0.57 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:47 PM PST 23
Peak memory 183212 kb
Host smart-b6abca8a-dac3-46a4-b17a-9d3ec193c132
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197034902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2197034902
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3111840508
Short name T477
Test name
Test status
Simulation time 41837695 ps
CPU time 1.19 seconds
Started Dec 27 01:09:22 PM PST 23
Finished Dec 27 01:09:32 PM PST 23
Peak memory 198136 kb
Host smart-8aacd729-7a9f-42bb-bc10-e485be1b60ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111840508 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3111840508
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.109558399
Short name T428
Test name
Test status
Simulation time 14641081 ps
CPU time 0.56 seconds
Started Dec 27 01:09:33 PM PST 23
Finished Dec 27 01:09:41 PM PST 23
Peak memory 182788 kb
Host smart-368d0bf2-8111-40d7-87d5-cd97933f41c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109558399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.109558399
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1268459002
Short name T476
Test name
Test status
Simulation time 15123802 ps
CPU time 0.54 seconds
Started Dec 27 01:09:22 PM PST 23
Finished Dec 27 01:09:31 PM PST 23
Peak memory 182128 kb
Host smart-61f155ab-34c2-41a2-8fd5-c717094606a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268459002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1268459002
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2038252614
Short name T432
Test name
Test status
Simulation time 64348902 ps
CPU time 0.69 seconds
Started Dec 27 01:09:36 PM PST 23
Finished Dec 27 01:09:44 PM PST 23
Peak memory 193492 kb
Host smart-b6f64ba6-5399-4ce2-a232-65a2ae857556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038252614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2038252614
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.353995818
Short name T40
Test name
Test status
Simulation time 229446875 ps
CPU time 1.39 seconds
Started Dec 27 01:09:22 PM PST 23
Finished Dec 27 01:09:32 PM PST 23
Peak memory 198080 kb
Host smart-861da7be-0eea-46e6-9980-2cc842deb509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353995818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.353995818
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3942655928
Short name T96
Test name
Test status
Simulation time 97192151 ps
CPU time 1.08 seconds
Started Dec 27 01:09:31 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 195124 kb
Host smart-adb7842a-c4f9-49dc-9ec3-08d3e5e1780b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942655928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3942655928
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3301689707
Short name T63
Test name
Test status
Simulation time 61898969 ps
CPU time 0.8 seconds
Started Dec 27 01:09:18 PM PST 23
Finished Dec 27 01:09:27 PM PST 23
Peak memory 183224 kb
Host smart-a13ac49b-12c5-47a0-bf64-03408db27eee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301689707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3301689707
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3264851453
Short name T453
Test name
Test status
Simulation time 371522461 ps
CPU time 2.45 seconds
Started Dec 27 01:09:21 PM PST 23
Finished Dec 27 01:09:32 PM PST 23
Peak memory 192752 kb
Host smart-8bd5c829-9835-4d47-87ea-b3551e35c917
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264851453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3264851453
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3320621005
Short name T423
Test name
Test status
Simulation time 54125845 ps
CPU time 0.56 seconds
Started Dec 27 01:09:28 PM PST 23
Finished Dec 27 01:09:37 PM PST 23
Peak memory 183248 kb
Host smart-bdb5a554-1a14-45ad-bdd9-82f129663714
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320621005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3320621005
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4209212420
Short name T390
Test name
Test status
Simulation time 37424847 ps
CPU time 0.6 seconds
Started Dec 27 01:09:46 PM PST 23
Finished Dec 27 01:09:53 PM PST 23
Peak memory 193508 kb
Host smart-ee630c1a-1b77-4f20-b035-e7847eb02cb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209212420 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4209212420
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1819931067
Short name T445
Test name
Test status
Simulation time 26895559 ps
CPU time 0.56 seconds
Started Dec 27 01:09:26 PM PST 23
Finished Dec 27 01:09:36 PM PST 23
Peak memory 183260 kb
Host smart-dcedcf35-354c-4067-85f4-062f75ef692a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819931067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1819931067
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2732870806
Short name T474
Test name
Test status
Simulation time 98604405 ps
CPU time 0.53 seconds
Started Dec 27 01:09:34 PM PST 23
Finished Dec 27 01:09:43 PM PST 23
Peak memory 182008 kb
Host smart-bf664653-3cf2-4d0b-89ac-8956d4fdb59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732870806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2732870806
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1701249270
Short name T413
Test name
Test status
Simulation time 174917590 ps
CPU time 1.48 seconds
Started Dec 27 01:09:20 PM PST 23
Finished Dec 27 01:09:29 PM PST 23
Peak memory 198020 kb
Host smart-c5ae217a-7de9-4ea7-be89-79bb6f7cf5f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701249270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1701249270
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.10946112
Short name T431
Test name
Test status
Simulation time 23288449 ps
CPU time 0.68 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:47 PM PST 23
Peak memory 195096 kb
Host smart-913bf78b-957a-46f9-a3f5-31c51fb74d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10946112 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.10946112
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.979104340
Short name T65
Test name
Test status
Simulation time 12249884 ps
CPU time 0.61 seconds
Started Dec 27 01:09:39 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 182888 kb
Host smart-2e7063fd-8ad2-4abf-a7b0-b8755f5e378d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979104340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.979104340
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.100287053
Short name T383
Test name
Test status
Simulation time 14802881 ps
CPU time 0.54 seconds
Started Dec 27 01:10:17 PM PST 23
Finished Dec 27 01:10:24 PM PST 23
Peak memory 181952 kb
Host smart-f580c1f6-756e-47db-8028-206fdb560bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100287053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.100287053
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3791883211
Short name T89
Test name
Test status
Simulation time 17594146 ps
CPU time 0.69 seconds
Started Dec 27 01:09:50 PM PST 23
Finished Dec 27 01:09:57 PM PST 23
Peak memory 192192 kb
Host smart-cbc4ae94-3757-45cd-bcc3-4c06c2903970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791883211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3791883211
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1758698406
Short name T457
Test name
Test status
Simulation time 194122007 ps
CPU time 1.23 seconds
Started Dec 27 01:09:43 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 197960 kb
Host smart-72ff7e5c-a7a3-47bd-8843-5ea5334a96ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758698406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1758698406
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3349578803
Short name T442
Test name
Test status
Simulation time 58614255 ps
CPU time 0.8 seconds
Started Dec 27 01:09:54 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 193816 kb
Host smart-9d911aab-38cb-4825-a71c-b11f2517cecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349578803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3349578803
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2941007934
Short name T50
Test name
Test status
Simulation time 65250142 ps
CPU time 0.81 seconds
Started Dec 27 01:09:47 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 194428 kb
Host smart-495b4d07-0814-499a-93c0-98b089a15d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941007934 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2941007934
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.549206198
Short name T49
Test name
Test status
Simulation time 17280602 ps
CPU time 0.58 seconds
Started Dec 27 01:09:28 PM PST 23
Finished Dec 27 01:09:37 PM PST 23
Peak memory 183332 kb
Host smart-b894e13f-8c2d-402c-9234-f52a1e6c3d98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549206198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.549206198
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3738400631
Short name T398
Test name
Test status
Simulation time 22111079 ps
CPU time 0.52 seconds
Started Dec 27 01:09:32 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 182088 kb
Host smart-e9d44179-e398-4a6c-8090-e9ee69973188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738400631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3738400631
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2956174798
Short name T451
Test name
Test status
Simulation time 18392363 ps
CPU time 0.68 seconds
Started Dec 27 01:09:32 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 192148 kb
Host smart-3a03b412-ceff-454f-be07-1047e20b72c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956174798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2956174798
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3270156404
Short name T406
Test name
Test status
Simulation time 429113150 ps
CPU time 2.26 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:49 PM PST 23
Peak memory 198124 kb
Host smart-2bda1271-0449-4d86-9c82-b3154b38051c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270156404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3270156404
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.332195515
Short name T44
Test name
Test status
Simulation time 119702624 ps
CPU time 1.35 seconds
Started Dec 27 01:09:42 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 195716 kb
Host smart-b19fdd4b-b850-41bd-b130-593209c1a734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332195515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.332195515
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.329063087
Short name T386
Test name
Test status
Simulation time 75544637 ps
CPU time 0.93 seconds
Started Dec 27 01:09:51 PM PST 23
Finished Dec 27 01:09:58 PM PST 23
Peak memory 197796 kb
Host smart-d907bd4a-ab9d-460c-9a0f-4b40bbf6394e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329063087 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.329063087
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2924965790
Short name T446
Test name
Test status
Simulation time 54828990 ps
CPU time 0.59 seconds
Started Dec 27 01:09:26 PM PST 23
Finished Dec 27 01:09:36 PM PST 23
Peak memory 183272 kb
Host smart-f440d0f8-4895-4ebb-b483-fb766873a702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924965790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2924965790
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2484036128
Short name T417
Test name
Test status
Simulation time 21524161 ps
CPU time 0.54 seconds
Started Dec 27 01:09:48 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 182852 kb
Host smart-5bddaaa4-6fd1-4c75-a24a-5bfc360fbf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484036128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2484036128
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1472465627
Short name T48
Test name
Test status
Simulation time 158659743 ps
CPU time 0.76 seconds
Started Dec 27 01:09:35 PM PST 23
Finished Dec 27 01:09:43 PM PST 23
Peak memory 192240 kb
Host smart-bc0f508d-fa42-4b5e-9cdc-59673196a202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472465627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1472465627
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.120163477
Short name T447
Test name
Test status
Simulation time 55325078 ps
CPU time 2.75 seconds
Started Dec 27 01:09:52 PM PST 23
Finished Dec 27 01:10:01 PM PST 23
Peak memory 198052 kb
Host smart-91fad905-24f3-40c5-9223-4fd413eb32ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120163477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.120163477
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1644902865
Short name T77
Test name
Test status
Simulation time 81557280 ps
CPU time 1.09 seconds
Started Dec 27 01:09:45 PM PST 23
Finished Dec 27 01:09:54 PM PST 23
Peak memory 195304 kb
Host smart-835b8b6e-0bef-42c5-be05-5444970dbe2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644902865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1644902865
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1842640592
Short name T391
Test name
Test status
Simulation time 169808914 ps
CPU time 0.64 seconds
Started Dec 27 01:10:02 PM PST 23
Finished Dec 27 01:10:06 PM PST 23
Peak memory 194744 kb
Host smart-a755e490-8fd1-4df9-bf27-07b6b729f354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842640592 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1842640592
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.634469160
Short name T61
Test name
Test status
Simulation time 24966455 ps
CPU time 0.57 seconds
Started Dec 27 01:09:30 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 183192 kb
Host smart-9874b266-0957-4bf3-ba4e-0a36104b8223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634469160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.634469160
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.41823653
Short name T416
Test name
Test status
Simulation time 17329214 ps
CPU time 0.57 seconds
Started Dec 27 01:09:59 PM PST 23
Finished Dec 27 01:10:04 PM PST 23
Peak memory 182972 kb
Host smart-c8de65d3-64b6-4ff6-8716-fe811fc5b84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41823653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.41823653
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3638440513
Short name T475
Test name
Test status
Simulation time 58081543 ps
CPU time 0.76 seconds
Started Dec 27 01:09:48 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 193660 kb
Host smart-7ae356c5-a143-40ba-b095-3687af54cd5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638440513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3638440513
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2976323068
Short name T458
Test name
Test status
Simulation time 87344381 ps
CPU time 1.19 seconds
Started Dec 27 01:09:52 PM PST 23
Finished Dec 27 01:09:59 PM PST 23
Peak memory 197956 kb
Host smart-d2e31b36-df28-4337-95fb-1d633d1f569f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976323068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2976323068
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2308068907
Short name T99
Test name
Test status
Simulation time 245441661 ps
CPU time 1.42 seconds
Started Dec 27 01:09:29 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 195456 kb
Host smart-5d153ade-c2cf-4129-9e3f-3ae98989b498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308068907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2308068907
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4281458856
Short name T472
Test name
Test status
Simulation time 19721676 ps
CPU time 0.94 seconds
Started Dec 27 01:09:43 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 197876 kb
Host smart-085bbc44-04f1-4944-aa20-53cf990fc115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281458856 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4281458856
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1740202809
Short name T68
Test name
Test status
Simulation time 13878588 ps
CPU time 0.56 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:47 PM PST 23
Peak memory 183272 kb
Host smart-0ec659f1-99f8-4af0-803c-228152860603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740202809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1740202809
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.844540511
Short name T437
Test name
Test status
Simulation time 77741405 ps
CPU time 0.55 seconds
Started Dec 27 01:09:46 PM PST 23
Finished Dec 27 01:09:54 PM PST 23
Peak memory 182980 kb
Host smart-b57348bf-579a-46bc-9bda-13ce09762ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844540511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.844540511
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4269402487
Short name T460
Test name
Test status
Simulation time 68099231 ps
CPU time 0.67 seconds
Started Dec 27 01:09:57 PM PST 23
Finished Dec 27 01:10:02 PM PST 23
Peak memory 192540 kb
Host smart-20dc7be0-8a53-43a0-a432-7d3611bbe178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269402487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4269402487
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2107340858
Short name T464
Test name
Test status
Simulation time 87439051 ps
CPU time 1.94 seconds
Started Dec 27 01:09:52 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 198016 kb
Host smart-e96ce309-29bb-4fce-9e43-583aea4243be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107340858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2107340858
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3935204185
Short name T461
Test name
Test status
Simulation time 83355331 ps
CPU time 1.14 seconds
Started Dec 27 01:09:56 PM PST 23
Finished Dec 27 01:10:02 PM PST 23
Peak memory 195404 kb
Host smart-cec024ba-5156-4300-a526-c00b969411e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935204185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3935204185
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1463773807
Short name T454
Test name
Test status
Simulation time 91905710 ps
CPU time 1.58 seconds
Started Dec 27 01:09:42 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 198128 kb
Host smart-1817bfe7-06c6-420b-b52d-b1d91d825885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463773807 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1463773807
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1201401457
Short name T81
Test name
Test status
Simulation time 18744847 ps
CPU time 0.56 seconds
Started Dec 27 01:09:53 PM PST 23
Finished Dec 27 01:09:59 PM PST 23
Peak memory 183144 kb
Host smart-20d5c339-e7bc-45cf-a77f-dabe0ecc681e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201401457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1201401457
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2958021287
Short name T381
Test name
Test status
Simulation time 15473618 ps
CPU time 0.55 seconds
Started Dec 27 01:09:45 PM PST 23
Finished Dec 27 01:09:53 PM PST 23
Peak memory 182892 kb
Host smart-f60c96e0-35d6-4ca5-9e60-8776eabbe2fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958021287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2958021287
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.699032069
Short name T440
Test name
Test status
Simulation time 106548283 ps
CPU time 0.61 seconds
Started Dec 27 01:10:01 PM PST 23
Finished Dec 27 01:10:06 PM PST 23
Peak memory 191708 kb
Host smart-a7703517-b829-41bc-8255-7c7b40bcebea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699032069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.699032069
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4279941407
Short name T43
Test name
Test status
Simulation time 202926846 ps
CPU time 1.16 seconds
Started Dec 27 01:09:40 PM PST 23
Finished Dec 27 01:09:49 PM PST 23
Peak memory 197636 kb
Host smart-214bcdb2-023b-4841-9033-c573094fa51f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279941407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4279941407
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1543868919
Short name T465
Test name
Test status
Simulation time 50252920 ps
CPU time 0.83 seconds
Started Dec 27 01:09:51 PM PST 23
Finished Dec 27 01:09:58 PM PST 23
Peak memory 193744 kb
Host smart-afefaae6-d20c-4436-9741-48860e86563c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543868919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1543868919
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4084483235
Short name T422
Test name
Test status
Simulation time 36438853 ps
CPU time 0.75 seconds
Started Dec 27 01:10:00 PM PST 23
Finished Dec 27 01:10:06 PM PST 23
Peak memory 195704 kb
Host smart-c3371b8d-6f8d-4f3c-a859-05e102c0bf07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084483235 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4084483235
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4090686018
Short name T82
Test name
Test status
Simulation time 12949118 ps
CPU time 0.58 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:47 PM PST 23
Peak memory 183284 kb
Host smart-0c7d1447-502c-4f36-855f-e39ecd1be3a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090686018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4090686018
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4271329089
Short name T86
Test name
Test status
Simulation time 15730993 ps
CPU time 0.53 seconds
Started Dec 27 01:09:50 PM PST 23
Finished Dec 27 01:09:56 PM PST 23
Peak memory 182068 kb
Host smart-60468e30-fb16-4ce6-9b46-793aab55c8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271329089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4271329089
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4085610890
Short name T90
Test name
Test status
Simulation time 20074490 ps
CPU time 0.75 seconds
Started Dec 27 01:09:58 PM PST 23
Finished Dec 27 01:10:03 PM PST 23
Peak memory 193648 kb
Host smart-140d4fec-fd7b-438b-86df-7f17a4137f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085610890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.4085610890
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3329460001
Short name T459
Test name
Test status
Simulation time 95409455 ps
CPU time 1.43 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 197812 kb
Host smart-6ae286a9-060e-4cea-9224-28c9b695b830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329460001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3329460001
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2832841465
Short name T33
Test name
Test status
Simulation time 83944820 ps
CPU time 0.87 seconds
Started Dec 27 01:10:01 PM PST 23
Finished Dec 27 01:10:06 PM PST 23
Peak memory 197140 kb
Host smart-3b717ba5-005f-4d3f-84a4-3763623b5cd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832841465 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2832841465
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1067029839
Short name T434
Test name
Test status
Simulation time 55271781 ps
CPU time 0.52 seconds
Started Dec 27 01:09:39 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 182680 kb
Host smart-9ebd0fa2-ee53-4071-81cf-36adaad91f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067029839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1067029839
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1496303398
Short name T78
Test name
Test status
Simulation time 13042298 ps
CPU time 0.53 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 182060 kb
Host smart-261623c7-7d88-4ab8-a8a5-811dac8c755d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496303398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1496303398
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2115949071
Short name T64
Test name
Test status
Simulation time 13606233 ps
CPU time 0.6 seconds
Started Dec 27 01:10:11 PM PST 23
Finished Dec 27 01:10:15 PM PST 23
Peak memory 191628 kb
Host smart-52527919-6d28-484c-a3bf-e714f3f3c3a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115949071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2115949071
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.862890944
Short name T39
Test name
Test status
Simulation time 34478143 ps
CPU time 0.94 seconds
Started Dec 27 01:09:43 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 196484 kb
Host smart-311b46c0-49f8-4337-b6ac-848982d3f895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862890944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.862890944
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1242529643
Short name T47
Test name
Test status
Simulation time 86692253 ps
CPU time 1.14 seconds
Started Dec 27 01:09:49 PM PST 23
Finished Dec 27 01:09:56 PM PST 23
Peak memory 195256 kb
Host smart-21d59bc6-5d3d-4c8f-a0cb-e9fbe954807e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242529643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1242529643
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4175247883
Short name T418
Test name
Test status
Simulation time 76169575 ps
CPU time 1.05 seconds
Started Dec 27 01:09:47 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 197880 kb
Host smart-d50ed0cf-e758-42f6-a9a1-b3829b31655b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175247883 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4175247883
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2513593696
Short name T73
Test name
Test status
Simulation time 39481279 ps
CPU time 0.54 seconds
Started Dec 27 01:09:48 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 183168 kb
Host smart-fe4e0427-abc9-4196-8e12-47e3069c525b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513593696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2513593696
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2615426526
Short name T53
Test name
Test status
Simulation time 58507442 ps
CPU time 0.56 seconds
Started Dec 27 01:10:00 PM PST 23
Finished Dec 27 01:10:05 PM PST 23
Peak memory 182940 kb
Host smart-91cec8ce-a084-4020-b4ba-df47bd22f67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615426526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2615426526
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1570056482
Short name T60
Test name
Test status
Simulation time 16433712 ps
CPU time 0.6 seconds
Started Dec 27 01:09:53 PM PST 23
Finished Dec 27 01:09:59 PM PST 23
Peak memory 192472 kb
Host smart-88ccf553-95a6-43d9-adcb-2f410f1bbd08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570056482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1570056482
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2281305739
Short name T403
Test name
Test status
Simulation time 372401524 ps
CPU time 3.09 seconds
Started Dec 27 01:10:04 PM PST 23
Finished Dec 27 01:10:11 PM PST 23
Peak memory 198028 kb
Host smart-ceb8f6c4-24e5-4cd7-a791-144e47751539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281305739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2281305739
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1381616987
Short name T83
Test name
Test status
Simulation time 351020877 ps
CPU time 1.28 seconds
Started Dec 27 01:09:56 PM PST 23
Finished Dec 27 01:10:02 PM PST 23
Peak memory 183472 kb
Host smart-18fdc083-a29b-41f3-8978-5074e8d87d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381616987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1381616987
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.820555589
Short name T59
Test name
Test status
Simulation time 65903675 ps
CPU time 1 seconds
Started Dec 27 01:09:53 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 197876 kb
Host smart-39a13316-3631-4b99-8e1a-7f971c6553b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820555589 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.820555589
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.336715141
Short name T17
Test name
Test status
Simulation time 27560981 ps
CPU time 0.55 seconds
Started Dec 27 01:09:53 PM PST 23
Finished Dec 27 01:09:59 PM PST 23
Peak memory 183272 kb
Host smart-86aebfd6-fc4b-4522-a4e6-890403d82fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336715141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.336715141
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1104848765
Short name T421
Test name
Test status
Simulation time 13721662 ps
CPU time 0.57 seconds
Started Dec 27 01:09:49 PM PST 23
Finished Dec 27 01:09:56 PM PST 23
Peak memory 182072 kb
Host smart-24678f38-997a-40f1-88ec-ad0b3bc45f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104848765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1104848765
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4242882659
Short name T427
Test name
Test status
Simulation time 88265682 ps
CPU time 0.7 seconds
Started Dec 27 01:09:56 PM PST 23
Finished Dec 27 01:10:02 PM PST 23
Peak memory 192160 kb
Host smart-9e45b0ba-ed37-4ccd-8f54-e31c2304da1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242882659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4242882659
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3052104400
Short name T407
Test name
Test status
Simulation time 37281854 ps
CPU time 1.71 seconds
Started Dec 27 01:09:53 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 197748 kb
Host smart-24d77fab-06ea-4f65-ac33-657b3de758a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052104400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3052104400
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2894842796
Short name T414
Test name
Test status
Simulation time 36263455 ps
CPU time 0.8 seconds
Started Dec 27 01:09:43 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 194164 kb
Host smart-ddcc8331-0586-456d-88ad-80925bb4f20c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894842796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2894842796
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.267615215
Short name T56
Test name
Test status
Simulation time 17396511 ps
CPU time 0.71 seconds
Started Dec 27 01:09:31 PM PST 23
Finished Dec 27 01:09:39 PM PST 23
Peak memory 193040 kb
Host smart-d5691e00-4cc1-4038-a342-5c7654cc267d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267615215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.267615215
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3665702444
Short name T70
Test name
Test status
Simulation time 89747384 ps
CPU time 3.28 seconds
Started Dec 27 01:09:19 PM PST 23
Finished Dec 27 01:09:30 PM PST 23
Peak memory 191676 kb
Host smart-1839019d-8d87-4f27-b93c-818ba35819fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665702444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3665702444
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.966939792
Short name T84
Test name
Test status
Simulation time 13469366 ps
CPU time 0.57 seconds
Started Dec 27 01:09:35 PM PST 23
Finished Dec 27 01:09:43 PM PST 23
Peak memory 183308 kb
Host smart-6fe13398-473d-4a13-914b-98d94b5e6c4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966939792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.966939792
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1874856079
Short name T433
Test name
Test status
Simulation time 34921285 ps
CPU time 0.82 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 196948 kb
Host smart-49eb627e-53c1-4afc-84f1-5f929bb3ab43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874856079 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1874856079
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3113745970
Short name T409
Test name
Test status
Simulation time 14431570 ps
CPU time 0.6 seconds
Started Dec 27 01:09:19 PM PST 23
Finished Dec 27 01:09:27 PM PST 23
Peak memory 183236 kb
Host smart-8b76cdf8-f488-4fb7-a300-2efc90d5667a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113745970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3113745970
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.844040729
Short name T426
Test name
Test status
Simulation time 22142245 ps
CPU time 0.54 seconds
Started Dec 27 01:09:35 PM PST 23
Finished Dec 27 01:09:43 PM PST 23
Peak memory 182500 kb
Host smart-6215c2ea-67fd-459e-baf3-7d0c2b4c7f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844040729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.844040729
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2767744175
Short name T424
Test name
Test status
Simulation time 113744670 ps
CPU time 0.78 seconds
Started Dec 27 01:09:36 PM PST 23
Finished Dec 27 01:09:45 PM PST 23
Peak memory 192164 kb
Host smart-b3b2ecb1-726a-4134-9ab9-3f1c415c1c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767744175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2767744175
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2777492010
Short name T480
Test name
Test status
Simulation time 65224070 ps
CPU time 3.22 seconds
Started Dec 27 01:09:40 PM PST 23
Finished Dec 27 01:09:51 PM PST 23
Peak memory 197996 kb
Host smart-c8f8ce80-1c16-4066-aa54-c63f9adaf221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777492010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2777492010
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2225346263
Short name T452
Test name
Test status
Simulation time 951319304 ps
CPU time 1.34 seconds
Started Dec 27 01:09:29 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 195584 kb
Host smart-2ff4c1c7-3fcd-428f-8093-6b322bf5e9dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225346263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2225346263
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.441426404
Short name T379
Test name
Test status
Simulation time 25149318 ps
CPU time 0.55 seconds
Started Dec 27 01:09:55 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 182968 kb
Host smart-9dc2be4c-2e7c-4da8-b1cf-ec9d1aac21c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441426404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.441426404
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4276400012
Short name T382
Test name
Test status
Simulation time 24347995 ps
CPU time 0.55 seconds
Started Dec 27 01:10:16 PM PST 23
Finished Dec 27 01:10:24 PM PST 23
Peak memory 182944 kb
Host smart-e583cbfa-daca-4dc5-9f9a-06208111f6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276400012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.4276400012
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2254921926
Short name T54
Test name
Test status
Simulation time 16954540 ps
CPU time 0.56 seconds
Started Dec 27 01:09:56 PM PST 23
Finished Dec 27 01:10:02 PM PST 23
Peak memory 183016 kb
Host smart-ec725ece-2e51-413e-b23a-8c4874c9d140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254921926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2254921926
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.546134527
Short name T402
Test name
Test status
Simulation time 34155522 ps
CPU time 0.55 seconds
Started Dec 27 01:09:53 PM PST 23
Finished Dec 27 01:09:59 PM PST 23
Peak memory 182948 kb
Host smart-71d1bc61-0b67-4898-8eaf-b29afac6d2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546134527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.546134527
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1126575042
Short name T57
Test name
Test status
Simulation time 22954482 ps
CPU time 0.54 seconds
Started Dec 27 01:10:07 PM PST 23
Finished Dec 27 01:10:11 PM PST 23
Peak memory 183016 kb
Host smart-d765dacc-89dc-4121-b541-dbf8f695d3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126575042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1126575042
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.108796004
Short name T468
Test name
Test status
Simulation time 21309541 ps
CPU time 0.53 seconds
Started Dec 27 01:09:46 PM PST 23
Finished Dec 27 01:09:54 PM PST 23
Peak memory 182044 kb
Host smart-bcbcc4ba-a8b8-4275-bb16-c019409b4f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108796004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.108796004
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1359606094
Short name T395
Test name
Test status
Simulation time 50975148 ps
CPU time 0.53 seconds
Started Dec 27 01:10:04 PM PST 23
Finished Dec 27 01:10:09 PM PST 23
Peak memory 182860 kb
Host smart-ce06505e-d3e3-4571-ad12-03306298c7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359606094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1359606094
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2270947532
Short name T463
Test name
Test status
Simulation time 33733083 ps
CPU time 0.6 seconds
Started Dec 27 01:10:10 PM PST 23
Finished Dec 27 01:10:14 PM PST 23
Peak memory 182908 kb
Host smart-60dd4387-cb6e-4139-8ad3-a616f14617b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270947532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2270947532
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2457625016
Short name T396
Test name
Test status
Simulation time 99112813 ps
CPU time 0.59 seconds
Started Dec 27 01:09:58 PM PST 23
Finished Dec 27 01:10:03 PM PST 23
Peak memory 182948 kb
Host smart-4e0e0b64-2552-4fa1-bc47-49572e7fa578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457625016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2457625016
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4221916556
Short name T392
Test name
Test status
Simulation time 13292131 ps
CPU time 0.54 seconds
Started Dec 27 01:09:48 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 182968 kb
Host smart-20ca19ef-7da8-44a3-b59e-23794e714052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221916556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4221916556
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.916934162
Short name T66
Test name
Test status
Simulation time 110695721 ps
CPU time 0.71 seconds
Started Dec 27 01:09:28 PM PST 23
Finished Dec 27 01:09:37 PM PST 23
Peak memory 183280 kb
Host smart-3f108460-549e-46ea-966f-156b6ebbf1e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916934162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.916934162
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3131296440
Short name T470
Test name
Test status
Simulation time 101881993 ps
CPU time 1.49 seconds
Started Dec 27 01:09:35 PM PST 23
Finished Dec 27 01:09:44 PM PST 23
Peak memory 191696 kb
Host smart-03ee5133-5ef0-4b45-a0b2-cf4b0d342c8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131296440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3131296440
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2548594089
Short name T439
Test name
Test status
Simulation time 16329725 ps
CPU time 0.57 seconds
Started Dec 27 01:09:37 PM PST 23
Finished Dec 27 01:09:46 PM PST 23
Peak memory 183200 kb
Host smart-34b44de8-3dfb-411f-ad6a-6ee942e304a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548594089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2548594089
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1449841518
Short name T469
Test name
Test status
Simulation time 35575503 ps
CPU time 0.63 seconds
Started Dec 27 01:09:32 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 194220 kb
Host smart-94055f89-72f7-4458-a5a7-b72f7f3f6b3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449841518 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1449841518
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1516326177
Short name T397
Test name
Test status
Simulation time 17997393 ps
CPU time 0.57 seconds
Started Dec 27 01:09:25 PM PST 23
Finished Dec 27 01:09:36 PM PST 23
Peak memory 183244 kb
Host smart-733bc0c7-939e-42cf-9314-e4bb38abbb99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516326177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1516326177
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1573062122
Short name T72
Test name
Test status
Simulation time 12952120 ps
CPU time 0.55 seconds
Started Dec 27 01:09:37 PM PST 23
Finished Dec 27 01:09:46 PM PST 23
Peak memory 182120 kb
Host smart-a2b4be77-5c69-4a3d-a548-afaabd2b1299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573062122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1573062122
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4239495202
Short name T430
Test name
Test status
Simulation time 31020764 ps
CPU time 0.71 seconds
Started Dec 27 01:09:27 PM PST 23
Finished Dec 27 01:09:36 PM PST 23
Peak memory 192220 kb
Host smart-21f1fb2f-f70a-4ad6-85a6-da7f27146bc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239495202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4239495202
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3299113006
Short name T404
Test name
Test status
Simulation time 65027541 ps
CPU time 1.78 seconds
Started Dec 27 01:09:42 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 191664 kb
Host smart-19dd5475-face-4b9a-a5ca-8ab2f657c151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299113006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3299113006
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.311800241
Short name T408
Test name
Test status
Simulation time 1196370686 ps
CPU time 1.07 seconds
Started Dec 27 01:09:34 PM PST 23
Finished Dec 27 01:09:42 PM PST 23
Peak memory 195132 kb
Host smart-3bef77fc-dc35-4c91-b289-645b49ccb2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311800241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.311800241
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.4087536775
Short name T393
Test name
Test status
Simulation time 39142703 ps
CPU time 0.54 seconds
Started Dec 27 01:09:52 PM PST 23
Finished Dec 27 01:09:59 PM PST 23
Peak memory 182488 kb
Host smart-71cec149-f5c2-4412-a37d-a7dd9973eac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087536775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.4087536775
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3191871383
Short name T384
Test name
Test status
Simulation time 30515170 ps
CPU time 0.62 seconds
Started Dec 27 01:09:40 PM PST 23
Finished Dec 27 01:09:49 PM PST 23
Peak memory 182992 kb
Host smart-e4e912e7-0685-4934-8c50-719e2444b911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191871383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3191871383
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2436888393
Short name T399
Test name
Test status
Simulation time 46439184 ps
CPU time 0.54 seconds
Started Dec 27 01:09:49 PM PST 23
Finished Dec 27 01:09:56 PM PST 23
Peak memory 182988 kb
Host smart-babfb2c6-d302-4c07-9ca4-de99b1e6eb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436888393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2436888393
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1071047275
Short name T405
Test name
Test status
Simulation time 12612070 ps
CPU time 0.56 seconds
Started Dec 27 01:09:56 PM PST 23
Finished Dec 27 01:10:01 PM PST 23
Peak memory 182908 kb
Host smart-4de61e3b-f296-43da-a653-3ed7d3803bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071047275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1071047275
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.307988405
Short name T467
Test name
Test status
Simulation time 14853564 ps
CPU time 0.55 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 182968 kb
Host smart-c66e8b45-758c-41c4-84ad-83db1dac2fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307988405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.307988405
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2800592604
Short name T74
Test name
Test status
Simulation time 47739178 ps
CPU time 0.59 seconds
Started Dec 27 01:09:59 PM PST 23
Finished Dec 27 01:10:04 PM PST 23
Peak memory 183004 kb
Host smart-87cad23b-6e01-4e5c-967e-19120fa9e6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800592604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2800592604
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1192841997
Short name T380
Test name
Test status
Simulation time 17031107 ps
CPU time 0.6 seconds
Started Dec 27 01:09:47 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 182936 kb
Host smart-a9e4a60f-05f3-475a-a353-eddd9f3d6427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192841997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1192841997
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3299477797
Short name T448
Test name
Test status
Simulation time 43005970 ps
CPU time 0.55 seconds
Started Dec 27 01:09:51 PM PST 23
Finished Dec 27 01:09:57 PM PST 23
Peak memory 182936 kb
Host smart-c1656bee-0b29-45f1-afb9-56f9b81492cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299477797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3299477797
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2896245158
Short name T52
Test name
Test status
Simulation time 37958902 ps
CPU time 0.51 seconds
Started Dec 27 01:09:50 PM PST 23
Finished Dec 27 01:09:56 PM PST 23
Peak memory 182124 kb
Host smart-2be4c0ef-5419-4919-a56b-161eb3325044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896245158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2896245158
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3040176939
Short name T401
Test name
Test status
Simulation time 28342271 ps
CPU time 0.55 seconds
Started Dec 27 01:10:06 PM PST 23
Finished Dec 27 01:10:10 PM PST 23
Peak memory 182888 kb
Host smart-4face791-71d7-4dfd-b4f6-a0230b0e8061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040176939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3040176939
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1295532311
Short name T429
Test name
Test status
Simulation time 93130235 ps
CPU time 0.72 seconds
Started Dec 27 01:09:29 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 183328 kb
Host smart-f1018744-ea8a-4eb2-9101-3762c6ae3f7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295532311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1295532311
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.560614436
Short name T69
Test name
Test status
Simulation time 89831490 ps
CPU time 3.11 seconds
Started Dec 27 01:09:28 PM PST 23
Finished Dec 27 01:09:39 PM PST 23
Peak memory 191644 kb
Host smart-7066e055-33a0-4812-a4d2-6fd91cfc7a82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560614436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.560614436
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1618476090
Short name T32
Test name
Test status
Simulation time 27768231 ps
CPU time 0.56 seconds
Started Dec 27 01:09:33 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 183256 kb
Host smart-ca70210d-10cd-4cf8-b49b-03a5e263859d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618476090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1618476090
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1438632204
Short name T466
Test name
Test status
Simulation time 20862855 ps
CPU time 0.64 seconds
Started Dec 27 01:09:39 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 193128 kb
Host smart-57428480-3aac-4d40-8ebb-eb508b7fd157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438632204 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1438632204
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.689839571
Short name T438
Test name
Test status
Simulation time 52724645 ps
CPU time 0.59 seconds
Started Dec 27 01:09:17 PM PST 23
Finished Dec 27 01:09:25 PM PST 23
Peak memory 192508 kb
Host smart-24577587-f129-450c-afc0-a9ab91a567b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689839571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.689839571
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.755332879
Short name T400
Test name
Test status
Simulation time 40452602 ps
CPU time 0.54 seconds
Started Dec 27 01:09:40 PM PST 23
Finished Dec 27 01:09:49 PM PST 23
Peak memory 182076 kb
Host smart-02b5e2a1-faea-4d6c-a38a-dd8b1d4357d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755332879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.755332879
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2002477513
Short name T436
Test name
Test status
Simulation time 36176022 ps
CPU time 0.62 seconds
Started Dec 27 01:09:33 PM PST 23
Finished Dec 27 01:09:41 PM PST 23
Peak memory 191920 kb
Host smart-c75e726b-0463-4a4d-8c79-d2d866527e5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002477513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2002477513
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.545227847
Short name T441
Test name
Test status
Simulation time 811318431 ps
CPU time 2.63 seconds
Started Dec 27 01:09:42 PM PST 23
Finished Dec 27 01:09:53 PM PST 23
Peak memory 198056 kb
Host smart-a3b7d486-3da2-4142-ab2f-e0dbd8f14c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545227847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.545227847
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.76249687
Short name T29
Test name
Test status
Simulation time 92517312 ps
CPU time 0.79 seconds
Started Dec 27 01:09:22 PM PST 23
Finished Dec 27 01:09:31 PM PST 23
Peak memory 193628 kb
Host smart-7e042de3-b930-4777-a9c6-b792c2062703
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76249687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg
_err.76249687
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1571766847
Short name T55
Test name
Test status
Simulation time 61266208 ps
CPU time 0.54 seconds
Started Dec 27 01:10:00 PM PST 23
Finished Dec 27 01:10:05 PM PST 23
Peak memory 183012 kb
Host smart-de084744-fd17-4902-9eb4-0aea301f3bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571766847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1571766847
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.944815533
Short name T387
Test name
Test status
Simulation time 13692096 ps
CPU time 0.52 seconds
Started Dec 27 01:09:58 PM PST 23
Finished Dec 27 01:10:03 PM PST 23
Peak memory 182096 kb
Host smart-ba7d67ac-8746-4ef5-8ca6-11be82497cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944815533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.944815533
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1178448345
Short name T419
Test name
Test status
Simulation time 29294147 ps
CPU time 0.56 seconds
Started Dec 27 01:10:04 PM PST 23
Finished Dec 27 01:10:08 PM PST 23
Peak memory 182968 kb
Host smart-8c509ba2-5fcc-4ec9-8faa-c8fb0890e789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178448345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1178448345
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4185402357
Short name T389
Test name
Test status
Simulation time 42248270 ps
CPU time 0.6 seconds
Started Dec 27 01:10:10 PM PST 23
Finished Dec 27 01:10:14 PM PST 23
Peak memory 182932 kb
Host smart-9d2e4702-be69-4338-a52e-8af6c1a1a18c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185402357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4185402357
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2284908793
Short name T76
Test name
Test status
Simulation time 17091577 ps
CPU time 0.53 seconds
Started Dec 27 01:09:42 PM PST 23
Finished Dec 27 01:09:51 PM PST 23
Peak memory 183020 kb
Host smart-85279b90-f45f-4701-9873-cb144fda879a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284908793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2284908793
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1833805408
Short name T478
Test name
Test status
Simulation time 16605741 ps
CPU time 0.59 seconds
Started Dec 27 01:10:07 PM PST 23
Finished Dec 27 01:10:11 PM PST 23
Peak memory 182872 kb
Host smart-5ed3dca3-8dbd-497b-9d76-633a9150a24c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833805408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1833805408
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.964466513
Short name T410
Test name
Test status
Simulation time 28166181 ps
CPU time 0.54 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 183008 kb
Host smart-f5bb3760-7d8c-4901-87f7-e87efbaf6382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964466513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.964466513
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2804818909
Short name T425
Test name
Test status
Simulation time 22773388 ps
CPU time 0.54 seconds
Started Dec 27 01:10:08 PM PST 23
Finished Dec 27 01:10:12 PM PST 23
Peak memory 182924 kb
Host smart-d62a3487-801d-42e4-ad47-99c83b88014b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804818909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2804818909
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3845805699
Short name T412
Test name
Test status
Simulation time 14386214 ps
CPU time 0.53 seconds
Started Dec 27 01:09:54 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 182016 kb
Host smart-ab26a2a1-e44c-4a0f-b562-6c0eefe6e172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845805699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3845805699
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.658326796
Short name T473
Test name
Test status
Simulation time 39512412 ps
CPU time 0.54 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 182920 kb
Host smart-a8f83b0f-6a43-4fc8-8c7a-e1b7f2d0e0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658326796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.658326796
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1504318253
Short name T450
Test name
Test status
Simulation time 14077017 ps
CPU time 0.66 seconds
Started Dec 27 01:09:37 PM PST 23
Finished Dec 27 01:09:46 PM PST 23
Peak memory 195284 kb
Host smart-03502de5-d3a3-46c8-8226-d900dfda14c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504318253 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1504318253
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1471952117
Short name T87
Test name
Test status
Simulation time 34985925 ps
CPU time 0.59 seconds
Started Dec 27 01:09:18 PM PST 23
Finished Dec 27 01:09:26 PM PST 23
Peak memory 192520 kb
Host smart-36626e4d-ecbb-400a-aeef-ca5d1db7bb3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471952117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1471952117
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.443875744
Short name T462
Test name
Test status
Simulation time 80297816 ps
CPU time 0.55 seconds
Started Dec 27 01:09:47 PM PST 23
Finished Dec 27 01:09:54 PM PST 23
Peak memory 182860 kb
Host smart-1706caa1-0201-4e68-bbf3-4a9a2513115f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443875744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.443875744
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.961653353
Short name T435
Test name
Test status
Simulation time 47361043 ps
CPU time 0.59 seconds
Started Dec 27 01:09:21 PM PST 23
Finished Dec 27 01:09:31 PM PST 23
Peak memory 191456 kb
Host smart-62318d9f-6ec8-413e-b0d9-11ddf9c5177b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961653353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.961653353
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2803151838
Short name T456
Test name
Test status
Simulation time 179770069 ps
CPU time 1.16 seconds
Started Dec 27 01:09:24 PM PST 23
Finished Dec 27 01:09:35 PM PST 23
Peak memory 197584 kb
Host smart-60da795e-29a5-460d-aa9d-80b9362e51d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803151838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2803151838
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.206180486
Short name T62
Test name
Test status
Simulation time 91083508 ps
CPU time 0.82 seconds
Started Dec 27 01:09:29 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 194080 kb
Host smart-a2a0e1b9-ffe4-4c48-9e5f-c49f91be876c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206180486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.206180486
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1452824455
Short name T471
Test name
Test status
Simulation time 78414802 ps
CPU time 0.72 seconds
Started Dec 27 01:09:21 PM PST 23
Finished Dec 27 01:09:31 PM PST 23
Peak memory 191544 kb
Host smart-ed2ed3b1-f47c-4cb6-9fe2-85340253d14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452824455 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1452824455
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3699248793
Short name T80
Test name
Test status
Simulation time 120012483 ps
CPU time 0.52 seconds
Started Dec 27 01:09:29 PM PST 23
Finished Dec 27 01:09:37 PM PST 23
Peak memory 182720 kb
Host smart-67b4ab7a-59c9-4f52-bd72-217115ff7f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699248793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3699248793
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2404880880
Short name T75
Test name
Test status
Simulation time 13174052 ps
CPU time 0.58 seconds
Started Dec 27 01:09:36 PM PST 23
Finished Dec 27 01:09:45 PM PST 23
Peak memory 182040 kb
Host smart-5eca0558-34c6-4b8f-9dff-68b138319e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404880880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2404880880
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1951878292
Short name T88
Test name
Test status
Simulation time 20326057 ps
CPU time 0.8 seconds
Started Dec 27 01:09:39 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 192240 kb
Host smart-3027daa5-9266-4219-8da3-d9e8b7ffb91c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951878292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1951878292
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1581691612
Short name T45
Test name
Test status
Simulation time 239367392 ps
CPU time 1.16 seconds
Started Dec 27 01:09:30 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 198076 kb
Host smart-db19313e-e900-4ec1-b43a-198295f457c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581691612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1581691612
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1422805082
Short name T31
Test name
Test status
Simulation time 110121947 ps
CPU time 0.9 seconds
Started Dec 27 01:09:28 PM PST 23
Finished Dec 27 01:09:37 PM PST 23
Peak memory 193968 kb
Host smart-88959c78-e56c-48a1-9fa6-7944be43537b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422805082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1422805082
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3569465079
Short name T388
Test name
Test status
Simulation time 49090715 ps
CPU time 0.94 seconds
Started Dec 27 01:09:47 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 197208 kb
Host smart-93be4252-2093-4c58-906c-a6c802f8d287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569465079 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3569465079
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3595450754
Short name T79
Test name
Test status
Simulation time 56491510 ps
CPU time 0.56 seconds
Started Dec 27 01:09:33 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 183176 kb
Host smart-01f236fc-c974-4727-b55c-abf68460918f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595450754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3595450754
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1407253155
Short name T411
Test name
Test status
Simulation time 14856916 ps
CPU time 0.54 seconds
Started Dec 27 01:09:21 PM PST 23
Finished Dec 27 01:09:31 PM PST 23
Peak memory 182876 kb
Host smart-db663894-faca-4a76-9246-8f23b9cc154c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407253155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1407253155
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3960120943
Short name T92
Test name
Test status
Simulation time 128162970 ps
CPU time 0.6 seconds
Started Dec 27 01:09:30 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 192556 kb
Host smart-30ed549b-f6bc-49d8-adde-3702b83af5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960120943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3960120943
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1353205238
Short name T385
Test name
Test status
Simulation time 125127536 ps
CPU time 2.05 seconds
Started Dec 27 01:09:34 PM PST 23
Finished Dec 27 01:09:43 PM PST 23
Peak memory 198088 kb
Host smart-85db7cdc-7012-4fc2-9fdc-35bd56f4c3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353205238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1353205238
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3815361342
Short name T98
Test name
Test status
Simulation time 124819825 ps
CPU time 1.46 seconds
Started Dec 27 01:09:32 PM PST 23
Finished Dec 27 01:09:40 PM PST 23
Peak memory 195664 kb
Host smart-fe1d014b-fafd-4922-87e1-883fca5b9c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815361342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3815361342
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2369836909
Short name T420
Test name
Test status
Simulation time 22133382 ps
CPU time 0.61 seconds
Started Dec 27 01:09:24 PM PST 23
Finished Dec 27 01:09:34 PM PST 23
Peak memory 194184 kb
Host smart-7d8987ee-51e2-4aab-bf44-e2709c03cb2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369836909 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2369836909
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.790778729
Short name T394
Test name
Test status
Simulation time 42208979 ps
CPU time 0.52 seconds
Started Dec 27 01:09:38 PM PST 23
Finished Dec 27 01:09:47 PM PST 23
Peak memory 182784 kb
Host smart-1dafa160-9120-4549-a987-65ed5e9a1866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790778729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.790778729
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2131590763
Short name T51
Test name
Test status
Simulation time 30647160 ps
CPU time 0.55 seconds
Started Dec 27 01:09:41 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 182948 kb
Host smart-470de321-bf49-4b2e-bea6-c9366d89e825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131590763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2131590763
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2004989334
Short name T91
Test name
Test status
Simulation time 19951722 ps
CPU time 0.63 seconds
Started Dec 27 01:09:47 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 191792 kb
Host smart-42754063-6799-4405-a10f-5608fec56b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004989334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2004989334
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2271177524
Short name T71
Test name
Test status
Simulation time 55664931 ps
CPU time 1.38 seconds
Started Dec 27 01:09:25 PM PST 23
Finished Dec 27 01:09:36 PM PST 23
Peak memory 198116 kb
Host smart-45e3cc79-ee4a-4878-94fa-1e7c9ddfef30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271177524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2271177524
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3815056371
Short name T443
Test name
Test status
Simulation time 110756050 ps
CPU time 1.32 seconds
Started Dec 27 01:09:50 PM PST 23
Finished Dec 27 01:09:58 PM PST 23
Peak memory 195676 kb
Host smart-4cf26a50-3950-4676-a7b5-a15402452f19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815056371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3815056371
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3716337318
Short name T444
Test name
Test status
Simulation time 22342646 ps
CPU time 0.55 seconds
Started Dec 27 01:09:55 PM PST 23
Finished Dec 27 01:10:01 PM PST 23
Peak memory 182920 kb
Host smart-032e4599-ce37-4428-8b81-51c605c71861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716337318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3716337318
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1073003679
Short name T479
Test name
Test status
Simulation time 32869602 ps
CPU time 0.79 seconds
Started Dec 27 01:09:40 PM PST 23
Finished Dec 27 01:09:50 PM PST 23
Peak memory 193756 kb
Host smart-b60a5866-dc5f-4de0-a91d-6d5cc1988bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073003679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1073003679
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.239888133
Short name T449
Test name
Test status
Simulation time 206164650 ps
CPU time 3.02 seconds
Started Dec 27 01:09:36 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 198112 kb
Host smart-505a2c7f-d5e1-4f34-9aa3-d0f61b83df2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239888133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.239888133
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2067977132
Short name T455
Test name
Test status
Simulation time 43392183 ps
CPU time 0.82 seconds
Started Dec 27 01:09:48 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 183380 kb
Host smart-c5fe8bdb-51ed-46fb-a621-db1aa6847517
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067977132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2067977132
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2315537082
Short name T321
Test name
Test status
Simulation time 270786615452 ps
CPU time 436.77 seconds
Started Dec 27 12:34:34 PM PST 23
Finished Dec 27 12:42:08 PM PST 23
Peak memory 182752 kb
Host smart-6eab1021-4691-4861-abee-0d5fc0cc0bb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315537082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2315537082
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1220475368
Short name T574
Test name
Test status
Simulation time 60573911048 ps
CPU time 95.19 seconds
Started Dec 27 12:34:33 PM PST 23
Finished Dec 27 12:36:26 PM PST 23
Peak memory 182992 kb
Host smart-f6a054e1-fabc-4766-8b09-223c27c4ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220475368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1220475368
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3126290647
Short name T242
Test name
Test status
Simulation time 43588587098 ps
CPU time 77.71 seconds
Started Dec 27 12:34:37 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 194396 kb
Host smart-f8e097f6-1c63-4876-87b0-ca0842e45146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126290647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3126290647
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.224931324
Short name T513
Test name
Test status
Simulation time 6058980733 ps
CPU time 63.02 seconds
Started Dec 27 12:34:56 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 197564 kb
Host smart-ce06c755-5b3d-4d7a-8823-05bd646e2de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224931324 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.224931324
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.551472434
Short name T511
Test name
Test status
Simulation time 213951849450 ps
CPU time 401.63 seconds
Started Dec 27 12:35:30 PM PST 23
Finished Dec 27 12:42:36 PM PST 23
Peak memory 182748 kb
Host smart-5ac748d6-4a63-43c9-96c5-240caf8381a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551472434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.551472434
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.921259924
Short name T556
Test name
Test status
Simulation time 737666530068 ps
CPU time 315.02 seconds
Started Dec 27 12:34:40 PM PST 23
Finished Dec 27 12:40:12 PM PST 23
Peak memory 182804 kb
Host smart-4c3469cb-9a55-4217-9ff4-b0824e752890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921259924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.921259924
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1527434087
Short name T185
Test name
Test status
Simulation time 254182697129 ps
CPU time 279.12 seconds
Started Dec 27 12:34:48 PM PST 23
Finished Dec 27 12:39:46 PM PST 23
Peak memory 191184 kb
Host smart-b90d9349-051a-42be-bce1-962306af1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527434087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1527434087
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2351485587
Short name T16
Test name
Test status
Simulation time 170221317 ps
CPU time 0.96 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 213764 kb
Host smart-fd882ca6-3064-46fc-ba13-6d9be3b2cfd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351485587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2351485587
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2951406145
Short name T552
Test name
Test status
Simulation time 369208328843 ps
CPU time 561.87 seconds
Started Dec 27 12:35:09 PM PST 23
Finished Dec 27 12:44:49 PM PST 23
Peak memory 207392 kb
Host smart-74758efe-c574-4d53-949b-502e24419397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951406145 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2951406145
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.742370442
Short name T192
Test name
Test status
Simulation time 473684186864 ps
CPU time 406.16 seconds
Started Dec 27 12:34:53 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 182800 kb
Host smart-abbda6c9-767c-4075-9db0-e9f638a7a3fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742370442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.742370442
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.449801683
Short name T596
Test name
Test status
Simulation time 84285050155 ps
CPU time 58.11 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 182892 kb
Host smart-aef013de-298b-4265-b60f-94cde07ac238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449801683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.449801683
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2624139179
Short name T310
Test name
Test status
Simulation time 30219734365 ps
CPU time 51.27 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:36:25 PM PST 23
Peak memory 182836 kb
Host smart-38ff33f1-d1ad-4715-b61f-3d8f5035fc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624139179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2624139179
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2670983353
Short name T500
Test name
Test status
Simulation time 200425180814 ps
CPU time 388.66 seconds
Started Dec 27 12:34:32 PM PST 23
Finished Dec 27 12:41:18 PM PST 23
Peak memory 205780 kb
Host smart-d917cc5c-ced6-421b-8b1c-82b39495361c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670983353 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2670983353
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.712081803
Short name T367
Test name
Test status
Simulation time 7420586011 ps
CPU time 12.8 seconds
Started Dec 27 12:35:21 PM PST 23
Finished Dec 27 12:35:49 PM PST 23
Peak memory 182824 kb
Host smart-bb4ed0d8-f26f-4d46-ab0f-0ff09295db75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712081803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.712081803
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.866154835
Short name T251
Test name
Test status
Simulation time 81278065368 ps
CPU time 145.92 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 191192 kb
Host smart-3e3cf7b1-1ffa-4f7b-9bf9-488c91f31f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866154835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.866154835
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3231264912
Short name T288
Test name
Test status
Simulation time 11626158156 ps
CPU time 17.05 seconds
Started Dec 27 12:35:58 PM PST 23
Finished Dec 27 12:36:34 PM PST 23
Peak memory 193848 kb
Host smart-b30b0ca3-57c4-4cc1-baad-cefa0798814a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231264912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3231264912
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2174927214
Short name T326
Test name
Test status
Simulation time 103636412307 ps
CPU time 115.38 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 182884 kb
Host smart-5177afb6-eae0-4fb2-afd2-519cab72be4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174927214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2174927214
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4131300306
Short name T250
Test name
Test status
Simulation time 13066968064 ps
CPU time 21.11 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:35:52 PM PST 23
Peak memory 182772 kb
Host smart-b92c6f3b-1477-4f3a-ba7f-dbd2a72602d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131300306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.4131300306
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2557124903
Short name T506
Test name
Test status
Simulation time 850207684257 ps
CPU time 190.15 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:38:54 PM PST 23
Peak memory 182824 kb
Host smart-27b7a82f-1949-4586-868d-1abaee6d3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557124903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2557124903
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2060520973
Short name T225
Test name
Test status
Simulation time 635407503243 ps
CPU time 169.23 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:38:08 PM PST 23
Peak memory 194848 kb
Host smart-b0883554-2837-43a2-bf9a-f714160f4292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060520973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2060520973
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3892337771
Short name T295
Test name
Test status
Simulation time 494736267541 ps
CPU time 112.17 seconds
Started Dec 27 12:34:46 PM PST 23
Finished Dec 27 12:36:58 PM PST 23
Peak memory 182848 kb
Host smart-74cb2d93-0a2e-4843-894c-be458aa25b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892337771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3892337771
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.833184675
Short name T502
Test name
Test status
Simulation time 11153041199 ps
CPU time 122.18 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:38:10 PM PST 23
Peak memory 196020 kb
Host smart-80f19961-5ed1-4d3a-b0b7-ed6a9914dcb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833184675 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.833184675
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.131125382
Short name T209
Test name
Test status
Simulation time 133127700535 ps
CPU time 219.18 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:39:48 PM PST 23
Peak memory 191044 kb
Host smart-a1342223-6859-491a-8ec6-6ad14047e828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131125382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.131125382
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2767442148
Short name T298
Test name
Test status
Simulation time 126161793703 ps
CPU time 196.5 seconds
Started Dec 27 12:35:08 PM PST 23
Finished Dec 27 12:38:43 PM PST 23
Peak memory 191136 kb
Host smart-6685d350-f3bb-4304-afa1-c92061c4a623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767442148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2767442148
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.505420446
Short name T353
Test name
Test status
Simulation time 30904678856 ps
CPU time 8.33 seconds
Started Dec 27 12:35:59 PM PST 23
Finished Dec 27 12:36:26 PM PST 23
Peak memory 182640 kb
Host smart-dea748be-4f12-42c9-90cc-f286a8fa9f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505420446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.505420446
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3350204223
Short name T104
Test name
Test status
Simulation time 56173920739 ps
CPU time 89.82 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 193636 kb
Host smart-3a20b258-646c-4eec-9ac9-326ebf5d73e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350204223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3350204223
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3026448476
Short name T580
Test name
Test status
Simulation time 489663348995 ps
CPU time 724 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 190980 kb
Host smart-6ad22d2a-53f5-4fbe-942a-60646e544bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026448476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3026448476
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.86080220
Short name T585
Test name
Test status
Simulation time 53059577174 ps
CPU time 49.74 seconds
Started Dec 27 12:35:16 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 191068 kb
Host smart-eb5dbd56-745d-4523-81a0-51e3ea15a865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86080220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.86080220
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2318391664
Short name T186
Test name
Test status
Simulation time 455082651462 ps
CPU time 245.35 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:39:52 PM PST 23
Peak memory 191200 kb
Host smart-9a2dabb1-f225-4c75-beb0-1aa3ddff655b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318391664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2318391664
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.571401888
Short name T264
Test name
Test status
Simulation time 1407026382141 ps
CPU time 876.44 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:50:44 PM PST 23
Peak memory 182284 kb
Host smart-c2de0cfc-51f9-4fb0-87b1-0fb855cc2772
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571401888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.571401888
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4101219214
Short name T508
Test name
Test status
Simulation time 159775108003 ps
CPU time 144.19 seconds
Started Dec 27 12:34:59 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 182980 kb
Host smart-8f46045b-459c-41b7-886f-00c9c73dc2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101219214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4101219214
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.367453711
Short name T146
Test name
Test status
Simulation time 41806344428 ps
CPU time 104.46 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 190956 kb
Host smart-6d6da79d-f91e-40d3-83c1-4230a69b38a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367453711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.367453711
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1424281892
Short name T356
Test name
Test status
Simulation time 38552394837 ps
CPU time 56.59 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 190992 kb
Host smart-b7145eaf-72d7-434d-9c1b-02d2bf484266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424281892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1424281892
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3815016902
Short name T13
Test name
Test status
Simulation time 89709246874 ps
CPU time 674.72 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:46:34 PM PST 23
Peak memory 208328 kb
Host smart-6f1350fd-72a0-41a5-90b2-65f3657e53d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815016902 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3815016902
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.488678573
Short name T357
Test name
Test status
Simulation time 83058851837 ps
CPU time 74.59 seconds
Started Dec 27 12:35:21 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 182964 kb
Host smart-f2ef0939-10cc-47ca-8aa9-604fe3851621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488678573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.488678573
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.330762975
Short name T193
Test name
Test status
Simulation time 171614034442 ps
CPU time 146.2 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:38:54 PM PST 23
Peak memory 191036 kb
Host smart-bf54c458-2ff3-4955-b6d9-4458d9386873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330762975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.330762975
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4146978319
Short name T567
Test name
Test status
Simulation time 119129865390 ps
CPU time 244.24 seconds
Started Dec 27 12:35:17 PM PST 23
Finished Dec 27 12:39:37 PM PST 23
Peak memory 182836 kb
Host smart-5ca4f49e-e807-4115-b33e-d8fa8687415c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146978319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4146978319
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1351720214
Short name T150
Test name
Test status
Simulation time 161500903257 ps
CPU time 275.58 seconds
Started Dec 27 12:35:43 PM PST 23
Finished Dec 27 12:40:37 PM PST 23
Peak memory 191052 kb
Host smart-3c3632d3-2b35-40dc-ad8b-6bc4c7499708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351720214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1351720214
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.691837422
Short name T282
Test name
Test status
Simulation time 62685171110 ps
CPU time 194.81 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:39:00 PM PST 23
Peak memory 191060 kb
Host smart-77f1097e-f32b-4ff1-a904-0d103a40f18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691837422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.691837422
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2463976879
Short name T269
Test name
Test status
Simulation time 521136183153 ps
CPU time 490.4 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:43:46 PM PST 23
Peak memory 193580 kb
Host smart-e9938aed-a1e5-414a-8491-cd0ed2048971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463976879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2463976879
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3927930275
Short name T137
Test name
Test status
Simulation time 61660955612 ps
CPU time 93.75 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 191044 kb
Host smart-88a830b2-8b4c-44e7-98eb-e57087cc8de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927930275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3927930275
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2167444428
Short name T604
Test name
Test status
Simulation time 18394946186 ps
CPU time 35.25 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 182852 kb
Host smart-e5ae137f-32ab-435e-8bcb-2bc317547fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167444428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2167444428
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2457881601
Short name T125
Test name
Test status
Simulation time 98084656829 ps
CPU time 1009.07 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:53:32 PM PST 23
Peak memory 190996 kb
Host smart-9e35d04e-b9c5-4c3e-92cb-32cc32f904da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457881601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2457881601
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1876770036
Short name T243
Test name
Test status
Simulation time 524260675220 ps
CPU time 271.98 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:40:45 PM PST 23
Peak memory 182932 kb
Host smart-d104ec13-c875-4eaf-9755-bf6b7564656c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876770036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1876770036
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.4175159585
Short name T481
Test name
Test status
Simulation time 120616219266 ps
CPU time 81.53 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 182984 kb
Host smart-4d4d96a3-208f-4e38-b91a-a02dfbb10389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175159585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4175159585
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3544869123
Short name T561
Test name
Test status
Simulation time 46681944209 ps
CPU time 120.96 seconds
Started Dec 27 12:35:13 PM PST 23
Finished Dec 27 12:37:30 PM PST 23
Peak memory 182896 kb
Host smart-1cac4065-99f0-4d29-ac43-7f7e6ed3209b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544869123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3544869123
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3532762545
Short name T560
Test name
Test status
Simulation time 556032356 ps
CPU time 1.6 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:35:54 PM PST 23
Peak memory 182764 kb
Host smart-8395ee5e-fed0-4b99-a846-b73a08be5b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532762545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3532762545
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1917528024
Short name T551
Test name
Test status
Simulation time 86663511209 ps
CPU time 67.45 seconds
Started Dec 27 12:34:57 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 193528 kb
Host smart-ab13de80-d5fa-411a-b4f8-68e7e8e3bef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917528024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1917528024
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3693608696
Short name T38
Test name
Test status
Simulation time 104790254412 ps
CPU time 995.87 seconds
Started Dec 27 12:35:13 PM PST 23
Finished Dec 27 12:52:06 PM PST 23
Peak memory 197868 kb
Host smart-28bed6f4-6aa9-420c-a483-e56d184bac21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693608696 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3693608696
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1802770649
Short name T376
Test name
Test status
Simulation time 104109052193 ps
CPU time 68.57 seconds
Started Dec 27 12:35:43 PM PST 23
Finished Dec 27 12:37:09 PM PST 23
Peak memory 182628 kb
Host smart-f715323c-3e60-425f-a364-f780f42c70e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802770649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1802770649
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2807388164
Short name T141
Test name
Test status
Simulation time 101879593349 ps
CPU time 1299.75 seconds
Started Dec 27 12:35:27 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 191036 kb
Host smart-c484007c-c98c-4532-ac94-20ded37dd1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807388164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2807388164
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1831309606
Short name T219
Test name
Test status
Simulation time 230259447893 ps
CPU time 78.14 seconds
Started Dec 27 12:36:38 PM PST 23
Finished Dec 27 12:38:25 PM PST 23
Peak memory 191056 kb
Host smart-0b124c53-4e32-4a12-bbe5-5a2487102731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831309606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1831309606
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2806988830
Short name T160
Test name
Test status
Simulation time 129788538900 ps
CPU time 102.05 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 191068 kb
Host smart-18332e0e-306a-4e78-8950-7663d491d802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806988830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2806988830
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.869301744
Short name T364
Test name
Test status
Simulation time 213657106530 ps
CPU time 371.25 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 191168 kb
Host smart-ed786d10-e3e3-474d-8eb5-e665210fe4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869301744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.869301744
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3001358741
Short name T233
Test name
Test status
Simulation time 47120500671 ps
CPU time 84.85 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 182820 kb
Host smart-7bb5dd75-8ec9-49f0-aac0-a4d45fb742b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001358741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3001358741
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2506450079
Short name T95
Test name
Test status
Simulation time 59208106724 ps
CPU time 105.26 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 193224 kb
Host smart-6639d0b0-95f5-45f2-ab4a-ec655e2f2907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506450079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2506450079
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2004005400
Short name T581
Test name
Test status
Simulation time 159946773558 ps
CPU time 1131.66 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:55:33 PM PST 23
Peak memory 191128 kb
Host smart-dbb24111-de1b-499f-85bc-9e82d1685354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004005400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2004005400
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2677357799
Short name T23
Test name
Test status
Simulation time 428794717043 ps
CPU time 708.02 seconds
Started Dec 27 12:34:39 PM PST 23
Finished Dec 27 12:46:44 PM PST 23
Peak memory 182792 kb
Host smart-1ce6ad8a-a00c-4dc9-871e-afdc59227bd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677357799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2677357799
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.282115261
Short name T583
Test name
Test status
Simulation time 876451085339 ps
CPU time 153.03 seconds
Started Dec 27 12:35:06 PM PST 23
Finished Dec 27 12:37:56 PM PST 23
Peak memory 182800 kb
Host smart-cf2324ba-fd8c-4454-9192-ee70f5c2e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282115261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.282115261
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.811844970
Short name T322
Test name
Test status
Simulation time 240825728616 ps
CPU time 60.14 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:36:44 PM PST 23
Peak memory 190964 kb
Host smart-524bfb33-0da9-4489-9ae6-8b79e658f1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811844970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.811844970
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3553087803
Short name T287
Test name
Test status
Simulation time 1470356242009 ps
CPU time 1017.08 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:52:35 PM PST 23
Peak memory 191032 kb
Host smart-6793972a-8088-4243-999f-1e8d5709adff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553087803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3553087803
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1233240516
Short name T613
Test name
Test status
Simulation time 47792917293 ps
CPU time 349.32 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:41:34 PM PST 23
Peak memory 205752 kb
Host smart-2beabc6d-1ff6-4dca-86db-71debb0fda4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233240516 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1233240516
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.210875318
Short name T183
Test name
Test status
Simulation time 158419064160 ps
CPU time 262.95 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:39:57 PM PST 23
Peak memory 191040 kb
Host smart-5d1184d3-d55e-4cf5-8aaf-626ebe697404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210875318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.210875318
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.931097789
Short name T284
Test name
Test status
Simulation time 458517567176 ps
CPU time 116.59 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:37:24 PM PST 23
Peak memory 191152 kb
Host smart-c0cc5ff0-6588-4377-b7ec-213302cde2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931097789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.931097789
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2628583053
Short name T165
Test name
Test status
Simulation time 209407006378 ps
CPU time 155.21 seconds
Started Dec 27 12:35:59 PM PST 23
Finished Dec 27 12:38:53 PM PST 23
Peak memory 191016 kb
Host smart-5af48599-45f0-4615-a95f-7fcb6b37010a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628583053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2628583053
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2061625634
Short name T252
Test name
Test status
Simulation time 68432964828 ps
CPU time 116.71 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:37:50 PM PST 23
Peak memory 191140 kb
Host smart-276f8ad8-f2c1-42bd-98c0-f8af73c1deec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061625634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2061625634
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2982987848
Short name T228
Test name
Test status
Simulation time 49796337284 ps
CPU time 116.46 seconds
Started Dec 27 12:35:27 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 182876 kb
Host smart-08178b92-70d3-4121-822d-924fa4d9c1e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982987848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2982987848
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4250167945
Short name T244
Test name
Test status
Simulation time 125311552670 ps
CPU time 100.57 seconds
Started Dec 27 12:35:27 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 182796 kb
Host smart-514904ff-f78a-43f2-9806-44c4cda69139
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250167945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4250167945
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2583073458
Short name T42
Test name
Test status
Simulation time 646338170630 ps
CPU time 254.43 seconds
Started Dec 27 12:36:54 PM PST 23
Finished Dec 27 12:41:34 PM PST 23
Peak memory 182780 kb
Host smart-e84b24bf-816c-480b-bb81-e788e235151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583073458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2583073458
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2075422028
Short name T579
Test name
Test status
Simulation time 65378626846 ps
CPU time 54.91 seconds
Started Dec 27 12:35:02 PM PST 23
Finished Dec 27 12:36:16 PM PST 23
Peak memory 191064 kb
Host smart-61633bc4-37fe-4733-846e-014838c38ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075422028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2075422028
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2333648224
Short name T514
Test name
Test status
Simulation time 712970942644 ps
CPU time 491.13 seconds
Started Dec 27 12:34:44 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 195368 kb
Host smart-fa6f18c2-6b9d-44f4-8025-f4a137727006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333648224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2333648224
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.489904688
Short name T538
Test name
Test status
Simulation time 813506239722 ps
CPU time 904.76 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:50:32 PM PST 23
Peak memory 213732 kb
Host smart-c3053d46-5eb5-4abc-ba20-e5df84166a40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489904688 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.489904688
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1930315429
Short name T281
Test name
Test status
Simulation time 5695576857 ps
CPU time 90.21 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:37:24 PM PST 23
Peak memory 182820 kb
Host smart-7a7d7ba4-9a7a-49f6-b982-1bf3e25f7acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930315429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1930315429
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.902441824
Short name T297
Test name
Test status
Simulation time 291405405022 ps
CPU time 147.73 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:38:43 PM PST 23
Peak memory 190968 kb
Host smart-4caedfcc-ba53-419f-a036-af39316e195c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902441824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.902441824
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.89652647
Short name T277
Test name
Test status
Simulation time 144138126517 ps
CPU time 295.46 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:40:52 PM PST 23
Peak memory 191024 kb
Host smart-54b04979-34a4-4257-94d7-4cacdaabced0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89652647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.89652647
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3303009533
Short name T595
Test name
Test status
Simulation time 91090145624 ps
CPU time 202.29 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:39:11 PM PST 23
Peak memory 191044 kb
Host smart-c4098b42-51aa-40a4-9114-f0c2faf0a924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303009533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3303009533
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2061065019
Short name T256
Test name
Test status
Simulation time 873879680396 ps
CPU time 363.31 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 193400 kb
Host smart-f6d56bad-8046-4d34-872e-d379abe84340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061065019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2061065019
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.670302187
Short name T124
Test name
Test status
Simulation time 110503588670 ps
CPU time 167.66 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:38:50 PM PST 23
Peak memory 193776 kb
Host smart-5adc42e1-11b5-4408-9032-e3452561bfc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670302187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.670302187
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.416792030
Short name T168
Test name
Test status
Simulation time 493581722497 ps
CPU time 273.73 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:40:24 PM PST 23
Peak memory 194116 kb
Host smart-e750af6e-6da0-4a14-ba7d-4a14885405e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416792030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.416792030
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3347784849
Short name T291
Test name
Test status
Simulation time 1059269735611 ps
CPU time 710.36 seconds
Started Dec 27 12:35:16 PM PST 23
Finished Dec 27 12:47:26 PM PST 23
Peak memory 182848 kb
Host smart-008cdf12-8395-4809-b28a-a025460df8ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347784849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3347784849
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1009117284
Short name T377
Test name
Test status
Simulation time 309315283097 ps
CPU time 170.4 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:38:03 PM PST 23
Peak memory 182840 kb
Host smart-64f88630-7ffe-48af-8778-d266f3207ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009117284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1009117284
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2888596110
Short name T591
Test name
Test status
Simulation time 1558402485 ps
CPU time 0.92 seconds
Started Dec 27 12:35:16 PM PST 23
Finished Dec 27 12:35:33 PM PST 23
Peak memory 193228 kb
Host smart-f073c242-e10b-4605-9dd7-34682545d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888596110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2888596110
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2404880034
Short name T346
Test name
Test status
Simulation time 1291555908317 ps
CPU time 894.47 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:50:07 PM PST 23
Peak memory 191148 kb
Host smart-adf72895-dfa3-43e8-b7ed-ee42bbfc5fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404880034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2404880034
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.831030378
Short name T605
Test name
Test status
Simulation time 21096390029 ps
CPU time 154.55 seconds
Started Dec 27 12:35:13 PM PST 23
Finished Dec 27 12:38:05 PM PST 23
Peak memory 197644 kb
Host smart-f96185c0-b6c6-4f88-96bb-63af35d6c8a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831030378 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.831030378
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1314744310
Short name T234
Test name
Test status
Simulation time 348877275635 ps
CPU time 203.43 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:39:08 PM PST 23
Peak memory 191092 kb
Host smart-f61f4dc9-fd5d-4bc6-bb6f-4879fa631737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314744310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1314744310
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2247673434
Short name T129
Test name
Test status
Simulation time 248637712672 ps
CPU time 301.04 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:41:00 PM PST 23
Peak memory 191140 kb
Host smart-94546268-76ce-4c30-ad81-d769dd1462f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247673434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2247673434
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.807156271
Short name T157
Test name
Test status
Simulation time 224401671724 ps
CPU time 262.96 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:41:01 PM PST 23
Peak memory 194448 kb
Host smart-0d7f1eab-1ecb-4bd1-bfb9-63d7d0dd2b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807156271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.807156271
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3390963764
Short name T316
Test name
Test status
Simulation time 186353528729 ps
CPU time 810.15 seconds
Started Dec 27 12:35:56 PM PST 23
Finished Dec 27 12:49:44 PM PST 23
Peak memory 191164 kb
Host smart-fb195ca2-141b-4cd1-9e4e-43ff3bf21b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390963764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3390963764
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2706208219
Short name T106
Test name
Test status
Simulation time 34137677496 ps
CPU time 81.66 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:37:08 PM PST 23
Peak memory 193616 kb
Host smart-8fa30fb3-c045-4312-aea3-c4d4537f14be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706208219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2706208219
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2475055177
Short name T304
Test name
Test status
Simulation time 679202046396 ps
CPU time 2122.69 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 01:11:45 PM PST 23
Peak memory 191108 kb
Host smart-104ceff4-5568-4788-b781-dc562ffe185a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475055177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2475055177
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.539077556
Short name T616
Test name
Test status
Simulation time 81545158306 ps
CPU time 32.38 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 182972 kb
Host smart-06e4783a-7800-4181-b5f4-a6dc8f2b6171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539077556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.539077556
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4231861000
Short name T167
Test name
Test status
Simulation time 70205116463 ps
CPU time 114.22 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 191120 kb
Host smart-b6deedaa-f88e-4bd1-bb5c-c73ca1e47adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231861000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4231861000
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3798115710
Short name T245
Test name
Test status
Simulation time 14274436295 ps
CPU time 23.73 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:35:42 PM PST 23
Peak memory 182848 kb
Host smart-d882b42e-4114-4fc7-8efa-02bac7db8536
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798115710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3798115710
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2850580839
Short name T564
Test name
Test status
Simulation time 62433910851 ps
CPU time 88.3 seconds
Started Dec 27 12:35:21 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 182840 kb
Host smart-f18a13fa-9725-4f5f-a781-614f5cc06aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850580839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2850580839
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.267901272
Short name T236
Test name
Test status
Simulation time 48590118238 ps
CPU time 70.04 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 194232 kb
Host smart-478e6996-ffae-48d4-b6f7-4fb3acf3d22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267901272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.267901272
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2353465629
Short name T375
Test name
Test status
Simulation time 159096807696 ps
CPU time 67.45 seconds
Started Dec 27 12:35:17 PM PST 23
Finished Dec 27 12:36:40 PM PST 23
Peak memory 191144 kb
Host smart-96818a24-27c0-43e1-8153-a5ad439b0b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353465629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2353465629
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2638465188
Short name T550
Test name
Test status
Simulation time 49852633834 ps
CPU time 102.45 seconds
Started Dec 27 12:35:11 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 205732 kb
Host smart-8d2ad57b-7ba6-4414-b428-9e1406370ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638465188 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2638465188
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.4265080512
Short name T174
Test name
Test status
Simulation time 20707544686 ps
CPU time 35.87 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:36:32 PM PST 23
Peak memory 182848 kb
Host smart-364e01ae-b81b-4a15-8e97-23b7330bf147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265080512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4265080512
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2786199443
Short name T195
Test name
Test status
Simulation time 64800632908 ps
CPU time 98.05 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 193736 kb
Host smart-1a9caa78-832c-49bf-acd0-b71c714ceb64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786199443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2786199443
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2326100017
Short name T119
Test name
Test status
Simulation time 16266222964 ps
CPU time 29.13 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 191148 kb
Host smart-dc0eafe6-773c-4bb4-a024-54ca88417f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326100017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2326100017
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2619287161
Short name T10
Test name
Test status
Simulation time 601256023953 ps
CPU time 129.73 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:37:55 PM PST 23
Peak memory 191148 kb
Host smart-7d57dae1-ac6b-4d6b-a0e1-7ebcedd7fa8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619287161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2619287161
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2988449507
Short name T41
Test name
Test status
Simulation time 231418659013 ps
CPU time 247.2 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:39:52 PM PST 23
Peak memory 191200 kb
Host smart-ba2b0b86-98b1-4be3-96c6-a367f623add8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988449507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2988449507
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4135596380
Short name T21
Test name
Test status
Simulation time 42713072314 ps
CPU time 37.02 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:36:24 PM PST 23
Peak memory 182808 kb
Host smart-04e4e51f-0505-4af6-8107-8531757f95df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135596380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4135596380
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2881449893
Short name T378
Test name
Test status
Simulation time 41253844738 ps
CPU time 30.83 seconds
Started Dec 27 12:34:59 PM PST 23
Finished Dec 27 12:35:49 PM PST 23
Peak memory 182840 kb
Host smart-8719b18b-b755-469c-a9ab-41666bfe43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881449893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2881449893
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1920895744
Short name T344
Test name
Test status
Simulation time 230591727408 ps
CPU time 109.67 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:37:03 PM PST 23
Peak memory 192072 kb
Host smart-6a9f7bad-9c87-4ca6-b1a5-87106f530d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920895744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1920895744
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2470939492
Short name T542
Test name
Test status
Simulation time 49444510143 ps
CPU time 23.27 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:35:51 PM PST 23
Peak memory 192692 kb
Host smart-ae45cfc8-d6e8-4e08-8d50-47d4e2ce59a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470939492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2470939492
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2445084446
Short name T510
Test name
Test status
Simulation time 2827203871228 ps
CPU time 1101.71 seconds
Started Dec 27 12:34:50 PM PST 23
Finished Dec 27 12:53:38 PM PST 23
Peak memory 191164 kb
Host smart-55a0ef98-64b9-413f-9619-5c7a3a74d234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445084446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2445084446
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2435457272
Short name T540
Test name
Test status
Simulation time 79652840122 ps
CPU time 846.66 seconds
Started Dec 27 12:34:54 PM PST 23
Finished Dec 27 12:49:22 PM PST 23
Peak memory 209788 kb
Host smart-5dbbc90c-de9a-4024-8114-e7aecbd731ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435457272 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2435457272
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2969024601
Short name T315
Test name
Test status
Simulation time 102870895504 ps
CPU time 190.04 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:39:02 PM PST 23
Peak memory 191200 kb
Host smart-2cf3f16a-4c78-4c54-8fbf-145f73ccd9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969024601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2969024601
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1709681539
Short name T341
Test name
Test status
Simulation time 87549074034 ps
CPU time 911.25 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:51:06 PM PST 23
Peak memory 191076 kb
Host smart-a9bff43d-950b-48a1-82cb-47bbf8e0dbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709681539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1709681539
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3510036086
Short name T267
Test name
Test status
Simulation time 41148298615 ps
CPU time 69.02 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:36:58 PM PST 23
Peak memory 191184 kb
Host smart-d545ccf1-12be-4faf-ae16-2030a06e1d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510036086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3510036086
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1061154030
Short name T115
Test name
Test status
Simulation time 345017134621 ps
CPU time 550.33 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:45:03 PM PST 23
Peak memory 191052 kb
Host smart-22779cb9-43d6-4905-93ea-0280348dc313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061154030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1061154030
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.867847418
Short name T265
Test name
Test status
Simulation time 196146288324 ps
CPU time 134.04 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:38:42 PM PST 23
Peak memory 191028 kb
Host smart-f1146260-f047-425c-a4e6-471575a8e1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867847418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.867847418
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2411447296
Short name T328
Test name
Test status
Simulation time 39490383967 ps
CPU time 31.61 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 193172 kb
Host smart-500aa40b-c7f8-42f0-9ba9-74e71a9c3d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411447296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2411447296
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2938695725
Short name T527
Test name
Test status
Simulation time 37533425710 ps
CPU time 64.94 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 12:36:27 PM PST 23
Peak memory 182800 kb
Host smart-c39bf99d-2e24-4767-885e-7a2b37efe1d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938695725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2938695725
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2732971475
Short name T516
Test name
Test status
Simulation time 571899487782 ps
CPU time 224.93 seconds
Started Dec 27 12:35:06 PM PST 23
Finished Dec 27 12:39:09 PM PST 23
Peak memory 182892 kb
Host smart-857f81a7-b9d4-40d3-b833-36a1423901a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732971475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2732971475
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2826084851
Short name T526
Test name
Test status
Simulation time 11329763505 ps
CPU time 5.6 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:56 PM PST 23
Peak memory 182964 kb
Host smart-dc2c4d1d-c942-4920-9c37-4e8b0a345039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826084851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2826084851
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.792022668
Short name T541
Test name
Test status
Simulation time 987678222 ps
CPU time 1.89 seconds
Started Dec 27 12:34:49 PM PST 23
Finished Dec 27 12:35:11 PM PST 23
Peak memory 182300 kb
Host smart-f7e79d92-8f82-4817-a204-01d37bb89b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792022668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.792022668
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1874486601
Short name T369
Test name
Test status
Simulation time 2884260415721 ps
CPU time 449.66 seconds
Started Dec 27 12:35:02 PM PST 23
Finished Dec 27 12:42:56 PM PST 23
Peak memory 182876 kb
Host smart-921b6c15-25f7-4f4b-805c-0f54c0a53124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874486601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1874486601
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1038549309
Short name T553
Test name
Test status
Simulation time 150939244610 ps
CPU time 277.1 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:40:21 PM PST 23
Peak memory 205808 kb
Host smart-a0fcb122-68b0-467c-9346-b48b1f372ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038549309 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1038549309
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.rv_timer_random.2910565361
Short name T255
Test name
Test status
Simulation time 345856712402 ps
CPU time 156.63 seconds
Started Dec 27 12:35:45 PM PST 23
Finished Dec 27 12:38:40 PM PST 23
Peak memory 191128 kb
Host smart-9cabe62e-c86e-460f-824b-31e98bdc17fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910565361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2910565361
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3279919752
Short name T210
Test name
Test status
Simulation time 91607597350 ps
CPU time 112.94 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 191052 kb
Host smart-d68b1dca-0a88-4fb6-b1ee-eda34010c107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279919752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3279919752
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1561199359
Short name T355
Test name
Test status
Simulation time 1206805729323 ps
CPU time 798.17 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:49:05 PM PST 23
Peak memory 191048 kb
Host smart-72a609fe-37ee-432e-b1bb-787fd82ca971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561199359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1561199359
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3478731425
Short name T253
Test name
Test status
Simulation time 84072368292 ps
CPU time 153.31 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:38:46 PM PST 23
Peak memory 193760 kb
Host smart-f2ec985f-0a20-4b55-b745-82db5fb0907c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478731425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3478731425
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3838212017
Short name T156
Test name
Test status
Simulation time 44787498999 ps
CPU time 75.75 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:38:15 PM PST 23
Peak memory 191104 kb
Host smart-da666057-4f59-40dd-a2e7-10ac0db46fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838212017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3838212017
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3737936283
Short name T276
Test name
Test status
Simulation time 15564880256 ps
CPU time 7.68 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 181476 kb
Host smart-3f0ce8b9-47f0-4e66-801d-3b44874d8de2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737936283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3737936283
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1140091787
Short name T503
Test name
Test status
Simulation time 124507242466 ps
CPU time 106.72 seconds
Started Dec 27 12:35:11 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 182980 kb
Host smart-013fcf80-b1fd-4fac-812e-bf743550f4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140091787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1140091787
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1049429667
Short name T112
Test name
Test status
Simulation time 480528852591 ps
CPU time 674.53 seconds
Started Dec 27 12:36:54 PM PST 23
Finished Dec 27 12:48:34 PM PST 23
Peak memory 191056 kb
Host smart-11de5232-57e8-4de3-831c-b1547a2796bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049429667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1049429667
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3356108129
Short name T570
Test name
Test status
Simulation time 149256445 ps
CPU time 0.57 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 182544 kb
Host smart-59cb06a9-bc53-4c35-b012-657c34cee929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356108129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3356108129
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2678865333
Short name T19
Test name
Test status
Simulation time 72553709 ps
CPU time 0.74 seconds
Started Dec 27 12:35:04 PM PST 23
Finished Dec 27 12:35:23 PM PST 23
Peak memory 212700 kb
Host smart-8ed1a1e3-068d-4626-a28f-4f21f3b7dd85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678865333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2678865333
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.134702892
Short name T599
Test name
Test status
Simulation time 55159056128 ps
CPU time 387.79 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 205860 kb
Host smart-4854b71c-5599-4f9d-930b-efb13edd03ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134702892 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.134702892
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.842908830
Short name T320
Test name
Test status
Simulation time 134751136553 ps
CPU time 69.05 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 182804 kb
Host smart-b8a9e2f0-046d-431b-8a7c-bf5357188994
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842908830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.842908830
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1066377503
Short name T528
Test name
Test status
Simulation time 166163428480 ps
CPU time 124.76 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:38:00 PM PST 23
Peak memory 182868 kb
Host smart-2cb45d91-0666-4005-90b5-c948e571c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066377503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1066377503
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2714180477
Short name T131
Test name
Test status
Simulation time 410680559418 ps
CPU time 235.69 seconds
Started Dec 27 12:36:54 PM PST 23
Finished Dec 27 12:41:15 PM PST 23
Peak memory 190964 kb
Host smart-edc1ce99-68ce-4b3c-9bab-80682855326e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714180477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2714180477
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3300371456
Short name T161
Test name
Test status
Simulation time 135961793392 ps
CPU time 241.2 seconds
Started Dec 27 12:34:40 PM PST 23
Finished Dec 27 12:38:58 PM PST 23
Peak memory 194896 kb
Host smart-c935a52a-fce8-42c6-9cb4-7e9c6fd53806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300371456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3300371456
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2765665245
Short name T507
Test name
Test status
Simulation time 35083368875 ps
CPU time 367.61 seconds
Started Dec 27 12:35:16 PM PST 23
Finished Dec 27 12:41:40 PM PST 23
Peak memory 205676 kb
Host smart-346a7926-2d2b-48d2-bcef-c27e0c38256c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765665245 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2765665245
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2048338583
Short name T554
Test name
Test status
Simulation time 43748964496 ps
CPU time 24.91 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:35:56 PM PST 23
Peak memory 182848 kb
Host smart-48263e21-7ea7-468f-8c62-8d9baec044c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048338583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2048338583
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1641889114
Short name T603
Test name
Test status
Simulation time 197972413553 ps
CPU time 137.21 seconds
Started Dec 27 12:34:53 PM PST 23
Finished Dec 27 12:37:31 PM PST 23
Peak memory 182876 kb
Host smart-bbc7d651-7d46-4586-aa0c-33f20e2e5cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641889114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1641889114
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1476826281
Short name T136
Test name
Test status
Simulation time 48274677759 ps
CPU time 74.57 seconds
Started Dec 27 12:35:16 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 182820 kb
Host smart-13009f65-c581-433f-90aa-c36c99e52051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476826281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1476826281
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.758029313
Short name T535
Test name
Test status
Simulation time 129337182772 ps
CPU time 302.18 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:40:44 PM PST 23
Peak memory 205752 kb
Host smart-4b6f4a48-5985-4f46-b5d1-833e1cdc702d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758029313 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.758029313
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1627534604
Short name T102
Test name
Test status
Simulation time 7253192864 ps
CPU time 12.69 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:35:34 PM PST 23
Peak memory 182808 kb
Host smart-f9f1192d-7333-4cf3-8fae-fdbcf484f6bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627534604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1627534604
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3826488123
Short name T557
Test name
Test status
Simulation time 156132398415 ps
CPU time 241.79 seconds
Started Dec 27 12:34:59 PM PST 23
Finished Dec 27 12:39:20 PM PST 23
Peak memory 182956 kb
Host smart-4f5befed-52b9-4253-8750-3d6fafaaf7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826488123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3826488123
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1579760258
Short name T266
Test name
Test status
Simulation time 981381516425 ps
CPU time 408.53 seconds
Started Dec 27 12:35:12 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 192228 kb
Host smart-9ee0881a-4bb6-47c1-9fb2-baf9151e4642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579760258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1579760258
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2470700350
Short name T275
Test name
Test status
Simulation time 165949347951 ps
CPU time 82.58 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 191052 kb
Host smart-e275fe74-67ce-421e-a812-119bccd2bb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470700350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2470700350
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.782894182
Short name T334
Test name
Test status
Simulation time 160710969383 ps
CPU time 261.11 seconds
Started Dec 27 12:34:44 PM PST 23
Finished Dec 27 12:39:24 PM PST 23
Peak memory 191008 kb
Host smart-b73d18a0-90a2-418c-b9b1-b0be0c056b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782894182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
782894182
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2771874125
Short name T584
Test name
Test status
Simulation time 47841014896 ps
CPU time 524.69 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:43:57 PM PST 23
Peak memory 210532 kb
Host smart-7f1ff1b8-4404-4068-ac5e-8b047cdcb021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771874125 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2771874125
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1091172942
Short name T188
Test name
Test status
Simulation time 1331903937922 ps
CPU time 545.62 seconds
Started Dec 27 12:34:56 PM PST 23
Finished Dec 27 12:44:23 PM PST 23
Peak memory 182728 kb
Host smart-c951073c-2c8d-4b28-963a-0938f257ca9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091172942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1091172942
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4212569646
Short name T25
Test name
Test status
Simulation time 59549095177 ps
CPU time 81.4 seconds
Started Dec 27 12:34:46 PM PST 23
Finished Dec 27 12:36:27 PM PST 23
Peak memory 182956 kb
Host smart-7310a8ef-dfa9-4749-b880-5bdd3173f732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212569646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4212569646
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.4072286572
Short name T237
Test name
Test status
Simulation time 304030746025 ps
CPU time 1650.68 seconds
Started Dec 27 12:36:06 PM PST 23
Finished Dec 27 01:03:58 PM PST 23
Peak memory 191132 kb
Host smart-c97c8c7d-a605-4708-b4b2-5a5a9a05a03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072286572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.4072286572
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4191194284
Short name T294
Test name
Test status
Simulation time 30949209895 ps
CPU time 42.13 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:36:43 PM PST 23
Peak memory 182820 kb
Host smart-6cdf616f-3273-4530-9277-72bf3b968b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191194284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4191194284
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3754278977
Short name T235
Test name
Test status
Simulation time 81259333483 ps
CPU time 194.96 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 194848 kb
Host smart-8caa23be-d4be-49b5-9168-c6f0eafe9d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754278977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3754278977
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.405019967
Short name T566
Test name
Test status
Simulation time 102792878996 ps
CPU time 143.43 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 182832 kb
Host smart-e26f18bf-4787-4ed0-8608-5dfef4c720d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405019967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.405019967
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1273685637
Short name T327
Test name
Test status
Simulation time 324140626780 ps
CPU time 192.4 seconds
Started Dec 27 12:34:44 PM PST 23
Finished Dec 27 12:38:15 PM PST 23
Peak memory 191152 kb
Host smart-50ab8f03-075c-4698-ae4d-6c9cfd1fbdbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273685637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1273685637
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.775691944
Short name T593
Test name
Test status
Simulation time 6439142463 ps
CPU time 5.36 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:35:40 PM PST 23
Peak memory 191044 kb
Host smart-34a84374-b007-44dc-ba80-37b4e5368e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775691944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.775691944
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1778037136
Short name T217
Test name
Test status
Simulation time 153149829168 ps
CPU time 85.81 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 205660 kb
Host smart-41b74935-67b9-41be-861e-27bc3ff711ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778037136 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1778037136
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.73747165
Short name T517
Test name
Test status
Simulation time 115347119694 ps
CPU time 178.88 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:40:29 PM PST 23
Peak memory 182456 kb
Host smart-05f996bb-202a-4b0e-ae8f-14f772344a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73747165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.73747165
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.109458796
Short name T607
Test name
Test status
Simulation time 188019382612 ps
CPU time 332.47 seconds
Started Dec 27 12:35:02 PM PST 23
Finished Dec 27 12:40:53 PM PST 23
Peak memory 191068 kb
Host smart-5ef82e62-2473-49d6-9bed-2b3b2892965e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109458796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.109458796
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1328796140
Short name T533
Test name
Test status
Simulation time 69395919307 ps
CPU time 191.29 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:39:00 PM PST 23
Peak memory 182956 kb
Host smart-2607b612-ab6a-4aa6-817d-4bb1d2a0d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328796140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1328796140
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3152198260
Short name T611
Test name
Test status
Simulation time 297724078992 ps
CPU time 1514.2 seconds
Started Dec 27 12:35:11 PM PST 23
Finished Dec 27 01:00:42 PM PST 23
Peak memory 213276 kb
Host smart-35775e8a-1f50-41fa-848c-167cef6922db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152198260 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3152198260
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3991959641
Short name T610
Test name
Test status
Simulation time 622075867403 ps
CPU time 251.14 seconds
Started Dec 27 12:35:08 PM PST 23
Finished Dec 27 12:39:37 PM PST 23
Peak memory 182828 kb
Host smart-841c33a9-e042-4b44-9720-f1e2e05442fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991959641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3991959641
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.683420595
Short name T370
Test name
Test status
Simulation time 553261399128 ps
CPU time 155.23 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:38:02 PM PST 23
Peak memory 191064 kb
Host smart-4fb673d1-ca7b-4364-8853-9ad0ecb623fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683420595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.683420595
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1859815119
Short name T572
Test name
Test status
Simulation time 394050785 ps
CPU time 1.04 seconds
Started Dec 27 12:35:20 PM PST 23
Finished Dec 27 12:35:37 PM PST 23
Peak memory 193664 kb
Host smart-9007bdb4-4d42-4141-b3aa-3c9d1d372f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859815119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1859815119
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3904626367
Short name T601
Test name
Test status
Simulation time 166569811958 ps
CPU time 244.44 seconds
Started Dec 27 12:35:09 PM PST 23
Finished Dec 27 12:39:31 PM PST 23
Peak memory 182884 kb
Host smart-99a5a619-18cd-485c-977d-12ef6eb77eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904626367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3904626367
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1342412333
Short name T36
Test name
Test status
Simulation time 372307783385 ps
CPU time 886.06 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:50:04 PM PST 23
Peak memory 209924 kb
Host smart-7b4c6e98-cee1-43bb-9539-e3acb93f1485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342412333 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1342412333
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.422168139
Short name T170
Test name
Test status
Simulation time 41314514666 ps
CPU time 70.45 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:38:45 PM PST 23
Peak memory 182452 kb
Host smart-b4a08d4f-35e5-4a18-89c4-77edbcfb42c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422168139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.422168139
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.506415642
Short name T491
Test name
Test status
Simulation time 156956161368 ps
CPU time 135.76 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:38:22 PM PST 23
Peak memory 182824 kb
Host smart-4a102731-935c-4792-83ff-3d6dc281e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506415642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.506415642
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.392660557
Short name T121
Test name
Test status
Simulation time 203061945760 ps
CPU time 389.76 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 12:41:52 PM PST 23
Peak memory 191200 kb
Host smart-7f6f2020-6b98-4e54-b0fe-304717fb3e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392660557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.392660557
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2275387274
Short name T489
Test name
Test status
Simulation time 113985258 ps
CPU time 0.72 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:35:32 PM PST 23
Peak memory 182680 kb
Host smart-6b876e0e-6f81-492b-891a-41852a5456e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275387274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2275387274
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1024788868
Short name T487
Test name
Test status
Simulation time 1361403600247 ps
CPU time 548.05 seconds
Started Dec 27 12:35:07 PM PST 23
Finished Dec 27 12:44:32 PM PST 23
Peak memory 191036 kb
Host smart-f47047d5-24d7-4977-ae75-be50e0c64cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024788868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1024788868
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1822752479
Short name T615
Test name
Test status
Simulation time 146060723670 ps
CPU time 956.69 seconds
Started Dec 27 12:35:21 PM PST 23
Finished Dec 27 12:51:33 PM PST 23
Peak memory 207640 kb
Host smart-5ea24199-d619-4fc5-a610-8266d165fdfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822752479 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1822752479
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.330222844
Short name T366
Test name
Test status
Simulation time 2064192111181 ps
CPU time 752.75 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:48:22 PM PST 23
Peak memory 182832 kb
Host smart-5e303d0d-64c0-4ba2-a153-a263022de61b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330222844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.330222844
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3438782385
Short name T521
Test name
Test status
Simulation time 476872214338 ps
CPU time 202.56 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:39:04 PM PST 23
Peak memory 182800 kb
Host smart-50de8a81-2ae5-4e12-90f0-a30b3336e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438782385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3438782385
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2007054882
Short name T592
Test name
Test status
Simulation time 133187928493 ps
CPU time 101.72 seconds
Started Dec 27 12:34:48 PM PST 23
Finished Dec 27 12:36:54 PM PST 23
Peak memory 194516 kb
Host smart-a0b959f6-22f4-4e07-ad9f-d795e4ccde17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007054882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2007054882
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3515103808
Short name T512
Test name
Test status
Simulation time 63872737 ps
CPU time 0.82 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:36 PM PST 23
Peak memory 181684 kb
Host smart-adf1b8a7-8eb5-495e-9ea5-59431fb91e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515103808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3515103808
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4180983030
Short name T289
Test name
Test status
Simulation time 223413828548 ps
CPU time 602.8 seconds
Started Dec 27 12:36:55 PM PST 23
Finished Dec 27 12:47:23 PM PST 23
Peak memory 190912 kb
Host smart-7ee15acf-ee89-4f94-98ed-7489177ba991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180983030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4180983030
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2748664281
Short name T488
Test name
Test status
Simulation time 124105404868 ps
CPU time 608.69 seconds
Started Dec 27 12:34:54 PM PST 23
Finished Dec 27 12:45:24 PM PST 23
Peak memory 206952 kb
Host smart-4c9b1a6b-44b5-4895-8bb9-ab1e4887f4e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748664281 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2748664281
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2327674602
Short name T614
Test name
Test status
Simulation time 647099428370 ps
CPU time 533.22 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:46:25 PM PST 23
Peak memory 182452 kb
Host smart-7fdefcc2-eefc-4078-a745-16b6e7226fab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327674602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2327674602
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.776610045
Short name T509
Test name
Test status
Simulation time 325316667361 ps
CPU time 147.02 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:38:04 PM PST 23
Peak memory 182912 kb
Host smart-e6a24eff-ccaf-43ff-b8a3-2095393f7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776610045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.776610045
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.4252929107
Short name T537
Test name
Test status
Simulation time 6111545541 ps
CPU time 7.16 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:36:02 PM PST 23
Peak memory 182864 kb
Host smart-c0299dc1-43b4-42d5-913c-c4f6b6267ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252929107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.4252929107
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2953853407
Short name T132
Test name
Test status
Simulation time 491044740967 ps
CPU time 621.31 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 190804 kb
Host smart-aad3eb9f-9098-4cb1-a2d9-a7f17e6484de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953853407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2953853407
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2374369750
Short name T484
Test name
Test status
Simulation time 33559342423 ps
CPU time 240 seconds
Started Dec 27 12:34:50 PM PST 23
Finished Dec 27 12:39:11 PM PST 23
Peak memory 197560 kb
Host smart-cab6c895-449a-4002-8be4-e2ff59c869b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374369750 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2374369750
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1013014309
Short name T323
Test name
Test status
Simulation time 4086911125 ps
CPU time 7.04 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:35:20 PM PST 23
Peak memory 182748 kb
Host smart-5f7274b5-0e5d-48d5-88b6-6c5a6bfcb07e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013014309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1013014309
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3524758349
Short name T6
Test name
Test status
Simulation time 31734204228 ps
CPU time 46.58 seconds
Started Dec 27 12:34:47 PM PST 23
Finished Dec 27 12:35:54 PM PST 23
Peak memory 182800 kb
Host smart-b7c1c2ba-15c5-4d84-88c3-99879fea15df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524758349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3524758349
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.207878874
Short name T197
Test name
Test status
Simulation time 46192721723 ps
CPU time 89.34 seconds
Started Dec 27 12:34:54 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 182848 kb
Host smart-95ef0cb1-eed6-4e3c-b359-e8959c8cd89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207878874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.207878874
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2081725165
Short name T18
Test name
Test status
Simulation time 70746119 ps
CPU time 0.81 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:35:38 PM PST 23
Peak memory 212780 kb
Host smart-e2bebdff-6311-4092-8437-13ee5f04279b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081725165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2081725165
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4168592425
Short name T492
Test name
Test status
Simulation time 102221283 ps
CPU time 0.57 seconds
Started Dec 27 12:34:53 PM PST 23
Finished Dec 27 12:35:14 PM PST 23
Peak memory 182464 kb
Host smart-0c2d5d19-6264-41b7-8475-3fbee2f1502f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168592425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4168592425
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3767621593
Short name T549
Test name
Test status
Simulation time 213154035079 ps
CPU time 204.99 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:38:56 PM PST 23
Peak memory 205800 kb
Host smart-d539c9cb-89d9-4ecc-a92e-4419c5fa5a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767621593 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3767621593
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1713283521
Short name T522
Test name
Test status
Simulation time 54880858460 ps
CPU time 85.02 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 182920 kb
Host smart-f2bedc3c-b22d-4f25-b1c7-f7cd35e800be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713283521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1713283521
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4201170758
Short name T126
Test name
Test status
Simulation time 30182749706 ps
CPU time 48.93 seconds
Started Dec 27 12:35:08 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 193564 kb
Host smart-f7a4eb3e-ea59-4305-80ee-be2d2869b3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201170758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4201170758
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.920346355
Short name T589
Test name
Test status
Simulation time 9829513095 ps
CPU time 11.04 seconds
Started Dec 27 12:37:12 PM PST 23
Finished Dec 27 12:37:45 PM PST 23
Peak memory 182436 kb
Host smart-75631ba4-68e1-48ab-9daf-d70bbd4af1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920346355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.920346355
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2422221984
Short name T313
Test name
Test status
Simulation time 516626293198 ps
CPU time 774.54 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:48:56 PM PST 23
Peak memory 191008 kb
Host smart-193b8eee-28fe-4bd5-8608-121c4e96f759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422221984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2422221984
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2102369727
Short name T498
Test name
Test status
Simulation time 48137937329 ps
CPU time 535.16 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:45:23 PM PST 23
Peak memory 204864 kb
Host smart-2a5fb28b-99de-418e-aa74-e4c0176fce0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102369727 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2102369727
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2156111078
Short name T345
Test name
Test status
Simulation time 2361205089187 ps
CPU time 575.58 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:46:11 PM PST 23
Peak memory 181400 kb
Host smart-93f00c0c-7c71-43e8-95c2-e13865c9e07f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156111078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2156111078
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3870123162
Short name T525
Test name
Test status
Simulation time 125111493010 ps
CPU time 92.77 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:38:08 PM PST 23
Peak memory 181356 kb
Host smart-ae4cd2d8-5f8f-4ab6-bc6d-41989a5519bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870123162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3870123162
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3484690425
Short name T278
Test name
Test status
Simulation time 161352635391 ps
CPU time 379.25 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 191144 kb
Host smart-6aba21ea-0260-4aa5-935d-3dc734166d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484690425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3484690425
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4271022769
Short name T257
Test name
Test status
Simulation time 144756609923 ps
CPU time 161.14 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:38:16 PM PST 23
Peak memory 190980 kb
Host smart-957f6e53-17bd-4444-b6c4-ca692015bc08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271022769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4271022769
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.4193928679
Short name T519
Test name
Test status
Simulation time 62287132020 ps
CPU time 730.96 seconds
Started Dec 27 12:35:11 PM PST 23
Finished Dec 27 12:47:39 PM PST 23
Peak memory 212920 kb
Host smart-7f8eb168-c73b-4b39-b2d9-861044a2aff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193928679 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.4193928679
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4166423197
Short name T226
Test name
Test status
Simulation time 253066604482 ps
CPU time 415.83 seconds
Started Dec 27 12:35:26 PM PST 23
Finished Dec 27 12:42:40 PM PST 23
Peak memory 182820 kb
Host smart-8879e2ab-f127-4745-a684-b7c4cfef7061
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166423197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.4166423197
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1143176928
Short name T618
Test name
Test status
Simulation time 655735138345 ps
CPU time 235.91 seconds
Started Dec 27 12:36:47 PM PST 23
Finished Dec 27 12:41:11 PM PST 23
Peak memory 182612 kb
Host smart-e4d52544-4504-4fb8-b298-4ff66585a313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143176928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1143176928
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.4238715167
Short name T558
Test name
Test status
Simulation time 61517753 ps
CPU time 0.53 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:35:21 PM PST 23
Peak memory 182400 kb
Host smart-c0e07be4-e8b9-412f-95f3-8af79d3415a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238715167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.4238715167
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3269190816
Short name T358
Test name
Test status
Simulation time 196823665994 ps
CPU time 956.64 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:53:20 PM PST 23
Peak memory 208424 kb
Host smart-f8c2b265-d122-4fc8-b943-59f06c13719f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269190816 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3269190816
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2277089779
Short name T248
Test name
Test status
Simulation time 2958903243 ps
CPU time 5.92 seconds
Started Dec 27 12:34:48 PM PST 23
Finished Dec 27 12:35:13 PM PST 23
Peak memory 182820 kb
Host smart-2e8ad7ed-d3c7-41e5-902f-339e0f156aa9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277089779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2277089779
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.442096521
Short name T539
Test name
Test status
Simulation time 66098149117 ps
CPU time 81 seconds
Started Dec 27 12:35:30 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 182956 kb
Host smart-2cf7bb53-5d34-4331-95bd-9f1cdaf14598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442096521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.442096521
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.371311439
Short name T12
Test name
Test status
Simulation time 22867101226 ps
CPU time 23.75 seconds
Started Dec 27 12:36:16 PM PST 23
Finished Dec 27 12:37:01 PM PST 23
Peak memory 190496 kb
Host smart-8b4a4350-4410-4a42-99e7-06205409b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371311439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.371311439
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1573351362
Short name T134
Test name
Test status
Simulation time 2829301392432 ps
CPU time 1272.55 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 190804 kb
Host smart-66ee59f1-5abb-4b8f-9c12-369daaf1ac3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573351362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1573351362
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3854019469
Short name T565
Test name
Test status
Simulation time 27124581266 ps
CPU time 615.33 seconds
Started Dec 27 12:36:40 PM PST 23
Finished Dec 27 12:47:25 PM PST 23
Peak memory 197312 kb
Host smart-8c8716d8-f268-4c08-bffa-abf658501daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854019469 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3854019469
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1807490731
Short name T270
Test name
Test status
Simulation time 679202516344 ps
CPU time 251.33 seconds
Started Dec 27 12:36:48 PM PST 23
Finished Dec 27 12:41:27 PM PST 23
Peak memory 182452 kb
Host smart-efe7e3ce-f47a-4f47-bbe4-3947e31a6f37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807490731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1807490731
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3282165781
Short name T499
Test name
Test status
Simulation time 395598125368 ps
CPU time 147.53 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:38:57 PM PST 23
Peak memory 182396 kb
Host smart-06841bf5-3b17-4b83-9de8-245e1c8f2d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282165781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3282165781
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3061025128
Short name T159
Test name
Test status
Simulation time 290064966601 ps
CPU time 181.36 seconds
Started Dec 27 12:36:53 PM PST 23
Finished Dec 27 12:40:20 PM PST 23
Peak memory 193896 kb
Host smart-d3efbc45-3bcc-4271-882d-e92663487008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061025128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3061025128
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.285788388
Short name T230
Test name
Test status
Simulation time 137415435824 ps
CPU time 222.1 seconds
Started Dec 27 12:35:11 PM PST 23
Finished Dec 27 12:39:10 PM PST 23
Peak memory 190956 kb
Host smart-9a35a21b-b29c-4f6c-afc6-cc380c2126e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285788388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.285788388
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1472214552
Short name T374
Test name
Test status
Simulation time 283941675159 ps
CPU time 934.93 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:52:46 PM PST 23
Peak memory 190636 kb
Host smart-a78c52db-ce50-4e4b-bd38-6cb5d92f5c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472214552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1472214552
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3626390387
Short name T504
Test name
Test status
Simulation time 255070885687 ps
CPU time 524.06 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:46:14 PM PST 23
Peak memory 205404 kb
Host smart-e64556e7-ec90-4957-808e-f06c70bdb8c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626390387 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3626390387
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3348813630
Short name T523
Test name
Test status
Simulation time 702436326034 ps
CPU time 193.85 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:38:52 PM PST 23
Peak memory 182792 kb
Host smart-2986763e-ee4a-4faf-a20d-30bd65315557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348813630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3348813630
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2342000186
Short name T576
Test name
Test status
Simulation time 109411738740 ps
CPU time 111.92 seconds
Started Dec 27 12:36:51 PM PST 23
Finished Dec 27 12:39:10 PM PST 23
Peak memory 190964 kb
Host smart-db27219d-615a-45d8-a4ed-a75487cf3e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342000186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2342000186
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2605828957
Short name T598
Test name
Test status
Simulation time 16208933455 ps
CPU time 29.92 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:43 PM PST 23
Peak memory 182820 kb
Host smart-d362b418-0b05-48a4-95f8-05a074703e59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605828957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2605828957
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3656421011
Short name T515
Test name
Test status
Simulation time 592593329322 ps
CPU time 214.91 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:41:09 PM PST 23
Peak memory 182784 kb
Host smart-f760d82a-8d8c-495a-9de7-b48bfb5f590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656421011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3656421011
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2377446580
Short name T224
Test name
Test status
Simulation time 66924558015 ps
CPU time 121.75 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:39:39 PM PST 23
Peak memory 182732 kb
Host smart-e777b8a9-e9ef-4591-a999-d819416fc67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377446580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2377446580
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1296909550
Short name T559
Test name
Test status
Simulation time 56961139573 ps
CPU time 587.23 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:45:25 PM PST 23
Peak memory 205744 kb
Host smart-7c781d39-f7f1-4186-aa84-8973319cb8fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296909550 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1296909550
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3038207488
Short name T5
Test name
Test status
Simulation time 181631215600 ps
CPU time 161.73 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:38:38 PM PST 23
Peak memory 182800 kb
Host smart-e94267df-e249-4753-a4ad-3cdbe1071cb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038207488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3038207488
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2410738359
Short name T532
Test name
Test status
Simulation time 182049635129 ps
CPU time 68.6 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:36:47 PM PST 23
Peak memory 182840 kb
Host smart-3e6c3c45-8668-436f-9884-56b307d6956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410738359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2410738359
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3518741053
Short name T173
Test name
Test status
Simulation time 224977199280 ps
CPU time 60.03 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 194576 kb
Host smart-1431e119-f2eb-4267-8355-a668b50d2103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518741053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3518741053
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3735881385
Short name T486
Test name
Test status
Simulation time 33274605430 ps
CPU time 348.82 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 197544 kb
Host smart-d6d7dc3e-7d2a-46cc-8210-f10f6163ae6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735881385 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3735881385
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.646969340
Short name T292
Test name
Test status
Simulation time 266487874900 ps
CPU time 412.26 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 182928 kb
Host smart-d62d013c-c9cd-49ab-ae10-1f5543828a0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646969340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.646969340
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.454667085
Short name T568
Test name
Test status
Simulation time 528959644187 ps
CPU time 185.02 seconds
Started Dec 27 12:36:34 PM PST 23
Finished Dec 27 12:40:07 PM PST 23
Peak memory 182840 kb
Host smart-76a7606b-06cf-4fa9-aef7-1cfd12db80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454667085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.454667085
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3263110462
Short name T343
Test name
Test status
Simulation time 98275971185 ps
CPU time 409.5 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:43:02 PM PST 23
Peak memory 194084 kb
Host smart-04c2458a-3a26-4c10-95e3-f7a58ba944f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263110462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3263110462
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1655413315
Short name T485
Test name
Test status
Simulation time 93223961043 ps
CPU time 357.52 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 205696 kb
Host smart-774738fb-4d96-4628-99e3-187c703b2e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655413315 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1655413315
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.283994326
Short name T258
Test name
Test status
Simulation time 7086233393 ps
CPU time 4.34 seconds
Started Dec 27 12:34:49 PM PST 23
Finished Dec 27 12:35:13 PM PST 23
Peak memory 182940 kb
Host smart-35e2082e-ca3a-4e4b-9721-2f4ad5bc6df4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283994326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.283994326
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3487227891
Short name T555
Test name
Test status
Simulation time 95171052594 ps
CPU time 42.44 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 182860 kb
Host smart-37fa97a5-250d-4b70-a6ef-1403174fb91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487227891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3487227891
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.289914863
Short name T24
Test name
Test status
Simulation time 193131093997 ps
CPU time 578.78 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:45:13 PM PST 23
Peak memory 191040 kb
Host smart-b966be00-849a-4452-9315-758e1e8d6368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289914863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.289914863
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2502059094
Short name T536
Test name
Test status
Simulation time 687927916393 ps
CPU time 1157.68 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:55:06 PM PST 23
Peak memory 215580 kb
Host smart-98591b0f-beb4-48d0-9a21-eec70306812e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502059094 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2502059094
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3949047431
Short name T562
Test name
Test status
Simulation time 28312394783 ps
CPU time 20.78 seconds
Started Dec 27 12:34:55 PM PST 23
Finished Dec 27 12:35:36 PM PST 23
Peak memory 182816 kb
Host smart-50e1f268-a05b-4c00-8adc-9182020f3c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949047431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3949047431
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1193578580
Short name T283
Test name
Test status
Simulation time 128356146900 ps
CPU time 1473.92 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 01:00:19 PM PST 23
Peak memory 190992 kb
Host smart-f7cba93e-8215-4e3c-a5a3-8bb5ea1b6d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193578580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1193578580
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1221159842
Short name T130
Test name
Test status
Simulation time 564916817175 ps
CPU time 187.55 seconds
Started Dec 27 12:35:07 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 191112 kb
Host smart-711b3f76-4b21-4d13-9e3f-270d79d8d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221159842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1221159842
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1070429575
Short name T20
Test name
Test status
Simulation time 38509670 ps
CPU time 0.72 seconds
Started Dec 27 12:35:11 PM PST 23
Finished Dec 27 12:35:29 PM PST 23
Peak memory 212740 kb
Host smart-df8e69c6-ccd1-4ad5-bc25-de649a4b1cc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070429575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1070429575
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2958405771
Short name T493
Test name
Test status
Simulation time 2804646429274 ps
CPU time 589.28 seconds
Started Dec 27 12:34:45 PM PST 23
Finished Dec 27 12:44:53 PM PST 23
Peak memory 191316 kb
Host smart-6d83f977-95c6-498d-8752-5e9ef5a2f7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958405771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2958405771
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2918920983
Short name T37
Test name
Test status
Simulation time 51772848217 ps
CPU time 105.64 seconds
Started Dec 27 12:34:54 PM PST 23
Finished Dec 27 12:37:00 PM PST 23
Peak memory 205724 kb
Host smart-ea06ec71-e40b-45ac-95eb-4bb7f604b557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918920983 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2918920983
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2848148707
Short name T7
Test name
Test status
Simulation time 787095708287 ps
CPU time 444.03 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:43:20 PM PST 23
Peak memory 182800 kb
Host smart-abc1f6e5-5498-4f88-b990-db213c99f6e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848148707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2848148707
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3931473652
Short name T505
Test name
Test status
Simulation time 314324880133 ps
CPU time 271.37 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:40:09 PM PST 23
Peak memory 182916 kb
Host smart-abe4faab-9a91-48aa-801d-b68d8a6c7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931473652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3931473652
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3356804945
Short name T116
Test name
Test status
Simulation time 123849475982 ps
CPU time 362.91 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 190848 kb
Host smart-0d72c003-507b-49da-8c18-ea6709690c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356804945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3356804945
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1412456765
Short name T4
Test name
Test status
Simulation time 21325027952 ps
CPU time 33.42 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:35:53 PM PST 23
Peak memory 182840 kb
Host smart-64ddf1cd-2953-416a-a27d-a30bfc1e3f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412456765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1412456765
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2163444281
Short name T586
Test name
Test status
Simulation time 21032292491 ps
CPU time 163.93 seconds
Started Dec 27 12:35:46 PM PST 23
Finished Dec 27 12:38:50 PM PST 23
Peak memory 197540 kb
Host smart-8a3ba5f5-c164-4701-ae9d-8ef53d216910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163444281 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2163444281
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1094715216
Short name T27
Test name
Test status
Simulation time 785440743662 ps
CPU time 696.72 seconds
Started Dec 27 12:34:55 PM PST 23
Finished Dec 27 12:46:52 PM PST 23
Peak memory 182808 kb
Host smart-9affe3f7-99d7-4df4-aab3-00d6a5e18acd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094715216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1094715216
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.4100208808
Short name T534
Test name
Test status
Simulation time 349837301793 ps
CPU time 139.69 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:37:55 PM PST 23
Peak memory 182920 kb
Host smart-6972fd35-c8f4-4f16-ad0d-6d00ba957dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100208808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.4100208808
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2930552449
Short name T207
Test name
Test status
Simulation time 68872398161 ps
CPU time 123.48 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 12:37:26 PM PST 23
Peak memory 191056 kb
Host smart-b54c313a-a9c6-4833-91d1-9cb9a509704b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930552449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2930552449
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.686960274
Short name T351
Test name
Test status
Simulation time 121512959122 ps
CPU time 50.02 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:36:47 PM PST 23
Peak memory 191172 kb
Host smart-fdc6e3df-3c73-4794-8d20-b2dc962fec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686960274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.686960274
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.305826149
Short name T494
Test name
Test status
Simulation time 25932996 ps
CPU time 0.56 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 182364 kb
Host smart-14fcb2b2-87cb-4395-a90b-eb332509f93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305826149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
305826149
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2041043758
Short name T335
Test name
Test status
Simulation time 436125296389 ps
CPU time 757.16 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 206828 kb
Host smart-c83aab14-e4eb-4b84-a6ab-d8ed8a080311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041043758 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2041043758
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1875576720
Short name T240
Test name
Test status
Simulation time 1099717655098 ps
CPU time 553.11 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:44:44 PM PST 23
Peak memory 182844 kb
Host smart-6907882f-4409-4e35-a447-45324ea7f0e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875576720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1875576720
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.372780963
Short name T483
Test name
Test status
Simulation time 744770618776 ps
CPU time 288.38 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:41:16 PM PST 23
Peak memory 182908 kb
Host smart-f6d11ce3-adf4-4610-ad72-472401330894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372780963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.372780963
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2072262403
Short name T145
Test name
Test status
Simulation time 31801289082 ps
CPU time 115.77 seconds
Started Dec 27 12:35:08 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 190964 kb
Host smart-6a38f5ee-59f9-40ba-9330-5bb1bd452182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072262403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2072262403
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2176636079
Short name T530
Test name
Test status
Simulation time 237106169 ps
CPU time 0.93 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 182640 kb
Host smart-beb4ee5a-1c36-49a9-9ab5-81fa047c73ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176636079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2176636079
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4232140756
Short name T354
Test name
Test status
Simulation time 400073698530 ps
CPU time 654.1 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:46:38 PM PST 23
Peak memory 191032 kb
Host smart-38103ca6-8a6f-4c07-986f-b043263bbcd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232140756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4232140756
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2082897862
Short name T318
Test name
Test status
Simulation time 479129467478 ps
CPU time 1381.08 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 213916 kb
Host smart-6e465993-33bb-4faf-876e-e35d93ccc574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082897862 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2082897862
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.114451622
Short name T215
Test name
Test status
Simulation time 35660221267 ps
CPU time 20.16 seconds
Started Dec 27 12:36:16 PM PST 23
Finished Dec 27 12:36:57 PM PST 23
Peak memory 182900 kb
Host smart-00973279-12c7-4c51-8f52-d060cee14fd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114451622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.114451622
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3545359521
Short name T617
Test name
Test status
Simulation time 110646883662 ps
CPU time 169.68 seconds
Started Dec 27 12:34:50 PM PST 23
Finished Dec 27 12:38:00 PM PST 23
Peak memory 182868 kb
Host smart-269f0443-5693-40e8-af66-aa6c46eef871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545359521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3545359521
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3641283625
Short name T227
Test name
Test status
Simulation time 677628569075 ps
CPU time 434.39 seconds
Started Dec 27 12:35:08 PM PST 23
Finished Dec 27 12:42:40 PM PST 23
Peak memory 191128 kb
Host smart-f3ae2e87-7dd4-4ec3-89a3-b4183eaa107e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641283625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3641283625
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2933698686
Short name T575
Test name
Test status
Simulation time 232920652994 ps
CPU time 715.75 seconds
Started Dec 27 12:35:30 PM PST 23
Finished Dec 27 12:47:39 PM PST 23
Peak memory 205884 kb
Host smart-64b92a19-3613-4936-ad75-f38b357902b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933698686 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2933698686
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4280469316
Short name T22
Test name
Test status
Simulation time 1520883178006 ps
CPU time 432.95 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:42:50 PM PST 23
Peak memory 182820 kb
Host smart-df2cb8ee-aeca-4f53-8eff-4e107826c8d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280469316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4280469316
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3772827950
Short name T571
Test name
Test status
Simulation time 213129419933 ps
CPU time 165.03 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:38:29 PM PST 23
Peak memory 182880 kb
Host smart-9a923a91-5ee4-40a8-8d00-ecf340493128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772827950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3772827950
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3934199483
Short name T1
Test name
Test status
Simulation time 421722506703 ps
CPU time 934.38 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:51:22 PM PST 23
Peak memory 191008 kb
Host smart-0c3ba5ac-e5ae-4653-85dc-5ccb0cd075ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934199483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3934199483
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1737713511
Short name T588
Test name
Test status
Simulation time 244626750976 ps
CPU time 1737.04 seconds
Started Dec 27 12:35:02 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 182964 kb
Host smart-047ecc2a-cce8-4e0f-945a-1331b72100de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737713511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1737713511
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1805466294
Short name T543
Test name
Test status
Simulation time 176165085797 ps
CPU time 639.42 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 206436 kb
Host smart-f0ea225a-e8bd-48d4-8db8-b678732d5e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805466294 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1805466294
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3938414904
Short name T337
Test name
Test status
Simulation time 191554805100 ps
CPU time 353.31 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 182772 kb
Host smart-e18e9010-313c-4557-b79a-702021515cd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938414904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3938414904
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.48196970
Short name T548
Test name
Test status
Simulation time 234793448854 ps
CPU time 173.97 seconds
Started Dec 27 12:34:55 PM PST 23
Finished Dec 27 12:38:10 PM PST 23
Peak memory 182876 kb
Host smart-acf50743-d46f-41fe-accc-17a15b519496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48196970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.48196970
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2291799485
Short name T279
Test name
Test status
Simulation time 29068601579 ps
CPU time 58.09 seconds
Started Dec 27 12:35:02 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 191024 kb
Host smart-05c55fec-06bb-4643-8c34-1d8e06b024c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291799485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2291799485
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.865503997
Short name T231
Test name
Test status
Simulation time 381377490132 ps
CPU time 637.81 seconds
Started Dec 27 12:35:12 PM PST 23
Finished Dec 27 12:46:06 PM PST 23
Peak memory 191032 kb
Host smart-1896d094-1e52-4615-8a20-9b4c7550ffd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865503997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
865503997
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3879298696
Short name T597
Test name
Test status
Simulation time 33676325203 ps
CPU time 469.67 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:43:35 PM PST 23
Peak memory 205708 kb
Host smart-ed1c029e-bd75-4c4a-a7d9-e2aa5a1f4cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879298696 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.3879298696
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.399112563
Short name T314
Test name
Test status
Simulation time 600099134568 ps
CPU time 511.79 seconds
Started Dec 27 12:35:45 PM PST 23
Finished Dec 27 12:44:36 PM PST 23
Peak memory 182948 kb
Host smart-0d68ab65-7624-4e33-95f0-88c23596b035
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399112563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.399112563
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1611713703
Short name T563
Test name
Test status
Simulation time 76219113707 ps
CPU time 121.69 seconds
Started Dec 27 12:35:49 PM PST 23
Finished Dec 27 12:38:09 PM PST 23
Peak memory 182836 kb
Host smart-703018be-3d61-4754-8673-b8c45fdef46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611713703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1611713703
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.826473819
Short name T128
Test name
Test status
Simulation time 93346688188 ps
CPU time 542.61 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:44:37 PM PST 23
Peak memory 182912 kb
Host smart-06506d59-b7d1-4a11-8f9e-a5ba6fb20947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826473819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.826473819
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3317347707
Short name T518
Test name
Test status
Simulation time 112649877 ps
CPU time 0.97 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:35:46 PM PST 23
Peak memory 182664 kb
Host smart-d8e5af6f-44c7-43e2-ad6b-f8d75d932afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317347707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3317347707
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1336105853
Short name T490
Test name
Test status
Simulation time 182863466901 ps
CPU time 285.63 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:40:21 PM PST 23
Peak memory 182924 kb
Host smart-8dfaa8e5-74c2-4162-a512-8aeb9bfd167f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336105853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1336105853
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.4046212529
Short name T501
Test name
Test status
Simulation time 72517338865 ps
CPU time 848.35 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:50:01 PM PST 23
Peak memory 208712 kb
Host smart-a2c0e54a-c24d-4c13-8867-34607efb95d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046212529 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.4046212529
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3872079455
Short name T162
Test name
Test status
Simulation time 190523590757 ps
CPU time 187.69 seconds
Started Dec 27 12:34:47 PM PST 23
Finished Dec 27 12:38:15 PM PST 23
Peak memory 182968 kb
Host smart-78b3b920-51cc-486c-b2f8-80c2d7918ab8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872079455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3872079455
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2103483902
Short name T600
Test name
Test status
Simulation time 306337259798 ps
CPU time 249.45 seconds
Started Dec 27 12:35:20 PM PST 23
Finished Dec 27 12:39:45 PM PST 23
Peak memory 182964 kb
Host smart-e325ebac-fd7b-43c9-aa9c-6ce60d8cc720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103483902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2103483902
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.283623800
Short name T317
Test name
Test status
Simulation time 88612063209 ps
CPU time 152.77 seconds
Started Dec 27 12:35:09 PM PST 23
Finished Dec 27 12:37:59 PM PST 23
Peak memory 191056 kb
Host smart-354d83ad-a888-4155-be35-ae9d585db842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283623800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.283623800
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3808194044
Short name T578
Test name
Test status
Simulation time 39043981368 ps
CPU time 17.56 seconds
Started Dec 27 12:35:01 PM PST 23
Finished Dec 27 12:35:37 PM PST 23
Peak memory 191196 kb
Host smart-6b3a48c8-f8d1-4b98-8801-291620f555d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808194044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3808194044
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2654570117
Short name T573
Test name
Test status
Simulation time 104776837847 ps
CPU time 855.42 seconds
Started Dec 27 12:35:17 PM PST 23
Finished Dec 27 12:49:48 PM PST 23
Peak memory 205732 kb
Host smart-3ff2df13-da37-49ea-b781-144546fd4d24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654570117 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.2654570117
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1945782389
Short name T544
Test name
Test status
Simulation time 637371105083 ps
CPU time 242.12 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:39:47 PM PST 23
Peak memory 182864 kb
Host smart-a8e9dd5a-4cf6-4c71-b0a6-4bd1059bccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945782389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1945782389
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1948715983
Short name T238
Test name
Test status
Simulation time 324745063177 ps
CPU time 198.05 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:39:05 PM PST 23
Peak memory 191084 kb
Host smart-455423a3-de8d-4be0-813e-779a2cf3aacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948715983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1948715983
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.100954547
Short name T216
Test name
Test status
Simulation time 122351339966 ps
CPU time 106.82 seconds
Started Dec 27 12:35:18 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 182820 kb
Host smart-f3140158-ecf5-4427-b0d2-0b2a2641807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100954547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.100954547
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2293343258
Short name T221
Test name
Test status
Simulation time 985980901857 ps
CPU time 3791.8 seconds
Started Dec 27 12:35:21 PM PST 23
Finished Dec 27 01:38:49 PM PST 23
Peak memory 195272 kb
Host smart-d2cf0628-b4e6-4341-b57f-cebe3b32cbb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293343258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2293343258
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1570267969
Short name T204
Test name
Test status
Simulation time 126262838041 ps
CPU time 1780.69 seconds
Started Dec 27 12:34:55 PM PST 23
Finished Dec 27 01:04:57 PM PST 23
Peak memory 213912 kb
Host smart-cbc357bc-0793-4de7-8dbc-48aaa3fbcb96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570267969 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1570267969
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3557370889
Short name T293
Test name
Test status
Simulation time 79280812627 ps
CPU time 37.65 seconds
Started Dec 27 12:35:09 PM PST 23
Finished Dec 27 12:36:04 PM PST 23
Peak memory 182796 kb
Host smart-e36f03ad-1dc2-4deb-8a8c-deba3e155fda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557370889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3557370889
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.4292881815
Short name T531
Test name
Test status
Simulation time 114272478135 ps
CPU time 186.69 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 182848 kb
Host smart-033ed1f3-6bce-4139-a545-6d804fdc14c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292881815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4292881815
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2035609399
Short name T163
Test name
Test status
Simulation time 8029792340 ps
CPU time 14.77 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 182824 kb
Host smart-5b324241-ed90-4381-8fcb-7f21875e25e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035609399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2035609399
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2265389205
Short name T482
Test name
Test status
Simulation time 1012966324 ps
CPU time 2.6 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:35:34 PM PST 23
Peak memory 190992 kb
Host smart-4e77ea18-643d-4025-9a09-b346c1de2d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265389205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2265389205
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2178586285
Short name T569
Test name
Test status
Simulation time 66386210303 ps
CPU time 240.62 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:39:28 PM PST 23
Peak memory 197704 kb
Host smart-fd149417-1030-4e49-b230-f1cc276a182f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178586285 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2178586285
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2212277700
Short name T594
Test name
Test status
Simulation time 505620642943 ps
CPU time 282.51 seconds
Started Dec 27 12:35:13 PM PST 23
Finished Dec 27 12:40:13 PM PST 23
Peak memory 182796 kb
Host smart-6cc9a831-b2c5-46ed-866d-6a68fe0e6c24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212277700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2212277700
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.342087251
Short name T545
Test name
Test status
Simulation time 215384509329 ps
CPU time 294.41 seconds
Started Dec 27 12:35:00 PM PST 23
Finished Dec 27 12:40:14 PM PST 23
Peak memory 182868 kb
Host smart-d4d841c5-c560-412b-884c-3402f2770a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342087251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.342087251
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.518455638
Short name T372
Test name
Test status
Simulation time 78930740735 ps
CPU time 181.19 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:38:14 PM PST 23
Peak memory 191032 kb
Host smart-480179a3-24cf-4338-8644-b28933dde509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518455638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.518455638
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2907581124
Short name T362
Test name
Test status
Simulation time 24671972936 ps
CPU time 18.67 seconds
Started Dec 27 12:35:12 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 191032 kb
Host smart-eefe047e-ab8c-44b2-9c15-08f8e3f7a244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907581124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2907581124
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3102960892
Short name T497
Test name
Test status
Simulation time 1241887857518 ps
CPU time 312.97 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:40:40 PM PST 23
Peak memory 190980 kb
Host smart-887ebb81-990d-44f9-a18d-ff473d8e8476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102960892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3102960892
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3042195948
Short name T312
Test name
Test status
Simulation time 119771069993 ps
CPU time 439.58 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:42:50 PM PST 23
Peak memory 205696 kb
Host smart-4b815f02-9fc5-4f0a-9a0c-d301b85c16da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042195948 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3042195948
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.2054547662
Short name T176
Test name
Test status
Simulation time 143410731089 ps
CPU time 113.2 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 193320 kb
Host smart-cefd30d8-37fd-4c0f-a88a-912fdee5605f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054547662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2054547662
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1834074477
Short name T222
Test name
Test status
Simulation time 74206688226 ps
CPU time 119.53 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:37:44 PM PST 23
Peak memory 190964 kb
Host smart-88231e60-a088-4e3a-a474-e0f2a901a58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834074477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1834074477
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.885356169
Short name T2
Test name
Test status
Simulation time 177995937153 ps
CPU time 89.03 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:36:56 PM PST 23
Peak memory 182816 kb
Host smart-9a662c95-3317-4f27-8408-5f31ce6f9854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885356169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.885356169
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.168593091
Short name T612
Test name
Test status
Simulation time 83768248064 ps
CPU time 198.4 seconds
Started Dec 27 12:35:05 PM PST 23
Finished Dec 27 12:38:42 PM PST 23
Peak memory 182940 kb
Host smart-5e6ac980-299d-4a86-95c0-e7805a482521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168593091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.168593091
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1209324238
Short name T339
Test name
Test status
Simulation time 89439155180 ps
CPU time 147.72 seconds
Started Dec 27 12:35:21 PM PST 23
Finished Dec 27 12:38:04 PM PST 23
Peak memory 191028 kb
Host smart-69bfc2ca-5061-4942-9dba-c6806937f813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209324238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1209324238
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2129844069
Short name T359
Test name
Test status
Simulation time 123267945735 ps
CPU time 830.9 seconds
Started Dec 27 12:35:43 PM PST 23
Finished Dec 27 12:49:51 PM PST 23
Peak memory 182824 kb
Host smart-cf2c0375-595c-4e11-bc0b-f0cd24f3ed47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129844069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2129844069
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2387512592
Short name T247
Test name
Test status
Simulation time 1566991626412 ps
CPU time 748.43 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 182828 kb
Host smart-5aa918ba-7d21-45c6-afed-3b90a11cc379
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387512592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2387512592
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3637611846
Short name T547
Test name
Test status
Simulation time 559851549990 ps
CPU time 234.24 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:39:15 PM PST 23
Peak memory 182504 kb
Host smart-ab47c94f-c85e-4b9f-b6d4-d2f7b106f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637611846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3637611846
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2287797911
Short name T220
Test name
Test status
Simulation time 36752919982 ps
CPU time 236.59 seconds
Started Dec 27 12:34:36 PM PST 23
Finished Dec 27 12:38:50 PM PST 23
Peak memory 182924 kb
Host smart-a0535cfc-657f-4faa-8e26-2cd3fe9489a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287797911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2287797911
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2652721844
Short name T348
Test name
Test status
Simulation time 5230656013 ps
CPU time 9.25 seconds
Started Dec 27 12:34:41 PM PST 23
Finished Dec 27 12:35:08 PM PST 23
Peak memory 182820 kb
Host smart-f82663ea-5e76-421a-aefe-8327dc1fc5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652721844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2652721844
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3454246093
Short name T582
Test name
Test status
Simulation time 529946966710 ps
CPU time 669.41 seconds
Started Dec 27 12:34:56 PM PST 23
Finished Dec 27 12:46:26 PM PST 23
Peak memory 205820 kb
Host smart-63222277-da1a-43e6-8a50-3ec6f5828815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454246093 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3454246093
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.1173269124
Short name T371
Test name
Test status
Simulation time 22526274120 ps
CPU time 786.55 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:48:55 PM PST 23
Peak memory 182724 kb
Host smart-a85b1c99-3f7e-49ba-abdb-1e5123da7dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173269124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1173269124
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3296811520
Short name T179
Test name
Test status
Simulation time 126325091976 ps
CPU time 199.92 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:39:14 PM PST 23
Peak memory 193956 kb
Host smart-f02202b7-4d9d-4f79-a480-c37c63ec80ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296811520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3296811520
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.243089808
Short name T350
Test name
Test status
Simulation time 193436181740 ps
CPU time 1486.25 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 01:00:17 PM PST 23
Peak memory 191096 kb
Host smart-795e1813-18b1-4780-9b4c-046b188ef6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243089808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.243089808
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.407598743
Short name T577
Test name
Test status
Simulation time 21973335750 ps
CPU time 10.26 seconds
Started Dec 27 12:35:52 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 182972 kb
Host smart-f40295fa-5f7e-46b0-b537-e5c6d8c63341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407598743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.407598743
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1235715531
Short name T373
Test name
Test status
Simulation time 22863737136 ps
CPU time 37.56 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 191320 kb
Host smart-7fc1e5b9-036f-4e6f-a741-ccb5217f3256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235715531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1235715531
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.305409277
Short name T117
Test name
Test status
Simulation time 414076850241 ps
CPU time 260.08 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:39:33 PM PST 23
Peak memory 191164 kb
Host smart-c487492f-7840-4bfc-a13b-9752644850e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305409277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.305409277
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1009170653
Short name T587
Test name
Test status
Simulation time 59221567609 ps
CPU time 98.53 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 194172 kb
Host smart-08c52b56-84dc-4e3d-908e-daf3460034c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009170653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1009170653
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.461453329
Short name T332
Test name
Test status
Simulation time 91385487819 ps
CPU time 853.91 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:50:00 PM PST 23
Peak memory 182964 kb
Host smart-e760d7df-989b-478d-8661-24e2cbcd415b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461453329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.461453329
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2103001951
Short name T178
Test name
Test status
Simulation time 22835263108 ps
CPU time 40.95 seconds
Started Dec 27 12:35:01 PM PST 23
Finished Dec 27 12:36:01 PM PST 23
Peak memory 182768 kb
Host smart-2c876d41-67ed-4484-b54c-4b5d1c2dd482
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103001951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2103001951
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3073861983
Short name T524
Test name
Test status
Simulation time 145852856791 ps
CPU time 227.49 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:39:06 PM PST 23
Peak memory 182936 kb
Host smart-5badfa8d-d2de-43fb-9f90-f6c5b4fa1993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073861983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3073861983
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.700125210
Short name T308
Test name
Test status
Simulation time 583147320445 ps
CPU time 489.29 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:43:47 PM PST 23
Peak memory 182928 kb
Host smart-771b56d8-4de2-420f-b4e0-b504db01cf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700125210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.700125210
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3605046047
Short name T529
Test name
Test status
Simulation time 174188810142 ps
CPU time 122.77 seconds
Started Dec 27 12:34:52 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 183084 kb
Host smart-233e29a6-2c5d-477e-a834-4df911054b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605046047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3605046047
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2383402446
Short name T14
Test name
Test status
Simulation time 58738317075 ps
CPU time 617.91 seconds
Started Dec 27 12:34:51 PM PST 23
Finished Dec 27 12:45:29 PM PST 23
Peak memory 205892 kb
Host smart-9e2d04f7-805b-4913-a8fa-d5fb3bfe09ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383402446 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2383402446
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.941985348
Short name T229
Test name
Test status
Simulation time 138170390644 ps
CPU time 584.73 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:45:55 PM PST 23
Peak memory 191012 kb
Host smart-ca66dc90-5071-4e86-928f-04acd466e784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941985348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.941985348
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1577822873
Short name T602
Test name
Test status
Simulation time 111333242637 ps
CPU time 580.11 seconds
Started Dec 27 12:35:13 PM PST 23
Finished Dec 27 12:45:10 PM PST 23
Peak memory 190928 kb
Host smart-fb8a0138-f3fe-424f-a4c8-3e5c5976d129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577822873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1577822873
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1487876381
Short name T199
Test name
Test status
Simulation time 240028524881 ps
CPU time 79.57 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 182772 kb
Host smart-75ee98cb-fb27-4096-aeb7-d6b7e6be6a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487876381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1487876381
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.50418265
Short name T194
Test name
Test status
Simulation time 54247823974 ps
CPU time 111.88 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 182852 kb
Host smart-4fc29560-513f-4ea3-891d-3ff4ad15abc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50418265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.50418265
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.437748723
Short name T108
Test name
Test status
Simulation time 384077544380 ps
CPU time 458.48 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 191016 kb
Host smart-f0049c0a-aedc-47aa-9f6a-486e9ad9a987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437748723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.437748723
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3406968648
Short name T352
Test name
Test status
Simulation time 119597088827 ps
CPU time 20.74 seconds
Started Dec 27 12:35:17 PM PST 23
Finished Dec 27 12:35:53 PM PST 23
Peak memory 191032 kb
Host smart-3cd36725-ee92-4904-b4dd-adcc04f8fc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406968648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3406968648
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.883463759
Short name T336
Test name
Test status
Simulation time 53283995920 ps
CPU time 83.18 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:37:08 PM PST 23
Peak memory 191060 kb
Host smart-de4543c0-0113-4867-8229-a1357485dbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883463759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.883463759
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.4138568065
Short name T118
Test name
Test status
Simulation time 616763142219 ps
CPU time 3203.48 seconds
Started Dec 27 12:36:13 PM PST 23
Finished Dec 27 01:29:57 PM PST 23
Peak memory 191024 kb
Host smart-c51984ad-2970-49c3-b1d1-9364884e5c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138568065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4138568065
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2447466112
Short name T319
Test name
Test status
Simulation time 24051425127 ps
CPU time 39.25 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 182768 kb
Host smart-56d8412a-1fb6-4655-9f44-ebcb86e1ef89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447466112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2447466112
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3322767290
Short name T496
Test name
Test status
Simulation time 343705111467 ps
CPU time 121.19 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 182872 kb
Host smart-6d4b8c90-32a6-44ea-91b7-113ff2d03b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322767290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3322767290
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2363978553
Short name T223
Test name
Test status
Simulation time 133829337977 ps
CPU time 256.33 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:39:47 PM PST 23
Peak memory 193116 kb
Host smart-32bed0b3-5869-41a0-a1db-46e0a913fb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363978553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2363978553
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.504418307
Short name T303
Test name
Test status
Simulation time 324161932444 ps
CPU time 1390.79 seconds
Started Dec 27 12:35:14 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 191060 kb
Host smart-82608200-03fc-4bf1-9560-b48b5f6569c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504418307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.504418307
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3187974030
Short name T85
Test name
Test status
Simulation time 235259058706 ps
CPU time 1055.07 seconds
Started Dec 27 12:34:58 PM PST 23
Finished Dec 27 12:52:53 PM PST 23
Peak memory 209344 kb
Host smart-bfb7ab31-4de0-408d-a2f9-fc60a941b010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187974030 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3187974030
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.2137555316
Short name T260
Test name
Test status
Simulation time 111888108117 ps
CPU time 480.66 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:43:42 PM PST 23
Peak memory 193924 kb
Host smart-f09b5227-2c63-416b-928e-21f567cb86f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137555316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2137555316
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1648204689
Short name T211
Test name
Test status
Simulation time 390637416935 ps
CPU time 643.45 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:46:28 PM PST 23
Peak memory 191008 kb
Host smart-c971be32-0ddd-4584-936a-b9319829ecc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648204689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1648204689
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.815526757
Short name T189
Test name
Test status
Simulation time 156077245613 ps
CPU time 320.56 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:41:22 PM PST 23
Peak memory 194220 kb
Host smart-b7bdcaaf-0d6c-4e24-8d29-4e4842ebf325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815526757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.815526757
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3557566738
Short name T609
Test name
Test status
Simulation time 46333120069 ps
CPU time 78.99 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 190996 kb
Host smart-34355349-da9a-4966-aac7-965ccaf81a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557566738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3557566738
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3900047963
Short name T520
Test name
Test status
Simulation time 29428646312 ps
CPU time 54.82 seconds
Started Dec 27 12:35:45 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 182880 kb
Host smart-611723c5-f8a3-4710-8913-6676c60b1906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900047963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3900047963
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3783592201
Short name T272
Test name
Test status
Simulation time 306343858853 ps
CPU time 1646.87 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 01:03:05 PM PST 23
Peak memory 191020 kb
Host smart-94358bda-88c0-4586-bfd4-8d3ca17ed2e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783592201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3783592201
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.604659628
Short name T196
Test name
Test status
Simulation time 140208265915 ps
CPU time 874.27 seconds
Started Dec 27 12:35:46 PM PST 23
Finished Dec 27 12:50:40 PM PST 23
Peak memory 191040 kb
Host smart-8c0f6bc0-2fe3-4567-bf13-7a57c7ba5d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604659628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.604659628
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.655713333
Short name T495
Test name
Test status
Simulation time 43682836879 ps
CPU time 378.57 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:41:56 PM PST 23
Peak memory 182788 kb
Host smart-29a35165-1bef-4de2-a0e1-9ab8cc8aebe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655713333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.655713333
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3013547444
Short name T151
Test name
Test status
Simulation time 493236714463 ps
CPU time 353.78 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:41:32 PM PST 23
Peak memory 191084 kb
Host smart-e34d272d-6f18-4b66-a973-1b78cd2cab37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013547444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3013547444
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1441104242
Short name T546
Test name
Test status
Simulation time 10325069388 ps
CPU time 17.2 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:35:38 PM PST 23
Peak memory 182440 kb
Host smart-78b5318d-395c-420b-96e1-637da369ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441104242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1441104242
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.854675291
Short name T184
Test name
Test status
Simulation time 362301908564 ps
CPU time 718.79 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 194256 kb
Host smart-ccf28cce-f237-4211-a10d-bff45672f046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854675291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.854675291
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.4240003499
Short name T94
Test name
Test status
Simulation time 608802354387 ps
CPU time 159.71 seconds
Started Dec 27 12:35:09 PM PST 23
Finished Dec 27 12:38:06 PM PST 23
Peak memory 182964 kb
Host smart-49e576be-c2f7-4974-a7bc-19b57acd569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240003499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4240003499
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1392997628
Short name T35
Test name
Test status
Simulation time 229265194199 ps
CPU time 719.52 seconds
Started Dec 27 12:34:50 PM PST 23
Finished Dec 27 12:47:10 PM PST 23
Peak memory 212304 kb
Host smart-2e631913-515b-4429-ad7e-820f48eb253f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392997628 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1392997628
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3330884383
Short name T306
Test name
Test status
Simulation time 55198993496 ps
CPU time 41.44 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 182840 kb
Host smart-57b26e1a-829c-4a2c-8cac-31c91b48f45f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330884383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3330884383
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1489911675
Short name T149
Test name
Test status
Simulation time 130905145497 ps
CPU time 1382.29 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 191116 kb
Host smart-57e0bdc0-ab33-42ce-b6d3-90b55315a39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489911675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1489911675
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1470687665
Short name T324
Test name
Test status
Simulation time 396802306926 ps
CPU time 227.9 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:40:03 PM PST 23
Peak memory 191052 kb
Host smart-152ae724-baff-4ff5-a824-ce5f30a82557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470687665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1470687665
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3000447978
Short name T590
Test name
Test status
Simulation time 29183311244 ps
CPU time 267.33 seconds
Started Dec 27 12:35:24 PM PST 23
Finished Dec 27 12:40:06 PM PST 23
Peak memory 191068 kb
Host smart-82c58a8c-db37-4f04-a7db-7e2321161877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000447978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3000447978
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3697698251
Short name T133
Test name
Test status
Simulation time 132072529607 ps
CPU time 415.03 seconds
Started Dec 27 12:35:28 PM PST 23
Finished Dec 27 12:42:37 PM PST 23
Peak memory 191044 kb
Host smart-17ed7629-d7fd-4b5f-9abf-721c84d76076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697698251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3697698251
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4214877833
Short name T330
Test name
Test status
Simulation time 133114395405 ps
CPU time 426.16 seconds
Started Dec 27 12:35:15 PM PST 23
Finished Dec 27 12:42:38 PM PST 23
Peak memory 194136 kb
Host smart-3789a0ca-95d1-4a7f-9f7a-2baadc1a890c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214877833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4214877833
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3859337203
Short name T158
Test name
Test status
Simulation time 450438053914 ps
CPU time 285.19 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:40:38 PM PST 23
Peak memory 191188 kb
Host smart-ced7f5c0-f937-4d8a-9177-951dfaaa9d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859337203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3859337203
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3784648327
Short name T144
Test name
Test status
Simulation time 209717755471 ps
CPU time 582.36 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:46:03 PM PST 23
Peak memory 191188 kb
Host smart-ce2300cc-f5df-4656-9450-dbdbfde16a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784648327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3784648327
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1592962701
Short name T113
Test name
Test status
Simulation time 196287261152 ps
CPU time 106.8 seconds
Started Dec 27 12:35:12 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 190960 kb
Host smart-ed5a7e34-92d1-41b8-ba6d-a96db8ecf169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592962701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1592962701
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.463900631
Short name T181
Test name
Test status
Simulation time 33197231138 ps
CPU time 59.32 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 182964 kb
Host smart-fdffe3af-cc92-4d53-a81c-7907add10769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463900631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.463900631
Directory /workspace/99.rv_timer_random/latest
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