Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 617
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T198 /workspace/coverage/default/42.rv_timer_stress_all.1517445300 Dec 31 12:58:59 PM PST 23 Dec 31 01:03:46 PM PST 23 307021981025 ps
T569 /workspace/coverage/default/8.rv_timer_random_reset.1167727277 Dec 31 12:58:53 PM PST 23 Dec 31 01:08:13 PM PST 23 77753691124 ps
T570 /workspace/coverage/default/6.rv_timer_disabled.52162098 Dec 31 12:58:58 PM PST 23 Dec 31 01:00:15 PM PST 23 178750128345 ps
T571 /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3090627986 Dec 31 12:59:04 PM PST 23 Dec 31 01:01:59 PM PST 23 100109905867 ps
T218 /workspace/coverage/default/110.rv_timer_random.2704143922 Dec 31 12:59:01 PM PST 23 Dec 31 01:03:37 PM PST 23 105700689929 ps
T182 /workspace/coverage/default/141.rv_timer_random.1446618369 Dec 31 12:59:00 PM PST 23 Dec 31 01:01:15 PM PST 23 148197348205 ps
T230 /workspace/coverage/default/14.rv_timer_stress_all.4175026970 Dec 31 12:58:46 PM PST 23 Dec 31 01:26:23 PM PST 23 688214739685 ps
T183 /workspace/coverage/default/48.rv_timer_stress_all.3461263307 Dec 31 12:59:16 PM PST 23 Dec 31 01:09:49 PM PST 23 1289673411045 ps
T572 /workspace/coverage/default/27.rv_timer_random.2026360937 Dec 31 12:58:43 PM PST 23 Dec 31 01:02:16 PM PST 23 833803848640 ps
T573 /workspace/coverage/default/10.rv_timer_disabled.1288648116 Dec 31 12:58:40 PM PST 23 Dec 31 01:01:51 PM PST 23 455573521822 ps
T238 /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3180450892 Dec 31 12:59:14 PM PST 23 Dec 31 01:08:42 PM PST 23 634423310923 ps
T574 /workspace/coverage/default/27.rv_timer_stress_all.1984366904 Dec 31 12:58:41 PM PST 23 Dec 31 01:03:02 PM PST 23 177543714024 ps
T159 /workspace/coverage/default/43.rv_timer_stress_all.450611303 Dec 31 12:59:17 PM PST 23 Dec 31 01:22:35 PM PST 23 822117319234 ps
T301 /workspace/coverage/default/4.rv_timer_stress_all.1335450372 Dec 31 12:58:59 PM PST 23 Dec 31 01:03:14 PM PST 23 805298712667 ps
T240 /workspace/coverage/default/170.rv_timer_random.934187035 Dec 31 12:59:25 PM PST 23 Dec 31 01:02:22 PM PST 23 297812566631 ps
T187 /workspace/coverage/default/112.rv_timer_random.795345505 Dec 31 12:59:17 PM PST 23 Dec 31 01:06:43 PM PST 23 1132496339241 ps
T139 /workspace/coverage/default/2.rv_timer_stress_all.4177173349 Dec 31 12:59:04 PM PST 23 Dec 31 01:24:48 PM PST 23 586374710903 ps
T231 /workspace/coverage/default/161.rv_timer_random.2856252263 Dec 31 12:59:14 PM PST 23 Dec 31 01:02:25 PM PST 23 104470596485 ps
T575 /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3574115409 Dec 31 12:59:09 PM PST 23 Dec 31 01:06:06 PM PST 23 49407864118 ps
T158 /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1732153658 Dec 31 12:59:06 PM PST 23 Dec 31 12:59:54 PM PST 23 35461649370 ps
T255 /workspace/coverage/default/42.rv_timer_random.2534582560 Dec 31 12:59:36 PM PST 23 Dec 31 01:10:48 PM PST 23 388450268308 ps
T576 /workspace/coverage/default/38.rv_timer_disabled.3108828279 Dec 31 12:58:54 PM PST 23 Dec 31 01:00:02 PM PST 23 45450176336 ps
T577 /workspace/coverage/default/27.rv_timer_random_reset.2512805187 Dec 31 12:59:13 PM PST 23 Dec 31 12:59:17 PM PST 23 17773129 ps
T350 /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2400619224 Dec 31 12:59:04 PM PST 23 Dec 31 01:03:34 PM PST 23 165696242143 ps
T287 /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1081584991 Dec 31 12:59:08 PM PST 23 Dec 31 01:01:00 PM PST 23 197774310235 ps
T578 /workspace/coverage/default/3.rv_timer_random.1569232956 Dec 31 12:59:08 PM PST 23 Dec 31 01:00:24 PM PST 23 148321757159 ps
T579 /workspace/coverage/default/118.rv_timer_random.901822845 Dec 31 12:59:14 PM PST 23 Dec 31 01:16:06 PM PST 23 389019728085 ps
T165 /workspace/coverage/default/16.rv_timer_random_reset.473194088 Dec 31 12:58:51 PM PST 23 Dec 31 01:00:58 PM PST 23 69759989185 ps
T168 /workspace/coverage/default/72.rv_timer_random.3358343296 Dec 31 12:58:58 PM PST 23 Dec 31 01:01:56 PM PST 23 109456335443 ps
T355 /workspace/coverage/default/120.rv_timer_random.2290444317 Dec 31 12:59:14 PM PST 23 Dec 31 01:08:37 PM PST 23 71643783709 ps
T328 /workspace/coverage/default/34.rv_timer_random_reset.2251831133 Dec 31 12:58:55 PM PST 23 Dec 31 12:59:52 PM PST 23 100959968527 ps
T580 /workspace/coverage/default/93.rv_timer_random.2855339362 Dec 31 12:59:12 PM PST 23 Dec 31 12:59:32 PM PST 23 31109955996 ps
T271 /workspace/coverage/default/199.rv_timer_random.2408279593 Dec 31 12:59:28 PM PST 23 Dec 31 01:17:51 PM PST 23 347438551173 ps
T219 /workspace/coverage/default/119.rv_timer_random.2166368319 Dec 31 12:59:19 PM PST 23 Dec 31 01:02:02 PM PST 23 86346912904 ps
T316 /workspace/coverage/default/48.rv_timer_random.2481274210 Dec 31 12:59:25 PM PST 23 Dec 31 01:02:42 PM PST 23 264906497434 ps
T581 /workspace/coverage/default/46.rv_timer_disabled.2163782871 Dec 31 12:59:04 PM PST 23 Dec 31 01:00:23 PM PST 23 52343432087 ps
T582 /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3606085302 Dec 31 12:58:46 PM PST 23 Dec 31 01:02:28 PM PST 23 47995567705 ps
T311 /workspace/coverage/default/50.rv_timer_random.2657701234 Dec 31 12:59:14 PM PST 23 Dec 31 01:33:20 PM PST 23 248780064053 ps
T345 /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4163122189 Dec 31 12:58:54 PM PST 23 Dec 31 01:07:57 PM PST 23 344628942437 ps
T583 /workspace/coverage/default/99.rv_timer_random.3545636403 Dec 31 12:58:50 PM PST 23 Dec 31 12:59:18 PM PST 23 42335265023 ps
T584 /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1916853908 Dec 31 12:58:49 PM PST 23 Dec 31 01:04:22 PM PST 23 189642250424 ps
T243 /workspace/coverage/default/21.rv_timer_random.1254777239 Dec 31 12:58:50 PM PST 23 Dec 31 01:04:01 PM PST 23 501706919956 ps
T169 /workspace/coverage/default/150.rv_timer_random.1443187642 Dec 31 12:58:55 PM PST 23 Dec 31 01:07:08 PM PST 23 282582320605 ps
T585 /workspace/coverage/default/32.rv_timer_stress_all.4155703168 Dec 31 12:58:57 PM PST 23 Dec 31 01:10:47 PM PST 23 359704811153 ps
T364 /workspace/coverage/default/101.rv_timer_random.978518718 Dec 31 12:59:22 PM PST 23 Dec 31 01:12:28 PM PST 23 613652606634 ps
T329 /workspace/coverage/default/40.rv_timer_stress_all.3520490425 Dec 31 12:59:22 PM PST 23 Dec 31 01:30:06 PM PST 23 2491489570060 ps
T180 /workspace/coverage/default/0.rv_timer_random.3209062864 Dec 31 12:59:12 PM PST 23 Dec 31 01:01:01 PM PST 23 110256953074 ps
T256 /workspace/coverage/default/6.rv_timer_random.2691668237 Dec 31 12:59:00 PM PST 23 Dec 31 01:01:50 PM PST 23 65478171613 ps
T295 /workspace/coverage/default/83.rv_timer_random.3228919911 Dec 31 12:59:30 PM PST 23 Dec 31 01:08:35 PM PST 23 540962972047 ps
T338 /workspace/coverage/default/20.rv_timer_stress_all.1455682678 Dec 31 12:59:18 PM PST 23 Dec 31 01:03:45 PM PST 23 313645147931 ps
T586 /workspace/coverage/default/33.rv_timer_random.2962997300 Dec 31 12:59:11 PM PST 23 Dec 31 01:01:39 PM PST 23 284598900315 ps
T365 /workspace/coverage/default/149.rv_timer_random.2781204179 Dec 31 12:59:13 PM PST 23 Dec 31 01:00:31 PM PST 23 9142468210 ps
T331 /workspace/coverage/default/24.rv_timer_random.4267260738 Dec 31 12:59:02 PM PST 23 Dec 31 01:01:11 PM PST 23 74582467026 ps
T587 /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2933296194 Dec 31 12:59:07 PM PST 23 Dec 31 01:06:09 PM PST 23 73590391549 ps
T588 /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.4130795047 Dec 31 12:58:52 PM PST 23 Dec 31 01:06:24 PM PST 23 114665292445 ps
T362 /workspace/coverage/default/162.rv_timer_random.1473666810 Dec 31 12:59:31 PM PST 23 Dec 31 01:02:11 PM PST 23 100817706701 ps
T220 /workspace/coverage/default/108.rv_timer_random.219913016 Dec 31 12:59:03 PM PST 23 Dec 31 01:01:03 PM PST 23 67675615375 ps
T589 /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.625591984 Dec 31 12:59:29 PM PST 23 Dec 31 01:07:33 PM PST 23 138315776729 ps
T336 /workspace/coverage/default/29.rv_timer_random_reset.3702449890 Dec 31 12:59:05 PM PST 23 Dec 31 01:00:23 PM PST 23 87577772367 ps
T590 /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1406937669 Dec 31 12:59:17 PM PST 23 Dec 31 01:06:02 PM PST 23 56472406341 ps
T181 /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2285135895 Dec 31 12:59:34 PM PST 23 Dec 31 01:05:09 PM PST 23 350021693119 ps
T232 /workspace/coverage/default/156.rv_timer_random.1609894939 Dec 31 12:59:26 PM PST 23 Dec 31 01:27:53 PM PST 23 221143015461 ps
T166 /workspace/coverage/default/189.rv_timer_random.3439954578 Dec 31 12:58:59 PM PST 23 Dec 31 01:04:25 PM PST 23 196096806477 ps
T591 /workspace/coverage/default/184.rv_timer_random.3648625221 Dec 31 12:59:24 PM PST 23 Dec 31 01:02:30 PM PST 23 187119445449 ps
T592 /workspace/coverage/default/32.rv_timer_random.4250834788 Dec 31 12:58:53 PM PST 23 Dec 31 01:00:07 PM PST 23 54214049329 ps
T593 /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.777133658 Dec 31 12:58:56 PM PST 23 Dec 31 12:59:06 PM PST 23 4026261177 ps
T314 /workspace/coverage/default/169.rv_timer_random.1296763416 Dec 31 12:59:14 PM PST 23 Dec 31 01:01:32 PM PST 23 71273765296 ps
T594 /workspace/coverage/default/47.rv_timer_stress_all.2336158678 Dec 31 12:59:25 PM PST 23 Dec 31 12:59:28 PM PST 23 32924428 ps
T595 /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.706239970 Dec 31 12:59:11 PM PST 23 Dec 31 12:59:31 PM PST 23 13980132512 ps
T151 /workspace/coverage/default/4.rv_timer_random_reset.3068323806 Dec 31 12:59:13 PM PST 23 Dec 31 01:03:02 PM PST 23 472413506654 ps
T162 /workspace/coverage/default/134.rv_timer_random.1509799312 Dec 31 12:59:07 PM PST 23 Dec 31 01:04:23 PM PST 23 116103094095 ps
T261 /workspace/coverage/default/191.rv_timer_random.500048344 Dec 31 12:59:43 PM PST 23 Dec 31 01:01:08 PM PST 23 43954794969 ps
T596 /workspace/coverage/default/16.rv_timer_stress_all.2148606388 Dec 31 12:59:14 PM PST 23 Dec 31 12:59:18 PM PST 23 33763240 ps
T597 /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2806006698 Dec 31 12:58:51 PM PST 23 Dec 31 01:00:19 PM PST 23 35194629823 ps
T598 /workspace/coverage/default/14.rv_timer_random.1616512628 Dec 31 12:58:51 PM PST 23 Dec 31 01:12:05 PM PST 23 602220641881 ps
T131 /workspace/coverage/default/1.rv_timer_stress_all.2945794382 Dec 31 12:59:12 PM PST 23 Dec 31 01:31:49 PM PST 23 2519702724316 ps
T278 /workspace/coverage/default/94.rv_timer_random.448231185 Dec 31 12:59:00 PM PST 23 Dec 31 01:05:01 PM PST 23 112612106271 ps
T599 /workspace/coverage/default/140.rv_timer_random.3268854078 Dec 31 12:59:01 PM PST 23 Dec 31 01:03:04 PM PST 23 471526839675 ps
T360 /workspace/coverage/default/100.rv_timer_random.3355161575 Dec 31 12:59:13 PM PST 23 Dec 31 01:10:47 PM PST 23 355551560916 ps
T200 /workspace/coverage/default/104.rv_timer_random.2113316070 Dec 31 12:59:20 PM PST 23 Dec 31 01:02:11 PM PST 23 103698633758 ps
T600 /workspace/coverage/default/5.rv_timer_disabled.2355667378 Dec 31 12:58:53 PM PST 23 Dec 31 01:01:26 PM PST 23 91135189971 ps
T357 /workspace/coverage/default/11.rv_timer_random.1711099578 Dec 31 12:58:51 PM PST 23 Dec 31 01:03:17 PM PST 23 303310345433 ps
T251 /workspace/coverage/default/44.rv_timer_random.3692934030 Dec 31 12:58:54 PM PST 23 Dec 31 01:01:21 PM PST 23 176309386101 ps
T342 /workspace/coverage/default/186.rv_timer_random.3038967150 Dec 31 12:59:16 PM PST 23 Dec 31 01:00:19 PM PST 23 32407811407 ps
T252 /workspace/coverage/default/31.rv_timer_random.3260393106 Dec 31 12:59:06 PM PST 23 Dec 31 01:12:08 PM PST 23 85452162233 ps
T20 /workspace/coverage/default/3.rv_timer_sec_cm.3751178430 Dec 31 12:58:51 PM PST 23 Dec 31 12:58:57 PM PST 23 75440548 ps
T601 /workspace/coverage/default/37.rv_timer_disabled.1597994538 Dec 31 12:58:56 PM PST 23 Dec 31 01:01:28 PM PST 23 92276089945 ps
T602 /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1812605710 Dec 31 12:58:45 PM PST 23 Dec 31 12:59:12 PM PST 23 10431035077 ps
T603 /workspace/coverage/default/12.rv_timer_random.3859453696 Dec 31 12:59:19 PM PST 23 Dec 31 01:10:02 PM PST 23 100079486502 ps
T346 /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3957951219 Dec 31 12:59:15 PM PST 23 Dec 31 01:01:35 PM PST 23 85452675557 ps
T604 /workspace/coverage/default/23.rv_timer_disabled.2124212362 Dec 31 12:59:07 PM PST 23 Dec 31 01:03:18 PM PST 23 301832200862 ps
T325 /workspace/coverage/default/105.rv_timer_random.2229682591 Dec 31 12:58:53 PM PST 23 Dec 31 01:00:54 PM PST 23 139422516039 ps
T266 /workspace/coverage/default/46.rv_timer_random.2744758819 Dec 31 12:59:06 PM PST 23 Dec 31 01:09:17 PM PST 23 1796314150190 ps
T152 /workspace/coverage/default/129.rv_timer_random.913649976 Dec 31 12:59:30 PM PST 23 Dec 31 01:15:01 PM PST 23 562515565471 ps
T605 /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1915947700 Dec 31 12:59:00 PM PST 23 Dec 31 01:10:36 PM PST 23 92859917129 ps
T606 /workspace/coverage/default/9.rv_timer_random.2275673531 Dec 31 12:58:54 PM PST 23 Dec 31 01:05:03 PM PST 23 155250783185 ps
T607 /workspace/coverage/default/21.rv_timer_stress_all.3032968553 Dec 31 12:59:21 PM PST 23 Dec 31 01:01:28 PM PST 23 80566665442 ps
T318 /workspace/coverage/default/57.rv_timer_random.3804803587 Dec 31 12:58:53 PM PST 23 Dec 31 01:00:54 PM PST 23 169379812352 ps
T608 /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4083260026 Dec 31 12:59:02 PM PST 23 Dec 31 01:07:40 PM PST 23 304707698282 ps
T609 /workspace/coverage/default/16.rv_timer_disabled.487435823 Dec 31 12:58:47 PM PST 23 Dec 31 01:00:19 PM PST 23 53318616470 ps
T221 /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4143208152 Dec 31 12:58:45 PM PST 23 Dec 31 01:11:23 PM PST 23 442987492579 ps
T267 /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3879408566 Dec 31 12:58:53 PM PST 23 Dec 31 01:03:47 PM PST 23 369347890385 ps
T343 /workspace/coverage/default/35.rv_timer_random.303356381 Dec 31 12:58:43 PM PST 23 Dec 31 01:00:28 PM PST 23 45468308372 ps
T310 /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3801380570 Dec 31 12:59:11 PM PST 23 Dec 31 12:59:45 PM PST 23 55012263671 ps
T341 /workspace/coverage/default/47.rv_timer_random.764219333 Dec 31 12:59:37 PM PST 23 Dec 31 01:04:54 PM PST 23 152592018546 ps
T610 /workspace/coverage/default/18.rv_timer_stress_all.1704614692 Dec 31 12:58:53 PM PST 23 Dec 31 01:06:46 PM PST 23 1597296917189 ps
T611 /workspace/coverage/default/13.rv_timer_random_reset.4130864550 Dec 31 12:59:00 PM PST 23 Dec 31 12:59:07 PM PST 23 188627049 ps
T340 /workspace/coverage/default/183.rv_timer_random.1787570429 Dec 31 12:59:04 PM PST 23 Dec 31 01:17:19 PM PST 23 1807997926801 ps
T288 /workspace/coverage/default/194.rv_timer_random.3484098139 Dec 31 12:59:34 PM PST 23 Dec 31 01:01:57 PM PST 23 87910240632 ps
T612 /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3324067773 Dec 31 12:58:48 PM PST 23 Dec 31 01:16:41 PM PST 23 281653794529 ps
T613 /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3024855792 Dec 31 12:58:58 PM PST 23 Dec 31 01:03:53 PM PST 23 30788337728 ps
T326 /workspace/coverage/default/24.rv_timer_stress_all.4012633347 Dec 31 12:58:51 PM PST 23 Dec 31 01:33:17 PM PST 23 4022518834771 ps
T330 /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1528001019 Dec 31 12:58:59 PM PST 23 Dec 31 01:00:40 PM PST 23 176211450994 ps
T614 /workspace/coverage/default/106.rv_timer_random.3224791029 Dec 31 12:59:15 PM PST 23 Dec 31 01:02:08 PM PST 23 150034056443 ps
T615 /workspace/coverage/default/185.rv_timer_random.535040143 Dec 31 12:59:11 PM PST 23 Dec 31 01:00:28 PM PST 23 49706298775 ps
T616 /workspace/coverage/default/37.rv_timer_random_reset.3813729688 Dec 31 12:58:53 PM PST 23 Dec 31 01:00:26 PM PST 23 46137463658 ps
T617 /workspace/coverage/default/21.rv_timer_disabled.1747734312 Dec 31 12:59:11 PM PST 23 Dec 31 12:59:49 PM PST 23 79079447631 ps

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2749250926
Short name T10
Test name
Test status
Simulation time 200656636123 ps
CPU time 730.62 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 211552 kb
Host smart-229958f6-9227-4129-9b00-b0e0f144a8e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749250926 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2749250926
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_random.2083706804
Short name T41
Test name
Test status
Simulation time 158103021309 ps
CPU time 110.82 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:01:06 PM PST 23
Peak memory 191124 kb
Host smart-2da1293b-cd2e-4b98-973f-ec8339504632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083706804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2083706804
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2112083207
Short name T30
Test name
Test status
Simulation time 125792191 ps
CPU time 1.34 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 195548 kb
Host smart-8a34a92f-2253-4822-9fa6-e32ff98e4053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112083207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2112083207
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.301377616
Short name T176
Test name
Test status
Simulation time 640790515296 ps
CPU time 1705.34 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:27:30 PM PST 23
Peak memory 191144 kb
Host smart-db3ca48a-a71c-4748-855c-3b0de5f94f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301377616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
301377616
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2576743127
Short name T93
Test name
Test status
Simulation time 1710445880108 ps
CPU time 1448.96 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:23:21 PM PST 23
Peak memory 191148 kb
Host smart-56ad9034-371f-4942-8348-f609edc68209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576743127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2576743127
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3776681790
Short name T34
Test name
Test status
Simulation time 2252573963999 ps
CPU time 1406.48 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:22:39 PM PST 23
Peak memory 191152 kb
Host smart-c7286378-8f30-40b3-bdf2-4daf9653a6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776681790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3776681790
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2855415386
Short name T102
Test name
Test status
Simulation time 1304148903269 ps
CPU time 2084.48 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 01:33:38 PM PST 23
Peak memory 195652 kb
Host smart-96603d53-48e3-4590-b1ca-da834e10d0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855415386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2855415386
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4177173349
Short name T139
Test name
Test status
Simulation time 586374710903 ps
CPU time 1537.68 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:24:48 PM PST 23
Peak memory 191168 kb
Host smart-6adf70f6-fae6-4727-9462-e1a99e84b7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177173349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4177173349
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3046294506
Short name T134
Test name
Test status
Simulation time 3627806236611 ps
CPU time 1748.48 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:28:12 PM PST 23
Peak memory 190996 kb
Host smart-c52e9a27-1872-4863-b936-9e898c4b30e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046294506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3046294506
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4210788544
Short name T127
Test name
Test status
Simulation time 6911295227886 ps
CPU time 3682.1 seconds
Started Dec 31 12:58:57 PM PST 23
Finished Dec 31 02:00:25 PM PST 23
Peak memory 190996 kb
Host smart-79a60985-eb22-44e1-b593-5eb510c1eeb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210788544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4210788544
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1898512545
Short name T55
Test name
Test status
Simulation time 1058169002783 ps
CPU time 565.86 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 191172 kb
Host smart-2303cbd0-49c4-4675-b1b2-5f7c39092f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898512545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1898512545
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1852508262
Short name T49
Test name
Test status
Simulation time 33185150 ps
CPU time 0.71 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 192512 kb
Host smart-6a841851-8032-428e-9f1d-3e4cad6bae8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852508262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1852508262
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_timer_random.769841943
Short name T1
Test name
Test status
Simulation time 221811700365 ps
CPU time 140.1 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:01:27 PM PST 23
Peak memory 191096 kb
Host smart-dc59fc65-11bd-46b9-8023-d5be25ba75bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769841943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.769841943
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2567376180
Short name T186
Test name
Test status
Simulation time 1475947150625 ps
CPU time 4998.3 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 02:22:25 PM PST 23
Peak memory 191132 kb
Host smart-b29b526d-b515-4a11-9539-e3b07784bfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567376180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2567376180
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2945794382
Short name T131
Test name
Test status
Simulation time 2519702724316 ps
CPU time 1952.65 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:31:49 PM PST 23
Peak memory 191144 kb
Host smart-32cebb4d-5814-4c4f-b45e-d43d78b18c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945794382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2945794382
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1217479426
Short name T17
Test name
Test status
Simulation time 185808178 ps
CPU time 0.79 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 12:59:19 PM PST 23
Peak memory 212860 kb
Host smart-ff8637c4-5b35-4ca2-a70b-317578843b4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217479426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1217479426
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3270137138
Short name T146
Test name
Test status
Simulation time 1365273349548 ps
CPU time 3657.37 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:59:57 PM PST 23
Peak memory 190404 kb
Host smart-04b63221-eba0-4c92-9ca4-3a9ce94eda8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270137138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3270137138
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.3167408465
Short name T106
Test name
Test status
Simulation time 197850204568 ps
CPU time 2737.8 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:44:37 PM PST 23
Peak memory 193236 kb
Host smart-f346ec40-f2c9-4c28-aeaa-baa5c66bf8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167408465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3167408465
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.782570180
Short name T185
Test name
Test status
Simulation time 961344130521 ps
CPU time 1828.91 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:29:41 PM PST 23
Peak memory 191052 kb
Host smart-d8f25dd7-ee07-42c3-afbd-30f71ca1bc45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782570180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
782570180
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_random.1145832567
Short name T174
Test name
Test status
Simulation time 897220748987 ps
CPU time 339.07 seconds
Started Dec 31 12:59:38 PM PST 23
Finished Dec 31 01:05:19 PM PST 23
Peak memory 193800 kb
Host smart-5b8ba33b-fa3b-4696-8aec-5021e41da4ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145832567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1145832567
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2179364187
Short name T111
Test name
Test status
Simulation time 119085357175 ps
CPU time 239.56 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:03:16 PM PST 23
Peak memory 194432 kb
Host smart-9286ac8b-c966-4fc0-9e58-1273e7482ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179364187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2179364187
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4012633347
Short name T326
Test name
Test status
Simulation time 4022518834771 ps
CPU time 2059.92 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:33:17 PM PST 23
Peak memory 191236 kb
Host smart-85e5fea0-f43d-415d-aec9-1814d62e03f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012633347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4012633347
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2740579407
Short name T95
Test name
Test status
Simulation time 473784473155 ps
CPU time 498.74 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:07:24 PM PST 23
Peak memory 183088 kb
Host smart-a55a95a5-2bfa-4673-88dd-7e1323bba037
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740579407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2740579407
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/146.rv_timer_random.4027210550
Short name T171
Test name
Test status
Simulation time 495571092930 ps
CPU time 354.59 seconds
Started Dec 31 12:59:41 PM PST 23
Finished Dec 31 01:05:39 PM PST 23
Peak memory 191020 kb
Host smart-c0037bef-aa34-435a-84eb-f181ca8d314d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027210550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4027210550
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3520490425
Short name T329
Test name
Test status
Simulation time 2491489570060 ps
CPU time 1840.41 seconds
Started Dec 31 12:59:22 PM PST 23
Finished Dec 31 01:30:06 PM PST 23
Peak memory 191124 kb
Host smart-35b80ba8-2081-4ab1-844c-89d9c22fa189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520490425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3520490425
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3461263307
Short name T183
Test name
Test status
Simulation time 1289673411045 ps
CPU time 627.97 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:09:49 PM PST 23
Peak memory 191064 kb
Host smart-9782bbb1-538c-4938-b896-636734e9369e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461263307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3461263307
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.1171857337
Short name T269
Test name
Test status
Simulation time 301696002370 ps
CPU time 407.65 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:05:53 PM PST 23
Peak memory 194672 kb
Host smart-b1d5c981-25f1-43d2-a6c7-a5966a3c3ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171857337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1171857337
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.448231185
Short name T278
Test name
Test status
Simulation time 112612106271 ps
CPU time 353.82 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:05:01 PM PST 23
Peak memory 191156 kb
Host smart-59801b15-57f1-40e6-a4b2-716d26f9ce52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448231185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.448231185
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1050443734
Short name T302
Test name
Test status
Simulation time 292268716384 ps
CPU time 978.78 seconds
Started Dec 31 12:59:24 PM PST 23
Finished Dec 31 01:15:46 PM PST 23
Peak memory 191208 kb
Host smart-446a1cb7-b2a5-45ef-8d7a-db1cb86a519f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050443734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1050443734
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.586137737
Short name T156
Test name
Test status
Simulation time 344938052506 ps
CPU time 513.33 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:07:38 PM PST 23
Peak memory 191152 kb
Host smart-11dbe070-ee6a-4782-a780-b9a5574d107a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586137737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.586137737
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.1526002752
Short name T92
Test name
Test status
Simulation time 139174556688 ps
CPU time 275.38 seconds
Started Dec 31 12:58:57 PM PST 23
Finished Dec 31 01:03:38 PM PST 23
Peak memory 182916 kb
Host smart-a4b66806-4867-40b8-b151-cbffb6bd2001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526002752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1526002752
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random.764219333
Short name T341
Test name
Test status
Simulation time 152592018546 ps
CPU time 315.74 seconds
Started Dec 31 12:59:37 PM PST 23
Finished Dec 31 01:04:54 PM PST 23
Peak memory 193420 kb
Host smart-c4c0bfe8-cb7c-4244-a3a9-2eddb4a34ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764219333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.764219333
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2130928609
Short name T23
Test name
Test status
Simulation time 261391539208 ps
CPU time 128.11 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:01:13 PM PST 23
Peak memory 191192 kb
Host smart-068dd3d8-2b22-471f-bd18-cbf2c3576f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130928609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2130928609
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1818909574
Short name T155
Test name
Test status
Simulation time 139094174889 ps
CPU time 2504.47 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:41:12 PM PST 23
Peak memory 191144 kb
Host smart-89271fbd-32db-4a41-a65b-3f843f255b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818909574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1818909574
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3314516922
Short name T191
Test name
Test status
Simulation time 127481819181 ps
CPU time 238.06 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:03:16 PM PST 23
Peak memory 194112 kb
Host smart-7e6369a4-6a88-406c-8d5f-72c593685d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314516922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3314516922
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3063815717
Short name T296
Test name
Test status
Simulation time 768562030632 ps
CPU time 452.78 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:06:47 PM PST 23
Peak memory 191104 kb
Host smart-4766df30-acbd-4cdc-97dd-8883b9867f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063815717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3063815717
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1296763416
Short name T314
Test name
Test status
Simulation time 71273765296 ps
CPU time 133.99 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:01:32 PM PST 23
Peak memory 192528 kb
Host smart-b9f37314-6ce5-4ee6-a50b-2512085a7804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296763416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1296763416
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3974868536
Short name T135
Test name
Test status
Simulation time 133446285593 ps
CPU time 590.31 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:08:51 PM PST 23
Peak memory 191192 kb
Host smart-028f6153-e49e-466e-9ac5-5d7f0c8e4e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974868536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3974868536
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3439954578
Short name T166
Test name
Test status
Simulation time 196096806477 ps
CPU time 320.44 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:04:25 PM PST 23
Peak memory 191160 kb
Host smart-aa1b3290-e970-4a90-be42-9cac8dae3600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439954578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3439954578
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.93980552
Short name T257
Test name
Test status
Simulation time 518245440795 ps
CPU time 1950.9 seconds
Started Dec 31 12:59:41 PM PST 23
Finished Dec 31 01:32:16 PM PST 23
Peak memory 191056 kb
Host smart-fb3c46a6-d897-41b2-a0f7-d63b6182aced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93980552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.93980552
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2166368319
Short name T219
Test name
Test status
Simulation time 86346912904 ps
CPU time 159.42 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:02:02 PM PST 23
Peak memory 191116 kb
Host smart-afebd630-67f5-4cc6-b5b1-4c78cf59df83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166368319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2166368319
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3715083349
Short name T254
Test name
Test status
Simulation time 922894965366 ps
CPU time 1421.14 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:22:55 PM PST 23
Peak memory 191056 kb
Host smart-2589a32d-4a33-4513-8ecc-dac378697fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715083349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3715083349
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4175026970
Short name T230
Test name
Test status
Simulation time 688214739685 ps
CPU time 1650.01 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 01:26:23 PM PST 23
Peak memory 191148 kb
Host smart-fd5b58b9-aa44-4546-a50a-fab2eca4e6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175026970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4175026970
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3101386072
Short name T289
Test name
Test status
Simulation time 19476051433 ps
CPU time 33.5 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 12:59:45 PM PST 23
Peak memory 182952 kb
Host smart-81dc2748-2a9d-4b15-9dc5-3e87801e8dd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101386072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3101386072
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.378956371
Short name T196
Test name
Test status
Simulation time 62512170754 ps
CPU time 647.65 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:10:00 PM PST 23
Peak memory 205908 kb
Host smart-e278de9b-97ee-4ca8-aed9-05f50f2ad09a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378956371 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.378956371
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1425447753
Short name T94
Test name
Test status
Simulation time 242789118339 ps
CPU time 768.07 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:12:07 PM PST 23
Peak memory 193340 kb
Host smart-5f3db4f7-2a23-40ca-bf0f-a8d02102e602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425447753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1425447753
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2555084882
Short name T237
Test name
Test status
Simulation time 211143580736 ps
CPU time 324.95 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:04:52 PM PST 23
Peak memory 182852 kb
Host smart-3d62c211-92c2-4e1d-a60f-af781bd05a8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555084882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2555084882
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/109.rv_timer_random.3712617470
Short name T104
Test name
Test status
Simulation time 201959672867 ps
CPU time 271.01 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:03:48 PM PST 23
Peak memory 191184 kb
Host smart-82b2cec6-ca14-4300-b1a0-4a8e2bc3e405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712617470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3712617470
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1918045141
Short name T129
Test name
Test status
Simulation time 371719457793 ps
CPU time 583.94 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:08:59 PM PST 23
Peak memory 194544 kb
Host smart-dffd7f84-878b-4ba0-8fa4-c6c5d5a0d3b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918045141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1918045141
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1882843168
Short name T249
Test name
Test status
Simulation time 159605863848 ps
CPU time 467.47 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:07:02 PM PST 23
Peak memory 193792 kb
Host smart-74f6397f-3bcf-48fb-9559-4eb9eeb4ca8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882843168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1882843168
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.98734327
Short name T211
Test name
Test status
Simulation time 165858862569 ps
CPU time 288.22 seconds
Started Dec 31 12:59:37 PM PST 23
Finished Dec 31 01:04:26 PM PST 23
Peak memory 193572 kb
Host smart-3374f66d-0c2f-4699-b54d-8accb83c65b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98734327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.98734327
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1609894939
Short name T232
Test name
Test status
Simulation time 221143015461 ps
CPU time 1704.91 seconds
Started Dec 31 12:59:26 PM PST 23
Finished Dec 31 01:27:53 PM PST 23
Peak memory 191036 kb
Host smart-623ada1f-e6e3-40bd-aa81-43a09c170d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609894939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1609894939
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2281731221
Short name T216
Test name
Test status
Simulation time 124800500200 ps
CPU time 259.39 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:03:46 PM PST 23
Peak memory 191316 kb
Host smart-ae0ee44a-e5a6-43be-bb98-2254f8ecc880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281731221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2281731221
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1787570429
Short name T340
Test name
Test status
Simulation time 1807997926801 ps
CPU time 1088.75 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:17:19 PM PST 23
Peak memory 191208 kb
Host smart-0a7d1b93-2420-4234-9352-58fe70275f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787570429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1787570429
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3520796877
Short name T132
Test name
Test status
Simulation time 865772770220 ps
CPU time 1177.57 seconds
Started Dec 31 12:59:28 PM PST 23
Finished Dec 31 01:19:07 PM PST 23
Peak memory 191128 kb
Host smart-c23ed589-dfa8-4520-a13c-81eea5045f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520796877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3520796877
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3595937736
Short name T116
Test name
Test status
Simulation time 345842951160 ps
CPU time 303.43 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:04:04 PM PST 23
Peak memory 191116 kb
Host smart-9ee1f29f-e658-414c-9172-4a1597016d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595937736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3595937736
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random.2534582560
Short name T255
Test name
Test status
Simulation time 388450268308 ps
CPU time 669.93 seconds
Started Dec 31 12:59:36 PM PST 23
Finished Dec 31 01:10:48 PM PST 23
Peak memory 191400 kb
Host smart-1f70805f-e14c-42c8-a5a7-59357a12ba76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534582560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2534582560
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1517445300
Short name T198
Test name
Test status
Simulation time 307021981025 ps
CPU time 281.01 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:03:46 PM PST 23
Peak memory 191064 kb
Host smart-5520f0be-ad36-4bd8-86b9-95fead7c5fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517445300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1517445300
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.3804803587
Short name T318
Test name
Test status
Simulation time 169379812352 ps
CPU time 114.84 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:00:54 PM PST 23
Peak memory 191040 kb
Host smart-bac72e16-8532-43ac-b831-90226487be12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804803587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3804803587
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3872827534
Short name T128
Test name
Test status
Simulation time 1180462940007 ps
CPU time 510.62 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 01:07:26 PM PST 23
Peak memory 182932 kb
Host smart-ff6e1815-909e-4ab5-94c8-68b37281ec94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872827534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3872827534
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4253642259
Short name T83
Test name
Test status
Simulation time 130971892 ps
CPU time 0.73 seconds
Started Dec 31 12:46:59 PM PST 23
Finished Dec 31 12:47:01 PM PST 23
Peak memory 192232 kb
Host smart-e3cc2ec6-559a-4717-964c-39dea63d49e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253642259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4253642259
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rv_timer_random.3312048280
Short name T210
Test name
Test status
Simulation time 127365427977 ps
CPU time 333.14 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 01:04:27 PM PST 23
Peak memory 191204 kb
Host smart-19dbfed1-b852-4919-8c0e-85ca1a1ad1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312048280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3312048280
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1509799312
Short name T162
Test name
Test status
Simulation time 116103094095 ps
CPU time 310.61 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:04:23 PM PST 23
Peak memory 193676 kb
Host smart-ee31cf57-589a-41f0-8620-f47a943bdbe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509799312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1509799312
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2052463809
Short name T227
Test name
Test status
Simulation time 186428615853 ps
CPU time 732.63 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:11:29 PM PST 23
Peak memory 191136 kb
Host smart-1abcdb47-25bd-438e-868a-9a17c7f639b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052463809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2052463809
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3781298045
Short name T222
Test name
Test status
Simulation time 135187294559 ps
CPU time 204 seconds
Started Dec 31 12:59:21 PM PST 23
Finished Dec 31 01:02:48 PM PST 23
Peak memory 194200 kb
Host smart-aac731d5-cd57-4013-b69f-71815e96f24c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781298045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3781298045
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1443187642
Short name T169
Test name
Test status
Simulation time 282582320605 ps
CPU time 486.29 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:07:08 PM PST 23
Peak memory 191184 kb
Host smart-aa5a1b61-a26e-464a-a800-575cd1a7e7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443187642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1443187642
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3879408566
Short name T267
Test name
Test status
Simulation time 369347890385 ps
CPU time 287.74 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:03:47 PM PST 23
Peak memory 182936 kb
Host smart-10b27d94-2e07-47e7-8304-9ad87d609c69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879408566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3879408566
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/182.rv_timer_random.1659676276
Short name T28
Test name
Test status
Simulation time 559155421446 ps
CPU time 510.29 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 191196 kb
Host smart-eed754ce-240f-4c22-9aad-01d1d75c9115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659676276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1659676276
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2003197725
Short name T147
Test name
Test status
Simulation time 2542544974377 ps
CPU time 1131.55 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:18:07 PM PST 23
Peak memory 191096 kb
Host smart-d53fca74-393a-4863-af95-81a697942d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003197725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2003197725
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.500048344
Short name T261
Test name
Test status
Simulation time 43954794969 ps
CPU time 81.09 seconds
Started Dec 31 12:59:43 PM PST 23
Finished Dec 31 01:01:08 PM PST 23
Peak memory 191160 kb
Host smart-ff9d7cad-6303-4adb-ab53-a12b514ffb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500048344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.500048344
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2616153983
Short name T177
Test name
Test status
Simulation time 241549132399 ps
CPU time 372.86 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:05:28 PM PST 23
Peak memory 182928 kb
Host smart-e3eb590a-e7a3-40df-a4a4-796266b79553
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616153983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2616153983
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/78.rv_timer_random.3910939432
Short name T150
Test name
Test status
Simulation time 239813720534 ps
CPU time 135.63 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 01:01:27 PM PST 23
Peak memory 191104 kb
Host smart-ab8a7846-b9ad-4756-aeef-4549969dcbc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910939432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3910939432
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.202986992
Short name T264
Test name
Test status
Simulation time 126391772493 ps
CPU time 329.34 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:04:30 PM PST 23
Peak memory 191364 kb
Host smart-86a588b8-2115-4bfe-ae8f-a42d195b0ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202986992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.202986992
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2935802616
Short name T203
Test name
Test status
Simulation time 297088331258 ps
CPU time 420.21 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 01:06:14 PM PST 23
Peak memory 191136 kb
Host smart-7888c9ba-e48e-47fd-a396-6ba526963944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935802616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2935802616
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2613997632
Short name T115
Test name
Test status
Simulation time 72534794521 ps
CPU time 92.87 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:00:52 PM PST 23
Peak memory 191184 kb
Host smart-33d5953d-5b1c-41de-bfe4-b9df61204868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613997632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2613997632
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1132640191
Short name T43
Test name
Test status
Simulation time 1554504571043 ps
CPU time 891.17 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 182960 kb
Host smart-4d59e0ec-fa1d-4690-a938-7d24a63fd923
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132640191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1132640191
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.716882769
Short name T108
Test name
Test status
Simulation time 2274532603017 ps
CPU time 998.89 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 01:15:50 PM PST 23
Peak memory 182892 kb
Host smart-04046706-0bbb-46ed-bac7-bd93f19aa18f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716882769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.716882769
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.325166502
Short name T294
Test name
Test status
Simulation time 29152641322 ps
CPU time 84.57 seconds
Started Dec 31 12:59:21 PM PST 23
Finished Dec 31 01:00:58 PM PST 23
Peak memory 182920 kb
Host smart-dd228b30-f433-40cc-b87b-70bb53c30bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325166502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.325166502
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.2856252263
Short name T231
Test name
Test status
Simulation time 104470596485 ps
CPU time 186.7 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:02:25 PM PST 23
Peak memory 191172 kb
Host smart-d8876ac7-ddca-48a7-8835-fabdac565d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856252263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2856252263
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3682850322
Short name T170
Test name
Test status
Simulation time 197933475278 ps
CPU time 1802.54 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:29:22 PM PST 23
Peak memory 191148 kb
Host smart-4262587b-cac3-4d20-9daf-42a4ed0e7f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682850322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3682850322
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4184826949
Short name T224
Test name
Test status
Simulation time 914808655543 ps
CPU time 2755.54 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:44:59 PM PST 23
Peak memory 191116 kb
Host smart-956118c2-c3fc-4335-8457-7b88a48b7863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184826949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4184826949
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.535040143
Short name T615
Test name
Test status
Simulation time 49706298775 ps
CPU time 72.62 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:00:28 PM PST 23
Peak memory 191148 kb
Host smart-28fd9d34-688f-4312-b252-353f469171aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535040143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.535040143
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1260051198
Short name T179
Test name
Test status
Simulation time 1124921643539 ps
CPU time 1175.02 seconds
Started Dec 31 12:59:24 PM PST 23
Finished Dec 31 01:19:01 PM PST 23
Peak memory 191160 kb
Host smart-425bfae4-c31a-4775-bdf8-eb179ad7ea7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260051198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1260051198
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3801380570
Short name T310
Test name
Test status
Simulation time 55012263671 ps
CPU time 29.53 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 12:59:45 PM PST 23
Peak memory 182924 kb
Host smart-337a8678-e689-40c5-aac4-7883a3cd0002
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801380570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3801380570
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1455682678
Short name T338
Test name
Test status
Simulation time 313645147931 ps
CPU time 262.66 seconds
Started Dec 31 12:59:18 PM PST 23
Finished Dec 31 01:03:45 PM PST 23
Peak memory 183024 kb
Host smart-ae80606c-1260-4651-83f4-1f29c5042c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455682678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1455682678
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random.1254777239
Short name T243
Test name
Test status
Simulation time 501706919956 ps
CPU time 304.74 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 01:04:01 PM PST 23
Peak memory 191316 kb
Host smart-8f55fb7e-9195-4981-b05a-1e7a86d927cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254777239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1254777239
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3747811658
Short name T105
Test name
Test status
Simulation time 659517376353 ps
CPU time 1181.57 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:18:49 PM PST 23
Peak memory 182948 kb
Host smart-2eadfb83-02a0-4c5a-93fc-d0c866b23e69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747811658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3747811658
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3223606943
Short name T291
Test name
Test status
Simulation time 80934342540 ps
CPU time 737.57 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:11:28 PM PST 23
Peak memory 205864 kb
Host smart-a149ce3b-9e6e-4664-b380-ac2000c46ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223606943 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3223606943
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2117823532
Short name T260
Test name
Test status
Simulation time 207813539792 ps
CPU time 210.82 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:02:52 PM PST 23
Peak memory 182864 kb
Host smart-199a190b-42f0-4ecd-b9ca-18d95dbd4d02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117823532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2117823532
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3957951219
Short name T346
Test name
Test status
Simulation time 85452675557 ps
CPU time 135.31 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:01:35 PM PST 23
Peak memory 182952 kb
Host smart-c22462b5-6371-4689-9aff-04f0e6c527cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957951219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3957951219
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2285135895
Short name T181
Test name
Test status
Simulation time 350021693119 ps
CPU time 333.1 seconds
Started Dec 31 12:59:34 PM PST 23
Finished Dec 31 01:05:09 PM PST 23
Peak memory 182852 kb
Host smart-e13fe2be-42cf-455a-a1cd-cfcc977462f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285135895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2285135895
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.514132046
Short name T272
Test name
Test status
Simulation time 123797414766 ps
CPU time 414.66 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:06:10 PM PST 23
Peak memory 194700 kb
Host smart-f18f05c7-d80d-4ab3-b60e-68e735cc928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514132046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.514132046
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1335450372
Short name T301
Test name
Test status
Simulation time 805298712667 ps
CPU time 248.95 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:03:14 PM PST 23
Peak memory 191184 kb
Host smart-f4e23c84-f33c-4898-b7dc-b8acf9af9af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335450372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1335450372
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.450611303
Short name T159
Test name
Test status
Simulation time 822117319234 ps
CPU time 1393.53 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:22:35 PM PST 23
Peak memory 191160 kb
Host smart-e53e4205-fc6d-4b57-8c01-c3ac2ccdab07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450611303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
450611303
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2520448462
Short name T199
Test name
Test status
Simulation time 726383058966 ps
CPU time 296.96 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:04:21 PM PST 23
Peak memory 182912 kb
Host smart-b0731faf-6543-4f8b-863e-71f16fccf1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520448462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2520448462
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4143208152
Short name T221
Test name
Test status
Simulation time 442987492579 ps
CPU time 750.86 seconds
Started Dec 31 12:58:45 PM PST 23
Finished Dec 31 01:11:23 PM PST 23
Peak memory 182868 kb
Host smart-ed1bddc8-cc36-4031-a322-258ab0fce710
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143208152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4143208152
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/79.rv_timer_random.2534348522
Short name T120
Test name
Test status
Simulation time 116100307963 ps
CPU time 346.4 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:05:06 PM PST 23
Peak memory 193752 kb
Host smart-a56d12f6-c31b-4ed2-b0b3-eac23322879b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534348522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2534348522
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.263266174
Short name T443
Test name
Test status
Simulation time 31868211 ps
CPU time 0.71 seconds
Started Dec 31 12:47:22 PM PST 23
Finished Dec 31 12:47:24 PM PST 23
Peak memory 183184 kb
Host smart-69283d4c-ac75-4cb7-96e6-52f8b95a5339
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263266174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.263266174
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.308386274
Short name T439
Test name
Test status
Simulation time 628330187 ps
CPU time 1.55 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 191628 kb
Host smart-f107aed4-0690-489e-8f84-54d2bca99a5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308386274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.308386274
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2231146970
Short name T391
Test name
Test status
Simulation time 53616778 ps
CPU time 0.52 seconds
Started Dec 31 12:47:10 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 183284 kb
Host smart-7eba2c71-c09f-48a8-b430-2cd703f44407
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231146970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2231146970
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2730105506
Short name T46
Test name
Test status
Simulation time 129535664 ps
CPU time 0.61 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 194192 kb
Host smart-ee880aa8-a536-43b5-92b0-96922a883e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730105506 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2730105506
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4031498444
Short name T412
Test name
Test status
Simulation time 11227412 ps
CPU time 0.54 seconds
Started Dec 31 12:47:10 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 182760 kb
Host smart-13c8521e-526c-4142-a3a5-2db6f97a85d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031498444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4031498444
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2969308587
Short name T438
Test name
Test status
Simulation time 32212809 ps
CPU time 0.54 seconds
Started Dec 31 12:47:05 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 182776 kb
Host smart-3507384b-5b61-429c-859e-22010812acdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969308587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2969308587
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.750350924
Short name T430
Test name
Test status
Simulation time 91078049 ps
CPU time 1.6 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:44 PM PST 23
Peak memory 198068 kb
Host smart-dda0e9aa-a0be-474c-a1bb-ebc444adac2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750350924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.750350924
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2187910721
Short name T448
Test name
Test status
Simulation time 127674665 ps
CPU time 0.82 seconds
Started Dec 31 12:46:51 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 183304 kb
Host smart-0bdd8e8c-9421-4d7d-b8c3-366b70b09a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187910721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2187910721
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1920416974
Short name T75
Test name
Test status
Simulation time 46496492 ps
CPU time 0.59 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:29 PM PST 23
Peak memory 183100 kb
Host smart-e233a554-9ea2-4e9d-9103-c6df31b9caab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920416974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1920416974
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1784138139
Short name T453
Test name
Test status
Simulation time 583358911 ps
CPU time 3.83 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:16 PM PST 23
Peak memory 192940 kb
Host smart-9f5daa14-8ce0-4d60-9619-55242ef7ceb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784138139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1784138139
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2701403160
Short name T15
Test name
Test status
Simulation time 14181062 ps
CPU time 0.54 seconds
Started Dec 31 12:46:45 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 183196 kb
Host smart-2efdd47b-1350-4cd4-96f2-188f7ff39a48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701403160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2701403160
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.67649115
Short name T464
Test name
Test status
Simulation time 33195811 ps
CPU time 0.89 seconds
Started Dec 31 12:47:09 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 196856 kb
Host smart-20e849d2-ce2e-44eb-beb7-19a05f796858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67649115 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.67649115
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.629646011
Short name T421
Test name
Test status
Simulation time 53315192 ps
CPU time 0.56 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 183240 kb
Host smart-38fc74f7-b057-44d9-8a9a-5714526ce98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629646011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.629646011
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3767860568
Short name T477
Test name
Test status
Simulation time 10799119 ps
CPU time 0.53 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:20 PM PST 23
Peak memory 182032 kb
Host smart-b500b5d1-f74a-4eb7-96b0-215287896201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767860568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3767860568
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1221013733
Short name T13
Test name
Test status
Simulation time 93841257 ps
CPU time 0.68 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 192416 kb
Host smart-91c8b012-b0ad-4d04-aae1-83a37f3030bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221013733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1221013733
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4258769064
Short name T398
Test name
Test status
Simulation time 60494246 ps
CPU time 1.25 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 197948 kb
Host smart-a34c1aeb-30a1-4f7b-90e5-c0f86157d458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258769064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4258769064
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4232389267
Short name T59
Test name
Test status
Simulation time 331481999 ps
CPU time 1.1 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 195420 kb
Host smart-7212f206-d86d-449c-a3ab-eef54a4cc1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232389267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4232389267
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1160540675
Short name T416
Test name
Test status
Simulation time 24253831 ps
CPU time 0.74 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 195340 kb
Host smart-870a79ef-d1e8-4d0f-a024-a34aba8d7d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160540675 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1160540675
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2691948019
Short name T434
Test name
Test status
Simulation time 15015735 ps
CPU time 0.54 seconds
Started Dec 31 12:47:41 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 183132 kb
Host smart-ac2ddb22-a462-4ffd-8906-697614abade5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691948019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2691948019
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1664546749
Short name T381
Test name
Test status
Simulation time 91893851 ps
CPU time 0.57 seconds
Started Dec 31 12:47:27 PM PST 23
Finished Dec 31 12:47:33 PM PST 23
Peak memory 182436 kb
Host smart-abc747f5-3c49-489b-ade2-880500c188e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664546749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1664546749
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4126698188
Short name T447
Test name
Test status
Simulation time 35707276 ps
CPU time 0.81 seconds
Started Dec 31 12:47:12 PM PST 23
Finished Dec 31 12:47:15 PM PST 23
Peak memory 193860 kb
Host smart-26950ee3-ccb3-446f-8b49-432ffbdfe77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126698188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4126698188
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3714834194
Short name T467
Test name
Test status
Simulation time 108834685 ps
CPU time 2.22 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 197992 kb
Host smart-343b7633-5eab-4025-8359-f5c4778fd557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714834194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3714834194
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1607204824
Short name T69
Test name
Test status
Simulation time 77158130 ps
CPU time 0.79 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 183368 kb
Host smart-06ca779d-954c-4e8a-9b3d-709dc0b51847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607204824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1607204824
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2537288681
Short name T491
Test name
Test status
Simulation time 40050423 ps
CPU time 0.9 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 197864 kb
Host smart-e59c6ff4-2550-4eaa-b585-57caf0602583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537288681 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2537288681
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.966757798
Short name T67
Test name
Test status
Simulation time 13033753 ps
CPU time 0.54 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 182596 kb
Host smart-6ca35504-f4ec-4f10-90a8-4930c2dd36e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966757798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.966757798
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1465955028
Short name T377
Test name
Test status
Simulation time 16025858 ps
CPU time 0.6 seconds
Started Dec 31 12:47:12 PM PST 23
Finished Dec 31 12:47:15 PM PST 23
Peak memory 182816 kb
Host smart-1c0863b9-85b7-4b76-b24e-a0db4570b6cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465955028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1465955028
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3522328733
Short name T484
Test name
Test status
Simulation time 127598562 ps
CPU time 0.8 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 193832 kb
Host smart-a1b0889d-76ea-446b-8646-145b9159a375
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522328733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3522328733
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.661638472
Short name T378
Test name
Test status
Simulation time 209654363 ps
CPU time 2.65 seconds
Started Dec 31 12:47:05 PM PST 23
Finished Dec 31 12:47:11 PM PST 23
Peak memory 197956 kb
Host smart-46a4673b-4e52-4184-b6d5-a86fd66a8b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661638472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.661638472
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2681720833
Short name T86
Test name
Test status
Simulation time 125199537 ps
CPU time 1.36 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 195684 kb
Host smart-2a2b54f1-b2d8-45c4-834b-120339b88e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681720833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2681720833
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1558107021
Short name T60
Test name
Test status
Simulation time 83779540 ps
CPU time 1.13 seconds
Started Dec 31 12:47:26 PM PST 23
Finished Dec 31 12:47:30 PM PST 23
Peak memory 198044 kb
Host smart-382ef9f3-4736-4c39-816d-e45fa86c7f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558107021 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1558107021
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1330039484
Short name T68
Test name
Test status
Simulation time 11563138 ps
CPU time 0.55 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 183124 kb
Host smart-1f2fc715-3a8b-4375-b201-f552bfe63cc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330039484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1330039484
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.838986772
Short name T370
Test name
Test status
Simulation time 12782629 ps
CPU time 0.52 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:21 PM PST 23
Peak memory 182492 kb
Host smart-612f31aa-9d7d-4766-aa75-143e9df1ea80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838986772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.838986772
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4114649933
Short name T475
Test name
Test status
Simulation time 70971711 ps
CPU time 0.72 seconds
Started Dec 31 12:47:09 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 192124 kb
Host smart-54183357-2b98-4ec8-9002-20d345300e87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114649933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4114649933
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1239732922
Short name T483
Test name
Test status
Simulation time 43906568 ps
CPU time 2.15 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 197928 kb
Host smart-5f8120ce-eaac-41a8-8c5b-9132de1941e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239732922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1239732922
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1846886995
Short name T440
Test name
Test status
Simulation time 98840784 ps
CPU time 0.85 seconds
Started Dec 31 12:47:12 PM PST 23
Finished Dec 31 12:47:15 PM PST 23
Peak memory 197052 kb
Host smart-b4a99f50-4b3d-480e-a066-91cff320bb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846886995 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1846886995
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1169958931
Short name T481
Test name
Test status
Simulation time 20980391 ps
CPU time 0.57 seconds
Started Dec 31 12:47:13 PM PST 23
Finished Dec 31 12:47:16 PM PST 23
Peak memory 183196 kb
Host smart-ce3b9c81-e6bd-4260-a773-efd8d3d8895d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169958931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1169958931
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4016441810
Short name T469
Test name
Test status
Simulation time 22291941 ps
CPU time 0.55 seconds
Started Dec 31 12:47:10 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 182028 kb
Host smart-bdad0209-2523-47bc-bc16-7c6deb22a9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016441810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4016441810
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3662497531
Short name T80
Test name
Test status
Simulation time 38876337 ps
CPU time 0.87 seconds
Started Dec 31 12:47:18 PM PST 23
Finished Dec 31 12:47:20 PM PST 23
Peak memory 194908 kb
Host smart-8dc47811-d4a7-46e5-8c41-b5be1deef696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662497531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3662497531
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.768565698
Short name T48
Test name
Test status
Simulation time 195306064 ps
CPU time 1.86 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:24 PM PST 23
Peak memory 197948 kb
Host smart-0b5a6167-7298-483e-b0bf-d54c9b15c32a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768565698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.768565698
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.133391262
Short name T414
Test name
Test status
Simulation time 414897324 ps
CPU time 1.33 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 195596 kb
Host smart-f7ae9f9f-fae0-4776-a30f-7c0136bb4849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133391262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.133391262
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1008667451
Short name T474
Test name
Test status
Simulation time 33886158 ps
CPU time 1.75 seconds
Started Dec 31 12:47:03 PM PST 23
Finished Dec 31 12:47:10 PM PST 23
Peak memory 198064 kb
Host smart-769e7b52-3cc0-4b22-8420-27f9c3cc68aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008667451 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1008667451
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1541621101
Short name T72
Test name
Test status
Simulation time 31780470 ps
CPU time 0.54 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 183168 kb
Host smart-db480eda-6498-45ae-b4da-60bc342a93c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541621101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1541621101
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.394598998
Short name T487
Test name
Test status
Simulation time 43544310 ps
CPU time 0.56 seconds
Started Dec 31 12:47:22 PM PST 23
Finished Dec 31 12:47:24 PM PST 23
Peak memory 182820 kb
Host smart-a8e8beaf-c12e-4468-896a-ce82cebdbc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394598998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.394598998
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3317527986
Short name T81
Test name
Test status
Simulation time 143051281 ps
CPU time 0.8 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 193560 kb
Host smart-198ce70c-2607-4bfc-b81a-cf3424aea18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317527986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3317527986
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3774899179
Short name T462
Test name
Test status
Simulation time 176732461 ps
CPU time 2.68 seconds
Started Dec 31 12:47:09 PM PST 23
Finished Dec 31 12:47:15 PM PST 23
Peak memory 197788 kb
Host smart-b765c44d-47e9-4c02-9f77-acf8d13a7dec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774899179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3774899179
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2688749703
Short name T384
Test name
Test status
Simulation time 53869245 ps
CPU time 0.82 seconds
Started Dec 31 12:47:18 PM PST 23
Finished Dec 31 12:47:25 PM PST 23
Peak memory 183292 kb
Host smart-979f9e77-472b-4314-be1d-5c6ae5e9a710
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688749703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2688749703
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2976113295
Short name T372
Test name
Test status
Simulation time 218336819 ps
CPU time 0.65 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:18 PM PST 23
Peak memory 194628 kb
Host smart-26ad4e1b-6e6a-4690-b7f4-930855045b8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976113295 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2976113295
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2897908859
Short name T45
Test name
Test status
Simulation time 12320219 ps
CPU time 0.52 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 183176 kb
Host smart-9c9eac44-2e3e-475e-b199-d6626088be2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897908859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2897908859
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3543805985
Short name T419
Test name
Test status
Simulation time 16018765 ps
CPU time 0.55 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:35 PM PST 23
Peak memory 182804 kb
Host smart-4051a925-258a-42f5-ba09-0396275437b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543805985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3543805985
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.229992237
Short name T433
Test name
Test status
Simulation time 34817456 ps
CPU time 0.8 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 192236 kb
Host smart-de9aa764-3501-4e6e-a7a3-bc4e44fec71a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229992237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.229992237
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4029423376
Short name T417
Test name
Test status
Simulation time 292755727 ps
CPU time 2.47 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:16 PM PST 23
Peak memory 198012 kb
Host smart-37d756df-7f1a-48d8-9383-d142c878cc3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029423376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4029423376
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1742359080
Short name T31
Test name
Test status
Simulation time 126065441 ps
CPU time 0.87 seconds
Started Dec 31 12:47:25 PM PST 23
Finished Dec 31 12:47:29 PM PST 23
Peak memory 194096 kb
Host smart-563f7602-3f52-4442-8e95-6365c70ec897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742359080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1742359080
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1252652162
Short name T420
Test name
Test status
Simulation time 72258449 ps
CPU time 0.68 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:33 PM PST 23
Peak memory 194888 kb
Host smart-56975872-04de-4bc1-9458-04d666d5bdc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252652162 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1252652162
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3648454347
Short name T78
Test name
Test status
Simulation time 27433361 ps
CPU time 0.57 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:25 PM PST 23
Peak memory 183196 kb
Host smart-2f499095-48fe-4d20-8900-25ba2240ee4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648454347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3648454347
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3039006196
Short name T376
Test name
Test status
Simulation time 23259598 ps
CPU time 0.53 seconds
Started Dec 31 12:47:12 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 182804 kb
Host smart-f27fd145-22fb-4e15-b5ab-9560e24509c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039006196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3039006196
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2406497248
Short name T14
Test name
Test status
Simulation time 13469301 ps
CPU time 0.59 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:18 PM PST 23
Peak memory 192452 kb
Host smart-4a3bbbe6-74a8-4745-90fd-146e72775c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406497248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2406497248
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1962775972
Short name T388
Test name
Test status
Simulation time 252428661 ps
CPU time 1.47 seconds
Started Dec 31 12:47:06 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 197976 kb
Host smart-80708d87-e8b2-495a-b702-add0243ac5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962775972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1962775972
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4146302251
Short name T405
Test name
Test status
Simulation time 813686242 ps
CPU time 1.15 seconds
Started Dec 31 12:47:33 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 183444 kb
Host smart-064e36d8-2187-415d-9371-7ad85e87e9db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146302251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.4146302251
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.766147629
Short name T490
Test name
Test status
Simulation time 114654070 ps
CPU time 1.52 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 198036 kb
Host smart-12d1427a-d6f4-42b9-b38e-a230d6780297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766147629 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.766147629
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2205796729
Short name T431
Test name
Test status
Simulation time 41538017 ps
CPU time 0.54 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 183168 kb
Host smart-c656f263-b4dc-4bf7-8485-9681ed0c7d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205796729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2205796729
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1105932751
Short name T472
Test name
Test status
Simulation time 152621307 ps
CPU time 0.55 seconds
Started Dec 31 12:47:14 PM PST 23
Finished Dec 31 12:47:16 PM PST 23
Peak memory 182920 kb
Host smart-c43498ae-a0d5-4d2e-9220-2cab4494687a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105932751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1105932751
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3351543238
Short name T65
Test name
Test status
Simulation time 42249558 ps
CPU time 0.58 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 191604 kb
Host smart-3dc8eb1d-6eaa-440d-860b-dfafc6991516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351543238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3351543238
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3493096132
Short name T459
Test name
Test status
Simulation time 267140578 ps
CPU time 1.23 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 196988 kb
Host smart-43bde21b-d637-4db3-8c90-4915a524fd31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493096132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3493096132
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2526978732
Short name T382
Test name
Test status
Simulation time 152689077 ps
CPU time 0.78 seconds
Started Dec 31 12:47:27 PM PST 23
Finished Dec 31 12:47:34 PM PST 23
Peak memory 183472 kb
Host smart-4edbe44f-070d-40d2-a7f2-e8db6e7cf374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526978732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2526978732
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3585931253
Short name T33
Test name
Test status
Simulation time 41047920 ps
CPU time 0.63 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 194060 kb
Host smart-fca6c52a-d0d1-4102-9fb3-c11920cf17dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585931253 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3585931253
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2802012418
Short name T397
Test name
Test status
Simulation time 30474188 ps
CPU time 0.54 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 182744 kb
Host smart-b349157b-6183-4bac-93b2-090d4c20a6fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802012418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2802012418
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.564958565
Short name T429
Test name
Test status
Simulation time 12941760 ps
CPU time 0.55 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 182896 kb
Host smart-9b11b17b-0994-40ef-92d8-26cff977a7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564958565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.564958565
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1010826820
Short name T79
Test name
Test status
Simulation time 16395969 ps
CPU time 0.71 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 193588 kb
Host smart-2c381dfe-5c16-47f0-b065-c8f886675855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010826820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1010826820
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3514669817
Short name T406
Test name
Test status
Simulation time 337855253 ps
CPU time 2.76 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 197972 kb
Host smart-1f45a5ab-2d21-48ae-8d87-9f76dc826f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514669817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3514669817
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1893976572
Short name T386
Test name
Test status
Simulation time 159864099 ps
CPU time 1.33 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 195780 kb
Host smart-da7a8a7f-c13c-4834-8783-28f7e75f1d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893976572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1893976572
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3607060982
Short name T476
Test name
Test status
Simulation time 30860353 ps
CPU time 0.83 seconds
Started Dec 31 12:47:35 PM PST 23
Finished Dec 31 12:47:42 PM PST 23
Peak memory 197828 kb
Host smart-d9dbdf39-60da-4d44-94ec-d708c34c9429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607060982 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3607060982
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1155781002
Short name T53
Test name
Test status
Simulation time 21405859 ps
CPU time 0.57 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 183124 kb
Host smart-7c6bc2a1-294b-4d79-afa5-7876e7e56347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155781002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1155781002
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.28467040
Short name T463
Test name
Test status
Simulation time 146942456 ps
CPU time 0.51 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:21 PM PST 23
Peak memory 182120 kb
Host smart-80e0f1bf-d43b-4330-94fc-fadb0e0e9f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28467040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.28467040
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4056984312
Short name T427
Test name
Test status
Simulation time 21811682 ps
CPU time 0.59 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 191656 kb
Host smart-3e17184e-da05-4186-8a51-04bfb627bb54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056984312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4056984312
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1261402976
Short name T479
Test name
Test status
Simulation time 335529379 ps
CPU time 1.33 seconds
Started Dec 31 12:47:18 PM PST 23
Finished Dec 31 12:47:20 PM PST 23
Peak memory 198040 kb
Host smart-c22bf3b0-be9d-4340-890a-73f387085455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261402976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1261402976
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4021561270
Short name T488
Test name
Test status
Simulation time 251514264 ps
CPU time 1.08 seconds
Started Dec 31 12:47:40 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 195320 kb
Host smart-55ed3b49-a99b-46e9-9257-a4c79f25fc31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021561270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4021561270
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2083653208
Short name T468
Test name
Test status
Simulation time 44844919 ps
CPU time 0.59 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 183212 kb
Host smart-ddc33404-2e16-40ee-8cb6-eb8dee044197
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083653208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2083653208
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4046055663
Short name T44
Test name
Test status
Simulation time 432013423 ps
CPU time 3.8 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 191676 kb
Host smart-c98c16fe-72bf-407c-a70f-1b4647e3fde1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046055663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4046055663
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3115653065
Short name T385
Test name
Test status
Simulation time 50437712 ps
CPU time 0.56 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:10 PM PST 23
Peak memory 182556 kb
Host smart-c031e289-dd9a-49fc-ac94-8a6cb6510b0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115653065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3115653065
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3569808825
Short name T402
Test name
Test status
Simulation time 20878763 ps
CPU time 1 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 197476 kb
Host smart-3611292f-7a50-4dcf-bef9-59c42eddaa7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569808825 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3569808825
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4222101524
Short name T73
Test name
Test status
Simulation time 54127632 ps
CPU time 0.52 seconds
Started Dec 31 12:47:05 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 182664 kb
Host smart-80d7de16-b45b-44b4-bded-64f042db64f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222101524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4222101524
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2182814538
Short name T422
Test name
Test status
Simulation time 46119329 ps
CPU time 0.53 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 182024 kb
Host smart-0969b30b-fe76-4bf0-9134-775c69c027d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182814538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2182814538
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1976321744
Short name T418
Test name
Test status
Simulation time 34604423 ps
CPU time 0.59 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 191912 kb
Host smart-410cc528-31b8-4912-9a57-e05b694045d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976321744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1976321744
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2089156181
Short name T461
Test name
Test status
Simulation time 91961237 ps
CPU time 2.23 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:21 PM PST 23
Peak memory 197760 kb
Host smart-e8582d42-32f4-4136-ad0c-27e9f8102587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089156181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2089156181
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1791412000
Short name T442
Test name
Test status
Simulation time 155162252 ps
CPU time 0.8 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:20 PM PST 23
Peak memory 183464 kb
Host smart-88ecc7a1-dde1-4399-8e09-d6d354d67579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791412000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1791412000
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2450914899
Short name T423
Test name
Test status
Simulation time 28405048 ps
CPU time 0.54 seconds
Started Dec 31 12:47:26 PM PST 23
Finished Dec 31 12:47:43 PM PST 23
Peak memory 182924 kb
Host smart-b8ef5335-d6d8-4926-961f-6d17bb5296a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450914899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2450914899
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3741103941
Short name T63
Test name
Test status
Simulation time 23235513 ps
CPU time 0.54 seconds
Started Dec 31 12:47:46 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 182928 kb
Host smart-6ede6883-f6e4-4cfd-9340-404ccac10e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741103941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3741103941
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2749973818
Short name T428
Test name
Test status
Simulation time 14822736 ps
CPU time 0.58 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 182860 kb
Host smart-e74f3d94-f5fe-4bb2-bdd1-7ea0aa3d178f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749973818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2749973818
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.458432299
Short name T482
Test name
Test status
Simulation time 39521982 ps
CPU time 0.52 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 182404 kb
Host smart-d69eee05-c4ed-4dc3-baee-63f6584ab208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458432299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.458432299
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2174495791
Short name T409
Test name
Test status
Simulation time 27722852 ps
CPU time 0.53 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 182920 kb
Host smart-d5232391-cfc4-4580-848b-8bb2fc3c0115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174495791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2174495791
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1409819855
Short name T454
Test name
Test status
Simulation time 57175082 ps
CPU time 0.55 seconds
Started Dec 31 12:47:36 PM PST 23
Finished Dec 31 12:47:43 PM PST 23
Peak memory 182928 kb
Host smart-4c16b220-cc39-41a1-9cfc-5f08aaec7046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409819855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1409819855
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3674165874
Short name T373
Test name
Test status
Simulation time 42505817 ps
CPU time 0.56 seconds
Started Dec 31 12:47:30 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 182824 kb
Host smart-84df91e0-8614-4188-affc-cf7a4445acda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674165874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3674165874
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1824276422
Short name T436
Test name
Test status
Simulation time 47309031 ps
CPU time 0.52 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:35 PM PST 23
Peak memory 182836 kb
Host smart-2df66904-d2f0-4a3d-8d8c-f79b91138ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824276422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1824276422
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2486992913
Short name T375
Test name
Test status
Simulation time 49771161 ps
CPU time 0.54 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 182852 kb
Host smart-3a99329f-94e6-4696-abf7-a9114b943e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486992913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2486992913
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3048745434
Short name T380
Test name
Test status
Simulation time 135147125 ps
CPU time 0.52 seconds
Started Dec 31 12:47:12 PM PST 23
Finished Dec 31 12:47:15 PM PST 23
Peak memory 182048 kb
Host smart-8ae2b30f-ea75-4c8a-b52f-ef0c39e0620c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048745434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3048745434
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2828636075
Short name T394
Test name
Test status
Simulation time 195773975 ps
CPU time 2.51 seconds
Started Dec 31 12:47:00 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 192636 kb
Host smart-0ce8a338-5a11-46f1-8d34-a122e2afb0a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828636075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2828636075
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.878746681
Short name T66
Test name
Test status
Simulation time 49894295 ps
CPU time 0.55 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 183116 kb
Host smart-321d648a-067e-42b6-8bda-1f8820044b50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878746681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.878746681
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1729502794
Short name T435
Test name
Test status
Simulation time 92800603 ps
CPU time 1.19 seconds
Started Dec 31 12:47:04 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 198092 kb
Host smart-832f167b-1693-4a4e-b16f-3f943e30c78c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729502794 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1729502794
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.21390234
Short name T77
Test name
Test status
Simulation time 12597355 ps
CPU time 0.57 seconds
Started Dec 31 12:46:57 PM PST 23
Finished Dec 31 12:46:58 PM PST 23
Peak memory 183208 kb
Host smart-dd9bc5be-0713-4033-838c-7e2e9ca15b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21390234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.21390234
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3046595111
Short name T424
Test name
Test status
Simulation time 45725189 ps
CPU time 0.53 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 182804 kb
Host smart-a5dd3916-bf0b-4e49-afc3-f4cc77e5e9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046595111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3046595111
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1825974298
Short name T451
Test name
Test status
Simulation time 39669273 ps
CPU time 0.62 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 192448 kb
Host smart-b641ab9e-599d-4a7a-a7fa-45f4ed4c25ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825974298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1825974298
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1689392987
Short name T425
Test name
Test status
Simulation time 72216070 ps
CPU time 1.05 seconds
Started Dec 31 12:47:01 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 197872 kb
Host smart-4482d85b-10ce-4df2-9602-70be0632d664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689392987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1689392987
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3086870751
Short name T401
Test name
Test status
Simulation time 44102321 ps
CPU time 0.8 seconds
Started Dec 31 12:47:00 PM PST 23
Finished Dec 31 12:47:03 PM PST 23
Peak memory 183304 kb
Host smart-64ae8f61-4739-4bb2-b8c7-37bc875a592d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086870751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3086870751
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.456288066
Short name T408
Test name
Test status
Simulation time 31336845 ps
CPU time 0.52 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 182468 kb
Host smart-6a9ee1a9-36f5-4a4f-8d99-c10039cb53ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456288066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.456288066
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3787224417
Short name T460
Test name
Test status
Simulation time 13972194 ps
CPU time 0.53 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 182872 kb
Host smart-9733bbd1-d0cb-4ffe-a2ac-cff61f69162d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787224417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3787224417
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1265992414
Short name T485
Test name
Test status
Simulation time 10558467 ps
CPU time 0.51 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 182060 kb
Host smart-3adc4386-d15c-4b31-806c-562935f36a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265992414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1265992414
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3844643176
Short name T393
Test name
Test status
Simulation time 23142140 ps
CPU time 0.54 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 182768 kb
Host smart-966e1174-1a3b-4fdc-a318-359eff2d0ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844643176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3844643176
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.269355097
Short name T396
Test name
Test status
Simulation time 40785857 ps
CPU time 0.53 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:36 PM PST 23
Peak memory 182876 kb
Host smart-7a5a7e7d-ae48-4a11-bba9-020f94858f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269355097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.269355097
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3219513284
Short name T389
Test name
Test status
Simulation time 115100475 ps
CPU time 0.52 seconds
Started Dec 31 12:47:18 PM PST 23
Finished Dec 31 12:47:20 PM PST 23
Peak memory 182448 kb
Host smart-319c5125-db53-4d09-988c-19b83cca6818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219513284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3219513284
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2723156914
Short name T399
Test name
Test status
Simulation time 65968145 ps
CPU time 0.54 seconds
Started Dec 31 12:47:27 PM PST 23
Finished Dec 31 12:47:33 PM PST 23
Peak memory 182836 kb
Host smart-14ba0f8c-6c89-4d0d-8d75-c96015c7559f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723156914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2723156914
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2792157845
Short name T446
Test name
Test status
Simulation time 16490279 ps
CPU time 0.54 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 182948 kb
Host smart-df6bc047-c805-4b5b-8eda-e74d5b812aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792157845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2792157845
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3498577994
Short name T392
Test name
Test status
Simulation time 27174046 ps
CPU time 0.56 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:24 PM PST 23
Peak memory 183176 kb
Host smart-ed12ead2-e2cd-4a20-a4a7-2ce42c75dce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498577994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3498577994
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1510962597
Short name T486
Test name
Test status
Simulation time 158637079 ps
CPU time 0.54 seconds
Started Dec 31 12:47:43 PM PST 23
Finished Dec 31 12:47:46 PM PST 23
Peak memory 182848 kb
Host smart-d3d75940-4d4e-456d-a94a-ffdad36793ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510962597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1510962597
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3623942343
Short name T64
Test name
Test status
Simulation time 18019943 ps
CPU time 0.73 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 183148 kb
Host smart-40e784a4-a604-4631-9bfa-4105f7ad2d88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623942343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3623942343
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1274510618
Short name T395
Test name
Test status
Simulation time 555088126 ps
CPU time 2.57 seconds
Started Dec 31 12:46:58 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 183380 kb
Host smart-3290dd91-2495-43e7-8159-0dee34aff5cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274510618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1274510618
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.580676338
Short name T71
Test name
Test status
Simulation time 46007009 ps
CPU time 0.55 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 183204 kb
Host smart-fa939214-2314-4550-a000-4e06673e4440
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580676338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.580676338
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1000202735
Short name T400
Test name
Test status
Simulation time 94483931 ps
CPU time 0.74 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 195368 kb
Host smart-baa53c68-3759-4375-ad54-4bab9411b49f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000202735 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1000202735
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1423778896
Short name T473
Test name
Test status
Simulation time 23934701 ps
CPU time 0.57 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 183200 kb
Host smart-b1ec9e94-10e8-4625-a2c8-2662a49d6eea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423778896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1423778896
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1110677481
Short name T387
Test name
Test status
Simulation time 39670709 ps
CPU time 0.51 seconds
Started Dec 31 12:47:03 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 182464 kb
Host smart-2121a697-a08a-4596-94ef-35f3e7ffc162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110677481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1110677481
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1766587651
Short name T445
Test name
Test status
Simulation time 18848287 ps
CPU time 0.77 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 192220 kb
Host smart-3daed094-5c86-4d4c-87a8-6689932af44c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766587651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1766587651
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3680524217
Short name T437
Test name
Test status
Simulation time 48579529 ps
CPU time 1.21 seconds
Started Dec 31 12:46:57 PM PST 23
Finished Dec 31 12:46:59 PM PST 23
Peak memory 197864 kb
Host smart-08430596-e155-4976-8d21-6f43e6921041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680524217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3680524217
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1652368243
Short name T58
Test name
Test status
Simulation time 197287640 ps
CPU time 0.84 seconds
Started Dec 31 12:46:55 PM PST 23
Finished Dec 31 12:46:57 PM PST 23
Peak memory 193904 kb
Host smart-1dfc2912-cd02-4c3e-a3f6-f993b4b313a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652368243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1652368243
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.241894623
Short name T379
Test name
Test status
Simulation time 168268093 ps
CPU time 0.56 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 182956 kb
Host smart-7e0e44d2-1b60-4ef3-82ad-ec6c07eb8204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241894623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.241894623
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2268866399
Short name T374
Test name
Test status
Simulation time 59208259 ps
CPU time 0.56 seconds
Started Dec 31 12:47:25 PM PST 23
Finished Dec 31 12:47:29 PM PST 23
Peak memory 182848 kb
Host smart-db9ad462-0f83-4682-86ea-302f0de89409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268866399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2268866399
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2187532449
Short name T415
Test name
Test status
Simulation time 15168140 ps
CPU time 0.54 seconds
Started Dec 31 12:47:22 PM PST 23
Finished Dec 31 12:47:24 PM PST 23
Peak memory 182496 kb
Host smart-05d2a727-d64a-4867-b8e6-dd5cfd5269d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187532449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2187532449
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.516349568
Short name T450
Test name
Test status
Simulation time 13616479 ps
CPU time 0.51 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:34 PM PST 23
Peak memory 182032 kb
Host smart-5c8ae0b9-97e0-4edd-96f0-cb763215b3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516349568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.516349568
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.134956798
Short name T390
Test name
Test status
Simulation time 54329261 ps
CPU time 0.58 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 182860 kb
Host smart-e5b1f706-d067-408e-8ed7-19488839c850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134956798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.134956798
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2816317625
Short name T404
Test name
Test status
Simulation time 18064061 ps
CPU time 0.55 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 182900 kb
Host smart-1a771676-4003-4b4b-8173-bd271ef36d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816317625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2816317625
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2000439934
Short name T444
Test name
Test status
Simulation time 16222740 ps
CPU time 0.54 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 182844 kb
Host smart-81648bcd-ea6d-4639-a116-ab8ba641bf36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000439934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2000439934
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.531621068
Short name T371
Test name
Test status
Simulation time 15374364 ps
CPU time 0.57 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:43 PM PST 23
Peak memory 182816 kb
Host smart-01fb7d04-e775-4cd6-b97f-127a4e8a9ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531621068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.531621068
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.783425585
Short name T480
Test name
Test status
Simulation time 14141766 ps
CPU time 0.54 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:41 PM PST 23
Peak memory 181992 kb
Host smart-36506d47-5ddf-4b40-8045-994832168d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783425585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.783425585
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1583648124
Short name T74
Test name
Test status
Simulation time 32947376 ps
CPU time 0.52 seconds
Started Dec 31 12:47:22 PM PST 23
Finished Dec 31 12:47:24 PM PST 23
Peak memory 182472 kb
Host smart-2d0d9976-d03c-461b-9f3b-1714409f8fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583648124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1583648124
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.131414894
Short name T54
Test name
Test status
Simulation time 67825135 ps
CPU time 0.94 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 197872 kb
Host smart-5c1b160d-4f65-413d-bafa-e1d4934b3c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131414894 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.131414894
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1248250961
Short name T76
Test name
Test status
Simulation time 15153459 ps
CPU time 0.61 seconds
Started Dec 31 12:47:25 PM PST 23
Finished Dec 31 12:47:29 PM PST 23
Peak memory 183228 kb
Host smart-a73b6f0e-11e2-452a-adb0-66bdac4788f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248250961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1248250961
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2343901922
Short name T70
Test name
Test status
Simulation time 44801699 ps
CPU time 0.52 seconds
Started Dec 31 12:47:13 PM PST 23
Finished Dec 31 12:47:16 PM PST 23
Peak memory 182804 kb
Host smart-7f5a10f5-850b-4f8d-a373-c8e6f9f29406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343901922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2343901922
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2182046039
Short name T82
Test name
Test status
Simulation time 53983212 ps
CPU time 0.58 seconds
Started Dec 31 12:47:08 PM PST 23
Finished Dec 31 12:47:12 PM PST 23
Peak memory 192472 kb
Host smart-dec9826b-648d-401e-bee7-ecd72bd4b06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182046039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2182046039
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2698033719
Short name T478
Test name
Test status
Simulation time 421267307 ps
CPU time 1.18 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:20 PM PST 23
Peak memory 197948 kb
Host smart-d1e98f5f-8d9a-4691-b9e3-9822f82ceae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698033719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2698033719
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1635833869
Short name T47
Test name
Test status
Simulation time 83820585 ps
CPU time 0.8 seconds
Started Dec 31 12:47:02 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 193896 kb
Host smart-1cc0c401-c3b7-4365-93f1-39946f290cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635833869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1635833869
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1696881022
Short name T452
Test name
Test status
Simulation time 215867563 ps
CPU time 0.76 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 195132 kb
Host smart-62fc6d59-b4db-48f8-9e43-340f1c26a773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696881022 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1696881022
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1497488855
Short name T466
Test name
Test status
Simulation time 54087278 ps
CPU time 0.58 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:21 PM PST 23
Peak memory 192432 kb
Host smart-a356658b-a2ba-4cd1-a809-110aec66ea2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497488855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1497488855
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3687001268
Short name T411
Test name
Test status
Simulation time 42769241 ps
CPU time 0.52 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 182056 kb
Host smart-258e2551-4938-436c-8af4-5bac44458298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687001268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3687001268
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.368632913
Short name T84
Test name
Test status
Simulation time 161335722 ps
CPU time 0.79 seconds
Started Dec 31 12:47:01 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 193724 kb
Host smart-2a8cdd64-d66c-42b5-916a-be1aeeaeabf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368632913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.368632913
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1244624818
Short name T407
Test name
Test status
Simulation time 154987345 ps
CPU time 1.64 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 197944 kb
Host smart-a525be23-7bd2-49f9-ac72-24a0975514c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244624818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1244624818
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.988915990
Short name T383
Test name
Test status
Simulation time 169258983 ps
CPU time 0.81 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 183272 kb
Host smart-4b1e117c-104f-4cbe-9009-aa67da5cea82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988915990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.988915990
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3862137549
Short name T413
Test name
Test status
Simulation time 67796530 ps
CPU time 1 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:18 PM PST 23
Peak memory 197824 kb
Host smart-bdbcf27f-ae1d-4784-9594-76d897ef7491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862137549 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3862137549
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.315514376
Short name T432
Test name
Test status
Simulation time 36543873 ps
CPU time 0.54 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 183144 kb
Host smart-35b3d317-b5fa-4d43-a96a-cae25c5db227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315514376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.315514376
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3078536034
Short name T470
Test name
Test status
Simulation time 22694039 ps
CPU time 0.57 seconds
Started Dec 31 12:47:27 PM PST 23
Finished Dec 31 12:47:33 PM PST 23
Peak memory 182296 kb
Host smart-6e079b3b-2a73-49c2-8001-af65ea37848d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078536034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3078536034
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.526530308
Short name T489
Test name
Test status
Simulation time 152750735 ps
CPU time 0.79 seconds
Started Dec 31 12:47:35 PM PST 23
Finished Dec 31 12:47:42 PM PST 23
Peak memory 193756 kb
Host smart-9c0ad848-3d99-465c-81a8-d67bc7b01e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526530308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.526530308
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3552769682
Short name T426
Test name
Test status
Simulation time 72143722 ps
CPU time 1.28 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 197964 kb
Host smart-a03ee830-4db3-49ed-b40f-1591ee11e14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552769682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3552769682
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4073438480
Short name T85
Test name
Test status
Simulation time 90595140 ps
CPU time 0.78 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 193648 kb
Host smart-22efba6b-5113-4669-bb4f-738b2bbc26b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073438480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4073438480
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.262718132
Short name T456
Test name
Test status
Simulation time 26395353 ps
CPU time 0.96 seconds
Started Dec 31 12:47:03 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 197644 kb
Host smart-eb46d870-aa07-40a6-b8bd-b2270cd1e356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262718132 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.262718132
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2266537984
Short name T455
Test name
Test status
Simulation time 18686329 ps
CPU time 0.56 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 183288 kb
Host smart-e12f65b2-af7e-476e-be52-ed97e387bb1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266537984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2266537984
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3719359234
Short name T449
Test name
Test status
Simulation time 11686039 ps
CPU time 0.52 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:18 PM PST 23
Peak memory 182008 kb
Host smart-e38c092a-29cb-489b-a76b-467395a0f82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719359234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3719359234
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3518999233
Short name T457
Test name
Test status
Simulation time 32286744 ps
CPU time 0.8 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 192172 kb
Host smart-a9cc0b21-4058-49a6-852a-eae122ea01bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518999233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3518999233
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3909530466
Short name T441
Test name
Test status
Simulation time 89017315 ps
CPU time 1.35 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 198000 kb
Host smart-57f1ffa5-bc5b-4886-81d5-91c95ff6410d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909530466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3909530466
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1090228994
Short name T410
Test name
Test status
Simulation time 137095647 ps
CPU time 0.83 seconds
Started Dec 31 12:47:05 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 193928 kb
Host smart-7d719ae3-81a2-4312-80c8-393a140ad205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090228994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1090228994
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1044875024
Short name T465
Test name
Test status
Simulation time 36112719 ps
CPU time 0.75 seconds
Started Dec 31 12:47:20 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 196472 kb
Host smart-35e5f744-250e-484d-8f71-da1986aed9ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044875024 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1044875024
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2219835352
Short name T62
Test name
Test status
Simulation time 36108176 ps
CPU time 0.55 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:25 PM PST 23
Peak memory 183296 kb
Host smart-605c414d-c9ca-44f2-add2-dae4017c5cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219835352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2219835352
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3282905465
Short name T458
Test name
Test status
Simulation time 51592450 ps
CPU time 0.53 seconds
Started Dec 31 12:47:02 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 182824 kb
Host smart-3290d319-cb19-46be-8215-a2b59ee75ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282905465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3282905465
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3891481426
Short name T471
Test name
Test status
Simulation time 35637938 ps
CPU time 0.83 seconds
Started Dec 31 12:47:06 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 192132 kb
Host smart-91a1bc0a-a370-4bee-86a1-04f70495fc0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891481426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3891481426
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.866583198
Short name T403
Test name
Test status
Simulation time 1187022959 ps
CPU time 2.13 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:25 PM PST 23
Peak memory 196896 kb
Host smart-a748d6f1-6724-4b50-9bfc-bda11fb03aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866583198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.866583198
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1582711644
Short name T32
Test name
Test status
Simulation time 179053719 ps
CPU time 1.33 seconds
Started Dec 31 12:47:17 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 195836 kb
Host smart-52ffff24-2ccf-487e-8418-b9edeee391de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582711644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1582711644
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.777133658
Short name T593
Test name
Test status
Simulation time 4026261177 ps
CPU time 4.57 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 12:59:06 PM PST 23
Peak memory 182836 kb
Host smart-36826c7e-4c17-46d6-a262-18586b41e367
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777133658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.777133658
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4027075085
Short name T506
Test name
Test status
Simulation time 365887660053 ps
CPU time 121.8 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:01:01 PM PST 23
Peak memory 182932 kb
Host smart-483af9c6-940c-414e-bc37-35923613935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027075085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4027075085
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3209062864
Short name T180
Test name
Test status
Simulation time 110256953074 ps
CPU time 105.16 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:01:01 PM PST 23
Peak memory 193092 kb
Host smart-2d4808e1-d72e-4599-8649-9f4a803e15ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209062864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3209062864
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2584309098
Short name T7
Test name
Test status
Simulation time 58174964729 ps
CPU time 48.61 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 12:59:56 PM PST 23
Peak memory 192440 kb
Host smart-f1f55b41-2b1e-47d6-a3c1-a518e1e6da31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584309098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2584309098
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4109179994
Short name T523
Test name
Test status
Simulation time 169136133537 ps
CPU time 483.51 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:07:10 PM PST 23
Peak memory 191088 kb
Host smart-1bfe92bf-ae18-4371-995f-4089ba6a24a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109179994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4109179994
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.679244270
Short name T535
Test name
Test status
Simulation time 27870629339 ps
CPU time 293.77 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 01:03:47 PM PST 23
Peak memory 197560 kb
Host smart-104f0cb6-acaf-42a6-98cd-7c08da2f634e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679244270 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.679244270
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.544562438
Short name T359
Test name
Test status
Simulation time 347093289159 ps
CPU time 614.76 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 182904 kb
Host smart-204a5027-1022-43b6-be60-ff577c93c846
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544562438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.544562438
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2277048798
Short name T514
Test name
Test status
Simulation time 110160706964 ps
CPU time 28.56 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 12:59:45 PM PST 23
Peak memory 182836 kb
Host smart-b4120910-07ee-4e21-a5e1-56d584505091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277048798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2277048798
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3407545632
Short name T242
Test name
Test status
Simulation time 145492105328 ps
CPU time 130.25 seconds
Started Dec 31 12:59:27 PM PST 23
Finished Dec 31 01:01:39 PM PST 23
Peak memory 191160 kb
Host smart-047aff32-d876-4fad-a00c-7138098d448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407545632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3407545632
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2099831610
Short name T19
Test name
Test status
Simulation time 33612213 ps
CPU time 0.75 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 12:59:17 PM PST 23
Peak memory 212788 kb
Host smart-feaf9597-c22a-4ad9-b06f-02804a8f4daa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099831610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2099831610
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2740536465
Short name T12
Test name
Test status
Simulation time 111557569380 ps
CPU time 527.58 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:07:59 PM PST 23
Peak memory 205852 kb
Host smart-65469366-cd20-46b4-9538-481af306f34c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740536465 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2740536465
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1288648116
Short name T573
Test name
Test status
Simulation time 455573521822 ps
CPU time 184.62 seconds
Started Dec 31 12:58:40 PM PST 23
Finished Dec 31 01:01:51 PM PST 23
Peak memory 182904 kb
Host smart-7012e251-6025-4d9b-9905-3af899fc79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288648116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1288648116
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3787840649
Short name T499
Test name
Test status
Simulation time 146144467946 ps
CPU time 68.02 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:00:17 PM PST 23
Peak memory 182876 kb
Host smart-81d995c3-81c1-48bc-83a4-c9f16e3c4e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787840649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3787840649
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.276386374
Short name T149
Test name
Test status
Simulation time 17994713166 ps
CPU time 15.51 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 12:59:24 PM PST 23
Peak memory 182988 kb
Host smart-aca26238-8cc5-4b26-9edf-5165ce503a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276386374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.276386374
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3681235118
Short name T57
Test name
Test status
Simulation time 979256836824 ps
CPU time 298.58 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:04:07 PM PST 23
Peak memory 182916 kb
Host smart-fc2d7bda-e92d-427e-852f-16e761c93b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681235118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3681235118
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.3806071381
Short name T133
Test name
Test status
Simulation time 213933319546 ps
CPU time 764.45 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 01:11:37 PM PST 23
Peak memory 213812 kb
Host smart-b3efe31c-25da-4eac-bb1d-c70af45a9f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806071381 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.3806071381
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3355161575
Short name T360
Test name
Test status
Simulation time 355551560916 ps
CPU time 690.45 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:10:47 PM PST 23
Peak memory 191184 kb
Host smart-f54627cb-ca79-4d38-a1a5-f6a9c2cec8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355161575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3355161575
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.978518718
Short name T364
Test name
Test status
Simulation time 613652606634 ps
CPU time 782.61 seconds
Started Dec 31 12:59:22 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 191316 kb
Host smart-b221e709-2b1e-4c93-b001-0af7edb0fea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978518718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.978518718
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2163197634
Short name T356
Test name
Test status
Simulation time 5048598375 ps
CPU time 9.15 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 12:59:08 PM PST 23
Peak memory 182984 kb
Host smart-d0324f57-bb95-4b82-88aa-0ea32df38e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163197634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2163197634
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.54372149
Short name T192
Test name
Test status
Simulation time 69244465201 ps
CPU time 61.79 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:00:08 PM PST 23
Peak memory 191104 kb
Host smart-c0b36476-52da-4837-9094-f9846147a452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54372149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.54372149
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2113316070
Short name T200
Test name
Test status
Simulation time 103698633758 ps
CPU time 166.86 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:02:11 PM PST 23
Peak memory 191112 kb
Host smart-6a527a84-c74c-4d9b-8359-dc2eef3f012c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113316070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2113316070
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2229682591
Short name T325
Test name
Test status
Simulation time 139422516039 ps
CPU time 115.06 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:00:54 PM PST 23
Peak memory 191184 kb
Host smart-48d0f3e3-5bf8-489f-a6f5-c2c4a8e41f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229682591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2229682591
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3224791029
Short name T614
Test name
Test status
Simulation time 150034056443 ps
CPU time 169.37 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:02:08 PM PST 23
Peak memory 192468 kb
Host smart-975fe7d3-15be-4f41-a522-1c775b927389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224791029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3224791029
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2593420771
Short name T250
Test name
Test status
Simulation time 197083835388 ps
CPU time 531.55 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:08:09 PM PST 23
Peak memory 191124 kb
Host smart-3b93bfa8-b9e9-4f2c-a14c-f8518823e7be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593420771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2593420771
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.219913016
Short name T220
Test name
Test status
Simulation time 67675615375 ps
CPU time 114.21 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:01:03 PM PST 23
Peak memory 191112 kb
Host smart-ca64ef4a-fa8d-425f-b727-1c26fb118089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219913016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.219913016
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1789868617
Short name T126
Test name
Test status
Simulation time 210912367020 ps
CPU time 359.79 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:05:18 PM PST 23
Peak memory 182868 kb
Host smart-a806686c-358a-46bc-83ed-d9c9d87bcbf8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789868617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1789868617
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2900380902
Short name T368
Test name
Test status
Simulation time 21750298922 ps
CPU time 9.28 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 12:59:16 PM PST 23
Peak memory 182872 kb
Host smart-9427a362-02dd-4cc5-b771-28d6e6090931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900380902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2900380902
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1711099578
Short name T357
Test name
Test status
Simulation time 303310345433 ps
CPU time 259.88 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:03:17 PM PST 23
Peak memory 194440 kb
Host smart-3d84b182-138e-41b9-9139-4cf35ada6742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711099578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1711099578
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2284414628
Short name T553
Test name
Test status
Simulation time 577790229 ps
CPU time 4.5 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 12:59:19 PM PST 23
Peak memory 192596 kb
Host smart-d58a97c9-e0af-4f40-b6bb-ebef638c83b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284414628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2284414628
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.2545886574
Short name T524
Test name
Test status
Simulation time 107796786049 ps
CPU time 467.64 seconds
Started Dec 31 12:58:45 PM PST 23
Finished Dec 31 01:06:40 PM PST 23
Peak memory 205880 kb
Host smart-deb5fa2d-9dc9-4bd0-ab5f-929c9325f2fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545886574 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.2545886574
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2704143922
Short name T218
Test name
Test status
Simulation time 105700689929 ps
CPU time 269.61 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:03:37 PM PST 23
Peak memory 191072 kb
Host smart-e68d0186-7336-4ffd-ba0e-ab7f3d2d6da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704143922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2704143922
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3358194314
Short name T52
Test name
Test status
Simulation time 311911215316 ps
CPU time 191 seconds
Started Dec 31 12:59:28 PM PST 23
Finished Dec 31 01:02:40 PM PST 23
Peak memory 190908 kb
Host smart-6fe48538-fb50-4370-ba31-99ef9af1ad84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358194314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3358194314
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.795345505
Short name T187
Test name
Test status
Simulation time 1132496339241 ps
CPU time 441.67 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:06:43 PM PST 23
Peak memory 192144 kb
Host smart-aa62ce27-64b8-4227-8301-ac29485b0485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795345505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.795345505
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3069726829
Short name T263
Test name
Test status
Simulation time 118970585230 ps
CPU time 131.26 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:01:34 PM PST 23
Peak memory 191196 kb
Host smart-c3931a1f-0f26-4942-a810-8c323b774efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069726829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3069726829
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.31734477
Short name T204
Test name
Test status
Simulation time 108131438012 ps
CPU time 297.96 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:04:22 PM PST 23
Peak memory 191160 kb
Host smart-c1b2a1cb-a478-4d0e-8236-30672d23f4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.31734477
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.309720913
Short name T324
Test name
Test status
Simulation time 91253116086 ps
CPU time 76.41 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:00:31 PM PST 23
Peak memory 182920 kb
Host smart-c03b675e-4bb8-4b29-baa5-11882775b816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309720913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.309720913
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2294421202
Short name T540
Test name
Test status
Simulation time 171357265093 ps
CPU time 444.37 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:06:33 PM PST 23
Peak memory 182832 kb
Host smart-fdf5bc25-6129-4a27-ac18-a961873e3cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294421202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2294421202
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.901822845
Short name T579
Test name
Test status
Simulation time 389019728085 ps
CPU time 1008.98 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:16:06 PM PST 23
Peak memory 193764 kb
Host smart-0469bc0e-43a3-4738-83e8-012b78f0def7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901822845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.901822845
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1761641839
Short name T498
Test name
Test status
Simulation time 21369714262 ps
CPU time 18.84 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 12:59:16 PM PST 23
Peak memory 182868 kb
Host smart-234dea36-04a4-4b02-adb2-9f062c849233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761641839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1761641839
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3859453696
Short name T603
Test name
Test status
Simulation time 100079486502 ps
CPU time 639.08 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:10:02 PM PST 23
Peak memory 191132 kb
Host smart-33f49e53-8250-4267-8418-2b198579575e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859453696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3859453696
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3265761106
Short name T110
Test name
Test status
Simulation time 116409866590 ps
CPU time 63.17 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:00:19 PM PST 23
Peak memory 191088 kb
Host smart-dd76b515-b919-47a1-a353-5dce1c44492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265761106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3265761106
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2074847695
Short name T502
Test name
Test status
Simulation time 111117897943 ps
CPU time 250.14 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:03:17 PM PST 23
Peak memory 197568 kb
Host smart-e51d6e19-b4da-4cf9-a236-5f63847d7390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074847695 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2074847695
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2290444317
Short name T355
Test name
Test status
Simulation time 71643783709 ps
CPU time 558.2 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:08:37 PM PST 23
Peak memory 191092 kb
Host smart-40cb7b4c-ed1c-44fa-8fc0-ddfb43818b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290444317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2290444317
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.142221575
Short name T212
Test name
Test status
Simulation time 434323570217 ps
CPU time 2207.89 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:35:47 PM PST 23
Peak memory 191048 kb
Host smart-dd78a1a4-50b3-432c-a493-22abbb03df97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142221575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.142221575
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2961469816
Short name T137
Test name
Test status
Simulation time 205116681325 ps
CPU time 567.03 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:08:41 PM PST 23
Peak memory 191160 kb
Host smart-68af3712-a47e-4dd3-b402-3498772f390b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961469816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2961469816
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3425548783
Short name T298
Test name
Test status
Simulation time 14625590662 ps
CPU time 7.08 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 12:59:19 PM PST 23
Peak memory 182996 kb
Host smart-1aaa1a7f-2fb4-4e99-8ef4-782be7682277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425548783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3425548783
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2847578889
Short name T253
Test name
Test status
Simulation time 38111499343 ps
CPU time 44.61 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 12:59:58 PM PST 23
Peak memory 192184 kb
Host smart-9aee38d0-f513-442f-b12c-c6baa6d5dc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847578889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2847578889
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1435551134
Short name T354
Test name
Test status
Simulation time 137284077806 ps
CPU time 252.42 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:03:32 PM PST 23
Peak memory 191116 kb
Host smart-79cdb0e6-791a-4e56-9c88-76a1e740add7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435551134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1435551134
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1660294754
Short name T332
Test name
Test status
Simulation time 3635664089 ps
CPU time 5.98 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 12:59:25 PM PST 23
Peak memory 182972 kb
Host smart-02f4086c-7317-471b-b6a8-f167708db4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660294754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1660294754
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.913649976
Short name T152
Test name
Test status
Simulation time 562515565471 ps
CPU time 930.46 seconds
Started Dec 31 12:59:30 PM PST 23
Finished Dec 31 01:15:01 PM PST 23
Peak memory 191048 kb
Host smart-03ff17c2-3fa8-4bef-83f0-a77d6c8f97f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913649976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.913649976
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.105783135
Short name T508
Test name
Test status
Simulation time 321074371003 ps
CPU time 236.15 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:03:08 PM PST 23
Peak memory 182760 kb
Host smart-73584a07-c2e7-4df2-90e7-0cadd0bb40ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105783135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.105783135
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.4130864550
Short name T611
Test name
Test status
Simulation time 188627049 ps
CPU time 0.7 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 12:59:07 PM PST 23
Peak memory 182708 kb
Host smart-5f737b92-67c2-40c4-815e-d997cf4915ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130864550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4130864550
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.933320967
Short name T507
Test name
Test status
Simulation time 529663227468 ps
CPU time 580.99 seconds
Started Dec 31 12:58:57 PM PST 23
Finished Dec 31 01:08:44 PM PST 23
Peak memory 183044 kb
Host smart-e7e1e047-f905-4940-98c2-c033b07af410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933320967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
933320967
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3024855792
Short name T613
Test name
Test status
Simulation time 30788337728 ps
CPU time 288.95 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:03:53 PM PST 23
Peak memory 205868 kb
Host smart-b2a94e89-6449-4204-93f7-0569db7b336b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024855792 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3024855792
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2102571578
Short name T259
Test name
Test status
Simulation time 13349088417 ps
CPU time 82.19 seconds
Started Dec 31 12:59:22 PM PST 23
Finished Dec 31 01:00:47 PM PST 23
Peak memory 182956 kb
Host smart-669938a3-2f1a-4060-92c9-8d3f52cba911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102571578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2102571578
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1955156075
Short name T339
Test name
Test status
Simulation time 14324131881 ps
CPU time 24.54 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 12:59:35 PM PST 23
Peak memory 182964 kb
Host smart-90f27894-61d8-4c42-a2d2-b5cba669105c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955156075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1955156075
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1124251499
Short name T215
Test name
Test status
Simulation time 522667087035 ps
CPU time 513.73 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:07:46 PM PST 23
Peak memory 191168 kb
Host smart-3afed48c-2e4c-4672-b449-f93cdc24c697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124251499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1124251499
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.116027176
Short name T305
Test name
Test status
Simulation time 7063122609 ps
CPU time 10.62 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 12:59:32 PM PST 23
Peak memory 182888 kb
Host smart-86d85497-57f5-4737-8528-43d89899599b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116027176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.116027176
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2996749626
Short name T113
Test name
Test status
Simulation time 61523102428 ps
CPU time 130.09 seconds
Started Dec 31 12:59:32 PM PST 23
Finished Dec 31 01:01:43 PM PST 23
Peak memory 193504 kb
Host smart-2c56ac2e-96fd-4461-8cec-5935168b0eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996749626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2996749626
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.85192357
Short name T557
Test name
Test status
Simulation time 48230763635 ps
CPU time 87.01 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:00:40 PM PST 23
Peak memory 182892 kb
Host smart-b4a245b1-2bc4-47c0-98fd-087e72ac24c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85192357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.85192357
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3718488801
Short name T312
Test name
Test status
Simulation time 54632541695 ps
CPU time 18.58 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 12:59:15 PM PST 23
Peak memory 182844 kb
Host smart-60238641-1c1a-4f5d-aec5-c2b6aaffac67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718488801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3718488801
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2872234328
Short name T519
Test name
Test status
Simulation time 714360637054 ps
CPU time 343.2 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:04:45 PM PST 23
Peak memory 182948 kb
Host smart-39cf9f66-c9c9-4d3a-aa05-9fb161166c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872234328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2872234328
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1616512628
Short name T598
Test name
Test status
Simulation time 602220641881 ps
CPU time 788.99 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:12:05 PM PST 23
Peak memory 191056 kb
Host smart-f54fa002-5291-447b-8789-09b4b164b8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616512628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1616512628
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3229464891
Short name T558
Test name
Test status
Simulation time 79054215923 ps
CPU time 539.6 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:07:59 PM PST 23
Peak memory 206104 kb
Host smart-d2210801-877c-4a46-8141-196f8a195364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229464891 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3229464891
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3268854078
Short name T599
Test name
Test status
Simulation time 471526839675 ps
CPU time 237.45 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:03:04 PM PST 23
Peak memory 191140 kb
Host smart-d2507390-706a-49f0-a36b-ccfebaf4f187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268854078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3268854078
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1446618369
Short name T182
Test name
Test status
Simulation time 148197348205 ps
CPU time 128.58 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:01:15 PM PST 23
Peak memory 191092 kb
Host smart-4bc907cd-032a-4707-8c36-7c2f7385bd53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446618369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1446618369
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3195103646
Short name T366
Test name
Test status
Simulation time 662232280199 ps
CPU time 518.13 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:07:56 PM PST 23
Peak memory 191028 kb
Host smart-f191b2c5-2712-414e-a5ad-df34fcde728d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195103646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3195103646
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1371367999
Short name T163
Test name
Test status
Simulation time 37306865200 ps
CPU time 29.48 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 12:59:48 PM PST 23
Peak memory 193740 kb
Host smart-1c86c495-7ee9-4800-aff9-40e76317901a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371367999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1371367999
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.18391875
Short name T206
Test name
Test status
Simulation time 430108212771 ps
CPU time 221.27 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 01:02:37 PM PST 23
Peak memory 191140 kb
Host smart-40985e04-fd80-4ee9-b2d7-f6e103adf7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18391875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.18391875
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2226495519
Short name T167
Test name
Test status
Simulation time 15667404980 ps
CPU time 20.8 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 12:59:32 PM PST 23
Peak memory 182856 kb
Host smart-4b90fbca-5609-4940-8ada-c6b9d9709d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226495519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2226495519
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3125399556
Short name T122
Test name
Test status
Simulation time 13413280979 ps
CPU time 24.66 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 12:59:33 PM PST 23
Peak memory 182928 kb
Host smart-d0c610c5-9d5f-41f8-bbdf-a2157c02d19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125399556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3125399556
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2781204179
Short name T365
Test name
Test status
Simulation time 9142468210 ps
CPU time 74.03 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:00:31 PM PST 23
Peak memory 191008 kb
Host smart-f683a48e-ff0e-4b96-a483-ba9637715d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781204179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2781204179
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1916853908
Short name T584
Test name
Test status
Simulation time 189642250424 ps
CPU time 326.5 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 01:04:22 PM PST 23
Peak memory 182956 kb
Host smart-1ef1c85c-1e44-4c9d-85ab-0e1c6c761424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916853908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1916853908
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.894052134
Short name T546
Test name
Test status
Simulation time 603129395238 ps
CPU time 244.63 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:03:11 PM PST 23
Peak memory 182848 kb
Host smart-3b78a849-9bb9-438c-bdf1-03c45ced5661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894052134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.894052134
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2704786139
Short name T98
Test name
Test status
Simulation time 329386852233 ps
CPU time 104.22 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:00:47 PM PST 23
Peak memory 182960 kb
Host smart-ec990669-c36e-46e0-8a27-384a0c05e2f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704786139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2704786139
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4293070441
Short name T547
Test name
Test status
Simulation time 860208585 ps
CPU time 1.66 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 12:58:55 PM PST 23
Peak memory 182720 kb
Host smart-e2e33118-5408-4abf-b3aa-42c49c448b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293070441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4293070441
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2798731157
Short name T35
Test name
Test status
Simulation time 419692997442 ps
CPU time 375.89 seconds
Started Dec 31 12:59:18 PM PST 23
Finished Dec 31 01:05:38 PM PST 23
Peak memory 193360 kb
Host smart-6fd259d1-315c-4dc8-bb39-8f08642853c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798731157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2798731157
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.4130795047
Short name T588
Test name
Test status
Simulation time 114665292445 ps
CPU time 445.12 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:06:24 PM PST 23
Peak memory 205836 kb
Host smart-e429abed-9e54-447c-a409-e2881ebf7f23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130795047 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.4130795047
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1617377713
Short name T297
Test name
Test status
Simulation time 375251711979 ps
CPU time 192 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:02:15 PM PST 23
Peak memory 191160 kb
Host smart-a164530a-e9c8-431f-8b63-d441522c1cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617377713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1617377713
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4206150976
Short name T275
Test name
Test status
Simulation time 33743979017 ps
CPU time 113.2 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:01:16 PM PST 23
Peak memory 182888 kb
Host smart-f0ab696c-f173-4408-8884-deaaed73737e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206150976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4206150976
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2404204694
Short name T327
Test name
Test status
Simulation time 156968885790 ps
CPU time 147.44 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:01:47 PM PST 23
Peak memory 193396 kb
Host smart-cbfe961f-2b9e-417a-af0c-e14859842611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404204694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2404204694
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2271640712
Short name T136
Test name
Test status
Simulation time 497865660827 ps
CPU time 245.35 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:03:15 PM PST 23
Peak memory 191116 kb
Host smart-566f7534-584d-4d9d-b3a6-84d32154cb5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271640712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2271640712
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2462025242
Short name T184
Test name
Test status
Simulation time 48549986744 ps
CPU time 50.39 seconds
Started Dec 31 12:59:32 PM PST 23
Finished Dec 31 01:00:24 PM PST 23
Peak memory 191160 kb
Host smart-a9be64c4-a3b1-4905-bde1-69f2e6de79e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462025242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2462025242
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3254804293
Short name T320
Test name
Test status
Simulation time 1154280442550 ps
CPU time 1039.73 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:16:32 PM PST 23
Peak memory 182892 kb
Host smart-192ba1ac-e49e-491d-9dc0-f9be0e559229
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254804293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3254804293
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.487435823
Short name T609
Test name
Test status
Simulation time 53318616470 ps
CPU time 84.91 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 01:00:19 PM PST 23
Peak memory 182868 kb
Host smart-1a61cf14-7728-405b-980f-03d82925447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487435823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.487435823
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3883013218
Short name T164
Test name
Test status
Simulation time 882161919966 ps
CPU time 542.78 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:08:25 PM PST 23
Peak memory 194188 kb
Host smart-36c32893-bcb4-42f1-98bd-9d3e14b7708e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883013218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3883013218
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.473194088
Short name T165
Test name
Test status
Simulation time 69759989185 ps
CPU time 121.54 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:00:58 PM PST 23
Peak memory 182856 kb
Host smart-9fd4b53e-1a59-440b-af02-eccc10050815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473194088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.473194088
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2148606388
Short name T596
Test name
Test status
Simulation time 33763240 ps
CPU time 0.59 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 12:59:18 PM PST 23
Peak memory 182520 kb
Host smart-289677ed-8be6-4d7c-b3d7-00f9ab40d345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148606388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2148606388
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3782288886
Short name T541
Test name
Test status
Simulation time 124213289164 ps
CPU time 1042.45 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:16:39 PM PST 23
Peak memory 213696 kb
Host smart-6524fda1-d524-464e-bbe6-c2203fac5bf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782288886 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3782288886
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.838152446
Short name T148
Test name
Test status
Simulation time 176343391024 ps
CPU time 960.65 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:15:20 PM PST 23
Peak memory 194412 kb
Host smart-a492be10-cab8-49c9-8f3d-1e7762160055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838152446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.838152446
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1473666810
Short name T362
Test name
Test status
Simulation time 100817706701 ps
CPU time 159.39 seconds
Started Dec 31 12:59:31 PM PST 23
Finished Dec 31 01:02:11 PM PST 23
Peak memory 193708 kb
Host smart-e8fd2338-6588-494e-ab34-0ee5b66360a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473666810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1473666810
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.379869919
Short name T282
Test name
Test status
Simulation time 30159787781 ps
CPU time 35.12 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 12:59:52 PM PST 23
Peak memory 182788 kb
Host smart-bb760f75-ab17-4411-9230-866d419bd515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379869919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.379869919
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.586062493
Short name T304
Test name
Test status
Simulation time 168556761029 ps
CPU time 209.81 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:02:29 PM PST 23
Peak memory 191136 kb
Host smart-48317154-43bb-4295-bda5-f707a71690aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586062493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.586062493
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3048990149
Short name T26
Test name
Test status
Simulation time 22869638387 ps
CPU time 23.43 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 12:59:47 PM PST 23
Peak memory 182852 kb
Host smart-7026f354-c765-4291-b651-b9e66fa1943e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048990149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3048990149
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1905815133
Short name T175
Test name
Test status
Simulation time 1435645439223 ps
CPU time 1042.54 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:16:43 PM PST 23
Peak memory 191036 kb
Host smart-40e2905d-6acd-487d-a0dd-510d53289524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905815133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1905815133
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1762075044
Short name T542
Test name
Test status
Simulation time 128539653730 ps
CPU time 189.5 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 01:02:23 PM PST 23
Peak memory 182896 kb
Host smart-3c2f6cfb-4d18-47b8-9997-74b2b40bff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762075044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1762075044
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1969133830
Short name T512
Test name
Test status
Simulation time 138704544 ps
CPU time 0.7 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 12:59:07 PM PST 23
Peak memory 182272 kb
Host smart-3fa226bb-b9fb-4d35-a6cb-1a4d95f2bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969133830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1969133830
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1979861322
Short name T173
Test name
Test status
Simulation time 182481787599 ps
CPU time 1920.07 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:31:06 PM PST 23
Peak memory 191096 kb
Host smart-f71553ea-786c-4cfe-bc7e-1f7433ccdca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979861322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1979861322
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3324067773
Short name T612
Test name
Test status
Simulation time 281653794529 ps
CPU time 1065.91 seconds
Started Dec 31 12:58:48 PM PST 23
Finished Dec 31 01:16:41 PM PST 23
Peak memory 209964 kb
Host smart-a3333b0b-3bac-4632-980e-ccb25b18799d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324067773 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3324067773
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.934187035
Short name T240
Test name
Test status
Simulation time 297812566631 ps
CPU time 174.92 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:02:22 PM PST 23
Peak memory 193792 kb
Host smart-275439b3-926e-4c99-bbc3-d7deba17bb74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934187035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.934187035
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1281620861
Short name T61
Test name
Test status
Simulation time 445058851654 ps
CPU time 209.37 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:02:43 PM PST 23
Peak memory 193216 kb
Host smart-5a949811-28c3-40bc-9eb7-01fa2ebe7e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281620861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1281620861
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1121091064
Short name T248
Test name
Test status
Simulation time 350809420346 ps
CPU time 135.22 seconds
Started Dec 31 12:59:23 PM PST 23
Finished Dec 31 01:01:41 PM PST 23
Peak memory 194036 kb
Host smart-eed5c793-252e-4d3c-936d-f3fbb5b3233c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121091064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1121091064
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.585240210
Short name T119
Test name
Test status
Simulation time 398143056675 ps
CPU time 703.91 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:11:03 PM PST 23
Peak memory 191200 kb
Host smart-8a2e19aa-6df4-4910-a8c7-c0bf8fde2dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585240210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.585240210
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3459881992
Short name T334
Test name
Test status
Simulation time 29791869165 ps
CPU time 66.23 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:00:18 PM PST 23
Peak memory 182892 kb
Host smart-c0b22e43-8850-4bf6-a11e-c3872db09b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459881992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3459881992
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.554141752
Short name T50
Test name
Test status
Simulation time 952274670887 ps
CPU time 258.81 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:03:35 PM PST 23
Peak memory 193112 kb
Host smart-5b11b686-cc80-488f-90f9-cc28ee29ce2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554141752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.554141752
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3699305738
Short name T344
Test name
Test status
Simulation time 48547875684 ps
CPU time 82.33 seconds
Started Dec 31 12:59:21 PM PST 23
Finished Dec 31 01:00:47 PM PST 23
Peak memory 182972 kb
Host smart-447693f4-bc49-4b6a-bd8d-b8df5edf90dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699305738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3699305738
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3882303427
Short name T321
Test name
Test status
Simulation time 1802295461993 ps
CPU time 624.25 seconds
Started Dec 31 12:59:28 PM PST 23
Finished Dec 31 01:09:53 PM PST 23
Peak memory 191176 kb
Host smart-9b27cd09-28b1-428a-ae57-53be3e91a55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882303427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3882303427
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1351266043
Short name T307
Test name
Test status
Simulation time 394790339783 ps
CPU time 1001.58 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:16:01 PM PST 23
Peak memory 191172 kb
Host smart-631532b8-2797-40a2-a912-bea8a0a765bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351266043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1351266043
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4065199044
Short name T363
Test name
Test status
Simulation time 1041524913141 ps
CPU time 584.77 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:08:58 PM PST 23
Peak memory 182860 kb
Host smart-31b3e3d6-38dd-4818-b60a-9636f80422b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065199044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4065199044
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3293757608
Short name T258
Test name
Test status
Simulation time 28280080094 ps
CPU time 44.54 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:00:02 PM PST 23
Peak memory 182832 kb
Host smart-d4f7707f-84dc-4175-9d50-7102a0543881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293757608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3293757608
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1704614692
Short name T610
Test name
Test status
Simulation time 1597296917189 ps
CPU time 467.16 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:06:46 PM PST 23
Peak memory 191308 kb
Host smart-6baaff0a-00e3-4559-9436-0ba53390325a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704614692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1704614692
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3574115409
Short name T575
Test name
Test status
Simulation time 49407864118 ps
CPU time 411.6 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:06:06 PM PST 23
Peak memory 197508 kb
Host smart-b1db46d6-ad79-4431-98bc-66c7fbe57902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574115409 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3574115409
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3017640524
Short name T277
Test name
Test status
Simulation time 77642199781 ps
CPU time 126.4 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:01:30 PM PST 23
Peak memory 191144 kb
Host smart-541014d6-fce7-4773-a2f1-70fda5fb794f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017640524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3017640524
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3315112530
Short name T262
Test name
Test status
Simulation time 63136628873 ps
CPU time 22.64 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 12:59:41 PM PST 23
Peak memory 182768 kb
Host smart-89b39549-1d1c-4c3f-b896-84f85ba682f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315112530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3315112530
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3648625221
Short name T591
Test name
Test status
Simulation time 187119445449 ps
CPU time 183.34 seconds
Started Dec 31 12:59:24 PM PST 23
Finished Dec 31 01:02:30 PM PST 23
Peak memory 192320 kb
Host smart-9969bc76-5115-4f50-b2cf-6ae8730c22d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648625221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3648625221
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3038967150
Short name T342
Test name
Test status
Simulation time 32407811407 ps
CPU time 58.8 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:00:19 PM PST 23
Peak memory 182784 kb
Host smart-74365f05-a7bd-4880-a267-36d64701dc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038967150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3038967150
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1295191600
Short name T118
Test name
Test status
Simulation time 470848209482 ps
CPU time 446.48 seconds
Started Dec 31 12:59:32 PM PST 23
Finished Dec 31 01:07:00 PM PST 23
Peak memory 191084 kb
Host smart-f137d231-5853-46c9-ae07-598a6236da7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295191600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1295191600
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.671983564
Short name T208
Test name
Test status
Simulation time 257489620966 ps
CPU time 463.95 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:07:05 PM PST 23
Peak memory 182924 kb
Host smart-899cbc5a-d12e-4426-912f-cb0ed37288be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671983564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.671983564
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4294028544
Short name T40
Test name
Test status
Simulation time 53953074286 ps
CPU time 79.7 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:00:32 PM PST 23
Peak memory 182928 kb
Host smart-ed502d67-b219-4987-8e84-c26c246f20fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294028544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4294028544
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1055385991
Short name T5
Test name
Test status
Simulation time 99188865 ps
CPU time 0.55 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 12:59:10 PM PST 23
Peak memory 182384 kb
Host smart-c27a48c0-93b2-46d7-b9bc-557008e0af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055385991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1055385991
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.198122425
Short name T38
Test name
Test status
Simulation time 571054052428 ps
CPU time 292.29 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:03:49 PM PST 23
Peak memory 205840 kb
Host smart-84763c03-86dc-40d7-a6dc-7a5810dcd6e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198122425 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.198122425
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3591151415
Short name T121
Test name
Test status
Simulation time 30180306053 ps
CPU time 21.36 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 12:59:45 PM PST 23
Peak memory 182672 kb
Host smart-3e14ad47-678d-46a0-a709-6f4d9ab33d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591151415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3591151415
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3317521898
Short name T213
Test name
Test status
Simulation time 152117251665 ps
CPU time 276.69 seconds
Started Dec 31 12:59:23 PM PST 23
Finished Dec 31 01:04:03 PM PST 23
Peak memory 193752 kb
Host smart-0caa39d3-68f8-48f8-b59e-97ee3987fb0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317521898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3317521898
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3484098139
Short name T288
Test name
Test status
Simulation time 87910240632 ps
CPU time 141.72 seconds
Started Dec 31 12:59:34 PM PST 23
Finished Dec 31 01:01:57 PM PST 23
Peak memory 191112 kb
Host smart-9a293823-8e8d-4645-a1c4-b77b11a24081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484098139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3484098139
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1774245532
Short name T201
Test name
Test status
Simulation time 419080424764 ps
CPU time 627.12 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 191144 kb
Host smart-313cac3d-50aa-4cef-adfe-227f85f48ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774245532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1774245532
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3353210533
Short name T239
Test name
Test status
Simulation time 91851564280 ps
CPU time 172.82 seconds
Started Dec 31 12:59:35 PM PST 23
Finished Dec 31 01:02:29 PM PST 23
Peak memory 191172 kb
Host smart-928e0255-2795-483f-838c-9ec4d6b7487a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353210533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3353210533
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2289098515
Short name T349
Test name
Test status
Simulation time 36798993722 ps
CPU time 61.27 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:00:28 PM PST 23
Peak memory 182996 kb
Host smart-d8c8a52a-300b-4e13-aabf-ae0cf296a4a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289098515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2289098515
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2408279593
Short name T271
Test name
Test status
Simulation time 347438551173 ps
CPU time 1101.77 seconds
Started Dec 31 12:59:28 PM PST 23
Finished Dec 31 01:17:51 PM PST 23
Peak memory 190984 kb
Host smart-5cd35b3b-d9cc-431b-9f81-c9662c94baa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408279593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2408279593
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3677761016
Short name T229
Test name
Test status
Simulation time 6205722977 ps
CPU time 10.89 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 12:59:04 PM PST 23
Peak memory 182856 kb
Host smart-50c63412-5153-4f7f-b0b5-97b6a126be43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677761016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3677761016
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3625967615
Short name T500
Test name
Test status
Simulation time 112689920545 ps
CPU time 151.18 seconds
Started Dec 31 12:59:34 PM PST 23
Finished Dec 31 01:02:07 PM PST 23
Peak memory 182960 kb
Host smart-30b19de2-4136-4686-bc3f-ace96f65fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625967615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3625967615
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3450947875
Short name T274
Test name
Test status
Simulation time 35607596815 ps
CPU time 52.51 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 12:59:49 PM PST 23
Peak memory 182980 kb
Host smart-02a824a3-f700-490e-8fee-50f700656636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450947875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3450947875
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1753980776
Short name T315
Test name
Test status
Simulation time 50601016314 ps
CPU time 44.67 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 12:59:41 PM PST 23
Peak memory 182896 kb
Host smart-ba1a216d-e1ed-4805-ae8a-223f4a2fa399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753980776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1753980776
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3273292700
Short name T16
Test name
Test status
Simulation time 88495320 ps
CPU time 0.87 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 12:59:08 PM PST 23
Peak memory 213620 kb
Host smart-fe913da3-6c32-4e81-b138-4c657cd22783
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273292700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3273292700
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2004835677
Short name T559
Test name
Test status
Simulation time 28255777691 ps
CPU time 217.44 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:02:48 PM PST 23
Peak memory 205768 kb
Host smart-d5498f15-f43b-4b16-8895-768e828e1f23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004835677 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2004835677
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1839906285
Short name T51
Test name
Test status
Simulation time 60585440651 ps
CPU time 96.85 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 01:00:39 PM PST 23
Peak memory 182944 kb
Host smart-8d04cbc6-a163-436f-9754-7ec34b069888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839906285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1839906285
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.470026044
Short name T190
Test name
Test status
Simulation time 171830379921 ps
CPU time 140.83 seconds
Started Dec 31 12:58:44 PM PST 23
Finished Dec 31 01:01:12 PM PST 23
Peak memory 191108 kb
Host smart-8d38ea70-e96a-416c-8e2c-b2f3d27f1f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470026044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.470026044
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.645611976
Short name T228
Test name
Test status
Simulation time 32665360235 ps
CPU time 15.99 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 12:59:29 PM PST 23
Peak memory 194736 kb
Host smart-c7f4555f-c4ce-4e62-ac00-683d346fc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645611976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.645611976
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1054711714
Short name T525
Test name
Test status
Simulation time 120111977485 ps
CPU time 1044.49 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 207804 kb
Host smart-1e3a6dad-fc39-4c57-be92-967ed8e64c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054711714 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1054711714
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.272520600
Short name T207
Test name
Test status
Simulation time 315949559946 ps
CPU time 282.16 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:04:01 PM PST 23
Peak memory 182848 kb
Host smart-047890bd-104b-44dc-a994-3a2d0068bd59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272520600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.272520600
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1747734312
Short name T617
Test name
Test status
Simulation time 79079447631 ps
CPU time 33.76 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 12:59:49 PM PST 23
Peak memory 182824 kb
Host smart-0b7a251c-11ec-4152-a950-9a9b57b24483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747734312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1747734312
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1779253261
Short name T194
Test name
Test status
Simulation time 44015491267 ps
CPU time 103.81 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:01:01 PM PST 23
Peak memory 182892 kb
Host smart-96a05278-259d-4900-b95b-3157287d4159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779253261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1779253261
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3032968553
Short name T607
Test name
Test status
Simulation time 80566665442 ps
CPU time 123.35 seconds
Started Dec 31 12:59:21 PM PST 23
Finished Dec 31 01:01:28 PM PST 23
Peak memory 182716 kb
Host smart-8981f649-ec69-4018-b265-02cb8a1db593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032968553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3032968553
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.2092089771
Short name T279
Test name
Test status
Simulation time 92580225826 ps
CPU time 845.04 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:13:12 PM PST 23
Peak memory 205860 kb
Host smart-e93c1ba0-18a8-4081-b131-a4082b403c9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092089771 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.2092089771
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3426698348
Short name T509
Test name
Test status
Simulation time 97391670065 ps
CPU time 146.13 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:01:33 PM PST 23
Peak memory 182852 kb
Host smart-155f2266-0645-493e-bf00-e92acbac572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426698348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3426698348
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3005266260
Short name T225
Test name
Test status
Simulation time 253929491083 ps
CPU time 124.01 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:01:09 PM PST 23
Peak memory 191100 kb
Host smart-499c08ab-77b1-467f-895d-54ee4e998b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005266260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3005266260
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3350113045
Short name T358
Test name
Test status
Simulation time 17066915117 ps
CPU time 15.4 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 12:59:09 PM PST 23
Peak memory 182948 kb
Host smart-11774599-4ad2-47fb-b7e9-be89850f8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350113045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3350113045
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.114378288
Short name T567
Test name
Test status
Simulation time 60325730974 ps
CPU time 293.49 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:03:54 PM PST 23
Peak memory 197684 kb
Host smart-bbb94812-9265-4403-ba4b-544470d5b506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114378288 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.114378288
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1218080817
Short name T39
Test name
Test status
Simulation time 1149172668909 ps
CPU time 1038.09 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 01:16:13 PM PST 23
Peak memory 182888 kb
Host smart-439e9687-1e42-4abe-8c35-c1ff5534630d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218080817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1218080817
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2124212362
Short name T604
Test name
Test status
Simulation time 301832200862 ps
CPU time 245.84 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:03:18 PM PST 23
Peak memory 183004 kb
Host smart-8804c484-fe1f-4d39-9318-c8b52813d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124212362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2124212362
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2758558794
Short name T303
Test name
Test status
Simulation time 106391573766 ps
CPU time 114.42 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:01:11 PM PST 23
Peak memory 191140 kb
Host smart-01bc8e06-c855-4808-8e02-0e351d87ebff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758558794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2758558794
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3771902898
Short name T555
Test name
Test status
Simulation time 92560147203 ps
CPU time 349.01 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:05:03 PM PST 23
Peak memory 182980 kb
Host smart-5b36b7c4-0c7f-4ba1-b55f-3f836f3c6aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771902898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3771902898
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.904552844
Short name T276
Test name
Test status
Simulation time 52941492302 ps
CPU time 600.34 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:09:09 PM PST 23
Peak memory 205884 kb
Host smart-a76ccf54-5b3e-44b5-a1b2-c47b3994dacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904552844 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.904552844
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1150657771
Short name T531
Test name
Test status
Simulation time 63218117526 ps
CPU time 103.63 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:00:52 PM PST 23
Peak memory 182928 kb
Host smart-687b8259-bbd4-4197-9fa1-8a2a7c504706
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150657771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1150657771
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4291476314
Short name T513
Test name
Test status
Simulation time 154066828792 ps
CPU time 60.78 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:00:04 PM PST 23
Peak memory 182884 kb
Host smart-4043978d-a46a-4784-a448-47231ae9465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291476314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4291476314
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.4267260738
Short name T331
Test name
Test status
Simulation time 74582467026 ps
CPU time 123.17 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:01:11 PM PST 23
Peak memory 191104 kb
Host smart-1ebf6cef-9585-4fde-81de-87a361abde94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267260738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4267260738
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3837588645
Short name T153
Test name
Test status
Simulation time 372422656637 ps
CPU time 151.97 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:01:45 PM PST 23
Peak memory 194036 kb
Host smart-08d7d07b-0d17-4d95-a46d-cdc8e96f4fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837588645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3837588645
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.412217159
Short name T188
Test name
Test status
Simulation time 124687898666 ps
CPU time 917.51 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:14:25 PM PST 23
Peak memory 207196 kb
Host smart-04f85d44-87ca-4f98-b4c4-83e2b71c1197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412217159 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.412217159
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.114827720
Short name T528
Test name
Test status
Simulation time 140432422166 ps
CPU time 191.59 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:02:10 PM PST 23
Peak memory 182988 kb
Host smart-a27fadfa-c05b-482a-9610-189fd0c744b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114827720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.114827720
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.29141415
Short name T246
Test name
Test status
Simulation time 101797924112 ps
CPU time 272.95 seconds
Started Dec 31 12:58:43 PM PST 23
Finished Dec 31 01:03:21 PM PST 23
Peak memory 191188 kb
Host smart-9fa315de-c765-44b3-bbcd-44f49eec6d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.29141415
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2620264766
Short name T545
Test name
Test status
Simulation time 67505102 ps
CPU time 0.61 seconds
Started Dec 31 12:58:57 PM PST 23
Finished Dec 31 12:59:04 PM PST 23
Peak memory 182396 kb
Host smart-b713eba1-5584-4a14-8b54-b329dd3a16ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620264766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2620264766
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1839374245
Short name T290
Test name
Test status
Simulation time 2642277518577 ps
CPU time 2161.05 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:35:08 PM PST 23
Peak memory 191204 kb
Host smart-e37d5974-f8ec-410a-8bab-8351199c8285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839374245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1839374245
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2279296643
Short name T37
Test name
Test status
Simulation time 27551531576 ps
CPU time 477.76 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:07:05 PM PST 23
Peak memory 205748 kb
Host smart-165cfe5f-9e6b-4de6-969a-bb64dc21d7f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279296643 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.2279296643
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3841865910
Short name T538
Test name
Test status
Simulation time 67780779513 ps
CPU time 53.59 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:00:06 PM PST 23
Peak memory 182916 kb
Host smart-f1adc55a-d0e3-409f-89ca-7f4bda6edb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841865910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3841865910
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.421503521
Short name T309
Test name
Test status
Simulation time 70821763749 ps
CPU time 123.68 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 01:01:05 PM PST 23
Peak memory 193612 kb
Host smart-79180702-0857-49e3-a6b8-496cd7a20962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421503521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.421503521
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.54594846
Short name T56
Test name
Test status
Simulation time 273800330148 ps
CPU time 207.78 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 01:02:23 PM PST 23
Peak memory 191180 kb
Host smart-e6bb7700-ba21-41c8-8eb7-01c16311c2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54594846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.54594846
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2933296194
Short name T587
Test name
Test status
Simulation time 73590391549 ps
CPU time 416.66 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:06:09 PM PST 23
Peak memory 205868 kb
Host smart-6039604e-996c-40bd-b57e-9ec39ba1b6f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933296194 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2933296194
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1812605710
Short name T602
Test name
Test status
Simulation time 10431035077 ps
CPU time 19.37 seconds
Started Dec 31 12:58:45 PM PST 23
Finished Dec 31 12:59:12 PM PST 23
Peak memory 182856 kb
Host smart-5e6e9a8e-53f1-48f2-9eb9-9e8c74b2dee1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812605710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1812605710
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.542264343
Short name T554
Test name
Test status
Simulation time 595686264024 ps
CPU time 236.07 seconds
Started Dec 31 12:58:45 PM PST 23
Finished Dec 31 01:02:49 PM PST 23
Peak memory 182996 kb
Host smart-f28c45a8-ec2c-4537-9564-e330f478ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542264343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.542264343
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2026360937
Short name T572
Test name
Test status
Simulation time 833803848640 ps
CPU time 203.61 seconds
Started Dec 31 12:58:43 PM PST 23
Finished Dec 31 01:02:16 PM PST 23
Peak memory 193220 kb
Host smart-d2b5d664-9e2f-4f29-82a9-33edd8de6d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026360937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2026360937
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2512805187
Short name T577
Test name
Test status
Simulation time 17773129 ps
CPU time 0.56 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 12:59:17 PM PST 23
Peak memory 182260 kb
Host smart-a2188a99-df39-47b2-86d3-b3a03983e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512805187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2512805187
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1984366904
Short name T574
Test name
Test status
Simulation time 177543714024 ps
CPU time 255 seconds
Started Dec 31 12:58:41 PM PST 23
Finished Dec 31 01:03:02 PM PST 23
Peak memory 191168 kb
Host smart-39585d8f-98a7-469e-9fed-05e373aa7472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984366904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1984366904
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.142976184
Short name T265
Test name
Test status
Simulation time 175127648846 ps
CPU time 301.17 seconds
Started Dec 31 12:59:18 PM PST 23
Finished Dec 31 01:04:23 PM PST 23
Peak memory 182780 kb
Host smart-05e45c5b-fb2c-4a38-86d1-5f2578e4d64d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142976184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.142976184
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.4060009727
Short name T548
Test name
Test status
Simulation time 185971703678 ps
CPU time 65.67 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:00:02 PM PST 23
Peak memory 182888 kb
Host smart-aa87b853-cc9f-48cc-873d-c1f0448bcb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060009727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.4060009727
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2939330655
Short name T189
Test name
Test status
Simulation time 140385620257 ps
CPU time 287.93 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:04:02 PM PST 23
Peak memory 191084 kb
Host smart-1ed4a7cf-8f85-4f2f-a58a-3668629fa454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939330655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2939330655
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3176306973
Short name T144
Test name
Test status
Simulation time 123151728687 ps
CPU time 115.92 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:00:55 PM PST 23
Peak memory 182948 kb
Host smart-0bf5d975-af55-45cd-9652-2565663d4a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176306973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3176306973
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3478036307
Short name T516
Test name
Test status
Simulation time 96768410172 ps
CPU time 374.59 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:05:15 PM PST 23
Peak memory 206744 kb
Host smart-f6a13b06-992e-4025-a5a4-5092becbd6bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478036307 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3478036307
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1081584991
Short name T287
Test name
Test status
Simulation time 197774310235 ps
CPU time 106.17 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 01:01:00 PM PST 23
Peak memory 182860 kb
Host smart-78e71f86-5ca4-40bf-a87d-0bcf0a76418e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081584991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1081584991
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2801907542
Short name T527
Test name
Test status
Simulation time 172193531499 ps
CPU time 280.94 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 01:03:37 PM PST 23
Peak memory 182848 kb
Host smart-161f5818-4e72-4336-add8-4aff38f8e239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801907542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2801907542
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3702449890
Short name T336
Test name
Test status
Simulation time 87577772367 ps
CPU time 72.41 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 01:00:23 PM PST 23
Peak memory 182856 kb
Host smart-73e62ebf-c15e-42c0-8584-364cecc19f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702449890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3702449890
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.879751760
Short name T235
Test name
Test status
Simulation time 468149854229 ps
CPU time 265.81 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:03:35 PM PST 23
Peak memory 182924 kb
Host smart-ab9ab194-f6a7-4694-94ec-2a1f6cab65c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879751760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.879751760
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1895137407
Short name T520
Test name
Test status
Simulation time 54441480472 ps
CPU time 46.2 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:00:01 PM PST 23
Peak memory 182892 kb
Host smart-0bb3decc-28ae-4e24-b54a-7197bc4f0d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895137407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1895137407
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1569232956
Short name T578
Test name
Test status
Simulation time 148321757159 ps
CPU time 70.89 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 01:00:24 PM PST 23
Peak memory 182920 kb
Host smart-57ef80e8-06bf-47df-9b1b-0f69ae325d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569232956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1569232956
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3837356775
Short name T561
Test name
Test status
Simulation time 46960319541 ps
CPU time 39.08 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 12:59:49 PM PST 23
Peak memory 194304 kb
Host smart-78a8e8a6-a75f-48bc-bcf0-d567b216e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837356775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3837356775
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3751178430
Short name T20
Test name
Test status
Simulation time 75440548 ps
CPU time 0.74 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 12:58:57 PM PST 23
Peak memory 212756 kb
Host smart-a0da270f-3f59-4d8e-9a7a-4cbe12c1dede
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751178430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3751178430
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1275622348
Short name T140
Test name
Test status
Simulation time 260579564018 ps
CPU time 620.41 seconds
Started Dec 31 12:58:48 PM PST 23
Finished Dec 31 01:09:14 PM PST 23
Peak memory 191056 kb
Host smart-cdd21d39-c91c-4538-966f-7890d2b66c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275622348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1275622348
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_random.2623907128
Short name T117
Test name
Test status
Simulation time 134489171083 ps
CPU time 165.59 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:02:00 PM PST 23
Peak memory 194228 kb
Host smart-2ea2f606-9157-4c4f-bb93-62191f37fae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623907128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2623907128
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.417379699
Short name T335
Test name
Test status
Simulation time 86159219160 ps
CPU time 100.32 seconds
Started Dec 31 12:58:40 PM PST 23
Finished Dec 31 01:00:27 PM PST 23
Peak memory 191200 kb
Host smart-2ea94d60-cafb-440f-bac1-be6bb0b4fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417379699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.417379699
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.3274991901
Short name T351
Test name
Test status
Simulation time 258649798321 ps
CPU time 734.15 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 211548 kb
Host smart-a00448d5-134d-452a-bf89-9ec6812f981b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274991901 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.3274991901
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2565885405
Short name T518
Test name
Test status
Simulation time 519640535067 ps
CPU time 187.61 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:02:22 PM PST 23
Peak memory 182956 kb
Host smart-43f36f8d-cd85-4b69-be83-4cd3c41ddb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565885405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2565885405
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3260393106
Short name T252
Test name
Test status
Simulation time 85452162233 ps
CPU time 775.58 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 194388 kb
Host smart-76a6376d-2dcf-4881-beb8-d67b1aef31c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260393106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3260393106
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3269741822
Short name T563
Test name
Test status
Simulation time 25706305 ps
CPU time 0.57 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 12:59:19 PM PST 23
Peak memory 182360 kb
Host smart-8845dd40-e8b8-4fff-87a0-ec3d5c450997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269741822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3269741822
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1408727331
Short name T11
Test name
Test status
Simulation time 493892268815 ps
CPU time 997.73 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:15:59 PM PST 23
Peak memory 211460 kb
Host smart-9d07746b-51c9-4506-8e4b-31c216cfddaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408727331 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.1408727331
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2547698695
Short name T236
Test name
Test status
Simulation time 269217354478 ps
CPU time 303.29 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:04:18 PM PST 23
Peak memory 182936 kb
Host smart-0074dbce-33b6-40bf-8cf1-de72649d6b2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547698695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2547698695
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2144486824
Short name T543
Test name
Test status
Simulation time 11812059277 ps
CPU time 20.13 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 12:59:21 PM PST 23
Peak memory 182900 kb
Host smart-8c04c7d2-3aff-4be5-9efc-f255445e9be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144486824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2144486824
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4250834788
Short name T592
Test name
Test status
Simulation time 54214049329 ps
CPU time 67.87 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:00:07 PM PST 23
Peak memory 182896 kb
Host smart-9ce1f2f8-9135-43a6-a7d2-236d8b3685ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250834788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4250834788
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.691774044
Short name T313
Test name
Test status
Simulation time 131159961484 ps
CPU time 419.25 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 01:05:53 PM PST 23
Peak memory 191148 kb
Host smart-a6c65db9-720e-4669-9436-e99b8451b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691774044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.691774044
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4155703168
Short name T585
Test name
Test status
Simulation time 359704811153 ps
CPU time 698.58 seconds
Started Dec 31 12:58:57 PM PST 23
Finished Dec 31 01:10:47 PM PST 23
Peak memory 191060 kb
Host smart-f21fbe9a-a0bf-4ec4-ab6f-efaccf8ad374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155703168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4155703168
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1995216008
Short name T537
Test name
Test status
Simulation time 87338090277 ps
CPU time 171.94 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:01:50 PM PST 23
Peak memory 205904 kb
Host smart-617cb2bb-0a5a-423b-89f1-2da19fd1d84a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995216008 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1995216008
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4163122189
Short name T345
Test name
Test status
Simulation time 344628942437 ps
CPU time 537.56 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:07:57 PM PST 23
Peak memory 182868 kb
Host smart-72a3949b-de9a-4572-9eaf-caaa5e4b2e49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163122189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.4163122189
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2503153612
Short name T550
Test name
Test status
Simulation time 174254414297 ps
CPU time 65.67 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 12:59:59 PM PST 23
Peak memory 182960 kb
Host smart-847e264c-5077-495d-9601-29360d4fe394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503153612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2503153612
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2962997300
Short name T586
Test name
Test status
Simulation time 284598900315 ps
CPU time 143.52 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:01:39 PM PST 23
Peak memory 191196 kb
Host smart-06bd0409-8ebc-4fd3-848e-f8abb050f646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962997300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2962997300
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2717784795
Short name T99
Test name
Test status
Simulation time 54642772530 ps
CPU time 19.88 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 12:59:13 PM PST 23
Peak memory 182892 kb
Host smart-657458a0-2c64-41e4-bb64-2eefbbe3d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717784795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2717784795
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2860084596
Short name T100
Test name
Test status
Simulation time 3611098686077 ps
CPU time 1140.35 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:18:18 PM PST 23
Peak memory 182928 kb
Host smart-5d93c870-7e6f-43c5-a8bd-770a6fc0f54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860084596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2860084596
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1859805557
Short name T494
Test name
Test status
Simulation time 137816145459 ps
CPU time 299.83 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 01:03:54 PM PST 23
Peak memory 210028 kb
Host smart-d513909f-ce8b-4e6b-88ea-487a4f0e4e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859805557 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1859805557
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2299915379
Short name T244
Test name
Test status
Simulation time 169674417306 ps
CPU time 285.88 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:03:43 PM PST 23
Peak memory 183172 kb
Host smart-a0c30ed7-7e23-4b08-b154-31f80be542b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299915379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2299915379
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1450286603
Short name T493
Test name
Test status
Simulation time 27846078766 ps
CPU time 20.25 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 12:59:14 PM PST 23
Peak memory 182860 kb
Host smart-42d7c2ec-088a-4bbf-bd1c-595f79a2f5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450286603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1450286603
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2251831133
Short name T328
Test name
Test status
Simulation time 100959968527 ps
CPU time 50.13 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 12:59:52 PM PST 23
Peak memory 194916 kb
Host smart-d2909bde-6169-40cf-8843-88e844723ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251831133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2251831133
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.569414046
Short name T161
Test name
Test status
Simulation time 147355845230 ps
CPU time 164.21 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:01:49 PM PST 23
Peak memory 193736 kb
Host smart-b8a58a40-bc10-4695-a284-b5b4374ab040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569414046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
569414046
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3830278663
Short name T299
Test name
Test status
Simulation time 696310789626 ps
CPU time 748.63 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 207688 kb
Host smart-77d46c55-38ee-4dbc-94bd-dc55d8032694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830278663 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3830278663
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1467286529
Short name T22
Test name
Test status
Simulation time 324971696410 ps
CPU time 135.29 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 01:01:27 PM PST 23
Peak memory 182864 kb
Host smart-30f67756-14b2-4209-aed5-ead2ab67b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467286529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1467286529
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.303356381
Short name T343
Test name
Test status
Simulation time 45468308372 ps
CPU time 100.23 seconds
Started Dec 31 12:58:43 PM PST 23
Finished Dec 31 01:00:28 PM PST 23
Peak memory 191124 kb
Host smart-8e7739f3-3df5-4de3-b0df-794774327a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303356381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.303356381
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2437442015
Short name T107
Test name
Test status
Simulation time 210096751128 ps
CPU time 162.01 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:01:40 PM PST 23
Peak memory 191184 kb
Host smart-6edb2796-8d45-4d42-b703-97325c81a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437442015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2437442015
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.812756256
Short name T141
Test name
Test status
Simulation time 226451853943 ps
CPU time 413.74 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:06:00 PM PST 23
Peak memory 191140 kb
Host smart-3b1f7b6d-51cb-4336-82ee-45630bf90240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812756256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
812756256
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.694200782
Short name T285
Test name
Test status
Simulation time 194472366609 ps
CPU time 646.04 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:10:03 PM PST 23
Peak memory 205912 kb
Host smart-185bfb04-02c3-40ef-8fc8-db2e37041149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694200782 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.694200782
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.876625378
Short name T21
Test name
Test status
Simulation time 443661152495 ps
CPU time 443.39 seconds
Started Dec 31 12:58:47 PM PST 23
Finished Dec 31 01:06:17 PM PST 23
Peak memory 182852 kb
Host smart-b0e710d8-2bf5-4458-a956-1cec6953f265
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876625378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.876625378
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1345665673
Short name T566
Test name
Test status
Simulation time 934457598239 ps
CPU time 161 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:01:49 PM PST 23
Peak memory 182864 kb
Host smart-740ec171-a809-4764-9e90-e26dfa535cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345665673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1345665673
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1058719402
Short name T145
Test name
Test status
Simulation time 70955363211 ps
CPU time 260.76 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:03:23 PM PST 23
Peak memory 191144 kb
Host smart-02b071b3-6e7d-47e7-b0c5-aac5063d8779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058719402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1058719402
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2413286901
Short name T317
Test name
Test status
Simulation time 27823046213 ps
CPU time 45.57 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:00:03 PM PST 23
Peak memory 182948 kb
Host smart-e1a06bda-8b6d-49a7-8b26-0527e434c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413286901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2413286901
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.806965841
Short name T96
Test name
Test status
Simulation time 2978262856788 ps
CPU time 2067.16 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 01:33:23 PM PST 23
Peak memory 191048 kb
Host smart-b6f8bd53-631f-49e3-9712-6f16699ec5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806965841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
806965841
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.706239970
Short name T595
Test name
Test status
Simulation time 13980132512 ps
CPU time 15.52 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 12:59:31 PM PST 23
Peak memory 197500 kb
Host smart-76d19072-1be5-47a8-a391-1100b38addfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706239970 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.706239970
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3993278984
Short name T24
Test name
Test status
Simulation time 65394676013 ps
CPU time 120.2 seconds
Started Dec 31 12:59:05 PM PST 23
Finished Dec 31 01:01:12 PM PST 23
Peak memory 182932 kb
Host smart-ce75ea37-96f7-4a8e-9997-e891d4f71374
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993278984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3993278984
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1597994538
Short name T601
Test name
Test status
Simulation time 92276089945 ps
CPU time 145.97 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 01:01:28 PM PST 23
Peak memory 183008 kb
Host smart-da7d0c40-0558-489c-be1c-cad2ec1facee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597994538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1597994538
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1672281996
Short name T154
Test name
Test status
Simulation time 157050814094 ps
CPU time 143.93 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 01:01:26 PM PST 23
Peak memory 191088 kb
Host smart-83832b85-1333-40d5-b046-f5c7ef4ee446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672281996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1672281996
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3813729688
Short name T616
Test name
Test status
Simulation time 46137463658 ps
CPU time 86.96 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:00:26 PM PST 23
Peak memory 182924 kb
Host smart-33d35e7e-a717-4e96-a074-998be3de0a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813729688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3813729688
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1629262224
Short name T369
Test name
Test status
Simulation time 408199587869 ps
CPU time 187.57 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:02:13 PM PST 23
Peak memory 191292 kb
Host smart-606ab514-f93a-4dfa-ad6a-09196316fe71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629262224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1629262224
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2384748357
Short name T347
Test name
Test status
Simulation time 238395487308 ps
CPU time 1308.53 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:20:58 PM PST 23
Peak memory 205840 kb
Host smart-7aa8ec8a-63db-4613-be82-7ee5ba33bc50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384748357 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2384748357
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3499473910
Short name T306
Test name
Test status
Simulation time 521458422118 ps
CPU time 193.12 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:02:24 PM PST 23
Peak memory 182824 kb
Host smart-73b5c562-9068-40cc-abfa-d723e15a8d28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499473910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3499473910
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3108828279
Short name T576
Test name
Test status
Simulation time 45450176336 ps
CPU time 61.48 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:00:02 PM PST 23
Peak memory 182976 kb
Host smart-4a54c462-60c4-4a1b-80fd-0901b87ee126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108828279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3108828279
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2014057279
Short name T533
Test name
Test status
Simulation time 44449326088 ps
CPU time 60.84 seconds
Started Dec 31 12:58:49 PM PST 23
Finished Dec 31 12:59:56 PM PST 23
Peak memory 182972 kb
Host smart-0ab38df6-754b-40e1-8431-08f455c0937a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014057279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2014057279
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4215973353
Short name T109
Test name
Test status
Simulation time 2085231067700 ps
CPU time 1396.36 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:22:33 PM PST 23
Peak memory 191108 kb
Host smart-53177038-2f31-42a0-ad7f-400896008228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215973353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4215973353
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1915947700
Short name T605
Test name
Test status
Simulation time 92859917129 ps
CPU time 689.46 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:10:36 PM PST 23
Peak memory 206844 kb
Host smart-5e22bfad-2a14-40a0-b02b-9ae3bf006356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915947700 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1915947700
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4083260026
Short name T608
Test name
Test status
Simulation time 304707698282 ps
CPU time 511.21 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:07:40 PM PST 23
Peak memory 182860 kb
Host smart-72db4149-2c6e-45be-8cd8-85d5d6449df4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083260026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.4083260026
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.605964056
Short name T125
Test name
Test status
Simulation time 86420732403 ps
CPU time 141.07 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 01:01:35 PM PST 23
Peak memory 191164 kb
Host smart-6c5e9419-155f-41b4-b0ad-a4267939fb15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605964056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.605964056
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.73820548
Short name T283
Test name
Test status
Simulation time 61009213571 ps
CPU time 227.79 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:03:10 PM PST 23
Peak memory 182944 kb
Host smart-615624db-62f9-4a54-9895-bd941b18ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73820548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.73820548
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.240830196
Short name T568
Test name
Test status
Simulation time 549563985973 ps
CPU time 1520.73 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:24:33 PM PST 23
Peak memory 222180 kb
Host smart-797d81aa-eddb-4f07-8008-107c8ee28b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240830196 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.240830196
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3180450892
Short name T238
Test name
Test status
Simulation time 634423310923 ps
CPU time 563.96 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:08:42 PM PST 23
Peak memory 182944 kb
Host smart-581f8100-52c4-4d5b-a2c8-629802d1f9ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180450892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3180450892
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3729040833
Short name T495
Test name
Test status
Simulation time 209355977954 ps
CPU time 168.06 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:01:58 PM PST 23
Peak memory 182936 kb
Host smart-2cbaea4a-2c5c-414e-a56a-0e38ae8d37d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729040833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3729040833
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.4042349105
Short name T202
Test name
Test status
Simulation time 738539353270 ps
CPU time 1160.93 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:18:18 PM PST 23
Peak memory 191064 kb
Host smart-1917b27f-7a64-4c20-af2c-ec105d59ac2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042349105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4042349105
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3068323806
Short name T151
Test name
Test status
Simulation time 472413506654 ps
CPU time 225.47 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:03:02 PM PST 23
Peak memory 182896 kb
Host smart-4094d8a3-0b1f-41f9-a339-1bc4ef9352b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068323806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3068323806
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2819808995
Short name T18
Test name
Test status
Simulation time 113735149 ps
CPU time 0.8 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 12:58:54 PM PST 23
Peak memory 212864 kb
Host smart-3de0ba94-b784-4ab1-865a-6e599ec1ee12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819808995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2819808995
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3606085302
Short name T582
Test name
Test status
Simulation time 47995567705 ps
CPU time 214.48 seconds
Started Dec 31 12:58:46 PM PST 23
Finished Dec 31 01:02:28 PM PST 23
Peak memory 197600 kb
Host smart-25ad1549-0e7f-47e7-b733-c6a14337702e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606085302 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3606085302
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1732153658
Short name T158
Test name
Test status
Simulation time 35461649370 ps
CPU time 42.57 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 12:59:54 PM PST 23
Peak memory 182896 kb
Host smart-678d127a-0427-41af-aa9a-8772a4ce8274
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732153658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1732153658
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3665697190
Short name T510
Test name
Test status
Simulation time 43116586005 ps
CPU time 66.74 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 01:00:20 PM PST 23
Peak memory 182932 kb
Host smart-f5380879-2be6-40a1-9a37-a59cbf66cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665697190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3665697190
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1825259095
Short name T6
Test name
Test status
Simulation time 268852240273 ps
CPU time 401.35 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:05:52 PM PST 23
Peak memory 191136 kb
Host smart-61d197fd-425b-4071-aa69-c7ec79fe3b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825259095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1825259095
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2343636211
Short name T496
Test name
Test status
Simulation time 1376274300 ps
CPU time 2 seconds
Started Dec 31 12:59:35 PM PST 23
Finished Dec 31 12:59:39 PM PST 23
Peak memory 193952 kb
Host smart-12794aa1-538c-47a9-8304-0e277426d778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343636211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2343636211
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3090627986
Short name T571
Test name
Test status
Simulation time 100109905867 ps
CPU time 168.88 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:01:59 PM PST 23
Peak memory 205760 kb
Host smart-9d04ae25-cd7a-4076-994a-d29a29f9ecdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090627986 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3090627986
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2970354166
Short name T521
Test name
Test status
Simulation time 443137023412 ps
CPU time 118.27 seconds
Started Dec 31 12:59:16 PM PST 23
Finished Dec 31 01:01:18 PM PST 23
Peak memory 182860 kb
Host smart-c4537cbf-bb13-4595-a42b-4dce2ed462a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970354166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2970354166
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.6366702
Short name T529
Test name
Test status
Simulation time 310428061444 ps
CPU time 126.47 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:01:17 PM PST 23
Peak memory 182892 kb
Host smart-fbacf802-257e-4332-9e13-df45d9d4e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6366702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.6366702
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1514926849
Short name T209
Test name
Test status
Simulation time 487890003344 ps
CPU time 274.55 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:03:51 PM PST 23
Peak memory 191136 kb
Host smart-32caf4b9-168c-4d7b-b5ce-9a2ae970e507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514926849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1514926849
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3930966459
Short name T544
Test name
Test status
Simulation time 99984618700 ps
CPU time 189.88 seconds
Started Dec 31 12:58:43 PM PST 23
Finished Dec 31 01:01:57 PM PST 23
Peak memory 191096 kb
Host smart-a434cdfd-ec48-449e-9236-b7251d86f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930966459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3930966459
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2933271242
Short name T539
Test name
Test status
Simulation time 37178713005 ps
CPU time 612.34 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:09:29 PM PST 23
Peak memory 205764 kb
Host smart-ddd0d2f4-3743-4b32-b75b-0e6f1838959a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933271242 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2933271242
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2933475669
Short name T214
Test name
Test status
Simulation time 1387483332913 ps
CPU time 339.71 seconds
Started Dec 31 12:59:19 PM PST 23
Finished Dec 31 01:05:02 PM PST 23
Peak memory 182944 kb
Host smart-2e8b6433-59f9-4220-89dc-e68d3fd18145
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933475669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2933475669
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3387343815
Short name T526
Test name
Test status
Simulation time 582910915757 ps
CPU time 212.9 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:02:57 PM PST 23
Peak memory 182976 kb
Host smart-0d6b759e-99e7-41d3-b4d9-2a8c6178968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387343815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3387343815
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.950658090
Short name T226
Test name
Test status
Simulation time 72698547017 ps
CPU time 42.14 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 12:59:46 PM PST 23
Peak memory 194480 kb
Host smart-02272a47-a3df-4161-9462-7936973214ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950658090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.950658090
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3267284224
Short name T36
Test name
Test status
Simulation time 15338847225 ps
CPU time 164.99 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:01:44 PM PST 23
Peak memory 197644 kb
Host smart-30a7d152-2b64-4c65-9114-4fd225dc9791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267284224 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3267284224
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2331874830
Short name T160
Test name
Test status
Simulation time 515884897542 ps
CPU time 925.56 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:14:38 PM PST 23
Peak memory 182932 kb
Host smart-735644cf-5265-43b9-b197-af0df83fd6a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331874830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2331874830
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.783921013
Short name T549
Test name
Test status
Simulation time 883160960540 ps
CPU time 377.08 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:05:15 PM PST 23
Peak memory 183012 kb
Host smart-a160df67-771e-4558-ab03-9ffc8c3d2c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783921013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.783921013
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1869881972
Short name T281
Test name
Test status
Simulation time 398541638854 ps
CPU time 515.3 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:07:37 PM PST 23
Peak memory 193492 kb
Host smart-9a14b4c7-24db-455a-8c5c-5a4b75bfd571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869881972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1869881972
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.107859212
Short name T530
Test name
Test status
Simulation time 39817301 ps
CPU time 0.53 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 12:59:11 PM PST 23
Peak memory 182340 kb
Host smart-d58d0f19-a630-4a97-89e7-e1a308ac932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107859212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.107859212
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.532622106
Short name T536
Test name
Test status
Simulation time 277815824739 ps
CPU time 469.39 seconds
Started Dec 31 12:59:22 PM PST 23
Finished Dec 31 01:07:14 PM PST 23
Peak memory 197636 kb
Host smart-a5c1ee86-9948-4a86-8fed-11e8d683fd78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532622106 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.532622106
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1528001019
Short name T330
Test name
Test status
Simulation time 176211450994 ps
CPU time 95.78 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:00:40 PM PST 23
Peak memory 182952 kb
Host smart-f6ab02f7-6722-4f7f-b940-074e8b6759ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528001019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1528001019
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1908422500
Short name T29
Test name
Test status
Simulation time 647639441092 ps
CPU time 258.18 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:03:33 PM PST 23
Peak memory 182884 kb
Host smart-746c49cd-35bb-4f34-98b6-8671e1774365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908422500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1908422500
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3692934030
Short name T251
Test name
Test status
Simulation time 176309386101 ps
CPU time 141.08 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:01:21 PM PST 23
Peak memory 192140 kb
Host smart-b23405e0-fc1f-4711-9364-dcb714abe642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692934030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3692934030
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3380730911
Short name T308
Test name
Test status
Simulation time 27293758289 ps
CPU time 27.92 seconds
Started Dec 31 12:59:08 PM PST 23
Finished Dec 31 12:59:41 PM PST 23
Peak memory 191132 kb
Host smart-3b6e82fe-eed1-4899-9eab-f431f1d1b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380730911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3380730911
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1123721552
Short name T143
Test name
Test status
Simulation time 186411706386 ps
CPU time 108.68 seconds
Started Dec 31 12:58:56 PM PST 23
Finished Dec 31 01:00:51 PM PST 23
Peak memory 191084 kb
Host smart-659cb548-3e9b-4da1-85ef-72bc3a3be9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123721552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1123721552
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3272674882
Short name T532
Test name
Test status
Simulation time 498856349659 ps
CPU time 707.59 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 01:10:43 PM PST 23
Peak memory 206876 kb
Host smart-daca9ad8-2aed-41aa-a6f7-4323227b86c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272674882 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3272674882
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2400619224
Short name T350
Test name
Test status
Simulation time 165696242143 ps
CPU time 263.86 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:03:34 PM PST 23
Peak memory 182252 kb
Host smart-28d8e095-d4a3-4f43-9b17-d39279e5e8f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400619224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2400619224
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.992395123
Short name T522
Test name
Test status
Simulation time 653457131 ps
CPU time 1.03 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 12:59:18 PM PST 23
Peak memory 182048 kb
Host smart-db1ce6c9-2584-47e7-9d08-dfb3873bec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992395123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.992395123
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3335919637
Short name T123
Test name
Test status
Simulation time 64933527070 ps
CPU time 236.02 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:03:04 PM PST 23
Peak memory 194240 kb
Host smart-c0ace2c0-f7c1-4dfe-8165-b5255cbff2d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335919637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3335919637
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2485868600
Short name T492
Test name
Test status
Simulation time 32982099 ps
CPU time 0.55 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 12:59:11 PM PST 23
Peak memory 181828 kb
Host smart-4006a0e4-236b-4314-97ff-9217bc7ca7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485868600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2485868600
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2806006698
Short name T597
Test name
Test status
Simulation time 35194629823 ps
CPU time 83.36 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:00:19 PM PST 23
Peak memory 196784 kb
Host smart-0e8c7367-7c7d-4a2d-a167-62f8125f48e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806006698 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2806006698
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3268872492
Short name T241
Test name
Test status
Simulation time 843869670158 ps
CPU time 474.61 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 01:06:51 PM PST 23
Peak memory 182896 kb
Host smart-f185a77f-d522-4bf9-8b59-bc06d97eb9ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268872492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3268872492
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2163782871
Short name T581
Test name
Test status
Simulation time 52343432087 ps
CPU time 71.85 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:00:23 PM PST 23
Peak memory 182928 kb
Host smart-8df46f49-d860-4db6-a704-01707318ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163782871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2163782871
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2744758819
Short name T266
Test name
Test status
Simulation time 1796314150190 ps
CPU time 604.94 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:09:17 PM PST 23
Peak memory 191120 kb
Host smart-01aa2dcd-1314-4286-a1f3-4b4821918905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744758819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2744758819
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4292290137
Short name T8
Test name
Test status
Simulation time 23787082613 ps
CPU time 8.53 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 12:59:15 PM PST 23
Peak memory 191808 kb
Host smart-278ac217-b76c-4ab8-a237-989e3ea87cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292290137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4292290137
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4047026199
Short name T534
Test name
Test status
Simulation time 82573893 ps
CPU time 0.51 seconds
Started Dec 31 12:59:29 PM PST 23
Finished Dec 31 12:59:31 PM PST 23
Peak memory 181752 kb
Host smart-ddfbbf86-28c4-4f4f-8fe1-5198ba0150d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047026199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4047026199
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.625591984
Short name T589
Test name
Test status
Simulation time 138315776729 ps
CPU time 482.83 seconds
Started Dec 31 12:59:29 PM PST 23
Finished Dec 31 01:07:33 PM PST 23
Peak memory 197584 kb
Host smart-c4d3c83c-fb3a-4fe8-a4b1-183fd0195819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625591984 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.625591984
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3297714683
Short name T367
Test name
Test status
Simulation time 67662781034 ps
CPU time 98.2 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:00:46 PM PST 23
Peak memory 182956 kb
Host smart-fff34fcb-a0fa-4709-9c3e-2948189ba702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297714683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3297714683
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3313670846
Short name T562
Test name
Test status
Simulation time 22101566564 ps
CPU time 63.22 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:00:16 PM PST 23
Peak memory 191116 kb
Host smart-55f601e1-c8ae-44ba-98ac-0436e436dbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313670846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3313670846
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2336158678
Short name T594
Test name
Test status
Simulation time 32924428 ps
CPU time 0.57 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 12:59:28 PM PST 23
Peak memory 182544 kb
Host smart-e1553244-2630-4073-9588-857125a8fc27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336158678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2336158678
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3327033255
Short name T247
Test name
Test status
Simulation time 201229721538 ps
CPU time 351.41 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:05:05 PM PST 23
Peak memory 205872 kb
Host smart-f67e37dc-fc34-448a-a08c-149018f6ddd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327033255 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3327033255
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.996255733
Short name T497
Test name
Test status
Simulation time 675173766822 ps
CPU time 104.5 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:01:08 PM PST 23
Peak memory 182956 kb
Host smart-b1191f8b-4818-402e-a6b9-4cb994be74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996255733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.996255733
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2481274210
Short name T316
Test name
Test status
Simulation time 264906497434 ps
CPU time 194.76 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:02:42 PM PST 23
Peak memory 191092 kb
Host smart-73b813f2-4a37-4b62-85a2-eab22aa8be54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481274210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2481274210
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3024291879
Short name T517
Test name
Test status
Simulation time 134000605 ps
CPU time 0.59 seconds
Started Dec 31 12:59:24 PM PST 23
Finished Dec 31 12:59:27 PM PST 23
Peak memory 182376 kb
Host smart-0c516e7f-5ad3-43bc-8df6-cddd672d0c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024291879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3024291879
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1093726802
Short name T556
Test name
Test status
Simulation time 282721846091 ps
CPU time 468.93 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:07:11 PM PST 23
Peak memory 205800 kb
Host smart-7fe854ae-a906-41d2-b9ba-8e7929d017cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093726802 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1093726802
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.206282870
Short name T87
Test name
Test status
Simulation time 326512535210 ps
CPU time 139.02 seconds
Started Dec 31 12:58:40 PM PST 23
Finished Dec 31 01:01:06 PM PST 23
Peak memory 182932 kb
Host smart-442a2c3b-4fd0-4c71-9982-9b0bc83d962d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206282870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.206282870
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1355843820
Short name T504
Test name
Test status
Simulation time 78391555947 ps
CPU time 125 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:01:29 PM PST 23
Peak memory 182868 kb
Host smart-3fc981c0-7918-415d-bc75-89b250bf70c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355843820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1355843820
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3430838556
Short name T233
Test name
Test status
Simulation time 54467814039 ps
CPU time 306.98 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:04:22 PM PST 23
Peak memory 191088 kb
Host smart-d07cb412-b750-4db3-b1ba-abf9a1cffef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430838556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3430838556
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.424513310
Short name T552
Test name
Test status
Simulation time 2689470670798 ps
CPU time 499.94 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:07:35 PM PST 23
Peak memory 191084 kb
Host smart-de4f9500-d550-4ea3-9819-68d0027dec81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424513310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
424513310
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1406937669
Short name T590
Test name
Test status
Simulation time 56472406341 ps
CPU time 400.17 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:06:02 PM PST 23
Peak memory 197604 kb
Host smart-3b8ac188-ebf6-4f37-b8d1-b940790ee81a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406937669 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1406937669
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1620670575
Short name T4
Test name
Test status
Simulation time 227619812916 ps
CPU time 398.21 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:05:48 PM PST 23
Peak memory 182784 kb
Host smart-12e4a2bd-6256-49c8-8652-6f6089ec42a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620670575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1620670575
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2355667378
Short name T600
Test name
Test status
Simulation time 91135189971 ps
CPU time 146.56 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:01:26 PM PST 23
Peak memory 183008 kb
Host smart-43f0d3eb-ed1c-462a-a30b-96bd1ed0a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355667378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2355667378
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.573265568
Short name T25
Test name
Test status
Simulation time 112310805351 ps
CPU time 92.7 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:00:43 PM PST 23
Peak memory 191176 kb
Host smart-e3fe8a7d-95e9-4617-9279-c5b62b24a22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573265568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.573265568
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3307627417
Short name T97
Test name
Test status
Simulation time 557103170911 ps
CPU time 111.34 seconds
Started Dec 31 12:58:41 PM PST 23
Finished Dec 31 01:00:38 PM PST 23
Peak memory 191140 kb
Host smart-151efe06-ecc2-44dd-a4f3-7c3111057b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307627417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3307627417
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3168652385
Short name T560
Test name
Test status
Simulation time 14605952466 ps
CPU time 20.68 seconds
Started Dec 31 12:58:39 PM PST 23
Finished Dec 31 12:59:07 PM PST 23
Peak memory 182972 kb
Host smart-69632e3a-6130-4592-ab76-9f2c07bf470e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168652385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3168652385
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3863276130
Short name T337
Test name
Test status
Simulation time 135244949251 ps
CPU time 241.44 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:03:01 PM PST 23
Peak memory 207488 kb
Host smart-cc938b4e-56be-4711-9e25-696899a4b695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863276130 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3863276130
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2657701234
Short name T311
Test name
Test status
Simulation time 248780064053 ps
CPU time 2042.3 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:33:20 PM PST 23
Peak memory 191056 kb
Host smart-7a03ccfc-1d26-4f4d-a750-34ca5dcad8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657701234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2657701234
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2348758955
Short name T361
Test name
Test status
Simulation time 326460483087 ps
CPU time 148.74 seconds
Started Dec 31 12:59:29 PM PST 23
Finished Dec 31 01:01:59 PM PST 23
Peak memory 191092 kb
Host smart-fce52bc4-12ea-4db8-bae3-913a94cd1ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348758955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2348758955
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3244892617
Short name T293
Test name
Test status
Simulation time 108727549044 ps
CPU time 648.52 seconds
Started Dec 31 12:58:55 PM PST 23
Finished Dec 31 01:09:49 PM PST 23
Peak memory 191076 kb
Host smart-ecd1d4fd-b8dc-4ffd-9339-37d2dba42b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244892617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3244892617
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1961101009
Short name T348
Test name
Test status
Simulation time 3457398944 ps
CPU time 28.46 seconds
Started Dec 31 12:59:36 PM PST 23
Finished Dec 31 01:00:05 PM PST 23
Peak memory 182876 kb
Host smart-379cf3a9-1254-4acc-a149-b014f5919e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961101009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1961101009
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1184831092
Short name T322
Test name
Test status
Simulation time 216561954914 ps
CPU time 1495.38 seconds
Started Dec 31 12:59:25 PM PST 23
Finished Dec 31 01:24:23 PM PST 23
Peak memory 194324 kb
Host smart-11f0f462-b7e9-4ec7-80f3-99d05c9e12e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184831092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1184831092
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2887730883
Short name T172
Test name
Test status
Simulation time 186911468911 ps
CPU time 713.56 seconds
Started Dec 31 12:58:57 PM PST 23
Finished Dec 31 01:10:56 PM PST 23
Peak memory 191112 kb
Host smart-5318b6e2-54d0-4321-a20d-855ee1e116c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887730883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2887730883
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3109914548
Short name T286
Test name
Test status
Simulation time 17542444082 ps
CPU time 28.31 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 12:59:39 PM PST 23
Peak memory 182912 kb
Host smart-4cf4797f-8e36-4fa1-82ce-d184572ee660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109914548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3109914548
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.865346227
Short name T101
Test name
Test status
Simulation time 80032936783 ps
CPU time 111.73 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:01:15 PM PST 23
Peak memory 191156 kb
Host smart-eeaf0b74-73b9-4f79-9022-e1e15b07fb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865346227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.865346227
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3654816914
Short name T300
Test name
Test status
Simulation time 304460500311 ps
CPU time 309.39 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:04:16 PM PST 23
Peak memory 182908 kb
Host smart-39a6cd7a-1c59-49b9-a6e1-f8f773b2da56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654816914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3654816914
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.52162098
Short name T570
Test name
Test status
Simulation time 178750128345 ps
CPU time 71.77 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:00:15 PM PST 23
Peak memory 182924 kb
Host smart-1af8d424-f5b2-42af-98b5-04ce1f13f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52162098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.52162098
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2691668237
Short name T256
Test name
Test status
Simulation time 65478171613 ps
CPU time 162.83 seconds
Started Dec 31 12:59:00 PM PST 23
Finished Dec 31 01:01:50 PM PST 23
Peak memory 194052 kb
Host smart-9f8626b4-a98e-469b-8069-9c782cc16468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691668237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2691668237
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1376469050
Short name T565
Test name
Test status
Simulation time 332125133 ps
CPU time 1.64 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 12:59:11 PM PST 23
Peak memory 193352 kb
Host smart-158dfc47-082d-42aa-b227-d756a6209772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376469050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1376469050
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2455484723
Short name T564
Test name
Test status
Simulation time 154194828765 ps
CPU time 552.61 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:08:18 PM PST 23
Peak memory 205876 kb
Host smart-f532188c-85e0-4b4a-963d-183a5be27f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455484723 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2455484723
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.364210467
Short name T157
Test name
Test status
Simulation time 336761258772 ps
CPU time 248.88 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 01:03:04 PM PST 23
Peak memory 194188 kb
Host smart-94c29d95-3a2d-427b-ac75-b711b06c18b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364210467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.364210467
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2526661860
Short name T91
Test name
Test status
Simulation time 420837659381 ps
CPU time 389.39 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:05:28 PM PST 23
Peak memory 191152 kb
Host smart-484f9799-8045-40c1-b7cd-92c11450be2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526661860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2526661860
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1777595768
Short name T319
Test name
Test status
Simulation time 102431080884 ps
CPU time 224.94 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:02:44 PM PST 23
Peak memory 191076 kb
Host smart-072c36bd-aaee-42be-97c1-a6e2b4541843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777595768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1777595768
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1598939517
Short name T2
Test name
Test status
Simulation time 23808010810 ps
CPU time 31.19 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 12:59:48 PM PST 23
Peak memory 193724 kb
Host smart-8aa9224b-127c-400a-a94d-d2e26369b273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598939517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1598939517
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2488504608
Short name T112
Test name
Test status
Simulation time 85552050559 ps
CPU time 1578.82 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:25:41 PM PST 23
Peak memory 191108 kb
Host smart-8a9ff474-52fc-44ef-82eb-5edfba2f9534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488504608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2488504608
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.294732839
Short name T89
Test name
Test status
Simulation time 339747534006 ps
CPU time 637.84 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:09:57 PM PST 23
Peak memory 191280 kb
Host smart-1daff5a6-0ed2-406f-949f-868448a4d5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294732839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.294732839
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.15501034
Short name T90
Test name
Test status
Simulation time 2118175648374 ps
CPU time 526.27 seconds
Started Dec 31 12:59:06 PM PST 23
Finished Dec 31 01:07:58 PM PST 23
Peak memory 191080 kb
Host smart-be3934ce-a98c-4599-abe1-97de8b65d071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.15501034
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3586575193
Short name T273
Test name
Test status
Simulation time 11034216668 ps
CPU time 23.06 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 12:59:38 PM PST 23
Peak memory 182920 kb
Host smart-dafaad40-006a-4e7e-804f-e2cd9b79bbfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586575193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3586575193
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.284454788
Short name T114
Test name
Test status
Simulation time 151516018968 ps
CPU time 262.41 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:03:25 PM PST 23
Peak memory 191088 kb
Host smart-09324125-4f84-4e26-9d31-cef1849803f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284454788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.284454788
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1954468044
Short name T3
Test name
Test status
Simulation time 83640509795 ps
CPU time 74.59 seconds
Started Dec 31 12:59:02 PM PST 23
Finished Dec 31 01:00:24 PM PST 23
Peak memory 182928 kb
Host smart-3a0946aa-08de-44d4-a0ea-253f9d3e0372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954468044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1954468044
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1112256086
Short name T27
Test name
Test status
Simulation time 1305297508460 ps
CPU time 1344.96 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:21:30 PM PST 23
Peak memory 182828 kb
Host smart-57b0847c-3a0a-41bc-9313-951421538d5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112256086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1112256086
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4189629371
Short name T505
Test name
Test status
Simulation time 461723725239 ps
CPU time 253.42 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:03:27 PM PST 23
Peak memory 183024 kb
Host smart-16acf841-e2fc-4b95-afd2-b530839d5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189629371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4189629371
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3498687689
Short name T197
Test name
Test status
Simulation time 78816835892 ps
CPU time 139.39 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:01:34 PM PST 23
Peak memory 191056 kb
Host smart-4eee33f2-a564-4799-bdfe-c159f51caf09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498687689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3498687689
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2460458461
Short name T333
Test name
Test status
Simulation time 69335483867 ps
CPU time 636.35 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:09:46 PM PST 23
Peak memory 182844 kb
Host smart-d2d8cff0-24ba-4abf-9203-35736f561de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460458461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2460458461
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2033308623
Short name T268
Test name
Test status
Simulation time 270909601929 ps
CPU time 244.58 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:03:08 PM PST 23
Peak memory 191088 kb
Host smart-25a22e82-24f0-42e5-8e68-114da544c606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033308623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2033308623
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1232472422
Short name T501
Test name
Test status
Simulation time 161973032693 ps
CPU time 429.43 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 01:06:08 PM PST 23
Peak memory 205840 kb
Host smart-9873f8bb-1290-44ac-aacb-31b69043394e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232472422 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1232472422
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3610645266
Short name T124
Test name
Test status
Simulation time 216124758926 ps
CPU time 398.98 seconds
Started Dec 31 12:59:20 PM PST 23
Finished Dec 31 01:06:02 PM PST 23
Peak memory 191080 kb
Host smart-8ecffd57-035a-4f21-b4a4-be8c6ee23813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610645266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3610645266
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.940372623
Short name T142
Test name
Test status
Simulation time 448236328090 ps
CPU time 386.39 seconds
Started Dec 31 12:59:11 PM PST 23
Finished Dec 31 01:05:42 PM PST 23
Peak memory 191164 kb
Host smart-efc3a4cc-1ba2-44ec-8885-f1ea7b90ace1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940372623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.940372623
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3358343296
Short name T168
Test name
Test status
Simulation time 109456335443 ps
CPU time 173.03 seconds
Started Dec 31 12:58:58 PM PST 23
Finished Dec 31 01:01:56 PM PST 23
Peak memory 193892 kb
Host smart-0e9b98bc-050a-4c6a-a8eb-3236dc544d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358343296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3358343296
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3837850775
Short name T323
Test name
Test status
Simulation time 22422666719 ps
CPU time 112.53 seconds
Started Dec 31 12:59:13 PM PST 23
Finished Dec 31 01:01:09 PM PST 23
Peak memory 191132 kb
Host smart-2debfb94-947d-49d6-a569-85141de80de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837850775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3837850775
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2761583177
Short name T195
Test name
Test status
Simulation time 43249423530 ps
CPU time 100.43 seconds
Started Dec 31 12:59:41 PM PST 23
Finished Dec 31 01:01:25 PM PST 23
Peak memory 191124 kb
Host smart-ca822ff8-08e7-4419-a6ed-9f4c584ecaa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761583177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2761583177
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.993618229
Short name T223
Test name
Test status
Simulation time 2329094903935 ps
CPU time 506.77 seconds
Started Dec 31 12:59:15 PM PST 23
Finished Dec 31 01:07:46 PM PST 23
Peak memory 191068 kb
Host smart-3b1b237d-544b-436d-8366-9d574b370d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993618229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.993618229
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1724282943
Short name T292
Test name
Test status
Simulation time 404994854722 ps
CPU time 812.56 seconds
Started Dec 31 12:59:30 PM PST 23
Finished Dec 31 01:13:04 PM PST 23
Peak memory 194476 kb
Host smart-3f78fd71-ab9f-463f-8703-34616b8edbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724282943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1724282943
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1943696325
Short name T217
Test name
Test status
Simulation time 748907728737 ps
CPU time 435.94 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:06:13 PM PST 23
Peak memory 182924 kb
Host smart-96b039c3-0b90-4913-972c-a9856a2a7a07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943696325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1943696325
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.887534570
Short name T511
Test name
Test status
Simulation time 190670394540 ps
CPU time 105.15 seconds
Started Dec 31 12:59:01 PM PST 23
Finished Dec 31 01:00:52 PM PST 23
Peak memory 182936 kb
Host smart-7f7a0c66-98e7-4789-b391-bb38da451568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887534570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.887534570
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3522825954
Short name T178
Test name
Test status
Simulation time 166296689883 ps
CPU time 708.23 seconds
Started Dec 31 12:58:38 PM PST 23
Finished Dec 31 01:10:35 PM PST 23
Peak memory 190944 kb
Host smart-1e02df91-9768-4576-82bd-2934ffa18353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522825954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3522825954
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1167727277
Short name T569
Test name
Test status
Simulation time 77753691124 ps
CPU time 554.17 seconds
Started Dec 31 12:58:53 PM PST 23
Finished Dec 31 01:08:13 PM PST 23
Peak memory 191144 kb
Host smart-a8b4aa07-6509-4c52-8738-02799174a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167727277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1167727277
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.72876771
Short name T503
Test name
Test status
Simulation time 23178053870 ps
CPU time 193.93 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:02:23 PM PST 23
Peak memory 197596 kb
Host smart-d8bef8b5-389c-47fb-b4d9-5751d244c589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72876771 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.72876771
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1795884744
Short name T88
Test name
Test status
Simulation time 53238262031 ps
CPU time 80.61 seconds
Started Dec 31 12:59:24 PM PST 23
Finished Dec 31 01:00:47 PM PST 23
Peak memory 192364 kb
Host smart-4a2cd87e-75a5-4b2e-86ed-2c38a37a7a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795884744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1795884744
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.728539667
Short name T352
Test name
Test status
Simulation time 205785546979 ps
CPU time 130.47 seconds
Started Dec 31 12:59:07 PM PST 23
Finished Dec 31 01:01:23 PM PST 23
Peak memory 191072 kb
Host smart-a83082a0-c14c-4431-860d-f1dc82d72de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728539667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.728539667
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3228919911
Short name T295
Test name
Test status
Simulation time 540962972047 ps
CPU time 543.74 seconds
Started Dec 31 12:59:30 PM PST 23
Finished Dec 31 01:08:35 PM PST 23
Peak memory 191160 kb
Host smart-c3fa519e-a996-4e27-9566-54dee0623bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228919911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3228919911
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1209269537
Short name T42
Test name
Test status
Simulation time 37986320084 ps
CPU time 273.46 seconds
Started Dec 31 12:59:03 PM PST 23
Finished Dec 31 01:03:43 PM PST 23
Peak memory 191064 kb
Host smart-0ed433d3-0a0e-4e14-bfbb-3b59e3d0d43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209269537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1209269537
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4256194083
Short name T280
Test name
Test status
Simulation time 189992805222 ps
CPU time 391.14 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:05:53 PM PST 23
Peak memory 191088 kb
Host smart-80a12f93-e3e4-4014-97a6-f0669e63b9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256194083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4256194083
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1707044681
Short name T9
Test name
Test status
Simulation time 398256148275 ps
CPU time 545.51 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:08:19 PM PST 23
Peak memory 182936 kb
Host smart-47ad2525-875f-4bae-9ed0-bcdeb91cfcc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707044681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1707044681
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1937735200
Short name T138
Test name
Test status
Simulation time 650206242344 ps
CPU time 1390.23 seconds
Started Dec 31 12:59:04 PM PST 23
Finished Dec 31 01:22:21 PM PST 23
Peak memory 194780 kb
Host smart-61141285-e0e0-472a-bca5-06383d4ae080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937735200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1937735200
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.481877072
Short name T515
Test name
Test status
Simulation time 160530798779 ps
CPU time 124.95 seconds
Started Dec 31 12:59:10 PM PST 23
Finished Dec 31 01:01:20 PM PST 23
Peak memory 182976 kb
Host smart-1e3e744a-590f-40fa-985e-211c52dee98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481877072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.481877072
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2275673531
Short name T606
Test name
Test status
Simulation time 155250783185 ps
CPU time 363.13 seconds
Started Dec 31 12:58:54 PM PST 23
Finished Dec 31 01:05:03 PM PST 23
Peak memory 191172 kb
Host smart-553511fb-aa93-4ce6-9288-15da23b8c340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275673531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2275673531
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2336557521
Short name T234
Test name
Test status
Simulation time 104641499330 ps
CPU time 56.73 seconds
Started Dec 31 12:58:52 PM PST 23
Finished Dec 31 12:59:54 PM PST 23
Peak memory 190988 kb
Host smart-44ce81db-258d-4a4e-8b8d-1efab3b72392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336557521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2336557521
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2796969084
Short name T551
Test name
Test status
Simulation time 28699640 ps
CPU time 0.56 seconds
Started Dec 31 12:59:21 PM PST 23
Finished Dec 31 12:59:25 PM PST 23
Peak memory 181780 kb
Host smart-1a37ab38-81fa-4e1c-bf23-4ae26bfdfe01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796969084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2796969084
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1952639958
Short name T353
Test name
Test status
Simulation time 72563713984 ps
CPU time 909.35 seconds
Started Dec 31 12:59:09 PM PST 23
Finished Dec 31 01:14:23 PM PST 23
Peak memory 206052 kb
Host smart-1d5e3c00-eb76-4bec-91dd-c9acca32dce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952639958 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1952639958
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.69485042
Short name T103
Test name
Test status
Simulation time 264149230788 ps
CPU time 221.95 seconds
Started Dec 31 12:59:18 PM PST 23
Finished Dec 31 01:03:08 PM PST 23
Peak memory 191088 kb
Host smart-587d3643-10b1-4831-8f28-ba34ef226a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69485042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.69485042
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1961505891
Short name T130
Test name
Test status
Simulation time 247156030489 ps
CPU time 276.25 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:03:55 PM PST 23
Peak memory 191052 kb
Host smart-03b7c130-69b4-44e5-9f16-92533ebaf9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961505891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1961505891
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3967854900
Short name T193
Test name
Test status
Simulation time 409692327041 ps
CPU time 545.21 seconds
Started Dec 31 12:58:59 PM PST 23
Finished Dec 31 01:08:10 PM PST 23
Peak memory 191184 kb
Host smart-86dc68c0-eb66-4064-baae-26909f806f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967854900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3967854900
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2855339362
Short name T580
Test name
Test status
Simulation time 31109955996 ps
CPU time 16.17 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 12:59:32 PM PST 23
Peak memory 183012 kb
Host smart-f3d234a2-9db8-4d2f-bdb7-bfaab64eace6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855339362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2855339362
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.167182231
Short name T284
Test name
Test status
Simulation time 182406946214 ps
CPU time 498.11 seconds
Started Dec 31 12:58:51 PM PST 23
Finished Dec 31 01:07:15 PM PST 23
Peak memory 182904 kb
Host smart-7f90e38f-6735-4ef6-a636-f61c13946a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167182231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.167182231
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2949620944
Short name T270
Test name
Test status
Simulation time 110664025853 ps
CPU time 418.4 seconds
Started Dec 31 12:59:14 PM PST 23
Finished Dec 31 01:06:17 PM PST 23
Peak memory 191032 kb
Host smart-07cc4112-adb3-4106-9513-bb32504ccfba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949620944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2949620944
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3511691302
Short name T245
Test name
Test status
Simulation time 46711800417 ps
CPU time 53.39 seconds
Started Dec 31 12:59:12 PM PST 23
Finished Dec 31 01:00:10 PM PST 23
Peak memory 182984 kb
Host smart-5622e4d0-3b9a-424f-8968-070fec356885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511691302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3511691302
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1819566617
Short name T205
Test name
Test status
Simulation time 43703240244 ps
CPU time 64.71 seconds
Started Dec 31 12:59:17 PM PST 23
Finished Dec 31 01:00:26 PM PST 23
Peak memory 191180 kb
Host smart-3221dc18-07b1-4609-9670-2b51feee7664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819566617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1819566617
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3545636403
Short name T583
Test name
Test status
Simulation time 42335265023 ps
CPU time 22.95 seconds
Started Dec 31 12:58:50 PM PST 23
Finished Dec 31 12:59:18 PM PST 23
Peak memory 182944 kb
Host smart-9681773e-b6d4-4415-8dec-7136134675c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545636403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3545636403
Directory /workspace/99.rv_timer_random/latest
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