| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.51 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 98.98 |
| T332 | /workspace/coverage/default/179.rv_timer_random.2248328132 | Jan 03 12:34:45 PM PST 24 | Jan 03 12:44:30 PM PST 24 | 643902843080 ps | ||
| T151 | /workspace/coverage/default/4.rv_timer_stress_all.3366752445 | Jan 03 12:33:24 PM PST 24 | Jan 03 12:53:44 PM PST 24 | 1137760454588 ps | ||
| T515 | /workspace/coverage/default/9.rv_timer_disabled.483621674 | Jan 03 12:33:25 PM PST 24 | Jan 03 12:39:29 PM PST 24 | 189514192913 ps | ||
| T516 | /workspace/coverage/default/16.rv_timer_disabled.3747618340 | Jan 03 12:34:59 PM PST 24 | Jan 03 12:42:10 PM PST 24 | 217327060718 ps | ||
| T27 | /workspace/coverage/default/1.rv_timer_sec_cm.2839012899 | Jan 03 12:35:33 PM PST 24 | Jan 03 12:37:06 PM PST 24 | 132364150 ps | ||
| T245 | /workspace/coverage/default/55.rv_timer_random.347037856 | Jan 03 12:34:26 PM PST 24 | Jan 03 01:02:51 PM PST 24 | 916523746744 ps | ||
| T517 | /workspace/coverage/default/4.rv_timer_random.2139798907 | Jan 03 12:33:17 PM PST 24 | Jan 03 12:37:14 PM PST 24 | 99277261571 ps | ||
| T518 | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.880848520 | Jan 03 12:34:50 PM PST 24 | Jan 03 12:43:47 PM PST 24 | 1046919579116 ps | ||
| T197 | /workspace/coverage/default/184.rv_timer_random.4001531567 | Jan 03 12:34:45 PM PST 24 | Jan 03 12:38:04 PM PST 24 | 129394474438 ps | ||
| T519 | /workspace/coverage/default/45.rv_timer_disabled.2601782678 | Jan 03 12:34:04 PM PST 24 | Jan 03 12:36:49 PM PST 24 | 211267101863 ps | ||
| T343 | /workspace/coverage/default/22.rv_timer_random.3927924113 | Jan 03 12:34:29 PM PST 24 | Jan 03 12:37:26 PM PST 24 | 66963676503 ps | ||
| T520 | /workspace/coverage/default/16.rv_timer_stress_all.3257117189 | Jan 03 12:33:26 PM PST 24 | Jan 03 12:43:45 PM PST 24 | 351139382319 ps | ||
| T141 | /workspace/coverage/default/14.rv_timer_random_reset.3978107654 | Jan 03 12:33:47 PM PST 24 | Jan 03 12:36:36 PM PST 24 | 22912977407 ps | ||
| T291 | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2392045296 | Jan 03 12:33:51 PM PST 24 | Jan 03 12:48:17 PM PST 24 | 87966097748 ps | ||
| T28 | /workspace/coverage/default/2.rv_timer_sec_cm.4227384601 | Jan 03 12:34:33 PM PST 24 | Jan 03 12:35:45 PM PST 24 | 301770612 ps | ||
| T521 | /workspace/coverage/default/10.rv_timer_random_reset.2209361981 | Jan 03 12:33:52 PM PST 24 | Jan 03 12:36:11 PM PST 24 | 35325558261 ps | ||
| T522 | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2271539495 | Jan 03 12:33:25 PM PST 24 | Jan 03 12:40:12 PM PST 24 | 28199815153 ps | ||
| T321 | /workspace/coverage/default/7.rv_timer_random_reset.76980458 | Jan 03 12:33:19 PM PST 24 | Jan 03 12:38:10 PM PST 24 | 56569918671 ps | ||
| T316 | /workspace/coverage/default/47.rv_timer_random.3736656968 | Jan 03 12:34:02 PM PST 24 | Jan 03 12:43:17 PM PST 24 | 140982808353 ps | ||
| T523 | /workspace/coverage/default/76.rv_timer_random.3877736438 | Jan 03 12:33:55 PM PST 24 | Jan 03 12:37:54 PM PST 24 | 434866923642 ps | ||
| T524 | /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2035525142 | Jan 03 12:37:27 PM PST 24 | Jan 03 12:48:19 PM PST 24 | 37999256675 ps | ||
| T248 | /workspace/coverage/default/95.rv_timer_random.1292865483 | Jan 03 12:33:58 PM PST 24 | Jan 03 12:40:22 PM PST 24 | 507341918334 ps | ||
| T338 | /workspace/coverage/default/190.rv_timer_random.1524740776 | Jan 03 12:34:19 PM PST 24 | Jan 03 12:44:38 PM PST 24 | 132101068271 ps | ||
| T525 | /workspace/coverage/default/111.rv_timer_random.509820221 | Jan 03 12:34:15 PM PST 24 | Jan 03 12:35:50 PM PST 24 | 3457410823 ps | ||
| T307 | /workspace/coverage/default/93.rv_timer_random.862525309 | Jan 03 12:34:28 PM PST 24 | Jan 03 12:40:19 PM PST 24 | 75682003474 ps | ||
| T526 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.523561431 | Jan 03 12:30:41 PM PST 24 | Jan 03 12:31:45 PM PST 24 | 47084148 ps | ||
| T527 | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2517798362 | Jan 03 12:29:27 PM PST 24 | Jan 03 12:30:01 PM PST 24 | 374719490 ps | ||
| T528 | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2985721924 | Jan 03 12:31:27 PM PST 24 | Jan 03 12:32:39 PM PST 24 | 24072656 ps | ||
| T529 | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.109722526 | Jan 03 12:30:39 PM PST 24 | Jan 03 12:31:42 PM PST 24 | 44679687 ps | ||
| T530 | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.637362617 | Jan 03 12:31:20 PM PST 24 | Jan 03 12:32:30 PM PST 24 | 669158449 ps | ||
| T531 | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1932991536 | Jan 03 12:30:43 PM PST 24 | Jan 03 12:31:49 PM PST 24 | 25684752 ps | ||
| T532 | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.149842490 | Jan 03 12:30:36 PM PST 24 | Jan 03 12:31:38 PM PST 24 | 24045713 ps | ||
| T533 | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3204946253 | Jan 03 12:29:39 PM PST 24 | Jan 03 12:30:18 PM PST 24 | 1552613040 ps | ||
| T534 | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1848321878 | Jan 03 12:29:21 PM PST 24 | Jan 03 12:29:53 PM PST 24 | 71363448 ps | ||
| T535 | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3237558764 | Jan 03 12:31:16 PM PST 24 | Jan 03 12:32:22 PM PST 24 | 25353892 ps | ||
| T536 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1520861160 | Jan 03 12:30:42 PM PST 24 | Jan 03 12:31:49 PM PST 24 | 152475139 ps | ||
| T537 | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1817786479 | Jan 03 12:30:37 PM PST 24 | Jan 03 12:31:42 PM PST 24 | 50626519 ps | ||
| T538 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4019903922 | Jan 03 12:30:31 PM PST 24 | Jan 03 12:31:33 PM PST 24 | 89610683 ps | ||
| T539 | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1461135641 | Jan 03 12:30:46 PM PST 24 | Jan 03 12:31:52 PM PST 24 | 262187685 ps | ||
| T540 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.529915272 | Jan 03 12:29:27 PM PST 24 | Jan 03 12:29:59 PM PST 24 | 26537014 ps | ||
| T541 | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.239574469 | Jan 03 12:29:50 PM PST 24 | Jan 03 12:30:32 PM PST 24 | 53060546 ps | ||
| T542 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3318697096 | Jan 03 12:30:44 PM PST 24 | Jan 03 12:31:49 PM PST 24 | 34588652 ps | ||
| T543 | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1964380137 | Jan 03 12:31:10 PM PST 24 | Jan 03 12:32:15 PM PST 24 | 35451420 ps | ||
| T544 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3381582835 | Jan 03 12:29:11 PM PST 24 | Jan 03 12:29:41 PM PST 24 | 293751432 ps | ||
| T545 | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4225794829 | Jan 03 12:30:45 PM PST 24 | Jan 03 12:31:52 PM PST 24 | 66501449 ps |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1363530858 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 368234702 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:29:58 PM PST 24 |
| Finished | Jan 03 12:30:44 PM PST 24 |
| Peak memory | 195524 kb |
| Host | smart-fb28a6ab-836a-4411-9d8e-d27ef777a3e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363530858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.1363530858 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.3151773430 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1485381895009 ps |
| CPU time | 1017.68 seconds |
| Started | Jan 03 12:33:34 PM PST 24 |
| Finished | Jan 03 12:51:57 PM PST 24 |
| Peak memory | 190988 kb |
| Host | smart-8b95c72b-1e29-4570-88cc-537d46c8cf05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151773430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .3151773430 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.784196529 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 79095089 ps |
| CPU time | 1.91 seconds |
| Started | Jan 03 12:30:43 PM PST 24 |
| Finished | Jan 03 12:31:49 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-06055540-9e56-4f43-b135-46204d55906c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784196529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.784196529 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.395571766 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 33897202 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:58 PM PST 24 |
| Finished | Jan 03 12:32:05 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-75033f98-2628-4756-9f5f-d9835dc0f61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395571766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.395571766 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.642474382 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2410653881427 ps |
| CPU time | 2352.05 seconds |
| Started | Jan 03 12:33:11 PM PST 24 |
| Finished | Jan 03 01:13:48 PM PST 24 |
| Peak memory | 191012 kb |
| Host | smart-14e2daba-619c-4e70-8974-233127cb5d74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642474382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all. 642474382 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1594194000 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 27986063 ps |
| CPU time | 0.72 seconds |
| Started | Jan 03 12:28:31 PM PST 24 |
| Finished | Jan 03 12:28:46 PM PST 24 |
| Peak memory | 183304 kb |
| Host | smart-65d78ffd-8d34-4eb8-a6ce-0b2a77b98728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594194000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.1594194000 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.4194706862 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2236154377751 ps |
| CPU time | 1561.86 seconds |
| Started | Jan 03 12:33:29 PM PST 24 |
| Finished | Jan 03 01:00:56 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-9a6adebb-473a-461d-9dcf-6ad3e7582506 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194706862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .4194706862 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.3201375703 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1777476349157 ps |
| CPU time | 2795.33 seconds |
| Started | Jan 03 12:33:35 PM PST 24 |
| Finished | Jan 03 01:21:25 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-e4a9cab4-df28-4917-9a23-d2bc545c41d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201375703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .3201375703 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.1833321823 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1082251420540 ps |
| CPU time | 1395.89 seconds |
| Started | Jan 03 12:35:03 PM PST 24 |
| Finished | Jan 03 12:59:51 PM PST 24 |
| Peak memory | 190444 kb |
| Host | smart-e4b45786-dd04-4ff9-a398-1de5a8b8a9f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833321823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .1833321823 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.86171490 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2615383197386 ps |
| CPU time | 2407.59 seconds |
| Started | Jan 03 12:33:18 PM PST 24 |
| Finished | Jan 03 01:14:51 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-3cd7321c-602a-420c-8fb4-c8bb69626281 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86171490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.86171490 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.2164065418 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 544656779992 ps |
| CPU time | 1272.23 seconds |
| Started | Jan 03 12:37:19 PM PST 24 |
| Finished | Jan 03 12:59:47 PM PST 24 |
| Peak memory | 190776 kb |
| Host | smart-931f58b9-db77-4da2-936c-1e23170cb6bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164065418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 2164065418 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.1211282477 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2842199109846 ps |
| CPU time | 1719.96 seconds |
| Started | Jan 03 12:34:01 PM PST 24 |
| Finished | Jan 03 01:03:57 PM PST 24 |
| Peak memory | 191316 kb |
| Host | smart-06229269-dadf-4b04-9165-1a54d1d42df8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211282477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .1211282477 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.4237236655 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 968459146972 ps |
| CPU time | 3190.19 seconds |
| Started | Jan 03 12:33:50 PM PST 24 |
| Finished | Jan 03 01:28:20 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-90455714-928b-4735-a3a7-e98d372a178a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237236655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all .4237236655 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2000835601 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 307255258581 ps |
| CPU time | 1144.32 seconds |
| Started | Jan 03 12:35:44 PM PST 24 |
| Finished | Jan 03 12:56:26 PM PST 24 |
| Peak memory | 211544 kb |
| Host | smart-a9862120-7247-4d7e-8294-4d9e29ef63f0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000835601 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2000835601 |
| Directory | /workspace/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.2329127844 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 58090629 ps |
| CPU time | 0.71 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:35:11 PM PST 24 |
| Peak memory | 212752 kb |
| Host | smart-06e4ea34-6513-4982-8033-2343ed1cb26d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329127844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2329127844 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1074920951 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 103970744 ps |
| CPU time | 1.12 seconds |
| Started | Jan 03 12:29:48 PM PST 24 |
| Finished | Jan 03 12:30:29 PM PST 24 |
| Peak memory | 197880 kb |
| Host | smart-d91d9b50-4860-4ce0-9e3b-c07693c24fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074920951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1074920951 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.4255008228 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 134188299866 ps |
| CPU time | 497.51 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:43:42 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-2ca5ee9b-9d91-470c-816a-b5f4f7ec2844 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255008228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4255008228 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.744335933 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5722348523966 ps |
| CPU time | 1459.64 seconds |
| Started | Jan 03 12:33:08 PM PST 24 |
| Finished | Jan 03 12:59:19 PM PST 24 |
| Peak memory | 191004 kb |
| Host | smart-fc512d6f-95e8-47d9-a234-a2b7428cacd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744335933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.744335933 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.538971780 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 725864498517 ps |
| CPU time | 2064.49 seconds |
| Started | Jan 03 12:35:06 PM PST 24 |
| Finished | Jan 03 01:10:57 PM PST 24 |
| Peak memory | 190728 kb |
| Host | smart-a45afd87-defa-4850-8623-a747d55093cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538971780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.538971780 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.3366752445 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1137760454588 ps |
| CPU time | 1124.47 seconds |
| Started | Jan 03 12:33:24 PM PST 24 |
| Finished | Jan 03 12:53:44 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-350c0c3f-edff-457a-97cc-99fdcaabc51a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366752445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 3366752445 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.984856040 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 839759626190 ps |
| CPU time | 732.27 seconds |
| Started | Jan 03 12:33:11 PM PST 24 |
| Finished | Jan 03 12:46:53 PM PST 24 |
| Peak memory | 190904 kb |
| Host | smart-a14b13ed-66c8-457c-b2c7-eccda31e9da0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984856040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.984856040 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.3448567873 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2619544173248 ps |
| CPU time | 1011.74 seconds |
| Started | Jan 03 12:34:07 PM PST 24 |
| Finished | Jan 03 12:52:21 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-85eca0b2-a477-4967-b8f8-843400a72b70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448567873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3448567873 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.1379855140 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 518095368016 ps |
| CPU time | 633.93 seconds |
| Started | Jan 03 12:35:15 PM PST 24 |
| Finished | Jan 03 12:47:17 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-82b08ed7-9f42-424c-97d9-64c665f816c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379855140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1379855140 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.762275126 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 117788863734 ps |
| CPU time | 235.34 seconds |
| Started | Jan 03 12:34:07 PM PST 24 |
| Finished | Jan 03 12:39:23 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-c1e3b206-c7ec-48b6-801a-1f39b688c991 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762275126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.762275126 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.3492671416 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 352569987845 ps |
| CPU time | 783.69 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:48:38 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-b3db4b70-e9a1-4ddf-b4df-57c392a67bbd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492671416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3492671416 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.3962057229 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 227388913098 ps |
| CPU time | 822.56 seconds |
| Started | Jan 03 12:34:07 PM PST 24 |
| Finished | Jan 03 12:49:14 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-fa969c15-3403-4fbb-92f9-6ee15998f7a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962057229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3962057229 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.2454605440 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 175209978287 ps |
| CPU time | 303.81 seconds |
| Started | Jan 03 12:34:29 PM PST 24 |
| Finished | Jan 03 12:40:52 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-408b04f4-f4f8-45a6-97d2-e17784b6caa5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454605440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2454605440 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.3425288442 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 151661333308 ps |
| CPU time | 1620.17 seconds |
| Started | Jan 03 12:34:30 PM PST 24 |
| Finished | Jan 03 01:02:57 PM PST 24 |
| Peak memory | 193896 kb |
| Host | smart-eda29f62-a5f3-4ba4-8a97-bc6b9e62718a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425288442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3425288442 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.2531438181 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 300118672389 ps |
| CPU time | 2631.59 seconds |
| Started | Jan 03 12:33:21 PM PST 24 |
| Finished | Jan 03 01:18:34 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-91ac66e9-fa3f-4717-a87c-b54b0c00a853 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531438181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2531438181 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.3077103711 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 749344009687 ps |
| CPU time | 559.94 seconds |
| Started | Jan 03 12:34:13 PM PST 24 |
| Finished | Jan 03 12:44:54 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-7f313240-b205-4e5b-bff3-1b7b8fcc7e21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077103711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3077103711 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.2139798907 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 99277261571 ps |
| CPU time | 156.54 seconds |
| Started | Jan 03 12:33:17 PM PST 24 |
| Finished | Jan 03 12:37:14 PM PST 24 |
| Peak memory | 191064 kb |
| Host | smart-9309f024-1021-48f6-ac92-f476a012b244 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139798907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2139798907 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.2206195364 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 117290517702 ps |
| CPU time | 1864.17 seconds |
| Started | Jan 03 12:34:48 PM PST 24 |
| Finished | Jan 03 01:07:43 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-fcc88a2c-cf3c-481b-b3f4-a70315c6cda8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206195364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2206195364 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.4022750017 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 188107947988 ps |
| CPU time | 208.53 seconds |
| Started | Jan 03 12:34:40 PM PST 24 |
| Finished | Jan 03 12:39:26 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-e8c5adcf-4fb6-455c-b82d-8154aab0228a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022750017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4022750017 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1367271819 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 32371687 ps |
| CPU time | 0.76 seconds |
| Started | Jan 03 12:30:02 PM PST 24 |
| Finished | Jan 03 12:30:47 PM PST 24 |
| Peak memory | 192128 kb |
| Host | smart-98a94093-c0e4-4ff0-b037-cc1e91845d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367271819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.1367271819 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.812223644 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 94843606049 ps |
| CPU time | 92.18 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:36:46 PM PST 24 |
| Peak memory | 194168 kb |
| Host | smart-3f9acfaa-3fe7-4c5d-8558-e2655df33b77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812223644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.812223644 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.2064930305 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 890972328910 ps |
| CPU time | 441.44 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:42:38 PM PST 24 |
| Peak memory | 194016 kb |
| Host | smart-7dfa995c-c187-42d0-96c3-9e295171d609 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064930305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2064930305 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.2024124443 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 111861372842 ps |
| CPU time | 242.54 seconds |
| Started | Jan 03 12:33:38 PM PST 24 |
| Finished | Jan 03 12:39:09 PM PST 24 |
| Peak memory | 193156 kb |
| Host | smart-b11ab6b6-89cf-45f5-a9c1-2876c00c4d0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024124443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2024124443 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.606930050 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 204791499852 ps |
| CPU time | 458.83 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:43:07 PM PST 24 |
| Peak memory | 193772 kb |
| Host | smart-99a5f94d-e25c-4a01-87cc-490c892ce96d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606930050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.606930050 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1147815948 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 397815898232 ps |
| CPU time | 107.66 seconds |
| Started | Jan 03 12:43:15 PM PST 24 |
| Finished | Jan 03 12:46:26 PM PST 24 |
| Peak memory | 182548 kb |
| Host | smart-8eedbbca-792b-4f17-b82e-e742eddb2db5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147815948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.1147815948 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3255780993 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 483118876902 ps |
| CPU time | 666.35 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:46:23 PM PST 24 |
| Peak memory | 182892 kb |
| Host | smart-8b3eb872-d303-4402-85a0-bad5a222946a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255780993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3255780993 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.3629739199 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1057722248882 ps |
| CPU time | 1042.37 seconds |
| Started | Jan 03 12:33:11 PM PST 24 |
| Finished | Jan 03 12:52:03 PM PST 24 |
| Peak memory | 190988 kb |
| Host | smart-5d9a8148-e80c-4032-a500-f71b8e551db5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629739199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 3629739199 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3346613197 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 408362020476 ps |
| CPU time | 386.79 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 182816 kb |
| Host | smart-7e6a9087-4946-4c2a-bc7f-915d83be201f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346613197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.3346613197 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.2846336973 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 82678588054 ps |
| CPU time | 97.66 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:37:02 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-4f841242-a1a5-4661-be70-852fe4ed1420 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846336973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2846336973 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.2365436183 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 349985833934 ps |
| CPU time | 458.39 seconds |
| Started | Jan 03 12:34:17 PM PST 24 |
| Finished | Jan 03 12:43:05 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-f77bc0f9-6291-42c6-8d66-7e2156b385ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365436183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2365436183 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.124842289 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 96309633085 ps |
| CPU time | 277.05 seconds |
| Started | Jan 03 12:36:00 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 190564 kb |
| Host | smart-7322f1b9-9191-4164-b46d-64ca2e03d7b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124842289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.124842289 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.347037856 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 916523746744 ps |
| CPU time | 1568.87 seconds |
| Started | Jan 03 12:34:26 PM PST 24 |
| Finished | Jan 03 01:02:51 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-9bb71a68-4e07-49c6-9e92-76d6c6ea1b3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347037856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.347037856 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2295267097 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 35550488 ps |
| CPU time | 0.7 seconds |
| Started | Jan 03 12:29:52 PM PST 24 |
| Finished | Jan 03 12:30:35 PM PST 24 |
| Peak memory | 194292 kb |
| Host | smart-fa389f6a-83a9-4f67-af66-3ac038ab4439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295267097 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2295267097 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2114001953 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 329561715 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:30:25 PM PST 24 |
| Finished | Jan 03 12:31:23 PM PST 24 |
| Peak memory | 183612 kb |
| Host | smart-cfa1ad88-a03b-426f-ab2a-0fd71382098f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114001953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.2114001953 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.3586395869 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 146774883890 ps |
| CPU time | 737.72 seconds |
| Started | Jan 03 12:34:03 PM PST 24 |
| Finished | Jan 03 12:47:39 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-3ad2fdfc-9de1-4f78-ae82-cc14557bb639 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586395869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3586395869 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.4028151044 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 413653048825 ps |
| CPU time | 234.1 seconds |
| Started | Jan 03 12:35:12 PM PST 24 |
| Finished | Jan 03 12:40:31 PM PST 24 |
| Peak memory | 194248 kb |
| Host | smart-ca7c5531-5000-4efa-bcb5-426a7478010b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028151044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4028151044 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.1557389175 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 424614888015 ps |
| CPU time | 1083.4 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:53:28 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-10a40984-7bfc-4a09-b275-64151ac87863 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557389175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1557389175 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.479665266 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 182713827081 ps |
| CPU time | 426.96 seconds |
| Started | Jan 03 12:34:42 PM PST 24 |
| Finished | Jan 03 12:43:07 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-12d6add2-bbdb-439e-873d-e4f33e4e76c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479665266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.479665266 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.1773359590 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 207153485345 ps |
| CPU time | 198.11 seconds |
| Started | Jan 03 12:34:23 PM PST 24 |
| Finished | Jan 03 12:39:03 PM PST 24 |
| Peak memory | 191108 kb |
| Host | smart-e5eb7108-cb60-4bf8-bc56-ea726dab32d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773359590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1773359590 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.1462805404 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 453156337662 ps |
| CPU time | 303.32 seconds |
| Started | Jan 03 12:35:02 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 194512 kb |
| Host | smart-0319eddb-1574-49ca-bcfd-c0e40239cf5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462805404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1462805404 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.3420057693 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 551385651060 ps |
| CPU time | 442.5 seconds |
| Started | Jan 03 12:34:40 PM PST 24 |
| Finished | Jan 03 12:44:19 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-845bc805-2a35-498e-87f2-de407472969f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420057693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3420057693 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.1414403592 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 135212249073 ps |
| CPU time | 651.55 seconds |
| Started | Jan 03 12:33:28 PM PST 24 |
| Finished | Jan 03 12:45:51 PM PST 24 |
| Peak memory | 193120 kb |
| Host | smart-62f9cb33-8685-49da-951a-998c2f02709d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414403592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1414403592 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.2045628684 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 620611785426 ps |
| CPU time | 274.27 seconds |
| Started | Jan 03 12:34:33 PM PST 24 |
| Finished | Jan 03 12:40:15 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-b4bbacd1-87bc-4dc4-900a-bc11f4aad1bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045628684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2045628684 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.1472889908 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3029270683526 ps |
| CPU time | 1238.85 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:56:07 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-9bc31b95-d276-4a67-b61c-158d4f2501b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472889908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1472889908 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2516721135 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 18100076 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:30:35 PM PST 24 |
| Finished | Jan 03 12:31:37 PM PST 24 |
| Peak memory | 182856 kb |
| Host | smart-851cb141-4338-4dac-8fb4-94778d2129c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516721135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2516721135 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.951266535 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 323639827046 ps |
| CPU time | 524.98 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:44:15 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-4638d0a2-118e-490c-af1f-00c45bf7283a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951266535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.951266535 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.4109464277 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 26766970616 ps |
| CPU time | 104.37 seconds |
| Started | Jan 03 12:34:11 PM PST 24 |
| Finished | Jan 03 12:37:12 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-644ccb36-cbe9-454f-80a3-4a019ad33cd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109464277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4109464277 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.2558003722 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 557319541606 ps |
| CPU time | 354.61 seconds |
| Started | Jan 03 12:34:25 PM PST 24 |
| Finished | Jan 03 12:41:45 PM PST 24 |
| Peak memory | 190952 kb |
| Host | smart-c5e00ee9-5f80-4d8c-aa25-729b071bd762 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558003722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2558003722 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3832403884 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 125323937169 ps |
| CPU time | 61.82 seconds |
| Started | Jan 03 12:34:03 PM PST 24 |
| Finished | Jan 03 12:36:34 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-98734dd5-262a-4e56-93f0-0c2a5b277efb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832403884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.3832403884 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.494438922 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 326508900390 ps |
| CPU time | 1266.33 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:56:42 PM PST 24 |
| Peak memory | 191020 kb |
| Host | smart-7b56f3f0-df5d-4678-abb0-c25745f187ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494438922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.494438922 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.3148124064 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 93922512553 ps |
| CPU time | 780.76 seconds |
| Started | Jan 03 12:34:01 PM PST 24 |
| Finished | Jan 03 12:48:28 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-52390de7-b101-4d6d-9b2d-3bbc996ba429 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148124064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3148124064 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.4253707141 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 215202483878 ps |
| CPU time | 962.34 seconds |
| Started | Jan 03 12:33:47 PM PST 24 |
| Finished | Jan 03 12:51:21 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-33e40a20-9f9b-4600-9e5c-f2775150ab0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253707141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4253707141 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.4076040236 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 154827384644 ps |
| CPU time | 639.26 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:45:37 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-8e71eda2-7e3c-4743-b398-3836b514b175 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076040236 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.4076040236 |
| Directory | /workspace/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1358798891 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3475870995795 ps |
| CPU time | 861.43 seconds |
| Started | Jan 03 12:33:18 PM PST 24 |
| Finished | Jan 03 12:49:05 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-ec081448-5085-4218-a50c-48e7aaa82ef8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358798891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1358798891 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.1805394418 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 85761741316 ps |
| CPU time | 194.07 seconds |
| Started | Jan 03 12:34:36 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-27b92cba-d775-480e-9574-a843a1a8f55e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805394418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1805394418 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.3522935540 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1586492808331 ps |
| CPU time | 1435.97 seconds |
| Started | Jan 03 12:35:13 PM PST 24 |
| Finished | Jan 03 01:00:33 PM PST 24 |
| Peak memory | 194144 kb |
| Host | smart-56cfceb9-c340-468e-8913-52bd0389a15a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522935540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 3522935540 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.2002680822 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 215643439174 ps |
| CPU time | 370.8 seconds |
| Started | Jan 03 12:34:25 PM PST 24 |
| Finished | Jan 03 12:42:11 PM PST 24 |
| Peak memory | 191088 kb |
| Host | smart-6e3a2148-d182-431a-84a5-3cae7f131d84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002680822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .2002680822 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.2945262052 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1139072265103 ps |
| CPU time | 254.4 seconds |
| Started | Jan 03 12:33:28 PM PST 24 |
| Finished | Jan 03 12:39:02 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-52aa4660-1118-487b-aae6-830f5fdefc88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945262052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2945262052 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.334653705 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 143106805336 ps |
| CPU time | 181.82 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:38:27 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-858f6648-6787-4740-8429-99cec6cf42aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334653705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.334653705 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3597368452 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 439648003631 ps |
| CPU time | 462.83 seconds |
| Started | Jan 03 12:34:18 PM PST 24 |
| Finished | Jan 03 12:43:42 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-f25637f0-3b18-44ef-94ab-414d13661e10 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597368452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.3597368452 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.1830855700 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 966293701561 ps |
| CPU time | 550.7 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:44:31 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-d4298c4f-6931-43c8-a530-de7c4e3c891d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830855700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1830855700 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1080118437 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 64687216288 ps |
| CPU time | 33.12 seconds |
| Started | Jan 03 12:34:26 PM PST 24 |
| Finished | Jan 03 12:37:15 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-d2d6b507-e67b-49f3-b54c-9c4677a918e8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080118437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1080118437 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.2614909326 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 948916320107 ps |
| CPU time | 376.26 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 191068 kb |
| Host | smart-fa5e98dc-9796-432b-b63f-7dd5fdac7353 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614909326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2614909326 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.1158628978 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 40277108652 ps |
| CPU time | 1424.29 seconds |
| Started | Jan 03 12:34:48 PM PST 24 |
| Finished | Jan 03 12:59:51 PM PST 24 |
| Peak memory | 182912 kb |
| Host | smart-29b567e7-1a83-4e23-b3a8-4f1155c091bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158628978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1158628978 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.76980458 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 56569918671 ps |
| CPU time | 183.17 seconds |
| Started | Jan 03 12:33:19 PM PST 24 |
| Finished | Jan 03 12:38:10 PM PST 24 |
| Peak memory | 191124 kb |
| Host | smart-7494398d-d511-45c2-9219-466067748250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76980458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.76980458 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.3974231977 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 829096967995 ps |
| CPU time | 269.8 seconds |
| Started | Jan 03 12:33:47 PM PST 24 |
| Finished | Jan 03 12:40:18 PM PST 24 |
| Peak memory | 191092 kb |
| Host | smart-d58c96b8-9422-4897-85ae-bdf541caf3fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974231977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3974231977 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.1231691036 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 31368919661 ps |
| CPU time | 23.52 seconds |
| Started | Jan 03 12:33:41 PM PST 24 |
| Finished | Jan 03 12:35:19 PM PST 24 |
| Peak memory | 191412 kb |
| Host | smart-b21a8f46-aec4-42a0-a3d1-562122f16a7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231691036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1231691036 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.1195494573 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 47771032564 ps |
| CPU time | 133.2 seconds |
| Started | Jan 03 12:34:37 PM PST 24 |
| Finished | Jan 03 12:38:05 PM PST 24 |
| Peak memory | 191104 kb |
| Host | smart-c110d7f7-714c-4936-8e50-7b4407982042 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195494573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1195494573 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.949984174 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 87626006966 ps |
| CPU time | 140.59 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:37:55 PM PST 24 |
| Peak memory | 191100 kb |
| Host | smart-a63b2449-e60a-490f-aed8-ed29d54348d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949984174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.949984174 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.3768261876 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 656007461150 ps |
| CPU time | 375.82 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:41:48 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-e5680609-73bb-405d-b837-1cf079c6572a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768261876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3768261876 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.781360946 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 395420254341 ps |
| CPU time | 205.66 seconds |
| Started | Jan 03 12:34:18 PM PST 24 |
| Finished | Jan 03 12:39:25 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-e2fccd29-25ae-4120-bf73-24bb8fbd95d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781360946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.781360946 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.1273371657 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1036074160532 ps |
| CPU time | 544.14 seconds |
| Started | Jan 03 12:44:23 PM PST 24 |
| Finished | Jan 03 12:54:45 PM PST 24 |
| Peak memory | 195392 kb |
| Host | smart-3c32ff6d-fcdf-4d48-a49c-9094bf88fef9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273371657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .1273371657 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.2064510516 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 52058297545 ps |
| CPU time | 77.94 seconds |
| Started | Jan 03 12:33:28 PM PST 24 |
| Finished | Jan 03 12:36:06 PM PST 24 |
| Peak memory | 192300 kb |
| Host | smart-951ca558-bc02-4ca5-b75f-66ba2ed66c75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064510516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2064510516 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.3978107654 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 22912977407 ps |
| CPU time | 54.67 seconds |
| Started | Jan 03 12:33:47 PM PST 24 |
| Finished | Jan 03 12:36:36 PM PST 24 |
| Peak memory | 182800 kb |
| Host | smart-d6124373-007d-429d-85d2-36b6fb741938 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978107654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3978107654 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.3344068211 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 449105145899 ps |
| CPU time | 382.18 seconds |
| Started | Jan 03 12:34:19 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-8003a1cb-e59d-46d9-9846-378b0000e7fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344068211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3344068211 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.3294712734 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 226631004628 ps |
| CPU time | 416.49 seconds |
| Started | Jan 03 12:34:25 PM PST 24 |
| Finished | Jan 03 12:42:35 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-ca4a44fe-d6c5-410c-af08-f8a53cb1e6dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294712734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3294712734 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.3556945753 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 144636209687 ps |
| CPU time | 851.76 seconds |
| Started | Jan 03 12:34:41 PM PST 24 |
| Finished | Jan 03 12:50:01 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-2f7b8c9a-6daa-45c8-a6d5-57909073e1a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556945753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3556945753 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.1934405419 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 98584615698 ps |
| CPU time | 801.13 seconds |
| Started | Jan 03 12:34:25 PM PST 24 |
| Finished | Jan 03 12:48:56 PM PST 24 |
| Peak memory | 193716 kb |
| Host | smart-e63893fd-1863-4059-a82f-2a4ef31e1932 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934405419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1934405419 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.1169497694 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 558902156787 ps |
| CPU time | 220.54 seconds |
| Started | Jan 03 12:34:14 PM PST 24 |
| Finished | Jan 03 12:39:12 PM PST 24 |
| Peak memory | 191064 kb |
| Host | smart-2256cfdb-f5b0-4404-8f4c-aac812b39c6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169497694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1169497694 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.4001531567 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 129394474438 ps |
| CPU time | 69.2 seconds |
| Started | Jan 03 12:34:45 PM PST 24 |
| Finished | Jan 03 12:38:04 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-386f468e-fe4a-43f9-8b5e-1f4df7c0aa11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001531567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.4001531567 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.830467990 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 159002677432 ps |
| CPU time | 176.01 seconds |
| Started | Jan 03 12:35:01 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 191068 kb |
| Host | smart-92a11188-4ee5-4ef9-be5c-77d9ad280ad2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830467990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.830467990 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.1184583445 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 728859307518 ps |
| CPU time | 644.27 seconds |
| Started | Jan 03 12:35:19 PM PST 24 |
| Finished | Jan 03 12:47:36 PM PST 24 |
| Peak memory | 190420 kb |
| Host | smart-d53513e5-001a-4da1-8971-07d69235f746 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184583445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .1184583445 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.1539015787 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 300511428164 ps |
| CPU time | 1022.26 seconds |
| Started | Jan 03 12:33:18 PM PST 24 |
| Finished | Jan 03 12:51:51 PM PST 24 |
| Peak memory | 191028 kb |
| Host | smart-37a074b4-401c-4602-a5d5-ba236f46c049 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539015787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1539015787 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.3948421434 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 397170973277 ps |
| CPU time | 137.14 seconds |
| Started | Jan 03 12:34:19 PM PST 24 |
| Finished | Jan 03 12:38:02 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-c957aea1-79cf-475b-b4d2-54791a0069ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948421434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3948421434 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.1558937913 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 160156546856 ps |
| CPU time | 194.1 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:38:13 PM PST 24 |
| Peak memory | 191240 kb |
| Host | smart-bb3a4938-1d3e-422b-90fb-3a62db69bc9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558937913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1558937913 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3746238897 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 281667506389 ps |
| CPU time | 248.56 seconds |
| Started | Jan 03 12:33:28 PM PST 24 |
| Finished | Jan 03 12:38:57 PM PST 24 |
| Peak memory | 182816 kb |
| Host | smart-b5b02cb4-1742-4fe1-881a-ed95b78b9058 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746238897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3746238897 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.722734693 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 408986212848 ps |
| CPU time | 454.63 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:43:10 PM PST 24 |
| Peak memory | 190984 kb |
| Host | smart-4f156e64-e0a4-4083-8fd9-9689b46a92a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722734693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all. 722734693 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.3736656968 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 140982808353 ps |
| CPU time | 468.89 seconds |
| Started | Jan 03 12:34:02 PM PST 24 |
| Finished | Jan 03 12:43:17 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-54c64fff-956e-4db1-a956-17bc4b56b972 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736656968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3736656968 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.3278027237 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 36662974587 ps |
| CPU time | 44.37 seconds |
| Started | Jan 03 12:34:06 PM PST 24 |
| Finished | Jan 03 12:36:18 PM PST 24 |
| Peak memory | 182804 kb |
| Host | smart-db2be79e-34e2-4d73-8c6b-b60b26cd2929 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278027237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3278027237 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.1874752474 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 96282668704 ps |
| CPU time | 132.69 seconds |
| Started | Jan 03 12:42:48 PM PST 24 |
| Finished | Jan 03 12:46:28 PM PST 24 |
| Peak memory | 190072 kb |
| Host | smart-0da58629-0416-4ee9-bd34-848ad90d0ceb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874752474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1874752474 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.1465830672 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 785290825802 ps |
| CPU time | 371.54 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:41:46 PM PST 24 |
| Peak memory | 194252 kb |
| Host | smart-c50149de-53b8-47ba-8896-8190b3451295 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465830672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1465830672 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3927472100 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 37847964 ps |
| CPU time | 1.4 seconds |
| Started | Jan 03 12:28:35 PM PST 24 |
| Finished | Jan 03 12:28:53 PM PST 24 |
| Peak memory | 183324 kb |
| Host | smart-0a54ce86-d58e-4117-9dfa-acdae388d60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927472100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.3927472100 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1012503717 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 15588923 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:28:47 PM PST 24 |
| Finished | Jan 03 12:29:17 PM PST 24 |
| Peak memory | 182420 kb |
| Host | smart-2cfa61ba-dee7-4d7b-890f-962b4f2f8209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012503717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.1012503717 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1882238060 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 25220772 ps |
| CPU time | 0.71 seconds |
| Started | Jan 03 12:29:39 PM PST 24 |
| Finished | Jan 03 12:30:17 PM PST 24 |
| Peak memory | 195808 kb |
| Host | smart-69538846-df3c-4f97-ba14-ccb3c192a9c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882238060 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1882238060 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1203439675 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 14682005 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:28:35 PM PST 24 |
| Finished | Jan 03 12:28:52 PM PST 24 |
| Peak memory | 183136 kb |
| Host | smart-53f2b8b6-1c31-4657-9932-2565378e23fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203439675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1203439675 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2744864236 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 28939894 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:28:47 PM PST 24 |
| Finished | Jan 03 12:29:18 PM PST 24 |
| Peak memory | 182840 kb |
| Host | smart-b2f08ba3-5ce4-4cec-9a2e-7b9949de2adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744864236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2744864236 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.853453757 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29109187 ps |
| CPU time | 0.73 seconds |
| Started | Jan 03 12:29:19 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 191988 kb |
| Host | smart-0631ca2d-30dc-4c10-91c0-0244589c58a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853453757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim er_same_csr_outstanding.853453757 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4284473042 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 42610899 ps |
| CPU time | 1.91 seconds |
| Started | Jan 03 12:28:47 PM PST 24 |
| Finished | Jan 03 12:29:19 PM PST 24 |
| Peak memory | 197604 kb |
| Host | smart-03172ee2-c879-439d-aea6-51cb94c11b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284473042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.4284473042 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1365155698 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 48717791 ps |
| CPU time | 0.82 seconds |
| Started | Jan 03 12:28:47 PM PST 24 |
| Finished | Jan 03 12:29:18 PM PST 24 |
| Peak memory | 193316 kb |
| Host | smart-3f8ed0eb-20f8-4560-99c9-fc983f0e4513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365155698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.1365155698 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2274782472 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 19091308 ps |
| CPU time | 0.59 seconds |
| Started | Jan 03 12:30:06 PM PST 24 |
| Finished | Jan 03 12:30:53 PM PST 24 |
| Peak memory | 183108 kb |
| Host | smart-b9a886b6-16c6-4788-b0e8-c52948c74375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274782472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.2274782472 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3381582835 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 293751432 ps |
| CPU time | 2.61 seconds |
| Started | Jan 03 12:29:11 PM PST 24 |
| Finished | Jan 03 12:29:41 PM PST 24 |
| Peak memory | 191756 kb |
| Host | smart-f19dcf11-7830-4a28-b804-8a50fa7a0315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381582835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.3381582835 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2144850713 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 48626901 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:29:15 PM PST 24 |
| Finished | Jan 03 12:29:44 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-c6545dc6-9c27-47ad-bb5a-5c8a1a7e238f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144850713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.2144850713 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4093774817 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 265207294 ps |
| CPU time | 0.84 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 196304 kb |
| Host | smart-da4bae3b-9dd8-4019-a79a-f9d06f7e5f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093774817 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4093774817 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3434301993 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 36258314 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:29:59 PM PST 24 |
| Peak memory | 183156 kb |
| Host | smart-91a4ba84-bb23-4665-896a-89d8fd98e0dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434301993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3434301993 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4249620408 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 30226902 ps |
| CPU time | 0.59 seconds |
| Started | Jan 03 12:29:56 PM PST 24 |
| Finished | Jan 03 12:30:40 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-0879faa5-0456-4984-83ea-0c640d7301ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249620408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4249620408 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4159218343 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 34341855 ps |
| CPU time | 0.74 seconds |
| Started | Jan 03 12:29:44 PM PST 24 |
| Finished | Jan 03 12:30:25 PM PST 24 |
| Peak memory | 192112 kb |
| Host | smart-fe6a124e-07b5-4b4f-a6cc-62180fe5decd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159218343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.4159218343 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3199402079 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 33796967 ps |
| CPU time | 1.59 seconds |
| Started | Jan 03 12:29:05 PM PST 24 |
| Finished | Jan 03 12:29:33 PM PST 24 |
| Peak memory | 197916 kb |
| Host | smart-dcbdccf2-b87c-4298-a3b2-7da26d5a9ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199402079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3199402079 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1704726307 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 290912630 ps |
| CPU time | 1.02 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:30:00 PM PST 24 |
| Peak memory | 195208 kb |
| Host | smart-b871843b-3d21-4dee-b93f-1c07f1694c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704726307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.1704726307 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3233190269 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 25026775 ps |
| CPU time | 0.67 seconds |
| Started | Jan 03 12:30:31 PM PST 24 |
| Finished | Jan 03 12:31:32 PM PST 24 |
| Peak memory | 193736 kb |
| Host | smart-f2d5d816-7bd2-4f0c-9a40-efb90515ba41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233190269 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3233190269 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3823520255 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 18338564 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:42 PM PST 24 |
| Finished | Jan 03 12:31:46 PM PST 24 |
| Peak memory | 182704 kb |
| Host | smart-72c40eea-b5e7-4ecc-b979-a702e755b55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823520255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3823520255 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1367103065 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 16292727 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 182868 kb |
| Host | smart-6136d949-3273-4bc6-a454-84bb67cb84fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367103065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1367103065 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4225794829 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 66501449 ps |
| CPU time | 0.6 seconds |
| Started | Jan 03 12:30:45 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 192400 kb |
| Host | smart-ad91257f-24de-461b-be78-bd8df4619b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225794829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.4225794829 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4019903922 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 89610683 ps |
| CPU time | 1.99 seconds |
| Started | Jan 03 12:30:31 PM PST 24 |
| Finished | Jan 03 12:31:33 PM PST 24 |
| Peak memory | 197956 kb |
| Host | smart-b60626f3-6a5d-4992-a65f-61ee86e31d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019903922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4019903922 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.523561431 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 47084148 ps |
| CPU time | 0.79 seconds |
| Started | Jan 03 12:30:41 PM PST 24 |
| Finished | Jan 03 12:31:45 PM PST 24 |
| Peak memory | 193312 kb |
| Host | smart-c657fa37-cfc2-4f76-bf1b-cd3d91a1da3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523561431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in tg_err.523561431 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2242313566 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 45270871 ps |
| CPU time | 1.17 seconds |
| Started | Jan 03 12:30:31 PM PST 24 |
| Finished | Jan 03 12:31:32 PM PST 24 |
| Peak memory | 197872 kb |
| Host | smart-483ef181-34b9-4625-bf3f-a6be43491dc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242313566 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2242313566 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3702705309 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 29239843 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:30:29 PM PST 24 |
| Finished | Jan 03 12:31:29 PM PST 24 |
| Peak memory | 183252 kb |
| Host | smart-848abd93-b2a5-445f-832f-5bfcf73ea64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702705309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3702705309 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4021776482 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 12666579 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:37 PM PST 24 |
| Finished | Jan 03 12:31:39 PM PST 24 |
| Peak memory | 182092 kb |
| Host | smart-78064ef6-1795-4f97-b7a1-8100d3984b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021776482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4021776482 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2786128129 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 119215800 ps |
| CPU time | 0.78 seconds |
| Started | Jan 03 12:30:25 PM PST 24 |
| Finished | Jan 03 12:31:23 PM PST 24 |
| Peak memory | 192104 kb |
| Host | smart-eaba2468-adad-46a8-b13f-779cad1015ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786128129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.2786128129 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2786544176 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 182969826 ps |
| CPU time | 2.22 seconds |
| Started | Jan 03 12:30:48 PM PST 24 |
| Finished | Jan 03 12:31:55 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-0b2153bb-c486-4a3a-b137-bf91b7e5e429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786544176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2786544176 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1817786479 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 50626519 ps |
| CPU time | 0.81 seconds |
| Started | Jan 03 12:30:37 PM PST 24 |
| Finished | Jan 03 12:31:42 PM PST 24 |
| Peak memory | 183332 kb |
| Host | smart-538a772e-7dbb-483e-9a2a-33f1ad65f427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817786479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.1817786479 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1886396097 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 85251471 ps |
| CPU time | 0.83 seconds |
| Started | Jan 03 12:30:31 PM PST 24 |
| Finished | Jan 03 12:31:32 PM PST 24 |
| Peak memory | 196312 kb |
| Host | smart-6dbe7d56-619f-40ed-a249-2b4e49ef84d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886396097 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1886396097 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3318697096 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 34588652 ps |
| CPU time | 0.67 seconds |
| Started | Jan 03 12:30:44 PM PST 24 |
| Finished | Jan 03 12:31:49 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-1d874c84-b6cf-4e63-8f98-1360d02cd966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318697096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3318697096 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3491599359 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 38594303 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:44 PM PST 24 |
| Finished | Jan 03 12:31:50 PM PST 24 |
| Peak memory | 182896 kb |
| Host | smart-4184c8b0-8767-465a-b7a5-a70c7f30b477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491599359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3491599359 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1932991536 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 25684752 ps |
| CPU time | 0.63 seconds |
| Started | Jan 03 12:30:43 PM PST 24 |
| Finished | Jan 03 12:31:49 PM PST 24 |
| Peak memory | 192044 kb |
| Host | smart-f305857d-fd45-4998-b5f8-9a5a85c50f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932991536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t imer_same_csr_outstanding.1932991536 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.83000671 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 43570666 ps |
| CPU time | 1.03 seconds |
| Started | Jan 03 12:30:44 PM PST 24 |
| Finished | Jan 03 12:31:49 PM PST 24 |
| Peak memory | 197836 kb |
| Host | smart-cafacf39-0f9b-415f-8d82-3225473c495c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83000671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.83000671 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2501016984 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 717271583 ps |
| CPU time | 1.02 seconds |
| Started | Jan 03 12:30:45 PM PST 24 |
| Finished | Jan 03 12:31:51 PM PST 24 |
| Peak memory | 195232 kb |
| Host | smart-879c3b65-d290-43a6-9f37-0412aa654f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501016984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.2501016984 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.109722526 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 44679687 ps |
| CPU time | 0.79 seconds |
| Started | Jan 03 12:30:39 PM PST 24 |
| Finished | Jan 03 12:31:42 PM PST 24 |
| Peak memory | 196580 kb |
| Host | smart-effc0265-0a1b-46e1-821e-70489c9516d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109722526 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.109722526 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3511673146 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 114296821 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:43 PM PST 24 |
| Finished | Jan 03 12:31:48 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-2412a864-8c05-4294-9b75-c9358c7c3c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511673146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3511673146 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2938179122 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 39726877 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:48 PM PST 24 |
| Finished | Jan 03 12:31:55 PM PST 24 |
| Peak memory | 182524 kb |
| Host | smart-274da2d4-3161-4ff9-9a5c-9bbc10e9b6c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938179122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2938179122 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.148203266 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 32967216 ps |
| CPU time | 0.72 seconds |
| Started | Jan 03 12:30:27 PM PST 24 |
| Finished | Jan 03 12:31:26 PM PST 24 |
| Peak memory | 193520 kb |
| Host | smart-546ea0b3-abf0-4669-a628-e2bf082e3184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148203266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti mer_same_csr_outstanding.148203266 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3080761995 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 663237772 ps |
| CPU time | 2.81 seconds |
| Started | Jan 03 12:30:40 PM PST 24 |
| Finished | Jan 03 12:31:47 PM PST 24 |
| Peak memory | 197940 kb |
| Host | smart-af90f611-e5ed-4703-8d5f-0b7a61a14619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080761995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3080761995 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1894552012 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 70872743 ps |
| CPU time | 1 seconds |
| Started | Jan 03 12:30:32 PM PST 24 |
| Finished | Jan 03 12:31:34 PM PST 24 |
| Peak memory | 195340 kb |
| Host | smart-781788da-55ab-4117-ac44-8a68156ff871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894552012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.1894552012 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3433396788 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 22013347 ps |
| CPU time | 0.96 seconds |
| Started | Jan 03 12:30:31 PM PST 24 |
| Finished | Jan 03 12:31:32 PM PST 24 |
| Peak memory | 197224 kb |
| Host | smart-7b9a8ba4-a513-47e6-8cd2-3bc4d9fcd54f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433396788 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3433396788 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2690596849 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 27172098 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:36 PM PST 24 |
| Finished | Jan 03 12:31:37 PM PST 24 |
| Peak memory | 183128 kb |
| Host | smart-5435f59e-c9d9-421f-8820-297b2ec11b77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690596849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2690596849 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.122356253 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 32631794 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:20 PM PST 24 |
| Finished | Jan 03 12:31:14 PM PST 24 |
| Peak memory | 181984 kb |
| Host | smart-117f947a-93e0-4451-9327-5ccd86115c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122356253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.122356253 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1886211296 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 16972012 ps |
| CPU time | 0.64 seconds |
| Started | Jan 03 12:30:43 PM PST 24 |
| Finished | Jan 03 12:31:48 PM PST 24 |
| Peak memory | 191672 kb |
| Host | smart-f074d519-7f26-4a84-a9fc-7e3fb666329e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886211296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.1886211296 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4258404462 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 179313298 ps |
| CPU time | 3.12 seconds |
| Started | Jan 03 12:30:39 PM PST 24 |
| Finished | Jan 03 12:31:45 PM PST 24 |
| Peak memory | 197928 kb |
| Host | smart-74d17ef7-eb41-4f10-b161-b9f70d38de4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258404462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4258404462 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.414838080 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 98574930 ps |
| CPU time | 0.58 seconds |
| Started | Jan 03 12:30:32 PM PST 24 |
| Finished | Jan 03 12:31:34 PM PST 24 |
| Peak memory | 193516 kb |
| Host | smart-b608f7d7-f186-441a-897b-eb41aa05235a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414838080 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.414838080 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.278894896 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15892007 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:24 PM PST 24 |
| Finished | Jan 03 12:31:20 PM PST 24 |
| Peak memory | 183124 kb |
| Host | smart-89b3f7fa-d1ae-42be-9992-767bed6bc8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278894896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.278894896 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.317598551 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 79117338 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:31 PM PST 24 |
| Finished | Jan 03 12:31:32 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-a8bf406a-ddbc-4b83-bd9b-e986d71cd16e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317598551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.317598551 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2474072273 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 47438079 ps |
| CPU time | 0.61 seconds |
| Started | Jan 03 12:30:27 PM PST 24 |
| Finished | Jan 03 12:31:25 PM PST 24 |
| Peak memory | 192036 kb |
| Host | smart-e0f7a700-a304-4b08-b32a-50c57fcb7ec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474072273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.2474072273 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.535613572 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1057499377 ps |
| CPU time | 1.28 seconds |
| Started | Jan 03 12:30:41 PM PST 24 |
| Finished | Jan 03 12:31:47 PM PST 24 |
| Peak memory | 197580 kb |
| Host | smart-3b846969-0253-49a1-bd0d-bc38abd22fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535613572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.535613572 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1484019943 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 437602035 ps |
| CPU time | 0.76 seconds |
| Started | Jan 03 12:30:30 PM PST 24 |
| Finished | Jan 03 12:31:30 PM PST 24 |
| Peak memory | 194096 kb |
| Host | smart-2cd26cb7-1de4-40ee-8fa2-b9acbc2ed857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484019943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.1484019943 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2946278558 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 440380718 ps |
| CPU time | 1.56 seconds |
| Started | Jan 03 12:30:27 PM PST 24 |
| Finished | Jan 03 12:31:26 PM PST 24 |
| Peak memory | 192076 kb |
| Host | smart-7dabbe93-0db9-43f3-982e-3987f36bf2fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946278558 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2946278558 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1463480955 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 13952864 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:45 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-e538597e-66bb-488a-9fac-415259c1c6cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463480955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1463480955 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.149842490 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 24045713 ps |
| CPU time | 0.69 seconds |
| Started | Jan 03 12:30:36 PM PST 24 |
| Finished | Jan 03 12:31:38 PM PST 24 |
| Peak memory | 192416 kb |
| Host | smart-6cca8a15-2c7a-47cf-8dbd-f5e5693054bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149842490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti mer_same_csr_outstanding.149842490 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3981574859 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 144333093 ps |
| CPU time | 1.82 seconds |
| Started | Jan 03 12:30:43 PM PST 24 |
| Finished | Jan 03 12:31:50 PM PST 24 |
| Peak memory | 197864 kb |
| Host | smart-0cdedbf6-c7db-43a6-94ef-fb8cca194e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981574859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3981574859 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2639035994 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 401154065 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:30:44 PM PST 24 |
| Finished | Jan 03 12:31:50 PM PST 24 |
| Peak memory | 183440 kb |
| Host | smart-f4ea02cf-6a22-448b-b8c9-97cb6f7b86fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639035994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.2639035994 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1564049104 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 19302685 ps |
| CPU time | 0.92 seconds |
| Started | Jan 03 12:30:33 PM PST 24 |
| Finished | Jan 03 12:31:35 PM PST 24 |
| Peak memory | 197180 kb |
| Host | smart-efbfd50d-38fb-44cf-9e13-c055eb6c0cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564049104 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1564049104 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1412406393 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30237598 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:30:40 PM PST 24 |
| Finished | Jan 03 12:31:43 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-88917bc1-34f7-4da5-bd50-302ffdbe3f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412406393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1412406393 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1389397538 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 12705637 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:36 PM PST 24 |
| Finished | Jan 03 12:31:38 PM PST 24 |
| Peak memory | 181972 kb |
| Host | smart-80c5a6a3-0a93-41cf-b265-f0a9bf15cebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389397538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1389397538 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1578246068 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 18042770 ps |
| CPU time | 0.67 seconds |
| Started | Jan 03 12:30:45 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 193432 kb |
| Host | smart-3f367fc3-a50e-4850-98f1-c503deff248f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578246068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.1578246068 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.637362617 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 669158449 ps |
| CPU time | 0.93 seconds |
| Started | Jan 03 12:31:20 PM PST 24 |
| Finished | Jan 03 12:32:30 PM PST 24 |
| Peak memory | 195264 kb |
| Host | smart-2d5efeaa-33ac-4d8c-9da4-236d0f3f27d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637362617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in tg_err.637362617 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1461135641 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 262187685 ps |
| CPU time | 0.83 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 196660 kb |
| Host | smart-20f2ed0f-2591-430c-b2b9-89029833c964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461135641 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1461135641 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.106690793 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 13919400 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:45 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-3d569763-372f-42f4-b3d9-05c6010ff97f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106690793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.106690793 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.158277505 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31939290 ps |
| CPU time | 0.59 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:36 PM PST 24 |
| Peak memory | 182804 kb |
| Host | smart-873e11df-2392-4533-afb9-4f694e5cd053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158277505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.158277505 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3717579887 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 134590644 ps |
| CPU time | 0.79 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:36 PM PST 24 |
| Peak memory | 193624 kb |
| Host | smart-f4752f1b-704a-466e-9a47-01fda98cef56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717579887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.3717579887 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1520861160 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 152475139 ps |
| CPU time | 2.85 seconds |
| Started | Jan 03 12:30:42 PM PST 24 |
| Finished | Jan 03 12:31:49 PM PST 24 |
| Peak memory | 197972 kb |
| Host | smart-35dacf32-2dfc-4b2e-8a64-2ccd9b59b3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520861160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1520861160 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3411278956 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 640683112 ps |
| CPU time | 1.15 seconds |
| Started | Jan 03 12:30:38 PM PST 24 |
| Finished | Jan 03 12:31:41 PM PST 24 |
| Peak memory | 183568 kb |
| Host | smart-1d346877-e4be-4b84-821b-af4692317f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411278956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.3411278956 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4045988709 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 131747402 ps |
| CPU time | 0.76 seconds |
| Started | Jan 03 12:30:54 PM PST 24 |
| Finished | Jan 03 12:32:00 PM PST 24 |
| Peak memory | 197080 kb |
| Host | smart-f27df3ae-098c-4eca-aa46-f42f22871cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045988709 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4045988709 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4141516275 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 18129475 ps |
| CPU time | 0.57 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 183164 kb |
| Host | smart-25777722-8133-4244-b975-5e3b6cc030a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141516275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4141516275 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3825202514 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 19875508 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:32 PM PST 24 |
| Finished | Jan 03 12:31:34 PM PST 24 |
| Peak memory | 182784 kb |
| Host | smart-c8d1967b-03a5-4ba7-b318-666baeac8356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825202514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3825202514 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.199663646 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 63207851 ps |
| CPU time | 0.72 seconds |
| Started | Jan 03 12:30:30 PM PST 24 |
| Finished | Jan 03 12:31:30 PM PST 24 |
| Peak memory | 193488 kb |
| Host | smart-7df7ad86-4e6f-43b1-9df2-5e5a5fc34436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199663646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti mer_same_csr_outstanding.199663646 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.359744370 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 114471008 ps |
| CPU time | 1.83 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:37 PM PST 24 |
| Peak memory | 197844 kb |
| Host | smart-65480197-82d1-475b-a692-df876f48dfd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359744370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.359744370 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3011475675 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 51481959 ps |
| CPU time | 0.79 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 183432 kb |
| Host | smart-7130d50f-e9c4-42d0-bc11-fb9a46705781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011475675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.3011475675 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2916887380 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 21284634 ps |
| CPU time | 0.79 seconds |
| Started | Jan 03 12:29:30 PM PST 24 |
| Finished | Jan 03 12:30:04 PM PST 24 |
| Peak memory | 192992 kb |
| Host | smart-1d72f847-8865-41f7-857a-3f41bf12cd58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916887380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.2916887380 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1358881079 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 92787262 ps |
| CPU time | 3.05 seconds |
| Started | Jan 03 12:29:07 PM PST 24 |
| Finished | Jan 03 12:29:37 PM PST 24 |
| Peak memory | 192776 kb |
| Host | smart-d6e92a87-5eb2-4844-ba1a-6ea60f76903a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358881079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.1358881079 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1488258529 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 25291755 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:29:51 PM PST 24 |
| Finished | Jan 03 12:30:33 PM PST 24 |
| Peak memory | 182424 kb |
| Host | smart-8e509bcd-4fc7-4a9a-a547-cb54956f2f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488258529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.1488258529 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1300011319 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 37656780 ps |
| CPU time | 0.64 seconds |
| Started | Jan 03 12:29:10 PM PST 24 |
| Finished | Jan 03 12:29:38 PM PST 24 |
| Peak memory | 195040 kb |
| Host | smart-12fc822d-b930-4016-8dc7-8697873ff147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300011319 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1300011319 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2071597594 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 38350010 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:02 PM PST 24 |
| Finished | Jan 03 12:30:47 PM PST 24 |
| Peak memory | 183132 kb |
| Host | smart-620bd1ba-2a64-4ae8-9754-a9105965f722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071597594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2071597594 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2798717364 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 14501762 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:29:53 PM PST 24 |
| Finished | Jan 03 12:30:36 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-60fef30a-abdd-4391-8882-5a3cd00f597c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798717364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2798717364 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4104648562 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13208243 ps |
| CPU time | 0.6 seconds |
| Started | Jan 03 12:29:10 PM PST 24 |
| Finished | Jan 03 12:29:38 PM PST 24 |
| Peak memory | 191756 kb |
| Host | smart-63b548de-a1c1-423c-8b2e-ebd6e61e0a47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104648562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.4104648562 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2419862190 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 87694191 ps |
| CPU time | 1.15 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 196324 kb |
| Host | smart-5bfab200-a1a5-4744-a639-ca572f4b8ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419862190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2419862190 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1005001830 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 89914663 ps |
| CPU time | 1.11 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 194676 kb |
| Host | smart-8020b0ca-af27-4b62-b345-43469802c061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005001830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.1005001830 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4256814401 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 37412726 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-8e0e3a86-3c00-4f62-8ea1-afb520121e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256814401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4256814401 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1201631878 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 50357813 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:39 PM PST 24 |
| Finished | Jan 03 12:31:43 PM PST 24 |
| Peak memory | 182864 kb |
| Host | smart-7c68dd3f-2f7a-4cf6-acb0-493867b07583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201631878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1201631878 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3599143679 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 60783970 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:32 PM PST 24 |
| Finished | Jan 03 12:31:34 PM PST 24 |
| Peak memory | 182416 kb |
| Host | smart-92322cdf-bbd1-49d2-bdbf-e71c4e26ae6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599143679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3599143679 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1022603250 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 60860488 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 181988 kb |
| Host | smart-bbfe275f-393e-4ce0-a8c7-1416bc817f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022603250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1022603250 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1438531213 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 141190815 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:30:30 PM PST 24 |
| Finished | Jan 03 12:31:30 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-e696eb9c-9efd-4306-9abe-f056bf1465f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438531213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1438531213 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3595891518 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 135233891 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:29 PM PST 24 |
| Finished | Jan 03 12:31:29 PM PST 24 |
| Peak memory | 182896 kb |
| Host | smart-8aa8ecd1-b216-4da3-ac19-9e5c841b643f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595891518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3595891518 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1789155986 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 13717477 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:42 PM PST 24 |
| Finished | Jan 03 12:31:47 PM PST 24 |
| Peak memory | 182868 kb |
| Host | smart-36192d44-5f0b-4c3e-b611-edc173b87e00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789155986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1789155986 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.660911338 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 11532653 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:30:48 PM PST 24 |
| Finished | Jan 03 12:31:54 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-f3064563-b2ce-4b46-93aa-6f3af5a45a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660911338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.660911338 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3846100774 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 21958079 ps |
| CPU time | 0.57 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:35 PM PST 24 |
| Peak memory | 182640 kb |
| Host | smart-859f9c77-4256-4f55-a9a5-1b9b749f3aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846100774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3846100774 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2011028145 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 216945738 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:35 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-1e8bd6f8-abfc-41ca-a86f-1e3aa4a290c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011028145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2011028145 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.529915272 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 26537014 ps |
| CPU time | 0.75 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:29:59 PM PST 24 |
| Peak memory | 192796 kb |
| Host | smart-d7784702-689b-4d2b-95f5-3a9ef6d3aa13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529915272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias ing.529915272 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2043308243 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 283168185 ps |
| CPU time | 2.51 seconds |
| Started | Jan 03 12:29:07 PM PST 24 |
| Finished | Jan 03 12:29:36 PM PST 24 |
| Peak memory | 183356 kb |
| Host | smart-de20e8e7-f3bd-4274-aa8e-a5920fee84d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043308243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.2043308243 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3709453153 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 67349759 ps |
| CPU time | 0.7 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 182536 kb |
| Host | smart-6be20997-0d5c-4eea-963f-c69b174c5b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709453153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.3709453153 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1919650508 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 60024446 ps |
| CPU time | 1.34 seconds |
| Started | Jan 03 12:29:24 PM PST 24 |
| Finished | Jan 03 12:29:57 PM PST 24 |
| Peak memory | 197724 kb |
| Host | smart-57347a65-b7eb-4933-ac8d-84316961f745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919650508 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1919650508 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3377206982 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 12528939 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:29:47 PM PST 24 |
| Finished | Jan 03 12:30:28 PM PST 24 |
| Peak memory | 183144 kb |
| Host | smart-98cad6b7-f0f1-445a-ad20-ac182c162f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377206982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3377206982 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.372336970 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 16125952 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:00 PM PST 24 |
| Finished | Jan 03 12:30:45 PM PST 24 |
| Peak memory | 182868 kb |
| Host | smart-a329e3fb-4877-4af4-8330-5bbb245d0f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372336970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.372336970 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.150156668 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 25090358 ps |
| CPU time | 0.58 seconds |
| Started | Jan 03 12:29:14 PM PST 24 |
| Finished | Jan 03 12:29:42 PM PST 24 |
| Peak memory | 191840 kb |
| Host | smart-f6fcb66a-93ae-44ce-a8e0-d460d7e884e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150156668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim er_same_csr_outstanding.150156668 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3204946253 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1552613040 ps |
| CPU time | 2.1 seconds |
| Started | Jan 03 12:29:39 PM PST 24 |
| Finished | Jan 03 12:30:18 PM PST 24 |
| Peak memory | 197944 kb |
| Host | smart-874decfb-a6b8-4f79-8ac7-e52d92b051f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204946253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3204946253 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1848321878 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 71363448 ps |
| CPU time | 1.03 seconds |
| Started | Jan 03 12:29:21 PM PST 24 |
| Finished | Jan 03 12:29:53 PM PST 24 |
| Peak memory | 195436 kb |
| Host | smart-7a7da5dc-0a18-4c43-b925-549ea236c659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848321878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.1848321878 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.658564426 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 14069793 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:50 PM PST 24 |
| Finished | Jan 03 12:31:57 PM PST 24 |
| Peak memory | 182776 kb |
| Host | smart-c116eead-4f56-4686-9be5-1699b8239790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658564426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.658564426 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2002559154 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 23252568 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:43 PM PST 24 |
| Finished | Jan 03 12:31:48 PM PST 24 |
| Peak memory | 182816 kb |
| Host | smart-fefe26ca-79f0-4930-9089-cb02ee914877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002559154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2002559154 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1359893427 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 12650961 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:51 PM PST 24 |
| Finished | Jan 03 12:31:57 PM PST 24 |
| Peak memory | 182396 kb |
| Host | smart-c89aa44b-3ba8-41ec-a9ef-b7d90532254d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359893427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1359893427 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3496587163 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 42641257 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:51 PM PST 24 |
| Finished | Jan 03 12:31:57 PM PST 24 |
| Peak memory | 182744 kb |
| Host | smart-28454cc6-e305-4e49-bdcc-7cb6408d5bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496587163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3496587163 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.31700632 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 12475843 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:32 PM PST 24 |
| Finished | Jan 03 12:31:33 PM PST 24 |
| Peak memory | 182632 kb |
| Host | smart-46806182-c17e-4054-b715-e11eff7f25fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.31700632 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2444760959 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 12959894 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:49 PM PST 24 |
| Finished | Jan 03 12:31:55 PM PST 24 |
| Peak memory | 182008 kb |
| Host | smart-d1bbdcf1-a26c-4a02-812b-236ce1b41323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444760959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2444760959 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.846267726 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 30008974 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:35 PM PST 24 |
| Peak memory | 182764 kb |
| Host | smart-f3edcd67-2539-46b6-8079-92f7e03022af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846267726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.846267726 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2659755864 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 12300599 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:30:54 PM PST 24 |
| Finished | Jan 03 12:32:00 PM PST 24 |
| Peak memory | 182840 kb |
| Host | smart-6d1e49eb-1900-45b0-949f-23a2012a4b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659755864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2659755864 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2570359747 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 163573319 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:55 PM PST 24 |
| Finished | Jan 03 12:32:01 PM PST 24 |
| Peak memory | 181952 kb |
| Host | smart-816b1915-d2f6-414a-a3db-c861cafea06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570359747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2570359747 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.649975457 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 31662748 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:31:06 PM PST 24 |
| Finished | Jan 03 12:32:13 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-6c518ec4-d670-473b-bacd-ca3d98343dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649975457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.649975457 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4009478315 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 41642983 ps |
| CPU time | 0.75 seconds |
| Started | Jan 03 12:29:57 PM PST 24 |
| Finished | Jan 03 12:30:41 PM PST 24 |
| Peak memory | 183108 kb |
| Host | smart-ef37fa24-3ae9-420e-b57c-5263c88481ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009478315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.4009478315 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4116992504 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 291256245 ps |
| CPU time | 3.27 seconds |
| Started | Jan 03 12:29:51 PM PST 24 |
| Finished | Jan 03 12:30:36 PM PST 24 |
| Peak memory | 192708 kb |
| Host | smart-83863f0f-9ebd-4f2c-aadc-6d791fd5bcfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116992504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.4116992504 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.615926368 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 53725087 ps |
| CPU time | 0.55 seconds |
| Started | Jan 03 12:29:21 PM PST 24 |
| Finished | Jan 03 12:29:51 PM PST 24 |
| Peak memory | 183220 kb |
| Host | smart-09763006-33b9-4522-913d-bd2f404ada59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615926368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re set.615926368 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.136880576 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 52319770 ps |
| CPU time | 1.34 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 197796 kb |
| Host | smart-6cfb3e91-8b0e-4ddd-8e53-5c4df58ce25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136880576 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.136880576 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.948734977 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 14004953 ps |
| CPU time | 0.57 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:30:00 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-45369def-92af-4806-8735-2fd8cf87218b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948734977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.948734977 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1502698355 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 33737935 ps |
| CPU time | 0.63 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 181376 kb |
| Host | smart-c6d11b05-c412-435c-b82a-54666fc239cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502698355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1502698355 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1628488522 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 54171082 ps |
| CPU time | 0.59 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:29:59 PM PST 24 |
| Peak memory | 191664 kb |
| Host | smart-5e819f7c-8058-4c29-a9ef-5878d8853d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628488522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.1628488522 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2517798362 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 374719490 ps |
| CPU time | 2.68 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:30:01 PM PST 24 |
| Peak memory | 197900 kb |
| Host | smart-3e8201af-715f-4530-bc74-16316d893009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517798362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2517798362 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1712947394 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 499621971 ps |
| CPU time | 1.29 seconds |
| Started | Jan 03 12:29:20 PM PST 24 |
| Finished | Jan 03 12:29:49 PM PST 24 |
| Peak memory | 195464 kb |
| Host | smart-87fffb44-7ee1-43c8-a7b9-0bbf7af2d4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712947394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.1712947394 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2815199482 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 16400868 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:31:00 PM PST 24 |
| Finished | Jan 03 12:32:07 PM PST 24 |
| Peak memory | 181852 kb |
| Host | smart-eca7af03-116f-4181-a084-7bde0a59113d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815199482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2815199482 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2985721924 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 24072656 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:31:27 PM PST 24 |
| Finished | Jan 03 12:32:39 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-a4dd9cf0-bf63-45b5-acb8-65a68d56fbe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985721924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2985721924 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.531744977 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 19755253 ps |
| CPU time | 0.58 seconds |
| Started | Jan 03 12:31:18 PM PST 24 |
| Finished | Jan 03 12:32:25 PM PST 24 |
| Peak memory | 182776 kb |
| Host | smart-40b0d33e-02a4-4c77-bab9-b608725f4cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531744977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.531744977 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3237558764 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 25353892 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:31:16 PM PST 24 |
| Finished | Jan 03 12:32:22 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-8c099ddc-0723-4d41-8baa-031b66d74059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237558764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3237558764 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3605918319 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 22710895 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:31:08 PM PST 24 |
| Finished | Jan 03 12:32:15 PM PST 24 |
| Peak memory | 182436 kb |
| Host | smart-f067c255-f62e-4e70-bc4e-d278c74789f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605918319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3605918319 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3990592017 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 14949273 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:31:08 PM PST 24 |
| Finished | Jan 03 12:32:14 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-5f0aa8db-c539-4014-94bb-e03f3a78db9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990592017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3990592017 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.436283721 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 46387659 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:59 PM PST 24 |
| Finished | Jan 03 12:32:07 PM PST 24 |
| Peak memory | 182764 kb |
| Host | smart-e4532273-e030-42cf-964c-4f11151173b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436283721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.436283721 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.737462144 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 35568933 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:52 PM PST 24 |
| Finished | Jan 03 12:32:00 PM PST 24 |
| Peak memory | 182744 kb |
| Host | smart-f5159c6a-827b-4739-8f4f-fa9651283fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737462144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.737462144 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1964380137 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 35451420 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:31:10 PM PST 24 |
| Finished | Jan 03 12:32:15 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-791c5040-fd71-48ea-adc1-0e472189ce29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964380137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1964380137 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.304433089 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 33482802 ps |
| CPU time | 0.9 seconds |
| Started | Jan 03 12:29:39 PM PST 24 |
| Finished | Jan 03 12:30:17 PM PST 24 |
| Peak memory | 197228 kb |
| Host | smart-613d5967-cb56-46a0-8f86-cfd9f3d5e056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304433089 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.304433089 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.784938868 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 14310761 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:29:32 PM PST 24 |
| Finished | Jan 03 12:30:06 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-602dc7af-91d4-4ea2-9095-a8746ff713cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784938868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.784938868 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1671718873 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 52773486 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:29:27 PM PST 24 |
| Finished | Jan 03 12:29:59 PM PST 24 |
| Peak memory | 181944 kb |
| Host | smart-64e12c47-bb19-465e-8b29-9e1eb5d59097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671718873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1671718873 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3345777288 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 12973766 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:29:58 PM PST 24 |
| Finished | Jan 03 12:30:42 PM PST 24 |
| Peak memory | 191564 kb |
| Host | smart-492f0016-79c3-45aa-8433-1b166911f607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345777288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.3345777288 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.35772547 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 27605743 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:29:43 PM PST 24 |
| Finished | Jan 03 12:30:24 PM PST 24 |
| Peak memory | 197224 kb |
| Host | smart-cf6865e6-04b9-4b09-a7fb-1059f58b9991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.35772547 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3956205510 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 208281544 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:29:28 PM PST 24 |
| Finished | Jan 03 12:30:02 PM PST 24 |
| Peak memory | 195532 kb |
| Host | smart-6fb75e44-4ced-4d3c-9fc1-9977c5bc6ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956205510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.3956205510 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.239574469 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 53060546 ps |
| CPU time | 0.6 seconds |
| Started | Jan 03 12:29:50 PM PST 24 |
| Finished | Jan 03 12:30:32 PM PST 24 |
| Peak memory | 193892 kb |
| Host | smart-6b52659c-c7ac-49ea-a5a9-881f6ee71602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239574469 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.239574469 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.515925293 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 100670083 ps |
| CPU time | 0.52 seconds |
| Started | Jan 03 12:30:05 PM PST 24 |
| Finished | Jan 03 12:30:51 PM PST 24 |
| Peak memory | 182652 kb |
| Host | smart-e9d4859d-3bfe-4a8b-a484-674d2262614a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515925293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.515925293 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1154415140 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 11904052 ps |
| CPU time | 0.58 seconds |
| Started | Jan 03 12:29:56 PM PST 24 |
| Finished | Jan 03 12:30:40 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-83d104aa-65a3-4f50-80a5-763e295eeb00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154415140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1154415140 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3977723587 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 522105303 ps |
| CPU time | 2.43 seconds |
| Started | Jan 03 12:29:32 PM PST 24 |
| Finished | Jan 03 12:30:09 PM PST 24 |
| Peak memory | 197884 kb |
| Host | smart-a2aeeefc-dc9f-4223-8c4a-fe3f20ba937f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977723587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3977723587 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1349754992 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 82161142 ps |
| CPU time | 1.09 seconds |
| Started | Jan 03 12:29:51 PM PST 24 |
| Finished | Jan 03 12:30:34 PM PST 24 |
| Peak memory | 195496 kb |
| Host | smart-71ef535d-550d-48cc-8700-5707aee69129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349754992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.1349754992 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2966972253 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 33915174 ps |
| CPU time | 0.57 seconds |
| Started | Jan 03 12:29:54 PM PST 24 |
| Finished | Jan 03 12:30:37 PM PST 24 |
| Peak memory | 183156 kb |
| Host | smart-e1b6ec22-0021-4b94-8ffc-4e6512bff7d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966972253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2966972253 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3948047058 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 13808216 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:29:43 PM PST 24 |
| Finished | Jan 03 12:30:24 PM PST 24 |
| Peak memory | 182056 kb |
| Host | smart-35505392-647e-4f6e-a8de-e64d8627ab82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948047058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3948047058 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.354012096 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 55330940 ps |
| CPU time | 0.65 seconds |
| Started | Jan 03 12:29:47 PM PST 24 |
| Finished | Jan 03 12:30:28 PM PST 24 |
| Peak memory | 192048 kb |
| Host | smart-de1781fd-8434-4094-a9bd-04d1f1d7f5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354012096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim er_same_csr_outstanding.354012096 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.579316538 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 321643360 ps |
| CPU time | 1.49 seconds |
| Started | Jan 03 12:29:55 PM PST 24 |
| Finished | Jan 03 12:30:39 PM PST 24 |
| Peak memory | 197800 kb |
| Host | smart-dbcf6c25-dcc5-4e14-9f64-cb5c884e91a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579316538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.579316538 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3961799404 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 28856570 ps |
| CPU time | 0.72 seconds |
| Started | Jan 03 12:30:28 PM PST 24 |
| Finished | Jan 03 12:31:29 PM PST 24 |
| Peak memory | 195492 kb |
| Host | smart-2d5c763e-02be-4102-93f8-9c543823acb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961799404 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3961799404 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2221489269 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14437115 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:34 PM PST 24 |
| Finished | Jan 03 12:31:40 PM PST 24 |
| Peak memory | 182608 kb |
| Host | smart-7d5278df-b61a-4115-b84e-9a00022e55ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221489269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2221489269 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1496224795 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 64373524 ps |
| CPU time | 0.53 seconds |
| Started | Jan 03 12:30:41 PM PST 24 |
| Finished | Jan 03 12:31:46 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-a721865a-e10a-410c-94d2-56563a517e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496224795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1496224795 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4004876002 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 16557502 ps |
| CPU time | 0.65 seconds |
| Started | Jan 03 12:30:26 PM PST 24 |
| Finished | Jan 03 12:31:24 PM PST 24 |
| Peak memory | 191780 kb |
| Host | smart-5bac6bcd-20bf-42d1-8ebd-bee0ff1ac8bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004876002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.4004876002 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4071588053 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 69757035 ps |
| CPU time | 1 seconds |
| Started | Jan 03 12:30:06 PM PST 24 |
| Finished | Jan 03 12:30:52 PM PST 24 |
| Peak memory | 183588 kb |
| Host | smart-f39d2dca-b7ab-48e6-a3ce-b18682cc6ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071588053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.4071588053 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3067962472 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 146877006 ps |
| CPU time | 1.18 seconds |
| Started | Jan 03 12:30:42 PM PST 24 |
| Finished | Jan 03 12:31:48 PM PST 24 |
| Peak memory | 198036 kb |
| Host | smart-01a18097-e423-483f-a240-50faf2c8aeb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067962472 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3067962472 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1839704135 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 42094297 ps |
| CPU time | 0.56 seconds |
| Started | Jan 03 12:30:32 PM PST 24 |
| Finished | Jan 03 12:31:34 PM PST 24 |
| Peak memory | 183116 kb |
| Host | smart-25d5a368-3be8-4b1f-b1ac-68a4b0340093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839704135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1839704135 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2960716712 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 161633764 ps |
| CPU time | 0.51 seconds |
| Started | Jan 03 12:30:21 PM PST 24 |
| Finished | Jan 03 12:31:15 PM PST 24 |
| Peak memory | 181844 kb |
| Host | smart-fe1931a4-dde2-4dde-9fbb-4c3ee7d30bec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960716712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2960716712 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3052521163 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 67983118 ps |
| CPU time | 0.76 seconds |
| Started | Jan 03 12:30:46 PM PST 24 |
| Finished | Jan 03 12:31:52 PM PST 24 |
| Peak memory | 193640 kb |
| Host | smart-9f8a9fd4-b98b-46b8-9424-82a0117e2413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052521163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.3052521163 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.104571449 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 146285601 ps |
| CPU time | 2.84 seconds |
| Started | Jan 03 12:30:21 PM PST 24 |
| Finished | Jan 03 12:31:18 PM PST 24 |
| Peak memory | 197984 kb |
| Host | smart-17604e76-9c06-4434-b98b-f1cc44283cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104571449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.104571449 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2715936968 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 124075369 ps |
| CPU time | 1.29 seconds |
| Started | Jan 03 12:30:50 PM PST 24 |
| Finished | Jan 03 12:31:57 PM PST 24 |
| Peak memory | 195780 kb |
| Host | smart-0aecfdd7-a07e-4ca1-b58c-db3e53d7efe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715936968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.2715936968 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3802150435 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 730737343271 ps |
| CPU time | 358.59 seconds |
| Started | Jan 03 12:37:13 PM PST 24 |
| Finished | Jan 03 12:44:23 PM PST 24 |
| Peak memory | 182568 kb |
| Host | smart-07bbd203-9c8e-44b1-969c-98d0848525dc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802150435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3802150435 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.3900621697 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 140330619212 ps |
| CPU time | 223.96 seconds |
| Started | Jan 03 12:35:21 PM PST 24 |
| Finished | Jan 03 12:40:33 PM PST 24 |
| Peak memory | 182540 kb |
| Host | smart-3d3b6649-0661-40e9-97a6-458c3b838556 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900621697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3900621697 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.1503000950 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 48618109130 ps |
| CPU time | 625.45 seconds |
| Started | Jan 03 12:35:03 PM PST 24 |
| Finished | Jan 03 12:46:43 PM PST 24 |
| Peak memory | 190752 kb |
| Host | smart-94bd5450-f580-407b-ba98-70245638b89d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503000950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1503000950 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.2839012899 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 132364150 ps |
| CPU time | 0.71 seconds |
| Started | Jan 03 12:35:33 PM PST 24 |
| Finished | Jan 03 12:37:06 PM PST 24 |
| Peak memory | 212100 kb |
| Host | smart-bc482fd3-9e0b-4655-8f8c-10c8246823bc |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839012899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2839012899 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1270394697 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 84906462984 ps |
| CPU time | 228.99 seconds |
| Started | Jan 03 12:35:38 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 205488 kb |
| Host | smart-27116ccd-3c5f-4fe1-86d4-9c1acde9b89f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270394697 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1270394697 |
| Directory | /workspace/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3390850878 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 36312718462 ps |
| CPU time | 18.72 seconds |
| Started | Jan 03 12:33:50 PM PST 24 |
| Finished | Jan 03 12:36:03 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-4508f985-8738-47fa-a94f-b87e1276cbd7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390850878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.3390850878 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.1217110417 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 55154023560 ps |
| CPU time | 88.32 seconds |
| Started | Jan 03 12:33:54 PM PST 24 |
| Finished | Jan 03 12:37:18 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-e5aca7b9-af75-4a17-a6d6-066e27f7bf3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217110417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1217110417 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.2209361981 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 35325558261 ps |
| CPU time | 61.21 seconds |
| Started | Jan 03 12:33:52 PM PST 24 |
| Finished | Jan 03 12:36:11 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-05f61782-543d-4a57-bae1-fd3ca96f80fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209361981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2209361981 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.1200133996 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 354317109524 ps |
| CPU time | 102.91 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:36:55 PM PST 24 |
| Peak memory | 182712 kb |
| Host | smart-434e09be-a051-42d8-b853-5e3c9dfc391f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200133996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .1200133996 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2553815248 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 78462160810 ps |
| CPU time | 613.66 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:45:21 PM PST 24 |
| Peak memory | 205896 kb |
| Host | smart-56a467cc-bee7-4834-b2b5-e2a40b2a10c9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553815248 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2553815248 |
| Directory | /workspace/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.639854042 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 110724550245 ps |
| CPU time | 178.5 seconds |
| Started | Jan 03 12:34:30 PM PST 24 |
| Finished | Jan 03 12:38:51 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-327ad727-68c8-4211-8dd2-ca341939828b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639854042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.639854042 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.500877740 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 84635280770 ps |
| CPU time | 230.45 seconds |
| Started | Jan 03 12:34:19 PM PST 24 |
| Finished | Jan 03 12:39:26 PM PST 24 |
| Peak memory | 191084 kb |
| Host | smart-237bb234-8298-4aeb-9136-4d0edec4bb56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500877740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.500877740 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.2435104487 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 157888980951 ps |
| CPU time | 245.18 seconds |
| Started | Jan 03 12:34:31 PM PST 24 |
| Finished | Jan 03 12:39:46 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-6c1d1f44-6ebb-47fd-8ff2-d8611ae0f922 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435104487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2435104487 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3714505735 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 643662536878 ps |
| CPU time | 206.92 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:38:43 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-9a2b4c3c-e277-45aa-b44b-da538c962bbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714505735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.3714505735 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.944603256 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 55418549212 ps |
| CPU time | 46.48 seconds |
| Started | Jan 03 12:33:46 PM PST 24 |
| Finished | Jan 03 12:36:09 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-90274ae7-9453-4ad3-b879-00387f3eccbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944603256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.944603256 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.1884479545 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2748676943644 ps |
| CPU time | 786.54 seconds |
| Started | Jan 03 12:33:37 PM PST 24 |
| Finished | Jan 03 12:48:13 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-78652d2c-f888-4783-9423-8c0da1ec2520 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884479545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .1884479545 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.1429968831 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 358106709313 ps |
| CPU time | 646.97 seconds |
| Started | Jan 03 12:33:34 PM PST 24 |
| Finished | Jan 03 12:45:42 PM PST 24 |
| Peak memory | 207096 kb |
| Host | smart-9bc440c9-dd19-4872-8d6a-6efc5dd8358b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429968831 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.1429968831 |
| Directory | /workspace/11.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.509820221 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3457410823 ps |
| CPU time | 19.49 seconds |
| Started | Jan 03 12:34:15 PM PST 24 |
| Finished | Jan 03 12:35:50 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-fbc93a40-6038-4da8-b0d3-854a18431bd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509820221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.509820221 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.2354648236 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 128054582368 ps |
| CPU time | 1166.1 seconds |
| Started | Jan 03 12:33:52 PM PST 24 |
| Finished | Jan 03 12:54:36 PM PST 24 |
| Peak memory | 191108 kb |
| Host | smart-5ac8c572-d313-4484-a7c2-5cfa55e020da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354648236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2354648236 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.3397884077 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 394737228315 ps |
| CPU time | 204.9 seconds |
| Started | Jan 03 12:34:24 PM PST 24 |
| Finished | Jan 03 12:39:10 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-5d605c24-a9f5-44be-b3cc-1ee8dec1c9c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397884077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3397884077 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.3873530433 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 454963115516 ps |
| CPU time | 1497.2 seconds |
| Started | Jan 03 12:34:10 PM PST 24 |
| Finished | Jan 03 01:00:26 PM PST 24 |
| Peak memory | 192140 kb |
| Host | smart-f220c807-848c-4beb-9e38-74e738ff3d6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873530433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3873530433 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.1139724652 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 20261162489 ps |
| CPU time | 25.11 seconds |
| Started | Jan 03 12:34:07 PM PST 24 |
| Finished | Jan 03 12:35:49 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-92428165-1334-4409-a783-b562e1360b7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139724652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1139724652 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2101573057 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 18239155210 ps |
| CPU time | 33.56 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:35:32 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-f239785d-4049-4cf1-af65-294b7f1c7cd8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101573057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.2101573057 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.857811758 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 325050065174 ps |
| CPU time | 122.5 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:37:27 PM PST 24 |
| Peak memory | 182768 kb |
| Host | smart-e1f589ec-ba21-4df5-bdfa-5827bfe7d62e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857811758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.857811758 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.1968243887 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 405231500090 ps |
| CPU time | 548.08 seconds |
| Started | Jan 03 12:33:16 PM PST 24 |
| Finished | Jan 03 12:43:34 PM PST 24 |
| Peak memory | 191124 kb |
| Host | smart-45a8798c-0f14-43e3-b400-def6b686c819 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968243887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1968243887 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2899245451 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 646827299591 ps |
| CPU time | 1195.31 seconds |
| Started | Jan 03 12:33:34 PM PST 24 |
| Finished | Jan 03 12:54:51 PM PST 24 |
| Peak memory | 207328 kb |
| Host | smart-db13c080-020e-4270-b498-61252edad60f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899245451 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2899245451 |
| Directory | /workspace/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.1670312266 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 9993813056 ps |
| CPU time | 51.15 seconds |
| Started | Jan 03 12:34:22 PM PST 24 |
| Finished | Jan 03 12:36:29 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-89eec81e-266b-459f-abe3-887dd7c455e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670312266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1670312266 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.779031188 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 100499455334 ps |
| CPU time | 178.5 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:38:06 PM PST 24 |
| Peak memory | 194440 kb |
| Host | smart-da735e75-974e-4aa1-bf5e-d50eb67bd892 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779031188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.779031188 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.4189332681 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 98707074566 ps |
| CPU time | 46.15 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:36:01 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-73de639a-b80f-4ac6-8134-48cb2ff47c89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189332681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4189332681 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.2360427 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 190717382637 ps |
| CPU time | 122.14 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:37:26 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-ba30a605-c6c9-4057-9fa3-a864e6666ae1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2360427 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.1330841067 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 263274544903 ps |
| CPU time | 196.5 seconds |
| Started | Jan 03 12:34:07 PM PST 24 |
| Finished | Jan 03 12:38:49 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-99f83f28-c81d-4c9b-916b-f4a72ff2280a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330841067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1330841067 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.3280165287 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 51183042646 ps |
| CPU time | 85.66 seconds |
| Started | Jan 03 12:34:35 PM PST 24 |
| Finished | Jan 03 12:37:14 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-0870e497-1f1e-4fbb-94f5-18f25b234df8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280165287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3280165287 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.2138274680 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 129995342031 ps |
| CPU time | 96.61 seconds |
| Started | Jan 03 12:34:13 PM PST 24 |
| Finished | Jan 03 12:37:01 PM PST 24 |
| Peak memory | 191092 kb |
| Host | smart-a3ed95bb-3c58-4f16-8386-7ba833b63284 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138274680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2138274680 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.4178903976 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 33244153541 ps |
| CPU time | 24.35 seconds |
| Started | Jan 03 12:33:44 PM PST 24 |
| Finished | Jan 03 12:35:19 PM PST 24 |
| Peak memory | 182736 kb |
| Host | smart-9ee9bd4c-681d-40c9-bcd5-8a42ff86526b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178903976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4178903976 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1574312342 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 66330074794 ps |
| CPU time | 540.53 seconds |
| Started | Jan 03 12:33:36 PM PST 24 |
| Finished | Jan 03 12:44:07 PM PST 24 |
| Peak memory | 205724 kb |
| Host | smart-fe9834e0-0331-4518-a8b4-f7e89adc112d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574312342 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1574312342 |
| Directory | /workspace/13.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.2500735128 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4999775206 ps |
| CPU time | 188.53 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:38:44 PM PST 24 |
| Peak memory | 182732 kb |
| Host | smart-12a61fff-f158-4e9b-aa5d-17fea804b53c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500735128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2500735128 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.3910503256 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 45833489672 ps |
| CPU time | 120.6 seconds |
| Started | Jan 03 12:34:24 PM PST 24 |
| Finished | Jan 03 12:37:49 PM PST 24 |
| Peak memory | 194216 kb |
| Host | smart-3558622c-6262-4942-9e99-c97af7fcc994 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910503256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3910503256 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.3463445100 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 189389198040 ps |
| CPU time | 586.32 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:45:17 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-dcd1267f-b467-4a50-8ed9-99495fc10d70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463445100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3463445100 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.170745744 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 320444871824 ps |
| CPU time | 195.93 seconds |
| Started | Jan 03 12:34:30 PM PST 24 |
| Finished | Jan 03 12:39:00 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-759c0477-f7dc-4a99-b08e-937b600d3154 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170745744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.rv_timer_cfg_update_on_fly.170745744 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.641034675 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 103694429240 ps |
| CPU time | 91.07 seconds |
| Started | Jan 03 12:33:47 PM PST 24 |
| Finished | Jan 03 12:37:03 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-642257f8-41ac-46f8-b404-e6fa75e93c4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641034675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.641034675 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.332599931 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 965859559834 ps |
| CPU time | 2515.81 seconds |
| Started | Jan 03 12:36:59 PM PST 24 |
| Finished | Jan 03 01:20:04 PM PST 24 |
| Peak memory | 189784 kb |
| Host | smart-53f59d8a-c7b9-4a4f-9f58-afaefce40e27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332599931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.332599931 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3593847496 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 106775560016 ps |
| CPU time | 886.22 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:50:06 PM PST 24 |
| Peak memory | 209168 kb |
| Host | smart-1eac6a95-2f4d-4f4b-b81e-1994489d7d9b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593847496 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3593847496 |
| Directory | /workspace/14.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.347898091 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 345470955725 ps |
| CPU time | 1846.52 seconds |
| Started | Jan 03 12:34:44 PM PST 24 |
| Finished | Jan 03 01:06:39 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-58df0fdd-2d9b-4ede-9c9d-a08b7b64bbb5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347898091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.347898091 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.2265529671 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1127463339360 ps |
| CPU time | 463.49 seconds |
| Started | Jan 03 12:34:12 PM PST 24 |
| Finished | Jan 03 12:43:12 PM PST 24 |
| Peak memory | 191108 kb |
| Host | smart-1cee9426-8799-4a33-8a83-b1a31daa028b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265529671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2265529671 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1325783624 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 10201745043 ps |
| CPU time | 17.2 seconds |
| Started | Jan 03 12:34:14 PM PST 24 |
| Finished | Jan 03 12:35:48 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-8b256653-a55e-41e4-ade0-a8599956eda7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325783624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1325783624 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.1321992697 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 429384361360 ps |
| CPU time | 115.25 seconds |
| Started | Jan 03 12:33:51 PM PST 24 |
| Finished | Jan 03 12:37:23 PM PST 24 |
| Peak memory | 182772 kb |
| Host | smart-742ca588-bdc8-45dc-8cc6-065f4188c949 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321992697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1321992697 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.3417291942 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 21785764119 ps |
| CPU time | 39.04 seconds |
| Started | Jan 03 12:33:54 PM PST 24 |
| Finished | Jan 03 12:36:10 PM PST 24 |
| Peak memory | 182792 kb |
| Host | smart-b836ee50-31d4-4f92-9577-6dbeddbc91b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417291942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3417291942 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.2001215757 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 532924802378 ps |
| CPU time | 928.65 seconds |
| Started | Jan 03 12:33:30 PM PST 24 |
| Finished | Jan 03 12:50:12 PM PST 24 |
| Peak memory | 191016 kb |
| Host | smart-a926c39f-bf1e-4697-9ab7-03a9986ae4a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001215757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .2001215757 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3500817087 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 210442020418 ps |
| CPU time | 315.22 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:40:40 PM PST 24 |
| Peak memory | 209048 kb |
| Host | smart-17bba46c-2e46-49b0-ba5b-90e7641569cf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500817087 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3500817087 |
| Directory | /workspace/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.1129284558 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 33605938225 ps |
| CPU time | 230.93 seconds |
| Started | Jan 03 12:34:43 PM PST 24 |
| Finished | Jan 03 12:40:10 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-1fe3a8d3-a2a6-484c-b852-b0d593453ce3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129284558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1129284558 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.926022739 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 101538308104 ps |
| CPU time | 645.69 seconds |
| Started | Jan 03 12:34:45 PM PST 24 |
| Finished | Jan 03 12:46:54 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-a8524db5-eb41-4b1b-ab25-826766b3d3ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926022739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.926022739 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.2618392220 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 694971186 ps |
| CPU time | 1.54 seconds |
| Started | Jan 03 12:34:35 PM PST 24 |
| Finished | Jan 03 12:36:01 PM PST 24 |
| Peak memory | 182572 kb |
| Host | smart-f7580389-4d22-4b6f-8dcb-6653960e947c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618392220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2618392220 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.4066039486 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1147817321260 ps |
| CPU time | 246.66 seconds |
| Started | Jan 03 12:34:39 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-a8cbcf86-248d-4812-bec2-025d7e9637e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066039486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4066039486 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.3747618340 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 217327060718 ps |
| CPU time | 328.25 seconds |
| Started | Jan 03 12:34:59 PM PST 24 |
| Finished | Jan 03 12:42:10 PM PST 24 |
| Peak memory | 182292 kb |
| Host | smart-88d4be0a-b944-4701-9dc7-f33dd0ddb44d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747618340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3747618340 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.864804930 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 120510402285 ps |
| CPU time | 103.33 seconds |
| Started | Jan 03 12:33:24 PM PST 24 |
| Finished | Jan 03 12:36:31 PM PST 24 |
| Peak memory | 194820 kb |
| Host | smart-48e36536-3add-42d0-8767-34c06176edd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864804930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.864804930 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.3257117189 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 351139382319 ps |
| CPU time | 551.01 seconds |
| Started | Jan 03 12:33:26 PM PST 24 |
| Finished | Jan 03 12:43:45 PM PST 24 |
| Peak memory | 191028 kb |
| Host | smart-0dbbdd00-b7a0-4183-85bc-b5d0c3ea4b77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257117189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .3257117189 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.2182735875 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 248076660051 ps |
| CPU time | 860.63 seconds |
| Started | Jan 03 12:34:34 PM PST 24 |
| Finished | Jan 03 12:50:33 PM PST 24 |
| Peak memory | 191056 kb |
| Host | smart-429f1271-0654-4d2a-90be-7efaf5abcb93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182735875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2182735875 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.1323407195 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 194771821220 ps |
| CPU time | 121.66 seconds |
| Started | Jan 03 12:34:34 PM PST 24 |
| Finished | Jan 03 12:38:21 PM PST 24 |
| Peak memory | 194280 kb |
| Host | smart-7fe872f5-2b5c-488a-a339-a1ba3abdb3be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323407195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1323407195 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.2963740742 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 339185085924 ps |
| CPU time | 778.64 seconds |
| Started | Jan 03 12:34:13 PM PST 24 |
| Finished | Jan 03 12:48:30 PM PST 24 |
| Peak memory | 191016 kb |
| Host | smart-a859f79b-013c-46ad-bf4f-5b6316e7bb56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963740742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2963740742 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.2262504211 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 44184848589 ps |
| CPU time | 154.33 seconds |
| Started | Jan 03 12:34:25 PM PST 24 |
| Finished | Jan 03 12:38:12 PM PST 24 |
| Peak memory | 193120 kb |
| Host | smart-12fafbbb-7b65-480d-bcf8-949f07d843ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262504211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2262504211 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.3958610769 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 8344236882 ps |
| CPU time | 15.15 seconds |
| Started | Jan 03 12:34:27 PM PST 24 |
| Finished | Jan 03 12:36:17 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-968358e6-49ab-48bb-8987-53bf71d3b779 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958610769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3958610769 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.2591632312 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 96255989523 ps |
| CPU time | 152.18 seconds |
| Started | Jan 03 12:33:50 PM PST 24 |
| Finished | Jan 03 12:37:54 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-d6c20d27-7425-463f-948f-92cf8d36d5de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591632312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2591632312 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.2715656133 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 135595040784 ps |
| CPU time | 229.53 seconds |
| Started | Jan 03 12:34:39 PM PST 24 |
| Finished | Jan 03 12:39:47 PM PST 24 |
| Peak memory | 189380 kb |
| Host | smart-305ea1e6-206f-49dc-8c4d-fa192f2793f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715656133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2715656133 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.107369449 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 56197691959 ps |
| CPU time | 88.28 seconds |
| Started | Jan 03 12:33:29 PM PST 24 |
| Finished | Jan 03 12:36:34 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-f8fa318e-161b-43ec-bd1e-26d2e40e2a35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107369449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.107369449 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2301854590 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 37856799520 ps |
| CPU time | 377.39 seconds |
| Started | Jan 03 12:33:38 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 197604 kb |
| Host | smart-cb26104c-3e3c-4512-95d1-04374e7e0b85 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301854590 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2301854590 |
| Directory | /workspace/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.3805025453 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 47419348452 ps |
| CPU time | 22.9 seconds |
| Started | Jan 03 12:34:36 PM PST 24 |
| Finished | Jan 03 12:36:16 PM PST 24 |
| Peak memory | 182840 kb |
| Host | smart-e18f4dcc-97ad-4a8a-ad46-3e3035474f13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805025453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3805025453 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.3491520063 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 224088356820 ps |
| CPU time | 195.63 seconds |
| Started | Jan 03 12:35:59 PM PST 24 |
| Finished | Jan 03 12:40:51 PM PST 24 |
| Peak memory | 193080 kb |
| Host | smart-1fc3cdfc-a311-432e-a65d-3499b4a4a1c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491520063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3491520063 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.2384996181 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 133878301397 ps |
| CPU time | 74.49 seconds |
| Started | Jan 03 12:34:49 PM PST 24 |
| Finished | Jan 03 12:37:18 PM PST 24 |
| Peak memory | 182876 kb |
| Host | smart-1297e2cd-4f57-4ca5-950f-36033004b29e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384996181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2384996181 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.4204936255 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 281648708272 ps |
| CPU time | 138.59 seconds |
| Started | Jan 03 12:34:24 PM PST 24 |
| Finished | Jan 03 12:38:21 PM PST 24 |
| Peak memory | 193408 kb |
| Host | smart-ae3d6720-02de-4f7d-a50d-365b6b311e6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204936255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4204936255 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.1566674272 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5012118960 ps |
| CPU time | 8.78 seconds |
| Started | Jan 03 12:35:44 PM PST 24 |
| Finished | Jan 03 12:37:29 PM PST 24 |
| Peak memory | 181360 kb |
| Host | smart-d9db684a-863f-4cc6-bb1f-49c107e3f062 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566674272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1566674272 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.2248328132 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 643902843080 ps |
| CPU time | 501.85 seconds |
| Started | Jan 03 12:34:45 PM PST 24 |
| Finished | Jan 03 12:44:30 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-f49483ee-1826-4fa9-aead-76d16f469cc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248328132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2248328132 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4003879274 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 778941329792 ps |
| CPU time | 431.81 seconds |
| Started | Jan 03 12:35:14 PM PST 24 |
| Finished | Jan 03 12:44:09 PM PST 24 |
| Peak memory | 182240 kb |
| Host | smart-88e1f32a-b494-4867-84ac-c8197f512f19 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003879274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.4003879274 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.2331547475 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 202459762180 ps |
| CPU time | 267.4 seconds |
| Started | Jan 03 12:34:39 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 181220 kb |
| Host | smart-7ef76b32-5a8d-4c51-ad6b-dffc4e204646 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331547475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2331547475 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.3598184102 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 276776010750 ps |
| CPU time | 78.31 seconds |
| Started | Jan 03 12:33:40 PM PST 24 |
| Finished | Jan 03 12:36:14 PM PST 24 |
| Peak memory | 182784 kb |
| Host | smart-4cc4cfe1-986e-43bf-950b-aa8b65a18c7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598184102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3598184102 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.3690150603 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 29235548910 ps |
| CPU time | 44.53 seconds |
| Started | Jan 03 12:35:19 PM PST 24 |
| Finished | Jan 03 12:37:30 PM PST 24 |
| Peak memory | 182284 kb |
| Host | smart-006b4cd9-4d79-4701-8814-16ad15fa2138 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3690150603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3690150603 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2885787076 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 221694227115 ps |
| CPU time | 787.08 seconds |
| Started | Jan 03 12:35:19 PM PST 24 |
| Finished | Jan 03 12:49:56 PM PST 24 |
| Peak memory | 205628 kb |
| Host | smart-c34051c7-91b7-48c0-b76a-52afeaa4cc0b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885787076 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2885787076 |
| Directory | /workspace/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.4189261836 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 264334808178 ps |
| CPU time | 181.15 seconds |
| Started | Jan 03 12:35:44 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 189492 kb |
| Host | smart-e75ade4f-04e0-4a2c-8d20-d715c9883a14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189261836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4189261836 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.542548231 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 36271129947 ps |
| CPU time | 45.51 seconds |
| Started | Jan 03 12:35:44 PM PST 24 |
| Finished | Jan 03 12:38:06 PM PST 24 |
| Peak memory | 181380 kb |
| Host | smart-37600a51-e943-4444-8f8c-d8540ebbd9d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542548231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.542548231 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.3857845633 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 468702962559 ps |
| CPU time | 440.07 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:42:54 PM PST 24 |
| Peak memory | 193628 kb |
| Host | smart-aeb4799b-26d1-4a09-85d7-3ecfbe4e98ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857845633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3857845633 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.2744760620 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 525618137968 ps |
| CPU time | 258.72 seconds |
| Started | Jan 03 12:34:11 PM PST 24 |
| Finished | Jan 03 12:39:44 PM PST 24 |
| Peak memory | 193064 kb |
| Host | smart-da345cbb-762d-4e20-a92b-fa652e07d7ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744760620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2744760620 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.2544064436 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 279539503570 ps |
| CPU time | 427.62 seconds |
| Started | Jan 03 12:34:27 PM PST 24 |
| Finished | Jan 03 12:42:59 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-7ef7f02a-57e5-4ac0-809e-bb40af49be76 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544064436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2544064436 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.3237296125 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 155411225871 ps |
| CPU time | 366.22 seconds |
| Started | Jan 03 12:34:41 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-4ad72d90-c2f2-4a9d-803a-0df1e0738987 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237296125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3237296125 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1266843926 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 68729682784 ps |
| CPU time | 113.53 seconds |
| Started | Jan 03 12:33:46 PM PST 24 |
| Finished | Jan 03 12:37:01 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-33171c13-3511-423c-8083-f9170ecdb3a8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266843926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.1266843926 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.1480604935 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 432318207328 ps |
| CPU time | 229.82 seconds |
| Started | Jan 03 12:33:54 PM PST 24 |
| Finished | Jan 03 12:39:06 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-e1a8c514-2ac1-406c-895e-d756913c7128 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480604935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1480604935 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.1050934242 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 61128290223 ps |
| CPU time | 30.39 seconds |
| Started | Jan 03 12:33:20 PM PST 24 |
| Finished | Jan 03 12:35:02 PM PST 24 |
| Peak memory | 194212 kb |
| Host | smart-5ce6a881-8ecd-4fdb-b1d1-8ccdc7892555 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050934242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1050934242 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.275642095 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 105969657721 ps |
| CPU time | 214.62 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:38:51 PM PST 24 |
| Peak memory | 205796 kb |
| Host | smart-304f8e95-cde5-4e71-9f61-2e173b87c48d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275642095 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.275642095 |
| Directory | /workspace/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.1524740776 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 132101068271 ps |
| CPU time | 543.85 seconds |
| Started | Jan 03 12:34:19 PM PST 24 |
| Finished | Jan 03 12:44:38 PM PST 24 |
| Peak memory | 194428 kb |
| Host | smart-df01a687-a152-4659-ba63-dc3168cf2cc7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524740776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1524740776 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.782613169 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 50983867043 ps |
| CPU time | 82.61 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:36:33 PM PST 24 |
| Peak memory | 182860 kb |
| Host | smart-bde3dfae-e669-454a-bfec-7ca33b8a5a8c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782613169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.782613169 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.4076943172 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 239132890167 ps |
| CPU time | 134.99 seconds |
| Started | Jan 03 12:34:44 PM PST 24 |
| Finished | Jan 03 12:38:42 PM PST 24 |
| Peak memory | 191040 kb |
| Host | smart-c40da9b7-3dbc-48c7-a3bd-d7c42f7d6d5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076943172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4076943172 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.3120977046 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 101495492663 ps |
| CPU time | 159.32 seconds |
| Started | Jan 03 12:34:32 PM PST 24 |
| Finished | Jan 03 12:38:38 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-2b7a451a-20c5-4974-88c7-9aea86d3ec4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120977046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3120977046 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.3511294307 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 66874776464 ps |
| CPU time | 64.52 seconds |
| Started | Jan 03 12:34:19 PM PST 24 |
| Finished | Jan 03 12:36:40 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-b6b909fa-74a8-4705-8384-08e16801e314 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511294307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3511294307 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.1112304162 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 236208210919 ps |
| CPU time | 708.62 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:47:21 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-67a9f9e2-0a2c-4b06-8ef1-badf02892f75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112304162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1112304162 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.3360445548 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 62931007603 ps |
| CPU time | 323.39 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:40:59 PM PST 24 |
| Peak memory | 191076 kb |
| Host | smart-8e3f010c-86f8-43a7-9573-cb9d627c078a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360445548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3360445548 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.522140923 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 86234501026 ps |
| CPU time | 70.61 seconds |
| Started | Jan 03 12:33:11 PM PST 24 |
| Finished | Jan 03 12:35:52 PM PST 24 |
| Peak memory | 193052 kb |
| Host | smart-fef429bb-aeac-4414-a3d0-5fcc3d11b8c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522140923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.522140923 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.4227384601 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 301770612 ps |
| CPU time | 0.9 seconds |
| Started | Jan 03 12:34:33 PM PST 24 |
| Finished | Jan 03 12:35:45 PM PST 24 |
| Peak memory | 212620 kb |
| Host | smart-24f6fbd3-fd5e-4246-a4a0-0e7d85246369 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227384601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4227384601 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3797780332 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 88212831222 ps |
| CPU time | 295.11 seconds |
| Started | Jan 03 12:33:46 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 205744 kb |
| Host | smart-40b99e8d-57c5-49f1-a19b-103410ef8099 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797780332 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3797780332 |
| Directory | /workspace/2.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.4109152969 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 77862348808 ps |
| CPU time | 119 seconds |
| Started | Jan 03 12:35:33 PM PST 24 |
| Finished | Jan 03 12:39:03 PM PST 24 |
| Peak memory | 182340 kb |
| Host | smart-ed8991d7-3998-4af0-afb1-011314bac5be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109152969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4109152969 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.3067918220 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 77476122688 ps |
| CPU time | 148.05 seconds |
| Started | Jan 03 12:33:41 PM PST 24 |
| Finished | Jan 03 12:37:35 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-aa2f4325-8f81-4d2b-a876-da8842060f29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067918220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3067918220 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.3580331092 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 125206546820 ps |
| CPU time | 160.65 seconds |
| Started | Jan 03 12:33:36 PM PST 24 |
| Finished | Jan 03 12:37:46 PM PST 24 |
| Peak memory | 182860 kb |
| Host | smart-8bba4f5a-4cd4-41e1-bcd1-a30252e7adac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580331092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .3580331092 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.1228935299 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 40851024786 ps |
| CPU time | 16.32 seconds |
| Started | Jan 03 12:33:33 PM PST 24 |
| Finished | Jan 03 12:35:03 PM PST 24 |
| Peak memory | 193704 kb |
| Host | smart-87bd7c29-9cbe-40d0-82c3-e43736473330 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228935299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1228935299 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.2687257649 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 703905908439 ps |
| CPU time | 299.32 seconds |
| Started | Jan 03 12:33:48 PM PST 24 |
| Finished | Jan 03 12:40:10 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-3f74ed71-116a-4628-a4eb-2ded60876059 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687257649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .2687257649 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.1705387015 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 28667607063 ps |
| CPU time | 111.17 seconds |
| Started | Jan 03 12:33:21 PM PST 24 |
| Finished | Jan 03 12:36:33 PM PST 24 |
| Peak memory | 197496 kb |
| Host | smart-162f1c24-e13d-4101-a3d8-1f5787d523f2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705387015 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.1705387015 |
| Directory | /workspace/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3984744077 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 10507231257 ps |
| CPU time | 18.14 seconds |
| Started | Jan 03 12:37:37 PM PST 24 |
| Finished | Jan 03 12:39:06 PM PST 24 |
| Peak memory | 182532 kb |
| Host | smart-8b71020c-c005-44bd-9028-45e691646b2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984744077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.3984744077 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_disabled.48729114 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 50503123845 ps |
| CPU time | 76.85 seconds |
| Started | Jan 03 12:33:46 PM PST 24 |
| Finished | Jan 03 12:36:19 PM PST 24 |
| Peak memory | 182752 kb |
| Host | smart-f1c2b95f-5ec6-475d-aa28-3b2577c17d7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48729114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.48729114 |
| Directory | /workspace/22.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.3927924113 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 66963676503 ps |
| CPU time | 97.97 seconds |
| Started | Jan 03 12:34:29 PM PST 24 |
| Finished | Jan 03 12:37:26 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-a549a2fe-6124-44cf-914c-54f4e3211e20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927924113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3927924113 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.33221381 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 147344413857 ps |
| CPU time | 124.06 seconds |
| Started | Jan 03 12:33:29 PM PST 24 |
| Finished | Jan 03 12:36:58 PM PST 24 |
| Peak memory | 194324 kb |
| Host | smart-b0ec5f0f-6f44-4725-9327-2e8a13c36f78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33221381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.33221381 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2017213838 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 153473693149 ps |
| CPU time | 230.73 seconds |
| Started | Jan 03 12:33:28 PM PST 24 |
| Finished | Jan 03 12:38:32 PM PST 24 |
| Peak memory | 182788 kb |
| Host | smart-6942900f-7822-4943-aad3-100e84fb52e4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017213838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.2017213838 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.2298475491 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 517892307198 ps |
| CPU time | 322.07 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 191088 kb |
| Host | smart-1997d290-883e-4806-9993-4ef340cd89c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298475491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2298475491 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.203141641 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 89833433386 ps |
| CPU time | 172.13 seconds |
| Started | Jan 03 12:43:30 PM PST 24 |
| Finished | Jan 03 12:47:57 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-32de24d2-2652-4a96-a0b8-797586421778 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203141641 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.203141641 |
| Directory | /workspace/23.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.4079873224 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 372597089406 ps |
| CPU time | 282.81 seconds |
| Started | Jan 03 12:33:26 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 182764 kb |
| Host | smart-8a5cab40-773b-4602-bb6a-24fe9d95d1f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079873224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4079873224 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.498168432 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 216532392599 ps |
| CPU time | 1073.75 seconds |
| Started | Jan 03 12:33:51 PM PST 24 |
| Finished | Jan 03 12:52:58 PM PST 24 |
| Peak memory | 193740 kb |
| Host | smart-7a52327d-1259-4e1c-80bb-c7bd47a2b034 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498168432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.498168432 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.2925126034 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8461686548 ps |
| CPU time | 4.79 seconds |
| Started | Jan 03 12:33:42 PM PST 24 |
| Finished | Jan 03 12:35:10 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-a6c65603-4834-472c-b000-c2d86249412f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925126034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2925126034 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1154344822 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 95252874957 ps |
| CPU time | 392.22 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:41:49 PM PST 24 |
| Peak memory | 205740 kb |
| Host | smart-d970b9b1-86d5-43be-ad9c-23c8f7b4d855 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154344822 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1154344822 |
| Directory | /workspace/24.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.376354340 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1553164314158 ps |
| CPU time | 729.55 seconds |
| Started | Jan 03 12:33:46 PM PST 24 |
| Finished | Jan 03 12:47:11 PM PST 24 |
| Peak memory | 182856 kb |
| Host | smart-a5894de0-8ca0-4448-a109-0446761bb83c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376354340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.rv_timer_cfg_update_on_fly.376354340 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.3329613082 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 28310584935 ps |
| CPU time | 16.09 seconds |
| Started | Jan 03 12:33:25 PM PST 24 |
| Finished | Jan 03 12:35:09 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-4c31816c-1a8b-46d8-8efc-8f7e3f19d54a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329613082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3329613082 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2393143523 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 157863007560 ps |
| CPU time | 641.55 seconds |
| Started | Jan 03 12:34:10 PM PST 24 |
| Finished | Jan 03 12:46:43 PM PST 24 |
| Peak memory | 206876 kb |
| Host | smart-d716da64-95e8-4ac3-abf9-ac8ba807410d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393143523 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.2393143523 |
| Directory | /workspace/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3851385483 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 53453949224 ps |
| CPU time | 35.38 seconds |
| Started | Jan 03 12:33:24 PM PST 24 |
| Finished | Jan 03 12:35:35 PM PST 24 |
| Peak memory | 182912 kb |
| Host | smart-4a195dbf-fbba-44d9-8265-9e54a943a76f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851385483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3851385483 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.1749052473 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 232905769937 ps |
| CPU time | 124.49 seconds |
| Started | Jan 03 12:34:02 PM PST 24 |
| Finished | Jan 03 12:37:32 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-d4d2377a-5a01-4c6b-8ca4-cb828cb83378 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749052473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1749052473 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.3319253011 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 219022600049 ps |
| CPU time | 123.88 seconds |
| Started | Jan 03 12:33:11 PM PST 24 |
| Finished | Jan 03 12:36:45 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-a836a7bb-d416-4d94-aabf-eff715d5493d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319253011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3319253011 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2035525142 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 37999256675 ps |
| CPU time | 582.72 seconds |
| Started | Jan 03 12:37:27 PM PST 24 |
| Finished | Jan 03 12:48:19 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-55c2fabb-11ed-41ec-9edc-a48bb577ef74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035525142 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2035525142 |
| Directory | /workspace/26.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3008565236 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 545166931718 ps |
| CPU time | 291.9 seconds |
| Started | Jan 03 12:34:13 PM PST 24 |
| Finished | Jan 03 12:40:16 PM PST 24 |
| Peak memory | 182776 kb |
| Host | smart-83e56ae5-9a52-4a5b-9d3f-258f35503145 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008565236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.3008565236 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.4235120718 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 331628036888 ps |
| CPU time | 212.46 seconds |
| Started | Jan 03 12:33:31 PM PST 24 |
| Finished | Jan 03 12:38:24 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-b273e18b-9023-402f-b628-688ebffed5b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235120718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4235120718 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.4240425485 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 23177590 ps |
| CPU time | 0.58 seconds |
| Started | Jan 03 12:34:08 PM PST 24 |
| Finished | Jan 03 12:35:27 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-7651b9c2-263d-49f5-800b-e8b416f6ee72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240425485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4240425485 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.2130793012 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1583114938854 ps |
| CPU time | 1722.37 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 01:03:48 PM PST 24 |
| Peak memory | 190972 kb |
| Host | smart-d0a9f1aa-d75c-46eb-be21-2afb74311df8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130793012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .2130793012 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2271539495 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 28199815153 ps |
| CPU time | 337.89 seconds |
| Started | Jan 03 12:33:25 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-563e5554-13d4-4129-be8c-b36b692edcfd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271539495 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2271539495 |
| Directory | /workspace/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.1534434845 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 75600839367 ps |
| CPU time | 105.34 seconds |
| Started | Jan 03 12:33:21 PM PST 24 |
| Finished | Jan 03 12:36:26 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-e1ad1d81-6c80-42b1-ad55-5859119345a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534434845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1534434845 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.2529795722 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 100448700006 ps |
| CPU time | 325.94 seconds |
| Started | Jan 03 12:34:03 PM PST 24 |
| Finished | Jan 03 12:40:54 PM PST 24 |
| Peak memory | 191024 kb |
| Host | smart-cf9efcff-1b41-4fff-8d48-4319451351c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529795722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2529795722 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.2503625608 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2614104855459 ps |
| CPU time | 1563.62 seconds |
| Started | Jan 03 12:33:53 PM PST 24 |
| Finished | Jan 03 01:01:12 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-dee6fecd-cedc-429d-ae17-78cd3eb3e845 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503625608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .2503625608 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3595058767 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 172372880901 ps |
| CPU time | 159.19 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:38:22 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-8e95bcd0-7595-4f7d-9ba1-b0a566a52185 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595058767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3595058767 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.2763805112 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 113867797136 ps |
| CPU time | 192.38 seconds |
| Started | Jan 03 12:33:50 PM PST 24 |
| Finished | Jan 03 12:38:43 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-bc3d01d4-ccf9-4073-a07b-7cee0c503756 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763805112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2763805112 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.1314576641 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 32340106471 ps |
| CPU time | 36.63 seconds |
| Started | Jan 03 12:33:24 PM PST 24 |
| Finished | Jan 03 12:35:36 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-3bb134e6-c9c3-4e47-8903-720724665d2e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314576641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1314576641 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.2205860968 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 135259850914 ps |
| CPU time | 278.3 seconds |
| Started | Jan 03 12:33:31 PM PST 24 |
| Finished | Jan 03 12:39:21 PM PST 24 |
| Peak memory | 182920 kb |
| Host | smart-ba41beee-17f8-4e41-ba78-b43bc3cfb2dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205860968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2205860968 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3017740018 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 503355919964 ps |
| CPU time | 315.22 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 207900 kb |
| Host | smart-cdf8a6a9-234f-4055-bb62-c198ced06c8f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017740018 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3017740018 |
| Directory | /workspace/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1729203418 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 302984216590 ps |
| CPU time | 278.97 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 182776 kb |
| Host | smart-367b8999-2035-48f8-9f14-51d77bb6e8d5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729203418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.1729203418 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.2532462584 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 348727974584 ps |
| CPU time | 129.36 seconds |
| Started | Jan 03 12:35:33 PM PST 24 |
| Finished | Jan 03 12:39:14 PM PST 24 |
| Peak memory | 182540 kb |
| Host | smart-dfd1dfea-ff58-4458-94f6-6234798ebbf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532462584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2532462584 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.2044912810 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 221045430 ps |
| CPU time | 0.78 seconds |
| Started | Jan 03 12:33:35 PM PST 24 |
| Finished | Jan 03 12:34:50 PM PST 24 |
| Peak memory | 212788 kb |
| Host | smart-02f41870-cbdd-4164-a3f0-50458629003b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044912810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2044912810 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3978738316 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 21774074005 ps |
| CPU time | 173.84 seconds |
| Started | Jan 03 12:33:47 PM PST 24 |
| Finished | Jan 03 12:38:26 PM PST 24 |
| Peak memory | 197604 kb |
| Host | smart-e3c9a16f-f12b-4980-b1a4-5ad3850ee149 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978738316 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3978738316 |
| Directory | /workspace/3.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.391353192 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 29178770376 ps |
| CPU time | 51.21 seconds |
| Started | Jan 03 12:34:08 PM PST 24 |
| Finished | Jan 03 12:36:18 PM PST 24 |
| Peak memory | 182760 kb |
| Host | smart-8d41c5da-425b-42ab-a8d8-a05a8ec6cb07 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391353192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.rv_timer_cfg_update_on_fly.391353192 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.1654477821 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 264305843095 ps |
| CPU time | 192.99 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:38:20 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-5761c3d5-0967-4f15-94c5-ab5659079dde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654477821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1654477821 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.3913026033 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 909791273 ps |
| CPU time | 1.57 seconds |
| Started | Jan 03 12:34:14 PM PST 24 |
| Finished | Jan 03 12:35:58 PM PST 24 |
| Peak memory | 193100 kb |
| Host | smart-87582096-b675-49c8-8a36-6a11aa6ac6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3913026033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3913026033 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.3476076546 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2187213585459 ps |
| CPU time | 952.7 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:51:09 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-a6b2a9ce-8003-4c1d-a627-1b8445357138 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476076546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .3476076546 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.747933555 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2248563102742 ps |
| CPU time | 1260.89 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:56:01 PM PST 24 |
| Peak memory | 182828 kb |
| Host | smart-879bc8f8-271f-4290-8ce0-ceabeaef8c1b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747933555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.rv_timer_cfg_update_on_fly.747933555 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.3347853294 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 574298694859 ps |
| CPU time | 513.65 seconds |
| Started | Jan 03 12:34:38 PM PST 24 |
| Finished | Jan 03 12:44:20 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-c6648b68-d0d6-45dc-9604-7f96a0bd38f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347853294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3347853294 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.3962960022 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 138805880200 ps |
| CPU time | 657.45 seconds |
| Started | Jan 03 12:34:03 PM PST 24 |
| Finished | Jan 03 12:46:31 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-c86cc255-0a18-4b05-9132-7a7007baa302 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962960022 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.3962960022 |
| Directory | /workspace/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.4195974858 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 438739683355 ps |
| CPU time | 310.43 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:40:13 PM PST 24 |
| Peak memory | 191100 kb |
| Host | smart-c927feb6-9f09-4da9-863c-5e208c6625fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195974858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4195974858 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.3894683864 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8339395623 ps |
| CPU time | 3.68 seconds |
| Started | Jan 03 12:35:10 PM PST 24 |
| Finished | Jan 03 12:36:36 PM PST 24 |
| Peak memory | 190436 kb |
| Host | smart-173c596d-c24f-4923-89aa-c2f209a0c54f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894683864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3894683864 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2732289142 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 80532211549 ps |
| CPU time | 522.33 seconds |
| Started | Jan 03 12:33:35 PM PST 24 |
| Finished | Jan 03 12:43:42 PM PST 24 |
| Peak memory | 197432 kb |
| Host | smart-59c13571-4ba8-47f6-99f4-5895c15c5fbe |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732289142 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2732289142 |
| Directory | /workspace/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.3788461368 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 16270436259 ps |
| CPU time | 26.58 seconds |
| Started | Jan 03 12:33:41 PM PST 24 |
| Finished | Jan 03 12:35:40 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-cbb2abab-f336-4ed9-8205-f4ec9e1e434c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788461368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3788461368 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.2193434193 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 61093855840 ps |
| CPU time | 107.59 seconds |
| Started | Jan 03 12:33:50 PM PST 24 |
| Finished | Jan 03 12:37:20 PM PST 24 |
| Peak memory | 194288 kb |
| Host | smart-7272d90c-0e6e-4c6b-8561-267347630446 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193434193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2193434193 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.2179535612 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 766537174366 ps |
| CPU time | 986.41 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:51:25 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-8fa48dc6-a705-416c-afd0-d92ef1e52395 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179535612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .2179535612 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3877149433 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 16078033764 ps |
| CPU time | 380.49 seconds |
| Started | Jan 03 12:33:51 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 197576 kb |
| Host | smart-47a48b57-3d7c-4fc7-8967-385746f50fc9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877149433 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3877149433 |
| Directory | /workspace/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4189513658 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 327985446260 ps |
| CPU time | 558.09 seconds |
| Started | Jan 03 12:33:54 PM PST 24 |
| Finished | Jan 03 12:44:48 PM PST 24 |
| Peak memory | 182912 kb |
| Host | smart-44b014f0-fcec-41b3-95ac-28977fc0a88e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189513658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.4189513658 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.116628929 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 232942272346 ps |
| CPU time | 92.02 seconds |
| Started | Jan 03 12:33:36 PM PST 24 |
| Finished | Jan 03 12:36:45 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-aa8fd3c7-0626-440d-bf73-d16d83808fc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116628929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.116628929 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.1961487086 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 36952152050 ps |
| CPU time | 16.42 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:35:32 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-95898390-ce5d-4e74-b207-6bb62d807b6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961487086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1961487086 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.3586461271 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 584414257570 ps |
| CPU time | 1487.84 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 01:00:08 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-002ee85f-bb56-4125-b8b2-5a0693534541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586461271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3586461271 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.30234015 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1415645744016 ps |
| CPU time | 590.16 seconds |
| Started | Jan 03 12:35:45 PM PST 24 |
| Finished | Jan 03 12:47:18 PM PST 24 |
| Peak memory | 190824 kb |
| Host | smart-856cfd36-7cd4-419b-a84d-faf4e390e779 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30234015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.30234015 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2245344634 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 470143918040 ps |
| CPU time | 255.46 seconds |
| Started | Jan 03 12:33:53 PM PST 24 |
| Finished | Jan 03 12:39:24 PM PST 24 |
| Peak memory | 182800 kb |
| Host | smart-a6987a0a-9131-47ab-b7ae-6104cf92f521 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245344634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2245344634 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.1528741496 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 34110304008 ps |
| CPU time | 53.32 seconds |
| Started | Jan 03 12:34:11 PM PST 24 |
| Finished | Jan 03 12:36:29 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-0cfb5230-d24f-4f5d-b920-0b5e83f4acfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528741496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1528741496 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.787243114 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 224627546802 ps |
| CPU time | 1618.42 seconds |
| Started | Jan 03 12:33:52 PM PST 24 |
| Finished | Jan 03 01:02:23 PM PST 24 |
| Peak memory | 194368 kb |
| Host | smart-5d30dc16-2e40-44cf-891b-50c0ceae7a6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787243114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.787243114 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.789656382 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 9476699737 ps |
| CPU time | 57.03 seconds |
| Started | Jan 03 12:33:41 PM PST 24 |
| Finished | Jan 03 12:35:56 PM PST 24 |
| Peak memory | 182808 kb |
| Host | smart-c684c277-9c17-4432-a424-87d0c853c03b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789656382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.789656382 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.3419116351 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 368898108756 ps |
| CPU time | 304.43 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 193948 kb |
| Host | smart-08e45428-9eef-430e-8dce-21f1afd42c92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419116351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .3419116351 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1611483774 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 179263107684 ps |
| CPU time | 563.52 seconds |
| Started | Jan 03 12:34:24 PM PST 24 |
| Finished | Jan 03 12:45:04 PM PST 24 |
| Peak memory | 197584 kb |
| Host | smart-f0f71dc0-3841-4b86-9546-55ec181101da |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611483774 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1611483774 |
| Directory | /workspace/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3385322312 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 507805731231 ps |
| CPU time | 910.16 seconds |
| Started | Jan 03 12:33:31 PM PST 24 |
| Finished | Jan 03 12:50:22 PM PST 24 |
| Peak memory | 182772 kb |
| Host | smart-3dde2e11-bb4a-40ab-ad39-6a36b7011a4d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385322312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.3385322312 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.415384774 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 503881073106 ps |
| CPU time | 191 seconds |
| Started | Jan 03 12:33:31 PM PST 24 |
| Finished | Jan 03 12:38:04 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-daace10b-2556-4fab-97dc-365a6a78fd82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415384774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.415384774 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.4151106364 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1459003550694 ps |
| CPU time | 694.83 seconds |
| Started | Jan 03 12:34:03 PM PST 24 |
| Finished | Jan 03 12:47:07 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-8d943e4d-22af-454e-ac1b-ddfb76e9c772 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151106364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .4151106364 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.166925339 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 148685255834 ps |
| CPU time | 824.05 seconds |
| Started | Jan 03 12:34:24 PM PST 24 |
| Finished | Jan 03 12:49:27 PM PST 24 |
| Peak memory | 209732 kb |
| Host | smart-3c1ed2b3-5df5-4a7a-aeb4-029d57d48732 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166925339 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.166925339 |
| Directory | /workspace/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2932730921 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 196876987202 ps |
| CPU time | 183.56 seconds |
| Started | Jan 03 12:33:42 PM PST 24 |
| Finished | Jan 03 12:38:13 PM PST 24 |
| Peak memory | 182860 kb |
| Host | smart-b1904f95-b35c-4660-b676-1ff021062e99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932730921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2932730921 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.183213402 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 303370224800 ps |
| CPU time | 242.87 seconds |
| Started | Jan 03 12:33:46 PM PST 24 |
| Finished | Jan 03 12:39:17 PM PST 24 |
| Peak memory | 182780 kb |
| Host | smart-f87d48b9-0859-4932-9667-e55614880ba2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183213402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.183213402 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.4191799501 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 19808396531 ps |
| CPU time | 42.46 seconds |
| Started | Jan 03 12:33:51 PM PST 24 |
| Finished | Jan 03 12:36:07 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-c53256b1-7249-4f4f-8f23-887596f09797 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191799501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.4191799501 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.1268223931 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 168275020681 ps |
| CPU time | 783.43 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:48:02 PM PST 24 |
| Peak memory | 182892 kb |
| Host | smart-c6a371a2-d90d-4512-81bf-b255bef62c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268223931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1268223931 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.2408210192 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 81361429 ps |
| CPU time | 0.65 seconds |
| Started | Jan 03 12:33:35 PM PST 24 |
| Finished | Jan 03 12:34:53 PM PST 24 |
| Peak memory | 182568 kb |
| Host | smart-2d7a1609-e84c-4157-82fe-24b1c8f492b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408210192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .2408210192 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.1427593166 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 114746736377 ps |
| CPU time | 954.75 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:51:28 PM PST 24 |
| Peak memory | 208656 kb |
| Host | smart-6a450ffc-a585-464e-951f-ea4a0cdd9376 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427593166 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.1427593166 |
| Directory | /workspace/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.67531978 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1973157975531 ps |
| CPU time | 845.86 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:49:38 PM PST 24 |
| Peak memory | 182816 kb |
| Host | smart-eec50638-4054-4312-b68e-8e069e7dde8a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67531978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .rv_timer_cfg_update_on_fly.67531978 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.3551057550 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 288470730877 ps |
| CPU time | 45.89 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:35:57 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-1f02b63b-91e0-47f7-9935-f60a082ceeef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551057550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3551057550 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.2688927588 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 44168081452 ps |
| CPU time | 105.86 seconds |
| Started | Jan 03 12:34:15 PM PST 24 |
| Finished | Jan 03 12:37:38 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-54b37836-d2db-4403-af3d-c232e1a5607c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688927588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2688927588 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.4149567650 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 431171911187 ps |
| CPU time | 709.24 seconds |
| Started | Jan 03 12:33:50 PM PST 24 |
| Finished | Jan 03 12:47:22 PM PST 24 |
| Peak memory | 209900 kb |
| Host | smart-461b2b9b-2b0a-4c3d-b53a-84e28a310aa9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149567650 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.4149567650 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2364285440 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1084286666689 ps |
| CPU time | 602.98 seconds |
| Started | Jan 03 12:34:07 PM PST 24 |
| Finished | Jan 03 12:45:27 PM PST 24 |
| Peak memory | 182888 kb |
| Host | smart-58c7eca4-8997-4326-8acf-992f29f55dfe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364285440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.2364285440 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.945938265 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 70920324769 ps |
| CPU time | 121.89 seconds |
| Started | Jan 03 12:33:47 PM PST 24 |
| Finished | Jan 03 12:37:34 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-3100889e-55ff-45e3-bfc9-dd429d8ef1a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945938265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.945938265 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.965000583 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 36045773405 ps |
| CPU time | 108.37 seconds |
| Started | Jan 03 12:33:51 PM PST 24 |
| Finished | Jan 03 12:37:16 PM PST 24 |
| Peak memory | 192156 kb |
| Host | smart-b5ad5a10-798e-416f-8047-4c32bd4a5284 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965000583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.965000583 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.2846619015 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 617334416315 ps |
| CPU time | 267.7 seconds |
| Started | Jan 03 12:34:14 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-da1ac8fe-3379-4c8a-b468-0d36f3120480 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846619015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2846619015 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.2621069635 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 414460068927 ps |
| CPU time | 602.65 seconds |
| Started | Jan 03 12:34:05 PM PST 24 |
| Finished | Jan 03 12:45:24 PM PST 24 |
| Peak memory | 190956 kb |
| Host | smart-a6aa40b1-ded4-499f-97ad-c1d86841df82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621069635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .2621069635 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2755586679 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 77578447787 ps |
| CPU time | 617.07 seconds |
| Started | Jan 03 12:34:12 PM PST 24 |
| Finished | Jan 03 12:45:53 PM PST 24 |
| Peak memory | 206340 kb |
| Host | smart-fe9c35f3-6f84-46f6-a9c7-c6377072f1f8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755586679 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2755586679 |
| Directory | /workspace/39.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3629763656 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 277981448547 ps |
| CPU time | 431.2 seconds |
| Started | Jan 03 12:34:43 PM PST 24 |
| Finished | Jan 03 12:43:16 PM PST 24 |
| Peak memory | 182436 kb |
| Host | smart-7b5a0236-cdb5-44de-af7f-9a6202579715 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629763656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3629763656 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_disabled.2697027175 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 181247630479 ps |
| CPU time | 56.32 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:35:59 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-4248a33e-abef-44da-94a8-f8dacad368ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697027175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2697027175 |
| Directory | /workspace/4.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.4122733855 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 22635907411 ps |
| CPU time | 32.14 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:35:27 PM PST 24 |
| Peak memory | 182616 kb |
| Host | smart-543c9e65-86f3-43b7-a94a-aec1ad594afc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122733855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4122733855 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.481183272 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 156824669 ps |
| CPU time | 0.97 seconds |
| Started | Jan 03 12:33:48 PM PST 24 |
| Finished | Jan 03 12:35:12 PM PST 24 |
| Peak memory | 213872 kb |
| Host | smart-8e5e7a08-4304-44e5-9ebc-0e9cbfb331db |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481183272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.481183272 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3785878175 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 21462533729 ps |
| CPU time | 220.23 seconds |
| Started | Jan 03 12:35:12 PM PST 24 |
| Finished | Jan 03 12:40:26 PM PST 24 |
| Peak memory | 197268 kb |
| Host | smart-72a96685-035d-4190-b8fe-bf0514114c30 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785878175 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3785878175 |
| Directory | /workspace/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2992508214 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5673163939 ps |
| CPU time | 9.61 seconds |
| Started | Jan 03 12:33:38 PM PST 24 |
| Finished | Jan 03 12:35:16 PM PST 24 |
| Peak memory | 182804 kb |
| Host | smart-fa141710-0528-4498-a8c8-60e3d7900938 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992508214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.2992508214 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.3945032506 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 226685389630 ps |
| CPU time | 79.36 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:36:35 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-69461aa1-7d84-44bc-b609-68312327d194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945032506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3945032506 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.2745603218 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 359636738 ps |
| CPU time | 3.01 seconds |
| Started | Jan 03 12:33:54 PM PST 24 |
| Finished | Jan 03 12:35:53 PM PST 24 |
| Peak memory | 182768 kb |
| Host | smart-9ca38e35-1c22-4684-81b1-93d2bfcf1511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745603218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2745603218 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.3395620610 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 318588594789 ps |
| CPU time | 221.28 seconds |
| Started | Jan 03 12:34:17 PM PST 24 |
| Finished | Jan 03 12:39:16 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-a79f6f05-63ee-4a3d-b23d-c350b534b847 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395620610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3395620610 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.1268198386 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 82356383761 ps |
| CPU time | 42.67 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:35:58 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-e52be2c7-622d-47bc-8928-746d45aa810e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268198386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1268198386 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.3707638689 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 483630902833 ps |
| CPU time | 232.89 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:39:09 PM PST 24 |
| Peak memory | 194948 kb |
| Host | smart-c6596c2a-4013-415c-b33f-16b29d5575dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707638689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all .3707638689 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2392045296 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 87966097748 ps |
| CPU time | 772.82 seconds |
| Started | Jan 03 12:33:51 PM PST 24 |
| Finished | Jan 03 12:48:17 PM PST 24 |
| Peak memory | 206796 kb |
| Host | smart-9bc0a203-805b-4f9f-a45c-57a58ac9d807 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392045296 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2392045296 |
| Directory | /workspace/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3882197546 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 121841802841 ps |
| CPU time | 216.11 seconds |
| Started | Jan 03 12:33:49 PM PST 24 |
| Finished | Jan 03 12:38:48 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-2c35b7a0-727b-4ad8-b9bc-f015e6093a67 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882197546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3882197546 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.2577798940 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 162203221135 ps |
| CPU time | 109.13 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:37:00 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-b6b36eff-7986-4e3a-9d38-a06b06c15486 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577798940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2577798940 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3337076003 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 210829954431 ps |
| CPU time | 120.21 seconds |
| Started | Jan 03 12:35:35 PM PST 24 |
| Finished | Jan 03 12:39:07 PM PST 24 |
| Peak memory | 182464 kb |
| Host | smart-e7a2ae00-3454-435c-9771-df05e16026ac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337076003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3337076003 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.1930080858 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 25317469735 ps |
| CPU time | 21.26 seconds |
| Started | Jan 03 12:33:52 PM PST 24 |
| Finished | Jan 03 12:35:53 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-94ef7ea3-be88-4993-81cf-e9691fc4ef0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930080858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1930080858 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.3627810766 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 83143928215 ps |
| CPU time | 58.21 seconds |
| Started | Jan 03 12:34:30 PM PST 24 |
| Finished | Jan 03 12:36:53 PM PST 24 |
| Peak memory | 195112 kb |
| Host | smart-0493d6c9-64c5-49ed-a2cb-4893482b5d0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627810766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3627810766 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.934457416 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 83063892169 ps |
| CPU time | 127.99 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:37:39 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-9d058348-11aa-407b-8254-9fd8fc9abe27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934457416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all. 934457416 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.988894336 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 88691655840 ps |
| CPU time | 625.37 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:45:57 PM PST 24 |
| Peak memory | 208004 kb |
| Host | smart-865421a1-db4c-4769-8dfb-4351d907bb90 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988894336 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.988894336 |
| Directory | /workspace/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.361501661 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 230027438368 ps |
| CPU time | 401.31 seconds |
| Started | Jan 03 12:34:18 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-e5c4941c-3f8a-4f93-b87d-22ed5f5bc2cc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361501661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.rv_timer_cfg_update_on_fly.361501661 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.112030840 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 261012912078 ps |
| CPU time | 201.89 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:38:33 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-7eaf254c-6b04-45f8-816c-30471b2f754b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112030840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.112030840 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.4177264968 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 350561196745 ps |
| CPU time | 226.75 seconds |
| Started | Jan 03 12:34:26 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 193136 kb |
| Host | smart-df09a752-da8b-494b-8bb9-53f915b05390 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177264968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4177264968 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.1188858783 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 32806001300 ps |
| CPU time | 29.51 seconds |
| Started | Jan 03 12:34:13 PM PST 24 |
| Finished | Jan 03 12:36:04 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-5a1b92c1-2736-417a-8151-95bf76688690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188858783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1188858783 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.2494491440 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 244847120221 ps |
| CPU time | 342.98 seconds |
| Started | Jan 03 12:34:28 PM PST 24 |
| Finished | Jan 03 12:41:29 PM PST 24 |
| Peak memory | 191068 kb |
| Host | smart-2b0dd37c-074b-41ff-ae0b-5de132185f54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494491440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .2494491440 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3356858492 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 281290818443 ps |
| CPU time | 1047.58 seconds |
| Started | Jan 03 12:34:02 PM PST 24 |
| Finished | Jan 03 12:53:02 PM PST 24 |
| Peak memory | 211088 kb |
| Host | smart-c169626d-9102-4852-ab31-bdfc804b5437 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356858492 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3356858492 |
| Directory | /workspace/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.2601782678 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 211267101863 ps |
| CPU time | 78.3 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:36:49 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-16737168-adf1-4995-80f4-9c41797a9ab8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601782678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2601782678 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.839972661 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 114087089318 ps |
| CPU time | 482.38 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:43:21 PM PST 24 |
| Peak memory | 190976 kb |
| Host | smart-1b5a35cc-adab-46a9-8a47-719321402fa1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839972661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.839972661 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.749008487 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 244486778223 ps |
| CPU time | 108.34 seconds |
| Started | Jan 03 12:34:09 PM PST 24 |
| Finished | Jan 03 12:37:24 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-3d915351-3382-47e7-88d1-055ee0aa8966 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749008487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.749008487 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.532491072 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 24892113 ps |
| CPU time | 0.54 seconds |
| Started | Jan 03 12:34:40 PM PST 24 |
| Finished | Jan 03 12:36:01 PM PST 24 |
| Peak memory | 182484 kb |
| Host | smart-36b5b6c9-50b9-4c9b-8bc4-bcf44f3e6674 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532491072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 532491072 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.880848520 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1046919579116 ps |
| CPU time | 457.88 seconds |
| Started | Jan 03 12:34:50 PM PST 24 |
| Finished | Jan 03 12:43:47 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-4e4f1dce-ffab-48af-b470-571daa8e3c00 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880848520 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.880848520 |
| Directory | /workspace/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2459079692 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 214072115295 ps |
| CPU time | 69.32 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:36:43 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-f0749e7e-861a-46a2-8d7b-14bce6f65e0f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459079692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2459079692 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.4117637840 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 274145005150 ps |
| CPU time | 126.52 seconds |
| Started | Jan 03 12:34:14 PM PST 24 |
| Finished | Jan 03 12:37:37 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-a755a654-5e47-4117-993c-3440c51b65d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117637840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4117637840 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.1376917548 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 19470785261 ps |
| CPU time | 9.27 seconds |
| Started | Jan 03 12:33:52 PM PST 24 |
| Finished | Jan 03 12:35:13 PM PST 24 |
| Peak memory | 182860 kb |
| Host | smart-455b45f9-0e6f-4a81-8b13-fc86abe3c1be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376917548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1376917548 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.120265993 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 40035273522 ps |
| CPU time | 428.55 seconds |
| Started | Jan 03 12:34:29 PM PST 24 |
| Finished | Jan 03 12:42:57 PM PST 24 |
| Peak memory | 182876 kb |
| Host | smart-47afb532-28e0-4999-83ce-138badc35fea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120265993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all. 120265993 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.976477709 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 61993911892 ps |
| CPU time | 688.15 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:46:36 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-52d9f3d9-ec64-4c72-9405-5717a4e04635 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976477709 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.976477709 |
| Directory | /workspace/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1095995880 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 136021281880 ps |
| CPU time | 60.11 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:36:20 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-e17b8fa8-8e11-410d-8ee3-541505ff5669 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095995880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.1095995880 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.2874017953 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 120234172549 ps |
| CPU time | 194.92 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:38:31 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-8b540e0f-4c8c-45fd-8413-8acd722dbcaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874017953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2874017953 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.2620277231 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 908519162 ps |
| CPU time | 1.8 seconds |
| Started | Jan 03 12:34:54 PM PST 24 |
| Finished | Jan 03 12:36:09 PM PST 24 |
| Peak memory | 182672 kb |
| Host | smart-eb7e9433-38a4-4558-9f2b-9432aaf5f308 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620277231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2620277231 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3399705825 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 122911770083 ps |
| CPU time | 185.16 seconds |
| Started | Jan 03 12:34:17 PM PST 24 |
| Finished | Jan 03 12:38:39 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-feef9e32-985a-4cc2-9ab6-90a85ad48c9f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399705825 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3399705825 |
| Directory | /workspace/47.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.4255797763 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 128698784146 ps |
| CPU time | 109.49 seconds |
| Started | Jan 03 12:34:48 PM PST 24 |
| Finished | Jan 03 12:38:02 PM PST 24 |
| Peak memory | 182800 kb |
| Host | smart-25d2921f-9ab1-451e-b290-b361988df35b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255797763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4255797763 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.3496748537 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 96137643550 ps |
| CPU time | 89.43 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:36:40 PM PST 24 |
| Peak memory | 191108 kb |
| Host | smart-5172705a-6b95-4c1b-bedc-540420817570 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496748537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3496748537 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.1917231827 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 118718184940 ps |
| CPU time | 223.43 seconds |
| Started | Jan 03 12:34:29 PM PST 24 |
| Finished | Jan 03 12:39:31 PM PST 24 |
| Peak memory | 194280 kb |
| Host | smart-95a9811a-65d7-466c-b9a6-07a9dfd8be91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917231827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1917231827 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.3094178827 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 812935628666 ps |
| CPU time | 1485.39 seconds |
| Started | Jan 03 12:34:15 PM PST 24 |
| Finished | Jan 03 01:00:21 PM PST 24 |
| Peak memory | 191016 kb |
| Host | smart-3e029ee3-3efe-4ee2-be53-b0ece7b3e71c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094178827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .3094178827 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.2936437330 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 16142570835 ps |
| CPU time | 152.17 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:37:43 PM PST 24 |
| Peak memory | 197552 kb |
| Host | smart-1cee1100-ddc4-490d-aca5-57098d72bc40 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936437330 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.2936437330 |
| Directory | /workspace/48.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4218559645 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 98047003153 ps |
| CPU time | 55.78 seconds |
| Started | Jan 03 12:34:40 PM PST 24 |
| Finished | Jan 03 12:36:53 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-5eae4d6c-69bf-431d-8dfd-e50660b3f713 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218559645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.4218559645 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.1540047522 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 202298359311 ps |
| CPU time | 157.82 seconds |
| Started | Jan 03 12:34:32 PM PST 24 |
| Finished | Jan 03 12:38:37 PM PST 24 |
| Peak memory | 182888 kb |
| Host | smart-f2408166-0309-49c7-8209-a5978a7a279a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540047522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1540047522 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.1329103994 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 111944489 ps |
| CPU time | 2.46 seconds |
| Started | Jan 03 12:34:35 PM PST 24 |
| Finished | Jan 03 12:35:56 PM PST 24 |
| Peak memory | 190916 kb |
| Host | smart-3ca10111-ae5d-4ace-a858-11db5f002df0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329103994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1329103994 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1743364422 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 66796657362 ps |
| CPU time | 276.83 seconds |
| Started | Jan 03 12:34:15 PM PST 24 |
| Finished | Jan 03 12:40:17 PM PST 24 |
| Peak memory | 197564 kb |
| Host | smart-cdb76511-9d09-4346-978d-3ae7eb7a0d37 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743364422 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1743364422 |
| Directory | /workspace/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4138289570 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 393122536247 ps |
| CPU time | 671.77 seconds |
| Started | Jan 03 12:33:31 PM PST 24 |
| Finished | Jan 03 12:45:55 PM PST 24 |
| Peak memory | 182792 kb |
| Host | smart-7fceace2-aef8-4d49-b7c8-6397c987b68d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138289570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.4138289570 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.2541213547 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 103753963146 ps |
| CPU time | 164.64 seconds |
| Started | Jan 03 12:33:13 PM PST 24 |
| Finished | Jan 03 12:37:21 PM PST 24 |
| Peak memory | 182876 kb |
| Host | smart-0dbf1cab-f97c-43f0-b2a5-f8cd95f772d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541213547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2541213547 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3933009345 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 17260610451 ps |
| CPU time | 146.97 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:37:34 PM PST 24 |
| Peak memory | 197728 kb |
| Host | smart-76f5a314-0c1f-4b6d-9337-d6dc567d17da |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933009345 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3933009345 |
| Directory | /workspace/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.2108084086 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 37603258130 ps |
| CPU time | 63.31 seconds |
| Started | Jan 03 12:34:02 PM PST 24 |
| Finished | Jan 03 12:36:17 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-afa05690-8033-45be-b378-872bfe3a79d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108084086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2108084086 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.116510856 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 18307774012 ps |
| CPU time | 16.92 seconds |
| Started | Jan 03 12:34:57 PM PST 24 |
| Finished | Jan 03 12:36:36 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-373500e0-9cf8-4c7c-9183-fe8605627531 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116510856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.116510856 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.1041812287 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 108609914783 ps |
| CPU time | 233.22 seconds |
| Started | Jan 03 12:34:44 PM PST 24 |
| Finished | Jan 03 12:40:17 PM PST 24 |
| Peak memory | 191056 kb |
| Host | smart-a0a6a7ea-d8b5-4e56-a09e-3c9d84184421 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041812287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1041812287 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.909222769 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 155645199366 ps |
| CPU time | 244.37 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:39:19 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-c0a0e1aa-060b-45be-aef5-92037128e90d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909222769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.909222769 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.1808911733 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 213032822649 ps |
| CPU time | 241.87 seconds |
| Started | Jan 03 12:34:34 PM PST 24 |
| Finished | Jan 03 12:39:52 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-0f421a64-0d5b-4294-af05-2c3b7aa33b41 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808911733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1808911733 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.1757603932 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 490150631736 ps |
| CPU time | 266.83 seconds |
| Started | Jan 03 12:34:02 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-d49c877a-b7e4-4bf5-ad46-bd4afc5e7b53 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757603932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1757603932 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.3167102093 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 409700903278 ps |
| CPU time | 347.19 seconds |
| Started | Jan 03 12:34:20 PM PST 24 |
| Finished | Jan 03 12:41:29 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-c29adaf9-eeae-4fdb-a7e1-97872de3db11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167102093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3167102093 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1630635538 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 309695325551 ps |
| CPU time | 580.7 seconds |
| Started | Jan 03 12:33:43 PM PST 24 |
| Finished | Jan 03 12:44:52 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-ee53e3bd-556a-46d1-a311-95850ba87c00 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630635538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.1630635538 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.1353568094 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 206298111338 ps |
| CPU time | 271.07 seconds |
| Started | Jan 03 12:33:15 PM PST 24 |
| Finished | Jan 03 12:39:16 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-b0766443-3da0-451a-b518-7c0bd7de0876 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353568094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1353568094 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.3126818575 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 89775498024 ps |
| CPU time | 180.17 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:38:15 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-008d826e-5ec7-4977-9176-da1ebc3f2c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126818575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3126818575 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.1944806485 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 79078460492 ps |
| CPU time | 70.94 seconds |
| Started | Jan 03 12:34:09 PM PST 24 |
| Finished | Jan 03 12:36:34 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-c5dca3bf-d8f4-4470-9a48-935a4f739967 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944806485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1944806485 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.695561537 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 30562627387 ps |
| CPU time | 58.65 seconds |
| Started | Jan 03 12:33:53 PM PST 24 |
| Finished | Jan 03 12:36:07 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-b015a529-e90e-4d55-87bb-8273c94ac99a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695561537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.695561537 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.2425794296 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 477872688410 ps |
| CPU time | 678.93 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:46:54 PM PST 24 |
| Peak memory | 190996 kb |
| Host | smart-0979626b-7996-42f0-9e98-12835fe5ff6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425794296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2425794296 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.4245460878 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 125175670937 ps |
| CPU time | 66.71 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:36:39 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-5844e665-6e56-4f22-88cc-5ece3a8ce93d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245460878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.4245460878 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.1885054405 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 104242016823 ps |
| CPU time | 53.6 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:36:27 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-92caa510-b7f7-4d8f-abfd-e8eb82b749d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885054405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1885054405 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.3655108803 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 309360536478 ps |
| CPU time | 754.62 seconds |
| Started | Jan 03 12:34:06 PM PST 24 |
| Finished | Jan 03 12:48:09 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-2b04f8df-f3c9-4038-a429-b13b435910b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655108803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3655108803 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.2733659606 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 169910577879 ps |
| CPU time | 121.73 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:37:26 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-8af35ee8-983b-414d-93f0-b2de793036cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733659606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2733659606 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3013141328 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 33819327687 ps |
| CPU time | 34.35 seconds |
| Started | Jan 03 12:33:28 PM PST 24 |
| Finished | Jan 03 12:35:15 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-91292923-b9df-4850-9184-07026fc14694 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013141328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3013141328 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.547671538 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 50731263318 ps |
| CPU time | 28.7 seconds |
| Started | Jan 03 12:35:15 PM PST 24 |
| Finished | Jan 03 12:37:08 PM PST 24 |
| Peak memory | 182492 kb |
| Host | smart-e744c15b-6499-4035-9539-a13f391e551b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547671538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.547671538 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.27103382 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 12269672323 ps |
| CPU time | 76.95 seconds |
| Started | Jan 03 12:37:56 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 197292 kb |
| Host | smart-2143e090-798b-4912-bf33-26ba8de38315 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103382 -assert nopos tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.27103382 |
| Directory | /workspace/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.1083629401 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 68557194455 ps |
| CPU time | 127.63 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:37:22 PM PST 24 |
| Peak memory | 191012 kb |
| Host | smart-93fbc326-6a9c-447e-9976-96653d144b12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083629401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1083629401 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.2512388984 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 306980196689 ps |
| CPU time | 143.22 seconds |
| Started | Jan 03 12:33:48 PM PST 24 |
| Finished | Jan 03 12:37:41 PM PST 24 |
| Peak memory | 191016 kb |
| Host | smart-015b849c-4254-4e77-8978-0c6da9ed1078 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512388984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2512388984 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.3046750244 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 90346309230 ps |
| CPU time | 33.89 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:36:05 PM PST 24 |
| Peak memory | 182740 kb |
| Host | smart-047bf983-b316-43fc-855f-18b215dd93bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046750244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3046750244 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.1195400184 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 78779974811 ps |
| CPU time | 168.05 seconds |
| Started | Jan 03 12:34:23 PM PST 24 |
| Finished | Jan 03 12:38:47 PM PST 24 |
| Peak memory | 190940 kb |
| Host | smart-1a3e1997-14cd-42d6-a6a8-f41565e6794c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195400184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1195400184 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.3877736438 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 434866923642 ps |
| CPU time | 157.27 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:37:54 PM PST 24 |
| Peak memory | 191064 kb |
| Host | smart-889dac6d-02c1-472f-9599-db47f94ce7e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877736438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3877736438 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.2656517300 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 56262299193 ps |
| CPU time | 171.97 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:37:59 PM PST 24 |
| Peak memory | 190956 kb |
| Host | smart-dc893754-014b-4750-a679-86bf9afe157b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656517300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2656517300 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.695528842 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1192133008951 ps |
| CPU time | 631.36 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:45:49 PM PST 24 |
| Peak memory | 182804 kb |
| Host | smart-bdab663e-3599-49af-8003-a4149f2676d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695528842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .rv_timer_cfg_update_on_fly.695528842 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.3493422756 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 422474768194 ps |
| CPU time | 186.21 seconds |
| Started | Jan 03 12:33:40 PM PST 24 |
| Finished | Jan 03 12:38:02 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-b503fe55-1186-4e6e-9d17-9aa930e6fe86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493422756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3493422756 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.480630763 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 36113075966 ps |
| CPU time | 104.89 seconds |
| Started | Jan 03 12:33:45 PM PST 24 |
| Finished | Jan 03 12:37:09 PM PST 24 |
| Peak memory | 182816 kb |
| Host | smart-a71bac94-30b9-4664-b7d7-f6d8b18a5902 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480630763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.480630763 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.292634253 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 22895596749 ps |
| CPU time | 3.73 seconds |
| Started | Jan 03 12:33:40 PM PST 24 |
| Finished | Jan 03 12:35:16 PM PST 24 |
| Peak memory | 182592 kb |
| Host | smart-47b11a12-a2bc-49a2-ad84-6ea8c9d11f2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292634253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.292634253 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.1789333181 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 209314418416 ps |
| CPU time | 311.65 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 194800 kb |
| Host | smart-362a4d08-647a-4e83-9bcf-aeb1ddf1f31e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789333181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 1789333181 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.4154197804 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 200784447451 ps |
| CPU time | 1201.85 seconds |
| Started | Jan 03 12:33:57 PM PST 24 |
| Finished | Jan 03 12:55:26 PM PST 24 |
| Peak memory | 193116 kb |
| Host | smart-45433f6c-3471-4b2d-b855-392d3326b9fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154197804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4154197804 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.3269203341 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 178971702850 ps |
| CPU time | 144.4 seconds |
| Started | Jan 03 12:33:55 PM PST 24 |
| Finished | Jan 03 12:37:42 PM PST 24 |
| Peak memory | 191064 kb |
| Host | smart-2513de50-7450-446b-9ba5-7e76940277cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269203341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3269203341 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.1842424233 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 157585290030 ps |
| CPU time | 139.18 seconds |
| Started | Jan 03 12:35:03 PM PST 24 |
| Finished | Jan 03 12:38:38 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-772e2c54-e5bd-4be2-91a7-fc8ca4a6d3e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842424233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1842424233 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.1007624018 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 155857235505 ps |
| CPU time | 666.98 seconds |
| Started | Jan 03 12:34:03 PM PST 24 |
| Finished | Jan 03 12:46:31 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-286511af-fd49-4bb7-a843-0bfba5b5953a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007624018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1007624018 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.2779473970 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 28964106913 ps |
| CPU time | 39.61 seconds |
| Started | Jan 03 12:34:28 PM PST 24 |
| Finished | Jan 03 12:36:28 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-5a4a7f6d-f022-4146-94d2-dbbc8830e192 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779473970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2779473970 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.804223811 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 79243482039 ps |
| CPU time | 202.04 seconds |
| Started | Jan 03 12:34:19 PM PST 24 |
| Finished | Jan 03 12:39:06 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-6af7f6c1-4ae4-48ca-ad62-9129db28bb74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804223811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.804223811 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.2754796446 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 108137906935 ps |
| CPU time | 250.22 seconds |
| Started | Jan 03 12:33:56 PM PST 24 |
| Finished | Jan 03 12:39:18 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-cb448d90-9043-460a-be5e-5b12fc2cc513 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754796446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2754796446 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.133015329 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 91963003957 ps |
| CPU time | 201.1 seconds |
| Started | Jan 03 12:34:25 PM PST 24 |
| Finished | Jan 03 12:39:01 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-67554037-59b0-4927-af74-25d0289659e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133015329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.133015329 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.483621674 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 189514192913 ps |
| CPU time | 280.06 seconds |
| Started | Jan 03 12:33:25 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-9fc5ede3-6f18-4457-a87b-1e5994cf2f3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483621674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.483621674 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.88200828 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 330520867393 ps |
| CPU time | 108.94 seconds |
| Started | Jan 03 12:37:47 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 182556 kb |
| Host | smart-bac94212-d727-4d33-af96-0efcc0e39b30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88200828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.88200828 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.2977592277 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 419908661759 ps |
| CPU time | 399.36 seconds |
| Started | Jan 03 12:33:29 PM PST 24 |
| Finished | Jan 03 12:41:19 PM PST 24 |
| Peak memory | 191016 kb |
| Host | smart-288e86ae-7a47-4666-86a1-c67789b9c64c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977592277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 2977592277 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.4278645571 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 97538669776 ps |
| CPU time | 685.4 seconds |
| Started | Jan 03 12:33:40 PM PST 24 |
| Finished | Jan 03 12:46:25 PM PST 24 |
| Peak memory | 205804 kb |
| Host | smart-c5153f6a-efa1-461f-a130-6af71467c498 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278645571 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.4278645571 |
| Directory | /workspace/9.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.380291431 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 110875564761 ps |
| CPU time | 198.38 seconds |
| Started | Jan 03 12:34:04 PM PST 24 |
| Finished | Jan 03 12:39:15 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-31e3375c-ea52-4c30-9f5e-7852979d4f29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380291431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.380291431 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.2484409105 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 236979699041 ps |
| CPU time | 679.33 seconds |
| Started | Jan 03 12:34:10 PM PST 24 |
| Finished | Jan 03 12:46:48 PM PST 24 |
| Peak memory | 191020 kb |
| Host | smart-6149b07a-71e9-42d8-abfe-c85b5d4910a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484409105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2484409105 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.862525309 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 75682003474 ps |
| CPU time | 272.3 seconds |
| Started | Jan 03 12:34:28 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-f1ddb485-be2e-424a-b982-0c2bcd3c50bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862525309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.862525309 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.216939761 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1002783535433 ps |
| CPU time | 849.95 seconds |
| Started | Jan 03 12:33:59 PM PST 24 |
| Finished | Jan 03 12:49:43 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-13a7ae70-f945-48d9-a7e1-9a22a6ba40cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216939761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.216939761 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.1292865483 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 507341918334 ps |
| CPU time | 291.02 seconds |
| Started | Jan 03 12:33:58 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 191124 kb |
| Host | smart-0560d00c-1d6c-4269-a02c-bb0d7426ccd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292865483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1292865483 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.2194368557 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 221967156755 ps |
| CPU time | 457.45 seconds |
| Started | Jan 03 12:34:29 PM PST 24 |
| Finished | Jan 03 12:43:26 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-9b50b622-fb8c-46c5-87df-7a962dcd9425 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194368557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2194368557 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.3919732891 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2111404750 ps |
| CPU time | 5.5 seconds |
| Started | Jan 03 12:34:33 PM PST 24 |
| Finished | Jan 03 12:35:47 PM PST 24 |
| Peak memory | 182792 kb |
| Host | smart-e8dbbe4c-66fe-4778-abce-65d2b0783adf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919732891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3919732891 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.1082186829 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 99179045496 ps |
| CPU time | 68.72 seconds |
| Started | Jan 03 12:34:00 PM PST 24 |
| Finished | Jan 03 12:36:45 PM PST 24 |
| Peak memory | 191000 kb |
| Host | smart-2d3a42f1-9c90-42b2-bde9-2dd983303a60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082186829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1082186829 |
| Directory | /workspace/99.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |