Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
107994402 |
1 |
|
T2 |
58 |
|
T6 |
56 |
|
T8 |
1 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54181193 |
1 |
|
T2 |
33 |
|
T6 |
17 |
|
T8 |
1 |
auto[1] |
53813209 |
1 |
|
T2 |
25 |
|
T6 |
39 |
|
T16 |
12 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
107987228 |
1 |
|
T2 |
4 |
|
T6 |
29 |
|
T8 |
1 |
auto[1] |
7174 |
1 |
|
T2 |
54 |
|
T6 |
27 |
|
T16 |
1 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
54177563 |
1 |
|
T2 |
4 |
|
T6 |
6 |
|
T8 |
1 |
all_values[0] |
auto[0] |
auto[1] |
3630 |
1 |
|
T2 |
29 |
|
T6 |
11 |
|
T47 |
5 |
all_values[0] |
auto[1] |
auto[0] |
53809665 |
1 |
|
T6 |
23 |
|
T16 |
11 |
|
T47 |
19 |
all_values[0] |
auto[1] |
auto[1] |
3544 |
1 |
|
T2 |
25 |
|
T6 |
16 |
|
T16 |
1 |