Unified Coverage Report :: Group : rv_timer_env_pkg::rv_timer_cfg_cov_obj::timer_cfg

Summary for Variable cp_mtime

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	50	0	50	100.00

Automatically Generated Bins for cp_mtime

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0000000000000000:051eb851eb851eb7]	22	1	T11	1	T12	1	T13	1
auto[051eb851eb851eb8:0a3d70a3d70a3d6f]	18	1	T11	3	T22	1	T94	1
auto[0a3d70a3d70a3d70:0f5c28f5c28f5c27]	21	1	T13	1	T19	1	T95	1
auto[0f5c28f5c28f5c28:147ae147ae147adf]	16	1	T13	1	T96	1	T95	1
auto[147ae147ae147ae0:1999999999999997]	12	1	T97	1	T98	1	T79	1
auto[1999999999999998:1eb851eb851eb84f]	22	1	T99	1	T100	1	T101	1
auto[1eb851eb851eb850:23d70a3d70a3d707]	14	1	T23	1	T102	1	T101	1
auto[23d70a3d70a3d708:28f5c28f5c28f5bf]	17	1	T21	1	T103	1	T104	1
auto[28f5c28f5c28f5c0:2e147ae147ae1477]	24	1	T19	1	T23	1	T105	1
auto[2e147ae147ae1478:333333333333332f]	16	1	T90	1	T106	1	T107	1
auto[3333333333333330:3851eb851eb851e7]	21	1	T11	1	T19	1	T108	1
auto[3851eb851eb851e8:3d70a3d70a3d709f]	15	1	T13	1	T109	1	T110	1
auto[3d70a3d70a3d70a0:428f5c28f5c28f57]	22	1	T104	1	T111	1	T101	1
auto[428f5c28f5c28f58:47ae147ae147ae0f]	13	1	T112	1	T113	1	T114	1
auto[47ae147ae147ae10:4cccccccccccccc7]	20	1	T105	1	T111	1	T99	1
auto[4cccccccccccccc8:51eb851eb851eb7f]	22	1	T17	1	T21	1	T111	1
auto[51eb851eb851eb80:570a3d70a3d70a37]	19	1	T21	1	T108	1	T90	1
auto[570a3d70a3d70a38:5c28f5c28f5c28ef]	15	1	T96	1	T115	1	T98	1
auto[5c28f5c28f5c28f0:6147ae147ae147a7]	20	1	T18	1	T103	1	T116	1
auto[6147ae147ae147a8:666666666666665f]	27	1	T11	1	T117	1	T118	1
auto[6666666666666660:6b851eb851eb8517]	22	1	T11	1	T103	1	T119	1
auto[6b851eb851eb8518:70a3d70a3d70a3cf]	31	1	T11	2	T108	1	T102	1
auto[70a3d70a3d70a3d0:75c28f5c28f5c287]	19	1	T108	1	T111	1	T99	1
auto[75c28f5c28f5c288:7ae147ae147ae13f]	27	1	T11	2	T22	1	T102	1
auto[7ae147ae147ae140:7ffffffffffffff7]	16	1	T11	2	T120	1	T121	1
auto[7ffffffffffffff8:851eb851eb851eaf]	13	1	T11	1	T13	1	T109	1
auto[851eb851eb851eb0:8a3d70a3d70a3d67]	21	1	T12	1	T19	1	T101	1
auto[8a3d70a3d70a3d68:8f5c28f5c28f5c1f]	23	1	T122	1	T102	1	T111	1
auto[8f5c28f5c28f5c20:947ae147ae147ad7]	20	1	T123	1	T124	1	T121	1
auto[947ae147ae147ad8:999999999999998f]	21	1	T12	1	T13	1	T101	1
auto[9999999999999990:9eb851eb851eb847]	19	1	T11	1	T123	1	T125	1
auto[9eb851eb851eb848:a3d70a3d70a3d6ff]	22	1	T109	1	T126	2	T127	1
auto[a3d70a3d70a3d700:a8f5c28f5c28f5b7]	19	1	T11	1	T117	1	T109	1
auto[a8f5c28f5c28f5b8:ae147ae147ae146f]	18	1	T105	1	T102	1	T96	1
auto[ae147ae147ae1470:b333333333333327]	13	1	T102	1	T110	1	T128	1
auto[b333333333333328:b851eb851eb851df]	17	1	T97	1	T96	1	T125	1
auto[b851eb851eb851e0:bd70a3d70a3d7097]	22	1	T11	1	T111	1	T98	2
auto[bd70a3d70a3d7098:c28f5c28f5c28f4f]	20	1	T122	1	T123	1	T117	1
auto[c28f5c28f5c28f50:c7ae147ae147ae07]	17	1	T11	1	T12	1	T122	1
auto[c7ae147ae147ae08:ccccccccccccccbf]	23	1	T11	1	T108	1	T123	1
auto[ccccccccccccccc0:d1eb851eb851eb77]	19	1	T23	1	T129	1	T130	1
auto[d1eb851eb851eb78:d70a3d70a3d70a2f]	18	1	T11	1	T131	1	T132	1
auto[d70a3d70a3d70a30:dc28f5c28f5c28e7]	15	1	T19	1	T99	1	T133	1
auto[dc28f5c28f5c28e8:e147ae147ae1479f]	23	1	T99	1	T107	1	T78	1
auto[e147ae147ae147a0:e666666666666657]	20	1	T22	1	T97	1	T98	1
auto[e666666666666658:eb851eb851eb850f]	20	1	T19	1	T96	1	T95	1
auto[eb851eb851eb8510:f0a3d70a3d70a3c7]	14	1	T11	2	T119	1	T102	1
auto[f0a3d70a3d70a3c8:f5c28f5c28f5c27f]	16	1	T95	1	T134	1	T120	1
auto[f5c28f5c28f5c280:fae147ae147ae137]	24	1	T108	1	T119	1	T102	1
auto[fae147ae147ae138:ffffffffffffffff]	20	1	T119	1	T135	1	T98	1

Summary for Variable cp_mtime_cmp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	50	0	50	100.00

Automatically Generated Bins for cp_mtime_cmp

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0000000000000000:051eb851eb851eb7]	22	1	T11	1	T12	1	T13	1
auto[051eb851eb851eb8:0a3d70a3d70a3d6f]	18	1	T11	3	T22	1	T94	1
auto[0a3d70a3d70a3d70:0f5c28f5c28f5c27]	21	1	T13	1	T19	1	T95	1
auto[0f5c28f5c28f5c28:147ae147ae147adf]	16	1	T13	1	T96	1	T95	1
auto[147ae147ae147ae0:1999999999999997]	12	1	T97	1	T98	1	T79	1
auto[1999999999999998:1eb851eb851eb84f]	22	1	T99	1	T100	1	T101	1
auto[1eb851eb851eb850:23d70a3d70a3d707]	14	1	T23	1	T102	1	T101	1
auto[23d70a3d70a3d708:28f5c28f5c28f5bf]	17	1	T21	1	T103	1	T104	1
auto[28f5c28f5c28f5c0:2e147ae147ae1477]	24	1	T19	1	T23	1	T105	1
auto[2e147ae147ae1478:333333333333332f]	16	1	T90	1	T106	1	T107	1
auto[3333333333333330:3851eb851eb851e7]	21	1	T11	1	T19	1	T108	1
auto[3851eb851eb851e8:3d70a3d70a3d709f]	15	1	T13	1	T109	1	T110	1
auto[3d70a3d70a3d70a0:428f5c28f5c28f57]	22	1	T104	1	T111	1	T101	1
auto[428f5c28f5c28f58:47ae147ae147ae0f]	13	1	T112	1	T113	1	T114	1
auto[47ae147ae147ae10:4cccccccccccccc7]	20	1	T105	1	T111	1	T99	1
auto[4cccccccccccccc8:51eb851eb851eb7f]	22	1	T17	1	T21	1	T111	1
auto[51eb851eb851eb80:570a3d70a3d70a37]	19	1	T21	1	T108	1	T90	1
auto[570a3d70a3d70a38:5c28f5c28f5c28ef]	15	1	T96	1	T115	1	T98	1
auto[5c28f5c28f5c28f0:6147ae147ae147a7]	20	1	T18	1	T103	1	T116	1
auto[6147ae147ae147a8:666666666666665f]	27	1	T11	1	T117	1	T118	1
auto[6666666666666660:6b851eb851eb8517]	22	1	T11	1	T103	1	T119	1
auto[6b851eb851eb8518:70a3d70a3d70a3cf]	31	1	T11	2	T108	1	T102	1
auto[70a3d70a3d70a3d0:75c28f5c28f5c287]	19	1	T108	1	T111	1	T99	1
auto[75c28f5c28f5c288:7ae147ae147ae13f]	27	1	T11	2	T22	1	T102	1
auto[7ae147ae147ae140:7ffffffffffffff7]	16	1	T11	2	T120	1	T121	1
auto[7ffffffffffffff8:851eb851eb851eaf]	13	1	T11	1	T13	1	T109	1
auto[851eb851eb851eb0:8a3d70a3d70a3d67]	21	1	T12	1	T19	1	T101	1
auto[8a3d70a3d70a3d68:8f5c28f5c28f5c1f]	23	1	T122	1	T102	1	T111	1
auto[8f5c28f5c28f5c20:947ae147ae147ad7]	20	1	T123	1	T124	1	T121	1
auto[947ae147ae147ad8:999999999999998f]	21	1	T12	1	T13	1	T101	1
auto[9999999999999990:9eb851eb851eb847]	19	1	T11	1	T123	1	T125	1
auto[9eb851eb851eb848:a3d70a3d70a3d6ff]	22	1	T109	1	T126	2	T127	1
auto[a3d70a3d70a3d700:a8f5c28f5c28f5b7]	19	1	T11	1	T117	1	T109	1
auto[a8f5c28f5c28f5b8:ae147ae147ae146f]	18	1	T105	1	T102	1	T96	1
auto[ae147ae147ae1470:b333333333333327]	13	1	T102	1	T110	1	T128	1
auto[b333333333333328:b851eb851eb851df]	17	1	T97	1	T96	1	T125	1
auto[b851eb851eb851e0:bd70a3d70a3d7097]	22	1	T11	1	T111	1	T98	2
auto[bd70a3d70a3d7098:c28f5c28f5c28f4f]	20	1	T122	1	T123	1	T117	1
auto[c28f5c28f5c28f50:c7ae147ae147ae07]	17	1	T11	1	T12	1	T122	1
auto[c7ae147ae147ae08:ccccccccccccccbf]	23	1	T11	1	T108	1	T123	1
auto[ccccccccccccccc0:d1eb851eb851eb77]	19	1	T23	1	T129	1	T130	1
auto[d1eb851eb851eb78:d70a3d70a3d70a2f]	18	1	T11	1	T131	1	T132	1
auto[d70a3d70a3d70a30:dc28f5c28f5c28e7]	15	1	T19	1	T99	1	T133	1
auto[dc28f5c28f5c28e8:e147ae147ae1479f]	23	1	T99	1	T107	1	T78	1
auto[e147ae147ae147a0:e666666666666657]	20	1	T22	1	T97	1	T98	1
auto[e666666666666658:eb851eb851eb850f]	20	1	T19	1	T96	1	T95	1
auto[eb851eb851eb8510:f0a3d70a3d70a3c7]	14	1	T11	2	T119	1	T102	1
auto[f0a3d70a3d70a3c8:f5c28f5c28f5c27f]	16	1	T95	1	T134	1	T120	1
auto[f5c28f5c28f5c280:fae147ae147ae137]	24	1	T108	1	T119	1	T102	1
auto[fae147ae147ae138:ffffffffffffffff]	20	1	T119	1	T135	1	T98	1

Summary for Variable cp_prescale

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	256	4	252	98.44

Automatically Generated Bins for cp_prescale

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[864:879]]	0	1	1
[auto[2016:2031]]	0	1	1
[auto[3328:3343]]	0	1	1
[auto[3920:3935]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:15]	7	1	T114	1	T136	1	T137	1
auto[16:31]	8	1	T12	1	T132	1	T138	1
auto[32:47]	3	1	T131	1	T139	1	T140	1
auto[48:63]	11	1	T123	1	T98	1	T141	1
auto[64:79]	2	1	T101	1	T142	1	-	-
auto[80:95]	3	1	T102	1	T143	1	T144	1
auto[96:111]	6	1	T105	1	T114	1	T145	1
auto[112:127]	3	1	T11	1	T146	1	T147	1
auto[128:143]	1	1	T148	1	-	-	-	-
auto[144:159]	5	1	T117	1	T149	1	T150	1
auto[160:175]	4	1	T11	1	T151	1	T152	1
auto[176:191]	4	1	T153	1	T154	1	T155	1
auto[192:207]	5	1	T11	1	T13	1	T156	1
auto[208:223]	7	1	T125	1	T95	1	T157	1
auto[224:239]	2	1	T138	1	T141	1	-	-
auto[240:255]	4	1	T21	1	T96	1	T158	1
auto[256:271]	4	1	T159	1	T160	1	T161	1
auto[272:287]	5	1	T162	1	T163	1	T126	1
auto[288:303]	4	1	T94	1	T164	1	T165	1
auto[304:319]	1	1	T135	1	-	-	-	-
auto[320:335]	4	1	T100	1	T166	2	T167	1
auto[336:351]	2	1	T168	1	T169	1	-	-
auto[352:367]	2	1	T113	1	T170	1	-	-
auto[368:383]	3	1	T171	1	T167	1	T172	1
auto[384:399]	2	1	T173	1	T166	1	-	-
auto[400:415]	3	1	T174	1	T98	1	T175	1
auto[416:431]	6	1	T11	1	T13	1	T176	1
auto[432:447]	6	1	T121	1	T177	1	T178	1
auto[448:463]	5	1	T179	1	T180	1	T181	1
auto[464:479]	2	1	T123	1	T124	1	-	-
auto[480:495]	4	1	T11	1	T120	1	T182	1
auto[496:511]	4	1	T108	1	T183	1	T184	1
auto[512:527]	4	1	T121	1	T143	1	T185	1
auto[528:543]	3	1	T120	1	T155	1	T186	1
auto[544:559]	1	1	T96	1	-	-	-	-
auto[560:575]	7	1	T13	1	T157	1	T165	1
auto[576:591]	5	1	T13	1	T102	1	T187	1
auto[592:607]	3	1	T99	1	T94	1	T188	1
auto[608:623]	5	1	T23	1	T141	1	T189	1
auto[624:639]	4	1	T190	1	T153	1	T191	1
auto[640:655]	5	1	T104	1	T143	1	T192	1
auto[656:671]	4	1	T134	1	T193	1	T194	1
auto[672:687]	7	1	T12	1	T195	1	T78	1
auto[688:703]	4	1	T95	1	T121	1	T148	1
auto[704:719]	2	1	T107	1	T157	1	-	-
auto[720:735]	6	1	T196	1	T197	1	T198	1
auto[736:751]	4	1	T173	1	T199	1	T200	1
auto[752:767]	2	1	T201	1	T167	1	-	-
auto[768:783]	2	1	T114	1	T202	1	-	-
auto[784:799]	2	1	T167	1	T143	1	-	-
auto[800:815]	5	1	T95	1	T202	1	T144	1
auto[816:831]	2	1	T177	1	T203	1	-	-
auto[832:847]	4	1	T113	1	T127	1	T204	1
auto[848:863]	5	1	T128	1	T205	1	T206	1
auto[880:895]	8	1	T12	1	T207	1	T184	2
auto[896:911]	4	1	T115	1	T208	1	T126	1
auto[912:927]	2	1	T120	1	T190	1	-	-
auto[928:943]	7	1	T111	1	T109	1	T209	1
auto[944:959]	5	1	T210	1	T211	1	T212	1
auto[960:975]	5	1	T142	1	T189	1	T213	1
auto[976:991]	7	1	T173	1	T214	1	T215	1
auto[992:1007]	4	1	T96	1	T216	1	T217	1
auto[1008:1023]	6	1	T111	1	T218	1	T158	1
auto[1024:1039]	4	1	T133	1	T219	1	T220	1
auto[1040:1055]	3	1	T119	1	T221	1	T222	1
auto[1056:1071]	2	1	T192	1	T185	1	-	-
auto[1072:1087]	1	1	T223	1	-	-	-	-
auto[1088:1103]	3	1	T145	1	T224	1	T225	1
auto[1104:1119]	7	1	T103	1	T33	1	T226	1
auto[1120:1135]	4	1	T227	1	T228	1	T181	1
auto[1136:1151]	5	1	T18	1	T229	1	T230	1
auto[1152:1167]	5	1	T11	1	T96	1	T145	1
auto[1168:1183]	5	1	T11	1	T107	1	T188	1
auto[1184:1199]	4	1	T12	1	T122	1	T187	1
auto[1200:1215]	3	1	T231	1	T224	1	T232	1
auto[1216:1231]	5	1	T19	1	T111	1	T135	1
auto[1232:1247]	1	1	T233	1	-	-	-	-
auto[1248:1263]	3	1	T113	1	T170	1	T154	1
auto[1264:1279]	2	1	T234	1	T235	1	-	-
auto[1280:1295]	2	1	T163	1	T236	1	-	-
auto[1296:1311]	3	1	T237	1	T238	1	T239	1
auto[1312:1327]	3	1	T11	1	T240	1	T241	1
auto[1328:1343]	4	1	T13	1	T109	1	T31	1
auto[1344:1359]	2	1	T145	1	T242	1	-	-
auto[1360:1375]	6	1	T102	1	T97	1	T96	1
auto[1376:1391]	6	1	T11	1	T90	1	T243	1
auto[1392:1407]	6	1	T163	1	T181	1	T190	1
auto[1408:1423]	4	1	T120	1	T226	1	T244	1
auto[1424:1439]	3	1	T245	1	T246	1	T247	1
auto[1440:1455]	4	1	T248	1	T189	1	T232	1
auto[1456:1471]	3	1	T13	1	T226	1	T172	1
auto[1472:1487]	2	1	T136	1	T249	1	-	-
auto[1488:1503]	5	1	T116	1	T130	1	T250	1
auto[1504:1519]	5	1	T97	1	T130	1	T218	1
auto[1520:1535]	4	1	T112	1	T183	1	T227	1
auto[1536:1551]	2	1	T150	1	T82	1	-	-
auto[1552:1567]	5	1	T130	1	T162	1	T196	1
auto[1568:1583]	6	1	T119	1	T228	1	T243	1
auto[1584:1599]	6	1	T105	1	T226	1	T199	1
auto[1600:1615]	1	1	T181	1	-	-	-	-
auto[1616:1631]	5	1	T107	1	T183	1	T146	1
auto[1632:1647]	1	1	T120	1	-	-	-	-
auto[1648:1663]	4	1	T98	1	T113	1	T251	1
auto[1664:1679]	3	1	T98	1	T188	2	-	-
auto[1680:1695]	4	1	T95	1	T132	1	T181	1
auto[1696:1711]	2	1	T252	1	T253	1	-	-
auto[1712:1727]	6	1	T98	1	T184	1	T196	1
auto[1728:1743]	1	1	T161	1	-	-	-	-
auto[1744:1759]	4	1	T102	1	T207	1	T254	1
auto[1760:1775]	4	1	T205	1	T255	1	T191	1
auto[1776:1791]	2	1	T256	1	T148	1	-	-
auto[1792:1807]	7	1	T11	1	T119	1	T157	1
auto[1808:1823]	1	1	T232	1	-	-	-	-
auto[1824:1839]	1	1	T257	1	-	-	-	-
auto[1840:1855]	5	1	T102	1	T157	1	T150	1
auto[1856:1871]	6	1	T19	1	T22	1	T90	1
auto[1872:1887]	3	1	T258	1	T162	1	T259	1
auto[1888:1903]	5	1	T11	1	T102	1	T117	1
auto[1904:1919]	2	1	T100	1	T202	1	-	-
auto[1920:1935]	3	1	T260	1	T261	1	T262	1
auto[1936:1951]	8	1	T123	1	T106	1	T110	1
auto[1952:1967]	5	1	T103	1	T263	1	T29	1
auto[1968:1983]	5	1	T227	1	T228	1	T264	1
auto[1984:1999]	6	1	T183	1	T110	1	T265	1
auto[2000:2015]	5	1	T96	1	T110	1	T266	1
auto[2032:2047]	2	1	T249	1	T220	1	-	-
auto[2048:2063]	3	1	T265	1	T224	1	T261	1
auto[2064:2079]	2	1	T138	1	T267	1	-	-
auto[2080:2095]	1	1	T108	1	-	-	-	-
auto[2096:2111]	6	1	T99	1	T196	1	T268	1
auto[2112:2127]	3	1	T179	1	T178	1	T269	1
auto[2128:2143]	2	1	T270	1	T81	1	-	-
auto[2144:2159]	4	1	T271	1	T178	1	T272	1
auto[2160:2175]	1	1	T175	1	-	-	-	-
auto[2176:2191]	3	1	T157	1	T273	1	T274	1
auto[2192:2207]	3	1	T11	1	T32	1	T182	1
auto[2208:2223]	5	1	T157	1	T121	1	T143	1
auto[2224:2239]	6	1	T104	1	T146	2	T275	1
auto[2240:2255]	3	1	T135	1	T228	1	T276	1
auto[2256:2271]	1	1	T277	1	-	-	-	-
auto[2272:2287]	2	1	T99	1	T190	1	-	-
auto[2288:2303]	1	1	T275	1	-	-	-	-
auto[2304:2319]	7	1	T105	1	T130	1	T278	1
auto[2320:2335]	4	1	T106	1	T279	1	T235	1
auto[2336:2351]	2	1	T280	1	T240	1	-	-
auto[2352:2367]	1	1	T281	1	-	-	-	-
auto[2368:2383]	5	1	T246	1	T282	1	T270	1
auto[2384:2399]	4	1	T249	1	T236	1	T283	1
auto[2400:2415]	3	1	T111	1	T205	1	T284	1
auto[2416:2431]	4	1	T98	1	T233	1	T254	1
auto[2432:2447]	2	1	T201	1	T225	1	-	-
auto[2448:2463]	2	1	T111	1	T145	1	-	-
auto[2464:2479]	7	1	T95	1	T243	1	T264	1
auto[2480:2495]	3	1	T33	1	T128	1	T285	1
auto[2496:2511]	3	1	T96	1	T198	1	T286	1
auto[2512:2527]	4	1	T102	1	T138	1	T250	1
auto[2528:2543]	6	1	T287	1	T288	1	T272	2
auto[2544:2559]	5	1	T157	1	T289	1	T198	1
auto[2560:2575]	4	1	T128	1	T138	1	T254	1
auto[2576:2591]	5	1	T108	1	T277	1	T254	1
auto[2592:2607]	3	1	T96	1	T98	1	T146	1
auto[2608:2623]	4	1	T101	1	T109	1	T255	1
auto[2624:2639]	4	1	T101	1	T290	1	T204	1
auto[2640:2655]	4	1	T111	1	T234	1	T158	1
auto[2656:2671]	2	1	T278	1	T261	1	-	-
auto[2672:2687]	3	1	T102	1	T218	1	T291	1
auto[2688:2703]	3	1	T23	1	T100	1	T114	1
auto[2704:2719]	7	1	T126	1	T292	1	T293	1
auto[2720:2735]	2	1	T246	1	T262	1	-	-
auto[2736:2751]	1	1	T287	1	-	-	-	-
auto[2752:2767]	4	1	T119	1	T111	1	T66	1
auto[2768:2783]	3	1	T122	1	T200	1	T294	1
auto[2784:2799]	2	1	T295	1	T224	1	-	-
auto[2800:2815]	1	1	T194	1	-	-	-	-
auto[2816:2831]	2	1	T233	1	T284	1	-	-
auto[2832:2847]	1	1	T156	1	-	-	-	-
auto[2848:2863]	1	1	T11	1	-	-	-	-
auto[2864:2879]	5	1	T228	1	T201	1	T237	1
auto[2880:2895]	2	1	T163	1	T296	1	-	-
auto[2896:2911]	9	1	T11	1	T297	1	T112	1
auto[2912:2927]	2	1	T19	1	T195	1	-	-
auto[2928:2943]	10	1	T11	1	T96	1	T166	1
auto[2944:2959]	3	1	T103	1	T165	1	T265	1
auto[2960:2975]	2	1	T247	1	T232	1	-	-
auto[2976:2991]	5	1	T22	1	T107	1	T263	1
auto[2992:3007]	1	1	T96	1	-	-	-	-
auto[3008:3023]	8	1	T11	1	T133	1	T157	1
auto[3024:3039]	5	1	T17	1	T183	1	T278	1
auto[3040:3055]	4	1	T108	1	T291	1	T298	1
auto[3056:3071]	2	1	T98	1	T208	1	-	-
auto[3072:3087]	6	1	T19	1	T90	1	T98	1
auto[3088:3103]	1	1	T102	1	-	-	-	-
auto[3104:3119]	9	1	T21	1	T157	1	T162	1
auto[3120:3135]	2	1	T141	1	T231	1	-	-
auto[3136:3151]	2	1	T101	1	T224	1	-	-
auto[3152:3167]	3	1	T200	1	T269	1	T143	1
auto[3168:3183]	7	1	T120	1	T299	1	T163	1
auto[3184:3199]	4	1	T264	1	T196	1	T300	1
auto[3200:3215]	4	1	T164	1	T182	1	T141	1
auto[3216:3231]	5	1	T178	1	T139	1	T273	1
auto[3232:3247]	1	1	T205	1	-	-	-	-
auto[3248:3263]	4	1	T301	1	T188	1	T266	1
auto[3264:3279]	4	1	T302	1	T224	1	T148	1
auto[3280:3295]	3	1	T123	1	T101	1	T241	1
auto[3296:3311]	5	1	T157	1	T114	1	T287	1
auto[3312:3327]	4	1	T182	1	T264	1	T141	1
auto[3344:3359]	3	1	T113	1	T234	1	T303	1
auto[3360:3375]	6	1	T96	1	T235	1	T304	1
auto[3376:3391]	3	1	T21	1	T107	1	T300	1
auto[3392:3407]	7	1	T11	1	T164	1	T226	1
auto[3408:3423]	5	1	T19	1	T162	1	T260	1
auto[3424:3439]	4	1	T200	1	T127	1	T159	1
auto[3440:3455]	8	1	T100	1	T113	1	T305	1
auto[3456:3471]	3	1	T22	1	T270	1	T306	1
auto[3472:3487]	2	1	T307	1	T154	1	-	-
auto[3488:3503]	3	1	T11	1	T235	1	T152	1
auto[3504:3519]	2	1	T263	1	T308	1	-	-
auto[3520:3535]	3	1	T183	1	T309	1	T154	1
auto[3536:3551]	2	1	T204	1	T232	1	-	-
auto[3552:3567]	4	1	T177	1	T205	1	T291	1
auto[3568:3583]	1	1	T155	1	-	-	-	-
auto[3584:3599]	3	1	T176	1	T202	1	T232	1
auto[3600:3615]	3	1	T11	1	T241	1	T155	1
auto[3616:3631]	7	1	T104	1	T118	1	T129	1
auto[3632:3647]	1	1	T200	1	-	-	-	-
auto[3648:3663]	3	1	T98	1	T183	1	T155	1
auto[3664:3679]	4	1	T149	1	T309	1	T294	1
auto[3680:3695]	7	1	T108	1	T111	1	T125	1
auto[3696:3711]	3	1	T310	1	T223	1	T192	1
auto[3712:3727]	4	1	T19	1	T125	1	T229	1
auto[3728:3743]	4	1	T11	1	T99	1	T80	1
auto[3744:3759]	2	1	T309	1	T224	1	-	-
auto[3760:3775]	2	1	T253	1	T311	1	-	-
auto[3776:3791]	4	1	T289	1	T312	1	T313	1
auto[3792:3807]	5	1	T182	1	T146	1	T143	1
auto[3808:3823]	3	1	T111	1	T101	1	T172	1
auto[3824:3839]	4	1	T314	1	T188	1	T155	1
auto[3840:3855]	8	1	T157	1	T315	1	T162	1
auto[3856:3871]	6	1	T98	1	T114	1	T299	1
auto[3872:3887]	1	1	T167	1	-	-	-	-
auto[3888:3903]	6	1	T11	1	T97	1	T126	1
auto[3904:3919]	5	1	T117	1	T279	1	T264	1
auto[3936:3951]	6	1	T111	1	T99	1	T157	1
auto[3952:3967]	4	1	T316	1	T180	1	T317	1
auto[3968:3983]	7	1	T23	1	T108	1	T79	1
auto[3984:3999]	4	1	T280	1	T163	1	T318	1
auto[4000:4015]	1	1	T95	1	-	-	-	-
auto[4016:4031]	3	1	T122	1	T273	1	T241	1
auto[4032:4047]	1	1	T155	1	-	-	-	-
auto[4048:4063]	4	1	T107	1	T145	1	T319	1
auto[4064:4079]	4	1	T11	1	T157	1	T138	1
auto[4080:4095]	2	1	T99	1	T232	1	-	-

Summary for Variable cp_step

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	255	7	248	97.25

User Defined Bins for cp_step

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
step_all_val[11]	0	1	1
step_all_val[30]	0	1	1
step_all_val[41]	0	1	1
step_all_val[65]	0	1	1
step_all_val[90]	0	1	1
step_all_val[135]	0	1	1
step_all_val[145]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
step_all_val[1]	5	1	T11	1	T113	1	T275	1
step_all_val[2]	3	1	T104	1	T167	1	T172	1
step_all_val[3]	2	1	T272	1	T155	1	-	-
step_all_val[4]	5	1	T183	1	T177	1	T178	1
step_all_val[5]	3	1	T98	1	T120	1	T244	1
step_all_val[6]	6	1	T200	1	T204	1	T320	1
step_all_val[7]	5	1	T314	1	T179	1	T201	1
step_all_val[8]	2	1	T107	1	T226	1	-	-
step_all_val[9]	5	1	T315	1	T282	1	T155	1
step_all_val[10]	4	1	T11	1	T235	1	T247	1
step_all_val[12]	5	1	T90	1	T279	1	T146	1
step_all_val[13]	4	1	T195	1	T100	1	T310	1
step_all_val[14]	4	1	T183	1	T157	1	T215	1
step_all_val[15]	5	1	T11	1	T12	1	T96	1
step_all_val[16]	1	1	T107	1	-	-	-	-
step_all_val[17]	7	1	T95	2	T227	1	T196	1
step_all_val[18]	5	1	T278	1	T226	1	T126	1
step_all_val[19]	3	1	T11	1	T130	1	T155	1
step_all_val[20]	3	1	T240	1	T154	1	T202	1
step_all_val[21]	7	1	T146	1	T126	1	T275	1
step_all_val[22]	3	1	T13	1	T188	1	T321	1
step_all_val[23]	3	1	T98	1	T268	1	T220	1
step_all_val[24]	5	1	T123	1	T125	1	T164	1
step_all_val[25]	2	1	T263	1	T127	1	-	-
step_all_val[26]	6	1	T19	1	T122	1	T105	1
step_all_val[27]	6	1	T108	1	T95	1	T224	1
step_all_val[28]	3	1	T22	1	T109	1	T178	1
step_all_val[29]	4	1	T102	1	T96	1	T201	1
step_all_val[31]	5	1	T13	1	T102	1	T111	1
step_all_val[32]	6	1	T96	1	T109	1	T193	1
step_all_val[33]	3	1	T135	1	T178	1	T166	1
step_all_val[34]	5	1	T114	1	T138	1	T194	1
step_all_val[35]	4	1	T102	1	T97	1	T212	1
step_all_val[36]	7	1	T94	1	T95	1	T182	2
step_all_val[37]	2	1	T96	1	T215	1	-	-
step_all_val[38]	1	1	T228	1	-	-	-	-
step_all_val[39]	1	1	T204	1	-	-	-	-
step_all_val[40]	3	1	T163	1	T190	1	T311	1
step_all_val[42]	5	1	T113	1	T163	1	T274	1
step_all_val[43]	6	1	T13	1	T19	1	T149	1
step_all_val[44]	3	1	T180	1	T231	1	T212	1
step_all_val[45]	5	1	T11	1	T129	1	T317	1
step_all_val[46]	3	1	T203	1	T235	1	T267	1
step_all_val[47]	3	1	T127	1	T155	1	T81	1
step_all_val[48]	6	1	T230	1	T289	1	T294	1
step_all_val[49]	4	1	T228	1	T266	1	T286	1
step_all_val[50]	3	1	T301	1	T273	1	T186	1
step_all_val[51]	5	1	T11	2	T111	1	T235	1
step_all_val[52]	4	1	T11	1	T246	1	T141	1
step_all_val[53]	6	1	T31	1	T114	1	T188	1
step_all_val[54]	3	1	T100	1	T322	1	T139	1
step_all_val[55]	3	1	T102	1	T141	1	T197	1
step_all_val[56]	5	1	T226	1	T150	1	T159	1
step_all_val[57]	5	1	T90	1	T116	1	T275	1
step_all_val[58]	3	1	T157	1	T323	1	T172	1
step_all_val[59]	4	1	T118	1	T100	1	T254	1
step_all_val[60]	2	1	T19	1	T122	1	-	-
step_all_val[61]	3	1	T176	1	T234	1	T259	1
step_all_val[62]	3	1	T206	1	T236	1	T191	1
step_all_val[63]	7	1	T173	1	T146	1	T188	1
step_all_val[64]	4	1	T126	1	T273	1	T298	1
step_all_val[66]	3	1	T117	1	T237	1	T224	1
step_all_val[67]	1	1	T324	1	-	-	-	-
step_all_val[68]	3	1	T11	1	T325	1	T249	1
step_all_val[69]	1	1	T277	1	-	-	-	-
step_all_val[70]	4	1	T187	1	T215	1	T186	1
step_all_val[71]	2	1	T130	1	T234	1	-	-
step_all_val[72]	4	1	T183	1	T205	1	T326	1
step_all_val[73]	7	1	T23	1	T119	1	T96	1
step_all_val[74]	5	1	T96	1	T157	1	T218	1
step_all_val[75]	3	1	T193	1	T231	1	T232	1
step_all_val[76]	4	1	T164	1	T29	1	T32	1
step_all_val[77]	5	1	T96	1	T100	1	T162	1
step_all_val[78]	4	1	T200	1	T184	1	T264	1
step_all_val[79]	2	1	T104	1	T232	1	-	-
step_all_val[80]	6	1	T11	1	T125	1	T290	1
step_all_val[81]	3	1	T11	1	T106	1	T139	1
step_all_val[82]	1	1	T254	1	-	-	-	-
step_all_val[83]	5	1	T188	1	T231	1	T143	1
step_all_val[84]	3	1	T125	1	T181	1	T304	1
step_all_val[85]	7	1	T103	1	T120	1	T149	1
step_all_val[86]	1	1	T108	1	-	-	-	-
step_all_val[87]	4	1	T173	1	T121	1	T177	1
step_all_val[88]	8	1	T11	1	T135	1	T208	1
step_all_val[89]	3	1	T143	1	T307	1	T140	1
step_all_val[91]	5	1	T11	1	T12	1	T156	1
step_all_val[92]	6	1	T105	1	T101	1	T150	1
step_all_val[93]	4	1	T97	1	T136	1	T268	1
step_all_val[94]	1	1	T105	1	-	-	-	-
step_all_val[95]	3	1	T117	1	T157	1	T190	1
step_all_val[96]	4	1	T199	1	T264	1	T179	1
step_all_val[97]	5	1	T145	1	T265	1	T190	1
step_all_val[98]	6	1	T276	1	T255	1	T198	1
step_all_val[99]	2	1	T13	1	T141	1	-	-
step_all_val[100]	3	1	T134	1	T217	1	T220	1
step_all_val[101]	3	1	T270	1	T327	1	T242	1
step_all_val[102]	6	1	T11	1	T12	1	T121	1
step_all_val[103]	7	1	T177	1	T184	1	T260	1
step_all_val[104]	4	1	T19	1	T101	1	T98	1
step_all_val[105]	6	1	T19	1	T103	1	T102	1
step_all_val[106]	5	1	T173	1	T181	1	T219	1
step_all_val[107]	1	1	T328	1	-	-	-	-
step_all_val[108]	3	1	T11	1	T152	1	T175	1
step_all_val[109]	3	1	T329	1	T147	1	T306	1
step_all_val[110]	6	1	T157	1	T145	1	T300	1
step_all_val[111]	5	1	T103	1	T157	1	T165	1
step_all_val[112]	4	1	T111	1	T184	1	T178	1
step_all_val[113]	3	1	T319	1	T141	1	T212	1
step_all_val[114]	7	1	T210	1	T29	1	T110	1
step_all_val[115]	3	1	T133	1	T145	1	T225	1
step_all_val[116]	2	1	T178	1	T302	1	-	-
step_all_val[117]	3	1	T246	1	T224	1	T155	1
step_all_val[118]	6	1	T97	1	T318	1	T330	1
step_all_val[119]	2	1	T218	1	T232	1	-	-
step_all_val[120]	5	1	T114	1	T265	1	T259	1
step_all_val[121]	3	1	T211	1	T144	1	T232	1
step_all_val[122]	2	1	T98	1	T170	1	-	-
step_all_val[123]	2	1	T117	1	T217	1	-	-
step_all_val[124]	2	1	T98	1	T121	1	-	-
step_all_val[125]	6	1	T99	1	T132	1	T98	1
step_all_val[126]	7	1	T13	1	T99	1	T107	1
step_all_val[127]	2	1	T113	1	T193	1	-	-
step_all_val[128]	4	1	T183	1	T250	1	T150	1
step_all_val[129]	7	1	T13	1	T123	1	T243	1
step_all_val[130]	5	1	T115	1	T114	1	T314	1
step_all_val[131]	4	1	T111	1	T174	1	T147	1
step_all_val[132]	4	1	T11	1	T278	1	T280	1
step_all_val[133]	2	1	T159	1	T166	1	-	-
step_all_val[134]	2	1	T161	1	T232	1	-	-
step_all_val[136]	4	1	T331	1	T332	1	T272	1
step_all_val[137]	2	1	T101	1	T181	1	-	-
step_all_val[138]	5	1	T12	1	T114	1	T165	1
step_all_val[139]	2	1	T112	1	T190	1	-	-
step_all_val[140]	6	1	T156	1	T170	1	T153	1
step_all_val[141]	3	1	T304	1	T155	1	T148	1
step_all_val[142]	3	1	T248	1	T142	1	T255	1
step_all_val[143]	3	1	T111	1	T132	1	T180	1
step_all_val[144]	1	1	T305	1	-	-	-	-
step_all_val[146]	5	1	T11	1	T22	1	T198	1
step_all_val[147]	3	1	T23	1	T183	1	T223	1
step_all_val[148]	2	1	T110	1	T148	1	-	-
step_all_val[149]	1	1	T130	1	-	-	-	-
step_all_val[150]	5	1	T96	1	T113	1	T157	1
step_all_val[151]	5	1	T98	1	T145	1	T223	1
step_all_val[152]	1	1	T327	1	-	-	-	-
step_all_val[153]	1	1	T111	1	-	-	-	-
step_all_val[154]	6	1	T107	1	T98	1	T183	1
step_all_val[155]	7	1	T11	1	T102	1	T96	1
step_all_val[156]	3	1	T79	1	T138	1	T168	1
step_all_val[157]	2	1	T263	1	T232	1	-	-
step_all_val[158]	2	1	T309	1	T147	1	-	-
step_all_val[159]	1	1	T111	1	-	-	-	-
step_all_val[160]	7	1	T102	1	T182	1	T121	1
step_all_val[161]	3	1	T163	1	T260	1	T294	1
step_all_val[162]	5	1	T21	1	T278	1	T205	1
step_all_val[163]	4	1	T157	1	T188	1	T179	1
step_all_val[164]	3	1	T133	1	T120	1	T302	1
step_all_val[165]	6	1	T113	1	T157	1	T266	1
step_all_val[166]	1	1	T286	1	-	-	-	-
step_all_val[167]	4	1	T112	1	T254	1	T318	1
step_all_val[168]	4	1	T229	1	T142	1	T166	1
step_all_val[169]	3	1	T297	1	T229	1	T206	1
step_all_val[170]	4	1	T99	1	T235	1	T161	1
step_all_val[171]	1	1	T205	1	-	-	-	-
step_all_val[172]	4	1	T249	1	T333	1	T204	1
step_all_val[173]	4	1	T11	1	T101	1	T114	1
step_all_val[174]	3	1	T209	1	T324	1	T225	1
step_all_val[175]	3	1	T228	1	T189	1	T257	1
step_all_val[176]	1	1	T119	1	-	-	-	-
step_all_val[177]	4	1	T243	1	T163	1	T212	1
step_all_val[178]	2	1	T113	1	T189	1	-	-
step_all_val[179]	2	1	T95	1	T327	1	-	-
step_all_val[180]	5	1	T184	1	T126	1	T191	1
step_all_val[181]	6	1	T90	1	T109	1	T182	1
step_all_val[182]	4	1	T243	1	T265	1	T167	1
step_all_val[183]	2	1	T177	1	T184	1	-	-
step_all_val[184]	3	1	T102	1	T316	1	T140	1
step_all_val[185]	2	1	T95	1	T189	1	-	-
step_all_val[186]	2	1	T226	1	T152	1	-	-
step_all_val[187]	2	1	T207	1	T242	1	-	-
step_all_val[188]	4	1	T17	1	T291	1	T288	1
step_all_val[189]	6	1	T196	1	T166	1	T281	1
step_all_val[190]	6	1	T145	1	T188	1	T138	1
step_all_val[191]	3	1	T182	1	T271	1	T273	1
step_all_val[192]	2	1	T277	1	T188	1	-	-
step_all_val[193]	4	1	T19	1	T99	1	T233	1
step_all_val[194]	4	1	T94	1	T263	1	T291	1
step_all_val[195]	4	1	T135	1	T264	1	T244	1
step_all_val[196]	2	1	T126	1	T296	1	-	-
step_all_val[197]	5	1	T102	1	T195	1	T280	1
step_all_val[198]	4	1	T107	1	T252	1	T334	1
step_all_val[199]	5	1	T123	1	T190	1	T141	1
step_all_val[200]	8	1	T108	1	T138	1	T150	1
step_all_val[201]	4	1	T290	1	T162	1	T238	1
step_all_val[202]	7	1	T233	1	T159	1	T158	1
step_all_val[203]	4	1	T96	1	T305	1	T252	1
step_all_val[204]	4	1	T188	1	T246	1	T191	1
step_all_val[205]	11	1	T109	1	T110	1	T299	1
step_all_val[206]	3	1	T183	1	T292	1	T212	1
step_all_val[207]	2	1	T264	1	T141	1	-	-
step_all_val[208]	5	1	T108	1	T104	1	T66	1
step_all_val[209]	3	1	T299	1	T245	1	T304	1
step_all_val[210]	5	1	T164	1	T309	1	T191	1
step_all_val[211]	2	1	T95	1	T143	1	-	-
step_all_val[212]	3	1	T11	1	T106	1	T83	1
step_all_val[213]	1	1	T298	1	-	-	-	-
step_all_val[214]	3	1	T196	1	T224	1	T191	1
step_all_val[215]	4	1	T146	1	T287	1	T158	1
step_all_val[216]	6	1	T101	1	T157	1	T269	2
step_all_val[217]	2	1	T271	1	T192	1	-	-
step_all_val[218]	3	1	T143	1	T335	1	T232	1
step_all_val[219]	5	1	T243	1	T214	1	T218	1
step_all_val[220]	3	1	T18	1	T162	1	T201	1
step_all_val[221]	4	1	T33	1	T128	1	T163	1
step_all_val[222]	5	1	T120	2	T227	1	T138	1
step_all_val[223]	3	1	T98	1	T181	1	T206	1
step_all_val[224]	5	1	T157	1	T188	1	T309	1
step_all_val[225]	3	1	T11	1	T107	1	T160	1
step_all_val[226]	6	1	T22	1	T120	1	T246	1
step_all_val[227]	2	1	T111	1	T282	1	-	-
step_all_val[228]	10	1	T98	1	T157	1	T279	1
step_all_val[229]	5	1	T196	1	T171	1	T218	1
step_all_val[230]	8	1	T21	1	T123	1	T131	1
step_all_val[231]	3	1	T78	1	T305	1	T140	1
step_all_val[232]	4	1	T139	1	T274	1	T253	1
step_all_val[233]	3	1	T11	1	T240	1	T262	1
step_all_val[234]	4	1	T200	1	T277	1	T194	1
step_all_val[235]	4	1	T108	1	T96	1	T99	1
step_all_val[236]	3	1	T199	1	T241	1	T237	1
step_all_val[237]	1	1	T163	1	-	-	-	-
step_all_val[238]	2	1	T99	1	T148	1	-	-
step_all_val[239]	3	1	T162	1	T188	1	T261	1
step_all_val[240]	5	1	T119	1	T226	1	T249	1
step_all_val[241]	3	1	T223	1	T322	1	T225	1
step_all_val[242]	4	1	T121	1	T167	1	T326	2
step_all_val[243]	6	1	T207	1	T228	1	T149	1
step_all_val[244]	2	1	T122	1	T276	1	-	-
step_all_val[245]	5	1	T227	1	T159	1	T336	1
step_all_val[246]	6	1	T21	1	T208	1	T124	1
step_all_val[247]	6	1	T23	1	T332	1	T241	1
step_all_val[248]	6	1	T108	1	T119	1	T285	1
step_all_val[249]	4	1	T200	1	T144	1	T186	1
step_all_val[250]	5	1	T111	1	T256	1	T234	1
step_all_val[251]	5	1	T258	1	T228	1	T197	1
step_all_val[252]	7	1	T162	1	T204	1	T231	1
step_all_val[253]	4	1	T146	1	T254	1	T167	1
step_all_val[254]	2	1	T111	1	T183	1	-	-
step_all_val[255]	4	1	T221	1	T212	1	T224	1