Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.48	99.36	98.73	100.00		100.00	100.00	98.75

Total test records in report: 504

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html

T501	/workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3766501840			Jan 07 12:52:19 PM PST 24	Jan 07 12:53:26 PM PST 24	21365138 ps
T502	/workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3477926403			Jan 07 12:52:39 PM PST 24	Jan 07 12:54:15 PM PST 24	337573389 ps
T503	/workspace/coverage/cover_reg_top/3.rv_timer_intr_test.192549813			Jan 07 12:52:45 PM PST 24	Jan 07 12:54:05 PM PST 24	11141976 ps
T504	/workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1162200351			Jan 07 12:52:37 PM PST 24	Jan 07 12:53:49 PM PST 24	28064504 ps

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3074241162
Short name	T3
Test name
Test status
Simulation time	753185348 ps
CPU time	2.58 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	191564 kb
Host	smart-426e486c-9e71-4d38-a840-4171653bb005
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074241162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.3074241162
Directory	/workspace/3.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/default/2.rv_timer_stress_all.4259161828
Short name	T11
Test name
Test status
Simulation time	1373644855907 ps
CPU time	2459.13 seconds
Started	Jan 07 12:39:05 PM PST 24
Finished	Jan 07 01:21:49 PM PST 24
Peak memory	191016 kb
Host	smart-92889960-15d7-4a2b-8891-d70a2a20c31e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259161828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 4259161828
Directory	/workspace/2.rv_timer_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.576025198
Short name	T41
Test name
Test status
Simulation time	249440518 ps
CPU time	2.2 seconds
Started	Jan 07 12:52:27 PM PST 24
Finished	Jan 07 12:53:35 PM PST 24
Peak memory	197972 kb
Host	smart-ec5ae3ba-7fc0-439e-929c-96fcaf8f0ead
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576025198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.576025198
Directory	/workspace/4.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2829190557
Short name	T53
Test name
Test status
Simulation time	237870800 ps
CPU time	1.36 seconds
Started	Jan 07 12:52:52 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	183448 kb
Host	smart-3e94aab5-5235-4289-97ad-af2a8a0a0ece
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829190557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.2829190557
Directory	/workspace/19.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/28.rv_timer_intr_test.606121292
Short name	T6
Test name
Test status
Simulation time	52302188 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:28 PM PST 24
Finished	Jan 07 12:53:51 PM PST 24
Peak memory	182912 kb
Host	smart-28480f82-8829-4992-a711-d1b0398743e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606121292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.606121292
Directory	/workspace/28.rv_timer_intr_test/latest

Test location	/workspace/coverage/default/44.rv_timer_stress_all.110492338
Short name	T98
Test name
Test status
Simulation time	1112234564578 ps
CPU time	1502.24 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 01:06:02 PM PST 24
Peak memory	191020 kb
Host	smart-636be40a-79b6-4abf-a081-1caad05a8dcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110492338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all. 110492338
Directory	/workspace/44.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/7.rv_timer_stress_all.181316992
Short name	T157
Test name
Test status
Simulation time	453828507789 ps
CPU time	2257.55 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 01:18:26 PM PST 24
Peak memory	191076 kb
Host	smart-f2779960-ca73-4378-a94d-8145f61e3164
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181316992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.181316992
Directory	/workspace/7.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/18.rv_timer_stress_all.344774711
Short name	T232
Test name
Test status
Simulation time	1127218972847 ps
CPU time	1983.15 seconds
Started	Jan 07 12:39:11 PM PST 24
Finished	Jan 07 01:13:30 PM PST 24
Peak memory	191128 kb
Host	smart-5b785091-e66d-47c9-8565-32032dcf833b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344774711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all. 344774711
Directory	/workspace/18.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2173405717
Short name	T78
Test name
Test status
Simulation time	106646601031 ps
CPU time	663.06 seconds
Started	Jan 07 12:39:14 PM PST 24
Finished	Jan 07 12:51:37 PM PST 24
Peak memory	205828 kb
Host	smart-5c9ca72d-9e76-46de-9985-351df03355be
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173405717 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2173405717
Directory	/workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.rv_timer_stress_all.355677212
Short name	T111
Test name
Test status
Simulation time	184309861520 ps
CPU time	1741.54 seconds
Started	Jan 07 12:39:35 PM PST 24
Finished	Jan 07 01:09:57 PM PST 24
Peak memory	191076 kb
Host	smart-557cb907-4ebf-42ac-b553-c02bbab18811
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355677212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 355677212
Directory	/workspace/45.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/20.rv_timer_stress_all.2794522890
Short name	T224
Test name
Test status
Simulation time	8258613737290 ps
CPU time	2124.02 seconds
Started	Jan 07 12:40:35 PM PST 24
Finished	Jan 07 01:17:07 PM PST 24
Peak memory	194700 kb
Host	smart-754127ab-da91-427f-a27c-a2c74d5752cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794522890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .2794522890
Directory	/workspace/20.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/23.rv_timer_stress_all.1114047212
Short name	T155
Test name
Test status
Simulation time	2427886283454 ps
CPU time	1956.68 seconds
Started	Jan 07 12:39:28 PM PST 24
Finished	Jan 07 01:13:30 PM PST 24
Peak memory	191100 kb
Host	smart-ae6ad71d-8023-4dcd-8789-037e29a099a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114047212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .1114047212
Directory	/workspace/23.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/10.rv_timer_stress_all.1587651517
Short name	T95
Test name
Test status
Simulation time	2791060882077 ps
CPU time	2125.93 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 01:15:58 PM PST 24
Peak memory	190996 kb
Host	smart-ed434af8-3674-405b-b219-2a0534c37246
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587651517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .1587651517
Directory	/workspace/10.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/19.rv_timer_stress_all.3370236210
Short name	T102
Test name
Test status
Simulation time	2916823997773 ps
CPU time	1081.37 seconds
Started	Jan 07 12:42:35 PM PST 24
Finished	Jan 07 01:01:58 PM PST 24
Peak memory	190628 kb
Host	smart-33eb375d-2b07-42c3-bf88-43f0ff4163a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370236210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all .3370236210
Directory	/workspace/19.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/0.rv_timer_sec_cm.2985392579
Short name	T24
Test name
Test status
Simulation time	319389352 ps
CPU time	0.87 seconds
Started	Jan 07 12:38:34 PM PST 24
Finished	Jan 07 12:40:14 PM PST 24
Peak memory	213892 kb
Host	smart-25b952b9-2dde-4674-b525-ae1624496267
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985392579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2985392579
Directory	/workspace/0.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/27.rv_timer_stress_all.4004918767
Short name	T188
Test name
Test status
Simulation time	513896005621 ps
CPU time	1498.76 seconds
Started	Jan 07 12:39:25 PM PST 24
Finished	Jan 07 01:05:49 PM PST 24
Peak memory	191056 kb
Host	smart-cbbed395-69ed-4eff-b23b-d61d01006dd2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004918767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .4004918767
Directory	/workspace/27.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/4.rv_timer_stress_all.2587060002
Short name	T163
Test name
Test status
Simulation time	1846537931238 ps
CPU time	757.42 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:54:34 PM PST 24
Peak memory	191116 kb
Host	smart-aa6b1d34-428b-48c4-ba31-de2f34c1aafe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587060002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 2587060002
Directory	/workspace/4.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/15.rv_timer_stress_all.2311029220
Short name	T200
Test name
Test status
Simulation time	387654833941 ps
CPU time	673.07 seconds
Started	Jan 07 12:39:11 PM PST 24
Finished	Jan 07 12:51:50 PM PST 24
Peak memory	191236 kb
Host	smart-f64b64cd-66a7-4610-8124-5398bce8e131
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311029220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .2311029220
Directory	/workspace/15.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/8.rv_timer_stress_all.1471602303
Short name	T183
Test name
Test status
Simulation time	527774066680 ps
CPU time	1416.75 seconds
Started	Jan 07 12:38:50 PM PST 24
Finished	Jan 07 01:03:57 PM PST 24
Peak memory	190888 kb
Host	smart-06ce02ff-b550-42e1-871f-5960246ce989
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471602303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 1471602303
Directory	/workspace/8.rv_timer_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3498977006
Short name	T70
Test name
Test status
Simulation time	102234505 ps
CPU time	0.74 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:21 PM PST 24
Peak memory	193668 kb
Host	smart-a42fc59c-18ad-4d2c-8de4-757dc1b785e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498977006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t imer_same_csr_outstanding.3498977006
Directory	/workspace/12.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/default/0.rv_timer_random.623495511
Short name	T167
Test name
Test status
Simulation time	457028253444 ps
CPU time	748.29 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:53:23 PM PST 24
Peak memory	191084 kb
Host	smart-d0594be0-9a2a-4e4d-9eae-60a4d02f17bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623495511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.623495511
Directory	/workspace/0.rv_timer_random/latest

Test location	/workspace/coverage/default/21.rv_timer_stress_all.1644040872
Short name	T191
Test name
Test status
Simulation time	2902004796690 ps
CPU time	2363.83 seconds
Started	Jan 07 12:38:41 PM PST 24
Finished	Jan 07 01:19:34 PM PST 24
Peak memory	190968 kb
Host	smart-4f3204c2-bfac-4926-8cf3-07f8bb83b8c1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644040872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .1644040872
Directory	/workspace/21.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/25.rv_timer_stress_all.4223700458
Short name	T141
Test name
Test status
Simulation time	1881299900462 ps
CPU time	954.54 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:56:21 PM PST 24
Peak memory	190880 kb
Host	smart-9779b693-6a69-4324-b05e-0f1802a96d0a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223700458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .4223700458
Directory	/workspace/25.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/181.rv_timer_random.4003607185
Short name	T228
Test name
Test status
Simulation time	314523244795 ps
CPU time	151.88 seconds
Started	Jan 07 12:40:00 PM PST 24
Finished	Jan 07 12:44:00 PM PST 24
Peak memory	191152 kb
Host	smart-0f368b54-1ec6-4743-bee8-29771e70fc82
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003607185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4003607185
Directory	/workspace/181.rv_timer_random/latest

Test location	/workspace/coverage/default/11.rv_timer_stress_all.2834491478
Short name	T225
Test name
Test status
Simulation time	440222885678 ps
CPU time	868.12 seconds
Started	Jan 07 12:39:00 PM PST 24
Finished	Jan 07 12:54:57 PM PST 24
Peak memory	190944 kb
Host	smart-7435cad5-1e99-4bf7-9ad5-c800b84011a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834491478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .2834491478
Directory	/workspace/11.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/9.rv_timer_stress_all.1833818186
Short name	T96
Test name
Test status
Simulation time	405843023938 ps
CPU time	1513.01 seconds
Started	Jan 07 12:42:41 PM PST 24
Finished	Jan 07 01:09:10 PM PST 24
Peak memory	190652 kb
Host	smart-4e6e4fa3-2924-4772-9bd7-ac5a9d633fc1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833818186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 1833818186
Directory	/workspace/9.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/109.rv_timer_random.1368584259
Short name	T270
Test name
Test status
Simulation time	113547858275 ps
CPU time	327.46 seconds
Started	Jan 07 12:39:32 PM PST 24
Finished	Jan 07 12:46:27 PM PST 24
Peak memory	191196 kb
Host	smart-79e878a2-9e52-4cc7-a2ff-efeb3d964124
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368584259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1368584259
Directory	/workspace/109.rv_timer_random/latest

Test location	/workspace/coverage/default/161.rv_timer_random.2983624901
Short name	T130
Test name
Test status
Simulation time	359552633380 ps
CPU time	242.99 seconds
Started	Jan 07 12:39:44 PM PST 24
Finished	Jan 07 12:45:31 PM PST 24
Peak memory	193696 kb
Host	smart-1d9c4548-2dba-4d5f-97f6-429e141d8726
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983624901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2983624901
Directory	/workspace/161.rv_timer_random/latest

Test location	/workspace/coverage/default/176.rv_timer_random.2943428976
Short name	T192
Test name
Test status
Simulation time	66206767209 ps
CPU time	324.06 seconds
Started	Jan 07 12:39:36 PM PST 24
Finished	Jan 07 12:46:30 PM PST 24
Peak memory	194304 kb
Host	smart-7a6b924f-e940-4a66-9ff2-7ee323cef9a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943428976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2943428976
Directory	/workspace/176.rv_timer_random/latest

Test location	/workspace/coverage/default/186.rv_timer_random.3603128061
Short name	T226
Test name
Test status
Simulation time	179806097516 ps
CPU time	280.65 seconds
Started	Jan 07 12:40:14 PM PST 24
Finished	Jan 07 12:46:20 PM PST 24
Peak memory	191016 kb
Host	smart-d4e2ed1d-5e97-42ca-a54b-cbe4228c5c86
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603128061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3603128061
Directory	/workspace/186.rv_timer_random/latest

Test location	/workspace/coverage/default/3.rv_timer_stress_all.3835195787
Short name	T148
Test name
Test status
Simulation time	294569876252 ps
CPU time	477.16 seconds
Started	Jan 07 12:40:53 PM PST 24
Finished	Jan 07 12:50:09 PM PST 24
Peak memory	190516 kb
Host	smart-67ac6dfe-f58f-4453-8dfc-7e909cf8b633
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835195787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 3835195787
Directory	/workspace/3.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/66.rv_timer_random.385967461
Short name	T19
Test name
Test status
Simulation time	1279332099168 ps
CPU time	3080.2 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 01:33:58 PM PST 24
Peak memory	191068 kb
Host	smart-f78d65ab-2647-4901-b6ad-02ef78e13349
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385967461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.385967461
Directory	/workspace/66.rv_timer_random/latest

Test location	/workspace/coverage/default/25.rv_timer_random.2259844536
Short name	T101
Test name
Test status
Simulation time	768982897201 ps
CPU time	772.56 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:53:43 PM PST 24
Peak memory	191040 kb
Host	smart-89eed619-b8f1-4303-8715-94e3c69a8032
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259844536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2259844536
Directory	/workspace/25.rv_timer_random/latest

Test location	/workspace/coverage/default/31.rv_timer_random.2944313829
Short name	T113
Test name
Test status
Simulation time	176013638311 ps
CPU time	284.45 seconds
Started	Jan 07 12:39:35 PM PST 24
Finished	Jan 07 12:45:59 PM PST 24
Peak memory	193536 kb
Host	smart-5ced91da-1685-4e66-b0a2-7d7f1de2aa1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944313829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2944313829
Directory	/workspace/31.rv_timer_random/latest

Test location	/workspace/coverage/default/120.rv_timer_random.2482631546
Short name	T159
Test name
Test status
Simulation time	150707774330 ps
CPU time	229.35 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:44:36 PM PST 24
Peak memory	191048 kb
Host	smart-b0a4a8e5-1705-4f56-9ee1-1ff9fdb20721
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482631546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2482631546
Directory	/workspace/120.rv_timer_random/latest

Test location	/workspace/coverage/default/24.rv_timer_stress_all.1409679788
Short name	T196
Test name
Test status
Simulation time	751035142699 ps
CPU time	717.66 seconds
Started	Jan 07 12:38:59 PM PST 24
Finished	Jan 07 12:52:17 PM PST 24
Peak memory	191020 kb
Host	smart-777a17ae-2513-4d2b-8ad4-f0c2655e88ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409679788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .1409679788
Directory	/workspace/24.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/31.rv_timer_stress_all.1452138581
Short name	T202
Test name
Test status
Simulation time	1994171140181 ps
CPU time	2995.77 seconds
Started	Jan 07 12:41:16 PM PST 24
Finished	Jan 07 01:32:49 PM PST 24
Peak memory	190564 kb
Host	smart-4509d434-485f-4427-b311-db8eed3d5e86
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452138581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .1452138581
Directory	/workspace/31.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/54.rv_timer_random.615308698
Short name	T307
Test name
Test status
Simulation time	46444195164 ps
CPU time	84.58 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:42:11 PM PST 24
Peak memory	191056 kb
Host	smart-9bd682dc-0120-4ab9-8083-db06a96d1144
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615308698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.615308698
Directory	/workspace/54.rv_timer_random/latest

Test location	/workspace/coverage/default/68.rv_timer_random.2865891068
Short name	T273
Test name
Test status
Simulation time	115410704059 ps
CPU time	501.84 seconds
Started	Jan 07 12:39:27 PM PST 24
Finished	Jan 07 12:49:13 PM PST 24
Peak memory	193776 kb
Host	smart-04b49b07-6a46-4f6f-b957-4891c51525c0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865891068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2865891068
Directory	/workspace/68.rv_timer_random/latest

Test location	/workspace/coverage/default/157.rv_timer_random.1555237657
Short name	T161
Test name
Test status
Simulation time	357940818850 ps
CPU time	273.02 seconds
Started	Jan 07 12:39:40 PM PST 24
Finished	Jan 07 12:46:00 PM PST 24
Peak memory	191100 kb
Host	smart-d989b542-1e5d-402f-bdd7-54f0e1eb3253
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555237657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1555237657
Directory	/workspace/157.rv_timer_random/latest

Test location	/workspace/coverage/default/167.rv_timer_random.3449837721
Short name	T261
Test name
Test status
Simulation time	2048355077269 ps
CPU time	603.71 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 12:51:16 PM PST 24
Peak memory	191068 kb
Host	smart-5eaec6ad-574b-40e5-a23f-39d1d51372e9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449837721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3449837721
Directory	/workspace/167.rv_timer_random/latest

Test location	/workspace/coverage/default/197.rv_timer_random.2930303684
Short name	T108
Test name
Test status
Simulation time	784153055461 ps
CPU time	779.91 seconds
Started	Jan 07 12:39:35 PM PST 24
Finished	Jan 07 12:53:58 PM PST 24
Peak memory	190996 kb
Host	smart-3b320616-7798-43aa-b9fc-5762ca43c874
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930303684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2930303684
Directory	/workspace/197.rv_timer_random/latest

Test location	/workspace/coverage/default/27.rv_timer_random.3025466484
Short name	T242
Test name
Test status
Simulation time	91444787567 ps
CPU time	399.49 seconds
Started	Jan 07 12:38:52 PM PST 24
Finished	Jan 07 12:46:50 PM PST 24
Peak memory	191120 kb
Host	smart-8b243458-6348-451f-b085-0efae7b5daf3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025466484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3025466484
Directory	/workspace/27.rv_timer_random/latest

Test location	/workspace/coverage/default/39.rv_timer_stress_all.588245177
Short name	T178
Test name
Test status
Simulation time	750138890425 ps
CPU time	774.74 seconds
Started	Jan 07 12:40:04 PM PST 24
Finished	Jan 07 12:54:16 PM PST 24
Peak memory	191148 kb
Host	smart-4764d4a2-4b00-41d7-bc7e-d073e5a2ac18
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588245177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all. 588245177
Directory	/workspace/39.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/55.rv_timer_random.1513774615
Short name	T139
Test name
Test status
Simulation time	220955519886 ps
CPU time	737.64 seconds
Started	Jan 07 12:39:22 PM PST 24
Finished	Jan 07 12:53:03 PM PST 24
Peak memory	193904 kb
Host	smart-32de0262-f829-4730-ba9f-8c342bb17d18
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513774615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1513774615
Directory	/workspace/55.rv_timer_random/latest

Test location	/workspace/coverage/default/61.rv_timer_random.2112939358
Short name	T263
Test name
Test status
Simulation time	67238798171 ps
CPU time	105.95 seconds
Started	Jan 07 12:40:16 PM PST 24
Finished	Jan 07 12:43:02 PM PST 24
Peak memory	191080 kb
Host	smart-e1270ddd-4d85-4a62-af43-d0d60b6763e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112939358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2112939358
Directory	/workspace/61.rv_timer_random/latest

Test location	/workspace/coverage/default/62.rv_timer_random.2475314984
Short name	T284
Test name
Test status
Simulation time	165109238106 ps
CPU time	304.89 seconds
Started	Jan 07 12:39:53 PM PST 24
Finished	Jan 07 12:46:19 PM PST 24
Peak memory	194208 kb
Host	smart-d62bb3e0-920f-4669-a212-a4fa605c7d63
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475314984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2475314984
Directory	/workspace/62.rv_timer_random/latest

Test location	/workspace/coverage/default/95.rv_timer_random.2719279560
Short name	T249
Test name
Test status
Simulation time	145751504677 ps
CPU time	62.56 seconds
Started	Jan 07 12:40:18 PM PST 24
Finished	Jan 07 12:42:21 PM PST 24
Peak memory	190320 kb
Host	smart-b9f142d3-f64a-4dc3-bf42-745fe9d3c41a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719279560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2719279560
Directory	/workspace/95.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2792857583
Short name	T68
Test name
Test status
Simulation time	124298243 ps
CPU time	1.52 seconds
Started	Jan 07 12:52:39 PM PST 24
Finished	Jan 07 12:54:14 PM PST 24
Peak memory	198056 kb
Host	smart-24a75f55-e194-4f84-a3d6-1dfe5c58fdb1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792857583 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2792857583
Directory	/workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/116.rv_timer_random.610826402
Short name	T165
Test name
Test status
Simulation time	66625625961 ps
CPU time	109.12 seconds
Started	Jan 07 12:39:43 PM PST 24
Finished	Jan 07 12:42:50 PM PST 24
Peak memory	193048 kb
Host	smart-ce9dffc2-ce06-4486-99f6-8dade0882e55
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610826402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.610826402
Directory	/workspace/116.rv_timer_random/latest

Test location	/workspace/coverage/default/121.rv_timer_random.3235166100
Short name	T235
Test name
Test status
Simulation time	295245630137 ps
CPU time	272.26 seconds
Started	Jan 07 12:40:07 PM PST 24
Finished	Jan 07 12:45:40 PM PST 24
Peak memory	194180 kb
Host	smart-ac455bf3-e637-4638-b12a-6267a5a10244
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235166100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3235166100
Directory	/workspace/121.rv_timer_random/latest

Test location	/workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3216700083
Short name	T18
Test name
Test status
Simulation time	184697488278 ps
CPU time	89.56 seconds
Started	Jan 07 12:38:54 PM PST 24
Finished	Jan 07 12:41:33 PM PST 24
Peak memory	182852 kb
Host	smart-b7f25e10-3ab2-4cd4-90e4-886335f817a2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216700083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3216700083
Directory	/workspace/3.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/33.rv_timer_stress_all.4147505077
Short name	T107
Test name
Test status
Simulation time	905394962409 ps
CPU time	939.72 seconds
Started	Jan 07 12:38:45 PM PST 24
Finished	Jan 07 12:56:10 PM PST 24
Peak memory	191116 kb
Host	smart-a74dfdee-b1d4-4e21-b13c-0bef224c1896
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147505077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .4147505077
Directory	/workspace/33.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/44.rv_timer_random.189647402
Short name	T237
Test name
Test status
Simulation time	543541418521 ps
CPU time	488.61 seconds
Started	Jan 07 12:39:37 PM PST 24
Finished	Jan 07 12:48:59 PM PST 24
Peak memory	191052 kb
Host	smart-ddcf7c37-e87d-422b-92f2-0b3172180901
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189647402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.189647402
Directory	/workspace/44.rv_timer_random/latest

Test location	/workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.4092048959
Short name	T177
Test name
Test status
Simulation time	94926388807 ps
CPU time	837.5 seconds
Started	Jan 07 12:39:28 PM PST 24
Finished	Jan 07 12:54:55 PM PST 24
Peak memory	211144 kb
Host	smart-7fefa95b-66a0-4e21-8d5e-90fdd96e49d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092048959 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.4092048959
Directory	/workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.rv_timer_random.1395063235
Short name	T120
Test name
Test status
Simulation time	186825218990 ps
CPU time	639.22 seconds
Started	Jan 07 12:39:13 PM PST 24
Finished	Jan 07 12:51:22 PM PST 24
Peak memory	190996 kb
Host	smart-826d0311-932e-47e3-9624-d1625934bac4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395063235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1395063235
Directory	/workspace/59.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2886176643
Short name	T75
Test name
Test status
Simulation time	37843046 ps
CPU time	0.78 seconds
Started	Jan 07 12:52:01 PM PST 24
Finished	Jan 07 12:53:39 PM PST 24
Peak memory	192788 kb
Host	smart-c65ece82-81b9-4081-a8e0-5bb09c8c8d95
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886176643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.2886176643
Directory	/workspace/0.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/default/1.rv_timer_stress_all.927903617
Short name	T117
Test name
Test status
Simulation time	366727349502 ps
CPU time	183.3 seconds
Started	Jan 07 12:38:37 PM PST 24
Finished	Jan 07 12:43:13 PM PST 24
Peak memory	194768 kb
Host	smart-0a211103-5a57-4581-8a02-32113437b45a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927903617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.927903617
Directory	/workspace/1.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/103.rv_timer_random.1006484830
Short name	T253
Test name
Test status
Simulation time	830137180574 ps
CPU time	1538.52 seconds
Started	Jan 07 12:39:49 PM PST 24
Finished	Jan 07 01:06:48 PM PST 24
Peak memory	191020 kb
Host	smart-ba434485-e1d6-40df-8cbb-4d2c1cfbe484
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006484830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1006484830
Directory	/workspace/103.rv_timer_random/latest

Test location	/workspace/coverage/default/106.rv_timer_random.3714917436
Short name	T182
Test name
Test status
Simulation time	158896610438 ps
CPU time	276.15 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:45:26 PM PST 24
Peak memory	191032 kb
Host	smart-20139ae9-d815-4516-9e69-200729feec70
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714917436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3714917436
Directory	/workspace/106.rv_timer_random/latest

Test location	/workspace/coverage/default/110.rv_timer_random.3785842486
Short name	T100
Test name
Test status
Simulation time	117762985978 ps
CPU time	828.69 seconds
Started	Jan 07 12:39:58 PM PST 24
Finished	Jan 07 12:54:52 PM PST 24
Peak memory	182816 kb
Host	smart-ca3129b3-1478-4175-861e-d1a77a2cb19b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785842486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3785842486
Directory	/workspace/110.rv_timer_random/latest

Test location	/workspace/coverage/default/122.rv_timer_random.4175716507
Short name	T259
Test name
Test status
Simulation time	245357421548 ps
CPU time	97.8 seconds
Started	Jan 07 12:39:25 PM PST 24
Finished	Jan 07 12:42:20 PM PST 24
Peak memory	191160 kb
Host	smart-9da76283-e5c3-4259-8863-0ccdc31b467a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175716507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4175716507
Directory	/workspace/122.rv_timer_random/latest

Test location	/workspace/coverage/default/13.rv_timer_random.2636953743
Short name	T126
Test name
Test status
Simulation time	417960844452 ps
CPU time	262.15 seconds
Started	Jan 07 12:40:17 PM PST 24
Finished	Jan 07 12:45:45 PM PST 24
Peak memory	190708 kb
Host	smart-46cc872f-3e56-484d-91e2-ba5cebc2fbd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636953743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2636953743
Directory	/workspace/13.rv_timer_random/latest

Test location	/workspace/coverage/default/16.rv_timer_cfg_update_on_fly.80375508
Short name	T254
Test name
Test status
Simulation time	2209871639664 ps
CPU time	1249.37 seconds
Started	Jan 07 12:39:03 PM PST 24
Finished	Jan 07 01:01:34 PM PST 24
Peak memory	182840 kb
Host	smart-2397b953-d447-403f-b148-a34d7d159e27
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80375508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .rv_timer_cfg_update_on_fly.80375508
Directory	/workspace/16.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/16.rv_timer_random.1672285377
Short name	T180
Test name
Test status
Simulation time	58066193391 ps
CPU time	387.47 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:46:57 PM PST 24
Peak memory	191076 kb
Host	smart-25f76f8a-ef72-4f2d-ad89-2e314364687d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672285377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1672285377
Directory	/workspace/16.rv_timer_random/latest

Test location	/workspace/coverage/default/164.rv_timer_random.2701524061
Short name	T304
Test name
Test status
Simulation time	861841813225 ps
CPU time	1949.21 seconds
Started	Jan 07 12:39:57 PM PST 24
Finished	Jan 07 01:13:45 PM PST 24
Peak memory	190992 kb
Host	smart-d24bd87f-ac9c-40b9-ae9b-5776160cf05a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701524061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2701524061
Directory	/workspace/164.rv_timer_random/latest

Test location	/workspace/coverage/default/166.rv_timer_random.1036283401
Short name	T142
Test name
Test status
Simulation time	193091599892 ps
CPU time	83.19 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:42:10 PM PST 24
Peak memory	194348 kb
Host	smart-75cecb01-12a3-4d4d-b64c-f1e878d3f750
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036283401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1036283401
Directory	/workspace/166.rv_timer_random/latest

Test location	/workspace/coverage/default/184.rv_timer_random.3088089167
Short name	T222
Test name
Test status
Simulation time	43152388817 ps
CPU time	84.54 seconds
Started	Jan 07 12:39:25 PM PST 24
Finished	Jan 07 12:42:19 PM PST 24
Peak memory	182832 kb
Host	smart-bebcb78e-1b94-4c83-b29b-f61eb3ae5ae0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088089167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3088089167
Directory	/workspace/184.rv_timer_random/latest

Test location	/workspace/coverage/default/24.rv_timer_random.484506720
Short name	T168
Test name
Test status
Simulation time	138368193383 ps
CPU time	520.29 seconds
Started	Jan 07 12:38:49 PM PST 24
Finished	Jan 07 12:48:46 PM PST 24
Peak memory	191176 kb
Host	smart-ee75f269-cdfd-402f-9e76-7ed11c17b506
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484506720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.484506720
Directory	/workspace/24.rv_timer_random/latest

Test location	/workspace/coverage/default/28.rv_timer_cfg_update_on_fly.465690637
Short name	T246
Test name
Test status
Simulation time	1290930652615 ps
CPU time	807.94 seconds
Started	Jan 07 12:38:58 PM PST 24
Finished	Jan 07 12:53:46 PM PST 24
Peak memory	182964 kb
Host	smart-a1fd80a8-6aa0-4e4c-84fb-5a7dba4455d8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465690637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.rv_timer_cfg_update_on_fly.465690637
Directory	/workspace/28.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.4184269150
Short name	T194
Test name
Test status
Simulation time	117988917417 ps
CPU time	222.71 seconds
Started	Jan 07 12:38:58 PM PST 24
Finished	Jan 07 12:44:01 PM PST 24
Peak memory	205848 kb
Host	smart-7b3d40da-b791-44c5-8898-edb3a60d8c01
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184269150 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.4184269150
Directory	/workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.rv_timer_random.1029398116
Short name	T277
Test name
Test status
Simulation time	372869655137 ps
CPU time	299.79 seconds
Started	Jan 07 12:39:45 PM PST 24
Finished	Jan 07 12:45:59 PM PST 24
Peak memory	191168 kb
Host	smart-cca8dcc3-9b83-4798-8b29-678e1957c05f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029398116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1029398116
Directory	/workspace/35.rv_timer_random/latest

Test location	/workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2135631231
Short name	T276
Test name
Test status
Simulation time	133433356247 ps
CPU time	240.86 seconds
Started	Jan 07 12:41:28 PM PST 24
Finished	Jan 07 12:47:02 PM PST 24
Peak memory	182416 kb
Host	smart-36659112-0b69-459d-98fd-f11eb300ccb9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135631231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.2135631231
Directory	/workspace/40.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/51.rv_timer_random.3611676358
Short name	T205
Test name
Test status
Simulation time	171907176822 ps
CPU time	323.52 seconds
Started	Jan 07 12:39:36 PM PST 24
Finished	Jan 07 12:46:20 PM PST 24
Peak memory	191032 kb
Host	smart-fc884da1-0c90-4310-8fbd-9419189b7a31
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611676358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3611676358
Directory	/workspace/51.rv_timer_random/latest

Test location	/workspace/coverage/default/78.rv_timer_random.3849797047
Short name	T179
Test name
Test status
Simulation time	627427647580 ps
CPU time	338.31 seconds
Started	Jan 07 12:39:16 PM PST 24
Finished	Jan 07 12:46:31 PM PST 24
Peak memory	191028 kb
Host	smart-b82e94eb-9aba-45f5-925f-c17c66e781b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849797047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3849797047
Directory	/workspace/78.rv_timer_random/latest

Test location	/workspace/coverage/default/87.rv_timer_random.278312389
Short name	T147
Test name
Test status
Simulation time	182189846153 ps
CPU time	1726.31 seconds
Started	Jan 07 12:39:41 PM PST 24
Finished	Jan 07 01:10:11 PM PST 24
Peak memory	191084 kb
Host	smart-1dca88fc-b494-4693-865a-28d0abe85c8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278312389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.278312389
Directory	/workspace/87.rv_timer_random/latest

Test location	/workspace/coverage/default/98.rv_timer_random.2446399559
Short name	T190
Test name
Test status
Simulation time	631893831419 ps
CPU time	595.91 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:50:46 PM PST 24
Peak memory	191028 kb
Host	smart-5fc6e240-a45a-4f5b-90b5-3c4a537dddb6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446399559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2446399559
Directory	/workspace/98.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.159858856
Short name	T476
Test name
Test status
Simulation time	67008310 ps
CPU time	0.79 seconds
Started	Jan 07 12:52:02 PM PST 24
Finished	Jan 07 12:53:11 PM PST 24
Peak memory	193540 kb
Host	smart-ec9f1b18-6891-4a7b-b49e-3001e707a520
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159858856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int g_err.159858856
Directory	/workspace/0.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_intr_test.90186726
Short name	T2
Test name
Test status
Simulation time	57968427 ps
CPU time	0.59 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	182964 kb
Host	smart-2081fc17-abc8-4153-802c-744e108c9a68
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90186726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.90186726
Directory	/workspace/11.rv_timer_intr_test/latest

Test location	/workspace/coverage/default/1.rv_timer_random.3845626767
Short name	T327
Test name
Test status
Simulation time	78890429726 ps
CPU time	318.54 seconds
Started	Jan 07 12:38:37 PM PST 24
Finished	Jan 07 12:45:40 PM PST 24
Peak memory	191052 kb
Host	smart-0210a425-7fa5-40dd-ad7f-fd7e5d7ffea4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845626767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3845626767
Directory	/workspace/1.rv_timer_random/latest

Test location	/workspace/coverage/default/11.rv_timer_random_reset.1003449037
Short name	T324
Test name
Test status
Simulation time	45404560783 ps
CPU time	204.82 seconds
Started	Jan 07 12:41:02 PM PST 24
Finished	Jan 07 12:45:55 PM PST 24
Peak memory	182300 kb
Host	smart-03dea39e-8458-412e-9829-c2e16a01d32d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003449037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1003449037
Directory	/workspace/11.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/111.rv_timer_random.2526573463
Short name	T175
Test name
Test status
Simulation time	194064732176 ps
CPU time	64.09 seconds
Started	Jan 07 12:40:03 PM PST 24
Finished	Jan 07 12:42:23 PM PST 24
Peak memory	182960 kb
Host	smart-9fedd02e-a17e-4efd-8102-8468e300782c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526573463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2526573463
Directory	/workspace/111.rv_timer_random/latest

Test location	/workspace/coverage/default/113.rv_timer_random.1466300030
Short name	T150
Test name
Test status
Simulation time	271215031579 ps
CPU time	1634.14 seconds
Started	Jan 07 12:39:37 PM PST 24
Finished	Jan 07 01:08:25 PM PST 24
Peak memory	190988 kb
Host	smart-0e1e607d-8718-404f-b7c5-c41f543650fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466300030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1466300030
Directory	/workspace/113.rv_timer_random/latest

Test location	/workspace/coverage/default/12.rv_timer_stress_all.2254289635
Short name	T297
Test name
Test status
Simulation time	481533538795 ps
CPU time	725.13 seconds
Started	Jan 07 12:40:10 PM PST 24
Finished	Jan 07 12:53:33 PM PST 24
Peak memory	190692 kb
Host	smart-45e992b0-099d-4e9d-8c76-7f2e300c542a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254289635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .2254289635
Directory	/workspace/12.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/129.rv_timer_random.2311319198
Short name	T240
Test name
Test status
Simulation time	183201322730 ps
CPU time	137.56 seconds
Started	Jan 07 12:39:23 PM PST 24
Finished	Jan 07 12:43:17 PM PST 24
Peak memory	190952 kb
Host	smart-b96f07e6-b613-4766-97b1-ba4f2caf2ee7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311319198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2311319198
Directory	/workspace/129.rv_timer_random/latest

Test location	/workspace/coverage/default/132.rv_timer_random.3638558978
Short name	T223
Test name
Test status
Simulation time	172260725096 ps
CPU time	667.28 seconds
Started	Jan 07 12:40:10 PM PST 24
Finished	Jan 07 12:52:21 PM PST 24
Peak memory	191040 kb
Host	smart-97d08210-e78d-4b99-b3dc-2dbe1efec2b1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638558978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3638558978
Directory	/workspace/132.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3838428169
Short name	T156
Test name
Test status
Simulation time	271642026646 ps
CPU time	500.42 seconds
Started	Jan 07 12:38:27 PM PST 24
Finished	Jan 07 12:48:20 PM PST 24
Peak memory	182940 kb
Host	smart-f596d28c-cad6-4e3e-b330-6bd560828ce5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838428169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3838428169
Directory	/workspace/14.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/14.rv_timer_stress_all.1611949776
Short name	T238
Test name
Test status
Simulation time	1081915920864 ps
CPU time	720.22 seconds
Started	Jan 07 12:38:57 PM PST 24
Finished	Jan 07 12:52:16 PM PST 24
Peak memory	195436 kb
Host	smart-86a69b7f-f681-40ad-be84-1d3e000659b4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611949776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all .1611949776
Directory	/workspace/14.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/146.rv_timer_random.416068133
Short name	T233
Test name
Test status
Simulation time	83820088315 ps
CPU time	214.14 seconds
Started	Jan 07 12:40:05 PM PST 24
Finished	Jan 07 12:44:58 PM PST 24
Peak memory	191184 kb
Host	smart-11e94db3-efdd-4bc2-affa-72bbe4c4bd16
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416068133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.416068133
Directory	/workspace/146.rv_timer_random/latest

Test location	/workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3536156685
Short name	T33
Test name
Test status
Simulation time	397407408681 ps
CPU time	995.15 seconds
Started	Jan 07 12:39:26 PM PST 24
Finished	Jan 07 12:57:17 PM PST 24
Peak memory	209024 kb
Host	smart-980a9238-6396-47b3-ba2f-a0616315bf03
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536156685 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3536156685
Directory	/workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.805305486
Short name	T217
Test name
Test status
Simulation time	985504337232 ps
CPU time	1324.38 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 01:02:58 PM PST 24
Peak memory	213700 kb
Host	smart-bfdfacd0-9846-4020-a91d-1eac675dd102
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805305486 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.805305486
Directory	/workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/171.rv_timer_random.1703836307
Short name	T298
Test name
Test status
Simulation time	357756217618 ps
CPU time	187.08 seconds
Started	Jan 07 12:39:45 PM PST 24
Finished	Jan 07 12:44:05 PM PST 24
Peak memory	193400 kb
Host	smart-d6922343-f947-4a7c-a9d6-5c179f6ab5a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703836307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1703836307
Directory	/workspace/171.rv_timer_random/latest

Test location	/workspace/coverage/default/187.rv_timer_random.803255676
Short name	T286
Test name
Test status
Simulation time	197834757778 ps
CPU time	440.25 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:48:12 PM PST 24
Peak memory	194244 kb
Host	smart-7956a976-f078-4fa4-aaef-85ed62cbdd84
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803255676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.803255676
Directory	/workspace/187.rv_timer_random/latest

Test location	/workspace/coverage/default/19.rv_timer_random.3974851472
Short name	T257
Test name
Test status
Simulation time	226391259575 ps
CPU time	127.4 seconds
Started	Jan 07 12:39:04 PM PST 24
Finished	Jan 07 12:42:46 PM PST 24
Peak memory	191020 kb
Host	smart-7d6f8dc2-3f8f-4132-8e3b-19994c02b4a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974851472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3974851472
Directory	/workspace/19.rv_timer_random/latest

Test location	/workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1271123743
Short name	T312
Test name
Test status
Simulation time	43282099301 ps
CPU time	23.12 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:40:45 PM PST 24
Peak memory	182752 kb
Host	smart-19648206-6257-4c64-bc7e-1ee7c5f814c5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271123743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1271123743
Directory	/workspace/26.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/28.rv_timer_random.2829089702
Short name	T181
Test name
Test status
Simulation time	679625079167 ps
CPU time	369.94 seconds
Started	Jan 07 12:39:45 PM PST 24
Finished	Jan 07 12:47:10 PM PST 24
Peak memory	191144 kb
Host	smart-8925f6ad-b018-4a72-bbed-b3e303b3faeb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829089702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2829089702
Directory	/workspace/28.rv_timer_random/latest

Test location	/workspace/coverage/default/29.rv_timer_random_reset.6947362
Short name	T267
Test name
Test status
Simulation time	27433623460 ps
CPU time	57.54 seconds
Started	Jan 07 12:39:41 PM PST 24
Finished	Jan 07 12:42:00 PM PST 24
Peak memory	191084 kb
Host	smart-1af06a28-d227-490c-acb2-ec4247673e0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6947362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.6947362
Directory	/workspace/29.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/3.rv_timer_random.345284716
Short name	T135
Test name
Test status
Simulation time	775938703683 ps
CPU time	230.09 seconds
Started	Jan 07 12:39:02 PM PST 24
Finished	Jan 07 12:44:19 PM PST 24
Peak memory	190912 kb
Host	smart-ecf143ff-8b91-486f-9405-dbca5054846e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345284716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.345284716
Directory	/workspace/3.rv_timer_random/latest

Test location	/workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1292367337
Short name	T105
Test name
Test status
Simulation time	77488335462 ps
CPU time	40.58 seconds
Started	Jan 07 12:39:05 PM PST 24
Finished	Jan 07 12:41:23 PM PST 24
Peak memory	182836 kb
Host	smart-9113b075-dbbc-4e3d-9445-f0e29c7eb56d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292367337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.1292367337
Directory	/workspace/32.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1755748031
Short name	T124
Test name
Test status
Simulation time	5324930888 ps
CPU time	10.27 seconds
Started	Jan 07 12:40:05 PM PST 24
Finished	Jan 07 12:41:30 PM PST 24
Peak memory	182840 kb
Host	smart-04cab043-5c2e-44e8-9166-b58a858acc63
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755748031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.1755748031
Directory	/workspace/35.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1428102568
Short name	T328
Test name
Test status
Simulation time	21588308280 ps
CPU time	21.93 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:41:15 PM PST 24
Peak memory	182788 kb
Host	smart-aa9b519e-5866-43bd-9252-abc5caa80312
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428102568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.1428102568
Directory	/workspace/36.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/45.rv_timer_random.2035985064
Short name	T204
Test name
Test status
Simulation time	585787790479 ps
CPU time	350.75 seconds
Started	Jan 07 12:39:27 PM PST 24
Finished	Jan 07 12:46:37 PM PST 24
Peak memory	191056 kb
Host	smart-786ba269-9bda-4940-97b0-8d7747bc986e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035985064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2035985064
Directory	/workspace/45.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3888175661
Short name	T287
Test name
Test status
Simulation time	862833198272 ps
CPU time	484.67 seconds
Started	Jan 07 12:39:37 PM PST 24
Finished	Jan 07 12:49:16 PM PST 24
Peak memory	182972 kb
Host	smart-878fff88-272e-47a5-93b0-f9162af22134
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888175661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3888175661
Directory	/workspace/7.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/79.rv_timer_random.487787216
Short name	T275
Test name
Test status
Simulation time	323910960832 ps
CPU time	1227.04 seconds
Started	Jan 07 12:39:15 PM PST 24
Finished	Jan 07 01:01:16 PM PST 24
Peak memory	190996 kb
Host	smart-2725c09e-9d10-479d-99ff-7c952a502993
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487787216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.487787216
Directory	/workspace/79.rv_timer_random/latest

Test location	/workspace/coverage/default/8.rv_timer_random.891767008
Short name	T305
Test name
Test status
Simulation time	87165638032 ps
CPU time	213.92 seconds
Started	Jan 07 12:38:48 PM PST 24
Finished	Jan 07 12:43:26 PM PST 24
Peak memory	190992 kb
Host	smart-f716bcde-e7bb-4e76-a190-a0313e3e993a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891767008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.891767008
Directory	/workspace/8.rv_timer_random/latest

Test location	/workspace/coverage/default/8.rv_timer_random_reset.208040386
Short name	T281
Test name
Test status
Simulation time	333447264957 ps
CPU time	82.5 seconds
Started	Jan 07 12:39:14 PM PST 24
Finished	Jan 07 12:41:56 PM PST 24
Peak memory	191000 kb
Host	smart-ffd180ae-fbfb-4c9e-9859-e4c2c83d3860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208040386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.208040386
Directory	/workspace/8.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/81.rv_timer_random.1984260471
Short name	T166
Test name
Test status
Simulation time	532101746564 ps
CPU time	362.1 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:46:49 PM PST 24
Peak memory	191084 kb
Host	smart-3ab80fe1-62e8-426b-a2d6-539d5e6d0a79
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984260471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1984260471
Directory	/workspace/81.rv_timer_random/latest

Test location	/workspace/coverage/default/84.rv_timer_random.2521651217
Short name	T119
Test name
Test status
Simulation time	218616180691 ps
CPU time	197.19 seconds
Started	Jan 07 12:40:11 PM PST 24
Finished	Jan 07 12:44:43 PM PST 24
Peak memory	191168 kb
Host	smart-b311a3a1-1e4e-4db6-a96b-bb7483b8a651
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521651217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2521651217
Directory	/workspace/84.rv_timer_random/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1700830424
Short name	T56
Test name
Test status
Simulation time	1698967256 ps
CPU time	3.47 seconds
Started	Jan 07 12:52:34 PM PST 24
Finished	Jan 07 12:53:55 PM PST 24
Peak memory	191616 kb
Host	smart-ae0c39c2-ca1e-4adf-bfec-f702679b20be
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700830424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.1700830424
Directory	/workspace/0.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1686900705
Short name	T77
Test name
Test status
Simulation time	24984940 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:28 PM PST 24
Finished	Jan 07 12:53:54 PM PST 24
Peak memory	182456 kb
Host	smart-a6d7e7b1-73c5-43ac-94a9-b22692a4670a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686900705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.1686900705
Directory	/workspace/0.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3777795583
Short name	T69
Test name
Test status
Simulation time	33221874 ps
CPU time	0.95 seconds
Started	Jan 07 12:52:14 PM PST 24
Finished	Jan 07 12:53:56 PM PST 24
Peak memory	197864 kb
Host	smart-4b70db7d-1a89-41ef-af42-749be45007cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777795583 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3777795583
Directory	/workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1380693973
Short name	T469
Test name
Test status
Simulation time	11334285 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:26 PM PST 24
Finished	Jan 07 12:53:48 PM PST 24
Peak memory	183216 kb
Host	smart-95afe9a9-3a9b-4579-854b-81d59d7c02dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380693973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1380693973
Directory	/workspace/0.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3026328992
Short name	T378
Test name
Test status
Simulation time	50267812 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:03 PM PST 24
Finished	Jan 07 12:53:10 PM PST 24
Peak memory	182880 kb
Host	smart-96107e37-0989-4c4d-9687-1cda62ec73dc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026328992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3026328992
Directory	/workspace/0.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2313918400
Short name	T89
Test name
Test status
Simulation time	52085707 ps
CPU time	0.68 seconds
Started	Jan 07 12:51:58 PM PST 24
Finished	Jan 07 12:53:24 PM PST 24
Peak memory	191928 kb
Host	smart-f26b609e-2854-4931-835c-565865adc03c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313918400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.2313918400
Directory	/workspace/0.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.374159986
Short name	T354
Test name
Test status
Simulation time	17467070 ps
CPU time	0.63 seconds
Started	Jan 07 12:51:59 PM PST 24
Finished	Jan 07 12:53:12 PM PST 24
Peak memory	183280 kb
Host	smart-aa3e202c-2d81-4ca6-8d91-a579bcfc149b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374159986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias ing.374159986
Directory	/workspace/1.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3469870730
Short name	T86
Test name
Test status
Simulation time	90279466 ps
CPU time	3.1 seconds
Started	Jan 07 12:52:03 PM PST 24
Finished	Jan 07 12:53:27 PM PST 24
Peak memory	192956 kb
Host	smart-f1799923-4c46-426e-a33c-cbea5e4473ff
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469870730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.3469870730
Directory	/workspace/1.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1124289854
Short name	T15
Test name
Test status
Simulation time	31389166 ps
CPU time	0.63 seconds
Started	Jan 07 12:52:30 PM PST 24
Finished	Jan 07 12:53:43 PM PST 24
Peak memory	183248 kb
Host	smart-4a3d192f-83c6-4c21-90e2-abb40894e671
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124289854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.1124289854
Directory	/workspace/1.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2257959396
Short name	T9
Test name
Test status
Simulation time	288559604 ps
CPU time	0.75 seconds
Started	Jan 07 12:52:28 PM PST 24
Finished	Jan 07 12:53:51 PM PST 24
Peak memory	195660 kb
Host	smart-2fa7bd2c-adec-4a05-ac32-801ea2e2ce0f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257959396 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2257959396
Directory	/workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3913028616
Short name	T373
Test name
Test status
Simulation time	39396306 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:06 PM PST 24
Finished	Jan 07 12:53:21 PM PST 24
Peak memory	182960 kb
Host	smart-aee6ea23-3def-4b40-9705-542ecda48356
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913028616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3913028616
Directory	/workspace/1.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1499801902
Short name	T4
Test name
Test status
Simulation time	16039113 ps
CPU time	0.62 seconds
Started	Jan 07 12:52:01 PM PST 24
Finished	Jan 07 12:53:38 PM PST 24
Peak memory	191816 kb
Host	smart-f76a092f-29f7-402a-873b-d190cb20bc09
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499801902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.1499801902
Directory	/workspace/1.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2380453561
Short name	T362
Test name
Test status
Simulation time	103601099 ps
CPU time	2.52 seconds
Started	Jan 07 12:52:18 PM PST 24
Finished	Jan 07 12:53:38 PM PST 24
Peak memory	198080 kb
Host	smart-ea69e953-6257-4daf-8a43-9149f579f367
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380453561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2380453561
Directory	/workspace/1.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.435994757
Short name	T342
Test name
Test status
Simulation time	39672873 ps
CPU time	0.82 seconds
Started	Jan 07 12:52:01 PM PST 24
Finished	Jan 07 12:53:26 PM PST 24
Peak memory	193852 kb
Host	smart-6dceea7c-585a-4e4a-9b4f-e16a76a67273
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435994757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int g_err.435994757
Directory	/workspace/1.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2595141555
Short name	T383
Test name
Test status
Simulation time	45855612 ps
CPU time	0.59 seconds
Started	Jan 07 12:52:54 PM PST 24
Finished	Jan 07 12:55:07 PM PST 24
Peak memory	193268 kb
Host	smart-24fea90b-9ace-4783-9b56-09d696d5e6b3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595141555 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2595141555
Directory	/workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3963274744
Short name	T87
Test name
Test status
Simulation time	12510322 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:39 PM PST 24
Finished	Jan 07 12:54:23 PM PST 24
Peak memory	183224 kb
Host	smart-6cf278c5-844c-4511-8c81-922f46149ecc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963274744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3963274744
Directory	/workspace/10.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2615843619
Short name	T491
Test name
Test status
Simulation time	22229495 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:52 PM PST 24
Finished	Jan 07 12:54:07 PM PST 24
Peak memory	182808 kb
Host	smart-a3960ea7-2e3e-419e-92e0-df79781aa56e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615843619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2615843619
Directory	/workspace/10.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1439865440
Short name	T48
Test name
Test status
Simulation time	75530612 ps
CPU time	0.68 seconds
Started	Jan 07 12:52:54 PM PST 24
Finished	Jan 07 12:54:06 PM PST 24
Peak memory	192128 kb
Host	smart-e2b70d4f-6144-404f-96d1-f818acbea762
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439865440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.1439865440
Directory	/workspace/10.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3084355851
Short name	T43
Test name
Test status
Simulation time	270343586 ps
CPU time	1.47 seconds
Started	Jan 07 12:52:24 PM PST 24
Finished	Jan 07 12:53:32 PM PST 24
Peak memory	198052 kb
Host	smart-59ec4efb-3351-4b4a-a0f0-b3aa2b256d91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084355851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3084355851
Directory	/workspace/10.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2869353991
Short name	T493
Test name
Test status
Simulation time	270891656 ps
CPU time	1.1 seconds
Started	Jan 07 12:52:51 PM PST 24
Finished	Jan 07 12:54:09 PM PST 24
Peak memory	195424 kb
Host	smart-aa1f5858-7797-441e-a1e6-d5569500a197
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869353991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.2869353991
Directory	/workspace/10.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3019082790
Short name	T50
Test name
Test status
Simulation time	11901176 ps
CPU time	0.52 seconds
Started	Jan 07 12:52:42 PM PST 24
Finished	Jan 07 12:54:27 PM PST 24
Peak memory	182720 kb
Host	smart-a5ce5e62-051a-4bb4-9347-f1a1d8d502ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019082790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3019082790
Directory	/workspace/11.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3204285939
Short name	T52
Test name
Test status
Simulation time	100752018 ps
CPU time	0.67 seconds
Started	Jan 07 12:52:53 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	192488 kb
Host	smart-5889f9e1-d925-4785-afac-9494fe9b7274
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204285939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.3204285939
Directory	/workspace/11.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3759916884
Short name	T384
Test name
Test status
Simulation time	120743055 ps
CPU time	3.14 seconds
Started	Jan 07 12:52:53 PM PST 24
Finished	Jan 07 12:54:13 PM PST 24
Peak memory	197904 kb
Host	smart-22b0f355-decf-4832-86be-418392e60e16
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759916884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3759916884
Directory	/workspace/11.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.918796758
Short name	T366
Test name
Test status
Simulation time	388858889 ps
CPU time	1.42 seconds
Started	Jan 07 12:52:54 PM PST 24
Finished	Jan 07 12:54:54 PM PST 24
Peak memory	183768 kb
Host	smart-f8cecdc7-06c0-4698-a993-681fbe26a574
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918796758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in tg_err.918796758
Directory	/workspace/11.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2838509891
Short name	T61
Test name
Test status
Simulation time	25296118 ps
CPU time	0.74 seconds
Started	Jan 07 12:52:34 PM PST 24
Finished	Jan 07 12:53:53 PM PST 24
Peak memory	196592 kb
Host	smart-89bf3bb1-9cb4-418c-815b-81b79a452ca7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838509891 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2838509891
Directory	/workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2446827166
Short name	T84
Test name
Test status
Simulation time	25046853 ps
CPU time	0.58 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:09 PM PST 24
Peak memory	183336 kb
Host	smart-c044e2e8-2ee9-44ad-8f4a-1aacad8131a7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446827166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2446827166
Directory	/workspace/12.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_intr_test.398450621
Short name	T465
Test name
Test status
Simulation time	14524530 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:28 PM PST 24
Finished	Jan 07 12:53:42 PM PST 24
Peak memory	182928 kb
Host	smart-a7090bd5-3bfa-41fe-8409-42399a88e17d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398450621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.398450621
Directory	/workspace/12.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2399944374
Short name	T360
Test name
Test status
Simulation time	43884879 ps
CPU time	1.52 seconds
Started	Jan 07 12:52:39 PM PST 24
Finished	Jan 07 12:54:19 PM PST 24
Peak memory	198048 kb
Host	smart-9070bb51-3330-48a8-a59f-53ac28f1b56f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399944374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2399944374
Directory	/workspace/12.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3192753370
Short name	T39
Test name
Test status
Simulation time	126686086 ps
CPU time	1.36 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:30 PM PST 24
Peak memory	183552 kb
Host	smart-0f979267-a4b4-449f-87c6-5b6a6e0120b6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192753370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.3192753370
Directory	/workspace/12.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2302766157
Short name	T46
Test name
Test status
Simulation time	73805312 ps
CPU time	0.96 seconds
Started	Jan 07 12:52:24 PM PST 24
Finished	Jan 07 12:53:36 PM PST 24
Peak memory	197744 kb
Host	smart-7fb43ace-d6b5-48ec-b77f-9edb507cafad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302766157 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2302766157
Directory	/workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1994262047
Short name	T74
Test name
Test status
Simulation time	12512517 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:55 PM PST 24
Finished	Jan 07 12:54:09 PM PST 24
Peak memory	192468 kb
Host	smart-1553e51e-d0b0-4ddb-a113-901fdd271c2c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994262047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1994262047
Directory	/workspace/13.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3481550253
Short name	T49
Test name
Test status
Simulation time	15291751 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:33 PM PST 24
Finished	Jan 07 12:54:07 PM PST 24
Peak memory	182852 kb
Host	smart-7f57b166-9ce8-444b-ba93-9e69bb6b3f48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481550253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3481550253
Directory	/workspace/13.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3623347131
Short name	T480
Test name
Test status
Simulation time	114449362 ps
CPU time	0.63 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:47 PM PST 24
Peak memory	192448 kb
Host	smart-637025a2-70e9-45be-9b46-3f583bcca1b8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623347131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.3623347131
Directory	/workspace/13.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.556174065
Short name	T363
Test name
Test status
Simulation time	104405978 ps
CPU time	1.17 seconds
Started	Jan 07 12:52:39 PM PST 24
Finished	Jan 07 12:54:00 PM PST 24
Peak memory	197672 kb
Host	smart-03ca5012-14bb-4076-b16d-00c38699bdc4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556174065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.556174065
Directory	/workspace/13.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1017249590
Short name	T54
Test name
Test status
Simulation time	48295335 ps
CPU time	0.86 seconds
Started	Jan 07 12:52:25 PM PST 24
Finished	Jan 07 12:53:40 PM PST 24
Peak memory	183404 kb
Host	smart-3422a01a-39bd-4aae-a424-8f3771c4f01e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017249590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.1017249590
Directory	/workspace/13.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2910217856
Short name	T377
Test name
Test status
Simulation time	57874539 ps
CPU time	1.54 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:53:51 PM PST 24
Peak memory	197996 kb
Host	smart-be093b2f-aeed-4072-bc1b-4235e1446eba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910217856 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2910217856
Directory	/workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2003867646
Short name	T468
Test name
Test status
Simulation time	20944064 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:17 PM PST 24
Finished	Jan 07 12:53:33 PM PST 24
Peak memory	183148 kb
Host	smart-f733c370-10b3-402c-a55d-8c294d9046ca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003867646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2003867646
Directory	/workspace/14.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_intr_test.452989843
Short name	T350
Test name
Test status
Simulation time	15062768 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:37 PM PST 24
Finished	Jan 07 12:53:45 PM PST 24
Peak memory	182568 kb
Host	smart-dcdaf049-8d70-48d1-b44c-830bda928fd5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452989843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.452989843
Directory	/workspace/14.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2855396156
Short name	T473
Test name
Test status
Simulation time	33939051 ps
CPU time	0.71 seconds
Started	Jan 07 12:52:48 PM PST 24
Finished	Jan 07 12:54:09 PM PST 24
Peak memory	193504 kb
Host	smart-cd7ba98c-4eed-48fb-bfaf-92581f934b79
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855396156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.2855396156
Directory	/workspace/14.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4196053684
Short name	T358
Test name
Test status
Simulation time	27115091 ps
CPU time	1.45 seconds
Started	Jan 07 12:52:30 PM PST 24
Finished	Jan 07 12:53:44 PM PST 24
Peak memory	198036 kb
Host	smart-83f02110-8c42-4870-93b6-977b93c5194e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196053684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4196053684
Directory	/workspace/14.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.149486307
Short name	T496
Test name
Test status
Simulation time	393637949 ps
CPU time	1.43 seconds
Started	Jan 07 12:52:46 PM PST 24
Finished	Jan 07 12:54:23 PM PST 24
Peak memory	195652 kb
Host	smart-d28f177d-cb45-48a5-ae04-fb6e7400615d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149486307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in tg_err.149486307
Directory	/workspace/14.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1382254753
Short name	T474
Test name
Test status
Simulation time	82714213 ps
CPU time	0.82 seconds
Started	Jan 07 12:52:51 PM PST 24
Finished	Jan 07 12:54:04 PM PST 24
Peak memory	195968 kb
Host	smart-49b4e38e-fb12-46af-8ba0-c873d5fcf66a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382254753 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1382254753
Directory	/workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1586307669
Short name	T375
Test name
Test status
Simulation time	12379036 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:24 PM PST 24
Finished	Jan 07 12:53:35 PM PST 24
Peak memory	183120 kb
Host	smart-c6af272e-f5bc-4469-bf14-11518179f64e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586307669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1586307669
Directory	/workspace/15.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2051719574
Short name	T347
Test name
Test status
Simulation time	13443505 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:53:26 PM PST 24
Peak memory	182912 kb
Host	smart-2b50955d-ed3c-4ea7-85c4-8129709c6353
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051719574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2051719574
Directory	/workspace/15.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3756138559
Short name	T379
Test name
Test status
Simulation time	36836124 ps
CPU time	0.62 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:54:11 PM PST 24
Peak memory	192472 kb
Host	smart-320c4d1d-404f-4b8a-9893-6cc460990523
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756138559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.3756138559
Directory	/workspace/15.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3088991717
Short name	T497
Test name
Test status
Simulation time	52721234 ps
CPU time	1.39 seconds
Started	Jan 07 12:52:48 PM PST 24
Finished	Jan 07 12:54:02 PM PST 24
Peak memory	197444 kb
Host	smart-747afbfc-d8c1-4e08-bf9e-a05262d9ec00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088991717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3088991717
Directory	/workspace/15.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3874940405
Short name	T355
Test name
Test status
Simulation time	137945410 ps
CPU time	0.81 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:28 PM PST 24
Peak memory	194080 kb
Host	smart-786e359d-828f-445f-9515-5ca30bf410b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874940405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.3874940405
Directory	/workspace/15.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2774286888
Short name	T359
Test name
Test status
Simulation time	134512576 ps
CPU time	0.8 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:54:07 PM PST 24
Peak memory	196596 kb
Host	smart-d7f94a03-3aae-4850-89a4-80df5141504a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774286888 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2774286888
Directory	/workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_intr_test.725549623
Short name	T352
Test name
Test status
Simulation time	13618593 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:54:14 PM PST 24
Peak memory	182984 kb
Host	smart-057ef21b-4319-422a-a8eb-033adb340bb1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725549623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.725549623
Directory	/workspace/16.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3003764692
Short name	T7
Test name
Test status
Simulation time	94265273 ps
CPU time	0.57 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:33 PM PST 24
Peak memory	191588 kb
Host	smart-af6aa956-e71c-4d3e-8b04-24982e618c92
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003764692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.3003764692
Directory	/workspace/16.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.172573483
Short name	T348
Test name
Test status
Simulation time	101545160 ps
CPU time	1.98 seconds
Started	Jan 07 12:52:49 PM PST 24
Finished	Jan 07 12:54:24 PM PST 24
Peak memory	191676 kb
Host	smart-dbbc4800-5d26-4cef-bf83-7f36ad68cc03
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172573483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.172573483
Directory	/workspace/16.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3149678012
Short name	T479
Test name
Test status
Simulation time	128742175 ps
CPU time	1.42 seconds
Started	Jan 07 12:52:51 PM PST 24
Finished	Jan 07 12:54:05 PM PST 24
Peak memory	183600 kb
Host	smart-3f182b35-821f-419e-8665-d53bc15b718e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149678012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.3149678012
Directory	/workspace/16.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1480636340
Short name	T345
Test name
Test status
Simulation time	71716168 ps
CPU time	0.92 seconds
Started	Jan 07 12:52:31 PM PST 24
Finished	Jan 07 12:54:44 PM PST 24
Peak memory	196732 kb
Host	smart-bb2f81a8-9572-4354-a8bf-8182fb72c3f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480636340 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1480636340
Directory	/workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.336421467
Short name	T481
Test name
Test status
Simulation time	54998298 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:37 PM PST 24
Finished	Jan 07 12:53:45 PM PST 24
Peak memory	183204 kb
Host	smart-3a726b65-58e5-4b8a-88b7-04404c8a5975
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336421467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.336421467
Directory	/workspace/17.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3826739803
Short name	T58
Test name
Test status
Simulation time	15565420 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:53:26 PM PST 24
Peak memory	182832 kb
Host	smart-104b4e60-740d-48f4-b821-b0b11a43dbac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826739803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3826739803
Directory	/workspace/17.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2766035563
Short name	T478
Test name
Test status
Simulation time	107679299 ps
CPU time	0.63 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:53:40 PM PST 24
Peak memory	192580 kb
Host	smart-27d3b247-71a7-4724-a925-41b619528877
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766035563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.2766035563
Directory	/workspace/17.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3644327616
Short name	T368
Test name
Test status
Simulation time	78234729 ps
CPU time	3.13 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:54:11 PM PST 24
Peak memory	198048 kb
Host	smart-ed3ccee8-9113-4f35-aabf-5449619ab614
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644327616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3644327616
Directory	/workspace/17.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2153789734
Short name	T93
Test name
Test status
Simulation time	250418041 ps
CPU time	1.02 seconds
Started	Jan 07 12:52:21 PM PST 24
Finished	Jan 07 12:53:49 PM PST 24
Peak memory	183540 kb
Host	smart-a6931987-837e-4d67-8db6-b36d354e531c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153789734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.2153789734
Directory	/workspace/17.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4120856660
Short name	T380
Test name
Test status
Simulation time	33989745 ps
CPU time	0.93 seconds
Started	Jan 07 12:52:25 PM PST 24
Finished	Jan 07 12:53:39 PM PST 24
Peak memory	197248 kb
Host	smart-92c7be12-f3db-451a-907b-058c15d94d58
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120856660 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4120856660
Directory	/workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3184616905
Short name	T494
Test name
Test status
Simulation time	25822251 ps
CPU time	0.57 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:36 PM PST 24
Peak memory	183156 kb
Host	smart-ad1eaf1c-d851-4f71-b8d0-afd62b3593d1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184616905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3184616905
Directory	/workspace/18.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2643320558
Short name	T16
Test name
Test status
Simulation time	20856385 ps
CPU time	0.51 seconds
Started	Jan 07 12:52:23 PM PST 24
Finished	Jan 07 12:53:41 PM PST 24
Peak memory	181988 kb
Host	smart-b65d59a4-d554-44ad-9ce5-434ad8db8272
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643320558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2643320558
Directory	/workspace/18.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2775215350
Short name	T486
Test name
Test status
Simulation time	61977486 ps
CPU time	0.76 seconds
Started	Jan 07 12:52:35 PM PST 24
Finished	Jan 07 12:53:46 PM PST 24
Peak memory	193848 kb
Host	smart-f27fd958-21b6-4d35-b1fc-9ff4651d966f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775215350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.2775215350
Directory	/workspace/18.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1948777638
Short name	T44
Test name
Test status
Simulation time	376028406 ps
CPU time	1.85 seconds
Started	Jan 07 12:52:25 PM PST 24
Finished	Jan 07 12:53:33 PM PST 24
Peak memory	197908 kb
Host	smart-2dfb90f4-7c27-4bec-aee2-2c30374d44ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948777638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1948777638
Directory	/workspace/18.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3615680518
Short name	T484
Test name
Test status
Simulation time	104415140 ps
CPU time	1.34 seconds
Started	Jan 07 12:52:33 PM PST 24
Finished	Jan 07 12:53:41 PM PST 24
Peak memory	183560 kb
Host	smart-9132d857-1bb1-470e-bcf2-5f9009b512f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615680518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.3615680518
Directory	/workspace/18.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.398444453
Short name	T357
Test name
Test status
Simulation time	27711480 ps
CPU time	0.68 seconds
Started	Jan 07 12:52:53 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	195244 kb
Host	smart-6909f4ee-4556-4acb-8b6e-2033def55d69
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398444453 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.398444453
Directory	/workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.216829998
Short name	T76
Test name
Test status
Simulation time	40382810 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:28 PM PST 24
Peak memory	183316 kb
Host	smart-5a58e899-8b58-467c-a90b-630e2cb59c2b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216829998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.216829998
Directory	/workspace/19.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_intr_test.318424922
Short name	T367
Test name
Test status
Simulation time	26527227 ps
CPU time	0.57 seconds
Started	Jan 07 12:52:59 PM PST 24
Finished	Jan 07 12:54:19 PM PST 24
Peak memory	182952 kb
Host	smart-da8f67fe-5a85-40b3-8e21-00a905e84b32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318424922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.318424922
Directory	/workspace/19.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4141028689
Short name	T51
Test name
Test status
Simulation time	31421823 ps
CPU time	0.7 seconds
Started	Jan 07 12:52:23 PM PST 24
Finished	Jan 07 12:54:16 PM PST 24
Peak memory	191228 kb
Host	smart-8070cacd-f445-4450-8c17-a5074f7cf199
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141028689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.4141028689
Directory	/workspace/19.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4105842912
Short name	T37
Test name
Test status
Simulation time	77967138 ps
CPU time	1.2 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:36 PM PST 24
Peak memory	198092 kb
Host	smart-3b9855a9-1f13-48f8-a986-e727df60832a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105842912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4105842912
Directory	/workspace/19.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2237648984
Short name	T353
Test name
Test status
Simulation time	51694660 ps
CPU time	0.6 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:29 PM PST 24
Peak memory	183204 kb
Host	smart-0a72655f-e2ac-474f-8187-3aeddb9ff4e9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237648984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.2237648984
Directory	/workspace/2.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2100501893
Short name	T338
Test name
Test status
Simulation time	285144212 ps
CPU time	3.58 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:53:37 PM PST 24
Peak memory	193868 kb
Host	smart-7a74eadc-18ee-46db-ad2f-f5f053b5eea3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100501893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.2100501893
Directory	/workspace/2.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1974852197
Short name	T72
Test name
Test status
Simulation time	61867305 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:29 PM PST 24
Peak memory	183212 kb
Host	smart-b080957b-b414-4fd8-a11f-8f1f7ca319cf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974852197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.1974852197
Directory	/workspace/2.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4011133999
Short name	T62
Test name
Test status
Simulation time	66526249 ps
CPU time	0.67 seconds
Started	Jan 07 12:52:24 PM PST 24
Finished	Jan 07 12:53:36 PM PST 24
Peak memory	194692 kb
Host	smart-e6e6c8e7-6ce7-4caf-a874-24f1e9371b4c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011133999 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4011133999
Directory	/workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3908656238
Short name	T1
Test name
Test status
Simulation time	15572319 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:32 PM PST 24
Peak memory	183268 kb
Host	smart-3a1348e5-4350-4e30-b62e-4535c7653cd1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908656238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3908656238
Directory	/workspace/2.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1000906098
Short name	T57
Test name
Test status
Simulation time	37474902 ps
CPU time	0.52 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:25 PM PST 24
Peak memory	182788 kb
Host	smart-1135be72-c3c9-461a-b3bd-ead5c5801dc0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000906098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1000906098
Directory	/workspace/2.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3513823365
Short name	T88
Test name
Test status
Simulation time	70771293 ps
CPU time	0.7 seconds
Started	Jan 07 12:52:58 PM PST 24
Finished	Jan 07 12:54:13 PM PST 24
Peak memory	193560 kb
Host	smart-73759a7f-1b5d-4751-8097-7e2aa7b2a013
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513823365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.3513823365
Directory	/workspace/2.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1355148852
Short name	T462
Test name
Test status
Simulation time	517504755 ps
CPU time	2.75 seconds
Started	Jan 07 12:52:27 PM PST 24
Finished	Jan 07 12:53:51 PM PST 24
Peak memory	198080 kb
Host	smart-c2b64fb9-e198-4db2-8bc2-0be5f9cdd5eb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355148852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1355148852
Directory	/workspace/2.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3238133311
Short name	T464
Test name
Test status
Simulation time	132768296 ps
CPU time	1.1 seconds
Started	Jan 07 12:52:48 PM PST 24
Finished	Jan 07 12:54:15 PM PST 24
Peak memory	195192 kb
Host	smart-6d62c106-d952-4f33-be35-52585d531313
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238133311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.3238133311
Directory	/workspace/2.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3896891176
Short name	T64
Test name
Test status
Simulation time	25833242 ps
CPU time	0.61 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:29 PM PST 24
Peak memory	182940 kb
Host	smart-686cff3d-c5b9-49c0-bbaa-e193536cae8f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896891176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3896891176
Directory	/workspace/20.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.rv_timer_intr_test.607768970
Short name	T341
Test name
Test status
Simulation time	16693887 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:38 PM PST 24
Finished	Jan 07 12:54:05 PM PST 24
Peak memory	182820 kb
Host	smart-873941b9-6438-499e-9e1f-6c0f4e434aad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607768970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.607768970
Directory	/workspace/21.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2794239967
Short name	T337
Test name
Test status
Simulation time	33102586 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:23 PM PST 24
Finished	Jan 07 12:53:37 PM PST 24
Peak memory	182476 kb
Host	smart-e0d60dce-1b94-4384-baad-56ea653b4f07
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794239967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2794239967
Directory	/workspace/22.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3607821065
Short name	T477
Test name
Test status
Simulation time	39037398 ps
CPU time	0.58 seconds
Started	Jan 07 12:52:46 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	182768 kb
Host	smart-07698b67-ac71-4954-9c3b-911136d8f90f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607821065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3607821065
Directory	/workspace/23.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.rv_timer_intr_test.93475536
Short name	T60
Test name
Test status
Simulation time	22397205 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:58 PM PST 24
Finished	Jan 07 12:54:16 PM PST 24
Peak memory	182868 kb
Host	smart-e6c4275f-d4a1-43b7-9cc8-d544921b2c68
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93475536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.93475536
Directory	/workspace/24.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2952760866
Short name	T364
Test name
Test status
Simulation time	30603999 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:42 PM PST 24
Finished	Jan 07 12:54:21 PM PST 24
Peak memory	182752 kb
Host	smart-4e694bd9-7aa7-4ef9-9761-d3505ed1db7e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952760866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2952760866
Directory	/workspace/25.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2743974584
Short name	T381
Test name
Test status
Simulation time	12422912 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:44 PM PST 24
Finished	Jan 07 12:54:16 PM PST 24
Peak memory	182972 kb
Host	smart-0f48a2e5-2ab7-4bdb-9f99-df34004e1c0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743974584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2743974584
Directory	/workspace/27.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2915119107
Short name	T349
Test name
Test status
Simulation time	49790472 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:45 PM PST 24
Finished	Jan 07 12:54:01 PM PST 24
Peak memory	182792 kb
Host	smart-93345b86-659d-4cf5-ad49-888b698abd60
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915119107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2915119107
Directory	/workspace/29.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3275700877
Short name	T483
Test name
Test status
Simulation time	34595757 ps
CPU time	0.59 seconds
Started	Jan 07 12:52:27 PM PST 24
Finished	Jan 07 12:53:46 PM PST 24
Peak memory	183080 kb
Host	smart-c03ab89c-d725-4704-8271-57f96aeca96f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275700877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.3275700877
Directory	/workspace/3.rv_timer_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1218725951
Short name	T71
Test name
Test status
Simulation time	15910451 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:54 PM PST 24
Finished	Jan 07 12:54:05 PM PST 24
Peak memory	183228 kb
Host	smart-ffef3792-4c22-488c-b469-9af2090779a0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218725951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.1218725951
Directory	/workspace/3.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1734869057
Short name	T361
Test name
Test status
Simulation time	21724555 ps
CPU time	0.72 seconds
Started	Jan 07 12:52:30 PM PST 24
Finished	Jan 07 12:53:41 PM PST 24
Peak memory	195200 kb
Host	smart-1d0fea04-12a6-4a01-b78c-98d6f8a89208
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734869057 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1734869057
Directory	/workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.96736958
Short name	T495
Test name
Test status
Simulation time	48747160 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:23 PM PST 24
Finished	Jan 07 12:54:16 PM PST 24
Peak memory	181836 kb
Host	smart-9862997e-2bbe-42a4-9a12-95348412acc2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96736958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.96736958
Directory	/workspace/3.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_intr_test.192549813
Short name	T503
Test name
Test status
Simulation time	11141976 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:45 PM PST 24
Finished	Jan 07 12:54:05 PM PST 24
Peak memory	182800 kb
Host	smart-3c41eae1-696a-42cb-a7a7-b25f5ad22371
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192549813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.192549813
Directory	/workspace/3.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1125402620
Short name	T471
Test name
Test status
Simulation time	29002723 ps
CPU time	0.73 seconds
Started	Jan 07 12:52:23 PM PST 24
Finished	Jan 07 12:53:44 PM PST 24
Peak memory	192176 kb
Host	smart-4f8da25f-c53c-452b-8764-d66dba8015f3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125402620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.1125402620
Directory	/workspace/3.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2190310910
Short name	T382
Test name
Test status
Simulation time	151256949 ps
CPU time	0.9 seconds
Started	Jan 07 12:52:27 PM PST 24
Finished	Jan 07 12:53:39 PM PST 24
Peak memory	183568 kb
Host	smart-4d893548-2b50-4290-8c5b-16f8d9f16ec3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190310910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.2190310910
Directory	/workspace/3.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1162200351
Short name	T504
Test name
Test status
Simulation time	28064504 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:37 PM PST 24
Finished	Jan 07 12:53:49 PM PST 24
Peak memory	182912 kb
Host	smart-a88b3d1d-0198-4b2b-90c9-6cff275e4aa1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162200351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1162200351
Directory	/workspace/30.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3515889999
Short name	T63
Test name
Test status
Simulation time	61570833 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:35 PM PST 24
Finished	Jan 07 12:53:54 PM PST 24
Peak memory	182924 kb
Host	smart-97fba76d-f81f-4598-9f33-e2fd797ab463
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515889999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3515889999
Directory	/workspace/32.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3387937793
Short name	T487
Test name
Test status
Simulation time	16751014 ps
CPU time	0.51 seconds
Started	Jan 07 12:52:45 PM PST 24
Finished	Jan 07 12:54:01 PM PST 24
Peak memory	182340 kb
Host	smart-07a79651-dc8b-45c0-b858-1432d93a3494
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387937793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3387937793
Directory	/workspace/33.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.rv_timer_intr_test.487089912
Short name	T500
Test name
Test status
Simulation time	15527517 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:38 PM PST 24
Finished	Jan 07 12:53:53 PM PST 24
Peak memory	182796 kb
Host	smart-d0b179e0-398d-403f-9ebd-33ba01dd9da4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487089912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.487089912
Directory	/workspace/34.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1052741505
Short name	T369
Test name
Test status
Simulation time	13516819 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:33 PM PST 24
Finished	Jan 07 12:53:47 PM PST 24
Peak memory	182856 kb
Host	smart-cb85e33e-5812-4c36-a2a3-7f31b55d7af9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052741505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1052741505
Directory	/workspace/35.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.rv_timer_intr_test.254961654
Short name	T374
Test name
Test status
Simulation time	16333850 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:17 PM PST 24
Peak memory	182896 kb
Host	smart-9cac216c-a908-4cdf-b96d-c7f9d98b68bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254961654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.254961654
Directory	/workspace/36.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1207816414
Short name	T492
Test name
Test status
Simulation time	12406150 ps
CPU time	0.51 seconds
Started	Jan 07 12:52:28 PM PST 24
Finished	Jan 07 12:53:46 PM PST 24
Peak memory	182080 kb
Host	smart-082251cd-2134-4f51-a1a0-053c7e769c2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207816414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1207816414
Directory	/workspace/37.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.rv_timer_intr_test.521227959
Short name	T339
Test name
Test status
Simulation time	38847315 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:55 PM PST 24
Finished	Jan 07 12:54:18 PM PST 24
Peak memory	182956 kb
Host	smart-2c315439-357d-41b2-9b57-b248ca4367aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521227959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.521227959
Directory	/workspace/38.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3349704192
Short name	T475
Test name
Test status
Simulation time	18747095 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:36 PM PST 24
Finished	Jan 07 12:53:56 PM PST 24
Peak memory	182804 kb
Host	smart-0886f1b1-6936-45e6-a1d1-6b3ccfe7f40b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349704192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3349704192
Directory	/workspace/39.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3477926403
Short name	T502
Test name
Test status
Simulation time	337573389 ps
CPU time	2.99 seconds
Started	Jan 07 12:52:39 PM PST 24
Finished	Jan 07 12:54:15 PM PST 24
Peak memory	192808 kb
Host	smart-84a99c96-cffe-48d5-bbc4-ef34b83c6674
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477926403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.3477926403
Directory	/workspace/4.rv_timer_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2425817899
Short name	T59
Test name
Test status
Simulation time	14787756 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:24 PM PST 24
Finished	Jan 07 12:53:36 PM PST 24
Peak memory	182648 kb
Host	smart-27da0e48-055d-4793-80f8-a2dc3675f85b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425817899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2425817899
Directory	/workspace/4.rv_timer_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3144551643
Short name	T351
Test name
Test status
Simulation time	16167097 ps
CPU time	0.59 seconds
Started	Jan 07 12:52:46 PM PST 24
Finished	Jan 07 12:53:58 PM PST 24
Peak memory	193216 kb
Host	smart-d29d0850-29a2-472c-9b5a-d3a45b2ead87
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144551643 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3144551643
Directory	/workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.15071407
Short name	T370
Test name
Test status
Simulation time	182059108 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:52 PM PST 24
Peak memory	183168 kb
Host	smart-89ac8ecc-0a00-440f-8655-1880789c1216
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.15071407
Directory	/workspace/4.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2185386043
Short name	T489
Test name
Test status
Simulation time	97085790 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:22 PM PST 24
Finished	Jan 07 12:53:28 PM PST 24
Peak memory	182936 kb
Host	smart-eec9bcb1-85bc-442c-9c58-dc91ea71500d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185386043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2185386043
Directory	/workspace/4.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3289437241
Short name	T371
Test name
Test status
Simulation time	137243647 ps
CPU time	0.76 seconds
Started	Jan 07 12:52:40 PM PST 24
Finished	Jan 07 12:53:47 PM PST 24
Peak memory	192180 kb
Host	smart-b13e017a-6f0b-4834-b07b-8b5fd4c2dc75
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289437241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.3289437241
Directory	/workspace/4.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1352406265
Short name	T38
Test name
Test status
Simulation time	145230754 ps
CPU time	1.03 seconds
Started	Jan 07 12:52:24 PM PST 24
Finished	Jan 07 12:53:51 PM PST 24
Peak memory	183788 kb
Host	smart-23624633-d378-4a2d-8426-3e2a6ade09a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352406265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.1352406265
Directory	/workspace/4.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.rv_timer_intr_test.294098401
Short name	T343
Test name
Test status
Simulation time	20314715 ps
CPU time	0.53 seconds
Started	Jan 07 12:52:47 PM PST 24
Finished	Jan 07 12:53:59 PM PST 24
Peak memory	182876 kb
Host	smart-8cad7f46-f70e-43c6-b795-2fe65bad8c4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294098401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.294098401
Directory	/workspace/40.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.rv_timer_intr_test.392019040
Short name	T340
Test name
Test status
Simulation time	12180393 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:56 PM PST 24
Finished	Jan 07 12:54:30 PM PST 24
Peak memory	182864 kb
Host	smart-6529817b-6dbb-42f1-a78c-7919411c4641
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392019040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.392019040
Directory	/workspace/41.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2077728166
Short name	T467
Test name
Test status
Simulation time	12168823 ps
CPU time	0.59 seconds
Started	Jan 07 12:53:22 PM PST 24
Finished	Jan 07 12:54:43 PM PST 24
Peak memory	182920 kb
Host	smart-e72aeabd-a7c5-46eb-b95e-d56dd6496a9a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077728166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2077728166
Directory	/workspace/42.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1084486198
Short name	T490
Test name
Test status
Simulation time	34546388 ps
CPU time	0.55 seconds
Started	Jan 07 12:53:00 PM PST 24
Finished	Jan 07 12:54:17 PM PST 24
Peak memory	182876 kb
Host	smart-7dc72176-ce87-430c-977e-aa10d847e0d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084486198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1084486198
Directory	/workspace/44.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.rv_timer_intr_test.532856853
Short name	T466
Test name
Test status
Simulation time	27993576 ps
CPU time	0.55 seconds
Started	Jan 07 12:52:59 PM PST 24
Finished	Jan 07 12:54:21 PM PST 24
Peak memory	182900 kb
Host	smart-79fa69a6-8c00-41c8-ab64-4c59d5c2437b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532856853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.532856853
Directory	/workspace/45.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3162517870
Short name	T463
Test name
Test status
Simulation time	50290407 ps
CPU time	0.55 seconds
Started	Jan 07 12:53:04 PM PST 24
Finished	Jan 07 12:54:24 PM PST 24
Peak memory	182820 kb
Host	smart-c28aa1b0-c43c-4e66-8a9f-45e78c4ae85c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162517870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3162517870
Directory	/workspace/46.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1996919027
Short name	T372
Test name
Test status
Simulation time	15010572 ps
CPU time	0.54 seconds
Started	Jan 07 12:53:03 PM PST 24
Finished	Jan 07 12:54:20 PM PST 24
Peak memory	181988 kb
Host	smart-3f18cae4-4e03-4346-a38b-f692aefcaa28
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996919027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1996919027
Directory	/workspace/47.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2910971120
Short name	T488
Test name
Test status
Simulation time	63175623 ps
CPU time	0.52 seconds
Started	Jan 07 12:53:43 PM PST 24
Finished	Jan 07 12:55:09 PM PST 24
Peak memory	182004 kb
Host	smart-8977f131-3e9e-4fde-abd9-2006ff0de5bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910971120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2910971120
Directory	/workspace/48.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1594448370
Short name	T470
Test name
Test status
Simulation time	16623593 ps
CPU time	0.54 seconds
Started	Jan 07 12:53:02 PM PST 24
Finished	Jan 07 12:54:21 PM PST 24
Peak memory	182868 kb
Host	smart-19be6d12-2e0e-41f2-ac2d-07f6c4b5122a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594448370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1594448370
Directory	/workspace/49.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2241446868
Short name	T10
Test name
Test status
Simulation time	24196548 ps
CPU time	0.58 seconds
Started	Jan 07 12:52:54 PM PST 24
Finished	Jan 07 12:54:18 PM PST 24
Peak memory	183256 kb
Host	smart-40760f51-3736-496a-af0b-eebced05618f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241446868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2241446868
Directory	/workspace/5.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2448604956
Short name	T47
Test name
Test status
Simulation time	41680669 ps
CPU time	0.51 seconds
Started	Jan 07 12:52:33 PM PST 24
Finished	Jan 07 12:54:07 PM PST 24
Peak memory	182912 kb
Host	smart-6141418c-eb37-40e5-88da-cc90d0f876fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448604956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2448604956
Directory	/workspace/5.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3032848815
Short name	T472
Test name
Test status
Simulation time	31201265 ps
CPU time	0.68 seconds
Started	Jan 07 12:52:30 PM PST 24
Finished	Jan 07 12:53:44 PM PST 24
Peak memory	192096 kb
Host	smart-d2e566e8-6c7e-4ab6-bcd8-110c4adf523e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032848815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.3032848815
Directory	/workspace/5.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2110416720
Short name	T376
Test name
Test status
Simulation time	148783775 ps
CPU time	1.85 seconds
Started	Jan 07 12:52:31 PM PST 24
Finished	Jan 07 12:54:06 PM PST 24
Peak memory	197340 kb
Host	smart-b7b1eec8-de2d-40fd-8182-3fe849285cba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110416720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2110416720
Directory	/workspace/5.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2575751383
Short name	T14
Test name
Test status
Simulation time	106273577 ps
CPU time	1.08 seconds
Started	Jan 07 12:52:40 PM PST 24
Finished	Jan 07 12:53:57 PM PST 24
Peak memory	183676 kb
Host	smart-378785e1-b81e-489a-a397-c1d97091e540
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575751383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.2575751383
Directory	/workspace/5.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2541363417
Short name	T67
Test name
Test status
Simulation time	162199300 ps
CPU time	1.02 seconds
Started	Jan 07 12:52:46 PM PST 24
Finished	Jan 07 12:54:13 PM PST 24
Peak memory	197760 kb
Host	smart-34797d7b-ded3-4a3a-89a3-f1d08bca6157
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541363417 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2541363417
Directory	/workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3943138252
Short name	T73
Test name
Test status
Simulation time	33810804 ps
CPU time	0.56 seconds
Started	Jan 07 12:52:20 PM PST 24
Finished	Jan 07 12:53:30 PM PST 24
Peak memory	183268 kb
Host	smart-27945e1e-6ed6-447c-aaa5-9482afbf5206
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943138252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3943138252
Directory	/workspace/6.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_intr_test.484869685
Short name	T346
Test name
Test status
Simulation time	16886795 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:53:59 PM PST 24
Peak memory	182932 kb
Host	smart-480d39b8-ff8e-42fe-ab66-6839e9e18625
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484869685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.484869685
Directory	/workspace/6.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1189259317
Short name	T485
Test name
Test status
Simulation time	46558527 ps
CPU time	1.69 seconds
Started	Jan 07 12:52:33 PM PST 24
Finished	Jan 07 12:53:48 PM PST 24
Peak memory	191592 kb
Host	smart-4e0e6ad3-557a-495b-9948-2e8d2fe4da47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189259317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1189259317
Directory	/workspace/6.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1906226235
Short name	T91
Test name
Test status
Simulation time	44558918 ps
CPU time	0.89 seconds
Started	Jan 07 12:52:47 PM PST 24
Finished	Jan 07 12:54:00 PM PST 24
Peak memory	193880 kb
Host	smart-43096b51-cdae-4624-b4e2-330dae9e6307
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906226235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.1906226235
Directory	/workspace/6.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4097907320
Short name	T344
Test name
Test status
Simulation time	36598972 ps
CPU time	0.62 seconds
Started	Jan 07 12:52:49 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	193852 kb
Host	smart-9fd82e20-740a-4203-9889-44ccd66ca7d9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097907320 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.4097907320
Directory	/workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3131927822
Short name	T85
Test name
Test status
Simulation time	25490621 ps
CPU time	0.57 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:29 PM PST 24
Peak memory	192536 kb
Host	smart-eeb4ad7d-671f-4d87-a65c-366375cbf03e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131927822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3131927822
Directory	/workspace/7.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_intr_test.9975877
Short name	T356
Test name
Test status
Simulation time	91104448 ps
CPU time	0.54 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:29 PM PST 24
Peak memory	182820 kb
Host	smart-ad275755-1662-4174-9d25-bf0137ef7947
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9975877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.9975877
Directory	/workspace/7.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3766501840
Short name	T501
Test name
Test status
Simulation time	21365138 ps
CPU time	0.67 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:26 PM PST 24
Peak memory	192240 kb
Host	smart-474f1f47-c3fa-4c6e-a035-d83a0d6a6586
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766501840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.3766501840
Directory	/workspace/7.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1076087029
Short name	T42
Test name
Test status
Simulation time	228306043 ps
CPU time	2.37 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:28 PM PST 24
Peak memory	198008 kb
Host	smart-a1567ec9-e963-4d3d-9bab-6464dd15860d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076087029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1076087029
Directory	/workspace/7.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.190499850
Short name	T92
Test name
Test status
Simulation time	259182084 ps
CPU time	1.13 seconds
Started	Jan 07 12:52:25 PM PST 24
Finished	Jan 07 12:53:32 PM PST 24
Peak memory	195220 kb
Host	smart-b66fc99a-a7ab-427c-b467-c7f5caa55c2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190499850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int g_err.190499850
Directory	/workspace/7.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1407798367
Short name	T499
Test name
Test status
Simulation time	22719235 ps
CPU time	0.75 seconds
Started	Jan 07 12:52:36 PM PST 24
Finished	Jan 07 12:54:21 PM PST 24
Peak memory	196176 kb
Host	smart-a70e3afc-9815-433d-80be-ff762c36eca7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407798367 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1407798367
Directory	/workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_intr_test.707290291
Short name	T482
Test name
Test status
Simulation time	23198798 ps
CPU time	0.57 seconds
Started	Jan 07 12:52:49 PM PST 24
Finished	Jan 07 12:54:23 PM PST 24
Peak memory	182856 kb
Host	smart-b0f75d72-a05a-4440-aef4-9072d879580b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707290291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.707290291
Directory	/workspace/8.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.239460799
Short name	T460
Test name
Test status
Simulation time	260554302 ps
CPU time	0.84 seconds
Started	Jan 07 12:52:32 PM PST 24
Finished	Jan 07 12:53:47 PM PST 24
Peak memory	193552 kb
Host	smart-d86399ad-c63a-4ea0-b5fd-5ac02d5edc0a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239460799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim er_same_csr_outstanding.239460799
Directory	/workspace/8.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2749283462
Short name	T8
Test name
Test status
Simulation time	280535801 ps
CPU time	1.46 seconds
Started	Jan 07 12:52:49 PM PST 24
Finished	Jan 07 12:54:10 PM PST 24
Peak memory	198064 kb
Host	smart-ddc5773c-7d9a-4b48-b6de-e81d86c81dc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749283462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2749283462
Directory	/workspace/8.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3125961979
Short name	T55
Test name
Test status
Simulation time	583844093 ps
CPU time	1.05 seconds
Started	Jan 07 12:52:27 PM PST 24
Finished	Jan 07 12:53:34 PM PST 24
Peak memory	183488 kb
Host	smart-8e24e6e6-40c2-4541-a02e-24b9d56d586c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125961979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.3125961979
Directory	/workspace/8.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1366890917
Short name	T45
Test name
Test status
Simulation time	24828844 ps
CPU time	0.64 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:54:07 PM PST 24
Peak memory	194720 kb
Host	smart-866092e5-30d0-43fc-8b85-d0ccf6a5302f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366890917 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1366890917
Directory	/workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.753306050
Short name	T5
Test name
Test status
Simulation time	17386741 ps
CPU time	0.52 seconds
Started	Jan 07 12:52:19 PM PST 24
Finished	Jan 07 12:53:28 PM PST 24
Peak memory	182564 kb
Host	smart-949f1972-2a1d-452b-9f0b-8c298588a4eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753306050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.753306050
Directory	/workspace/9.rv_timer_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2758955890
Short name	T461
Test name
Test status
Simulation time	49517909 ps
CPU time	0.58 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:54:07 PM PST 24
Peak memory	182996 kb
Host	smart-4b5f0d78-d8fc-4748-92ac-42aa7d75555c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758955890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2758955890
Directory	/workspace/9.rv_timer_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1976570656
Short name	T365
Test name
Test status
Simulation time	26360443 ps
CPU time	0.72 seconds
Started	Jan 07 12:52:50 PM PST 24
Finished	Jan 07 12:54:04 PM PST 24
Peak memory	193464 kb
Host	smart-e7f028d2-84c8-4dd5-bba7-ebc7c5d082e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976570656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.1976570656
Directory	/workspace/9.rv_timer_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.486835956
Short name	T40
Test name
Test status
Simulation time	72610186 ps
CPU time	1.53 seconds
Started	Jan 07 12:52:21 PM PST 24
Finished	Jan 07 12:53:42 PM PST 24
Peak memory	197952 kb
Host	smart-cde51304-ecc6-434c-82fa-f258b14fbedb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486835956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.486835956
Directory	/workspace/9.rv_timer_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.974543129
Short name	T498
Test name
Test status
Simulation time	256920598 ps
CPU time	1.03 seconds
Started	Jan 07 12:52:32 PM PST 24
Finished	Jan 07 12:53:40 PM PST 24
Peak memory	195508 kb
Host	smart-ad2fe9b4-7f27-4b92-bdef-70766b847fef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974543129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int g_err.974543129
Directory	/workspace/9.rv_timer_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4187905614
Short name	T303
Test name
Test status
Simulation time	55012247912 ps
CPU time	30.48 seconds
Started	Jan 07 12:38:58 PM PST 24
Finished	Jan 07 12:40:57 PM PST 24
Peak memory	182820 kb
Host	smart-f2d1a224-97ad-4faf-b835-cf8e8e9d008e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187905614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.4187905614
Directory	/workspace/0.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/0.rv_timer_disabled.143037758
Short name	T434
Test name
Test status
Simulation time	506336858137 ps
CPU time	213.79 seconds
Started	Jan 07 12:38:38 PM PST 24
Finished	Jan 07 12:43:35 PM PST 24
Peak memory	182976 kb
Host	smart-7ec3ba81-bc37-46e3-837e-10826ef3c4c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143037758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.143037758
Directory	/workspace/0.rv_timer_disabled/latest

Test location	/workspace/coverage/default/0.rv_timer_random_reset.1732449925
Short name	T306
Test name
Test status
Simulation time	587450276332 ps
CPU time	694.53 seconds
Started	Jan 07 12:38:33 PM PST 24
Finished	Jan 07 12:51:29 PM PST 24
Peak memory	191012 kb
Host	smart-2d0e7afa-9de6-4cfc-aa96-29f3b4b79c3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732449925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1732449925
Directory	/workspace/0.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/0.rv_timer_stress_all.1877885450
Short name	T90
Test name
Test status
Simulation time	976812971097 ps
CPU time	882.67 seconds
Started	Jan 07 12:38:44 PM PST 24
Finished	Jan 07 12:54:59 PM PST 24
Peak memory	195436 kb
Host	smart-f399016d-71dd-4194-9f95-cd209dd686b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877885450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 1877885450
Directory	/workspace/0.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/1.rv_timer_cfg_update_on_fly.133133140
Short name	T321
Test name
Test status
Simulation time	353246068191 ps
CPU time	528.07 seconds
Started	Jan 07 12:38:42 PM PST 24
Finished	Jan 07 12:48:47 PM PST 24
Peak memory	182752 kb
Host	smart-71708f71-37d7-4dee-8053-169e4995fbff
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133133140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rv_timer_cfg_update_on_fly.133133140
Directory	/workspace/1.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/1.rv_timer_disabled.414820619
Short name	T402
Test name
Test status
Simulation time	136744608367 ps
CPU time	188.6 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 12:43:22 PM PST 24
Peak memory	182848 kb
Host	smart-651844ba-f43d-4f36-971a-b6a6b94c9197
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414820619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.414820619
Directory	/workspace/1.rv_timer_disabled/latest

Test location	/workspace/coverage/default/1.rv_timer_random_reset.2617602639
Short name	T422
Test name
Test status
Simulation time	3249733639 ps
CPU time	7.52 seconds
Started	Jan 07 12:39:05 PM PST 24
Finished	Jan 07 12:40:34 PM PST 24
Peak memory	182884 kb
Host	smart-256c0747-07a7-43dc-ab55-4b6fdc5c3a26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617602639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2617602639
Directory	/workspace/1.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/1.rv_timer_sec_cm.3825890585
Short name	T27
Test name
Test status
Simulation time	261130432 ps
CPU time	0.8 seconds
Started	Jan 07 12:38:21 PM PST 24
Finished	Jan 07 12:39:48 PM PST 24
Peak memory	212748 kb
Host	smart-6f8e26a7-d476-4470-888a-945ba5c667e7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825890585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3825890585
Directory	/workspace/1.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3320055214
Short name	T442
Test name
Test status
Simulation time	426421080171 ps
CPU time	852.96 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:54:50 PM PST 24
Peak memory	210204 kb
Host	smart-20d47bae-4a9a-49d2-a4e8-e7df4dc6c532
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320055214 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3320055214
Directory	/workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.rv_timer_random_reset.3755712183
Short name	T403
Test name
Test status
Simulation time	3663869631 ps
CPU time	6.28 seconds
Started	Jan 07 12:39:47 PM PST 24
Finished	Jan 07 12:41:17 PM PST 24
Peak memory	182788 kb
Host	smart-fee0db7a-e905-4e8c-a41a-ca2fc468aa4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755712183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3755712183
Directory	/workspace/10.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.965366732
Short name	T396
Test name
Test status
Simulation time	175351949313 ps
CPU time	379.52 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 12:47:11 PM PST 24
Peak memory	205728 kb
Host	smart-8f95ba36-56b3-4764-8732-1dc4664c1215
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965366732 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.965366732
Directory	/workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/101.rv_timer_random.673007905
Short name	T218
Test name
Test status
Simulation time	77865049709 ps
CPU time	148.78 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 12:43:29 PM PST 24
Peak memory	191080 kb
Host	smart-fd493fbc-d929-424e-86c5-ec5a0b6bad5d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673007905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.673007905
Directory	/workspace/101.rv_timer_random/latest

Test location	/workspace/coverage/default/102.rv_timer_random.1256608339
Short name	T334
Test name
Test status
Simulation time	15987480675 ps
CPU time	144.97 seconds
Started	Jan 07 12:39:41 PM PST 24
Finished	Jan 07 12:43:24 PM PST 24
Peak memory	182824 kb
Host	smart-067a31bd-4773-436d-8f69-4bf6dc3e395f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256608339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1256608339
Directory	/workspace/102.rv_timer_random/latest

Test location	/workspace/coverage/default/105.rv_timer_random.2262662036
Short name	T118
Test name
Test status
Simulation time	42311558403 ps
CPU time	60.45 seconds
Started	Jan 07 12:40:03 PM PST 24
Finished	Jan 07 12:42:22 PM PST 24
Peak memory	182624 kb
Host	smart-ad67cb12-38ec-4089-85cf-57e24dbcfa7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262662036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2262662036
Directory	/workspace/105.rv_timer_random/latest

Test location	/workspace/coverage/default/107.rv_timer_random.127268541
Short name	T21
Test name
Test status
Simulation time	70666096197 ps
CPU time	473.19 seconds
Started	Jan 07 12:40:34 PM PST 24
Finished	Jan 07 12:49:50 PM PST 24
Peak memory	193752 kb
Host	smart-48a2b6b4-d2e9-4167-929e-c958e917e52a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127268541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.127268541
Directory	/workspace/107.rv_timer_random/latest

Test location	/workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2858848263
Short name	T207
Test name
Test status
Simulation time	467345107534 ps
CPU time	244.16 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:44:23 PM PST 24
Peak memory	182752 kb
Host	smart-19697b29-6a9d-47ed-9f28-04d2399a407c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858848263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2858848263
Directory	/workspace/11.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/11.rv_timer_disabled.4102220446
Short name	T454
Test name
Test status
Simulation time	358212668348 ps
CPU time	142.06 seconds
Started	Jan 07 12:40:40 PM PST 24
Finished	Jan 07 12:44:25 PM PST 24
Peak memory	182328 kb
Host	smart-60adf0ac-a61e-4725-9fc7-3a0e418be17e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102220446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4102220446
Directory	/workspace/11.rv_timer_disabled/latest

Test location	/workspace/coverage/default/11.rv_timer_random.1720772214
Short name	T288
Test name
Test status
Simulation time	126657383052 ps
CPU time	1511.42 seconds
Started	Jan 07 12:42:38 PM PST 24
Finished	Jan 07 01:09:06 PM PST 24
Peak memory	190624 kb
Host	smart-5698f5d8-c8b7-4e22-81d7-c9b276de963b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720772214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1720772214
Directory	/workspace/11.rv_timer_random/latest

Test location	/workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.2944976802
Short name	T65
Test name
Test status
Simulation time	177105601764 ps
CPU time	892.84 seconds
Started	Jan 07 12:39:26 PM PST 24
Finished	Jan 07 12:55:48 PM PST 24
Peak memory	210780 kb
Host	smart-7dc14526-ab0b-4a0b-9330-c09053c9670f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944976802 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.2944976802
Directory	/workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/112.rv_timer_random.3943660102
Short name	T122
Test name
Test status
Simulation time	86076003523 ps
CPU time	168.57 seconds
Started	Jan 07 12:39:27 PM PST 24
Finished	Jan 07 12:43:53 PM PST 24
Peak memory	191036 kb
Host	smart-e4f276a4-508a-48ad-ac3e-763a4dd286f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943660102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3943660102
Directory	/workspace/112.rv_timer_random/latest

Test location	/workspace/coverage/default/114.rv_timer_random.3032579290
Short name	T278
Test name
Test status
Simulation time	46066252714 ps
CPU time	77.26 seconds
Started	Jan 07 12:39:32 PM PST 24
Finished	Jan 07 12:42:21 PM PST 24
Peak memory	191172 kb
Host	smart-64bc21e8-4183-4000-8ee4-7213e5738bd9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032579290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3032579290
Directory	/workspace/114.rv_timer_random/latest

Test location	/workspace/coverage/default/117.rv_timer_random.1011772034
Short name	T265
Test name
Test status
Simulation time	363899844948 ps
CPU time	211.46 seconds
Started	Jan 07 12:39:26 PM PST 24
Finished	Jan 07 12:44:23 PM PST 24
Peak memory	191092 kb
Host	smart-7cf44b11-efd9-4dd7-b130-9535e9838d12
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011772034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1011772034
Directory	/workspace/117.rv_timer_random/latest

Test location	/workspace/coverage/default/118.rv_timer_random.500258651
Short name	T189
Test name
Test status
Simulation time	80578679843 ps
CPU time	233.95 seconds
Started	Jan 07 12:40:02 PM PST 24
Finished	Jan 07 12:45:39 PM PST 24
Peak memory	191012 kb
Host	smart-cc7fe679-c302-4993-a61d-40ec7c01c728
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500258651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.500258651
Directory	/workspace/118.rv_timer_random/latest

Test location	/workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3762794106
Short name	T170
Test name
Test status
Simulation time	194534471103 ps
CPU time	340.75 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:47:07 PM PST 24
Peak memory	182824 kb
Host	smart-9a032371-1527-4664-a311-1d8b80eb8c70
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762794106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.3762794106
Directory	/workspace/12.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/12.rv_timer_random.143925736
Short name	T260
Test name
Test status
Simulation time	395059310215 ps
CPU time	355.42 seconds
Started	Jan 07 12:39:45 PM PST 24
Finished	Jan 07 12:46:56 PM PST 24
Peak memory	191264 kb
Host	smart-84364b40-0cf1-4e8d-affe-fe9f01c71b5a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143925736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.143925736
Directory	/workspace/12.rv_timer_random/latest

Test location	/workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3349270334
Short name	T271
Test name
Test status
Simulation time	122351186223 ps
CPU time	877.69 seconds
Started	Jan 07 12:39:55 PM PST 24
Finished	Jan 07 12:55:57 PM PST 24
Peak memory	205696 kb
Host	smart-e76c8c0e-ca6c-48a2-a0fc-47eb7628a0e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349270334 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3349270334
Directory	/workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/123.rv_timer_random.3753503149
Short name	T154
Test name
Test status
Simulation time	237211021667 ps
CPU time	1066.28 seconds
Started	Jan 07 12:40:03 PM PST 24
Finished	Jan 07 12:59:15 PM PST 24
Peak memory	190972 kb
Host	smart-5c56360c-eede-48bd-9bde-cc564c25026e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753503149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3753503149
Directory	/workspace/123.rv_timer_random/latest

Test location	/workspace/coverage/default/127.rv_timer_random.3183336955
Short name	T99
Test name
Test status
Simulation time	434941850654 ps
CPU time	450.26 seconds
Started	Jan 07 12:40:06 PM PST 24
Finished	Jan 07 12:48:59 PM PST 24
Peak memory	190996 kb
Host	smart-b3ffd8ea-ce2f-40ce-93e6-11e178d71d1f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183336955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3183336955
Directory	/workspace/127.rv_timer_random/latest

Test location	/workspace/coverage/default/128.rv_timer_random.977643642
Short name	T215
Test name
Test status
Simulation time	123224547496 ps
CPU time	92.18 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:43:06 PM PST 24
Peak memory	190996 kb
Host	smart-475968dc-72a4-459c-b875-974dd1861761
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977643642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.977643642
Directory	/workspace/128.rv_timer_random/latest

Test location	/workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2326824940
Short name	T210
Test name
Test status
Simulation time	6134938600 ps
CPU time	10.6 seconds
Started	Jan 07 12:39:13 PM PST 24
Finished	Jan 07 12:41:05 PM PST 24
Peak memory	183052 kb
Host	smart-fb5d5a64-459b-4cb5-9cee-656e3de6b0eb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326824940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.2326824940
Directory	/workspace/13.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/13.rv_timer_disabled.1012513049
Short name	T391
Test name
Test status
Simulation time	273839462843 ps
CPU time	198.78 seconds
Started	Jan 07 12:39:03 PM PST 24
Finished	Jan 07 12:43:56 PM PST 24
Peak memory	182816 kb
Host	smart-8321e368-d903-436a-8a5a-f51aa7b91905
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012513049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1012513049
Directory	/workspace/13.rv_timer_disabled/latest

Test location	/workspace/coverage/default/13.rv_timer_random_reset.3066054555
Short name	T390
Test name
Test status
Simulation time	428747557 ps
CPU time	2.4 seconds
Started	Jan 07 12:40:07 PM PST 24
Finished	Jan 07 12:41:17 PM PST 24
Peak memory	182352 kb
Host	smart-5210b7f2-101c-430c-aa05-404371967250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066054555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3066054555
Directory	/workspace/13.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/13.rv_timer_stress_all.177419414
Short name	T399
Test name
Test status
Simulation time	140021403747 ps
CPU time	204.72 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 12:44:04 PM PST 24
Peak memory	182804 kb
Host	smart-2facf8fe-c1cc-40a6-859c-ba0343fde812
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177419414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all. 177419414
Directory	/workspace/13.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.465456386
Short name	T80
Test name
Test status
Simulation time	81581150674 ps
CPU time	215.77 seconds
Started	Jan 07 12:39:41 PM PST 24
Finished	Jan 07 12:45:10 PM PST 24
Peak memory	205716 kb
Host	smart-07dda84a-f533-410b-a427-f48d9e75aa38
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465456386 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.465456386
Directory	/workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/130.rv_timer_random.4249657527
Short name	T282
Test name
Test status
Simulation time	1004361183710 ps
CPU time	1530.45 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 01:06:32 PM PST 24
Peak memory	190952 kb
Host	smart-a5dab7a3-72a6-4829-bb60-ddd7087f302e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249657527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4249657527
Directory	/workspace/130.rv_timer_random/latest

Test location	/workspace/coverage/default/134.rv_timer_random.1283670850
Short name	T146
Test name
Test status
Simulation time	265617928811 ps
CPU time	317.88 seconds
Started	Jan 07 12:40:19 PM PST 24
Finished	Jan 07 12:46:43 PM PST 24
Peak memory	191032 kb
Host	smart-5af4486f-2414-4944-b770-d6e70e569f5c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283670850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1283670850
Directory	/workspace/134.rv_timer_random/latest

Test location	/workspace/coverage/default/135.rv_timer_random.2455775663
Short name	T169
Test name
Test status
Simulation time	79591173325 ps
CPU time	215.2 seconds
Started	Jan 07 12:39:16 PM PST 24
Finished	Jan 07 12:44:30 PM PST 24
Peak memory	191044 kb
Host	smart-609e2be1-a72c-4702-9563-f778c74d2810
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455775663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2455775663
Directory	/workspace/135.rv_timer_random/latest

Test location	/workspace/coverage/default/136.rv_timer_random.3233993788
Short name	T94
Test name
Test status
Simulation time	265508853386 ps
CPU time	136.02 seconds
Started	Jan 07 12:40:24 PM PST 24
Finished	Jan 07 12:43:44 PM PST 24
Peak memory	193508 kb
Host	smart-b52067dc-2658-4240-b056-0d424333faf8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233993788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3233993788
Directory	/workspace/136.rv_timer_random/latest

Test location	/workspace/coverage/default/137.rv_timer_random.3895710154
Short name	T336
Test name
Test status
Simulation time	491703937448 ps
CPU time	371.83 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:47:38 PM PST 24
Peak memory	182784 kb
Host	smart-39b87f30-6c16-4757-ba14-258aafa780ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895710154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3895710154
Directory	/workspace/137.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_disabled.3703193461
Short name	T34
Test name
Test status
Simulation time	56424296136 ps
CPU time	76.63 seconds
Started	Jan 07 12:38:52 PM PST 24
Finished	Jan 07 12:41:43 PM PST 24
Peak memory	182816 kb
Host	smart-96abad02-ea9a-494a-8a51-95f627ff3e29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703193461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3703193461
Directory	/workspace/14.rv_timer_disabled/latest

Test location	/workspace/coverage/default/14.rv_timer_random.3197022266
Short name	T106
Test name
Test status
Simulation time	84745582773 ps
CPU time	538.24 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:49:28 PM PST 24
Peak memory	190984 kb
Host	smart-2ca3ba39-f856-488a-811c-5c680c389ed9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197022266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3197022266
Directory	/workspace/14.rv_timer_random/latest

Test location	/workspace/coverage/default/14.rv_timer_random_reset.4259088857
Short name	T411
Test name
Test status
Simulation time	63804635 ps
CPU time	0.59 seconds
Started	Jan 07 12:39:11 PM PST 24
Finished	Jan 07 12:40:27 PM PST 24
Peak memory	182240 kb
Host	smart-3df54b91-494a-4818-94f8-83ea6a09729e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259088857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4259088857
Directory	/workspace/14.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.2148890147
Short name	T394
Test name
Test status
Simulation time	171924639020 ps
CPU time	632.73 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:51:19 PM PST 24
Peak memory	207708 kb
Host	smart-465cbe1b-c43b-4a53-b10f-86a8fd430abf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148890147 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.2148890147
Directory	/workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/140.rv_timer_random.3271295829
Short name	T323
Test name
Test status
Simulation time	75460073249 ps
CPU time	705.26 seconds
Started	Jan 07 12:39:55 PM PST 24
Finished	Jan 07 12:52:50 PM PST 24
Peak memory	182932 kb
Host	smart-2821a27e-281e-4ef9-b5f1-0aaad2a2e1c1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271295829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3271295829
Directory	/workspace/140.rv_timer_random/latest

Test location	/workspace/coverage/default/141.rv_timer_random.1516316640
Short name	T171
Test name
Test status
Simulation time	188999733762 ps
CPU time	103.64 seconds
Started	Jan 07 12:39:32 PM PST 24
Finished	Jan 07 12:42:38 PM PST 24
Peak memory	182904 kb
Host	smart-a2759e3b-5187-42dc-9b74-ca27f22fccfa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516316640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1516316640
Directory	/workspace/141.rv_timer_random/latest

Test location	/workspace/coverage/default/143.rv_timer_random.2252061587
Short name	T199
Test name
Test status
Simulation time	193151374921 ps
CPU time	473.83 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:49:20 PM PST 24
Peak memory	191028 kb
Host	smart-4bf52c98-075c-4688-9e83-ca23914959c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252061587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2252061587
Directory	/workspace/143.rv_timer_random/latest

Test location	/workspace/coverage/default/145.rv_timer_random.1505558897
Short name	T255
Test name
Test status
Simulation time	132366822235 ps
CPU time	118.52 seconds
Started	Jan 07 12:39:40 PM PST 24
Finished	Jan 07 12:43:13 PM PST 24
Peak memory	190972 kb
Host	smart-d4596696-ff84-499d-847a-eaf755621b4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505558897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1505558897
Directory	/workspace/145.rv_timer_random/latest

Test location	/workspace/coverage/default/147.rv_timer_random.3091182474
Short name	T333
Test name
Test status
Simulation time	37492657213 ps
CPU time	464.52 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:48:37 PM PST 24
Peak memory	182932 kb
Host	smart-79d86fca-bd7c-4bad-a34e-25c94e4a8d1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091182474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3091182474
Directory	/workspace/147.rv_timer_random/latest

Test location	/workspace/coverage/default/148.rv_timer_random.2371891452
Short name	T415
Test name
Test status
Simulation time	59798321082 ps
CPU time	593.76 seconds
Started	Jan 07 12:40:21 PM PST 24
Finished	Jan 07 12:52:02 PM PST 24
Peak memory	182888 kb
Host	smart-8a685e43-4ab8-4edd-9423-9806003d764f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371891452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2371891452
Directory	/workspace/148.rv_timer_random/latest

Test location	/workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4263178131
Short name	T160
Test name
Test status
Simulation time	546591492642 ps
CPU time	992.82 seconds
Started	Jan 07 12:38:44 PM PST 24
Finished	Jan 07 12:56:36 PM PST 24
Peak memory	182736 kb
Host	smart-d6c80aaa-a594-4697-9a4a-f0d35daa0afa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263178131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.4263178131
Directory	/workspace/15.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/15.rv_timer_disabled.2496578260
Short name	T417
Test name
Test status
Simulation time	137801171826 ps
CPU time	218.52 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 12:44:08 PM PST 24
Peak memory	182948 kb
Host	smart-263b615d-a3ac-4b7e-8899-b8141df7f1c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496578260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2496578260
Directory	/workspace/15.rv_timer_disabled/latest

Test location	/workspace/coverage/default/15.rv_timer_random.2953206818
Short name	T329
Test name
Test status
Simulation time	45646382569 ps
CPU time	20.12 seconds
Started	Jan 07 12:38:46 PM PST 24
Finished	Jan 07 12:40:18 PM PST 24
Peak memory	182672 kb
Host	smart-9af62a65-6a71-4e69-a7a1-e2309ead468b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953206818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2953206818
Directory	/workspace/15.rv_timer_random/latest

Test location	/workspace/coverage/default/15.rv_timer_random_reset.2058944139
Short name	T409
Test name
Test status
Simulation time	37256822998 ps
CPU time	68.91 seconds
Started	Jan 07 12:38:55 PM PST 24
Finished	Jan 07 12:41:35 PM PST 24
Peak memory	182708 kb
Host	smart-a7d24fc0-d48c-4fa8-b845-4e9f05ae1aae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058944139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2058944139
Directory	/workspace/15.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.4131050748
Short name	T81
Test name
Test status
Simulation time	104813549145 ps
CPU time	1059.43 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:58:01 PM PST 24
Peak memory	206748 kb
Host	smart-58e2ff3f-00ca-4ad7-a472-6f5ee34a1b10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131050748 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.4131050748
Directory	/workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/150.rv_timer_random.2004898466
Short name	T12
Test name
Test status
Simulation time	836436346365 ps
CPU time	510.61 seconds
Started	Jan 07 12:40:11 PM PST 24
Finished	Jan 07 12:49:54 PM PST 24
Peak memory	191092 kb
Host	smart-2acf605a-fe86-4405-aa6f-0e78585a6219
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004898466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2004898466
Directory	/workspace/150.rv_timer_random/latest

Test location	/workspace/coverage/default/151.rv_timer_random.4066492669
Short name	T236
Test name
Test status
Simulation time	135591590705 ps
CPU time	60.04 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 12:41:48 PM PST 24
Peak memory	191168 kb
Host	smart-50641d4d-7d62-482e-9326-b581010b1af9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066492669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4066492669
Directory	/workspace/151.rv_timer_random/latest

Test location	/workspace/coverage/default/153.rv_timer_random.1498408785
Short name	T459
Test name
Test status
Simulation time	187952449398 ps
CPU time	756.73 seconds
Started	Jan 07 12:40:08 PM PST 24
Finished	Jan 07 12:54:12 PM PST 24
Peak memory	182708 kb
Host	smart-133f7e03-09d4-4a4d-8836-adf317774812
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498408785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1498408785
Directory	/workspace/153.rv_timer_random/latest

Test location	/workspace/coverage/default/154.rv_timer_random.525548329
Short name	T266
Test name
Test status
Simulation time	26280992372 ps
CPU time	153.42 seconds
Started	Jan 07 12:39:28 PM PST 24
Finished	Jan 07 12:43:31 PM PST 24
Peak memory	190940 kb
Host	smart-2a731dbf-b7e2-406f-a1c2-2741396fec19
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525548329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.525548329
Directory	/workspace/154.rv_timer_random/latest

Test location	/workspace/coverage/default/156.rv_timer_random.2657564740
Short name	T309
Test name
Test status
Simulation time	598226854823 ps
CPU time	304.82 seconds
Started	Jan 07 12:40:12 PM PST 24
Finished	Jan 07 12:46:24 PM PST 24
Peak memory	193060 kb
Host	smart-756a3e55-e725-420d-becd-883951a210bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657564740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2657564740
Directory	/workspace/156.rv_timer_random/latest

Test location	/workspace/coverage/default/158.rv_timer_random.4210302977
Short name	T104
Test name
Test status
Simulation time	92376377395 ps
CPU time	1060.83 seconds
Started	Jan 07 12:40:32 PM PST 24
Finished	Jan 07 12:59:34 PM PST 24
Peak memory	191124 kb
Host	smart-6edd6e6f-5b7c-4332-8976-72f9b3181c60
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210302977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4210302977
Directory	/workspace/158.rv_timer_random/latest

Test location	/workspace/coverage/default/159.rv_timer_random.1008785784
Short name	T193
Test name
Test status
Simulation time	348060036754 ps
CPU time	508.22 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:49:49 PM PST 24
Peak memory	191136 kb
Host	smart-39a72c95-3672-465d-8b91-2f4f3c7ad84d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008785784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1008785784
Directory	/workspace/159.rv_timer_random/latest

Test location	/workspace/coverage/default/16.rv_timer_disabled.320684648
Short name	T414
Test name
Test status
Simulation time	264134705377 ps
CPU time	208.17 seconds
Started	Jan 07 12:39:14 PM PST 24
Finished	Jan 07 12:44:03 PM PST 24
Peak memory	182880 kb
Host	smart-569821ea-c18a-4553-9518-718057b4f38a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320684648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.320684648
Directory	/workspace/16.rv_timer_disabled/latest

Test location	/workspace/coverage/default/160.rv_timer_random.1166558218
Short name	T310
Test name
Test status
Simulation time	28675473285 ps
CPU time	25.17 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 12:41:22 PM PST 24
Peak memory	182648 kb
Host	smart-1619f321-5343-4ac5-99f5-437107e31e09
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166558218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1166558218
Directory	/workspace/160.rv_timer_random/latest

Test location	/workspace/coverage/default/162.rv_timer_random.2460399749
Short name	T151
Test name
Test status
Simulation time	32683538854 ps
CPU time	53.95 seconds
Started	Jan 07 12:40:31 PM PST 24
Finished	Jan 07 12:42:38 PM PST 24
Peak memory	182808 kb
Host	smart-18cbb089-8285-4341-a1f0-bad7ee705e89
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460399749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2460399749
Directory	/workspace/162.rv_timer_random/latest

Test location	/workspace/coverage/default/165.rv_timer_random.3987412404
Short name	T116
Test name
Test status
Simulation time	1884332710 ps
CPU time	3.59 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:41:18 PM PST 24
Peak memory	182576 kb
Host	smart-7d412c7b-8127-42c8-8b82-0af64e853037
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987412404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3987412404
Directory	/workspace/165.rv_timer_random/latest

Test location	/workspace/coverage/default/168.rv_timer_random.2414747232
Short name	T258
Test name
Test status
Simulation time	38951435151 ps
CPU time	110.18 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:43:33 PM PST 24
Peak memory	182812 kb
Host	smart-d01749ad-9579-458d-9899-bdba326f7fc0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414747232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2414747232
Directory	/workspace/168.rv_timer_random/latest

Test location	/workspace/coverage/default/169.rv_timer_random.747408371
Short name	T302
Test name
Test status
Simulation time	146707098754 ps
CPU time	135.76 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:43:58 PM PST 24
Peak memory	190968 kb
Host	smart-30775b49-fc39-46df-88fa-8c903442a9fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747408371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.747408371
Directory	/workspace/169.rv_timer_random/latest

Test location	/workspace/coverage/default/17.rv_timer_disabled.3373088907
Short name	T447
Test name
Test status
Simulation time	216735855624 ps
CPU time	52.51 seconds
Started	Jan 07 12:38:58 PM PST 24
Finished	Jan 07 12:41:22 PM PST 24
Peak memory	182836 kb
Host	smart-a17eeceb-6259-41f9-8d10-91b76c7a36e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373088907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3373088907
Directory	/workspace/17.rv_timer_disabled/latest

Test location	/workspace/coverage/default/17.rv_timer_random.1285619230
Short name	T448
Test name
Test status
Simulation time	615739039840 ps
CPU time	803.5 seconds
Started	Jan 07 12:39:00 PM PST 24
Finished	Jan 07 12:53:42 PM PST 24
Peak memory	193340 kb
Host	smart-25f677b6-3e55-4d6b-80fb-55d68a3cc3c2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285619230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1285619230
Directory	/workspace/17.rv_timer_random/latest

Test location	/workspace/coverage/default/17.rv_timer_random_reset.2915007976
Short name	T219
Test name
Test status
Simulation time	516730822921 ps
CPU time	126.82 seconds
Started	Jan 07 12:39:38 PM PST 24
Finished	Jan 07 12:43:04 PM PST 24
Peak memory	182920 kb
Host	smart-5aa95a54-fb88-4a0c-a67b-d6fbd73c237d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915007976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2915007976
Directory	/workspace/17.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/170.rv_timer_random.2605314795
Short name	T455
Test name
Test status
Simulation time	165367720991 ps
CPU time	432.08 seconds
Started	Jan 07 12:40:08 PM PST 24
Finished	Jan 07 12:48:42 PM PST 24
Peak memory	191140 kb
Host	smart-19b35ea9-d384-4734-92fb-6f473e208329
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605314795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2605314795
Directory	/workspace/170.rv_timer_random/latest

Test location	/workspace/coverage/default/172.rv_timer_random.2502886665
Short name	T252
Test name
Test status
Simulation time	684448308547 ps
CPU time	882.01 seconds
Started	Jan 07 12:39:59 PM PST 24
Finished	Jan 07 12:55:53 PM PST 24
Peak memory	191068 kb
Host	smart-79e4b81f-06f9-4ea1-8318-c099a7f0da65
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502886665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2502886665
Directory	/workspace/172.rv_timer_random/latest

Test location	/workspace/coverage/default/175.rv_timer_random.4092972862
Short name	T198
Test name
Test status
Simulation time	636954409263 ps
CPU time	533.32 seconds
Started	Jan 07 12:39:57 PM PST 24
Finished	Jan 07 12:50:15 PM PST 24
Peak memory	191044 kb
Host	smart-fda287f4-2cd4-4e4c-be92-0eb73093e885
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092972862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4092972862
Directory	/workspace/175.rv_timer_random/latest

Test location	/workspace/coverage/default/177.rv_timer_random.3601938223
Short name	T109
Test name
Test status
Simulation time	468960426133 ps
CPU time	1900.08 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 01:12:31 PM PST 24
Peak memory	193220 kb
Host	smart-dd0ffa9a-7110-480e-aee8-026d7dcb7b36
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601938223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3601938223
Directory	/workspace/177.rv_timer_random/latest

Test location	/workspace/coverage/default/178.rv_timer_random.2570546060
Short name	T152
Test name
Test status
Simulation time	973462861231 ps
CPU time	1440.33 seconds
Started	Jan 07 12:39:38 PM PST 24
Finished	Jan 07 01:05:04 PM PST 24
Peak memory	191016 kb
Host	smart-67469bfd-58bc-45a5-abd1-76504ace1866
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570546060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2570546060
Directory	/workspace/178.rv_timer_random/latest

Test location	/workspace/coverage/default/179.rv_timer_random.1485000235
Short name	T149
Test name
Test status
Simulation time	90532994770 ps
CPU time	123.47 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:42:48 PM PST 24
Peak memory	193664 kb
Host	smart-076caf7d-d995-44de-b327-de46730c5e76
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485000235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1485000235
Directory	/workspace/179.rv_timer_random/latest

Test location	/workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2435058658
Short name	T320
Test name
Test status
Simulation time	282577222065 ps
CPU time	518.24 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 12:49:01 PM PST 24
Peak memory	182812 kb
Host	smart-492e3097-815d-409b-846b-6230a51d44e5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435058658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2435058658
Directory	/workspace/18.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/180.rv_timer_random.3326887843
Short name	T185
Test name
Test status
Simulation time	280442739775 ps
CPU time	1120.16 seconds
Started	Jan 07 12:40:09 PM PST 24
Finished	Jan 07 01:00:10 PM PST 24
Peak memory	191164 kb
Host	smart-bbc94242-ecd4-42b7-a2a4-30c137735365
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326887843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3326887843
Directory	/workspace/180.rv_timer_random/latest

Test location	/workspace/coverage/default/183.rv_timer_random.2001420785
Short name	T316
Test name
Test status
Simulation time	35960714009 ps
CPU time	78.07 seconds
Started	Jan 07 12:39:38 PM PST 24
Finished	Jan 07 12:42:15 PM PST 24
Peak memory	182828 kb
Host	smart-b759f79a-08ae-47ea-baff-47dc947e496d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001420785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2001420785
Directory	/workspace/183.rv_timer_random/latest

Test location	/workspace/coverage/default/185.rv_timer_random.2904563539
Short name	T184
Test name
Test status
Simulation time	900955792672 ps
CPU time	1100.93 seconds
Started	Jan 07 12:40:29 PM PST 24
Finished	Jan 07 01:00:11 PM PST 24
Peak memory	191024 kb
Host	smart-bf5fa60d-e124-494c-bb7c-53ccacafc4c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904563539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2904563539
Directory	/workspace/185.rv_timer_random/latest

Test location	/workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3508310567
Short name	T136
Test name
Test status
Simulation time	175013673534 ps
CPU time	94.77 seconds
Started	Jan 07 12:39:41 PM PST 24
Finished	Jan 07 12:43:08 PM PST 24
Peak memory	182880 kb
Host	smart-b2786273-8665-4fb8-91f4-c5525a02f2c7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508310567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3508310567
Directory	/workspace/19.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/19.rv_timer_disabled.3917827372
Short name	T404
Test name
Test status
Simulation time	242861263986 ps
CPU time	134.79 seconds
Started	Jan 07 12:43:04 PM PST 24
Finished	Jan 07 12:47:13 PM PST 24
Peak memory	182496 kb
Host	smart-22ac73e1-6340-4ec8-938f-531943a7c91b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917827372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3917827372
Directory	/workspace/19.rv_timer_disabled/latest

Test location	/workspace/coverage/default/192.rv_timer_random.2152412632
Short name	T158
Test name
Test status
Simulation time	128546292819 ps
CPU time	254.15 seconds
Started	Jan 07 12:40:16 PM PST 24
Finished	Jan 07 12:45:43 PM PST 24
Peak memory	193312 kb
Host	smart-1dcd58da-8531-455d-8f96-51375e5c1cec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152412632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2152412632
Directory	/workspace/192.rv_timer_random/latest

Test location	/workspace/coverage/default/193.rv_timer_random.285764578
Short name	T268
Test name
Test status
Simulation time	48979142089 ps
CPU time	234.32 seconds
Started	Jan 07 12:40:10 PM PST 24
Finished	Jan 07 12:46:06 PM PST 24
Peak memory	191012 kb
Host	smart-9dbde841-c920-4210-8836-5e66244dd03d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285764578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.285764578
Directory	/workspace/193.rv_timer_random/latest

Test location	/workspace/coverage/default/194.rv_timer_random.3027962570
Short name	T247
Test name
Test status
Simulation time	184715218131 ps
CPU time	169 seconds
Started	Jan 07 12:39:41 PM PST 24
Finished	Jan 07 12:44:23 PM PST 24
Peak memory	191080 kb
Host	smart-713d103b-df60-4915-9734-0a3f1a43562b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027962570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3027962570
Directory	/workspace/194.rv_timer_random/latest

Test location	/workspace/coverage/default/195.rv_timer_random.3627695800
Short name	T234
Test name
Test status
Simulation time	432033723885 ps
CPU time	491.47 seconds
Started	Jan 07 12:39:44 PM PST 24
Finished	Jan 07 12:49:39 PM PST 24
Peak memory	191188 kb
Host	smart-0d4f15c9-a416-4684-b88a-f973fbd0edbf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627695800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3627695800
Directory	/workspace/195.rv_timer_random/latest

Test location	/workspace/coverage/default/196.rv_timer_random.2830687705
Short name	T274
Test name
Test status
Simulation time	380664361022 ps
CPU time	351.21 seconds
Started	Jan 07 12:40:30 PM PST 24
Finished	Jan 07 12:47:55 PM PST 24
Peak memory	191040 kb
Host	smart-26bd5b87-aed8-4266-bcd7-04d4778171fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830687705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2830687705
Directory	/workspace/196.rv_timer_random/latest

Test location	/workspace/coverage/default/198.rv_timer_random.2361429701
Short name	T291
Test name
Test status
Simulation time	93769833028 ps
CPU time	171.67 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:43:57 PM PST 24
Peak memory	191028 kb
Host	smart-007e13c5-abd3-43ae-9eca-122b93d2331c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361429701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2361429701
Directory	/workspace/198.rv_timer_random/latest

Test location	/workspace/coverage/default/199.rv_timer_random.870428098
Short name	T201
Test name
Test status
Simulation time	275001593320 ps
CPU time	264.21 seconds
Started	Jan 07 12:39:45 PM PST 24
Finished	Jan 07 12:45:30 PM PST 24
Peak memory	190996 kb
Host	smart-3350e11a-9c95-4100-a4a0-1c22ee8ee877
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870428098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.870428098
Directory	/workspace/199.rv_timer_random/latest

Test location	/workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1167281043
Short name	T449
Test name
Test status
Simulation time	192257331648 ps
CPU time	180.91 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 12:43:33 PM PST 24
Peak memory	182704 kb
Host	smart-d8b4a9ec-4108-446b-a981-084437f2a6e9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167281043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.1167281043
Directory	/workspace/2.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/2.rv_timer_disabled.1883087269
Short name	T35
Test name
Test status
Simulation time	171420412973 ps
CPU time	87.47 seconds
Started	Jan 07 12:38:52 PM PST 24
Finished	Jan 07 12:41:26 PM PST 24
Peak memory	182872 kb
Host	smart-5c1be5d6-54ad-4ff8-b4c8-519b34b5509b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883087269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1883087269
Directory	/workspace/2.rv_timer_disabled/latest

Test location	/workspace/coverage/default/2.rv_timer_sec_cm.646861818
Short name	T26
Test name
Test status
Simulation time	110854699 ps
CPU time	0.8 seconds
Started	Jan 07 12:38:30 PM PST 24
Finished	Jan 07 12:39:49 PM PST 24
Peak memory	212776 kb
Host	smart-59d3a94f-d48e-4db3-8b0b-11927c7c10ee
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646861818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.646861818
Directory	/workspace/2.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2626331425
Short name	T412
Test name
Test status
Simulation time	29201611896 ps
CPU time	186.31 seconds
Started	Jan 07 12:39:38 PM PST 24
Finished	Jan 07 12:44:03 PM PST 24
Peak memory	197416 kb
Host	smart-b5c7db23-4a1f-4496-8be4-0402ac6d69e9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626331425 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2626331425
Directory	/workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.rv_timer_cfg_update_on_fly.4131371630
Short name	T137
Test name
Test status
Simulation time	6481750822 ps
CPU time	12 seconds
Started	Jan 07 12:43:06 PM PST 24
Finished	Jan 07 12:44:24 PM PST 24
Peak memory	182416 kb
Host	smart-c544a3d2-5fee-4719-8d08-b1af28670373
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131371630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.4131371630
Directory	/workspace/20.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/20.rv_timer_disabled.698010446
Short name	T392
Test name
Test status
Simulation time	391320142263 ps
CPU time	80.43 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:41:59 PM PST 24
Peak memory	182960 kb
Host	smart-cd4e3858-ba08-4a72-8f70-c5ba8f504a9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698010446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.698010446
Directory	/workspace/20.rv_timer_disabled/latest

Test location	/workspace/coverage/default/20.rv_timer_random.486530023
Short name	T103
Test name
Test status
Simulation time	75485590233 ps
CPU time	153.67 seconds
Started	Jan 07 12:39:19 PM PST 24
Finished	Jan 07 12:43:26 PM PST 24
Peak memory	191032 kb
Host	smart-e08ceed2-7d0d-41db-a411-73a136df872c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486530023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.486530023
Directory	/workspace/20.rv_timer_random/latest

Test location	/workspace/coverage/default/20.rv_timer_random_reset.844181517
Short name	T31
Test name
Test status
Simulation time	24175555757 ps
CPU time	36.73 seconds
Started	Jan 07 12:41:33 PM PST 24
Finished	Jan 07 12:43:20 PM PST 24
Peak memory	190600 kb
Host	smart-0d53c244-565c-47b9-b121-65e0f3ad6f57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844181517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.844181517
Directory	/workspace/20.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3901093900
Short name	T213
Test name
Test status
Simulation time	52412450183 ps
CPU time	243.42 seconds
Started	Jan 07 12:38:42 PM PST 24
Finished	Jan 07 12:44:03 PM PST 24
Peak memory	197496 kb
Host	smart-ae6de2df-eb54-4e52-9823-e4b666222148
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901093900 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3901093900
Directory	/workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.rv_timer_cfg_update_on_fly.422432077
Short name	T125
Test name
Test status
Simulation time	292819438147 ps
CPU time	165.98 seconds
Started	Jan 07 12:38:56 PM PST 24
Finished	Jan 07 12:43:05 PM PST 24
Peak memory	182924 kb
Host	smart-2d5dac8b-b219-48f4-8aa6-041e96041ce2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422432077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.rv_timer_cfg_update_on_fly.422432077
Directory	/workspace/21.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/21.rv_timer_disabled.1694587414
Short name	T450
Test name
Test status
Simulation time	228552975679 ps
CPU time	95.83 seconds
Started	Jan 07 12:41:00 PM PST 24
Finished	Jan 07 12:44:01 PM PST 24
Peak memory	182292 kb
Host	smart-110cd8fc-5ccc-4ce9-b679-e275c4953be9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694587414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1694587414
Directory	/workspace/21.rv_timer_disabled/latest

Test location	/workspace/coverage/default/21.rv_timer_random.1869188942
Short name	T335
Test name
Test status
Simulation time	203009216237 ps
CPU time	263 seconds
Started	Jan 07 12:39:28 PM PST 24
Finished	Jan 07 12:45:20 PM PST 24
Peak memory	193564 kb
Host	smart-d31f4c6a-87e9-4974-aa6e-523ce50a3a01
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869188942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1869188942
Directory	/workspace/21.rv_timer_random/latest

Test location	/workspace/coverage/default/21.rv_timer_random_reset.896923766
Short name	T421
Test name
Test status
Simulation time	2034398711 ps
CPU time	1.13 seconds
Started	Jan 07 12:39:43 PM PST 24
Finished	Jan 07 12:41:00 PM PST 24
Peak memory	182708 kb
Host	smart-8445e205-972c-4c02-94d3-b75f594426c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896923766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.896923766
Directory	/workspace/21.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.282393708
Short name	T397
Test name
Test status
Simulation time	127434807967 ps
CPU time	246.62 seconds
Started	Jan 07 12:40:07 PM PST 24
Finished	Jan 07 12:45:18 PM PST 24
Peak memory	203876 kb
Host	smart-3c879866-d7d6-4a7d-a934-d22d1b51cea2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282393708 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.282393708
Directory	/workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.rv_timer_disabled.925101523
Short name	T430
Test name
Test status
Simulation time	450382416385 ps
CPU time	188.92 seconds
Started	Jan 07 12:40:55 PM PST 24
Finished	Jan 07 12:45:44 PM PST 24
Peak memory	182324 kb
Host	smart-b8bda6b1-ed1c-4f97-84d4-5de281eb0a0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925101523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.925101523
Directory	/workspace/22.rv_timer_disabled/latest

Test location	/workspace/coverage/default/22.rv_timer_random.2689695369
Short name	T197
Test name
Test status
Simulation time	299607761967 ps
CPU time	444.91 seconds
Started	Jan 07 12:39:58 PM PST 24
Finished	Jan 07 12:48:32 PM PST 24
Peak memory	190464 kb
Host	smart-0f7d42df-ccae-4c0a-af9a-6c1cff648775
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689695369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2689695369
Directory	/workspace/22.rv_timer_random/latest

Test location	/workspace/coverage/default/22.rv_timer_stress_all.3695790479
Short name	T308
Test name
Test status
Simulation time	306954218209 ps
CPU time	96.71 seconds
Started	Jan 07 12:38:44 PM PST 24
Finished	Jan 07 12:42:13 PM PST 24
Peak memory	182888 kb
Host	smart-e9518475-56a2-40bc-b060-bd84b3a20c97
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695790479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .3695790479
Directory	/workspace/22.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.982469264
Short name	T440
Test name
Test status
Simulation time	92745070501 ps
CPU time	196.45 seconds
Started	Jan 07 12:38:59 PM PST 24
Finished	Jan 07 12:43:52 PM PST 24
Peak memory	197532 kb
Host	smart-0a34d13b-c132-4ca8-8e59-00e6cc7b1f9d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982469264 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.982469264
Directory	/workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1321912827
Short name	T214
Test name
Test status
Simulation time	90356884352 ps
CPU time	154.6 seconds
Started	Jan 07 12:38:52 PM PST 24
Finished	Jan 07 12:42:33 PM PST 24
Peak memory	182832 kb
Host	smart-cf90ea62-da8d-4f76-9e88-3c0abc6418be
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321912827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1321912827
Directory	/workspace/23.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/23.rv_timer_disabled.3641402714
Short name	T398
Test name
Test status
Simulation time	100635054470 ps
CPU time	137.89 seconds
Started	Jan 07 12:38:37 PM PST 24
Finished	Jan 07 12:42:40 PM PST 24
Peak memory	182800 kb
Host	smart-ddd0d73d-0efd-4f98-859c-27265425605b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641402714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3641402714
Directory	/workspace/23.rv_timer_disabled/latest

Test location	/workspace/coverage/default/23.rv_timer_random.3036475441
Short name	T172
Test name
Test status
Simulation time	152048339384 ps
CPU time	471.74 seconds
Started	Jan 07 12:38:37 PM PST 24
Finished	Jan 07 12:47:48 PM PST 24
Peak memory	194996 kb
Host	smart-4b1dca9b-ffc9-4b9e-9842-fce0264dac48
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036475441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3036475441
Directory	/workspace/23.rv_timer_random/latest

Test location	/workspace/coverage/default/24.rv_timer_random_reset.209584562
Short name	T401
Test name
Test status
Simulation time	18158142474 ps
CPU time	29.86 seconds
Started	Jan 07 12:39:07 PM PST 24
Finished	Jan 07 12:42:12 PM PST 24
Peak memory	182840 kb
Host	smart-1e89c8d7-b87a-4e1c-b39f-34e7d0afc07c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209584562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.209584562
Directory	/workspace/24.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.722303488
Short name	T82
Test name
Test status
Simulation time	47300102725 ps
CPU time	345.12 seconds
Started	Jan 07 12:39:33 PM PST 24
Finished	Jan 07 12:46:41 PM PST 24
Peak memory	197548 kb
Host	smart-a7ba31b1-7ecf-4814-b23c-ff25aac76a53
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722303488 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.722303488
Directory	/workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.rv_timer_cfg_update_on_fly.648579080
Short name	T115
Test name
Test status
Simulation time	85079519169 ps
CPU time	31.38 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 12:40:58 PM PST 24
Peak memory	182768 kb
Host	smart-8e600882-a896-42e7-bc35-ab35704478af
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648579080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.rv_timer_cfg_update_on_fly.648579080
Directory	/workspace/25.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/25.rv_timer_disabled.2117106692
Short name	T426
Test name
Test status
Simulation time	32622607137 ps
CPU time	22.05 seconds
Started	Jan 07 12:39:11 PM PST 24
Finished	Jan 07 12:40:54 PM PST 24
Peak memory	182784 kb
Host	smart-0194aa9c-f18e-46a8-8d4d-6c05dc7ac852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117106692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2117106692
Directory	/workspace/25.rv_timer_disabled/latest

Test location	/workspace/coverage/default/26.rv_timer_disabled.2594887594
Short name	T386
Test name
Test status
Simulation time	102540843663 ps
CPU time	175.89 seconds
Started	Jan 07 12:39:01 PM PST 24
Finished	Jan 07 12:43:25 PM PST 24
Peak memory	182828 kb
Host	smart-c1e9a14e-98fd-45a8-bd38-271d09b199c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594887594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2594887594
Directory	/workspace/26.rv_timer_disabled/latest

Test location	/workspace/coverage/default/26.rv_timer_random.4071938532
Short name	T264
Test name
Test status
Simulation time	567140534811 ps
CPU time	690.19 seconds
Started	Jan 07 12:38:53 PM PST 24
Finished	Jan 07 12:51:54 PM PST 24
Peak memory	191088 kb
Host	smart-67c9589e-5883-4308-ae22-f4bb5693aba9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071938532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4071938532
Directory	/workspace/26.rv_timer_random/latest

Test location	/workspace/coverage/default/26.rv_timer_random_reset.1238345146
Short name	T457
Test name
Test status
Simulation time	88072472969 ps
CPU time	93.58 seconds
Started	Jan 07 12:42:12 PM PST 24
Finished	Jan 07 12:45:12 PM PST 24
Peak memory	181812 kb
Host	smart-b76dbadb-b295-4f26-88bc-be0c9b048220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238345146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1238345146
Directory	/workspace/26.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2989377208
Short name	T211
Test name
Test status
Simulation time	816218201481 ps
CPU time	1040.4 seconds
Started	Jan 07 12:39:59 PM PST 24
Finished	Jan 07 12:59:11 PM PST 24
Peak memory	211484 kb
Host	smart-8c94138d-23d9-4345-a9b0-d6a915318837
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989377208 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2989377208
Directory	/workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.rv_timer_cfg_update_on_fly.117545485
Short name	T220
Test name
Test status
Simulation time	264420741595 ps
CPU time	150.85 seconds
Started	Jan 07 12:42:55 PM PST 24
Finished	Jan 07 12:46:44 PM PST 24
Peak memory	182452 kb
Host	smart-b4a0f2d2-b176-4738-9a0f-b94c2f03314b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117545485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.rv_timer_cfg_update_on_fly.117545485
Directory	/workspace/27.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/27.rv_timer_disabled.2670760540
Short name	T423
Test name
Test status
Simulation time	36971292124 ps
CPU time	55.64 seconds
Started	Jan 07 12:39:00 PM PST 24
Finished	Jan 07 12:41:18 PM PST 24
Peak memory	182804 kb
Host	smart-da5f992a-dc38-4eb1-8322-d9c12f79f8f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670760540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2670760540
Directory	/workspace/27.rv_timer_disabled/latest

Test location	/workspace/coverage/default/27.rv_timer_random_reset.1585840059
Short name	T446
Test name
Test status
Simulation time	61220714148 ps
CPU time	60.98 seconds
Started	Jan 07 12:43:04 PM PST 24
Finished	Jan 07 12:45:25 PM PST 24
Peak memory	190660 kb
Host	smart-9be8b8c9-eea6-4ef6-9caf-cc8126120722
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585840059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1585840059
Directory	/workspace/27.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3542591078
Short name	T418
Test name
Test status
Simulation time	236844567482 ps
CPU time	502.56 seconds
Started	Jan 07 12:38:41 PM PST 24
Finished	Jan 07 12:48:27 PM PST 24
Peak memory	205724 kb
Host	smart-96e19941-289a-430a-bc9e-75acd5339c2f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542591078 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3542591078
Directory	/workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.rv_timer_disabled.1232907249
Short name	T451
Test name
Test status
Simulation time	528121869086 ps
CPU time	208.7 seconds
Started	Jan 07 12:39:39 PM PST 24
Finished	Jan 07 12:44:30 PM PST 24
Peak memory	182816 kb
Host	smart-678a5d0b-4cda-47ef-aa78-c5613c6bc160
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232907249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1232907249
Directory	/workspace/28.rv_timer_disabled/latest

Test location	/workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2208186644
Short name	T203
Test name
Test status
Simulation time	185410854544 ps
CPU time	450.16 seconds
Started	Jan 07 12:39:22 PM PST 24
Finished	Jan 07 12:48:25 PM PST 24
Peak memory	212932 kb
Host	smart-f4a07c99-bcb3-4d4b-9e59-02f8fbd5682f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208186644 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2208186644
Directory	/workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3474878007
Short name	T332
Test name
Test status
Simulation time	1680554604948 ps
CPU time	1428.25 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 01:04:28 PM PST 24
Peak memory	182856 kb
Host	smart-7bd7a539-ee7c-45d1-8778-6f2420e38630
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474878007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3474878007
Directory	/workspace/29.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/29.rv_timer_disabled.1578736835
Short name	T410
Test name
Test status
Simulation time	208582765211 ps
CPU time	79.94 seconds
Started	Jan 07 12:39:18 PM PST 24
Finished	Jan 07 12:41:54 PM PST 24
Peak memory	182832 kb
Host	smart-6533a8db-0eaa-4f1b-babf-6c8b2c6bcd05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578736835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1578736835
Directory	/workspace/29.rv_timer_disabled/latest

Test location	/workspace/coverage/default/29.rv_timer_random.205627260
Short name	T283
Test name
Test status
Simulation time	44754925468 ps
CPU time	37.27 seconds
Started	Jan 07 12:38:58 PM PST 24
Finished	Jan 07 12:41:06 PM PST 24
Peak memory	182876 kb
Host	smart-651e9a3a-2a5b-4701-9a62-32e286d08e34
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205627260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.205627260
Directory	/workspace/29.rv_timer_random/latest

Test location	/workspace/coverage/default/29.rv_timer_stress_all.2824100517
Short name	T439
Test name
Test status
Simulation time	28960225242 ps
CPU time	10.96 seconds
Started	Jan 07 12:39:39 PM PST 24
Finished	Jan 07 12:41:40 PM PST 24
Peak memory	182880 kb
Host	smart-dd693f67-c355-493a-bbb8-5ff2f7d666d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824100517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .2824100517
Directory	/workspace/29.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/3.rv_timer_disabled.640730325
Short name	T387
Test name
Test status
Simulation time	112235491360 ps
CPU time	67.59 seconds
Started	Jan 07 12:38:45 PM PST 24
Finished	Jan 07 12:41:34 PM PST 24
Peak memory	182864 kb
Host	smart-6b374f0f-d1ba-4e02-bf89-b0f2a34fce77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640730325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.640730325
Directory	/workspace/3.rv_timer_disabled/latest

Test location	/workspace/coverage/default/3.rv_timer_random_reset.2202294847
Short name	T195
Test name
Test status
Simulation time	54662524964 ps
CPU time	668.32 seconds
Started	Jan 07 12:42:53 PM PST 24
Finished	Jan 07 12:55:25 PM PST 24
Peak memory	194252 kb
Host	smart-2761644c-f740-473c-9cfb-a9f7600da9f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202294847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2202294847
Directory	/workspace/3.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/3.rv_timer_sec_cm.3900823555
Short name	T25
Test name
Test status
Simulation time	218732066 ps
CPU time	0.78 seconds
Started	Jan 07 12:38:49 PM PST 24
Finished	Jan 07 12:39:57 PM PST 24
Peak memory	212804 kb
Host	smart-47a26d9c-da53-48f9-b1e5-852b51cddb3e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900823555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3900823555
Directory	/workspace/3.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/30.rv_timer_disabled.2175743175
Short name	T452
Test name
Test status
Simulation time	406229476994 ps
CPU time	155.66 seconds
Started	Jan 07 12:38:59 PM PST 24
Finished	Jan 07 12:43:02 PM PST 24
Peak memory	182772 kb
Host	smart-ab6ac58e-fb54-4547-aa22-209245dd49a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175743175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2175743175
Directory	/workspace/30.rv_timer_disabled/latest

Test location	/workspace/coverage/default/30.rv_timer_random_reset.3895959753
Short name	T290
Test name
Test status
Simulation time	141064480601 ps
CPU time	90.42 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:41:57 PM PST 24
Peak memory	192936 kb
Host	smart-b2edb591-35ee-4a4f-8c0f-e7096a4d2472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895959753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3895959753
Directory	/workspace/30.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1750204171
Short name	T83
Test name
Test status
Simulation time	562984417623 ps
CPU time	945.46 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 12:57:05 PM PST 24
Peak memory	205672 kb
Host	smart-344722af-18eb-438c-8797-992300f4a301
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750204171 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1750204171
Directory	/workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.rv_timer_random_reset.3604945069
Short name	T295
Test name
Test status
Simulation time	207001411061 ps
CPU time	85.38 seconds
Started	Jan 07 12:39:32 PM PST 24
Finished	Jan 07 12:42:31 PM PST 24
Peak memory	190964 kb
Host	smart-ba5a3e73-40b2-41d8-9ef8-bf3a748bc6e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604945069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3604945069
Directory	/workspace/31.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2599454663
Short name	T435
Test name
Test status
Simulation time	246736213166 ps
CPU time	492.77 seconds
Started	Jan 07 12:38:58 PM PST 24
Finished	Jan 07 12:48:23 PM PST 24
Peak memory	209076 kb
Host	smart-4f61ace7-6971-4de1-9e31-9aa841dc1d61
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599454663 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2599454663
Directory	/workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.rv_timer_disabled.3471114972
Short name	T458
Test name
Test status
Simulation time	145541522522 ps
CPU time	89.36 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:42:57 PM PST 24
Peak memory	182808 kb
Host	smart-067d6666-18d7-4663-b0c2-6be4ffc2f0bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471114972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3471114972
Directory	/workspace/32.rv_timer_disabled/latest

Test location	/workspace/coverage/default/32.rv_timer_random.4153013198
Short name	T229
Test name
Test status
Simulation time	65141723025 ps
CPU time	103.08 seconds
Started	Jan 07 12:39:55 PM PST 24
Finished	Jan 07 12:43:15 PM PST 24
Peak memory	191000 kb
Host	smart-e9d2e858-f0ec-4e34-b368-dc99f9552a98
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153013198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4153013198
Directory	/workspace/32.rv_timer_random/latest

Test location	/workspace/coverage/default/32.rv_timer_random_reset.1231680380
Short name	T400
Test name
Test status
Simulation time	354084843 ps
CPU time	0.67 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 12:41:15 PM PST 24
Peak memory	182528 kb
Host	smart-89f7ddd2-b90c-4664-bb9b-fc9cec14ea74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231680380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1231680380
Directory	/workspace/32.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/32.rv_timer_stress_all.2982198451
Short name	T388
Test name
Test status
Simulation time	2751945100220 ps
CPU time	382.17 seconds
Started	Jan 07 12:39:10 PM PST 24
Finished	Jan 07 12:46:59 PM PST 24
Peak memory	191016 kb
Host	smart-e5ceacd1-f0e6-4363-91b4-b99251fa5a56
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982198451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .2982198451
Directory	/workspace/32.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.844252164
Short name	T20
Test name
Test status
Simulation time	19309497726 ps
CPU time	163.65 seconds
Started	Jan 07 12:39:20 PM PST 24
Finished	Jan 07 12:43:37 PM PST 24
Peak memory	197564 kb
Host	smart-c514814b-3913-4ded-a255-d52a33c94612
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844252164 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.844252164
Directory	/workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.rv_timer_disabled.1590933400
Short name	T441
Test name
Test status
Simulation time	97642241051 ps
CPU time	152.4 seconds
Started	Jan 07 12:39:38 PM PST 24
Finished	Jan 07 12:43:38 PM PST 24
Peak memory	182876 kb
Host	smart-785ea33f-b109-4580-83b0-292000acf859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590933400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1590933400
Directory	/workspace/33.rv_timer_disabled/latest

Test location	/workspace/coverage/default/33.rv_timer_random.1263712637
Short name	T127
Test name
Test status
Simulation time	280581093034 ps
CPU time	252.53 seconds
Started	Jan 07 12:40:59 PM PST 24
Finished	Jan 07 12:46:57 PM PST 24
Peak memory	190592 kb
Host	smart-eebe29e7-d749-4de6-a892-cd54a81bd566
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263712637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1263712637
Directory	/workspace/33.rv_timer_random/latest

Test location	/workspace/coverage/default/33.rv_timer_random_reset.291009833
Short name	T245
Test name
Test status
Simulation time	146343228071 ps
CPU time	22.59 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:41:24 PM PST 24
Peak memory	193900 kb
Host	smart-823d4531-93df-4009-94e3-1044c36757f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291009833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.291009833
Directory	/workspace/33.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1567205422
Short name	T436
Test name
Test status
Simulation time	45213863133 ps
CPU time	203.14 seconds
Started	Jan 07 12:40:59 PM PST 24
Finished	Jan 07 12:45:39 PM PST 24
Peak memory	197084 kb
Host	smart-5b121111-2629-4635-a738-541656cc5049
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567205422 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1567205422
Directory	/workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.rv_timer_disabled.1482511423
Short name	T407
Test name
Test status
Simulation time	174787281427 ps
CPU time	115.61 seconds
Started	Jan 07 12:38:49 PM PST 24
Finished	Jan 07 12:42:05 PM PST 24
Peak memory	182960 kb
Host	smart-80d9a972-84cd-4719-ace1-8e405c69b307
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482511423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1482511423
Directory	/workspace/34.rv_timer_disabled/latest

Test location	/workspace/coverage/default/34.rv_timer_random_reset.2102565475
Short name	T134
Test name
Test status
Simulation time	82421093930 ps
CPU time	29.88 seconds
Started	Jan 07 12:39:09 PM PST 24
Finished	Jan 07 12:41:06 PM PST 24
Peak memory	194296 kb
Host	smart-e270d91c-d5fc-456e-92e6-9ca0ebf4b1fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102565475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2102565475
Directory	/workspace/34.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.4090943054
Short name	T432
Test name
Test status
Simulation time	247767661576 ps
CPU time	936.3 seconds
Started	Jan 07 12:39:16 PM PST 24
Finished	Jan 07 12:56:19 PM PST 24
Peak memory	207260 kb
Host	smart-af5d09d4-be3e-487a-b5b9-afa4a8e8234b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090943054 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.4090943054
Directory	/workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.rv_timer_random_reset.1230561883
Short name	T428
Test name
Test status
Simulation time	202135103 ps
CPU time	0.61 seconds
Started	Jan 07 12:39:03 PM PST 24
Finished	Jan 07 12:40:30 PM PST 24
Peak memory	182552 kb
Host	smart-abbc7c5a-d7fb-48b2-814d-cc831f510006
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230561883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1230561883
Directory	/workspace/35.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/35.rv_timer_stress_all.196286706
Short name	T164
Test name
Test status
Simulation time	71181724349 ps
CPU time	63.86 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:42:09 PM PST 24
Peak memory	191036 kb
Host	smart-482e55fe-0265-4617-8136-638a70d59df9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196286706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all. 196286706
Directory	/workspace/35.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/36.rv_timer_random.2049500032
Short name	T32
Test name
Test status
Simulation time	134089895024 ps
CPU time	1111.25 seconds
Started	Jan 07 12:39:06 PM PST 24
Finished	Jan 07 12:59:07 PM PST 24
Peak memory	182772 kb
Host	smart-774843a8-4fc1-4574-a2de-ef85f3d8d598
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049500032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2049500032
Directory	/workspace/36.rv_timer_random/latest

Test location	/workspace/coverage/default/36.rv_timer_random_reset.2570516756
Short name	T315
Test name
Test status
Simulation time	32368189526 ps
CPU time	43.85 seconds
Started	Jan 07 12:39:34 PM PST 24
Finished	Jan 07 12:41:40 PM PST 24
Peak memory	191528 kb
Host	smart-067c977e-727b-414c-98df-1ef3e2582d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2570516756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2570516756
Directory	/workspace/36.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/36.rv_timer_stress_all.1063453270
Short name	T317
Test name
Test status
Simulation time	136831105744 ps
CPU time	157.12 seconds
Started	Jan 07 12:39:02 PM PST 24
Finished	Jan 07 12:43:14 PM PST 24
Peak memory	194652 kb
Host	smart-e6cd3a16-9300-4939-b409-f70e6a855c39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063453270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .1063453270
Directory	/workspace/36.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2118246077
Short name	T23
Test name
Test status
Simulation time	422909082183 ps
CPU time	701.91 seconds
Started	Jan 07 12:39:56 PM PST 24
Finished	Jan 07 12:53:03 PM PST 24
Peak memory	182944 kb
Host	smart-a4ee00fa-0f93-41b1-b62b-b22d63c9bd92
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118246077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2118246077
Directory	/workspace/37.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/37.rv_timer_disabled.768935135
Short name	T408
Test name
Test status
Simulation time	76369828276 ps
CPU time	56.25 seconds
Started	Jan 07 12:39:02 PM PST 24
Finished	Jan 07 12:41:21 PM PST 24
Peak memory	182804 kb
Host	smart-a9df661a-aa6a-443f-98d7-965084691be5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768935135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.768935135
Directory	/workspace/37.rv_timer_disabled/latest

Test location	/workspace/coverage/default/37.rv_timer_random.4095934045
Short name	T145
Test name
Test status
Simulation time	898417017345 ps
CPU time	1128.9 seconds
Started	Jan 07 12:39:11 PM PST 24
Finished	Jan 07 12:59:24 PM PST 24
Peak memory	191132 kb
Host	smart-707600d8-f0d8-4f07-bcbc-1234f76492f4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095934045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.4095934045
Directory	/workspace/37.rv_timer_random/latest

Test location	/workspace/coverage/default/37.rv_timer_stress_all.3811593293
Short name	T133
Test name
Test status
Simulation time	1865830061308 ps
CPU time	532.46 seconds
Started	Jan 07 12:39:14 PM PST 24
Finished	Jan 07 12:49:22 PM PST 24
Peak memory	190984 kb
Host	smart-f478627b-49d6-4358-8afb-2713d86b9c88
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811593293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .3811593293
Directory	/workspace/37.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/38.rv_timer_random.438956199
Short name	T314
Test name
Test status
Simulation time	588272527457 ps
CPU time	189.53 seconds
Started	Jan 07 12:39:23 PM PST 24
Finished	Jan 07 12:43:55 PM PST 24
Peak memory	190956 kb
Host	smart-295078b9-46a6-4544-a840-e6c15517daa9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438956199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.438956199
Directory	/workspace/38.rv_timer_random/latest

Test location	/workspace/coverage/default/38.rv_timer_random_reset.1564623632
Short name	T453
Test name
Test status
Simulation time	33400787593 ps
CPU time	51.66 seconds
Started	Jan 07 12:39:26 PM PST 24
Finished	Jan 07 12:41:47 PM PST 24
Peak memory	193884 kb
Host	smart-2daafc1e-b330-4475-9c0b-321a54612216
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564623632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1564623632
Directory	/workspace/38.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/38.rv_timer_stress_all.82850065
Short name	T143
Test name
Test status
Simulation time	1128678851763 ps
CPU time	1487.26 seconds
Started	Jan 07 12:39:13 PM PST 24
Finished	Jan 07 01:05:30 PM PST 24
Peak memory	191024 kb
Host	smart-1a69fd0b-28d1-4873-83f0-f94c998cccd2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82850065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.82850065
Directory	/workspace/38.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3249403114
Short name	T325
Test name
Test status
Simulation time	39605706934 ps
CPU time	282.39 seconds
Started	Jan 07 12:39:38 PM PST 24
Finished	Jan 07 12:45:57 PM PST 24
Peak memory	205776 kb
Host	smart-0898b10a-6d01-46f9-a3fd-5c37fea3ce99
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249403114 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3249403114
Directory	/workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3817791853
Short name	T280
Test name
Test status
Simulation time	1355508685384 ps
CPU time	383.43 seconds
Started	Jan 07 12:40:00 PM PST 24
Finished	Jan 07 12:47:38 PM PST 24
Peak memory	182716 kb
Host	smart-b4bd7b08-b51e-4652-8d94-37fee6079197
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817791853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.3817791853
Directory	/workspace/39.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/39.rv_timer_disabled.669005376
Short name	T456
Test name
Test status
Simulation time	13678402168 ps
CPU time	19.16 seconds
Started	Jan 07 12:39:33 PM PST 24
Finished	Jan 07 12:41:33 PM PST 24
Peak memory	182840 kb
Host	smart-9785a5e0-fb23-4fe5-992a-75f70d29f720
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669005376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.669005376
Directory	/workspace/39.rv_timer_disabled/latest

Test location	/workspace/coverage/default/39.rv_timer_random.2240995423
Short name	T174
Test name
Test status
Simulation time	7218221103 ps
CPU time	6.81 seconds
Started	Jan 07 12:38:56 PM PST 24
Finished	Jan 07 12:40:22 PM PST 24
Peak memory	182808 kb
Host	smart-3a696840-ee23-4af0-8006-3b390b60c5cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240995423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2240995423
Directory	/workspace/39.rv_timer_random/latest

Test location	/workspace/coverage/default/39.rv_timer_random_reset.736050808
Short name	T433
Test name
Test status
Simulation time	312756996 ps
CPU time	0.69 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:40:55 PM PST 24
Peak memory	182528 kb
Host	smart-50e23db6-6536-4c47-8849-dace534e6f33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736050808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.736050808
Directory	/workspace/39.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2909980996
Short name	T301
Test name
Test status
Simulation time	366180405749 ps
CPU time	766.77 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:53:33 PM PST 24
Peak memory	210108 kb
Host	smart-ca8b9c3f-6123-45fc-8ea8-c742f726be51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909980996 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2909980996
Directory	/workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2732732676
Short name	T208
Test name
Test status
Simulation time	138289700890 ps
CPU time	128.61 seconds
Started	Jan 07 12:39:11 PM PST 24
Finished	Jan 07 12:42:35 PM PST 24
Peak memory	182964 kb
Host	smart-789466ec-9715-4824-b2ff-dc4f3b07a314
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732732676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.2732732676
Directory	/workspace/4.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/4.rv_timer_disabled.2641780364
Short name	T429
Test name
Test status
Simulation time	515892948157 ps
CPU time	200.18 seconds
Started	Jan 07 12:40:07 PM PST 24
Finished	Jan 07 12:44:31 PM PST 24
Peak memory	180728 kb
Host	smart-2450525c-4857-4879-9908-94baaed37467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641780364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2641780364
Directory	/workspace/4.rv_timer_disabled/latest

Test location	/workspace/coverage/default/4.rv_timer_sec_cm.167593044
Short name	T28
Test name
Test status
Simulation time	86083072 ps
CPU time	0.9 seconds
Started	Jan 07 12:39:15 PM PST 24
Finished	Jan 07 12:40:51 PM PST 24
Peak memory	213908 kb
Host	smart-341dea49-f289-40e1-9b7e-9b6ee0f8a76b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167593044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.167593044
Directory	/workspace/4.rv_timer_sec_cm/latest

Test location	/workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3261076302
Short name	T66
Test name
Test status
Simulation time	89958555039 ps
CPU time	692.24 seconds
Started	Jan 07 12:41:14 PM PST 24
Finished	Jan 07 12:54:42 PM PST 24
Peak memory	209464 kb
Host	smart-0db53507-ec42-4437-92ed-ffd1f94b2c5a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261076302 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3261076302
Directory	/workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.rv_timer_disabled.2836357391
Short name	T438
Test name
Test status
Simulation time	555104401099 ps
CPU time	202.15 seconds
Started	Jan 07 12:39:42 PM PST 24
Finished	Jan 07 12:44:19 PM PST 24
Peak memory	182852 kb
Host	smart-108dd2d3-680b-4f57-aff2-22dc69a09e4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836357391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2836357391
Directory	/workspace/40.rv_timer_disabled/latest

Test location	/workspace/coverage/default/40.rv_timer_random_reset.3034250594
Short name	T131
Test name
Test status
Simulation time	640395912481 ps
CPU time	145.78 seconds
Started	Jan 07 12:39:15 PM PST 24
Finished	Jan 07 12:43:03 PM PST 24
Peak memory	182916 kb
Host	smart-e1a50280-4885-4df0-b9bb-ddfa6b82f3a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034250594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3034250594
Directory	/workspace/40.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2873062932
Short name	T79
Test name
Test status
Simulation time	436784373121 ps
CPU time	1752.5 seconds
Started	Jan 07 12:40:22 PM PST 24
Finished	Jan 07 01:10:43 PM PST 24
Peak memory	204184 kb
Host	smart-7559b082-8fb7-4574-b600-03d75a1b4c70
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873062932 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2873062932
Directory	/workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2607589662
Short name	T285
Test name
Test status
Simulation time	460950002499 ps
CPU time	281.69 seconds
Started	Jan 07 12:39:17 PM PST 24
Finished	Jan 07 12:45:16 PM PST 24
Peak memory	182876 kb
Host	smart-4b854340-abf5-4c1f-9416-dc5d2f237a83
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607589662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.2607589662
Directory	/workspace/41.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/41.rv_timer_disabled.3840015633
Short name	T427
Test name
Test status
Simulation time	62351740415 ps
CPU time	89.73 seconds
Started	Jan 07 12:41:13 PM PST 24
Finished	Jan 07 12:44:02 PM PST 24
Peak memory	182384 kb
Host	smart-d9c882b5-4f97-4cb2-882f-3019c82d8836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840015633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3840015633
Directory	/workspace/41.rv_timer_disabled/latest

Test location	/workspace/coverage/default/41.rv_timer_random_reset.4223925786
Short name	T385
Test name
Test status
Simulation time	397720730 ps
CPU time	5.23 seconds
Started	Jan 07 12:40:22 PM PST 24
Finished	Jan 07 12:41:35 PM PST 24
Peak memory	181276 kb
Host	smart-4395c882-6ebc-4583-85e9-b305c2d43cc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223925786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4223925786
Directory	/workspace/41.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3045761826
Short name	T294
Test name
Test status
Simulation time	157954249366 ps
CPU time	747.09 seconds
Started	Jan 07 12:41:24 PM PST 24
Finished	Jan 07 12:55:06 PM PST 24
Peak memory	205984 kb
Host	smart-d39ed1d3-d69e-49d7-b21f-cd0f8bbf40c0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045761826 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3045761826
Directory	/workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.rv_timer_cfg_update_on_fly.885190678
Short name	T129
Test name
Test status
Simulation time	97842323752 ps
CPU time	172.64 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 12:43:37 PM PST 24
Peak memory	182928 kb
Host	smart-e38a95ef-db80-4395-a7ea-b358e45417dd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885190678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.rv_timer_cfg_update_on_fly.885190678
Directory	/workspace/42.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/42.rv_timer_random.2788683256
Short name	T153
Test name
Test status
Simulation time	72643366825 ps
CPU time	131.36 seconds
Started	Jan 07 12:39:23 PM PST 24
Finished	Jan 07 12:42:56 PM PST 24
Peak memory	190996 kb
Host	smart-460d98a8-584c-433e-baa8-c40ad4279113
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788683256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2788683256
Directory	/workspace/42.rv_timer_random/latest

Test location	/workspace/coverage/default/42.rv_timer_random_reset.1815803541
Short name	T425
Test name
Test status
Simulation time	1667730335 ps
CPU time	1.05 seconds
Started	Jan 07 12:39:35 PM PST 24
Finished	Jan 07 12:40:56 PM PST 24
Peak memory	182452 kb
Host	smart-52ba48c3-7062-46c5-b0fc-0bd335164cc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815803541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1815803541
Directory	/workspace/42.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/42.rv_timer_stress_all.1903800867
Short name	T293
Test name
Test status
Simulation time	273397506715 ps
CPU time	147.43 seconds
Started	Jan 07 12:39:56 PM PST 24
Finished	Jan 07 12:43:32 PM PST 24
Peak memory	182944 kb
Host	smart-17ed6d4b-f30a-4a99-9629-5e3cac04cff0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903800867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .1903800867
Directory	/workspace/42.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/43.rv_timer_disabled.2768606024
Short name	T30
Test name
Test status
Simulation time	377104576960 ps
CPU time	239.61 seconds
Started	Jan 07 12:39:19 PM PST 24
Finished	Jan 07 12:44:44 PM PST 24
Peak memory	182840 kb
Host	smart-aa010f35-6fe2-49a9-841a-5b74d3175e15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768606024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2768606024
Directory	/workspace/43.rv_timer_disabled/latest

Test location	/workspace/coverage/default/43.rv_timer_random.2966843134
Short name	T250
Test name
Test status
Simulation time	518537008476 ps
CPU time	309.9 seconds
Started	Jan 07 12:39:15 PM PST 24
Finished	Jan 07 12:46:05 PM PST 24
Peak memory	191124 kb
Host	smart-f4cb880a-32c3-4e9b-a7d2-fb7899220970
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966843134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2966843134
Directory	/workspace/43.rv_timer_random/latest

Test location	/workspace/coverage/default/43.rv_timer_random_reset.882770501
Short name	T29
Test name
Test status
Simulation time	50646770274 ps
CPU time	94.87 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:43:18 PM PST 24
Peak memory	191012 kb
Host	smart-0e61fd16-6b0c-4a19-b9ec-a3cd8c51d241
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882770501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.882770501
Directory	/workspace/43.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/43.rv_timer_stress_all.902164152
Short name	T420
Test name
Test status
Simulation time	303571311021 ps
CPU time	503.01 seconds
Started	Jan 07 12:39:47 PM PST 24
Finished	Jan 07 12:49:52 PM PST 24
Peak memory	191176 kb
Host	smart-eb223304-d02f-4023-b6a6-10ee64f35ead
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902164152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all. 902164152
Directory	/workspace/43.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2910647904
Short name	T187
Test name
Test status
Simulation time	28982542292 ps
CPU time	383.25 seconds
Started	Jan 07 12:39:57 PM PST 24
Finished	Jan 07 12:47:45 PM PST 24
Peak memory	197484 kb
Host	smart-08e96ab5-4b51-4389-afe7-48c17be669f7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910647904 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2910647904
Directory	/workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.rv_timer_disabled.1004278271
Short name	T444
Test name
Test status
Simulation time	27647629137 ps
CPU time	41.23 seconds
Started	Jan 07 12:39:51 PM PST 24
Finished	Jan 07 12:41:44 PM PST 24
Peak memory	182948 kb
Host	smart-06227712-9c8e-4094-a535-a3c5897a91b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004278271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1004278271
Directory	/workspace/44.rv_timer_disabled/latest

Test location	/workspace/coverage/default/44.rv_timer_random_reset.88183541
Short name	T216
Test name
Test status
Simulation time	43822165509 ps
CPU time	263.49 seconds
Started	Jan 07 12:39:29 PM PST 24
Finished	Jan 07 12:45:14 PM PST 24
Peak memory	182812 kb
Host	smart-ef784546-6090-43e0-b3b8-4d6f5d37e5ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88183541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.88183541
Directory	/workspace/44.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.104983780
Short name	T330
Test name
Test status
Simulation time	129996957167 ps
CPU time	543.86 seconds
Started	Jan 07 12:39:18 PM PST 24
Finished	Jan 07 12:49:45 PM PST 24
Peak memory	205740 kb
Host	smart-3b5f434d-0626-4d48-9c33-8f9781c3937e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104983780 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.104983780
Directory	/workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2102860111
Short name	T311
Test name
Test status
Simulation time	52837173950 ps
CPU time	18.9 seconds
Started	Jan 07 12:39:24 PM PST 24
Finished	Jan 07 12:41:06 PM PST 24
Peak memory	182824 kb
Host	smart-c107ebae-790b-4617-9ecc-26941185cc72
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102860111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2102860111
Directory	/workspace/45.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/45.rv_timer_disabled.2114341034
Short name	T389
Test name
Test status
Simulation time	119181101360 ps
CPU time	110.64 seconds
Started	Jan 07 12:39:20 PM PST 24
Finished	Jan 07 12:42:27 PM PST 24
Peak memory	182972 kb
Host	smart-60e481c1-cb90-49db-8437-73efa5029a0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114341034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2114341034
Directory	/workspace/45.rv_timer_disabled/latest

Test location	/workspace/coverage/default/45.rv_timer_random_reset.3390898519
Short name	T331
Test name
Test status
Simulation time	16043556988 ps
CPU time	31.96 seconds
Started	Jan 07 12:39:43 PM PST 24
Finished	Jan 07 12:41:47 PM PST 24
Peak memory	194440 kb
Host	smart-feab1a33-8a82-42fb-ba5e-43ad94972cb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390898519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3390898519
Directory	/workspace/45.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3297089141
Short name	T424
Test name
Test status
Simulation time	134513884589 ps
CPU time	361.81 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 12:47:21 PM PST 24
Peak memory	205748 kb
Host	smart-c9a09aa0-85a3-4499-94eb-5b488b83b08b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297089141 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.3297089141
Directory	/workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.rv_timer_disabled.2818246149
Short name	T445
Test name
Test status
Simulation time	464357396983 ps
CPU time	200.72 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 12:44:38 PM PST 24
Peak memory	182816 kb
Host	smart-8f7356f1-5805-4a58-8a38-ce4b000ba14d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818246149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2818246149
Directory	/workspace/46.rv_timer_disabled/latest

Test location	/workspace/coverage/default/46.rv_timer_random.1913058310
Short name	T110
Test name
Test status
Simulation time	162081859869 ps
CPU time	87.7 seconds
Started	Jan 07 12:39:26 PM PST 24
Finished	Jan 07 12:42:21 PM PST 24
Peak memory	191056 kb
Host	smart-8e4e203d-e693-4ea9-ad97-6cf2cbab2a80
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913058310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1913058310
Directory	/workspace/46.rv_timer_random/latest

Test location	/workspace/coverage/default/46.rv_timer_random_reset.1687777082
Short name	T319
Test name
Test status
Simulation time	108184075028 ps
CPU time	53.06 seconds
Started	Jan 07 12:39:46 PM PST 24
Finished	Jan 07 12:42:01 PM PST 24
Peak memory	191084 kb
Host	smart-93772776-65e6-4723-87c4-1de746efa665
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687777082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1687777082
Directory	/workspace/46.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2527542773
Short name	T431
Test name
Test status
Simulation time	38114114122 ps
CPU time	187.36 seconds
Started	Jan 07 12:39:17 PM PST 24
Finished	Jan 07 12:43:42 PM PST 24
Peak memory	197556 kb
Host	smart-f009acea-ad8e-4a3f-bb3f-b19cc3af317d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527542773 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2527542773
Directory	/workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2437762958
Short name	T299
Test name
Test status
Simulation time	315766614764 ps
CPU time	574.5 seconds
Started	Jan 07 12:39:52 PM PST 24
Finished	Jan 07 12:50:41 PM PST 24
Peak memory	182752 kb
Host	smart-6075e784-0895-4f26-bc00-be1fea35c377
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437762958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2437762958
Directory	/workspace/47.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/47.rv_timer_disabled.1040605791
Short name	T406
Test name
Test status
Simulation time	209969504116 ps
CPU time	141.58 seconds
Started	Jan 07 12:39:33 PM PST 24
Finished	Jan 07 12:43:24 PM PST 24
Peak memory	182812 kb
Host	smart-adfae9a0-158a-4c67-b744-eac4bfc8cebd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040605791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1040605791
Directory	/workspace/47.rv_timer_disabled/latest

Test location	/workspace/coverage/default/47.rv_timer_random.2338386710
Short name	T121
Test name
Test status
Simulation time	1159639744350 ps
CPU time	647.12 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:52:13 PM PST 24
Peak memory	191104 kb
Host	smart-cefd5db0-fffc-44cd-bb23-5b07f4d8ae0c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338386710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2338386710
Directory	/workspace/47.rv_timer_random/latest

Test location	/workspace/coverage/default/47.rv_timer_random_reset.1718228934
Short name	T318
Test name
Test status
Simulation time	251675684625 ps
CPU time	1472.97 seconds
Started	Jan 07 12:39:25 PM PST 24
Finished	Jan 07 01:05:20 PM PST 24
Peak memory	182812 kb
Host	smart-fca71763-1b24-41be-8c88-6fae14e310a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718228934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1718228934
Directory	/workspace/47.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.327210354
Short name	T413
Test name
Test status
Simulation time	83903166732 ps
CPU time	162.13 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:43:43 PM PST 24
Peak memory	205788 kb
Host	smart-08fb0443-878f-4554-8a0a-e1295268873a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327210354 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.327210354
Directory	/workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3529266834
Short name	T313
Test name
Test status
Simulation time	822332910264 ps
CPU time	571.64 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:50:20 PM PST 24
Peak memory	182936 kb
Host	smart-8a297233-f491-41a7-8d11-ffe5c7a763a8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529266834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.3529266834
Directory	/workspace/48.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/48.rv_timer_disabled.2972396828
Short name	T36
Test name
Test status
Simulation time	127876702563 ps
CPU time	188.77 seconds
Started	Jan 07 12:39:26 PM PST 24
Finished	Jan 07 12:44:01 PM PST 24
Peak memory	182788 kb
Host	smart-95795907-bdf5-4cfe-84d3-dfa957188e30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972396828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2972396828
Directory	/workspace/48.rv_timer_disabled/latest

Test location	/workspace/coverage/default/48.rv_timer_random.3804487344
Short name	T176
Test name
Test status
Simulation time	867632949667 ps
CPU time	187.36 seconds
Started	Jan 07 12:39:51 PM PST 24
Finished	Jan 07 12:44:09 PM PST 24
Peak memory	191092 kb
Host	smart-d7b7f09b-ca2a-4b95-bf20-48ac949ee2a5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804487344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3804487344
Directory	/workspace/48.rv_timer_random/latest

Test location	/workspace/coverage/default/48.rv_timer_random_reset.930202401
Short name	T419
Test name
Test status
Simulation time	100746087 ps
CPU time	0.65 seconds
Started	Jan 07 12:39:15 PM PST 24
Finished	Jan 07 12:40:56 PM PST 24
Peak memory	182552 kb
Host	smart-e51460fb-f944-4032-89a1-910a7f07c64b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930202401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.930202401
Directory	/workspace/48.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3728518632
Short name	T112
Test name
Test status
Simulation time	3196844198856 ps
CPU time	741.68 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 12:53:37 PM PST 24
Peak memory	182776 kb
Host	smart-00a0a269-4b54-4a20-8939-6beef2c6a40a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728518632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3728518632
Directory	/workspace/49.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/49.rv_timer_disabled.2935153600
Short name	T395
Test name
Test status
Simulation time	157842052646 ps
CPU time	117.59 seconds
Started	Jan 07 12:39:17 PM PST 24
Finished	Jan 07 12:42:52 PM PST 24
Peak memory	182836 kb
Host	smart-38fbe060-9706-4f35-853b-de5c2d13f98f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935153600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2935153600
Directory	/workspace/49.rv_timer_disabled/latest

Test location	/workspace/coverage/default/49.rv_timer_random.2000118547
Short name	T244
Test name
Test status
Simulation time	139380378084 ps
CPU time	64.43 seconds
Started	Jan 07 12:39:28 PM PST 24
Finished	Jan 07 12:42:02 PM PST 24
Peak memory	194404 kb
Host	smart-a03c9c9e-d525-4a18-9645-bb9738b87f2f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000118547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2000118547
Directory	/workspace/49.rv_timer_random/latest

Test location	/workspace/coverage/default/49.rv_timer_random_reset.1014913923
Short name	T296
Test name
Test status
Simulation time	4631116633 ps
CPU time	7.75 seconds
Started	Jan 07 12:39:42 PM PST 24
Finished	Jan 07 12:41:08 PM PST 24
Peak memory	193008 kb
Host	smart-e3dcb413-427c-4cc5-a833-ec4ae0d7507b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014913923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1014913923
Directory	/workspace/49.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/49.rv_timer_stress_all.4044487460
Short name	T128
Test name
Test status
Simulation time	145949198432 ps
CPU time	219.88 seconds
Started	Jan 07 12:39:16 PM PST 24
Finished	Jan 07 12:44:16 PM PST 24
Peak memory	191004 kb
Host	smart-f2463721-6e58-4150-b9cc-02dfe11ba8a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044487460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .4044487460
Directory	/workspace/49.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.50370748
Short name	T443
Test name
Test status
Simulation time	168443276465 ps
CPU time	469.8 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 12:49:25 PM PST 24
Peak memory	197524 kb
Host	smart-66b7dcc0-6254-4430-a874-7cbee5e85b51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50370748 -assert nopos tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.50370748
Directory	/workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.rv_timer_random.1630083522
Short name	T114
Test name
Test status
Simulation time	396098895702 ps
CPU time	2044.45 seconds
Started	Jan 07 12:39:34 PM PST 24
Finished	Jan 07 01:15:09 PM PST 24
Peak memory	191152 kb
Host	smart-f4aee5db-1d22-4002-a11c-44c7d527162e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630083522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1630083522
Directory	/workspace/5.rv_timer_random/latest

Test location	/workspace/coverage/default/5.rv_timer_stress_all.4109307600
Short name	T162
Test name
Test status
Simulation time	255379990330 ps
CPU time	2316.33 seconds
Started	Jan 07 12:38:59 PM PST 24
Finished	Jan 07 01:18:47 PM PST 24
Peak memory	191168 kb
Host	smart-45e55ce2-86fe-4851-82d8-c7bd4024ff39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109307600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 4109307600
Directory	/workspace/5.rv_timer_stress_all/latest

Test location	/workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3104852706
Short name	T405
Test name
Test status
Simulation time	64873850784 ps
CPU time	446.49 seconds
Started	Jan 07 12:39:12 PM PST 24
Finished	Jan 07 12:47:53 PM PST 24
Peak memory	197636 kb
Host	smart-b2a2f1af-45d2-4c15-81bc-9a58e5a476fc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104852706 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3104852706
Directory	/workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/50.rv_timer_random.443662752
Short name	T206
Test name
Test status
Simulation time	307467856042 ps
CPU time	432.22 seconds
Started	Jan 07 12:39:20 PM PST 24
Finished	Jan 07 12:47:52 PM PST 24
Peak memory	191088 kb
Host	smart-62f16532-4665-4cda-b59d-f76d71bd8a64
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443662752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.443662752
Directory	/workspace/50.rv_timer_random/latest

Test location	/workspace/coverage/default/52.rv_timer_random.1478357467
Short name	T144
Test name
Test status
Simulation time	142492400191 ps
CPU time	249.67 seconds
Started	Jan 07 12:39:54 PM PST 24
Finished	Jan 07 12:45:31 PM PST 24
Peak memory	193472 kb
Host	smart-683baefd-1f5d-456e-9f65-0fe1337d15a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478357467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1478357467
Directory	/workspace/52.rv_timer_random/latest

Test location	/workspace/coverage/default/53.rv_timer_random.3497503037
Short name	T256
Test name
Test status
Simulation time	98549028690 ps
CPU time	66.45 seconds
Started	Jan 07 12:39:35 PM PST 24
Finished	Jan 07 12:42:18 PM PST 24
Peak memory	182792 kb
Host	smart-5a0ee8ac-54eb-48b6-989b-f86fdde9c06b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497503037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3497503037
Directory	/workspace/53.rv_timer_random/latest

Test location	/workspace/coverage/default/56.rv_timer_random.4252359730
Short name	T279
Test name
Test status
Simulation time	18682299109 ps
CPU time	31.96 seconds
Started	Jan 07 12:40:05 PM PST 24
Finished	Jan 07 12:41:48 PM PST 24
Peak memory	190960 kb
Host	smart-d439f83e-93d2-4479-847e-1fced430c55c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252359730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4252359730
Directory	/workspace/56.rv_timer_random/latest

Test location	/workspace/coverage/default/58.rv_timer_random.2342157710
Short name	T292
Test name
Test status
Simulation time	271802796275 ps
CPU time	152.05 seconds
Started	Jan 07 12:39:42 PM PST 24
Finished	Jan 07 12:43:32 PM PST 24
Peak memory	191460 kb
Host	smart-e1c727c3-eb70-4023-b02b-c618af45e62e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342157710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2342157710
Directory	/workspace/58.rv_timer_random/latest

Test location	/workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2853217252
Short name	T251
Test name
Test status
Simulation time	2973947610757 ps
CPU time	940.61 seconds
Started	Jan 07 12:39:32 PM PST 24
Finished	Jan 07 12:56:33 PM PST 24
Peak memory	182920 kb
Host	smart-bb42c7d4-7819-4c8a-a534-e80ce5653637
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853217252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.2853217252
Directory	/workspace/6.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/6.rv_timer_random.3659804624
Short name	T322
Test name
Test status
Simulation time	93389212187 ps
CPU time	369.87 seconds
Started	Jan 07 12:39:04 PM PST 24
Finished	Jan 07 12:46:34 PM PST 24
Peak memory	191044 kb
Host	smart-09e2c4a6-44ba-40db-a4c1-44ef325b53d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659804624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3659804624
Directory	/workspace/6.rv_timer_random/latest

Test location	/workspace/coverage/default/6.rv_timer_random_reset.3945214722
Short name	T437
Test name
Test status
Simulation time	53014442 ps
CPU time	0.54 seconds
Started	Jan 07 12:38:37 PM PST 24
Finished	Jan 07 12:40:11 PM PST 24
Peak memory	182556 kb
Host	smart-a119252d-002a-4564-b615-fd1abfa19ebf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945214722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3945214722
Directory	/workspace/6.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/60.rv_timer_random.1281398024
Short name	T227
Test name
Test status
Simulation time	599778605680 ps
CPU time	298.84 seconds
Started	Jan 07 12:39:33 PM PST 24
Finished	Jan 07 12:45:56 PM PST 24
Peak memory	191020 kb
Host	smart-09ce7fbd-6431-45c6-99b8-77e785a852e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281398024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1281398024
Directory	/workspace/60.rv_timer_random/latest

Test location	/workspace/coverage/default/63.rv_timer_random.1401487152
Short name	T230
Test name
Test status
Simulation time	2121604243 ps
CPU time	17.52 seconds
Started	Jan 07 12:39:42 PM PST 24
Finished	Jan 07 12:41:11 PM PST 24
Peak memory	182776 kb
Host	smart-894b7e9c-bf48-4c72-b5b9-8967635ffa55
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401487152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1401487152
Directory	/workspace/63.rv_timer_random/latest

Test location	/workspace/coverage/default/64.rv_timer_random.2851574997
Short name	T13
Test name
Test status
Simulation time	196617397508 ps
CPU time	354.2 seconds
Started	Jan 07 12:39:44 PM PST 24
Finished	Jan 07 12:47:31 PM PST 24
Peak memory	191008 kb
Host	smart-20b372a9-6a82-4b7b-b4be-f56e2d77fea3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851574997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2851574997
Directory	/workspace/64.rv_timer_random/latest

Test location	/workspace/coverage/default/65.rv_timer_random.2811330883
Short name	T239
Test name
Test status
Simulation time	327370391589 ps
CPU time	131.24 seconds
Started	Jan 07 12:39:28 PM PST 24
Finished	Jan 07 12:42:56 PM PST 24
Peak memory	190964 kb
Host	smart-e2e4b37f-710b-4b67-be81-9bf36bbceb3e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811330883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2811330883
Directory	/workspace/65.rv_timer_random/latest

Test location	/workspace/coverage/default/67.rv_timer_random.976341414
Short name	T209
Test name
Test status
Simulation time	33647911626 ps
CPU time	373.01 seconds
Started	Jan 07 12:39:48 PM PST 24
Finished	Jan 07 12:47:17 PM PST 24
Peak memory	182976 kb
Host	smart-76f05e28-eae7-47ed-915c-3bbd74eeed0d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976341414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.976341414
Directory	/workspace/67.rv_timer_random/latest

Test location	/workspace/coverage/default/69.rv_timer_random.2550506245
Short name	T212
Test name
Test status
Simulation time	129722678387 ps
CPU time	485.94 seconds
Started	Jan 07 12:39:50 PM PST 24
Finished	Jan 07 12:49:48 PM PST 24
Peak memory	191048 kb
Host	smart-c35ac221-ea19-4813-9709-7952aefedc5b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550506245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2550506245
Directory	/workspace/69.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_disabled.1908290080
Short name	T416
Test name
Test status
Simulation time	48022892721 ps
CPU time	63.11 seconds
Started	Jan 07 12:39:42 PM PST 24
Finished	Jan 07 12:42:02 PM PST 24
Peak memory	182796 kb
Host	smart-ba8c1a91-bc36-4a2f-a4c9-1f78bd4fce81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908290080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1908290080
Directory	/workspace/7.rv_timer_disabled/latest

Test location	/workspace/coverage/default/7.rv_timer_random.2878614709
Short name	T186
Test name
Test status
Simulation time	220928163062 ps
CPU time	216.06 seconds
Started	Jan 07 12:38:46 PM PST 24
Finished	Jan 07 12:43:50 PM PST 24
Peak memory	193084 kb
Host	smart-b9296b55-5410-417d-992d-9744d589fc16
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878614709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2878614709
Directory	/workspace/7.rv_timer_random/latest

Test location	/workspace/coverage/default/7.rv_timer_random_reset.3462188346
Short name	T221
Test name
Test status
Simulation time	144945079454 ps
CPU time	420.78 seconds
Started	Jan 07 12:39:02 PM PST 24
Finished	Jan 07 12:47:27 PM PST 24
Peak memory	194252 kb
Host	smart-f398fbc8-29a7-4367-9542-993be35362f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462188346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3462188346
Directory	/workspace/7.rv_timer_random_reset/latest

Test location	/workspace/coverage/default/70.rv_timer_random.2505479275
Short name	T140
Test name
Test status
Simulation time	265469468992 ps
CPU time	280.56 seconds
Started	Jan 07 12:39:56 PM PST 24
Finished	Jan 07 12:45:45 PM PST 24
Peak memory	191080 kb
Host	smart-038aa4b6-7d93-439d-92c5-fdf6bf315197
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505479275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2505479275
Directory	/workspace/70.rv_timer_random/latest

Test location	/workspace/coverage/default/71.rv_timer_random.1368306591
Short name	T123
Test name
Test status
Simulation time	251748163323 ps
CPU time	492.53 seconds
Started	Jan 07 12:40:19 PM PST 24
Finished	Jan 07 12:49:47 PM PST 24
Peak memory	191196 kb
Host	smart-bf450db3-2f7f-4e68-ab7e-6a741f141de6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368306591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1368306591
Directory	/workspace/71.rv_timer_random/latest

Test location	/workspace/coverage/default/74.rv_timer_random.2076761221
Short name	T243
Test name
Test status
Simulation time	248646157450 ps
CPU time	302.04 seconds
Started	Jan 07 12:40:00 PM PST 24
Finished	Jan 07 12:46:12 PM PST 24
Peak memory	193928 kb
Host	smart-5bcec29a-0af0-4edb-a233-f3dc5f70fbf4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076761221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2076761221
Directory	/workspace/74.rv_timer_random/latest

Test location	/workspace/coverage/default/75.rv_timer_random.2749438301
Short name	T22
Test name
Test status
Simulation time	210298698586 ps
CPU time	121.74 seconds
Started	Jan 07 12:40:00 PM PST 24
Finished	Jan 07 12:43:30 PM PST 24
Peak memory	193592 kb
Host	smart-e151479f-f266-441c-8295-56c728757c8d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749438301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2749438301
Directory	/workspace/75.rv_timer_random/latest

Test location	/workspace/coverage/default/76.rv_timer_random.2775207225
Short name	T300
Test name
Test status
Simulation time	257784106976 ps
CPU time	478.07 seconds
Started	Jan 07 12:40:07 PM PST 24
Finished	Jan 07 12:49:06 PM PST 24
Peak memory	190996 kb
Host	smart-24314fbc-dea1-45a7-88bb-4ece76841222
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775207225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2775207225
Directory	/workspace/76.rv_timer_random/latest

Test location	/workspace/coverage/default/77.rv_timer_random.4106497370
Short name	T272
Test name
Test status
Simulation time	272816220122 ps
CPU time	106.93 seconds
Started	Jan 07 12:40:02 PM PST 24
Finished	Jan 07 12:43:26 PM PST 24
Peak memory	193996 kb
Host	smart-3ca17099-3155-4c1e-b0fb-2d7a1351566a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106497370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4106497370
Directory	/workspace/77.rv_timer_random/latest

Test location	/workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3302628768
Short name	T289
Test name
Test status
Simulation time	135813203156 ps
CPU time	73.08 seconds
Started	Jan 07 12:38:39 PM PST 24
Finished	Jan 07 12:41:11 PM PST 24
Peak memory	182820 kb
Host	smart-eb7c6ba3-02cc-4c2b-b83d-d45374fe992e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302628768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3302628768
Directory	/workspace/8.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/8.rv_timer_disabled.3294995373
Short name	T393
Test name
Test status
Simulation time	26046702127 ps
CPU time	43.04 seconds
Started	Jan 07 12:39:19 PM PST 24
Finished	Jan 07 12:41:20 PM PST 24
Peak memory	182844 kb
Host	smart-2e40514f-cbcc-4af8-8050-8fd2851c030f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294995373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3294995373
Directory	/workspace/8.rv_timer_disabled/latest

Test location	/workspace/coverage/default/83.rv_timer_random.707462139
Short name	T269
Test name
Test status
Simulation time	488573237971 ps
CPU time	395.92 seconds
Started	Jan 07 12:39:43 PM PST 24
Finished	Jan 07 12:47:51 PM PST 24
Peak memory	193280 kb
Host	smart-2ed7319d-a3d6-4c6d-aee3-4fae88ee4862
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707462139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.707462139
Directory	/workspace/83.rv_timer_random/latest

Test location	/workspace/coverage/default/85.rv_timer_random.2695388912
Short name	T326
Test name
Test status
Simulation time	297512713067 ps
CPU time	510.15 seconds
Started	Jan 07 12:39:27 PM PST 24
Finished	Jan 07 12:50:07 PM PST 24
Peak memory	190968 kb
Host	smart-6528b8b8-d33c-4251-972d-5783895afafd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695388912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2695388912
Directory	/workspace/85.rv_timer_random/latest

Test location	/workspace/coverage/default/86.rv_timer_random.2030938222
Short name	T231
Test name
Test status
Simulation time	596005908857 ps
CPU time	293.88 seconds
Started	Jan 07 12:40:03 PM PST 24
Finished	Jan 07 12:46:15 PM PST 24
Peak memory	191008 kb
Host	smart-801c7c2f-f08a-47b9-ae6d-542d6bb3f754
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030938222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2030938222
Directory	/workspace/86.rv_timer_random/latest

Test location	/workspace/coverage/default/88.rv_timer_random.3676301476
Short name	T248
Test name
Test status
Simulation time	308198664 ps
CPU time	0.68 seconds
Started	Jan 07 12:39:30 PM PST 24
Finished	Jan 07 12:41:20 PM PST 24
Peak memory	182516 kb
Host	smart-9c3f56e2-1021-4b71-9534-9b370dd1e4fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676301476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3676301476
Directory	/workspace/88.rv_timer_random/latest

Test location	/workspace/coverage/default/89.rv_timer_random.1545680311
Short name	T262
Test name
Test status
Simulation time	27244304180 ps
CPU time	49.32 seconds
Started	Jan 07 12:40:00 PM PST 24
Finished	Jan 07 12:42:09 PM PST 24
Peak memory	190960 kb
Host	smart-0b89c6ec-18be-4d06-9e94-2ba3c62ffba2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545680311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1545680311
Directory	/workspace/89.rv_timer_random/latest

Test location	/workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1879678962
Short name	T173
Test name
Test status
Simulation time	195326269187 ps
CPU time	110.3 seconds
Started	Jan 07 12:39:27 PM PST 24
Finished	Jan 07 12:42:36 PM PST 24
Peak memory	182856 kb
Host	smart-1239a36f-1110-4ccb-8533-9786200b5139
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879678962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1879678962
Directory	/workspace/9.rv_timer_cfg_update_on_fly/latest

Test location	/workspace/coverage/default/9.rv_timer_random.459561663
Short name	T241
Test name
Test status
Simulation time	163808295627 ps
CPU time	693.76 seconds
Started	Jan 07 12:38:50 PM PST 24
Finished	Jan 07 12:51:50 PM PST 24
Peak memory	191160 kb
Host	smart-21d39856-d0d8-4025-bc48-71db191608ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459561663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.459561663
Directory	/workspace/9.rv_timer_random/latest

Test location	/workspace/coverage/default/91.rv_timer_random.3912265190
Short name	T97
Test name
Test status
Simulation time	186354960340 ps
CPU time	213.68 seconds
Started	Jan 07 12:39:31 PM PST 24
Finished	Jan 07 12:46:12 PM PST 24
Peak memory	191092 kb
Host	smart-59deb1be-2eea-419a-bbd7-2c767b6e40fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912265190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3912265190
Directory	/workspace/91.rv_timer_random/latest

Test location	/workspace/coverage/default/93.rv_timer_random.2065504653
Short name	T17
Test name
Test status
Simulation time	16227123700 ps
CPU time	12.08 seconds
Started	Jan 07 12:39:39 PM PST 24
Finished	Jan 07 12:41:14 PM PST 24
Peak memory	182956 kb
Host	smart-acab243c-2793-4f59-9b52-23f24fac6c04
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065504653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2065504653
Directory	/workspace/93.rv_timer_random/latest

Test location	/workspace/coverage/default/94.rv_timer_random.2848174103
Short name	T132
Test name
Test status
Simulation time	55483063864 ps
CPU time	50.3 seconds
Started	Jan 07 12:39:36 PM PST 24
Finished	Jan 07 12:41:41 PM PST 24
Peak memory	191060 kb
Host	smart-89d7e377-1e2a-4557-93ae-caf0af823e82
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848174103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2848174103
Directory	/workspace/94.rv_timer_random/latest

Test location	/workspace/coverage/default/96.rv_timer_random.2046996316
Short name	T138
Test name
Test status
Simulation time	579716586770 ps
CPU time	1575.01 seconds
Started	Jan 07 12:40:00 PM PST 24
Finished	Jan 07 01:07:30 PM PST 24
Peak memory	191064 kb
Host	smart-dfc1d4cb-b407-4184-9c9e-4c96ede0a472
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046996316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2046996316
Directory	/workspace/96.rv_timer_random/latest

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