| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.66 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.89 |
| T538 | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3963396327 | Jan 10 01:08:41 PM PST 24 | Jan 10 01:10:09 PM PST 24 | 4271540827 ps | ||
| T264 | /workspace/coverage/default/133.rv_timer_random.3931245401 | Jan 10 01:09:27 PM PST 24 | Jan 10 01:14:07 PM PST 24 | 405460540117 ps | ||
| T293 | /workspace/coverage/default/141.rv_timer_random.3516634166 | Jan 10 01:09:18 PM PST 24 | Jan 10 01:14:57 PM PST 24 | 540200078588 ps | ||
| T539 | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2169708545 | Jan 10 01:09:09 PM PST 24 | Jan 10 01:12:04 PM PST 24 | 172337237415 ps | ||
| T540 | /workspace/coverage/default/16.rv_timer_disabled.2820794722 | Jan 10 01:08:30 PM PST 24 | Jan 10 01:12:40 PM PST 24 | 735228649849 ps | ||
| T153 | /workspace/coverage/default/192.rv_timer_random.3530040472 | Jan 10 01:09:33 PM PST 24 | Jan 10 01:19:53 PM PST 24 | 1021913155064 ps | ||
| T23 | /workspace/coverage/default/2.rv_timer_sec_cm.2233075956 | Jan 10 01:07:36 PM PST 24 | Jan 10 01:08:58 PM PST 24 | 61069866 ps | ||
| T341 | /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.541080742 | Jan 10 01:08:49 PM PST 24 | Jan 10 01:36:39 PM PST 24 | 149319997191 ps | ||
| T333 | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1075053383 | Jan 10 01:08:48 PM PST 24 | Jan 10 01:32:52 PM PST 24 | 836525060996 ps | ||
| T327 | /workspace/coverage/default/48.rv_timer_random.2663865088 | Jan 10 01:09:08 PM PST 24 | Jan 10 01:16:30 PM PST 24 | 2239954262470 ps | ||
| T541 | /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2527129318 | Jan 10 01:08:51 PM PST 24 | Jan 10 01:21:49 PM PST 24 | 352541559512 ps | ||
| T346 | /workspace/coverage/default/35.rv_timer_random.2236654799 | Jan 10 01:08:47 PM PST 24 | Jan 10 01:12:20 PM PST 24 | 63992904410 ps | ||
| T180 | /workspace/coverage/default/34.rv_timer_random.2768285970 | Jan 10 01:09:02 PM PST 24 | Jan 10 01:13:44 PM PST 24 | 303132701117 ps | ||
| T316 | /workspace/coverage/default/113.rv_timer_random.3291173128 | Jan 10 01:09:19 PM PST 24 | Jan 10 01:17:03 PM PST 24 | 515393193350 ps | ||
| T542 | /workspace/coverage/default/5.rv_timer_stress_all.1972208828 | Jan 10 01:08:51 PM PST 24 | Jan 10 01:26:06 PM PST 24 | 1872242477283 ps | ||
| T263 | /workspace/coverage/default/23.rv_timer_random.2050610733 | Jan 10 01:10:27 PM PST 24 | Jan 10 01:13:05 PM PST 24 | 50137400647 ps | ||
| T543 | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3461377761 | Jan 10 01:08:42 PM PST 24 | Jan 10 01:32:10 PM PST 24 | 160421696364 ps | ||
| T243 | /workspace/coverage/default/107.rv_timer_random.248968187 | Jan 10 01:09:13 PM PST 24 | Jan 10 01:14:33 PM PST 24 | 90231571687 ps | ||
| T244 | /workspace/coverage/default/168.rv_timer_random.1214610201 | Jan 10 01:09:17 PM PST 24 | Jan 10 01:13:03 PM PST 24 | 351272789443 ps | ||
| T326 | /workspace/coverage/default/1.rv_timer_random.3634544441 | Jan 10 01:07:19 PM PST 24 | Jan 10 01:14:40 PM PST 24 | 155580630458 ps | ||
| T544 | /workspace/coverage/default/27.rv_timer_stress_all.3564656713 | Jan 10 01:08:55 PM PST 24 | Jan 10 01:17:38 PM PST 24 | 306627104576 ps | ||
| T164 | /workspace/coverage/default/44.rv_timer_random.2720030129 | Jan 10 01:08:52 PM PST 24 | Jan 10 01:15:55 PM PST 24 | 175311912603 ps | ||
| T174 | /workspace/coverage/default/186.rv_timer_random.3421187667 | Jan 10 01:09:43 PM PST 24 | Jan 10 01:12:52 PM PST 24 | 166148723019 ps | ||
| T545 | /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.155332098 | Jan 10 01:09:06 PM PST 24 | Jan 10 01:17:49 PM PST 24 | 104730155672 ps | ||
| T338 | /workspace/coverage/default/12.rv_timer_stress_all.503205887 | Jan 10 01:07:44 PM PST 24 | Jan 10 01:09:30 PM PST 24 | 14232318287 ps | ||
| T546 | /workspace/coverage/default/22.rv_timer_random_reset.414880271 | Jan 10 01:10:28 PM PST 24 | Jan 10 01:13:03 PM PST 24 | 42791753215 ps | ||
| T547 | /workspace/coverage/default/5.rv_timer_random_reset.1389179716 | Jan 10 01:07:51 PM PST 24 | Jan 10 01:09:34 PM PST 24 | 11261973244 ps | ||
| T548 | /workspace/coverage/default/2.rv_timer_random.1966611857 | Jan 10 01:07:28 PM PST 24 | Jan 10 01:12:33 PM PST 24 | 101664598767 ps | ||
| T549 | /workspace/coverage/default/24.rv_timer_disabled.340856535 | Jan 10 01:08:31 PM PST 24 | Jan 10 01:09:56 PM PST 24 | 6370417412 ps | ||
| T160 | /workspace/coverage/default/31.rv_timer_random.1408217621 | Jan 10 01:08:35 PM PST 24 | Jan 10 01:14:37 PM PST 24 | 360145916796 ps | ||
| T252 | /workspace/coverage/default/9.rv_timer_stress_all.2810325907 | Jan 10 01:07:35 PM PST 24 | Jan 10 01:56:14 PM PST 24 | 1208496874570 ps | ||
| T550 | /workspace/coverage/default/37.rv_timer_random.1767861680 | Jan 10 01:10:23 PM PST 24 | Jan 10 01:12:56 PM PST 24 | 41613077274 ps | ||
| T317 | /workspace/coverage/default/80.rv_timer_random.3268764701 | Jan 10 01:09:03 PM PST 24 | Jan 10 01:14:33 PM PST 24 | 502605361456 ps | ||
| T551 | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.4151051904 | Jan 10 01:07:34 PM PST 24 | Jan 10 01:17:33 PM PST 24 | 47173301281 ps | ||
| T552 | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.512627103 | Jan 10 01:08:45 PM PST 24 | Jan 10 01:22:57 PM PST 24 | 118577457164 ps | ||
| T553 | /workspace/coverage/default/97.rv_timer_random.574802950 | Jan 10 01:09:25 PM PST 24 | Jan 10 01:14:32 PM PST 24 | 277446472876 ps | ||
| T554 | /workspace/coverage/default/8.rv_timer_disabled.3599598139 | Jan 10 01:07:54 PM PST 24 | Jan 10 01:12:59 PM PST 24 | 158495970812 ps | ||
| T555 | /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3841398743 | Jan 10 01:09:16 PM PST 24 | Jan 10 01:13:41 PM PST 24 | 20117922746 ps | ||
| T364 | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2893288405 | Jan 10 01:07:40 PM PST 24 | Jan 10 01:23:54 PM PST 24 | 1556390943311 ps | ||
| T350 | /workspace/coverage/default/7.rv_timer_random.1494332938 | Jan 10 01:07:48 PM PST 24 | Jan 10 01:19:16 PM PST 24 | 536216478477 ps | ||
| T556 | /workspace/coverage/default/40.rv_timer_disabled.3924940831 | Jan 10 01:09:10 PM PST 24 | Jan 10 01:12:27 PM PST 24 | 238220661031 ps | ||
| T557 | /workspace/coverage/default/128.rv_timer_random.2016920223 | Jan 10 01:09:20 PM PST 24 | Jan 10 01:37:37 PM PST 24 | 259746825842 ps | ||
| T197 | /workspace/coverage/default/4.rv_timer_random_reset.1071799085 | Jan 10 01:07:45 PM PST 24 | Jan 10 01:10:11 PM PST 24 | 94675721152 ps | ||
| T331 | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.351227408 | Jan 10 01:08:02 PM PST 24 | Jan 10 01:10:23 PM PST 24 | 49754363973 ps | ||
| T273 | /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.721740781 | Jan 10 01:07:46 PM PST 24 | Jan 10 01:22:43 PM PST 24 | 128041285956 ps | ||
| T558 | /workspace/coverage/default/32.rv_timer_stress_all.30201911 | Jan 10 01:08:58 PM PST 24 | Jan 10 01:10:25 PM PST 24 | 24151459134 ps | ||
| T559 | /workspace/coverage/default/16.rv_timer_stress_all.523585450 | Jan 10 01:08:13 PM PST 24 | Jan 10 01:14:16 PM PST 24 | 680355334784 ps | ||
| T365 | /workspace/coverage/default/25.rv_timer_stress_all.1727517512 | Jan 10 01:08:52 PM PST 24 | Jan 10 01:19:41 PM PST 24 | 1162121804511 ps | ||
| T560 | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.806400953 | Jan 10 01:07:32 PM PST 24 | Jan 10 01:09:03 PM PST 24 | 3474882521 ps | ||
| T357 | /workspace/coverage/default/105.rv_timer_random.3934246053 | Jan 10 01:09:41 PM PST 24 | Jan 10 01:19:16 PM PST 24 | 324456325924 ps | ||
| T353 | /workspace/coverage/default/50.rv_timer_random.1262460570 | Jan 10 01:09:10 PM PST 24 | Jan 10 01:14:24 PM PST 24 | 231820485796 ps | ||
| T226 | /workspace/coverage/default/1.rv_timer_stress_all.4234154627 | Jan 10 01:07:30 PM PST 24 | Jan 10 01:37:51 PM PST 24 | 1807449002269 ps | ||
| T283 | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4249995916 | Jan 10 01:09:27 PM PST 24 | Jan 10 01:14:18 PM PST 24 | 232798036804 ps | ||
| T561 | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1699954055 | Jan 10 01:07:44 PM PST 24 | Jan 10 01:09:12 PM PST 24 | 3565030774 ps | ||
| T562 | /workspace/coverage/default/43.rv_timer_disabled.2528071926 | Jan 10 01:09:05 PM PST 24 | Jan 10 01:14:06 PM PST 24 | 844979170517 ps | ||
| T161 | /workspace/coverage/default/178.rv_timer_random.2307830751 | Jan 10 01:09:39 PM PST 24 | Jan 10 01:27:41 PM PST 24 | 317179314433 ps | ||
| T563 | /workspace/coverage/default/40.rv_timer_random_reset.623980996 | Jan 10 01:15:58 PM PST 24 | Jan 10 01:16:03 PM PST 24 | 55187765 ps | ||
| T564 | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3096035718 | Jan 10 01:08:57 PM PST 24 | Jan 10 01:13:31 PM PST 24 | 919957234006 ps | ||
| T565 | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1270593489 | Jan 10 01:07:39 PM PST 24 | Jan 10 01:10:56 PM PST 24 | 59835181679 ps | ||
| T566 | /workspace/coverage/default/111.rv_timer_random.2235366440 | Jan 10 01:09:23 PM PST 24 | Jan 10 01:40:04 PM PST 24 | 116825195880 ps | ||
| T347 | /workspace/coverage/default/149.rv_timer_random.2193361323 | Jan 10 01:09:21 PM PST 24 | Jan 10 01:34:31 PM PST 24 | 1422741605614 ps | ||
| T202 | /workspace/coverage/default/69.rv_timer_random.478604458 | Jan 10 01:09:11 PM PST 24 | Jan 10 01:23:11 PM PST 24 | 510562907320 ps | ||
| T253 | /workspace/coverage/default/115.rv_timer_random.1383062676 | Jan 10 01:09:27 PM PST 24 | Jan 10 01:23:24 PM PST 24 | 290229256155 ps | ||
| T567 | /workspace/coverage/default/47.rv_timer_disabled.184020108 | Jan 10 01:08:59 PM PST 24 | Jan 10 01:11:04 PM PST 24 | 66445177234 ps | ||
| T355 | /workspace/coverage/default/14.rv_timer_random.3105292507 | Jan 10 01:08:48 PM PST 24 | Jan 10 01:17:57 PM PST 24 | 120709101304 ps | ||
| T568 | /workspace/coverage/default/95.rv_timer_random.1437414445 | Jan 10 01:09:23 PM PST 24 | Jan 10 01:11:55 PM PST 24 | 45616163909 ps | ||
| T296 | /workspace/coverage/default/152.rv_timer_random.2659414790 | Jan 10 01:09:37 PM PST 24 | Jan 10 01:14:34 PM PST 24 | 742740287107 ps | ||
| T569 | /workspace/coverage/default/154.rv_timer_random.473168890 | Jan 10 01:09:42 PM PST 24 | Jan 10 01:12:12 PM PST 24 | 184638344714 ps | ||
| T570 | /workspace/coverage/default/39.rv_timer_disabled.355264544 | Jan 10 01:10:15 PM PST 24 | Jan 10 01:13:06 PM PST 24 | 241334640911 ps | ||
| T571 | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1412908081 | Jan 10 01:08:31 PM PST 24 | Jan 10 01:19:15 PM PST 24 | 104416330210 ps | ||
| T572 | /workspace/coverage/default/17.rv_timer_random_reset.4179071907 | Jan 10 01:08:11 PM PST 24 | Jan 10 01:09:48 PM PST 24 | 14436746 ps | ||
| T573 | /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.849631246 | Jan 10 01:08:44 PM PST 24 | Jan 10 01:13:28 PM PST 24 | 309441385632 ps | ||
| T288 | /workspace/coverage/default/103.rv_timer_random.782046696 | Jan 10 01:09:31 PM PST 24 | Jan 10 01:14:41 PM PST 24 | 582186196785 ps | ||
| T574 | /workspace/coverage/default/21.rv_timer_disabled.2057627278 | Jan 10 01:10:28 PM PST 24 | Jan 10 01:13:25 PM PST 24 | 263120563967 ps | ||
| T575 | /workspace/coverage/default/38.rv_timer_random.934834529 | Jan 10 01:09:02 PM PST 24 | Jan 10 01:15:16 PM PST 24 | 62733754099 ps | ||
| T576 | /workspace/coverage/default/55.rv_timer_random.3637091714 | Jan 10 01:09:06 PM PST 24 | Jan 10 01:12:06 PM PST 24 | 131801220475 ps | ||
| T577 | /workspace/coverage/default/16.rv_timer_random_reset.1903065054 | Jan 10 01:08:25 PM PST 24 | Jan 10 01:12:19 PM PST 24 | 31037387083 ps |
| Test location | /workspace/coverage/default/156.rv_timer_random.882352411 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 498586766719 ps |
| CPU time | 358.4 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:16:26 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-d79ce123-452a-4090-90bd-85ac62ba662b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882352411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.882352411 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.291364500 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 335546593212 ps |
| CPU time | 432.75 seconds |
| Started | Jan 10 01:10:19 PM PST 24 |
| Finished | Jan 10 01:18:47 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-7c205945-8350-458e-b474-4980bc8e6a97 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291364500 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.291364500 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.84867717 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2252555639443 ps |
| CPU time | 1758.85 seconds |
| Started | Jan 10 01:08:35 PM PST 24 |
| Finished | Jan 10 01:39:08 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-baa2fa3a-5a2b-4b82-88f9-289e04fd47f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84867717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.84867717 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.2810786569 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 586384769387 ps |
| CPU time | 1532.27 seconds |
| Started | Jan 10 01:07:46 PM PST 24 |
| Finished | Jan 10 01:34:43 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-1a126cfc-5107-4b8a-9da4-1871d4fc1113 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810786569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 2810786569 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1623775494 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 176518355 ps |
| CPU time | 1.11 seconds |
| Started | Jan 10 01:01:18 PM PST 24 |
| Finished | Jan 10 01:02:44 PM PST 24 |
| Peak memory | 195596 kb |
| Host | smart-c18b0369-0e8c-4ffc-be36-dffc6e421e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623775494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.1623775494 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.1495633370 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 575134732986 ps |
| CPU time | 1804.9 seconds |
| Started | Jan 10 01:07:44 PM PST 24 |
| Finished | Jan 10 01:39:10 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-6bfaa331-595f-4375-88dd-718736115fa6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495633370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 1495633370 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.2253062804 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1893813718176 ps |
| CPU time | 1829.74 seconds |
| Started | Jan 10 01:10:21 PM PST 24 |
| Finished | Jan 10 01:42:07 PM PST 24 |
| Peak memory | 190696 kb |
| Host | smart-7e624c95-6d7f-4c2b-b664-2fc14b18660a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253062804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .2253062804 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.2810325907 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1208496874570 ps |
| CPU time | 2823.18 seconds |
| Started | Jan 10 01:07:35 PM PST 24 |
| Finished | Jan 10 01:56:14 PM PST 24 |
| Peak memory | 191100 kb |
| Host | smart-459d1353-4b55-48dd-a610-03a057b7a023 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810325907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 2810325907 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.2342125979 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5991914168795 ps |
| CPU time | 2558.46 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:52:47 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-94ed117d-f7d8-4521-8f19-3bb63dea6ac3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342125979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .2342125979 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.4234154627 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1807449002269 ps |
| CPU time | 1740.03 seconds |
| Started | Jan 10 01:07:30 PM PST 24 |
| Finished | Jan 10 01:37:51 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-734c5e09-ab7e-4a07-bbf7-fdc59e24b1fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234154627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 4234154627 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2006758399 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 36392428 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:49 PM PST 24 |
| Peak memory | 192356 kb |
| Host | smart-31ae72f0-cc87-4de8-a04e-0453ea4101cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006758399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.2006758399 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.4095241185 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2712629099078 ps |
| CPU time | 1976.12 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:42:54 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-05bc5cca-2179-4752-801c-ace4c8e23562 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095241185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .4095241185 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.378636618 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 451069957358 ps |
| CPU time | 3630.21 seconds |
| Started | Jan 10 01:08:23 PM PST 24 |
| Finished | Jan 10 02:10:10 PM PST 24 |
| Peak memory | 191228 kb |
| Host | smart-dc48e6df-37bb-481c-aa11-c0b6f49e2175 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378636618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all. 378636618 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.2461069787 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 61310983 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:07:41 PM PST 24 |
| Finished | Jan 10 01:09:06 PM PST 24 |
| Peak memory | 212860 kb |
| Host | smart-04fc51f2-e1a1-4721-8b47-781231a82320 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461069787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2461069787 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.1204901355 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 722722180114 ps |
| CPU time | 526.83 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:18:49 PM PST 24 |
| Peak memory | 191124 kb |
| Host | smart-fc5ec843-c97e-4f21-b64d-dc28ec9e24f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204901355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1204901355 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.3047754461 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 381810850432 ps |
| CPU time | 1397.78 seconds |
| Started | Jan 10 01:08:16 PM PST 24 |
| Finished | Jan 10 01:33:01 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-c0b456fd-772f-4a54-8b73-a733f8b6d767 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047754461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all .3047754461 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.3005051549 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1001539604334 ps |
| CPU time | 2256.86 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:48:05 PM PST 24 |
| Peak memory | 194212 kb |
| Host | smart-70943649-f1f7-457a-bb49-e5b0317f84fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005051549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3005051549 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.4240839288 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 534863272622 ps |
| CPU time | 583.26 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:20:51 PM PST 24 |
| Peak memory | 192052 kb |
| Host | smart-3b82fbe6-f64f-41a3-a0db-1bd8e10bc032 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240839288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .4240839288 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.3455840256 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 432650045779 ps |
| CPU time | 1472.15 seconds |
| Started | Jan 10 01:08:46 PM PST 24 |
| Finished | Jan 10 01:34:29 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-3f482435-818a-4b21-a0df-d5897bc0e1b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455840256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .3455840256 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.879044198 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 952537194348 ps |
| CPU time | 949.75 seconds |
| Started | Jan 10 01:10:17 PM PST 24 |
| Finished | Jan 10 01:27:25 PM PST 24 |
| Peak memory | 195128 kb |
| Host | smart-1735ac95-17f7-4bba-97af-7bc6b22fada9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879044198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all. 879044198 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.1557097912 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 97432315789 ps |
| CPU time | 168.23 seconds |
| Started | Jan 10 01:10:25 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-e545b93b-84fa-4925-8339-bf2f706673af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557097912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1557097912 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.4210277006 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 737938434164 ps |
| CPU time | 794.96 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:23:50 PM PST 24 |
| Peak memory | 191088 kb |
| Host | smart-43d1c2db-78f5-40f1-b40d-a4155ea2b7a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210277006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4210277006 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.3384944427 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 359248904697 ps |
| CPU time | 678.04 seconds |
| Started | Jan 10 01:09:28 PM PST 24 |
| Finished | Jan 10 01:21:54 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-dbc5b4f5-0d7f-46d7-9f9b-4c396dab493f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384944427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3384944427 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.3995336581 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 91935163248 ps |
| CPU time | 1872.06 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:41:40 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-3bfe5e64-a0f4-4853-b051-f9d9ebccb22c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995336581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3995336581 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.3716433727 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 211721672742 ps |
| CPU time | 748.66 seconds |
| Started | Jan 10 01:07:50 PM PST 24 |
| Finished | Jan 10 01:21:54 PM PST 24 |
| Peak memory | 191040 kb |
| Host | smart-a5150a6e-5fec-4dac-a1e0-e26a605c8a56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716433727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 3716433727 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.3751243944 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 154482499256 ps |
| CPU time | 229.16 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:14:31 PM PST 24 |
| Peak memory | 194236 kb |
| Host | smart-31165ea0-738d-4ad9-a45e-e92f0da199d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751243944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3751243944 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.3785062035 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 168925648570 ps |
| CPU time | 287.06 seconds |
| Started | Jan 10 01:09:36 PM PST 24 |
| Finished | Jan 10 01:15:29 PM PST 24 |
| Peak memory | 194064 kb |
| Host | smart-37173655-0557-4931-aa66-a27d618bc6ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785062035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3785062035 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.2683094791 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 270066858385 ps |
| CPU time | 846.8 seconds |
| Started | Jan 10 01:08:50 PM PST 24 |
| Finished | Jan 10 01:24:09 PM PST 24 |
| Peak memory | 191248 kb |
| Host | smart-c4a97114-a19d-460b-8c28-c42f9c7e7f26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683094791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .2683094791 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.2720030129 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 175311912603 ps |
| CPU time | 348.96 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:15:55 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-4b15d81d-30c8-4ea3-9029-25dc3e5b71b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720030129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2720030129 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.351227408 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 49754363973 ps |
| CPU time | 49.4 seconds |
| Started | Jan 10 01:08:02 PM PST 24 |
| Finished | Jan 10 01:10:23 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-92b59c83-5fe8-44e3-ad59-56a9ac4677ab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351227408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.rv_timer_cfg_update_on_fly.351227408 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.3246550054 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 579220829225 ps |
| CPU time | 432 seconds |
| Started | Jan 10 01:09:33 PM PST 24 |
| Finished | Jan 10 01:17:51 PM PST 24 |
| Peak memory | 191236 kb |
| Host | smart-932b7e15-f5b8-4455-ab07-418831f549b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246550054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3246550054 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.3533724565 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1334924415532 ps |
| CPU time | 962.75 seconds |
| Started | Jan 10 01:09:09 PM PST 24 |
| Finished | Jan 10 01:26:19 PM PST 24 |
| Peak memory | 190628 kb |
| Host | smart-b3c07f2e-3df0-4b3f-8c35-a5680e3e6d4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533724565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all .3533724565 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.1781264083 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 491231808591 ps |
| CPU time | 889.39 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:25:17 PM PST 24 |
| Peak memory | 193788 kb |
| Host | smart-34b38caf-f94a-4340-bb78-7be388e6dcba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781264083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1781264083 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.2656054831 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1190870214974 ps |
| CPU time | 408.34 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:17:20 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-b5e1e32c-6fd7-425b-9338-c2d06a952285 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656054831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2656054831 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.3153711743 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 948887114818 ps |
| CPU time | 900.81 seconds |
| Started | Jan 10 01:08:03 PM PST 24 |
| Finished | Jan 10 01:24:32 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-fa51eac5-a7ec-4e08-9026-d0379bdca968 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153711743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 3153711743 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.3027124210 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 265470517034 ps |
| CPU time | 440.94 seconds |
| Started | Jan 10 01:08:49 PM PST 24 |
| Finished | Jan 10 01:17:19 PM PST 24 |
| Peak memory | 190976 kb |
| Host | smart-6a86385a-f315-487e-83c3-d09685f93e57 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027124210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3027124210 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1096596016 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 282019649 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:53 PM PST 24 |
| Peak memory | 192168 kb |
| Host | smart-43fd76d8-53ea-4847-b0f8-252fdf804d4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096596016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.1096596016 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.324833406 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 139198107510 ps |
| CPU time | 325.63 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:15:59 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-fff17bd5-ef07-4b50-893b-d1c4e8d6f32d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324833406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.324833406 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.1580539805 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 708526267168 ps |
| CPU time | 315.27 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:15:57 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-4aa6757a-2f50-4e1f-8fa6-f328d141eca3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580539805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1580539805 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.576048320 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 645545548902 ps |
| CPU time | 490.46 seconds |
| Started | Jan 10 01:09:31 PM PST 24 |
| Finished | Jan 10 01:18:46 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-3c8f62bb-3434-483f-b4f1-8d73c2730610 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576048320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.576048320 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.336849387 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 621893274422 ps |
| CPU time | 930.56 seconds |
| Started | Jan 10 01:08:30 PM PST 24 |
| Finished | Jan 10 01:25:15 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-b2f47f59-86d3-43c6-980b-806524784cd1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336849387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.336849387 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.273515427 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 564219018569 ps |
| CPU time | 232.13 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:14:01 PM PST 24 |
| Peak memory | 191216 kb |
| Host | smart-cfacbf04-07ee-40a8-9eb3-2c2ddb588f98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273515427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.273515427 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.3957119781 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2004506483463 ps |
| CPU time | 1700.14 seconds |
| Started | Jan 10 01:08:49 PM PST 24 |
| Finished | Jan 10 01:38:21 PM PST 24 |
| Peak memory | 190600 kb |
| Host | smart-8278c2d5-902b-46b5-a63e-8bdd1bd83416 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957119781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all .3957119781 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.642174402 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 76165697623 ps |
| CPU time | 782.39 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:23:45 PM PST 24 |
| Peak memory | 194292 kb |
| Host | smart-a579ee0f-e795-4725-b4be-03eb893c0e67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642174402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.642174402 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.3076064055 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 250588463430 ps |
| CPU time | 328.43 seconds |
| Started | Jan 10 01:09:20 PM PST 24 |
| Finished | Jan 10 01:15:55 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-e561b604-3589-485f-934b-f901be20645f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076064055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3076064055 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.1724078776 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 565532783748 ps |
| CPU time | 390.08 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:16:40 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-eb7b5812-f199-4fc9-9b87-dcd685c77f7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724078776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1724078776 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.2978804959 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 130811286605 ps |
| CPU time | 1363.86 seconds |
| Started | Jan 10 01:09:19 PM PST 24 |
| Finished | Jan 10 01:33:10 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-7e10cd94-fc70-4a31-99c6-7ce35a308869 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978804959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2978804959 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.537226938 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 606858567861 ps |
| CPU time | 352.11 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:16:21 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-bfe26cea-40cd-4857-9a23-94bf1e175a63 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537226938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.537226938 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.2205515303 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 924532484811 ps |
| CPU time | 948.62 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:26:06 PM PST 24 |
| Peak memory | 195536 kb |
| Host | smart-d6510ed3-984b-4b8d-b2a9-d813f00a8a94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205515303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .2205515303 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.4056878435 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2597645177429 ps |
| CPU time | 1064.98 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:28:05 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-18c0b844-a947-4c54-8f1c-51a5072aba5b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056878435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.4056878435 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.2663865088 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2239954262470 ps |
| CPU time | 375.02 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:16:30 PM PST 24 |
| Peak memory | 191192 kb |
| Host | smart-0161d345-15fd-4a7b-97ad-4b73a1c5ca90 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663865088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2663865088 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.1262460570 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 231820485796 ps |
| CPU time | 246.22 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 194228 kb |
| Host | smart-db95773d-4de9-407d-b4d5-39ea3fa42921 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262460570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1262460570 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.3394517394 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 178013920006 ps |
| CPU time | 309.91 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:15:18 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-fe016f86-3bd2-4cfd-b717-6333d5a6947a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394517394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3394517394 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.3634544441 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 155580630458 ps |
| CPU time | 360.5 seconds |
| Started | Jan 10 01:07:19 PM PST 24 |
| Finished | Jan 10 01:14:40 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-27aa0cb1-757c-4143-a21c-81dfbff77839 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634544441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3634544441 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.2541281951 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 322095150125 ps |
| CPU time | 468.21 seconds |
| Started | Jan 10 01:07:33 PM PST 24 |
| Finished | Jan 10 01:16:46 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-80afc4f7-2da8-4bdb-90d4-9a216e5643f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541281951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .2541281951 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.3199004438 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 202449666951 ps |
| CPU time | 330.45 seconds |
| Started | Jan 10 01:09:19 PM PST 24 |
| Finished | Jan 10 01:15:55 PM PST 24 |
| Peak memory | 193800 kb |
| Host | smart-0d0cc007-5328-425c-ae0c-adc32674f88d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199004438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3199004438 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.793721601 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 468853086503 ps |
| CPU time | 266.24 seconds |
| Started | Jan 10 01:09:17 PM PST 24 |
| Finished | Jan 10 01:14:50 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-c2165513-b7c3-4502-823e-d6b58f4a097b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793721601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.793721601 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.2183377352 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1288962049281 ps |
| CPU time | 829.91 seconds |
| Started | Jan 10 01:09:16 PM PST 24 |
| Finished | Jan 10 01:24:16 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-49e3cdbf-3e6d-4c3e-bbab-9e669304cc4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183377352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2183377352 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.3930536770 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1354934777313 ps |
| CPU time | 513.13 seconds |
| Started | Jan 10 01:09:41 PM PST 24 |
| Finished | Jan 10 01:19:21 PM PST 24 |
| Peak memory | 195000 kb |
| Host | smart-d9452797-bf3d-4b30-8e50-6b9335ddba7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930536770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3930536770 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.3741425290 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 287361200031 ps |
| CPU time | 316.21 seconds |
| Started | Jan 10 01:09:45 PM PST 24 |
| Finished | Jan 10 01:16:08 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-1b7647f4-7a5e-4bb1-ac61-5b6b359c0ad2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741425290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3741425290 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.1512226153 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 500025319244 ps |
| CPU time | 307.57 seconds |
| Started | Jan 10 01:09:20 PM PST 24 |
| Finished | Jan 10 01:15:34 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-63b2322a-110c-4bc3-be07-c850e68534f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512226153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1512226153 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.3014476172 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 445095135556 ps |
| CPU time | 199.35 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:13:51 PM PST 24 |
| Peak memory | 194460 kb |
| Host | smart-432b62de-cbe6-48f1-ad46-46d92c4a934e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014476172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3014476172 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.2867497374 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 97303290520 ps |
| CPU time | 175.76 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 191100 kb |
| Host | smart-89512fbb-fbe2-44eb-b800-da8d9b977392 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867497374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2867497374 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.2000131982 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 253721326730 ps |
| CPU time | 96.63 seconds |
| Started | Jan 10 01:08:27 PM PST 24 |
| Finished | Jan 10 01:11:27 PM PST 24 |
| Peak memory | 191012 kb |
| Host | smart-6cf881b2-4a98-4f3d-a99f-3e21b3b1a895 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000131982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2000131982 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.1928155532 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 78362092432 ps |
| CPU time | 120.74 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:12:31 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-bb1a312d-bd96-463b-ae98-31288916f4dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928155532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1928155532 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.1518368887 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 129068366963 ps |
| CPU time | 221.19 seconds |
| Started | Jan 10 01:09:18 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 191224 kb |
| Host | smart-f41658aa-9871-457d-ab6a-1cf2b42898b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518368887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1518368887 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.1031810314 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 102216434409 ps |
| CPU time | 105.05 seconds |
| Started | Jan 10 01:08:39 PM PST 24 |
| Finished | Jan 10 01:11:37 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-cc39889e-0ae6-4a91-ae5f-1f17530ef955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031810314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1031810314 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.478604458 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 510562907320 ps |
| CPU time | 771.82 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:23:11 PM PST 24 |
| Peak memory | 194376 kb |
| Host | smart-fd4578ac-dc99-48a2-8e16-c86a19c3618b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478604458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.478604458 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1048824058 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 774889931 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:01:58 PM PST 24 |
| Finished | Jan 10 01:03:25 PM PST 24 |
| Peak memory | 183740 kb |
| Host | smart-155fda21-fd63-4d56-b7fd-1d9b3abe00fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048824058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.1048824058 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.2469288071 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 595018501680 ps |
| CPU time | 544.35 seconds |
| Started | Jan 10 01:07:26 PM PST 24 |
| Finished | Jan 10 01:17:58 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-9a37dcbd-99b1-4423-8e5e-de9229acd0bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469288071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2469288071 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1664388160 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 10845377468 ps |
| CPU time | 19.2 seconds |
| Started | Jan 10 01:07:34 PM PST 24 |
| Finished | Jan 10 01:09:26 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-ea6bb356-f5d5-4cf6-a6ec-4c0652fad624 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664388160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.1664388160 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.2105002028 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 149557005451 ps |
| CPU time | 216.01 seconds |
| Started | Jan 10 01:07:34 PM PST 24 |
| Finished | Jan 10 01:12:35 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-bee0ba22-3e14-4114-ab34-95ed2ed5b61a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105002028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2105002028 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.782046696 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 582186196785 ps |
| CPU time | 245.38 seconds |
| Started | Jan 10 01:09:31 PM PST 24 |
| Finished | Jan 10 01:14:41 PM PST 24 |
| Peak memory | 193824 kb |
| Host | smart-89b453d2-a518-4ece-b61e-abb486bada0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782046696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.782046696 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.248968187 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 90231571687 ps |
| CPU time | 251.91 seconds |
| Started | Jan 10 01:09:13 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 191104 kb |
| Host | smart-cdd5e524-cdf0-4dd6-b2cb-3d2021ee64c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248968187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.248968187 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.2207661259 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 307001834292 ps |
| CPU time | 200.65 seconds |
| Started | Jan 10 01:07:31 PM PST 24 |
| Finished | Jan 10 01:12:12 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-35d0dfec-9026-44d8-872d-992e85fc8b3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207661259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2207661259 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.3291173128 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 515393193350 ps |
| CPU time | 397.69 seconds |
| Started | Jan 10 01:09:19 PM PST 24 |
| Finished | Jan 10 01:17:03 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-22536479-d207-43fd-b94c-3e66238b7bb2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291173128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3291173128 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.112162695 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 105342310338 ps |
| CPU time | 117.39 seconds |
| Started | Jan 10 01:07:41 PM PST 24 |
| Finished | Jan 10 01:11:00 PM PST 24 |
| Peak memory | 191048 kb |
| Host | smart-94816b60-8b43-403b-9ae7-10179ee3e4f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112162695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.112162695 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.1880286657 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 453362470887 ps |
| CPU time | 182.47 seconds |
| Started | Jan 10 01:09:28 PM PST 24 |
| Finished | Jan 10 01:13:38 PM PST 24 |
| Peak memory | 191048 kb |
| Host | smart-8b80fd8e-dd39-4c0e-9af2-7dd17253d8e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880286657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1880286657 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.3105292507 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 120709101304 ps |
| CPU time | 478.6 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:17:57 PM PST 24 |
| Peak memory | 190648 kb |
| Host | smart-fcb0b4ae-4ebd-4e54-a018-acc36baa405d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105292507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3105292507 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.3516634166 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 540200078588 ps |
| CPU time | 274.1 seconds |
| Started | Jan 10 01:09:18 PM PST 24 |
| Finished | Jan 10 01:14:57 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-63698e73-5f1b-4744-b2b4-72a9f50c829c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516634166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3516634166 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.2193361323 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1422741605614 ps |
| CPU time | 1444.13 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:34:31 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-d0205f19-d5f6-4b25-bf47-59df233fa607 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193361323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2193361323 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.495432317 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 385983142346 ps |
| CPU time | 1044.77 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:27:52 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-808aaac1-f8bd-44fd-a4c0-b15244c80ebf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495432317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.495432317 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.2002247605 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 116965000277 ps |
| CPU time | 1980.06 seconds |
| Started | Jan 10 01:09:15 PM PST 24 |
| Finished | Jan 10 01:43:23 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-f26647e7-65a6-4ebe-bcfd-e95eaf9c8a12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002247605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2002247605 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.347785521 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 120662071199 ps |
| CPU time | 96.02 seconds |
| Started | Jan 10 01:08:11 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-c60a840d-f754-48db-85e7-31f6ed148952 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347785521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.347785521 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.1823159463 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 26992194177 ps |
| CPU time | 71.85 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:11:47 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-876db637-3be1-421b-9b5c-94ff9d7dd4d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823159463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1823159463 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.3421187667 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 166148723019 ps |
| CPU time | 122.84 seconds |
| Started | Jan 10 01:09:43 PM PST 24 |
| Finished | Jan 10 01:12:52 PM PST 24 |
| Peak memory | 193428 kb |
| Host | smart-0cfdfc8c-1e11-4d77-b701-1d496222ea00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421187667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3421187667 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1318336875 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 384995147470 ps |
| CPU time | 613.68 seconds |
| Started | Jan 10 01:08:47 PM PST 24 |
| Finished | Jan 10 01:20:11 PM PST 24 |
| Peak memory | 183012 kb |
| Host | smart-a81798ec-9c4d-485c-8985-d7bd2d912b94 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318336875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1318336875 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3810883573 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 106542161878 ps |
| CPU time | 196.9 seconds |
| Started | Jan 10 01:08:49 PM PST 24 |
| Finished | Jan 10 01:13:15 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-54cf3402-58a7-4376-9a81-dad1325346b1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810883573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.3810883573 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.614669849 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 58754898586 ps |
| CPU time | 555.07 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:19:34 PM PST 24 |
| Peak memory | 205848 kb |
| Host | smart-f77f010c-b364-49bb-8dd5-f3ee23df3d83 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614669849 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.614669849 |
| Directory | /workspace/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.2759744432 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 537593165176 ps |
| CPU time | 888.12 seconds |
| Started | Jan 10 01:10:24 PM PST 24 |
| Finished | Jan 10 01:26:29 PM PST 24 |
| Peak memory | 194460 kb |
| Host | smart-3d41f546-aae4-4484-bb4c-c843dc9e7980 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759744432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .2759744432 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.2804950189 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 71652324920 ps |
| CPU time | 139.85 seconds |
| Started | Jan 10 01:09:05 PM PST 24 |
| Finished | Jan 10 01:12:31 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-4bd527c5-fe11-47fb-802f-5e1d501c58fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804950189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2804950189 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.3209887076 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 479254072913 ps |
| CPU time | 2588.6 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:53:20 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-43b34469-50c4-4575-b141-39c6691d79e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209887076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3209887076 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2894758138 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 16142299 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:01:10 PM PST 24 |
| Finished | Jan 10 01:02:51 PM PST 24 |
| Peak memory | 183428 kb |
| Host | smart-e5d0448d-68a6-4d64-809c-b848e091900a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894758138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.2894758138 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.555639755 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 402170336 ps |
| CPU time | 1.52 seconds |
| Started | Jan 10 01:01:03 PM PST 24 |
| Finished | Jan 10 01:02:26 PM PST 24 |
| Peak memory | 183520 kb |
| Host | smart-71f53203-fb47-4eee-9b03-f0cc268cc48b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555639755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b ash.555639755 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4256106817 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 39758448 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:01:20 PM PST 24 |
| Finished | Jan 10 01:02:51 PM PST 24 |
| Peak memory | 183332 kb |
| Host | smart-75c634a7-600c-47f6-bf03-ade0a22e3e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256106817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.4256106817 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.104725671 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 23968911 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:01:55 PM PST 24 |
| Finished | Jan 10 01:03:22 PM PST 24 |
| Peak memory | 191700 kb |
| Host | smart-782cef01-7754-42c3-9c16-d4a706101f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104725671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim er_same_csr_outstanding.104725671 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.677810728 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 175925379 ps |
| CPU time | 1.78 seconds |
| Started | Jan 10 01:01:06 PM PST 24 |
| Finished | Jan 10 01:02:37 PM PST 24 |
| Peak memory | 197956 kb |
| Host | smart-6c2ea12e-f9ba-4f41-8190-cfdaef0b3dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677810728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.677810728 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2415948398 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 84968359 ps |
| CPU time | 0.8 seconds |
| Started | Jan 10 01:01:02 PM PST 24 |
| Finished | Jan 10 01:02:30 PM PST 24 |
| Peak memory | 193852 kb |
| Host | smart-bfd61466-aafb-4fe2-8f39-6413f1ee41c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415948398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.2415948398 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.952220604 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 48055178 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:10 PM PST 24 |
| Finished | Jan 10 01:02:36 PM PST 24 |
| Peak memory | 183312 kb |
| Host | smart-be3f5b95-3f48-4547-8fc7-de4bf985d068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952220604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re set.952220604 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2570904011 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 29970386 ps |
| CPU time | 1.35 seconds |
| Started | Jan 10 01:01:28 PM PST 24 |
| Finished | Jan 10 01:02:56 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-c1b8527a-a79e-4677-ad83-fff0ad93a93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570904011 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2570904011 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.483667975 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 23526519 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:03 PM PST 24 |
| Finished | Jan 10 01:02:25 PM PST 24 |
| Peak memory | 182792 kb |
| Host | smart-3b3d5bdb-b530-446b-a440-d22fa33894fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483667975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.483667975 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2485567352 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 75552384 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:29 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 182892 kb |
| Host | smart-efb0c656-5d2a-4680-964c-49a73d821842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485567352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2485567352 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2298882864 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 375117694 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:01:14 PM PST 24 |
| Finished | Jan 10 01:02:41 PM PST 24 |
| Peak memory | 193680 kb |
| Host | smart-cbb70de6-2ef9-4ea7-859b-6626f5226243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298882864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.2298882864 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4149434192 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 22378136 ps |
| CPU time | 1.01 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:53 PM PST 24 |
| Peak memory | 197412 kb |
| Host | smart-583759bb-0e48-426c-9659-b15dc9bd09e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149434192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4149434192 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1224877162 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 144567569 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:01:04 PM PST 24 |
| Finished | Jan 10 01:02:37 PM PST 24 |
| Peak memory | 193888 kb |
| Host | smart-7f73a7d5-196a-4eb9-97ea-956eba953b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224877162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.1224877162 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2722356249 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 34216527 ps |
| CPU time | 1.66 seconds |
| Started | Jan 10 01:01:57 PM PST 24 |
| Finished | Jan 10 01:03:32 PM PST 24 |
| Peak memory | 198160 kb |
| Host | smart-89070379-0609-4635-99c9-176a282bf5b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722356249 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2722356249 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.914297119 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 51431171 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:01:32 PM PST 24 |
| Finished | Jan 10 01:02:57 PM PST 24 |
| Peak memory | 183332 kb |
| Host | smart-3dfafdca-5e50-4428-9ef5-d17dccfa73ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914297119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.914297119 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.775538040 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 15705646 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:32 PM PST 24 |
| Finished | Jan 10 01:02:58 PM PST 24 |
| Peak memory | 182828 kb |
| Host | smart-8324698a-5fa5-4fb5-911e-ef9fe521dbb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775538040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.775538040 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2780677237 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 122258471 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:01:32 PM PST 24 |
| Finished | Jan 10 01:03:07 PM PST 24 |
| Peak memory | 193572 kb |
| Host | smart-c6e8e9d6-ee6f-413b-9e95-cc3a1c4cee0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780677237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.2780677237 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4014102651 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 365776273 ps |
| CPU time | 1.96 seconds |
| Started | Jan 10 01:01:53 PM PST 24 |
| Finished | Jan 10 01:03:32 PM PST 24 |
| Peak memory | 198112 kb |
| Host | smart-6cb79e99-74e9-4a2a-90af-ce96cf9bd852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014102651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4014102651 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1044462552 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 84568710 ps |
| CPU time | 1.08 seconds |
| Started | Jan 10 01:01:50 PM PST 24 |
| Finished | Jan 10 01:03:16 PM PST 24 |
| Peak memory | 195456 kb |
| Host | smart-f8ab2619-151b-4fca-a088-333b1b77e69f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044462552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.1044462552 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2044305715 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 24779849 ps |
| CPU time | 0.71 seconds |
| Started | Jan 10 01:01:39 PM PST 24 |
| Finished | Jan 10 01:03:13 PM PST 24 |
| Peak memory | 195916 kb |
| Host | smart-54ce2b59-2e86-49c3-beea-9aceabc72959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044305715 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2044305715 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2958850689 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 141018483 ps |
| CPU time | 2.5 seconds |
| Started | Jan 10 01:01:31 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 198096 kb |
| Host | smart-6e96e26c-084c-4154-beb1-8064e83582be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958850689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2958850689 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3163886007 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 41764974 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:01:59 PM PST 24 |
| Finished | Jan 10 01:03:56 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-356e09c7-cd95-42da-8950-c73417b9aa25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163886007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3163886007 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.36072849 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 25245822 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:02:00 PM PST 24 |
| Finished | Jan 10 01:03:32 PM PST 24 |
| Peak memory | 192568 kb |
| Host | smart-9a2e303f-62d8-42b5-bc52-511e29fed24d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_tim er_same_csr_outstanding.36072849 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2004395446 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 59292385 ps |
| CPU time | 1.24 seconds |
| Started | Jan 10 01:02:01 PM PST 24 |
| Finished | Jan 10 01:03:32 PM PST 24 |
| Peak memory | 198040 kb |
| Host | smart-2c54297f-da9d-4ccf-922c-037dd3428af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004395446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2004395446 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4141767429 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 164397270 ps |
| CPU time | 0.79 seconds |
| Started | Jan 10 01:04:45 PM PST 24 |
| Finished | Jan 10 01:06:17 PM PST 24 |
| Peak memory | 183212 kb |
| Host | smart-ca401288-befb-47b6-8b34-545c811c37b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141767429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.4141767429 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2492161074 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 43700833 ps |
| CPU time | 0.84 seconds |
| Started | Jan 10 01:01:56 PM PST 24 |
| Finished | Jan 10 01:03:27 PM PST 24 |
| Peak memory | 197112 kb |
| Host | smart-76a95da2-a04a-4c3c-b963-ab5c1f5e9b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492161074 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2492161074 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1706296742 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 14588584 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:01:33 PM PST 24 |
| Finished | Jan 10 01:03:11 PM PST 24 |
| Peak memory | 181960 kb |
| Host | smart-4c050d9d-5e0a-4df2-8fc3-17677dc69b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706296742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1706296742 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.622823246 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 33330989 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:01:38 PM PST 24 |
| Finished | Jan 10 01:03:04 PM PST 24 |
| Peak memory | 193744 kb |
| Host | smart-9557c551-f4bf-4b4a-bd38-a11ad6b2bebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622823246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti mer_same_csr_outstanding.622823246 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1848705415 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 185156298 ps |
| CPU time | 2.8 seconds |
| Started | Jan 10 01:02:09 PM PST 24 |
| Finished | Jan 10 01:03:58 PM PST 24 |
| Peak memory | 198076 kb |
| Host | smart-66e75414-6bb5-4330-afbd-f36a1e0c1af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848705415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1848705415 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1833177520 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 124673898 ps |
| CPU time | 1.35 seconds |
| Started | Jan 10 01:02:01 PM PST 24 |
| Finished | Jan 10 01:04:01 PM PST 24 |
| Peak memory | 183612 kb |
| Host | smart-5f525ec6-2f34-4400-965a-c2670dd8db57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833177520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.1833177520 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2249889060 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 32297292 ps |
| CPU time | 1.45 seconds |
| Started | Jan 10 01:01:46 PM PST 24 |
| Finished | Jan 10 01:03:16 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-88640925-d26d-40a5-9ae4-00e54db102a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249889060 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2249889060 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3549617931 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 16753609 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:01:39 PM PST 24 |
| Finished | Jan 10 01:03:28 PM PST 24 |
| Peak memory | 183224 kb |
| Host | smart-4766ce63-d954-48a0-8d98-0891fbc55e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549617931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3549617931 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2372963092 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 307840918 ps |
| CPU time | 1.63 seconds |
| Started | Jan 10 01:02:06 PM PST 24 |
| Finished | Jan 10 01:03:42 PM PST 24 |
| Peak memory | 198032 kb |
| Host | smart-b8e7d822-b8cb-4f35-a41c-e6b9dac3f0ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372963092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2372963092 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1949549686 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 157279112 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:01:39 PM PST 24 |
| Finished | Jan 10 01:03:17 PM PST 24 |
| Peak memory | 193792 kb |
| Host | smart-2638b8a2-5272-4dd9-bb42-774dfe428e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949549686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.1949549686 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3966210431 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 13460260 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:58 PM PST 24 |
| Finished | Jan 10 01:03:45 PM PST 24 |
| Peak memory | 182652 kb |
| Host | smart-61ef0aa9-afeb-402c-a433-8da58c77c326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966210431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3966210431 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3830565411 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 16067414 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:57 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-754aa398-0118-4aec-b2a9-aec1ec168b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830565411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3830565411 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1637451953 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 20826621 ps |
| CPU time | 0.94 seconds |
| Started | Jan 10 01:01:34 PM PST 24 |
| Finished | Jan 10 01:03:14 PM PST 24 |
| Peak memory | 196952 kb |
| Host | smart-789bbd30-9e9f-49e7-8653-83af4b0f5fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637451953 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1637451953 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.365735435 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 12395707 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:52 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-4c4f36ff-c48f-435d-9e5b-ed336a79c9c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365735435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.365735435 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.893084005 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 116307873 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:01:27 PM PST 24 |
| Finished | Jan 10 01:03:12 PM PST 24 |
| Peak memory | 193780 kb |
| Host | smart-c1c99232-7812-4467-aa11-0354d816b455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893084005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti mer_same_csr_outstanding.893084005 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1439181876 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 32512943 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:03:16 PM PST 24 |
| Peak memory | 196304 kb |
| Host | smart-745f8b91-30ee-4c94-b8bb-9dbf80f48ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439181876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1439181876 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2206713570 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 135543871 ps |
| CPU time | 1.45 seconds |
| Started | Jan 10 01:01:38 PM PST 24 |
| Finished | Jan 10 01:03:03 PM PST 24 |
| Peak memory | 197388 kb |
| Host | smart-8b2235be-653e-4e26-9fde-a8b4797b0d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206713570 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2206713570 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2747002131 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 37424609 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:57 PM PST 24 |
| Finished | Jan 10 01:03:36 PM PST 24 |
| Peak memory | 183280 kb |
| Host | smart-109f152b-0814-4ec9-b833-f3405a77b32e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747002131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2747002131 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3176922863 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 21171898 ps |
| CPU time | 0.63 seconds |
| Started | Jan 10 01:02:02 PM PST 24 |
| Finished | Jan 10 01:03:30 PM PST 24 |
| Peak memory | 191736 kb |
| Host | smart-f5e12824-b670-4d0f-bcb2-7a703fa38c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176922863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.3176922863 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1520564782 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 86439636 ps |
| CPU time | 2.05 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:54 PM PST 24 |
| Peak memory | 198012 kb |
| Host | smart-005f2030-cc89-4535-899a-e9ee54501504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520564782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1520564782 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2465591776 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1179604213 ps |
| CPU time | 1.37 seconds |
| Started | Jan 10 01:01:57 PM PST 24 |
| Finished | Jan 10 01:03:25 PM PST 24 |
| Peak memory | 195576 kb |
| Host | smart-3bfbe86e-7800-4aa2-b6e2-a9300e0cbe9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465591776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.2465591776 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1873444707 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 28434615 ps |
| CPU time | 0.85 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:03:27 PM PST 24 |
| Peak memory | 197588 kb |
| Host | smart-22c99259-2b05-4655-aaa2-910014d026d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873444707 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1873444707 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.20891879 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 32635592 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 183112 kb |
| Host | smart-dfd24416-5376-48aa-a097-8a00f97d3d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.20891879 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3097690947 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 25638310 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:29 PM PST 24 |
| Finished | Jan 10 01:02:55 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-b25d51dc-e566-4e7d-9365-10692fb333de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097690947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3097690947 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2862081860 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 68188590 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 192436 kb |
| Host | smart-04833f79-a653-4b16-b74b-0563d8f587a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862081860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.2862081860 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.809541463 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 720392174 ps |
| CPU time | 1.81 seconds |
| Started | Jan 10 01:02:00 PM PST 24 |
| Finished | Jan 10 01:03:42 PM PST 24 |
| Peak memory | 198044 kb |
| Host | smart-3c6a177a-721b-4a9e-b99c-0515c954e4bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809541463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.809541463 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2563279325 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 352520623 ps |
| CPU time | 1.27 seconds |
| Started | Jan 10 01:02:00 PM PST 24 |
| Finished | Jan 10 01:03:28 PM PST 24 |
| Peak memory | 183504 kb |
| Host | smart-8911c14f-cc41-4ac0-8d3c-f38e633a8881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563279325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.2563279325 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.760714162 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 104472625 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:01:18 PM PST 24 |
| Finished | Jan 10 01:02:44 PM PST 24 |
| Peak memory | 192524 kb |
| Host | smart-de558f90-5a2e-4103-b171-5ad0d5ad940f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760714162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias ing.760714162 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3459952862 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 189560296 ps |
| CPU time | 2.59 seconds |
| Started | Jan 10 01:01:23 PM PST 24 |
| Finished | Jan 10 01:02:56 PM PST 24 |
| Peak memory | 193808 kb |
| Host | smart-c5ff4546-8322-4c0a-8a16-b63fe7afeec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459952862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.3459952862 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1808849000 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 14466556 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:01:23 PM PST 24 |
| Finished | Jan 10 01:02:51 PM PST 24 |
| Peak memory | 183252 kb |
| Host | smart-a504a7ee-ef01-42db-a13c-c0aac649b66a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808849000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.1808849000 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4274049049 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 77474429 ps |
| CPU time | 1.12 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:49 PM PST 24 |
| Peak memory | 198104 kb |
| Host | smart-14e7fab5-bfb7-497f-8b5b-f1674c12be7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274049049 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4274049049 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3086939610 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 14845678 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:01:15 PM PST 24 |
| Finished | Jan 10 01:02:46 PM PST 24 |
| Peak memory | 183228 kb |
| Host | smart-8473edec-262a-4c64-8d50-7f5e347f45e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086939610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3086939610 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2740828346 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 271608526 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:23 PM PST 24 |
| Finished | Jan 10 01:02:54 PM PST 24 |
| Peak memory | 183004 kb |
| Host | smart-8f863e30-d6a7-45ce-a0ce-1652e875c2d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740828346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2740828346 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.507988217 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 270359819 ps |
| CPU time | 0.69 seconds |
| Started | Jan 10 01:01:16 PM PST 24 |
| Finished | Jan 10 01:02:46 PM PST 24 |
| Peak memory | 192568 kb |
| Host | smart-29993a4b-2226-43ea-ab08-df1d53209204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507988217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim er_same_csr_outstanding.507988217 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2967801867 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 32139492 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:45 PM PST 24 |
| Peak memory | 195260 kb |
| Host | smart-e1f2d7fd-46a6-4394-af3e-eefe7336f56a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967801867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2967801867 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.256392294 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 111836706 ps |
| CPU time | 1.28 seconds |
| Started | Jan 10 01:01:16 PM PST 24 |
| Finished | Jan 10 01:02:58 PM PST 24 |
| Peak memory | 183808 kb |
| Host | smart-911a97e1-1cd6-4a53-b571-0460e5d69341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256392294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int g_err.256392294 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2362088335 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 205684685 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:02:00 PM PST 24 |
| Finished | Jan 10 01:03:32 PM PST 24 |
| Peak memory | 182788 kb |
| Host | smart-b70c533a-dfa6-455b-af1d-475e1d8c628c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362088335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2362088335 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4070933261 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 28211640 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:29 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 182896 kb |
| Host | smart-794c310a-d605-4af7-8f96-9c9265293ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070933261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.4070933261 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3646702169 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 14230645 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:57 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-fe4e4c57-c85f-4200-bca9-a694c2a85133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646702169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3646702169 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3792860293 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 47581556 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:32 PM PST 24 |
| Finished | Jan 10 01:02:58 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-d5003886-ab30-4e8f-9638-a7f8288d0443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792860293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3792860293 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1544838726 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 45721826 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:02:08 PM PST 24 |
| Finished | Jan 10 01:04:07 PM PST 24 |
| Peak memory | 182128 kb |
| Host | smart-77c18336-7ab4-4b84-b6f1-5500ff906609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544838726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1544838726 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3109316938 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 42644065 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:56 PM PST 24 |
| Finished | Jan 10 01:03:27 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-2631d155-33ec-4388-9e9f-22435867ff15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109316938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3109316938 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.114808109 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 14475072 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:45 PM PST 24 |
| Finished | Jan 10 01:03:20 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-8d2aa052-ce30-4ef6-8a50-590c3af35ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114808109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.114808109 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3179374967 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 13103570 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:47 PM PST 24 |
| Finished | Jan 10 01:03:29 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-f84fee2c-668d-41c6-aa2b-3befab9653fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179374967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3179374967 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4197002782 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 12355914 ps |
| CPU time | 0.57 seconds |
| Started | Jan 10 01:01:34 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 182012 kb |
| Host | smart-dd619b79-08d7-4fcd-8ac5-1bedaf155918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197002782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4197002782 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4196805577 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 91232356 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:48 PM PST 24 |
| Peak memory | 192448 kb |
| Host | smart-c7b90020-35cf-4a51-8ed9-e5bb6b322931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196805577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.4196805577 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4052338641 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 423111900 ps |
| CPU time | 3.61 seconds |
| Started | Jan 10 01:01:19 PM PST 24 |
| Finished | Jan 10 01:03:02 PM PST 24 |
| Peak memory | 191636 kb |
| Host | smart-c8b7b88b-f859-4ef1-b2a8-6cfc9d603689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052338641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.4052338641 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1502160957 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 42528426 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:33 PM PST 24 |
| Finished | Jan 10 01:03:07 PM PST 24 |
| Peak memory | 182748 kb |
| Host | smart-50300f94-5c30-4b0f-9360-a66b2417d8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502160957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.1502160957 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.241760312 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 15469488 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:01:13 PM PST 24 |
| Finished | Jan 10 01:02:43 PM PST 24 |
| Peak memory | 192172 kb |
| Host | smart-f98a70e3-286b-49b0-a6ea-c6343d48e972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241760312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim er_same_csr_outstanding.241760312 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1463684906 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 47582908 ps |
| CPU time | 2.49 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:50 PM PST 24 |
| Peak memory | 197984 kb |
| Host | smart-1ee345f4-b186-4602-b11b-b1c68e13ff71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463684906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1463684906 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1853196226 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 466492818 ps |
| CPU time | 1.35 seconds |
| Started | Jan 10 01:01:15 PM PST 24 |
| Finished | Jan 10 01:02:51 PM PST 24 |
| Peak memory | 195588 kb |
| Host | smart-7c7b52a9-48ca-47b2-bcc1-96e99a9c799c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853196226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.1853196226 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1117911233 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 12851222 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 182128 kb |
| Host | smart-3dd04f9a-4685-4bfd-8c1c-00a167dcb5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117911233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1117911233 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3771825345 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 27610508 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:02:04 PM PST 24 |
| Finished | Jan 10 01:03:43 PM PST 24 |
| Peak memory | 182548 kb |
| Host | smart-95904d8f-fdb1-455e-82c1-d48563120290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771825345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3771825345 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1376844080 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 14743830 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:01:33 PM PST 24 |
| Finished | Jan 10 01:03:07 PM PST 24 |
| Peak memory | 182552 kb |
| Host | smart-89745033-c5dd-451a-958e-03501d7122a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376844080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1376844080 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2460706191 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 41778681 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:27 PM PST 24 |
| Finished | Jan 10 01:03:05 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-5e46cbd5-c5fa-4e94-b0ca-6dc25012dee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460706191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2460706191 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.500382865 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 14763865 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:45 PM PST 24 |
| Finished | Jan 10 01:03:26 PM PST 24 |
| Peak memory | 182728 kb |
| Host | smart-f9effb98-560c-4315-a417-ea48de9b8ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500382865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.500382865 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2402353818 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 37416302 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:02:00 PM PST 24 |
| Finished | Jan 10 01:03:27 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-c060edd5-dfcf-419a-988a-c83491ad0343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402353818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2402353818 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2198338020 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 32768784 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:01:40 PM PST 24 |
| Finished | Jan 10 01:03:15 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-e30e8fb9-f0f4-4045-8301-22a85d1a76dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198338020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2198338020 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3542743621 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 14907454 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:01:53 PM PST 24 |
| Finished | Jan 10 01:03:40 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-40fbf06f-6652-4f07-9884-9fe6dd0d8f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542743621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3542743621 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.643619754 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 34157829 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:36 PM PST 24 |
| Finished | Jan 10 01:03:07 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-fd985617-b8ff-452c-87d1-9786e217c6d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643619754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.643619754 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3795319160 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 16656261 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:01:21 PM PST 24 |
| Finished | Jan 10 01:02:47 PM PST 24 |
| Peak memory | 192472 kb |
| Host | smart-01d3ab10-5ebd-42d2-ad7d-07d378ec01a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795319160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.3795319160 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2895254080 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 397858534 ps |
| CPU time | 1.51 seconds |
| Started | Jan 10 01:01:23 PM PST 24 |
| Finished | Jan 10 01:02:55 PM PST 24 |
| Peak memory | 191700 kb |
| Host | smart-3855a596-05fc-43dc-895f-02f553a02abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895254080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.2895254080 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2778512671 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 56739547 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:01:23 PM PST 24 |
| Finished | Jan 10 01:02:54 PM PST 24 |
| Peak memory | 183308 kb |
| Host | smart-91a3fe53-87f5-4431-9f48-bed0fdb55734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778512671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2778512671 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1392590850 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 11531384 ps |
| CPU time | 0.54 seconds |
| Started | Jan 10 01:01:16 PM PST 24 |
| Finished | Jan 10 01:02:43 PM PST 24 |
| Peak memory | 182720 kb |
| Host | smart-2c0d7fd4-4727-4628-af81-c9a183f9bb9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392590850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1392590850 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1196012976 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 22904670 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:15 PM PST 24 |
| Finished | Jan 10 01:02:45 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-9829f250-ff37-4afc-afa2-6f5a1663bac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196012976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1196012976 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3069407133 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 158216258 ps |
| CPU time | 0.59 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:44 PM PST 24 |
| Peak memory | 191728 kb |
| Host | smart-d64c1f64-24a6-443d-878f-232909ce0d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069407133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.3069407133 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2433414134 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 74544049 ps |
| CPU time | 1.98 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:50 PM PST 24 |
| Peak memory | 197380 kb |
| Host | smart-fa3ae617-2579-436c-aacc-9985b37f1abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433414134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2433414134 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2745351330 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 69058036 ps |
| CPU time | 1.07 seconds |
| Started | Jan 10 01:01:16 PM PST 24 |
| Finished | Jan 10 01:02:46 PM PST 24 |
| Peak memory | 195368 kb |
| Host | smart-a2f355d5-000a-491e-8160-59ca7973dc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745351330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.2745351330 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1984209982 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 19945536 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:01:41 PM PST 24 |
| Finished | Jan 10 01:03:15 PM PST 24 |
| Peak memory | 182160 kb |
| Host | smart-29f63a7f-393a-49cf-9374-63fe8ebd802f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984209982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1984209982 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3921231626 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 15784571 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-71a2cd2a-5c93-4839-a1de-18cc13fc2cfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921231626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3921231626 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1923392849 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 101246321 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:29 PM PST 24 |
| Finished | Jan 10 01:02:55 PM PST 24 |
| Peak memory | 182920 kb |
| Host | smart-8fb00d42-8309-4e11-81f9-9542aa19496a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923392849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1923392849 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1237994968 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 40710817 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:01:38 PM PST 24 |
| Finished | Jan 10 01:03:12 PM PST 24 |
| Peak memory | 182092 kb |
| Host | smart-16adfd7b-ef0a-442b-b3b9-b5a0c84cfd64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237994968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1237994968 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2289075753 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 14672029 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:32 PM PST 24 |
| Finished | Jan 10 01:02:57 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-f4817ceb-9822-4f53-b491-4ef129c35123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289075753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2289075753 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4089550305 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 16639414 ps |
| CPU time | 0.81 seconds |
| Started | Jan 10 01:01:15 PM PST 24 |
| Finished | Jan 10 01:02:45 PM PST 24 |
| Peak memory | 196404 kb |
| Host | smart-5a57ab05-2b50-44c1-b10c-2e5b6dcc5c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089550305 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4089550305 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2941345595 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 14426432 ps |
| CPU time | 0.58 seconds |
| Started | Jan 10 01:01:24 PM PST 24 |
| Finished | Jan 10 01:02:54 PM PST 24 |
| Peak memory | 183300 kb |
| Host | smart-3ab25c41-22f5-49a6-b851-47a8d5457b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941345595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2941345595 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.89605491 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 10302090 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:01:13 PM PST 24 |
| Finished | Jan 10 01:02:43 PM PST 24 |
| Peak memory | 182036 kb |
| Host | smart-e433418b-1e01-4b38-9d12-cbd93d445b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89605491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.89605491 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1485561117 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 18682848 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:44 PM PST 24 |
| Peak memory | 192460 kb |
| Host | smart-e04fcdef-15a8-4388-b6bb-1c07b759afb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485561117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.1485561117 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1863309126 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 258442392 ps |
| CPU time | 3.25 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:51 PM PST 24 |
| Peak memory | 198024 kb |
| Host | smart-8e034f93-0b7e-4aea-b83d-897c47118161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863309126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1863309126 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.428391545 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 898070280 ps |
| CPU time | 1.33 seconds |
| Started | Jan 10 01:01:13 PM PST 24 |
| Finished | Jan 10 01:02:43 PM PST 24 |
| Peak memory | 183540 kb |
| Host | smart-533c2b41-b23d-446c-9c43-bcb9a29be772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428391545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int g_err.428391545 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1833902451 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 25982033 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:01:20 PM PST 24 |
| Finished | Jan 10 01:02:47 PM PST 24 |
| Peak memory | 193560 kb |
| Host | smart-384c8519-af97-4544-bc73-3fe7f585b26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833902451 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1833902451 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3337107328 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 163953802 ps |
| CPU time | 0.55 seconds |
| Started | Jan 10 01:01:25 PM PST 24 |
| Finished | Jan 10 01:02:53 PM PST 24 |
| Peak memory | 182756 kb |
| Host | smart-27322dd5-225f-4bbb-a1ae-d539d926ce8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337107328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3337107328 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3524682672 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 42163665 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:01:19 PM PST 24 |
| Finished | Jan 10 01:02:51 PM PST 24 |
| Peak memory | 182124 kb |
| Host | smart-da4680ba-e603-40a9-8c9f-b3c671907998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524682672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3524682672 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1773573066 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 202281362 ps |
| CPU time | 0.64 seconds |
| Started | Jan 10 01:01:17 PM PST 24 |
| Finished | Jan 10 01:02:43 PM PST 24 |
| Peak memory | 192560 kb |
| Host | smart-63852360-dc05-4482-9ff4-1bb91be4508e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773573066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.1773573066 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.42378911 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 31378435 ps |
| CPU time | 1.41 seconds |
| Started | Jan 10 01:01:14 PM PST 24 |
| Finished | Jan 10 01:02:45 PM PST 24 |
| Peak memory | 198024 kb |
| Host | smart-dc56c3c3-c700-472c-b2fb-3b8c01c4a394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.42378911 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.841717218 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 23313332 ps |
| CPU time | 0.56 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:52 PM PST 24 |
| Peak memory | 183328 kb |
| Host | smart-e597b514-393c-457b-ad82-72c0fa834aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841717218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.841717218 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3512262653 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 51740061 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:01:25 PM PST 24 |
| Finished | Jan 10 01:02:53 PM PST 24 |
| Peak memory | 182128 kb |
| Host | smart-49e9fac9-789a-4e5c-9065-4d5a458cac70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512262653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3512262653 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3858144509 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 45518303 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:01:28 PM PST 24 |
| Finished | Jan 10 01:03:02 PM PST 24 |
| Peak memory | 192564 kb |
| Host | smart-bcb78be3-b5cf-4eac-9eac-2ab42fe69671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858144509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.3858144509 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.626814586 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 387350632 ps |
| CPU time | 1.87 seconds |
| Started | Jan 10 01:01:25 PM PST 24 |
| Finished | Jan 10 01:02:55 PM PST 24 |
| Peak memory | 198020 kb |
| Host | smart-0f54ff89-6682-489f-8171-fb3d3611398d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626814586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.626814586 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2865523512 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 16367816 ps |
| CPU time | 0.62 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:53 PM PST 24 |
| Peak memory | 193704 kb |
| Host | smart-e5ccc67f-283d-4065-9026-b0f45771e9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865523512 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2865523512 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2538804224 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 95526535 ps |
| CPU time | 0.7 seconds |
| Started | Jan 10 01:01:31 PM PST 24 |
| Finished | Jan 10 01:03:07 PM PST 24 |
| Peak memory | 192176 kb |
| Host | smart-99bfb929-61db-4ac0-b41d-c1633b7d7597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538804224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.2538804224 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.818037215 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 122684758 ps |
| CPU time | 1.37 seconds |
| Started | Jan 10 01:01:29 PM PST 24 |
| Finished | Jan 10 01:03:00 PM PST 24 |
| Peak memory | 195636 kb |
| Host | smart-d7acef0b-a118-48a3-8b6e-65b69c0befc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818037215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int g_err.818037215 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1379748452 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 40041588 ps |
| CPU time | 1.05 seconds |
| Started | Jan 10 01:01:57 PM PST 24 |
| Finished | Jan 10 01:03:30 PM PST 24 |
| Peak memory | 191752 kb |
| Host | smart-53bd41ea-ce12-4e5d-a257-a29a97a9ae48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379748452 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1379748452 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1646462051 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 31773157 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:02:00 PM PST 24 |
| Finished | Jan 10 01:03:27 PM PST 24 |
| Peak memory | 182700 kb |
| Host | smart-188dd218-e3c2-4384-85b3-21b145a60c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646462051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1646462051 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.828470942 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 63673215 ps |
| CPU time | 0.52 seconds |
| Started | Jan 10 01:01:30 PM PST 24 |
| Finished | Jan 10 01:02:59 PM PST 24 |
| Peak memory | 182524 kb |
| Host | smart-0526f32f-06e9-44c1-b5a9-2f3dafd77512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828470942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.828470942 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1007432615 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 197193404 ps |
| CPU time | 0.69 seconds |
| Started | Jan 10 01:01:31 PM PST 24 |
| Finished | Jan 10 01:02:58 PM PST 24 |
| Peak memory | 193656 kb |
| Host | smart-57a9414e-1f00-4177-bcc9-2a6aa9327680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007432615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.1007432615 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4021525287 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 413929773 ps |
| CPU time | 2.33 seconds |
| Started | Jan 10 01:01:26 PM PST 24 |
| Finished | Jan 10 01:02:54 PM PST 24 |
| Peak memory | 197956 kb |
| Host | smart-1a34df3e-f391-4085-8f32-8a399c53c0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021525287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4021525287 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3834846544 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2703215371658 ps |
| CPU time | 1236.18 seconds |
| Started | Jan 10 01:07:26 PM PST 24 |
| Finished | Jan 10 01:29:25 PM PST 24 |
| Peak memory | 182788 kb |
| Host | smart-3de59cef-c508-4483-9caa-097eb4ca35df |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834846544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3834846544 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.2512638828 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 50016969320 ps |
| CPU time | 66.62 seconds |
| Started | Jan 10 01:07:30 PM PST 24 |
| Finished | Jan 10 01:09:57 PM PST 24 |
| Peak memory | 183024 kb |
| Host | smart-929dfaa1-5930-44d1-808f-7c792354fc72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512638828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2512638828 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.2784428998 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 112792097 ps |
| CPU time | 0.73 seconds |
| Started | Jan 10 01:07:30 PM PST 24 |
| Finished | Jan 10 01:08:53 PM PST 24 |
| Peak memory | 190916 kb |
| Host | smart-cde1d16c-ca86-4022-8517-f6b5afe7be0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784428998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2784428998 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.337713846 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2384021548598 ps |
| CPU time | 746.68 seconds |
| Started | Jan 10 01:07:33 PM PST 24 |
| Finished | Jan 10 01:21:25 PM PST 24 |
| Peak memory | 191284 kb |
| Host | smart-1f7a4517-2d74-4e7c-84a7-d5cb141a26b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337713846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.337713846 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.4274745199 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 42972824245 ps |
| CPU time | 177.78 seconds |
| Started | Jan 10 01:07:26 PM PST 24 |
| Finished | Jan 10 01:11:55 PM PST 24 |
| Peak memory | 205808 kb |
| Host | smart-27a173cd-b635-4acf-a941-e7d97fc2a322 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274745199 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.4274745199 |
| Directory | /workspace/0.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.3921565074 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 157290752610 ps |
| CPU time | 33.6 seconds |
| Started | Jan 10 01:07:37 PM PST 24 |
| Finished | Jan 10 01:09:44 PM PST 24 |
| Peak memory | 183032 kb |
| Host | smart-de8aa756-a091-43ae-879f-a655934d5b98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921565074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3921565074 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.3692972114 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 44010480549 ps |
| CPU time | 25.94 seconds |
| Started | Jan 10 01:07:18 PM PST 24 |
| Finished | Jan 10 01:09:12 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-b84284a9-7e16-4ac2-8ef8-ba4b755552fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692972114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3692972114 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.2522703686 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1404052533 ps |
| CPU time | 1.21 seconds |
| Started | Jan 10 01:07:30 PM PST 24 |
| Finished | Jan 10 01:08:57 PM PST 24 |
| Peak memory | 214004 kb |
| Host | smart-ed3aa48d-326c-4552-aec1-a815be901e36 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522703686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2522703686 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2480657978 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 69819669582 ps |
| CPU time | 169.16 seconds |
| Started | Jan 10 01:07:30 PM PST 24 |
| Finished | Jan 10 01:11:41 PM PST 24 |
| Peak memory | 197616 kb |
| Host | smart-5e52a389-2184-468e-b6d3-8a19e3aa80a4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480657978 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2480657978 |
| Directory | /workspace/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.505576133 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 389174791238 ps |
| CPU time | 644.34 seconds |
| Started | Jan 10 01:07:35 PM PST 24 |
| Finished | Jan 10 01:19:46 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-604ff5fd-a122-4431-9655-98613a7f5e31 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505576133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.rv_timer_cfg_update_on_fly.505576133 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.596172008 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 32686857184 ps |
| CPU time | 45.97 seconds |
| Started | Jan 10 01:07:46 PM PST 24 |
| Finished | Jan 10 01:09:56 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-4e1d114d-7d53-4693-b6fa-89383839663a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596172008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.596172008 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.580772434 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 18124690 ps |
| CPU time | 0.61 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:09:00 PM PST 24 |
| Peak memory | 182724 kb |
| Host | smart-8a51c9db-5e17-4adf-bb8d-30c66e5967c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580772434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.580772434 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1641547461 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 100195772137 ps |
| CPU time | 430.88 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:16:10 PM PST 24 |
| Peak memory | 205856 kb |
| Host | smart-eb85cc7e-1fce-4cf2-b815-ee0285ba67d1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641547461 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1641547461 |
| Directory | /workspace/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.1463111314 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 631439025729 ps |
| CPU time | 1825.6 seconds |
| Started | Jan 10 01:09:54 PM PST 24 |
| Finished | Jan 10 01:41:26 PM PST 24 |
| Peak memory | 190960 kb |
| Host | smart-0b8b12ca-02b2-4eb5-a906-48993f6a2255 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463111314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1463111314 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.2524221196 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 79732116396 ps |
| CPU time | 28.95 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:10:57 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-9cdbbee8-3e38-4518-b4e3-053fe726129f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524221196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2524221196 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.1095580494 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 126369358185 ps |
| CPU time | 70.17 seconds |
| Started | Jan 10 01:09:42 PM PST 24 |
| Finished | Jan 10 01:11:58 PM PST 24 |
| Peak memory | 182608 kb |
| Host | smart-61167ba4-66d4-43c2-ba35-73829c7704c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095580494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1095580494 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.3913480923 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 103018478926 ps |
| CPU time | 291.69 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:15:18 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-f1ceeefa-9a0e-4d1c-ba62-9ad5c41d3693 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913480923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3913480923 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.3934246053 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 324456325924 ps |
| CPU time | 508.67 seconds |
| Started | Jan 10 01:09:41 PM PST 24 |
| Finished | Jan 10 01:19:16 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-a7f009ab-50d3-422c-b6a7-bde4bb6f2c20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934246053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3934246053 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.3695496673 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 75343024936 ps |
| CPU time | 353.52 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:16:35 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-c648d301-e3c8-4d0e-b9fb-27a60ea8ce73 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695496673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3695496673 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.2520710884 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 11997836184 ps |
| CPU time | 17.15 seconds |
| Started | Jan 10 01:09:25 PM PST 24 |
| Finished | Jan 10 01:10:46 PM PST 24 |
| Peak memory | 182584 kb |
| Host | smart-37658b6a-e3c5-4a00-9168-c6e8dda02d40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520710884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2520710884 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.3711410765 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 528751775892 ps |
| CPU time | 178.45 seconds |
| Started | Jan 10 01:07:40 PM PST 24 |
| Finished | Jan 10 01:12:03 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-838691e8-a62b-4629-a5fc-491c542acd3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711410765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3711410765 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.825877497 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6882382332 ps |
| CPU time | 5.03 seconds |
| Started | Jan 10 01:07:33 PM PST 24 |
| Finished | Jan 10 01:09:08 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-5da870ab-82cb-4692-9cc2-e3eb631c5e86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825877497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.825877497 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.881983270 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 320530988253 ps |
| CPU time | 387.03 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:15:27 PM PST 24 |
| Peak memory | 191340 kb |
| Host | smart-55c9d2b3-ea22-445d-a36b-01a2142e2432 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881983270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all. 881983270 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3240790415 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 407991430305 ps |
| CPU time | 792.63 seconds |
| Started | Jan 10 01:07:33 PM PST 24 |
| Finished | Jan 10 01:22:07 PM PST 24 |
| Peak memory | 209476 kb |
| Host | smart-1c56c0ec-610b-497d-97a4-7576243f72c8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240790415 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3240790415 |
| Directory | /workspace/11.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.2535762615 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 309590267886 ps |
| CPU time | 223.98 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:14:24 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-0a0f2d9f-43b3-418c-b915-f90e7d5b4046 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535762615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2535762615 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.2235366440 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 116825195880 ps |
| CPU time | 1775.1 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:40:04 PM PST 24 |
| Peak memory | 191040 kb |
| Host | smart-3cd23406-4c91-4b60-9084-e377b6da0274 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235366440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2235366440 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.2788724720 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 86012255791 ps |
| CPU time | 725.65 seconds |
| Started | Jan 10 01:09:28 PM PST 24 |
| Finished | Jan 10 01:22:41 PM PST 24 |
| Peak memory | 191192 kb |
| Host | smart-2bfc4b1e-fc82-4835-9967-2d2712367fa9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788724720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2788724720 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.1383062676 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 290229256155 ps |
| CPU time | 772.49 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:23:24 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-d2988614-8696-4017-8721-cf9343c44e5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383062676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1383062676 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.4031307093 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 170621215834 ps |
| CPU time | 450.03 seconds |
| Started | Jan 10 01:09:28 PM PST 24 |
| Finished | Jan 10 01:18:03 PM PST 24 |
| Peak memory | 191240 kb |
| Host | smart-f3e457cd-51fc-44d0-a0c3-d4bfbbc2d484 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031307093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4031307093 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.1867601913 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 748277695004 ps |
| CPU time | 951.13 seconds |
| Started | Jan 10 01:09:42 PM PST 24 |
| Finished | Jan 10 01:26:39 PM PST 24 |
| Peak memory | 191020 kb |
| Host | smart-10280d3c-2dcd-4df7-967a-757ddb68dff3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867601913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1867601913 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1699954055 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3565030774 ps |
| CPU time | 6.92 seconds |
| Started | Jan 10 01:07:44 PM PST 24 |
| Finished | Jan 10 01:09:12 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-1c8bc93e-21a5-4897-9fb2-6fb66fb198e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699954055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1699954055 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.2832981648 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 167869659534 ps |
| CPU time | 70.82 seconds |
| Started | Jan 10 01:07:28 PM PST 24 |
| Finished | Jan 10 01:10:04 PM PST 24 |
| Peak memory | 183056 kb |
| Host | smart-520017ae-1653-40e8-9182-1aaec48987be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832981648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2832981648 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.1483384710 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 173646392513 ps |
| CPU time | 1779.77 seconds |
| Started | Jan 10 01:07:43 PM PST 24 |
| Finished | Jan 10 01:38:48 PM PST 24 |
| Peak memory | 191324 kb |
| Host | smart-f5a3a700-7863-4651-8ad8-6330a8f13ea7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483384710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1483384710 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.503205887 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 14232318287 ps |
| CPU time | 24.4 seconds |
| Started | Jan 10 01:07:44 PM PST 24 |
| Finished | Jan 10 01:09:30 PM PST 24 |
| Peak memory | 192260 kb |
| Host | smart-cda7a290-ac41-4115-97ac-d6226c5fb36f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503205887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all. 503205887 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2906752622 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 42912133676 ps |
| CPU time | 713.83 seconds |
| Started | Jan 10 01:07:49 PM PST 24 |
| Finished | Jan 10 01:21:08 PM PST 24 |
| Peak memory | 205712 kb |
| Host | smart-f760ae56-37b0-4d97-8246-8f5388756792 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906752622 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2906752622 |
| Directory | /workspace/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.1717694468 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 138256192478 ps |
| CPU time | 38.74 seconds |
| Started | Jan 10 01:09:20 PM PST 24 |
| Finished | Jan 10 01:11:10 PM PST 24 |
| Peak memory | 182616 kb |
| Host | smart-ba624ada-e12a-4757-baeb-2dc760ba0a24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717694468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1717694468 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.4226396574 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 115658302951 ps |
| CPU time | 106.71 seconds |
| Started | Jan 10 01:09:14 PM PST 24 |
| Finished | Jan 10 01:12:08 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-80b3c819-6784-4330-9046-2bfd8755d1a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226396574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4226396574 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.3675536789 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 489398984152 ps |
| CPU time | 387.94 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:16:55 PM PST 24 |
| Peak memory | 191076 kb |
| Host | smart-a29b3872-9e9f-408e-a964-dedb4d43f900 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675536789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3675536789 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.2606677305 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 104234661202 ps |
| CPU time | 180.14 seconds |
| Started | Jan 10 01:09:39 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 192248 kb |
| Host | smart-98938a0e-0320-49de-b34b-d3c9f2480278 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606677305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2606677305 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.1310290439 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 39837405601 ps |
| CPU time | 31.71 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-5e1866a5-d9fd-45b2-a3f1-3660a5233977 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310290439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1310290439 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.3379160444 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 552065379585 ps |
| CPU time | 1293.35 seconds |
| Started | Jan 10 01:09:54 PM PST 24 |
| Finished | Jan 10 01:32:33 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-7e79f311-742e-46e6-aa9a-36eefee31f0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379160444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3379160444 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.2016920223 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 259746825842 ps |
| CPU time | 1626.17 seconds |
| Started | Jan 10 01:09:20 PM PST 24 |
| Finished | Jan 10 01:37:37 PM PST 24 |
| Peak memory | 182864 kb |
| Host | smart-a1203186-3e12-45e7-801a-ed00d0222f2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016920223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2016920223 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.1886433013 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 242029619734 ps |
| CPU time | 772 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:23:19 PM PST 24 |
| Peak memory | 193876 kb |
| Host | smart-31697950-0bbb-484e-aea0-c876eef8fdab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886433013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1886433013 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3710381866 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 856155412755 ps |
| CPU time | 481.18 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:17:00 PM PST 24 |
| Peak memory | 182772 kb |
| Host | smart-4f42f0c3-96ec-45c7-8c72-10959b841528 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710381866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.3710381866 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.370881260 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 620844652230 ps |
| CPU time | 240.35 seconds |
| Started | Jan 10 01:07:52 PM PST 24 |
| Finished | Jan 10 01:13:15 PM PST 24 |
| Peak memory | 182888 kb |
| Host | smart-257141a6-c64c-43ce-a00d-a1233c406ac4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370881260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.370881260 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.977347728 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 58746730211 ps |
| CPU time | 113.51 seconds |
| Started | Jan 10 01:09:04 PM PST 24 |
| Finished | Jan 10 01:12:05 PM PST 24 |
| Peak memory | 190628 kb |
| Host | smart-58f6bf4f-3f32-4fb0-ae9e-12d744ada658 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977347728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.977347728 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.3625612174 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 67791621546 ps |
| CPU time | 316.79 seconds |
| Started | Jan 10 01:07:37 PM PST 24 |
| Finished | Jan 10 01:14:19 PM PST 24 |
| Peak memory | 194588 kb |
| Host | smart-1c2b546e-71fb-49c8-a130-9a8a81746aa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625612174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3625612174 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.849631246 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 309441385632 ps |
| CPU time | 206.02 seconds |
| Started | Jan 10 01:08:44 PM PST 24 |
| Finished | Jan 10 01:13:28 PM PST 24 |
| Peak memory | 206232 kb |
| Host | smart-d70ee8cb-891e-4ff9-87ae-067a698ec317 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849631246 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.849631246 |
| Directory | /workspace/13.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.228273191 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 86282469087 ps |
| CPU time | 148.67 seconds |
| Started | Jan 10 01:09:18 PM PST 24 |
| Finished | Jan 10 01:12:52 PM PST 24 |
| Peak memory | 191220 kb |
| Host | smart-c26ec249-7766-44f3-9020-2ffcabf2f0de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228273191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.228273191 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.141125946 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24310570159 ps |
| CPU time | 24.89 seconds |
| Started | Jan 10 01:09:17 PM PST 24 |
| Finished | Jan 10 01:10:49 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-0dcb81a4-0f59-437f-9b1a-e8906d5286b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141125946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.141125946 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.3931245401 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 405460540117 ps |
| CPU time | 215.95 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:14:07 PM PST 24 |
| Peak memory | 193932 kb |
| Host | smart-a4d2e0f6-7c1f-40e8-b67b-8ae319bca7b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931245401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3931245401 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.565776609 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 295149134320 ps |
| CPU time | 977.49 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:26:49 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-78a2f494-c319-4017-89f1-4c120b9bd6a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565776609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.565776609 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.3567223034 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 195045493345 ps |
| CPU time | 556.73 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:19:44 PM PST 24 |
| Peak memory | 193832 kb |
| Host | smart-138dee59-a96d-41b2-85ef-65e6a3467a65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567223034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3567223034 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.2838257226 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 215791194830 ps |
| CPU time | 690.22 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:22:05 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-8bda239c-f145-4a56-97d1-69a91054f5e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838257226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2838257226 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.2219656336 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 58652380546 ps |
| CPU time | 164.09 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:13:12 PM PST 24 |
| Peak memory | 191048 kb |
| Host | smart-20cbb4fc-8bd4-4f67-8caf-c84d9e25daf3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219656336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2219656336 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2568901186 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 286985093759 ps |
| CPU time | 258.77 seconds |
| Started | Jan 10 01:08:02 PM PST 24 |
| Finished | Jan 10 01:13:52 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-663f9808-ac6b-4933-bb0b-e4dc9868e60d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568901186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.2568901186 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.2038344853 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 127977202128 ps |
| CPU time | 170.39 seconds |
| Started | Jan 10 01:07:31 PM PST 24 |
| Finished | Jan 10 01:11:43 PM PST 24 |
| Peak memory | 182888 kb |
| Host | smart-4fecdde4-4b62-4d31-8e19-c200ae8cf58e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038344853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2038344853 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.3980624321 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 20678078 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:07:52 PM PST 24 |
| Finished | Jan 10 01:09:15 PM PST 24 |
| Peak memory | 182468 kb |
| Host | smart-4d9a88b7-da3f-4395-8854-27ec887b3a5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980624321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3980624321 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.721740781 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 128041285956 ps |
| CPU time | 812.47 seconds |
| Started | Jan 10 01:07:46 PM PST 24 |
| Finished | Jan 10 01:22:43 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-41b086d8-6154-48d0-ade7-aafeb6d59ab9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721740781 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.721740781 |
| Directory | /workspace/14.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.1884893768 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 208446487948 ps |
| CPU time | 369.9 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:16:41 PM PST 24 |
| Peak memory | 194504 kb |
| Host | smart-93137288-e800-43c4-9311-1d2c21c73baf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884893768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1884893768 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.1208997665 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1375041090754 ps |
| CPU time | 351.15 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:16:34 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-aa64f786-dbf0-4a49-9709-a91b917bb54c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208997665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1208997665 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1270593489 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 59835181679 ps |
| CPU time | 111.97 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:10:56 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-54282941-08bd-448d-9505-ac10698eee4c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270593489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1270593489 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.2346626693 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 76437402324 ps |
| CPU time | 112.21 seconds |
| Started | Jan 10 01:07:36 PM PST 24 |
| Finished | Jan 10 01:11:02 PM PST 24 |
| Peak memory | 182692 kb |
| Host | smart-1abaac96-bb59-4858-a88c-df02bde10648 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346626693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2346626693 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.993661310 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 103402915819 ps |
| CPU time | 352.38 seconds |
| Started | Jan 10 01:07:32 PM PST 24 |
| Finished | Jan 10 01:14:48 PM PST 24 |
| Peak memory | 194424 kb |
| Host | smart-1323f6b6-bdc6-4ad1-98d0-0e6693ba1783 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993661310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.993661310 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.341311180 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 413323661764 ps |
| CPU time | 227.16 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-aab93429-d2fd-4f63-8f85-353019e7825b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341311180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.341311180 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.1024254324 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1084808396032 ps |
| CPU time | 392.54 seconds |
| Started | Jan 10 01:08:41 PM PST 24 |
| Finished | Jan 10 01:16:30 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-572100be-b611-47ed-bd6e-1c3ddf0dcffe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024254324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .1024254324 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3461377761 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 160421696364 ps |
| CPU time | 1336.44 seconds |
| Started | Jan 10 01:08:42 PM PST 24 |
| Finished | Jan 10 01:32:10 PM PST 24 |
| Peak memory | 213828 kb |
| Host | smart-7f5e44bb-a9dd-4499-bc42-018bca8a0a6b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461377761 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3461377761 |
| Directory | /workspace/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.4189864714 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 59104858255 ps |
| CPU time | 113.3 seconds |
| Started | Jan 10 01:09:28 PM PST 24 |
| Finished | Jan 10 01:12:29 PM PST 24 |
| Peak memory | 191224 kb |
| Host | smart-1abeebc4-a7b9-4a6f-b221-1685d49fcacb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189864714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4189864714 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.2659414790 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 742740287107 ps |
| CPU time | 231.44 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:14:34 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-3145c3ef-5f67-449d-80a4-c00a41c0c688 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659414790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2659414790 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.2676345683 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 154026647877 ps |
| CPU time | 527.98 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:19:19 PM PST 24 |
| Peak memory | 191100 kb |
| Host | smart-600df2f9-5764-4503-92ab-ad168bf4c4e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676345683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2676345683 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.473168890 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 184638344714 ps |
| CPU time | 84.74 seconds |
| Started | Jan 10 01:09:42 PM PST 24 |
| Finished | Jan 10 01:12:12 PM PST 24 |
| Peak memory | 182912 kb |
| Host | smart-b198c7a8-09b0-4571-a32a-c2c0a2637002 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473168890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.473168890 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.993227970 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 38820910809 ps |
| CPU time | 73.38 seconds |
| Started | Jan 10 01:09:35 PM PST 24 |
| Finished | Jan 10 01:11:53 PM PST 24 |
| Peak memory | 194456 kb |
| Host | smart-3b449360-dbb1-431a-82df-eb780c4b8895 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993227970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.993227970 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.1456507721 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 89907776068 ps |
| CPU time | 195.16 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:13:42 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-2067a174-ce13-4153-8dfb-5dc662bfb21b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456507721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1456507721 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1707938956 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 17526686796 ps |
| CPU time | 30.05 seconds |
| Started | Jan 10 01:08:14 PM PST 24 |
| Finished | Jan 10 01:10:09 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-3d9f87f5-a43a-4e90-97ac-40d75f1bf68a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707938956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.1707938956 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.2820794722 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 735228649849 ps |
| CPU time | 174.77 seconds |
| Started | Jan 10 01:08:30 PM PST 24 |
| Finished | Jan 10 01:12:40 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-165ad065-a3ad-43dd-a32d-50a0ff85e73d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820794722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2820794722 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.3310805753 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 111797963443 ps |
| CPU time | 201.05 seconds |
| Started | Jan 10 01:08:36 PM PST 24 |
| Finished | Jan 10 01:13:10 PM PST 24 |
| Peak memory | 193268 kb |
| Host | smart-753d0fb6-9883-458a-9952-e57fa581d9ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310805753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3310805753 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.1903065054 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 31037387083 ps |
| CPU time | 157.33 seconds |
| Started | Jan 10 01:08:25 PM PST 24 |
| Finished | Jan 10 01:12:19 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-198e46cb-20fc-4d8a-bac1-b3268daae9dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903065054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1903065054 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.523585450 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 680355334784 ps |
| CPU time | 280.34 seconds |
| Started | Jan 10 01:08:13 PM PST 24 |
| Finished | Jan 10 01:14:16 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-415007fb-a8a5-4dfe-bbe3-0b15b0bd048d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523585450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all. 523585450 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3144459124 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 380848528554 ps |
| CPU time | 1097.09 seconds |
| Started | Jan 10 01:08:13 PM PST 24 |
| Finished | Jan 10 01:28:00 PM PST 24 |
| Peak memory | 212752 kb |
| Host | smart-bac8f830-ad71-4035-8873-401cfcdf2465 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144459124 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3144459124 |
| Directory | /workspace/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.3326875378 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 42468705094 ps |
| CPU time | 72.54 seconds |
| Started | Jan 10 01:09:25 PM PST 24 |
| Finished | Jan 10 01:11:43 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-6f8732b4-49d4-4e7b-ba7b-ee625542fe6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326875378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3326875378 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.2780956556 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 114141017640 ps |
| CPU time | 176.98 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:13:30 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-34ac2fdb-d057-4dc7-a1db-ee534ace3915 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780956556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2780956556 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.393042894 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 119060753839 ps |
| CPU time | 1836.93 seconds |
| Started | Jan 10 01:09:32 PM PST 24 |
| Finished | Jan 10 01:41:13 PM PST 24 |
| Peak memory | 193744 kb |
| Host | smart-63b80f94-c464-42af-a28c-57d4f83264cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393042894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.393042894 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.79108906 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 57663447696 ps |
| CPU time | 98.34 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:12:15 PM PST 24 |
| Peak memory | 194252 kb |
| Host | smart-64f0b7a2-74b0-46e3-854e-1454fbffa526 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79108906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.79108906 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.1174423475 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 129430166399 ps |
| CPU time | 1894.02 seconds |
| Started | Jan 10 01:09:44 PM PST 24 |
| Finished | Jan 10 01:42:25 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-ec920e82-92fa-403a-9c09-e927a15e30d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174423475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1174423475 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.1754922711 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 606498043603 ps |
| CPU time | 282.3 seconds |
| Started | Jan 10 01:09:24 PM PST 24 |
| Finished | Jan 10 01:15:11 PM PST 24 |
| Peak memory | 193656 kb |
| Host | smart-d0e5d318-3cc2-48d0-9502-6a4d9146d39d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754922711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1754922711 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.1214610201 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 351272789443 ps |
| CPU time | 159.81 seconds |
| Started | Jan 10 01:09:17 PM PST 24 |
| Finished | Jan 10 01:13:03 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-76346843-592b-4a66-9a4b-68a49263c0dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214610201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1214610201 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.3979607775 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 99356931510 ps |
| CPU time | 228.67 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-f344c617-45fb-4848-a3cd-b8eca15b3f3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979607775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3979607775 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.949196227 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 117828575881 ps |
| CPU time | 65.93 seconds |
| Started | Jan 10 01:08:10 PM PST 24 |
| Finished | Jan 10 01:10:46 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-8b99c85e-6a82-45ca-b650-609c99836b6b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949196227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.rv_timer_cfg_update_on_fly.949196227 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.2497379197 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 528096235184 ps |
| CPU time | 213.61 seconds |
| Started | Jan 10 01:08:12 PM PST 24 |
| Finished | Jan 10 01:13:06 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-34c39c46-ef2f-49c3-8e70-7084e9db0ef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497379197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2497379197 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.4179071907 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 14436746 ps |
| CPU time | 0.53 seconds |
| Started | Jan 10 01:08:11 PM PST 24 |
| Finished | Jan 10 01:09:48 PM PST 24 |
| Peak memory | 182400 kb |
| Host | smart-8b496dbb-6dfb-45e0-a522-9afa246a6d7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179071907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4179071907 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2449735810 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 305012134766 ps |
| CPU time | 868.28 seconds |
| Started | Jan 10 01:08:13 PM PST 24 |
| Finished | Jan 10 01:24:08 PM PST 24 |
| Peak memory | 210488 kb |
| Host | smart-cf31e85b-c71d-425c-a9e9-8262ac218153 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449735810 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2449735810 |
| Directory | /workspace/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.947758743 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 517261280185 ps |
| CPU time | 1163.76 seconds |
| Started | Jan 10 01:09:37 PM PST 24 |
| Finished | Jan 10 01:30:06 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-f1d18d49-f2ae-4aa4-b809-df1f247fee1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947758743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.947758743 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.1522886101 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 208461151313 ps |
| CPU time | 1935.88 seconds |
| Started | Jan 10 01:09:32 PM PST 24 |
| Finished | Jan 10 01:42:53 PM PST 24 |
| Peak memory | 191220 kb |
| Host | smart-f137e65b-cabd-4094-96e4-17855782456b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522886101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1522886101 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.3815842373 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1353497238181 ps |
| CPU time | 2825.65 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:57:38 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-50386def-6f27-4ef0-9521-ba1471f137dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815842373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3815842373 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.134299237 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 57259348789 ps |
| CPU time | 101.59 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:12:13 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-da7e91b6-42f7-46ca-b26b-60471baa2ddb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134299237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.134299237 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.2796595078 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 438692670744 ps |
| CPU time | 533.71 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:19:27 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-b10d2a42-eabd-41d6-8d5b-b29c04910deb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796595078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2796595078 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.1234166558 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 99903770812 ps |
| CPU time | 610 seconds |
| Started | Jan 10 01:09:20 PM PST 24 |
| Finished | Jan 10 01:20:36 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-2b73a892-6cc2-4b71-ab24-565b3cf6211f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234166558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1234166558 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.2307830751 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 317179314433 ps |
| CPU time | 1015.95 seconds |
| Started | Jan 10 01:09:39 PM PST 24 |
| Finished | Jan 10 01:27:41 PM PST 24 |
| Peak memory | 191092 kb |
| Host | smart-24f7676b-f21b-48d6-a936-309fcadd4a44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307830751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2307830751 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.460421860 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 117521216214 ps |
| CPU time | 1786.32 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:40:20 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-da9ac347-ac8c-4b84-bfd5-b6eefcd1e7dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460421860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.460421860 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.994802522 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 237408127403 ps |
| CPU time | 274.76 seconds |
| Started | Jan 10 01:08:22 PM PST 24 |
| Finished | Jan 10 01:14:17 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-156ce250-a520-44f7-954b-e3a977e849de |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994802522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.rv_timer_cfg_update_on_fly.994802522 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.1055954806 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 400032860489 ps |
| CPU time | 191.6 seconds |
| Started | Jan 10 01:08:27 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 183032 kb |
| Host | smart-307e36af-c274-492b-8a1b-5d40f0d2f65a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055954806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1055954806 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.1229059173 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 896567282 ps |
| CPU time | 0.96 seconds |
| Started | Jan 10 01:08:46 PM PST 24 |
| Finished | Jan 10 01:09:57 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-21724e87-ec3a-4e91-9cde-5cca68908ad3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229059173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1229059173 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2003774059 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 73877853791 ps |
| CPU time | 739.94 seconds |
| Started | Jan 10 01:08:28 PM PST 24 |
| Finished | Jan 10 01:22:06 PM PST 24 |
| Peak memory | 208300 kb |
| Host | smart-a20591b7-6b1c-4ed1-b29b-57d45396151d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003774059 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2003774059 |
| Directory | /workspace/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.1740057190 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 826638861214 ps |
| CPU time | 230.52 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 191028 kb |
| Host | smart-5f5fd539-1e7e-4048-857b-48600a614be7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740057190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1740057190 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.4148251420 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 450707489244 ps |
| CPU time | 1884.01 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:41:52 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-148779b3-c78b-4962-80b7-18894a05dad0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148251420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4148251420 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.3392882748 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 190597360935 ps |
| CPU time | 311.29 seconds |
| Started | Jan 10 01:09:38 PM PST 24 |
| Finished | Jan 10 01:15:54 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-3520dab1-11bb-421c-844e-c4b7039edcdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392882748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3392882748 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.1312763048 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 578177911934 ps |
| CPU time | 728.01 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:22:40 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-c5ced582-d371-4475-8ebc-2adb51dd74bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312763048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1312763048 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.1015535529 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 421685469435 ps |
| CPU time | 380.27 seconds |
| Started | Jan 10 01:09:33 PM PST 24 |
| Finished | Jan 10 01:16:58 PM PST 24 |
| Peak memory | 194264 kb |
| Host | smart-69f3e151-bf13-48ee-950b-b1eba4c2abed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015535529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1015535529 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4122895181 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1838497726223 ps |
| CPU time | 951.59 seconds |
| Started | Jan 10 01:08:11 PM PST 24 |
| Finished | Jan 10 01:25:28 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-739d4f82-0642-4a9f-aefc-546debbe2b88 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122895181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.4122895181 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_disabled.3462631784 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 398524557765 ps |
| CPU time | 283.71 seconds |
| Started | Jan 10 01:08:19 PM PST 24 |
| Finished | Jan 10 01:14:22 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-dd980778-ef01-4768-b7a6-d1261a156f2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462631784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3462631784 |
| Directory | /workspace/19.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.2702348885 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 170505368911 ps |
| CPU time | 310.66 seconds |
| Started | Jan 10 01:08:15 PM PST 24 |
| Finished | Jan 10 01:14:56 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-c9beb222-6526-4203-992e-9da7dff9507c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702348885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2702348885 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.1505871342 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 38285309342 ps |
| CPU time | 13.43 seconds |
| Started | Jan 10 01:08:19 PM PST 24 |
| Finished | Jan 10 01:09:50 PM PST 24 |
| Peak memory | 182684 kb |
| Host | smart-c2d284fb-eb4a-42e2-833a-c16f24617277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505871342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1505871342 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.334575736 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 35776757461 ps |
| CPU time | 102.59 seconds |
| Started | Jan 10 01:08:17 PM PST 24 |
| Finished | Jan 10 01:11:24 PM PST 24 |
| Peak memory | 197692 kb |
| Host | smart-06fefa7e-f0d4-4856-a4d1-53dc9a049610 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334575736 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.334575736 |
| Directory | /workspace/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.3015243648 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 81992868471 ps |
| CPU time | 320.68 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:15:48 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-f512d96d-6e7c-439c-9443-f9e10245079b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015243648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3015243648 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.3530040472 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1021913155064 ps |
| CPU time | 555.14 seconds |
| Started | Jan 10 01:09:33 PM PST 24 |
| Finished | Jan 10 01:19:53 PM PST 24 |
| Peak memory | 194132 kb |
| Host | smart-9031e095-201b-4422-835e-9fd28bf6501f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530040472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3530040472 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.2047930914 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 367113960913 ps |
| CPU time | 283.9 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:15:19 PM PST 24 |
| Peak memory | 192192 kb |
| Host | smart-c38235d3-89d4-4474-9435-37d0cc38eb6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047930914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2047930914 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.1387680708 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 146417991904 ps |
| CPU time | 261.88 seconds |
| Started | Jan 10 01:09:57 PM PST 24 |
| Finished | Jan 10 01:15:26 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-bd549315-68bf-4eae-9463-8802c4a1c78c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387680708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1387680708 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.1545545197 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 124853855891 ps |
| CPU time | 194.5 seconds |
| Started | Jan 10 01:09:39 PM PST 24 |
| Finished | Jan 10 01:13:59 PM PST 24 |
| Peak memory | 193240 kb |
| Host | smart-267c9f12-1610-46a1-8707-5597a509e1da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545545197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1545545197 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.4106135177 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 95977635988 ps |
| CPU time | 234.2 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:14:27 PM PST 24 |
| Peak memory | 191092 kb |
| Host | smart-c0fc64be-225f-442c-bbbe-f0d7d8ce5bc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106135177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4106135177 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.4026757180 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2503278208611 ps |
| CPU time | 829.64 seconds |
| Started | Jan 10 01:09:36 PM PST 24 |
| Finished | Jan 10 01:24:31 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-f5781300-39e1-4b4e-b519-41d2f1ad507a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026757180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4026757180 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.806400953 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3474882521 ps |
| CPU time | 6.74 seconds |
| Started | Jan 10 01:07:32 PM PST 24 |
| Finished | Jan 10 01:09:03 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-5904a274-8287-4e8c-847f-b497693fc6bb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806400953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rv_timer_cfg_update_on_fly.806400953 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.2358840751 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 90818247133 ps |
| CPU time | 70.33 seconds |
| Started | Jan 10 01:07:34 PM PST 24 |
| Finished | Jan 10 01:10:14 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-e8363325-2037-4914-9b07-97cb62721788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2358840751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2358840751 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.1966611857 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 101664598767 ps |
| CPU time | 220.24 seconds |
| Started | Jan 10 01:07:28 PM PST 24 |
| Finished | Jan 10 01:12:33 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-a1c183f0-b44d-4dbe-92df-0a0afb3d5d1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966611857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1966611857 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.3976476842 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 321997066764 ps |
| CPU time | 577.88 seconds |
| Started | Jan 10 01:07:24 PM PST 24 |
| Finished | Jan 10 01:18:25 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-e4ba32cc-3ba2-43fb-afbb-c41ec31d9df9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976476842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3976476842 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.2233075956 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 61069866 ps |
| CPU time | 0.74 seconds |
| Started | Jan 10 01:07:36 PM PST 24 |
| Finished | Jan 10 01:08:58 PM PST 24 |
| Peak memory | 212860 kb |
| Host | smart-9eca77c6-ba5f-4ea7-9a02-1e3d966dccd6 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233075956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2233075956 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.3498663528 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 388741049201 ps |
| CPU time | 282.13 seconds |
| Started | Jan 10 01:07:20 PM PST 24 |
| Finished | Jan 10 01:13:34 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-4846a638-4854-4571-9af7-352ea3744a30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498663528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 3498663528 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3583867044 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 47321644196 ps |
| CPU time | 347.94 seconds |
| Started | Jan 10 01:07:25 PM PST 24 |
| Finished | Jan 10 01:14:35 PM PST 24 |
| Peak memory | 197732 kb |
| Host | smart-d2ff7fc6-a9dd-4708-9319-e4f6f48d94cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583867044 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3583867044 |
| Directory | /workspace/2.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2258361550 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 370013352377 ps |
| CPU time | 191.76 seconds |
| Started | Jan 10 01:08:29 PM PST 24 |
| Finished | Jan 10 01:12:57 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-839c0b1d-2cc8-4f06-82a8-d5f944eb0a28 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258361550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2258361550 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.1985687065 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 391389350320 ps |
| CPU time | 161.84 seconds |
| Started | Jan 10 01:08:19 PM PST 24 |
| Finished | Jan 10 01:12:25 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-78034e89-bdc7-40a9-8d3c-91224c5519ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985687065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1985687065 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.4042929502 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 200486877918 ps |
| CPU time | 251.06 seconds |
| Started | Jan 10 01:08:11 PM PST 24 |
| Finished | Jan 10 01:13:43 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-5fb8d538-b0de-4e45-8637-fca5c2cbd99b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042929502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.4042929502 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.797034285 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 966534177 ps |
| CPU time | 0.91 seconds |
| Started | Jan 10 01:08:21 PM PST 24 |
| Finished | Jan 10 01:09:44 PM PST 24 |
| Peak memory | 192192 kb |
| Host | smart-fc184b8d-93d9-4b6d-b2d0-5156ada60943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797034285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.797034285 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.6056403 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 121606759057 ps |
| CPU time | 175.3 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:12:55 PM PST 24 |
| Peak memory | 182816 kb |
| Host | smart-816ae932-1d37-46bc-b95b-c024c82f3640 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6056403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.6056403 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3578000761 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 49337281854 ps |
| CPU time | 390.09 seconds |
| Started | Jan 10 01:08:26 PM PST 24 |
| Finished | Jan 10 01:16:13 PM PST 24 |
| Peak memory | 196880 kb |
| Host | smart-de5ab2a4-f07c-4405-8099-50ce9249d7ca |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578000761 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3578000761 |
| Directory | /workspace/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1413350294 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 575353409621 ps |
| CPU time | 936.11 seconds |
| Started | Jan 10 01:08:36 PM PST 24 |
| Finished | Jan 10 01:25:25 PM PST 24 |
| Peak memory | 182896 kb |
| Host | smart-24889723-504e-4b8b-9a41-b305d9aa5e26 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413350294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1413350294 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.2057627278 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 263120563967 ps |
| CPU time | 96.99 seconds |
| Started | Jan 10 01:10:28 PM PST 24 |
| Finished | Jan 10 01:13:25 PM PST 24 |
| Peak memory | 182508 kb |
| Host | smart-d2704d96-8886-47b4-8403-04e340bba25f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057627278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2057627278 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.372652425 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 96043798183 ps |
| CPU time | 44.28 seconds |
| Started | Jan 10 01:08:30 PM PST 24 |
| Finished | Jan 10 01:10:29 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-ae851b5d-ef2a-44dd-a68b-a2898cf1ee37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372652425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.372652425 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.50064899 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1664159722073 ps |
| CPU time | 1079.68 seconds |
| Started | Jan 10 01:08:24 PM PST 24 |
| Finished | Jan 10 01:27:50 PM PST 24 |
| Peak memory | 191332 kb |
| Host | smart-61d1f2f7-d1fc-4f1c-b70d-445dace253c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50064899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.50064899 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.3042098621 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 261514938870 ps |
| CPU time | 527.4 seconds |
| Started | Jan 10 01:08:26 PM PST 24 |
| Finished | Jan 10 01:18:30 PM PST 24 |
| Peak memory | 213168 kb |
| Host | smart-0e9dd82e-4816-4459-b9b1-0098638c6caf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042098621 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.3042098621 |
| Directory | /workspace/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2073550002 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 15979606806 ps |
| CPU time | 13.93 seconds |
| Started | Jan 10 01:10:01 PM PST 24 |
| Finished | Jan 10 01:11:23 PM PST 24 |
| Peak memory | 181924 kb |
| Host | smart-5b4545a3-c0a5-4b8b-a4d0-4a277691d1cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073550002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2073550002 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_disabled.2244200093 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 514325791997 ps |
| CPU time | 208.34 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:13:26 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-3a05c38f-3d5f-40cd-bd82-9b5f724f1ed4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244200093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2244200093 |
| Directory | /workspace/22.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.3843033863 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 115255532408 ps |
| CPU time | 250.41 seconds |
| Started | Jan 10 01:10:27 PM PST 24 |
| Finished | Jan 10 01:15:56 PM PST 24 |
| Peak memory | 190680 kb |
| Host | smart-de37c916-a69a-4fe3-9ae7-3e2e1f4580e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843033863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3843033863 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.414880271 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 42791753215 ps |
| CPU time | 76.06 seconds |
| Started | Jan 10 01:10:28 PM PST 24 |
| Finished | Jan 10 01:13:03 PM PST 24 |
| Peak memory | 182512 kb |
| Host | smart-99ef27ed-1e83-4ea6-bb0d-94f2a733e62a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414880271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.414880271 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2428960745 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 429057486863 ps |
| CPU time | 1562.71 seconds |
| Started | Jan 10 01:08:32 PM PST 24 |
| Finished | Jan 10 01:35:57 PM PST 24 |
| Peak memory | 209556 kb |
| Host | smart-3216f9b0-ee5a-4dc3-b632-d9e4d09eb8cf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428960745 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2428960745 |
| Directory | /workspace/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1499964896 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 391917672706 ps |
| CPU time | 628.01 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:21:36 PM PST 24 |
| Peak memory | 181032 kb |
| Host | smart-d8e8ae5e-8cfc-44d7-bd45-ce85594efd82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499964896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1499964896 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.1891290275 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 826696831825 ps |
| CPU time | 189.81 seconds |
| Started | Jan 10 01:08:36 PM PST 24 |
| Finished | Jan 10 01:13:02 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-4ed0cb9a-0660-46fd-8aa0-f975fb9c25c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891290275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1891290275 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.2050610733 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 50137400647 ps |
| CPU time | 80.26 seconds |
| Started | Jan 10 01:10:27 PM PST 24 |
| Finished | Jan 10 01:13:05 PM PST 24 |
| Peak memory | 190680 kb |
| Host | smart-52fd50a0-aac6-40f3-a95f-6cae66e81b5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050610733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2050610733 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.3388088199 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 12406532933 ps |
| CPU time | 18.59 seconds |
| Started | Jan 10 01:08:34 PM PST 24 |
| Finished | Jan 10 01:10:06 PM PST 24 |
| Peak memory | 191248 kb |
| Host | smart-357f511b-305d-43a5-a939-b72553374431 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388088199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3388088199 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3776458685 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 83078714518 ps |
| CPU time | 156.93 seconds |
| Started | Jan 10 01:08:27 PM PST 24 |
| Finished | Jan 10 01:12:20 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-3943b9d1-9e4e-4c02-aa1c-3866b06501ba |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776458685 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3776458685 |
| Directory | /workspace/23.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1173297736 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 253375811326 ps |
| CPU time | 313.17 seconds |
| Started | Jan 10 01:08:32 PM PST 24 |
| Finished | Jan 10 01:15:00 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-1bf5465e-a164-4cca-a3fa-2e8316541dd4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173297736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.1173297736 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.340856535 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 6370417412 ps |
| CPU time | 1.9 seconds |
| Started | Jan 10 01:08:31 PM PST 24 |
| Finished | Jan 10 01:09:56 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-1a7b16dd-733c-4f50-ac29-8bdbc9d57907 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340856535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.340856535 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.15969548 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 38824737396 ps |
| CPU time | 104.99 seconds |
| Started | Jan 10 01:08:33 PM PST 24 |
| Finished | Jan 10 01:11:32 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-241950ec-3205-451a-b958-e096e7288033 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.15969548 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.3026578051 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 557227839589 ps |
| CPU time | 689.38 seconds |
| Started | Jan 10 01:08:30 PM PST 24 |
| Finished | Jan 10 01:21:14 PM PST 24 |
| Peak memory | 191100 kb |
| Host | smart-246e5b64-f6f6-4fd0-803a-8293890832e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026578051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3026578051 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1412908081 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 104416330210 ps |
| CPU time | 564.39 seconds |
| Started | Jan 10 01:08:31 PM PST 24 |
| Finished | Jan 10 01:19:15 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-4868113a-e4ff-45b3-86f6-91066e920f71 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412908081 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1412908081 |
| Directory | /workspace/24.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2167778879 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 238364204659 ps |
| CPU time | 364.01 seconds |
| Started | Jan 10 01:08:37 PM PST 24 |
| Finished | Jan 10 01:15:56 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-0c1751d5-a50a-4238-bf17-e89a7cd72a17 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167778879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2167778879 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.2006904269 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 54820363495 ps |
| CPU time | 76.74 seconds |
| Started | Jan 10 01:08:28 PM PST 24 |
| Finished | Jan 10 01:11:09 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-c2f93421-6787-4523-9a43-d74bac5d5fa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006904269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2006904269 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.685186975 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 277572984806 ps |
| CPU time | 146.44 seconds |
| Started | Jan 10 01:08:43 PM PST 24 |
| Finished | Jan 10 01:12:21 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-1a66714b-ff39-462b-a8f6-4a05e94b370f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685186975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.685186975 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.2332003809 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 181470521802 ps |
| CPU time | 94.14 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:11:40 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-5f65d960-f56f-4664-9601-7ab3b9701da7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332003809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2332003809 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.1727517512 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1162121804511 ps |
| CPU time | 575.33 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:19:41 PM PST 24 |
| Peak memory | 191308 kb |
| Host | smart-6edf0659-bfb0-4913-b687-01800de32231 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727517512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .1727517512 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.1634458201 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 393240333153 ps |
| CPU time | 792.47 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:23:14 PM PST 24 |
| Peak memory | 209064 kb |
| Host | smart-d4599f07-660c-4cca-960b-25432bef929a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634458201 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.1634458201 |
| Directory | /workspace/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.86817920 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 339211037694 ps |
| CPU time | 292.73 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:15:12 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-bf72ea39-dc77-4e54-b3e1-aca31686aedb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86817920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .rv_timer_cfg_update_on_fly.86817920 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.1727880738 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 95572279439 ps |
| CPU time | 72.88 seconds |
| Started | Jan 10 01:08:45 PM PST 24 |
| Finished | Jan 10 01:11:08 PM PST 24 |
| Peak memory | 183016 kb |
| Host | smart-dd631782-4f1f-40fd-ad32-5dc085b13ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727880738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1727880738 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.2147654609 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 467882085 ps |
| CPU time | 0.67 seconds |
| Started | Jan 10 01:08:46 PM PST 24 |
| Finished | Jan 10 01:09:56 PM PST 24 |
| Peak memory | 182536 kb |
| Host | smart-844458ab-2561-4083-8b93-71c3f59a6c0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147654609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2147654609 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.249797914 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 556640174841 ps |
| CPU time | 741.44 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:22:24 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-4215558c-81a1-4170-a884-e19d24701102 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249797914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all. 249797914 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.893635134 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 176181048632 ps |
| CPU time | 417.84 seconds |
| Started | Jan 10 01:08:42 PM PST 24 |
| Finished | Jan 10 01:16:52 PM PST 24 |
| Peak memory | 197556 kb |
| Host | smart-9b055205-0849-4c09-a6dc-4c58d3ae7214 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893635134 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.893635134 |
| Directory | /workspace/26.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3963396327 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 4271540827 ps |
| CPU time | 8.69 seconds |
| Started | Jan 10 01:08:41 PM PST 24 |
| Finished | Jan 10 01:10:09 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-cedd499c-ba85-418d-a775-820730e81828 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963396327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.3963396327 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_disabled.2470655164 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 34409689537 ps |
| CPU time | 51.77 seconds |
| Started | Jan 10 01:08:43 PM PST 24 |
| Finished | Jan 10 01:10:46 PM PST 24 |
| Peak memory | 182868 kb |
| Host | smart-a554e5d4-515b-4087-908a-6d1626b43370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470655164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2470655164 |
| Directory | /workspace/27.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.3117709980 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 275570084167 ps |
| CPU time | 278.95 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:14:46 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-6b959482-0814-4a1c-9ab2-6661e2b090fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117709980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3117709980 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.4070822158 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 228891603651 ps |
| CPU time | 261.44 seconds |
| Started | Jan 10 01:08:50 PM PST 24 |
| Finished | Jan 10 01:14:21 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-d37612a2-d96d-4f96-afca-bba04f94ffdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070822158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4070822158 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.3564656713 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 306627104576 ps |
| CPU time | 453.2 seconds |
| Started | Jan 10 01:08:55 PM PST 24 |
| Finished | Jan 10 01:17:38 PM PST 24 |
| Peak memory | 191308 kb |
| Host | smart-cd8939f1-e7ac-47be-aa8a-fb1378ed8eb8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564656713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .3564656713 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.512627103 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 118577457164 ps |
| CPU time | 781.31 seconds |
| Started | Jan 10 01:08:45 PM PST 24 |
| Finished | Jan 10 01:22:57 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-9020c6ba-63cc-4ad5-b5a8-47b81391fb5c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512627103 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.512627103 |
| Directory | /workspace/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.3784535735 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 143113528757 ps |
| CPU time | 52.39 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:11:00 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-3770af99-bcf5-4d7e-9b19-244987d5aa18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784535735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3784535735 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.2718299782 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 485443104881 ps |
| CPU time | 1926.33 seconds |
| Started | Jan 10 01:08:46 PM PST 24 |
| Finished | Jan 10 01:42:02 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-1eae53e6-3b1f-4109-aa1b-fdf4d8b330c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718299782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2718299782 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.4030397502 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 166185968339 ps |
| CPU time | 450.08 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:17:33 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-07b2fcd7-287e-4e89-bbc9-1ac6b8531d40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030397502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4030397502 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.541080742 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 149319997191 ps |
| CPU time | 1600.36 seconds |
| Started | Jan 10 01:08:49 PM PST 24 |
| Finished | Jan 10 01:36:39 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-a855b65c-7203-49fa-b8e7-efc9fcaea73f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541080742 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.541080742 |
| Directory | /workspace/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2485603631 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 619491552238 ps |
| CPU time | 292.29 seconds |
| Started | Jan 10 01:10:27 PM PST 24 |
| Finished | Jan 10 01:16:38 PM PST 24 |
| Peak memory | 182500 kb |
| Host | smart-4964c747-1660-44f2-bf06-94b20bb3342c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485603631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2485603631 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.676689347 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 182721548449 ps |
| CPU time | 154.64 seconds |
| Started | Jan 10 01:08:40 PM PST 24 |
| Finished | Jan 10 01:12:27 PM PST 24 |
| Peak memory | 183056 kb |
| Host | smart-4d2f133b-e9d7-401e-8175-b44be2f207e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676689347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.676689347 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.695112529 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 101784369388 ps |
| CPU time | 566.64 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:19:41 PM PST 24 |
| Peak memory | 191220 kb |
| Host | smart-4ce87f17-6e62-497d-81ed-6d320b44fa21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695112529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.695112529 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.2501822005 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 71963754790 ps |
| CPU time | 324.01 seconds |
| Started | Jan 10 01:10:24 PM PST 24 |
| Finished | Jan 10 01:17:04 PM PST 24 |
| Peak memory | 190708 kb |
| Host | smart-145a7736-9ecf-40a0-997e-2ed67b96b87d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501822005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2501822005 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.4013745098 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 440124539847 ps |
| CPU time | 929.27 seconds |
| Started | Jan 10 01:08:31 PM PST 24 |
| Finished | Jan 10 01:25:20 PM PST 24 |
| Peak memory | 210356 kb |
| Host | smart-147500f3-398c-457f-a785-78bffc58ed0e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013745098 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.4013745098 |
| Directory | /workspace/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2598369232 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 585958316612 ps |
| CPU time | 501.57 seconds |
| Started | Jan 10 01:07:38 PM PST 24 |
| Finished | Jan 10 01:17:24 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-ba780f7a-afd8-4b92-80b2-5a53275c1a65 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598369232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.2598369232 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.4052610871 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 143690727063 ps |
| CPU time | 116.57 seconds |
| Started | Jan 10 01:07:30 PM PST 24 |
| Finished | Jan 10 01:10:48 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-c417614d-0971-4437-a6ed-00b5ed44db29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052610871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4052610871 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.1709864740 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 22956171835 ps |
| CPU time | 34.1 seconds |
| Started | Jan 10 01:07:31 PM PST 24 |
| Finished | Jan 10 01:09:25 PM PST 24 |
| Peak memory | 191216 kb |
| Host | smart-d3322ed8-66f0-4019-a221-b603ae6c8f5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709864740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1709864740 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.1222559333 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 103954430505 ps |
| CPU time | 49.97 seconds |
| Started | Jan 10 01:07:36 PM PST 24 |
| Finished | Jan 10 01:09:47 PM PST 24 |
| Peak memory | 182732 kb |
| Host | smart-146e24f8-67e7-443b-83b2-c4f8cf4036c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222559333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1222559333 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.4137005787 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 65348708 ps |
| CPU time | 0.83 seconds |
| Started | Jan 10 01:07:50 PM PST 24 |
| Finished | Jan 10 01:09:13 PM PST 24 |
| Peak memory | 212800 kb |
| Host | smart-97275d62-c2eb-4eea-851b-22b7ce9825e1 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137005787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4137005787 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3029464806 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 116133251686 ps |
| CPU time | 688.56 seconds |
| Started | Jan 10 01:07:36 PM PST 24 |
| Finished | Jan 10 01:20:26 PM PST 24 |
| Peak memory | 206044 kb |
| Host | smart-ceb62324-5fed-407f-a559-376e67ec4589 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029464806 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3029464806 |
| Directory | /workspace/3.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1936200638 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 32973705108 ps |
| CPU time | 18.34 seconds |
| Started | Jan 10 01:08:38 PM PST 24 |
| Finished | Jan 10 01:10:09 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-4692553c-2d96-429f-9fc6-58ea10f27045 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936200638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.1936200638 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.3694603832 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 242776178958 ps |
| CPU time | 162.85 seconds |
| Started | Jan 10 01:08:40 PM PST 24 |
| Finished | Jan 10 01:12:38 PM PST 24 |
| Peak memory | 183024 kb |
| Host | smart-05d70805-4eea-4a75-8d88-fe2570b56d2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694603832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3694603832 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.797720171 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 80605235980 ps |
| CPU time | 48.02 seconds |
| Started | Jan 10 01:10:19 PM PST 24 |
| Finished | Jan 10 01:12:22 PM PST 24 |
| Peak memory | 182392 kb |
| Host | smart-0a86d560-da38-4858-9657-083e9410c199 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797720171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.797720171 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.2956951687 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 53145649 ps |
| CPU time | 0.6 seconds |
| Started | Jan 10 01:08:32 PM PST 24 |
| Finished | Jan 10 01:09:54 PM PST 24 |
| Peak memory | 182460 kb |
| Host | smart-bc5968ee-647c-4e8d-a9b3-8900ee8a9c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956951687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2956951687 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1425566737 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 10838135053 ps |
| CPU time | 78.19 seconds |
| Started | Jan 10 01:08:33 PM PST 24 |
| Finished | Jan 10 01:11:05 PM PST 24 |
| Peak memory | 194964 kb |
| Host | smart-cd3059c5-0a96-4013-a337-b60bbca5d21b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425566737 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1425566737 |
| Directory | /workspace/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2736745778 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 277710202108 ps |
| CPU time | 460.84 seconds |
| Started | Jan 10 01:08:31 PM PST 24 |
| Finished | Jan 10 01:17:26 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-71bc504e-bd5a-4b3d-a966-0cb41b9c90b0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736745778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2736745778 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.2206991089 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 119942494072 ps |
| CPU time | 157.51 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:13:45 PM PST 24 |
| Peak memory | 181628 kb |
| Host | smart-91c01e17-e8c7-4486-a3f4-5682450958b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206991089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2206991089 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.1408217621 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 360145916796 ps |
| CPU time | 287.97 seconds |
| Started | Jan 10 01:08:35 PM PST 24 |
| Finished | Jan 10 01:14:37 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-14e4c5b4-e046-4ad6-b2bd-5842e8209232 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408217621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1408217621 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.2261068378 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 659499233 ps |
| CPU time | 2.64 seconds |
| Started | Jan 10 01:08:25 PM PST 24 |
| Finished | Jan 10 01:09:51 PM PST 24 |
| Peak memory | 182792 kb |
| Host | smart-7c4cb9a6-0a38-4ee5-bf80-59bd0f43769b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261068378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2261068378 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.3098790689 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 361284049890 ps |
| CPU time | 215.31 seconds |
| Started | Jan 10 01:08:40 PM PST 24 |
| Finished | Jan 10 01:13:30 PM PST 24 |
| Peak memory | 193632 kb |
| Host | smart-2d14c630-1c93-4be7-ac38-bbd530c460c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098790689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .3098790689 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.275054213 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 315108814196 ps |
| CPU time | 182.87 seconds |
| Started | Jan 10 01:08:34 PM PST 24 |
| Finished | Jan 10 01:12:57 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-02e06f81-717e-42c8-ac88-736583ad8f7f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275054213 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.275054213 |
| Directory | /workspace/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3584479642 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2335532972842 ps |
| CPU time | 754.97 seconds |
| Started | Jan 10 01:08:40 PM PST 24 |
| Finished | Jan 10 01:22:30 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-b5355a64-6e21-4b6a-bd15-6c28d7e91425 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584479642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3584479642 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.2447558651 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 14199447800 ps |
| CPU time | 21.08 seconds |
| Started | Jan 10 01:08:44 PM PST 24 |
| Finished | Jan 10 01:10:22 PM PST 24 |
| Peak memory | 182912 kb |
| Host | smart-66e6b634-8085-47fb-b48c-a6f3cb408373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447558651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2447558651 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.2062121055 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 97209789283 ps |
| CPU time | 325.78 seconds |
| Started | Jan 10 01:08:40 PM PST 24 |
| Finished | Jan 10 01:15:21 PM PST 24 |
| Peak memory | 190940 kb |
| Host | smart-556c4956-eb1a-4151-bd46-2036771348e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062121055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2062121055 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.30201911 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 24151459134 ps |
| CPU time | 19.68 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:10:25 PM PST 24 |
| Peak memory | 194304 kb |
| Host | smart-9b3a304e-c555-4c04-89fb-15ecb4184590 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.30201911 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2527129318 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 352541559512 ps |
| CPU time | 706.49 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:21:49 PM PST 24 |
| Peak memory | 207104 kb |
| Host | smart-250e4e81-162a-418d-bdad-39ecf0bdeac0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527129318 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2527129318 |
| Directory | /workspace/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1351348850 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 767590833985 ps |
| CPU time | 414.51 seconds |
| Started | Jan 10 01:08:46 PM PST 24 |
| Finished | Jan 10 01:16:50 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-32f60133-e406-454d-9ec0-c093e889857d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351348850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1351348850 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.4246293622 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 193925879923 ps |
| CPU time | 267.25 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:14:29 PM PST 24 |
| Peak memory | 182848 kb |
| Host | smart-b5a99584-6b4c-4c20-90ae-d42d1f5cb674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246293622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4246293622 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.3358499674 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 550911313992 ps |
| CPU time | 1155.14 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:29:24 PM PST 24 |
| Peak memory | 191056 kb |
| Host | smart-0b8a4689-87d0-4cbc-bea2-d8d0c1fdc20f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358499674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3358499674 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.4287106212 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 258463476889 ps |
| CPU time | 277.59 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:14:47 PM PST 24 |
| Peak memory | 191228 kb |
| Host | smart-38cf3208-87f3-438b-88ff-fdb9cf2a8730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287106212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.4287106212 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.347460286 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 111530495235 ps |
| CPU time | 174.79 seconds |
| Started | Jan 10 01:08:45 PM PST 24 |
| Finished | Jan 10 01:12:50 PM PST 24 |
| Peak memory | 183084 kb |
| Host | smart-a3f341cb-35f1-4f46-948b-f2fda96eba2a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347460286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all. 347460286 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1461940554 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 597578003104 ps |
| CPU time | 1891.54 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:41:38 PM PST 24 |
| Peak memory | 209992 kb |
| Host | smart-f19d90f5-d4c1-40c1-8750-56c160a06d81 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461940554 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1461940554 |
| Directory | /workspace/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.1783770885 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 111195672063 ps |
| CPU time | 162.45 seconds |
| Started | Jan 10 01:09:01 PM PST 24 |
| Finished | Jan 10 01:12:57 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-d5b7b7a8-7973-48bf-98f7-fc464ae99004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783770885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1783770885 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.2768285970 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 303132701117 ps |
| CPU time | 215.8 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 191012 kb |
| Host | smart-e89bd957-29e3-497e-b9fb-2d51af45f8d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768285970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2768285970 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.361668091 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 92749255537 ps |
| CPU time | 97.53 seconds |
| Started | Jan 10 01:09:24 PM PST 24 |
| Finished | Jan 10 01:12:06 PM PST 24 |
| Peak memory | 194812 kb |
| Host | smart-5f21f09c-a403-4a47-8ea2-90ae4fa80c3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361668091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.361668091 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.2794956294 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2054906532875 ps |
| CPU time | 1369.59 seconds |
| Started | Jan 10 01:08:53 PM PST 24 |
| Finished | Jan 10 01:32:52 PM PST 24 |
| Peak memory | 191292 kb |
| Host | smart-33fc4b85-c1dc-440a-a7a9-62dc66ebe907 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794956294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .2794956294 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3841398743 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 20117922746 ps |
| CPU time | 195.44 seconds |
| Started | Jan 10 01:09:16 PM PST 24 |
| Finished | Jan 10 01:13:41 PM PST 24 |
| Peak memory | 196336 kb |
| Host | smart-57aa0962-68ec-4742-9066-97dc6c51786e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841398743 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3841398743 |
| Directory | /workspace/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1651293798 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 174958152785 ps |
| CPU time | 271.12 seconds |
| Started | Jan 10 01:08:55 PM PST 24 |
| Finished | Jan 10 01:14:43 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-1b1b0ac2-3fa5-4149-b5ac-53e2ea4e2031 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651293798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.1651293798 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.4000949792 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 104778014213 ps |
| CPU time | 82.66 seconds |
| Started | Jan 10 01:09:01 PM PST 24 |
| Finished | Jan 10 01:11:31 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-596f3da4-08b4-4d19-a36d-9836d9a35124 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000949792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4000949792 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.2236654799 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 63992904410 ps |
| CPU time | 134.55 seconds |
| Started | Jan 10 01:08:47 PM PST 24 |
| Finished | Jan 10 01:12:20 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-bec4f77e-7723-4397-8fe9-60549c9f1839 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236654799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2236654799 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.2838615683 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 129625134745 ps |
| CPU time | 112.73 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:12:12 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-8ca64ce8-523a-42f1-9433-c36a59ef7a37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838615683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2838615683 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.3312765533 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 184636640829 ps |
| CPU time | 97.07 seconds |
| Started | Jan 10 01:08:54 PM PST 24 |
| Finished | Jan 10 01:11:42 PM PST 24 |
| Peak memory | 183020 kb |
| Host | smart-6c781038-9f76-4d3a-8ec9-50f4245bdedc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312765533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .3312765533 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3166424989 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 430107427799 ps |
| CPU time | 791.78 seconds |
| Started | Jan 10 01:09:05 PM PST 24 |
| Finished | Jan 10 01:23:25 PM PST 24 |
| Peak memory | 207232 kb |
| Host | smart-8861e886-ec89-43bd-8eb7-58755c1e2e0d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166424989 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3166424989 |
| Directory | /workspace/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2404169723 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 223059794239 ps |
| CPU time | 222.21 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:13:44 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-12f8589c-fea6-4585-a46c-6f499707e343 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404169723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.2404169723 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.1917315382 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 291056682556 ps |
| CPU time | 208.11 seconds |
| Started | Jan 10 01:09:01 PM PST 24 |
| Finished | Jan 10 01:13:37 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-c3bd0c52-87ba-4880-8b8b-224c5cc3de18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917315382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1917315382 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.1843140162 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 124033039113 ps |
| CPU time | 527.39 seconds |
| Started | Jan 10 01:08:50 PM PST 24 |
| Finished | Jan 10 01:18:48 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-54f5bdbd-df46-495a-8eca-f036d54a0956 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843140162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1843140162 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.3648655127 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 445365601 ps |
| CPU time | 0.82 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:10:07 PM PST 24 |
| Peak memory | 191056 kb |
| Host | smart-8cd27580-3092-4db7-b611-d2fcf74f4294 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648655127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3648655127 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.2137713823 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1356676280789 ps |
| CPU time | 456.32 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:17:36 PM PST 24 |
| Peak memory | 195164 kb |
| Host | smart-ec040558-9c0b-4000-88fb-2cdc12aabf50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137713823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .2137713823 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.845281085 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 199784186700 ps |
| CPU time | 455.03 seconds |
| Started | Jan 10 01:08:54 PM PST 24 |
| Finished | Jan 10 01:17:37 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-b98ad698-34c2-4648-86ab-8ace3e843166 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845281085 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.845281085 |
| Directory | /workspace/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3096035718 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 919957234006 ps |
| CPU time | 205.75 seconds |
| Started | Jan 10 01:08:57 PM PST 24 |
| Finished | Jan 10 01:13:31 PM PST 24 |
| Peak memory | 182856 kb |
| Host | smart-7d4223d2-7dac-4e53-b73e-268e5e8854c4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096035718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.3096035718 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.1316600859 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 999787943359 ps |
| CPU time | 194.23 seconds |
| Started | Jan 10 01:09:06 PM PST 24 |
| Finished | Jan 10 01:13:28 PM PST 24 |
| Peak memory | 182892 kb |
| Host | smart-7e8bde25-5dc4-4d57-9a9b-370625196aa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316600859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1316600859 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.1767861680 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 41613077274 ps |
| CPU time | 76.23 seconds |
| Started | Jan 10 01:10:23 PM PST 24 |
| Finished | Jan 10 01:12:56 PM PST 24 |
| Peak memory | 182284 kb |
| Host | smart-c04bed78-fd7e-422a-8c33-700a19f10612 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767861680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1767861680 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.2732311139 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 55364428195 ps |
| CPU time | 54.18 seconds |
| Started | Jan 10 01:09:16 PM PST 24 |
| Finished | Jan 10 01:11:33 PM PST 24 |
| Peak memory | 193752 kb |
| Host | smart-809b2112-038d-44bb-98f9-0034f3228a54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732311139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2732311139 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.3399699724 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 275793886187 ps |
| CPU time | 443.1 seconds |
| Started | Jan 10 01:08:47 PM PST 24 |
| Finished | Jan 10 01:17:21 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-81728b2a-4822-497a-9973-b31acadd831c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399699724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .3399699724 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.1805750287 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 179210121054 ps |
| CPU time | 1076.57 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:28:15 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-0745f9b6-abc0-457a-92e5-c0058ed025cf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805750287 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.1805750287 |
| Directory | /workspace/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1075053383 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 836525060996 ps |
| CPU time | 1371.19 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:32:52 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-ca38bbad-9e9e-403f-a6f6-c5df17757972 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075053383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.1075053383 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.2187536575 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 418625874310 ps |
| CPU time | 159.2 seconds |
| Started | Jan 10 01:08:55 PM PST 24 |
| Finished | Jan 10 01:12:47 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-bc8c063b-6dd6-47ea-8aa0-041e5320c9ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187536575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2187536575 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.934834529 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 62733754099 ps |
| CPU time | 307.42 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:15:16 PM PST 24 |
| Peak memory | 191324 kb |
| Host | smart-86b9a926-045a-4ced-b5d5-d3ff5184f4f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934834529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.934834529 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.1035474219 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 6787424425 ps |
| CPU time | 39.65 seconds |
| Started | Jan 10 01:08:55 PM PST 24 |
| Finished | Jan 10 01:10:43 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-ce085300-b468-4ec1-bbe9-612a3de59ef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035474219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1035474219 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.1575488090 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 971148926468 ps |
| CPU time | 307.72 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:15:10 PM PST 24 |
| Peak memory | 183016 kb |
| Host | smart-efbd0bad-bc4d-48d2-9529-b400ab443ceb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575488090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .1575488090 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1922444908 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 59289048428 ps |
| CPU time | 26.51 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:10:35 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-e99b72ed-c80e-4a5e-ba1d-fc7276320faa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922444908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.1922444908 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.355264544 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 241334640911 ps |
| CPU time | 97.96 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:13:06 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-d4922a44-89aa-47cb-a5f2-942daea53d33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355264544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.355264544 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.1120256107 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 38677398920 ps |
| CPU time | 33.99 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:10:43 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-17c3dbc4-2cc3-44c7-9aff-30afdde207f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120256107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1120256107 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.3974467946 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4274117536 ps |
| CPU time | 35.68 seconds |
| Started | Jan 10 01:08:56 PM PST 24 |
| Finished | Jan 10 01:10:39 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-7f22c33a-7acd-4027-bbd4-e22e77536451 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974467946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3974467946 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.155332098 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 104730155672 ps |
| CPU time | 457.1 seconds |
| Started | Jan 10 01:09:06 PM PST 24 |
| Finished | Jan 10 01:17:49 PM PST 24 |
| Peak memory | 197676 kb |
| Host | smart-4050bf23-4275-4a2f-a32d-2dbdb15958ba |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155332098 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.155332098 |
| Directory | /workspace/39.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.540556090 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 727636499823 ps |
| CPU time | 1052.72 seconds |
| Started | Jan 10 01:07:45 PM PST 24 |
| Finished | Jan 10 01:26:42 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-961ef629-0136-4553-976a-d8d23314f052 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540556090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .rv_timer_cfg_update_on_fly.540556090 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_disabled.1789491417 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 102104197222 ps |
| CPU time | 78.1 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:10:31 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-03fdde67-603e-41c6-bacb-b28a9258bd14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789491417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1789491417 |
| Directory | /workspace/4.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.3531977571 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 115772133977 ps |
| CPU time | 177.86 seconds |
| Started | Jan 10 01:07:37 PM PST 24 |
| Finished | Jan 10 01:12:00 PM PST 24 |
| Peak memory | 194716 kb |
| Host | smart-f055aeea-9ca7-4ac4-bd4b-fc0d9aec9751 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531977571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3531977571 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.1071799085 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 94675721152 ps |
| CPU time | 61.24 seconds |
| Started | Jan 10 01:07:45 PM PST 24 |
| Finished | Jan 10 01:10:11 PM PST 24 |
| Peak memory | 182804 kb |
| Host | smart-17ef3e96-6516-4414-b577-a0af3349d25d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071799085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1071799085 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.3862250040 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 153825675 ps |
| CPU time | 0.89 seconds |
| Started | Jan 10 01:07:49 PM PST 24 |
| Finished | Jan 10 01:09:15 PM PST 24 |
| Peak memory | 213864 kb |
| Host | smart-3988c652-b774-41ae-9647-1b623f88eb1e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862250040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3862250040 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1530131043 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 181429988537 ps |
| CPU time | 1940.85 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:41:20 PM PST 24 |
| Peak memory | 222956 kb |
| Host | smart-2c93a9fd-013c-4064-9566-8c638bb2ad06 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530131043 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1530131043 |
| Directory | /workspace/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2444731737 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 564188561835 ps |
| CPU time | 322.29 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:15:32 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-9642a567-601b-4c8b-9f4f-04c211c04a7d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444731737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.2444731737 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.3924940831 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 238220661031 ps |
| CPU time | 127.67 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:12:27 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-31243ee5-e6d5-40db-9293-fc62ef538869 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924940831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3924940831 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.2262046070 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 10309117157 ps |
| CPU time | 42.05 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:10:52 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-578b8397-aa62-479a-b261-92ae6693472f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262046070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2262046070 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.623980996 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 55187765 ps |
| CPU time | 0.76 seconds |
| Started | Jan 10 01:15:58 PM PST 24 |
| Finished | Jan 10 01:16:03 PM PST 24 |
| Peak memory | 182688 kb |
| Host | smart-b25527ee-f57a-455a-8d8b-d874506d7ffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623980996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.623980996 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.476360851 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1044696238933 ps |
| CPU time | 1010.4 seconds |
| Started | Jan 10 01:08:52 PM PST 24 |
| Finished | Jan 10 01:26:53 PM PST 24 |
| Peak memory | 191192 kb |
| Host | smart-f1573b5e-1f07-4c62-9f6a-9a623cc30660 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476360851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all. 476360851 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3336727441 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 93056797779 ps |
| CPU time | 345.28 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:15:51 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-5571352d-5b50-4df9-bfe5-df800520d0b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336727441 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3336727441 |
| Directory | /workspace/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.568316460 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 983410905759 ps |
| CPU time | 841.82 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:24:21 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-1e646ea8-8531-40e8-841f-05af1fb78c71 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568316460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.rv_timer_cfg_update_on_fly.568316460 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.1471572374 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 327144209028 ps |
| CPU time | 152.74 seconds |
| Started | Jan 10 01:09:18 PM PST 24 |
| Finished | Jan 10 01:12:57 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-fa7b5e27-fac2-4a11-a366-be5f343744dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471572374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1471572374 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.433914331 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 16789649980 ps |
| CPU time | 30.71 seconds |
| Started | Jan 10 01:08:53 PM PST 24 |
| Finished | Jan 10 01:10:36 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-fbe4fc79-8331-483f-be02-37816d88a8d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433914331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.433914331 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.3539533177 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 93650434 ps |
| CPU time | 0.68 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:10:06 PM PST 24 |
| Peak memory | 182380 kb |
| Host | smart-02272cec-de0c-4717-83f3-46b8f812937d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539533177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3539533177 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.352628672 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 462024076476 ps |
| CPU time | 316.38 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:15:31 PM PST 24 |
| Peak memory | 195364 kb |
| Host | smart-02573014-5c9a-4752-bd9c-a4fe2976679c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352628672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all. 352628672 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1710568986 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 240767163614 ps |
| CPU time | 1937.39 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:42:38 PM PST 24 |
| Peak memory | 220688 kb |
| Host | smart-609f66d4-527e-4993-a331-aa7753e190c4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710568986 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1710568986 |
| Directory | /workspace/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2099398915 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 583336767308 ps |
| CPU time | 601.48 seconds |
| Started | Jan 10 01:08:54 PM PST 24 |
| Finished | Jan 10 01:20:04 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-b2be00c8-952b-46e5-a900-1d4c7c42e928 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099398915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2099398915 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.2900107162 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 79355237678 ps |
| CPU time | 64.37 seconds |
| Started | Jan 10 01:08:53 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-191957d4-1b25-473f-bfcc-3cbe6d5f2f9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900107162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2900107162 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.1905888372 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 185439797089 ps |
| CPU time | 71.36 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:11:30 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-43b344bc-f0d5-4556-b9ed-f42464938cc5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905888372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1905888372 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.3470491884 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 108619668983 ps |
| CPU time | 43.37 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:10:43 PM PST 24 |
| Peak memory | 182828 kb |
| Host | smart-d014d4e9-4bad-4250-bf96-7541052478c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470491884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3470491884 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1466412835 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 140749822142 ps |
| CPU time | 832.96 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:24:19 PM PST 24 |
| Peak memory | 211236 kb |
| Host | smart-d4c6f173-359c-4c70-b0d2-ddb07b4ca3f9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466412835 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1466412835 |
| Directory | /workspace/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1615891579 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1498807827246 ps |
| CPU time | 326.57 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:15:45 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-45839e14-c299-4327-b638-ab58977465e9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615891579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.1615891579 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.2528071926 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 844979170517 ps |
| CPU time | 234.28 seconds |
| Started | Jan 10 01:09:05 PM PST 24 |
| Finished | Jan 10 01:14:06 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-3ef4034d-1c3a-4b2f-a25b-a7f796cba1b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528071926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2528071926 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.3184372244 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 23366175099 ps |
| CPU time | 11.01 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:10:27 PM PST 24 |
| Peak memory | 182860 kb |
| Host | smart-54f16909-91d6-4cd7-bafb-754d1d250128 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184372244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3184372244 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.2900963517 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1732179499010 ps |
| CPU time | 1299.34 seconds |
| Started | Jan 10 01:08:49 PM PST 24 |
| Finished | Jan 10 01:31:38 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-17e739c6-063f-4809-a1c8-7053ce578a40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900963517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .2900963517 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2147424095 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 61392342904 ps |
| CPU time | 288.98 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:14:50 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-e200980f-f2ba-4cb7-8f6d-7994d9cb49d4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147424095 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2147424095 |
| Directory | /workspace/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1656658715 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 223930408481 ps |
| CPU time | 221.65 seconds |
| Started | Jan 10 01:09:15 PM PST 24 |
| Finished | Jan 10 01:14:05 PM PST 24 |
| Peak memory | 183016 kb |
| Host | smart-ab36aa63-cfbe-4fc4-80c5-dfa1099ad402 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656658715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.1656658715 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.3698100408 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 195810373562 ps |
| CPU time | 84.32 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:11:35 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-095f0abf-6ffa-4025-a274-d3a8cb8dca45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698100408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3698100408 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.2591617302 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 49033486498 ps |
| CPU time | 29.01 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:10:28 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-0561eee7-b53b-48ed-9348-65f1322cf368 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591617302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2591617302 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.4197418648 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 115915513421 ps |
| CPU time | 63.44 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:11:13 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-299e90f2-bddc-445f-a36b-324230ce6bec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197418648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .4197418648 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1081288414 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 62610237723 ps |
| CPU time | 439.31 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:17:19 PM PST 24 |
| Peak memory | 197732 kb |
| Host | smart-d25679eb-cc30-436d-b7db-71fc72f28d4d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081288414 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1081288414 |
| Directory | /workspace/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1273789739 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 668469523944 ps |
| CPU time | 363.63 seconds |
| Started | Jan 10 01:10:00 PM PST 24 |
| Finished | Jan 10 01:17:11 PM PST 24 |
| Peak memory | 180592 kb |
| Host | smart-c3388028-f83a-4a6d-93fa-0b6958f0e504 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273789739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.1273789739 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.1621675023 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 29306993049 ps |
| CPU time | 25.63 seconds |
| Started | Jan 10 01:09:01 PM PST 24 |
| Finished | Jan 10 01:10:41 PM PST 24 |
| Peak memory | 182864 kb |
| Host | smart-e1a324d9-d1e8-4f18-9e82-d7683a7a8434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621675023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1621675023 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.2603083769 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 65425306283 ps |
| CPU time | 409.59 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:17:00 PM PST 24 |
| Peak memory | 193328 kb |
| Host | smart-70e963b5-3b3d-44fe-bcd6-ef64ab3eb26c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603083769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2603083769 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.3933604508 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 514932708228 ps |
| CPU time | 804.59 seconds |
| Started | Jan 10 01:09:09 PM PST 24 |
| Finished | Jan 10 01:23:50 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-cf709af4-08b8-4e0d-b949-19ec263acfec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933604508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all .3933604508 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1896521924 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 349803442403 ps |
| CPU time | 386.85 seconds |
| Started | Jan 10 01:08:48 PM PST 24 |
| Finished | Jan 10 01:16:25 PM PST 24 |
| Peak memory | 207580 kb |
| Host | smart-b776a7b8-2e1f-4380-b967-479a6f68b830 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896521924 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1896521924 |
| Directory | /workspace/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.2354393276 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 90358038865 ps |
| CPU time | 144.7 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:12:34 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-e49033f3-49d9-4689-8de5-df259571043f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354393276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2354393276 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.860190460 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 126772042953 ps |
| CPU time | 316.05 seconds |
| Started | Jan 10 01:09:05 PM PST 24 |
| Finished | Jan 10 01:15:29 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-0c449902-fedc-4c61-a7a9-2dd2713354af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860190460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.860190460 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.4209847060 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 275363535 ps |
| CPU time | 1.15 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:10:19 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-b0d5a5da-1318-405f-8d5f-3284b737cd30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209847060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4209847060 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.2177477635 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2487830263072 ps |
| CPU time | 1561.37 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:36:21 PM PST 24 |
| Peak memory | 194012 kb |
| Host | smart-00ed9526-565e-4a71-8250-f4fac1e1c432 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177477635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .2177477635 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2169708545 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 172337237415 ps |
| CPU time | 99.03 seconds |
| Started | Jan 10 01:09:09 PM PST 24 |
| Finished | Jan 10 01:12:04 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-5f2cd41d-6da9-4b70-af9f-166c28a499f5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169708545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2169708545 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.184020108 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 66445177234 ps |
| CPU time | 58.7 seconds |
| Started | Jan 10 01:08:59 PM PST 24 |
| Finished | Jan 10 01:11:04 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-41b1a04c-94f1-41d1-b868-8d4ec8f59176 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184020108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.184020108 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.381055441 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11675716014 ps |
| CPU time | 22.16 seconds |
| Started | Jan 10 01:09:09 PM PST 24 |
| Finished | Jan 10 01:10:47 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-40f0dccb-267f-4160-be7d-2f31e088b72a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381055441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.381055441 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.3513848176 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 32096255 ps |
| CPU time | 0.87 seconds |
| Started | Jan 10 01:09:04 PM PST 24 |
| Finished | Jan 10 01:10:18 PM PST 24 |
| Peak memory | 182652 kb |
| Host | smart-054439a5-dc41-4b04-a3fd-3080f87420e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513848176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3513848176 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.3129897920 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 419775779810 ps |
| CPU time | 443.84 seconds |
| Started | Jan 10 01:09:12 PM PST 24 |
| Finished | Jan 10 01:17:47 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-0d0a2e56-79a3-4310-9bae-dfd374e49f35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129897920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .3129897920 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2112339760 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 123738011124 ps |
| CPU time | 722.53 seconds |
| Started | Jan 10 01:09:14 PM PST 24 |
| Finished | Jan 10 01:22:24 PM PST 24 |
| Peak memory | 208940 kb |
| Host | smart-86b54cd7-01d3-4a6e-92cf-df1779f71ae8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112339760 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.2112339760 |
| Directory | /workspace/47.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4249995916 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 232798036804 ps |
| CPU time | 225.67 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:14:18 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-068745fa-9a97-4df6-a8a5-5441eb848086 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249995916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.4249995916 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.1809278735 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 200431956992 ps |
| CPU time | 67.75 seconds |
| Started | Jan 10 01:08:59 PM PST 24 |
| Finished | Jan 10 01:11:15 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-9c511b88-9bdc-4cba-a768-13f59338ed4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809278735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1809278735 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.1277091544 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 828512975 ps |
| CPU time | 1.67 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:10:17 PM PST 24 |
| Peak memory | 182384 kb |
| Host | smart-d3f3f5c2-4df8-4b20-b208-76da6eb96b30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277091544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1277091544 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.130110883 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 709951854283 ps |
| CPU time | 310.9 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:15:30 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-da32802e-374e-452b-b063-ae81fd3b1cd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130110883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all. 130110883 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1552419758 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 480404197300 ps |
| CPU time | 2128.33 seconds |
| Started | Jan 10 01:09:05 PM PST 24 |
| Finished | Jan 10 01:45:41 PM PST 24 |
| Peak memory | 211132 kb |
| Host | smart-9dda06c4-a79a-4318-b535-90e58879db54 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552419758 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1552419758 |
| Directory | /workspace/48.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.391082645 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 95290351417 ps |
| CPU time | 54.28 seconds |
| Started | Jan 10 01:09:01 PM PST 24 |
| Finished | Jan 10 01:11:03 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-ad323371-be9e-4c99-b32f-844195174078 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391082645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.rv_timer_cfg_update_on_fly.391082645 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.2833543857 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 359204763261 ps |
| CPU time | 304.35 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:15:25 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-e4cbf8fa-2b1f-4431-8414-cf2e3cb348f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833543857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2833543857 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.886401088 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 18453328219 ps |
| CPU time | 17.65 seconds |
| Started | Jan 10 01:09:04 PM PST 24 |
| Finished | Jan 10 01:10:29 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-a46a3073-5cf7-4420-af9d-c6abe7c8d631 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886401088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.886401088 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.2278269427 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5481055550 ps |
| CPU time | 6.3 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:10:26 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-f3ba6551-f5d7-4f54-bc01-ad91c4442929 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278269427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2278269427 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2179808375 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 454801515402 ps |
| CPU time | 1859.44 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:41:15 PM PST 24 |
| Peak memory | 213404 kb |
| Host | smart-5de87cd8-df6b-40dc-a8d6-85aab1499e80 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179808375 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2179808375 |
| Directory | /workspace/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.997342326 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 649431772423 ps |
| CPU time | 1008.98 seconds |
| Started | Jan 10 01:07:56 PM PST 24 |
| Finished | Jan 10 01:26:08 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-fd5138b8-3e2c-4905-9cd4-31fc94930f67 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997342326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .rv_timer_cfg_update_on_fly.997342326 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.1306288027 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 124915280341 ps |
| CPU time | 188.88 seconds |
| Started | Jan 10 01:07:47 PM PST 24 |
| Finished | Jan 10 01:12:17 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-46970cd7-8bc9-4671-b8b8-342dab28b09c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306288027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1306288027 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.2020828335 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 104648924377 ps |
| CPU time | 167.83 seconds |
| Started | Jan 10 01:08:01 PM PST 24 |
| Finished | Jan 10 01:12:12 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-987db8f0-1f4a-43b7-a8fa-8fc66def816e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020828335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2020828335 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.1389179716 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 11261973244 ps |
| CPU time | 17.45 seconds |
| Started | Jan 10 01:07:51 PM PST 24 |
| Finished | Jan 10 01:09:34 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-f33aad21-db93-4c34-9f3e-c20914152f0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389179716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1389179716 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.1972208828 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1872242477283 ps |
| CPU time | 966.45 seconds |
| Started | Jan 10 01:08:51 PM PST 24 |
| Finished | Jan 10 01:26:06 PM PST 24 |
| Peak memory | 190656 kb |
| Host | smart-84a60329-fa34-4219-a22a-396fc1fe5676 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972208828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 1972208828 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.4151051904 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 47173301281 ps |
| CPU time | 514.57 seconds |
| Started | Jan 10 01:07:34 PM PST 24 |
| Finished | Jan 10 01:17:33 PM PST 24 |
| Peak memory | 197680 kb |
| Host | smart-94394f53-2e74-4a80-b43e-08ac7dbe07b5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151051904 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.4151051904 |
| Directory | /workspace/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.644615142 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 107755658460 ps |
| CPU time | 394.14 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:16:40 PM PST 24 |
| Peak memory | 191024 kb |
| Host | smart-861afb5a-290f-4665-afb7-2acd84610b5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644615142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.644615142 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.1308190043 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 473309946778 ps |
| CPU time | 410.9 seconds |
| Started | Jan 10 01:10:22 PM PST 24 |
| Finished | Jan 10 01:18:29 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-e69cae14-b9f0-4537-b6ae-4fe0c16e1055 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308190043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1308190043 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.2064607163 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 102130831904 ps |
| CPU time | 179.9 seconds |
| Started | Jan 10 01:09:01 PM PST 24 |
| Finished | Jan 10 01:13:15 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-5c50a58d-c82b-43ec-8e55-3584c1271454 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064607163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2064607163 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.1523108900 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 70981568724 ps |
| CPU time | 99.23 seconds |
| Started | Jan 10 01:09:31 PM PST 24 |
| Finished | Jan 10 01:12:16 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-0f74af5c-4b59-405f-9861-030f7d0e4980 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523108900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1523108900 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.3637091714 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 131801220475 ps |
| CPU time | 113.06 seconds |
| Started | Jan 10 01:09:06 PM PST 24 |
| Finished | Jan 10 01:12:06 PM PST 24 |
| Peak memory | 191224 kb |
| Host | smart-d3f67099-30f4-4ec7-98a8-6f543f8475c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637091714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3637091714 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.3575822870 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 109121041590 ps |
| CPU time | 347.35 seconds |
| Started | Jan 10 01:09:02 PM PST 24 |
| Finished | Jan 10 01:15:55 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-89ee3bc6-a522-46d5-85f2-f28701d64391 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575822870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3575822870 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.3628897107 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 343692279734 ps |
| CPU time | 313.35 seconds |
| Started | Jan 10 01:09:18 PM PST 24 |
| Finished | Jan 10 01:15:37 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-e22392dc-7779-434f-b1bf-7da840b5e4b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628897107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3628897107 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.1672728992 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 117297263352 ps |
| CPU time | 439.67 seconds |
| Started | Jan 10 01:09:29 PM PST 24 |
| Finished | Jan 10 01:17:53 PM PST 24 |
| Peak memory | 193504 kb |
| Host | smart-43c11035-40cf-434c-a5d5-ba6941be7088 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672728992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1672728992 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3826144635 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1114384276848 ps |
| CPU time | 578.53 seconds |
| Started | Jan 10 01:07:43 PM PST 24 |
| Finished | Jan 10 01:18:46 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-0a778ba0-13b2-4760-823c-c20bef9bb380 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826144635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3826144635 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.3998078440 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 484832697871 ps |
| CPU time | 219.02 seconds |
| Started | Jan 10 01:07:50 PM PST 24 |
| Finished | Jan 10 01:12:50 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-55c4e413-e38d-499f-b17b-b81b54b67f56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998078440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3998078440 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.1613221354 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 153676205500 ps |
| CPU time | 262.6 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:13:26 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-c85b76be-e2c4-4dbd-85a4-370b4d980240 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613221354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1613221354 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.298633634 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1873423137669 ps |
| CPU time | 849.3 seconds |
| Started | Jan 10 01:07:44 PM PST 24 |
| Finished | Jan 10 01:23:15 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-9f107282-9be1-4e97-847b-9ac380d56c70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298633634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.298633634 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3975241775 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 445249615837 ps |
| CPU time | 186.8 seconds |
| Started | Jan 10 01:07:50 PM PST 24 |
| Finished | Jan 10 01:12:18 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-3da0b439-2bb0-49c2-93ce-2fa474fb4f99 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975241775 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3975241775 |
| Directory | /workspace/6.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.3460572755 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 110100707484 ps |
| CPU time | 95.99 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:11:54 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-abd7eec8-ab58-4901-835c-add6388dd813 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460572755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3460572755 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/61.rv_timer_random.676931451 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 53845548020 ps |
| CPU time | 94 seconds |
| Started | Jan 10 01:09:15 PM PST 24 |
| Finished | Jan 10 01:11:56 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-9625c3bd-f742-47cc-a1f5-6d060cbafdbf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676931451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.676931451 |
| Directory | /workspace/61.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.2400470301 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 212767250909 ps |
| CPU time | 208.48 seconds |
| Started | Jan 10 01:10:15 PM PST 24 |
| Finished | Jan 10 01:14:56 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-39090130-d208-44ad-903d-464bd90c42db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400470301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2400470301 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.497977374 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 23421046108 ps |
| CPU time | 168.52 seconds |
| Started | Jan 10 01:08:58 PM PST 24 |
| Finished | Jan 10 01:12:56 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-64c5a9da-6847-4515-acd1-cab0670aaacb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497977374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.497977374 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.1967591697 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 142070271822 ps |
| CPU time | 111.48 seconds |
| Started | Jan 10 01:09:15 PM PST 24 |
| Finished | Jan 10 01:12:14 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-a2d2e82d-b618-4ada-95d7-0c6624dc2524 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967591697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1967591697 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.2587216704 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 447186967577 ps |
| CPU time | 508.91 seconds |
| Started | Jan 10 01:09:11 PM PST 24 |
| Finished | Jan 10 01:18:48 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-d0d1ba95-5e7c-43d4-858c-5f1da78ffa20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587216704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2587216704 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.226294536 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 73496393054 ps |
| CPU time | 327.19 seconds |
| Started | Jan 10 01:09:42 PM PST 24 |
| Finished | Jan 10 01:16:15 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-b4c98980-e51e-4475-95f5-3f8dc3172a6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226294536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.226294536 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.3865570558 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 187199363954 ps |
| CPU time | 188.52 seconds |
| Started | Jan 10 01:09:06 PM PST 24 |
| Finished | Jan 10 01:13:22 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-4d287b16-a648-44ca-a51a-697451dda23b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865570558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3865570558 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.1390461580 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 59613286857 ps |
| CPU time | 298.9 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:15:08 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-ff4d5146-01c0-47d9-9b28-a8d779e7ed96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390461580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1390461580 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1773213850 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 63933493465 ps |
| CPU time | 109.62 seconds |
| Started | Jan 10 01:07:43 PM PST 24 |
| Finished | Jan 10 01:10:57 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-5cb2cd4d-c618-4f30-9a7f-578ebb8d68f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773213850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.1773213850 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.3351620570 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 107640033993 ps |
| CPU time | 147.73 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:11:31 PM PST 24 |
| Peak memory | 182752 kb |
| Host | smart-a9a10520-fe04-4b7c-9539-186b64dab5ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351620570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3351620570 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.1494332938 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 536216478477 ps |
| CPU time | 606.6 seconds |
| Started | Jan 10 01:07:48 PM PST 24 |
| Finished | Jan 10 01:19:16 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-c837cadf-1643-47cd-9d00-8fc6bde904cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494332938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1494332938 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.2520836984 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 287429777827 ps |
| CPU time | 408.75 seconds |
| Started | Jan 10 01:07:52 PM PST 24 |
| Finished | Jan 10 01:16:03 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-9936d46b-809b-4a82-9d3d-b13f21b137c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520836984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2520836984 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3452563400 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 100984994364 ps |
| CPU time | 277 seconds |
| Started | Jan 10 01:07:34 PM PST 24 |
| Finished | Jan 10 01:13:36 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-a139fb88-8daf-425e-ba49-0c51068950b8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452563400 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3452563400 |
| Directory | /workspace/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.3246120937 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 768620936582 ps |
| CPU time | 655.03 seconds |
| Started | Jan 10 01:09:19 PM PST 24 |
| Finished | Jan 10 01:21:20 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-c569fb6f-c003-49ce-b30f-505fb930b4ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246120937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3246120937 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.180488236 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1273891510672 ps |
| CPU time | 818.92 seconds |
| Started | Jan 10 01:09:08 PM PST 24 |
| Finished | Jan 10 01:23:55 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-9d2ca405-b6c7-40ac-8141-8660753d8a3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180488236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.180488236 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.2940392 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 131280312713 ps |
| CPU time | 652.87 seconds |
| Started | Jan 10 01:09:10 PM PST 24 |
| Finished | Jan 10 01:21:13 PM PST 24 |
| Peak memory | 191248 kb |
| Host | smart-10e23ee8-d09a-4dd0-8bd5-e663502d0672 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2940392 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.4193524146 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 69968823197 ps |
| CPU time | 41.28 seconds |
| Started | Jan 10 01:09:05 PM PST 24 |
| Finished | Jan 10 01:10:52 PM PST 24 |
| Peak memory | 183048 kb |
| Host | smart-ad237f88-c589-42f3-a7bf-422b8f3779e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193524146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4193524146 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.1402343973 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 23718834695 ps |
| CPU time | 39.98 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:10:49 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-aa918fd0-eec2-4ec5-8096-2c83048fb607 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402343973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1402343973 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.608850284 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1321934123707 ps |
| CPU time | 404.17 seconds |
| Started | Jan 10 01:07:55 PM PST 24 |
| Finished | Jan 10 01:16:03 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-b89fb827-1ce6-4d76-a55b-03184f93f619 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608850284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .rv_timer_cfg_update_on_fly.608850284 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.3599598139 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 158495970812 ps |
| CPU time | 219.97 seconds |
| Started | Jan 10 01:07:54 PM PST 24 |
| Finished | Jan 10 01:12:59 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-4102d54d-7bbf-4e89-b83b-2d2f1569bfe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599598139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3599598139 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.3255422967 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 55491771013 ps |
| CPU time | 101.89 seconds |
| Started | Jan 10 01:07:42 PM PST 24 |
| Finished | Jan 10 01:10:50 PM PST 24 |
| Peak memory | 193772 kb |
| Host | smart-d9efe7a9-685f-430c-a541-bc3d6cf9e0c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255422967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3255422967 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.2995895525 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2972780568 ps |
| CPU time | 4.74 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:09:04 PM PST 24 |
| Peak memory | 194004 kb |
| Host | smart-ccd6c9d4-da3e-4a24-9884-1caccf1595ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995895525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2995895525 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3554745540 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 54312245968 ps |
| CPU time | 116.44 seconds |
| Started | Jan 10 01:07:39 PM PST 24 |
| Finished | Jan 10 01:11:01 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-05bffede-c36e-4c5b-8ef5-dc497458c3d0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554745540 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3554745540 |
| Directory | /workspace/8.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.3268764701 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 502605361456 ps |
| CPU time | 262.23 seconds |
| Started | Jan 10 01:09:03 PM PST 24 |
| Finished | Jan 10 01:14:33 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-89075a5c-6808-47d8-b972-59009839d3f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268764701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3268764701 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.370429657 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 71956722937 ps |
| CPU time | 126.06 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:12:33 PM PST 24 |
| Peak memory | 191020 kb |
| Host | smart-bf16e408-6782-43e0-a56c-d232ee5b077a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370429657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.370429657 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.816355605 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 70863443282 ps |
| CPU time | 52.76 seconds |
| Started | Jan 10 01:09:06 PM PST 24 |
| Finished | Jan 10 01:11:06 PM PST 24 |
| Peak memory | 183036 kb |
| Host | smart-90b65107-7abd-4a1d-8d4d-ceffdaffddd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816355605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.816355605 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.1833923419 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 31533661694 ps |
| CPU time | 19.13 seconds |
| Started | Jan 10 01:09:00 PM PST 24 |
| Finished | Jan 10 01:10:29 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-c20d0c98-a2ba-4956-8b95-53666d96c00e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833923419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1833923419 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.1682822629 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3793630775711 ps |
| CPU time | 1053.51 seconds |
| Started | Jan 10 01:09:18 PM PST 24 |
| Finished | Jan 10 01:27:57 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-247343b0-5701-4d6e-8c96-2a878322ed52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682822629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1682822629 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.2335493229 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 48729034698 ps |
| CPU time | 177.26 seconds |
| Started | Jan 10 01:09:16 PM PST 24 |
| Finished | Jan 10 01:13:22 PM PST 24 |
| Peak memory | 194356 kb |
| Host | smart-d1984a1c-94ef-4b43-ba6e-5a71552f17f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335493229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2335493229 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.1713210985 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 117157854531 ps |
| CPU time | 298.15 seconds |
| Started | Jan 10 01:09:09 PM PST 24 |
| Finished | Jan 10 01:15:15 PM PST 24 |
| Peak memory | 191040 kb |
| Host | smart-839fa57b-9021-43cb-b63e-3c7c261925e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713210985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1713210985 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.2983781824 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 619924253153 ps |
| CPU time | 2206.12 seconds |
| Started | Jan 10 01:09:31 PM PST 24 |
| Finished | Jan 10 01:47:22 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-7d5fd556-3f3c-4c3b-a1a2-ff8316c476b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983781824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2983781824 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.3534702043 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 204793993412 ps |
| CPU time | 575.44 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:20:03 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-2c224464-9ff5-4d57-8806-f68a35dc6e40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534702043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3534702043 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2893288405 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1556390943311 ps |
| CPU time | 888.72 seconds |
| Started | Jan 10 01:07:40 PM PST 24 |
| Finished | Jan 10 01:23:54 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-62657a7e-8f20-4018-bce8-7807ca5e505a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893288405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.2893288405 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.2609533123 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 783483168558 ps |
| CPU time | 332.75 seconds |
| Started | Jan 10 01:08:05 PM PST 24 |
| Finished | Jan 10 01:15:00 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-cd034931-6fb5-4d69-84b8-292ab66a7239 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609533123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2609533123 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.1374723612 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 190054807558 ps |
| CPU time | 345.85 seconds |
| Started | Jan 10 01:07:46 PM PST 24 |
| Finished | Jan 10 01:14:56 PM PST 24 |
| Peak memory | 191224 kb |
| Host | smart-e0526be7-dd23-49ca-ac37-a3af62b026f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374723612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1374723612 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.333747681 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 38238397472 ps |
| CPU time | 63.42 seconds |
| Started | Jan 10 01:07:44 PM PST 24 |
| Finished | Jan 10 01:10:09 PM PST 24 |
| Peak memory | 190956 kb |
| Host | smart-8c46bcc2-3d5b-43b8-968d-ab2d1ace640c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333747681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.333747681 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1612395914 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 39306089784 ps |
| CPU time | 333.75 seconds |
| Started | Jan 10 01:08:00 PM PST 24 |
| Finished | Jan 10 01:14:58 PM PST 24 |
| Peak memory | 205848 kb |
| Host | smart-efccbfe1-08a5-41af-8905-fcc2c130ca0d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612395914 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1612395914 |
| Directory | /workspace/9.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.2487761321 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 29509069857 ps |
| CPU time | 54.46 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:11:22 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-6442af51-9723-4d92-9791-4a19fc2e40c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487761321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2487761321 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.787889175 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1340376844694 ps |
| CPU time | 423.69 seconds |
| Started | Jan 10 01:09:38 PM PST 24 |
| Finished | Jan 10 01:17:47 PM PST 24 |
| Peak memory | 193888 kb |
| Host | smart-5832ed92-8788-4937-bca5-24fae6ff3f6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787889175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.787889175 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.2700344113 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 353274723041 ps |
| CPU time | 126.99 seconds |
| Started | Jan 10 01:09:21 PM PST 24 |
| Finished | Jan 10 01:12:33 PM PST 24 |
| Peak memory | 193028 kb |
| Host | smart-4719f697-59d5-43cd-84b0-c40cd361cfa2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700344113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2700344113 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.3735440521 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 50872845493 ps |
| CPU time | 77.93 seconds |
| Started | Jan 10 01:09:22 PM PST 24 |
| Finished | Jan 10 01:11:45 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-a66cf134-1f1f-4235-99e4-299723ac127b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735440521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3735440521 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.826050148 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 38144546709 ps |
| CPU time | 63.69 seconds |
| Started | Jan 10 01:09:59 PM PST 24 |
| Finished | Jan 10 01:12:10 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-584d9e90-ff00-4850-ab97-60c70169def0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826050148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.826050148 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.1437414445 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 45616163909 ps |
| CPU time | 81.01 seconds |
| Started | Jan 10 01:09:23 PM PST 24 |
| Finished | Jan 10 01:11:55 PM PST 24 |
| Peak memory | 190940 kb |
| Host | smart-8feb0191-504b-471d-b53f-2d4b820550a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437414445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1437414445 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.3172190375 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 528633318015 ps |
| CPU time | 156.16 seconds |
| Started | Jan 10 01:09:20 PM PST 24 |
| Finished | Jan 10 01:13:03 PM PST 24 |
| Peak memory | 194252 kb |
| Host | smart-52baaa27-acc2-483c-b656-4ba55e074419 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172190375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3172190375 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.574802950 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 277446472876 ps |
| CPU time | 241.45 seconds |
| Started | Jan 10 01:09:25 PM PST 24 |
| Finished | Jan 10 01:14:32 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-f7d2bf4c-77c6-4e80-b50f-842498453d7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574802950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.574802950 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.911572443 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 158835605814 ps |
| CPU time | 78.65 seconds |
| Started | Jan 10 01:09:27 PM PST 24 |
| Finished | Jan 10 01:11:50 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-67e3365a-5a72-4ddb-a634-d50c9df3fb31 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911572443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.911572443 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.3491119671 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 680008345663 ps |
| CPU time | 568.84 seconds |
| Started | Jan 10 01:09:26 PM PST 24 |
| Finished | Jan 10 01:20:02 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-4f0f5162-2afa-41f1-8c3b-3f2a6ff0d70e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491119671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3491119671 |
| Directory | /workspace/99.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |